gcc/config/v850/v850.md

   1 ;; GCC machine description for NEC V850
   2 ;; Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   3 ;; Contributed by Jeff Law (law@cygnus.com).
   4
   5 ;; This file is part of GNU CC.
   6
   7 ;; GNU CC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11
  12 ;; GNU CC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GNU CC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  20 ;; Boston, MA 02111-1307, USA.
  21
  22 ;; The original PO technology requires these to be ordered by speed,
  23 ;; so that assigner will pick the fastest.
  24
  25 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
  26
  27 ;; The V851 manual states that the instruction address space is 16M;
  28 ;; the various branch/call instructions only have a 22bit offset (4M range).
  29 ;;
  30 ;; One day we'll probably need to handle calls to targets more than 4M
  31 ;; away.
  32
  33 ;; The size of instructions in bytes.
  34
  35 (define_attr "length" ""
  36   (const_int 200))
  37
  38 (define_attr "long_calls" "yes,no"
  39   (const (if_then_else (symbol_ref "TARGET_LONG_CALLS")
  40                        (const_string "yes")
  41                        (const_string "no"))))
  42
  43 ;; Types of instructions (for scheduling purposes).
  44
  45 (define_attr "type" "load,mult,other"
  46   (const_string "other"))
  47
  48 ;; Condition code settings.
  49 ;; none - insn does not affect cc
  50 ;; none_0hit - insn does not affect cc but it does modify operand 0
  51 ;;      This attribute is used to keep track of when operand 0 changes.
  52 ;;      See the description of NOTICE_UPDATE_CC for more info.
  53 ;; set_znv - sets z,n,v to usable values; c is unknown.
  54 ;; set_zn  - sets z,n to usable values; v,c is unknown.
  55 ;; compare - compare instruction
  56 ;; clobber - value of cc is unknown
  57 (define_attr "cc" "none,none_0hit,set_zn,set_znv,compare,clobber"
  58   (const_string "clobber"))
  59 \f
  60 ;; Function units for the V850.  As best as I can tell, there's
  61 ;; a traditional memory load/use stall as well as a stall if
  62 ;; the result of a multiply is used too early.
  63 ;;
  64 (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
  65 (define_function_unit "mult"   1 0 (eq_attr "type" "mult") 2 0)
  66
  67 \f
  68 ;; ----------------------------------------------------------------------
  69 ;; MOVE INSTRUCTIONS
  70 ;; ----------------------------------------------------------------------
  71
  72 ;; movqi
  73
  74 (define_expand "movqi"
  75   [(set (match_operand:QI 0 "general_operand" "")
  76         (match_operand:QI 1 "general_operand" ""))]
  77   ""
  78   "
  79 {
  80   /* One of the ops has to be in a register or 0 */
  81   if (!register_operand (operand0, QImode)
  82       && !reg_or_0_operand (operand1, QImode))
  83     operands[1] = copy_to_mode_reg (QImode, operand1);
  84 }")
  85
  86 (define_insn "*movqi_internal"
  87   [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m")
  88         (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
  89   "register_operand (operands[0], QImode)
  90    || reg_or_0_operand (operands[1], QImode)"
  91   "* return output_move_single (operands);"
  92   [(set_attr "length" "2,4,2,2,4,4,4")
  93    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
  94    (set_attr "type" "other,other,load,other,load,other,other")])
  95
  96 ;; movhi
  97
  98 (define_expand "movhi"
  99   [(set (match_operand:HI 0 "general_operand" "")
 100         (match_operand:HI 1 "general_operand" ""))]
 101   ""
 102   "
 103 {
 104   /* One of the ops has to be in a register or 0 */
 105   if (!register_operand (operand0, HImode)
 106       && !reg_or_0_operand (operand1, HImode))
 107     operands[1] = copy_to_mode_reg (HImode, operand1);
 108 }")
 109
 110 (define_insn "*movhi_internal"
 111   [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m")
 112         (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
 113   "register_operand (operands[0], HImode)
 114    || reg_or_0_operand (operands[1], HImode)"
 115   "* return output_move_single (operands);"
 116   [(set_attr "length" "2,4,2,2,4,4,4")
 117    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 118    (set_attr "type" "other,other,load,other,load,other,other")])
 119
 120 ;; movsi and helpers
 121
 122 (define_insn "*movsi_high"
 123   [(set (match_operand:SI 0 "register_operand" "=r")
 124         (high:SI (match_operand 1 "" "")))]
 125   ""
 126   "movhi hi(%1),%.,%0"
 127   [(set_attr "length" "4")
 128    (set_attr "cc" "none_0hit")
 129    (set_attr "type" "other")])
 130
 131 (define_insn "*movsi_lo"
 132   [(set (match_operand:SI 0 "register_operand" "=r")
 133         (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 134                    (match_operand:SI 2 "immediate_operand" "i")))]
 135   ""
 136   "movea lo(%2),%1,%0"
 137   [(set_attr "length" "4")
 138    (set_attr "cc" "none_0hit")
 139    (set_attr "type" "other")])
 140
 141 (define_expand "movsi"
 142   [(set (match_operand:SI 0 "general_operand" "")
 143         (match_operand:SI 1 "general_operand" ""))]
 144   ""
 145   "
 146 {
 147   /* One of the ops has to be in a register or 0 */
 148   if (!register_operand (operand0, SImode)
 149       && !reg_or_0_operand (operand1, SImode))
 150     operands[1] = copy_to_mode_reg (SImode, operand1);
 151
 152   /* Some constants, as well as symbolic operands
 153      must be done with HIGH & LO_SUM patterns.  */
 154   if (CONSTANT_P (operands[1])
 155       && GET_CODE (operands[1]) != HIGH
 156       && !special_symbolref_operand (operands[1], VOIDmode)
 157       && !(GET_CODE (operands[1]) == CONST_INT
 158            && (CONST_OK_FOR_J (INTVAL (operands[1]))
 159                || CONST_OK_FOR_K (INTVAL (operands[1]))
 160                || CONST_OK_FOR_L (INTVAL (operands[1])))))
 161     {
 162       rtx high;
 163       rtx temp;
 164
 165       if (reload_in_progress || reload_completed)
 166         temp = operands[0];
 167       else
 168         temp = gen_reg_rtx (SImode);
 169
 170       emit_insn (gen_rtx_SET (SImode, temp,
 171                               gen_rtx_HIGH (SImode, operand1)));
 172       emit_insn (gen_rtx_SET (SImode, operand0,
 173                               gen_rtx_LO_SUM (SImode, temp, operand1)));
 174       DONE;
 175     }
 176 }")
 177
 178 (define_insn "*movsi_internal"
 179   [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m")
 180         (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
 181   "register_operand (operands[0], SImode)
 182    || reg_or_0_operand (operands[1], SImode)"
 183   "* return output_move_single (operands);"
 184   [(set_attr "length" "2,4,4,2,2,4,4,4,4")
 185    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 186    (set_attr "type" "other,other,other,load,other,load,other,other,other")])
 187
 188
 189
 190 (define_expand "movdi"
 191   [(set (match_operand:DI 0 "general_operand" "")
 192         (match_operand:DI 1 "general_operand" ""))]
 193   ""
 194   "
 195 {
 196   /* One of the ops has to be in a register or 0 */
 197   if (!register_operand (operand0, DImode)
 198       && !reg_or_0_operand (operand1, DImode))
 199     operands[1] = copy_to_mode_reg (DImode, operand1);
 200 }")
 201
 202 (define_insn "*movdi_internal"
 203   [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,m,r")
 204         (match_operand:DI 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
 205   "register_operand (operands[0], DImode)
 206    || reg_or_0_operand (operands[1], DImode)"
 207   "* return output_move_double (operands);"
 208   [(set_attr "length" "4,8,8,16,8,8,8,16")
 209    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 210    (set_attr "type" "other,other,other,other,load,other,other,other")])
 211
 212 (define_expand "movsf"
 213   [(set (match_operand:SF 0 "general_operand" "")
 214         (match_operand:SF 1 "general_operand" ""))]
 215   ""
 216   "
 217 {
 218   /* One of the ops has to be in a register or 0 */
 219   if (!register_operand (operand0, SFmode)
 220       && !reg_or_0_operand (operand1, SFmode))
 221     operands[1] = copy_to_mode_reg (SFmode, operand1);
 222 }")
 223
 224 (define_insn "*movsf_internal"
 225   [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r")
 226         (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
 227   "register_operand (operands[0], SFmode)
 228    || reg_or_0_operand (operands[1], SFmode)"
 229   "* return output_move_single (operands);"
 230   [(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
 231    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 232    (set_attr "type" "other,other,other,other,load,other,load,other,other,other")])
 233
 234 (define_expand "movdf"
 235   [(set (match_operand:DF 0 "general_operand" "")
 236         (match_operand:DF 1 "general_operand" ""))]
 237   ""
 238   "
 239 {
 240   /* One of the ops has to be in a register or 0 */
 241   if (!register_operand (operand0, DFmode)
 242       && !reg_or_0_operand (operand1, DFmode))
 243     operands[1] = copy_to_mode_reg (DFmode, operand1);
 244 }")
 245
 246 (define_insn "*movdf_internal"
 247   [(set (match_operand:DF 0 "general_operand" "=r,r,r,r,r,m,m,r")
 248         (match_operand:DF 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
 249   "register_operand (operands[0], DFmode)
 250    || reg_or_0_operand (operands[1], DFmode)"
 251   "* return output_move_double (operands);"
 252   [(set_attr "length" "4,8,8,16,8,8,8,16")
 253    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 254    (set_attr "type" "other,other,other,other,load,other,other,other")])
 255
 256 \f
 257 ;; ----------------------------------------------------------------------
 258 ;; TEST INSTRUCTIONS
 259 ;; ----------------------------------------------------------------------
 260
 261 (define_insn "*v850_tst1"
 262   [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
 263                                (const_int 1)
 264                                (match_operand:QI 1 "const_int_operand" "n")))]
 265   ""
 266   "tst1 %1,%0"
 267   [(set_attr "length" "4")
 268    (set_attr "cc" "clobber")])
 269
 270 ;; This replaces ld.b;sar;andi with tst1;setf nz.
 271
 272 ;; ??? The zero_extract sets the Z bit to the opposite of what one would
 273 ;; expect.  This perhaps should be wrapped in a (eq: X (const_int 0)).
 274
 275 (define_split
 276   [(set (match_operand:SI 0 "register_operand" "")
 277         (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
 278                          (const_int 1)
 279                          (match_operand 2 "const_int_operand" "")))]
 280   ""
 281   [(set (cc0) (zero_extract:SI (match_dup 1)
 282                                (const_int 1)
 283                                (match_dup 2)))
 284    (set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
 285
 286 (define_insn "tstsi"
 287   [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
 288   ""
 289   "cmp %.,%0"
 290   [(set_attr "length" "2")
 291    (set_attr "cc" "set_znv")])
 292
 293 (define_insn "cmpsi"
 294   [(set (cc0)
 295         (compare (match_operand:SI 0 "register_operand" "r,r")
 296                  (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
 297   ""
 298   "@
 299   cmp %1,%0
 300   cmp %1,%0"
 301   [(set_attr "length" "2,2")
 302    (set_attr "cc" "compare")])
 303 \f
 304 ;; ----------------------------------------------------------------------
 305 ;; ADD INSTRUCTIONS
 306 ;; ----------------------------------------------------------------------
 307
 308 (define_insn "addsi3"
 309   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 310         (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
 311                  (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))]
 312   ""
 313   "@
 314    add %2,%0
 315    addi %2,%1,%0
 316    addi %O2(%P2),%1,%0"
 317   [(set_attr "length" "2,4,4")
 318    (set_attr "cc" "set_zn,set_zn,set_zn")])
 319
 320 ;; ----------------------------------------------------------------------
 321 ;; SUBTRACT INSTRUCTIONS
 322 ;; ----------------------------------------------------------------------
 323
 324 (define_insn "subsi3"
 325   [(set (match_operand:SI 0 "register_operand" "=r,r")
 326         (minus:SI (match_operand:SI 1 "register_operand" "0,r")
 327                   (match_operand:SI 2 "register_operand" "r,0")))]
 328   ""
 329   "@
 330   sub %2,%0
 331   subr %1,%0"
 332   [(set_attr "length" "2,2")
 333    (set_attr "cc" "set_zn")])
 334
 335 (define_insn "negsi2"
 336   [(set (match_operand:SI 0 "register_operand" "=r")
 337         (neg:SI (match_operand:SI 1 "register_operand" "0")))]
 338   ""
 339   "subr %.,%0"
 340   [(set_attr "length" "2")
 341    (set_attr "cc" "set_zn")])
 342
 343 ;; ----------------------------------------------------------------------
 344 ;; MULTIPLY INSTRUCTIONS
 345 ;; ----------------------------------------------------------------------
 346
 347 (define_expand "mulhisi3"
 348   [(set (match_operand:SI 0 "register_operand" "")
 349         (mult:SI
 350           (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
 351           (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
 352   ""
 353   "")
 354
 355 (define_insn "*mulhisi3_internal1"
 356   [(set (match_operand:SI 0 "register_operand" "=r")
 357         (mult:SI
 358           (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
 359           (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
 360   ""
 361   "mulh %2,%0"
 362   [(set_attr "length" "2")
 363    (set_attr "cc" "none_0hit")
 364    (set_attr "type" "mult")])
 365
 366 ;; ??? Sign extending constants isn't valid.  Fix?
 367
 368 (define_insn "*mulhisi3_internal2"
 369   [(set (match_operand:SI 0 "register_operand" "=r,r")
 370         (mult:SI
 371           (sign_extend:SI (match_operand:HI 1 "register_operand" "%0,r"))
 372           (sign_extend:SI (match_operand 2 "const_int_operand" "J,K"))))]
 373   ""
 374   "@
 375    mulh %2,%0
 376    mulhi %2,%1,%0"
 377   [(set_attr "length" "2,4")
 378    (set_attr "cc" "none_0hit,none_0hit")
 379    (set_attr "type" "mult")])
 380
 381 \f
 382 ;; ----------------------------------------------------------------------
 383 ;; AND INSTRUCTIONS
 384 ;; ----------------------------------------------------------------------
 385
 386 (define_insn "*v850_clr1_1"
 387   [(set (match_operand:QI 0 "memory_operand" "=m")
 388         (subreg:QI
 389           (and:SI (subreg:SI (match_dup 0) 0)
 390                   (match_operand:QI 1 "not_power_of_two_operand" "")) 0))]
 391   ""
 392   "*
 393 {
 394   rtx xoperands[2];
 395   xoperands[0] = operands[0];
 396   xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
 397   output_asm_insn (\"clr1 %M1,%0\", xoperands);
 398   return \"\";
 399 }"
 400   [(set_attr "length" "4")
 401    (set_attr "cc" "clobber")])
 402
 403 (define_insn "*v850_clr1_2"
 404   [(set (match_operand:HI 0 "indirect_operand" "=m")
 405         (subreg:HI
 406           (and:SI (subreg:SI (match_dup 0) 0)
 407                   (match_operand:HI 1 "not_power_of_two_operand" "")) 0))]
 408   ""
 409   "*
 410 {
 411   int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
 412
 413   rtx xoperands[2];
 414   xoperands[0] = gen_rtx_MEM (QImode,
 415                               plus_constant (XEXP (operands[0], 0), log2 / 8));
 416   xoperands[1] = GEN_INT (log2 % 8);
 417   output_asm_insn (\"clr1 %1,%0\", xoperands);
 418   return \"\";
 419 }"
 420   [(set_attr "length" "4")
 421    (set_attr "cc" "clobber")])
 422
 423 (define_insn "*v850_clr1_3"
 424   [(set (match_operand:SI 0 "indirect_operand" "=m")
 425         (and:SI (match_dup 0)
 426                 (match_operand:SI 1 "not_power_of_two_operand" "")))]
 427   ""
 428   "*
 429 {
 430   int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
 431
 432   rtx xoperands[2];
 433   xoperands[0] = gen_rtx_MEM (QImode,
 434                               plus_constant (XEXP (operands[0], 0), log2 / 8));
 435   xoperands[1] = GEN_INT (log2 % 8);
 436   output_asm_insn (\"clr1 %1,%0\", xoperands);
 437   return \"\";
 438 }"
 439   [(set_attr "length" "4")
 440    (set_attr "cc" "clobber")])
 441
 442 (define_insn "andsi3"
 443   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 444         (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
 445                 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
 446   ""
 447   "@
 448   and %2,%0
 449   and %.,%0
 450   andi %2,%1,%0"
 451   [(set_attr "length" "2,2,4")
 452    (set_attr "cc" "set_znv")])
 453
 454 ;; ----------------------------------------------------------------------
 455 ;; OR INSTRUCTIONS
 456 ;; ----------------------------------------------------------------------
 457
 458 (define_insn "*v850_set1_1"
 459   [(set (match_operand:QI 0 "memory_operand" "=m")
 460         (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0)
 461                            (match_operand 1 "power_of_two_operand" "")) 0))]
 462   ""
 463   "set1 %M1,%0"
 464   [(set_attr "length" "4")
 465    (set_attr "cc" "clobber")])
 466
 467 (define_insn "*v850_set1_2"
 468   [(set (match_operand:HI 0 "indirect_operand" "=m")
 469         (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
 470                            (match_operand 1 "power_of_two_operand" "")) 0))]
 471   ""
 472   "*
 473 {
 474   int log2 = exact_log2 (INTVAL (operands[1]));
 475
 476   if (log2 < 8)
 477     return \"set1 %M1,%0\";
 478   else
 479     {
 480       rtx xoperands[2];
 481       xoperands[0] = gen_rtx_MEM (QImode,
 482                                   plus_constant (XEXP (operands[0], 0),
 483                                                  log2 / 8));
 484       xoperands[1] = GEN_INT (log2 % 8);
 485       output_asm_insn (\"set1 %1,%0\", xoperands);
 486     }
 487   return \"\";
 488 }"
 489   [(set_attr "length" "4")
 490    (set_attr "cc" "clobber")])
 491
 492 (define_insn "*v850_set1_3"
 493   [(set (match_operand:SI 0 "indirect_operand" "=m")
 494         (ior:SI (match_dup 0)
 495                 (match_operand 1 "power_of_two_operand" "")))]
 496   ""
 497   "*
 498 {
 499   int log2 = exact_log2 (INTVAL (operands[1]));
 500
 501   if (log2 < 8)
 502     return \"set1 %M1,%0\";
 503   else
 504     {
 505       rtx xoperands[2];
 506       xoperands[0] = gen_rtx_MEM (QImode,
 507                                   plus_constant (XEXP (operands[0], 0),
 508                                                  log2 / 8));
 509       xoperands[1] = GEN_INT (log2 % 8);
 510       output_asm_insn (\"set1 %1,%0\", xoperands);
 511     }
 512   return \"\";
 513 }"
 514   [(set_attr "length" "4")
 515    (set_attr "cc" "clobber")])
 516
 517 (define_insn "iorsi3"
 518   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 519         (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
 520                 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
 521   ""
 522   "@
 523   or %2,%0
 524   or %.,%0
 525   ori %2,%1,%0"
 526   [(set_attr "length" "2,2,4")
 527    (set_attr "cc" "set_znv")])
 528
 529 ;; ----------------------------------------------------------------------
 530 ;; XOR INSTRUCTIONS
 531 ;; ----------------------------------------------------------------------
 532
 533 (define_insn "*v850_not1_1"
 534   [(set (match_operand:QI 0 "memory_operand" "=m")
 535         (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0)
 536                            (match_operand 1 "power_of_two_operand" "")) 0))]
 537   ""
 538   "not1 %M1,%0"
 539   [(set_attr "length" "4")
 540    (set_attr "cc" "clobber")])
 541
 542 (define_insn "*v850_not1_2"
 543   [(set (match_operand:HI 0 "indirect_operand" "=m")
 544         (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
 545                            (match_operand 1 "power_of_two_operand" "")) 0))]
 546   ""
 547   "*
 548 {
 549   int log2 = exact_log2 (INTVAL (operands[1]));
 550
 551   if (log2 < 8)
 552     return \"not1 %M1,%0\";
 553   else
 554     {
 555       rtx xoperands[2];
 556       xoperands[0] = gen_rtx_MEM (QImode,
 557                                   plus_constant (XEXP (operands[0], 0),
 558                                                  log2 / 8));
 559       xoperands[1] = GEN_INT (log2 % 8);
 560       output_asm_insn (\"not1 %1,%0\", xoperands);
 561     }
 562   return \"\";
 563 }"
 564   [(set_attr "length" "4")
 565    (set_attr "cc" "clobber")])
 566
 567 (define_insn "*v850_not1_3"
 568   [(set (match_operand:SI 0 "indirect_operand" "=m")
 569         (xor:SI (match_dup 0)
 570                 (match_operand 1 "power_of_two_operand" "")))]
 571   ""
 572   "*
 573 {
 574   int log2 = exact_log2 (INTVAL (operands[1]));
 575
 576   if (log2 < 8)
 577     return \"not1 %M1,%0\";
 578   else
 579     {
 580       rtx xoperands[2];
 581       xoperands[0] = gen_rtx_MEM (QImode,
 582                                   plus_constant (XEXP (operands[0], 0),
 583                                                  log2 / 8));
 584       xoperands[1] = GEN_INT (log2 % 8);
 585       output_asm_insn (\"not1 %1,%0\", xoperands);
 586     }
 587   return \"\";
 588 }"
 589   [(set_attr "length" "4")
 590    (set_attr "cc" "clobber")])
 591
 592 (define_insn "xorsi3"
 593   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 594         (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
 595                 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
 596   ""
 597   "@
 598   xor %2,%0
 599   xor %.,%0
 600   xori %2,%1,%0"
 601   [(set_attr "length" "2,2,4")
 602    (set_attr "cc" "set_znv")])
 603 \f
 604 ;; ----------------------------------------------------------------------
 605 ;; NOT INSTRUCTIONS
 606 ;; ----------------------------------------------------------------------
 607
 608 (define_insn "one_cmplsi2"
 609   [(set (match_operand:SI 0 "register_operand" "=r")
 610         (not:SI (match_operand:SI 1 "register_operand" "r")))]
 611   ""
 612   "not %1,%0"
 613   [(set_attr "length" "2")
 614    (set_attr "cc" "set_znv")])
 615 \f
 616 ;; -----------------------------------------------------------------
 617 ;; BIT FIELDS
 618 ;; -----------------------------------------------------------------
 619
 620 ;; ??? Is it worth defining insv and extv for the V850 series?!?
 621
 622 ;; An insv pattern would be useful, but does not get used because
 623 ;; store_bit_field never calls insv when storing a constant value into a
 624 ;; single-bit bitfield.
 625
 626 ;; extv/extzv patterns would be useful, but do not get used because
 627 ;; optimize_bitfield_compare in fold-const usually converts single
 628 ;; bit extracts into an AND with a mask.
 629
 630 ;; -----------------------------------------------------------------
 631 ;; Scc INSTRUCTIONS
 632 ;; -----------------------------------------------------------------
 633
 634 (define_insn "sle"
 635   [(set (match_operand:SI 0 "register_operand" "=r")
 636         (le:SI (cc0) (const_int 0)))]
 637   ""
 638   "*
 639 {
 640   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 641     return 0;
 642
 643   return \"setf le,%0\";
 644 }"
 645   [(set_attr "length" "4")
 646    (set_attr "cc" "none_0hit")])
 647
 648 (define_insn "sleu"
 649   [(set (match_operand:SI 0 "register_operand" "=r")
 650         (leu:SI (cc0) (const_int 0)))]
 651   ""
 652   "setf nh,%0"
 653   [(set_attr "length" "4")
 654    (set_attr "cc" "none_0hit")])
 655
 656 (define_insn "sge"
 657   [(set (match_operand:SI 0 "register_operand" "=r")
 658         (ge:SI (cc0) (const_int 0)))]
 659   ""
 660   "*
 661 {
 662   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 663     return 0;
 664
 665   return \"setf ge,%0\";
 666 }"
 667   [(set_attr "length" "4")
 668    (set_attr "cc" "none_0hit")])
 669
 670 (define_insn "sgeu"
 671   [(set (match_operand:SI 0 "register_operand" "=r")
 672         (geu:SI (cc0) (const_int 0)))]
 673   ""
 674   "setf nl,%0"
 675   [(set_attr "length" "4")
 676    (set_attr "cc" "none_0hit")])
 677
 678 (define_insn "slt"
 679   [(set (match_operand:SI 0 "register_operand" "=r")
 680         (lt:SI (cc0) (const_int 0)))]
 681   ""
 682   "*
 683 {
 684   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 685     return 0;
 686
 687   return \"setf lt,%0\";
 688 }"
 689   [(set_attr "length" "4")
 690    (set_attr "cc" "none_0hit")])
 691
 692 (define_insn "sltu"
 693   [(set (match_operand:SI 0 "register_operand" "=r")
 694         (ltu:SI (cc0) (const_int 0)))]
 695   ""
 696   "setf l,%0"
 697   [(set_attr "length" "4")
 698    (set_attr "cc" "none_0hit")])
 699
 700 (define_insn "sgt"
 701   [(set (match_operand:SI 0 "register_operand" "=r")
 702         (gt:SI (cc0) (const_int 0)))]
 703   ""
 704   "*
 705 {
 706   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 707     return 0;
 708
 709   return \"setf gt,%0\";
 710 }"
 711   [(set_attr "length" "4")
 712    (set_attr "cc" "none_0hit")])
 713
 714 (define_insn "sgtu"
 715   [(set (match_operand:SI 0 "register_operand" "=r")
 716         (gtu:SI (cc0) (const_int 0)))]
 717   ""
 718   "setf h,%0"
 719   [(set_attr "length" "4")
 720    (set_attr "cc" "none_0hit")])
 721
 722 (define_insn "seq"
 723   [(set (match_operand:SI 0 "register_operand" "=r")
 724         (eq:SI (cc0) (const_int 0)))]
 725   ""
 726   "setf z,%0"
 727   [(set_attr "length" "4")
 728    (set_attr "cc" "none_0hit")])
 729
 730 (define_insn "sne"
 731   [(set (match_operand:SI 0 "register_operand" "=r")
 732         (ne:SI (cc0) (const_int 0)))]
 733   ""
 734   "setf nz,%0"
 735   [(set_attr "length" "4")
 736    (set_attr "cc" "none_0hit")])
 737
 738 \f
 739 ;; ----------------------------------------------------------------------
 740 ;; JUMP INSTRUCTIONS
 741 ;; ----------------------------------------------------------------------
 742
 743 ;; Conditional jump instructions
 744
 745 (define_expand "ble"
 746   [(set (pc)
 747         (if_then_else (le (cc0)
 748                           (const_int 0))
 749                       (label_ref (match_operand 0 "" ""))
 750                       (pc)))]
 751   ""
 752   "")
 753
 754 (define_expand "bleu"
 755   [(set (pc)
 756         (if_then_else (leu (cc0)
 757                            (const_int 0))
 758                       (label_ref (match_operand 0 "" ""))
 759                       (pc)))]
 760   ""
 761   "")
 762
 763 (define_expand "bge"
 764   [(set (pc)
 765         (if_then_else (ge (cc0)
 766                           (const_int 0))
 767                       (label_ref (match_operand 0 "" ""))
 768                       (pc)))]
 769   ""
 770   "")
 771
 772 (define_expand "bgeu"
 773   [(set (pc)
 774         (if_then_else (geu (cc0)
 775                            (const_int 0))
 776                       (label_ref (match_operand 0 "" ""))
 777                       (pc)))]
 778   ""
 779   "")
 780
 781 (define_expand "blt"
 782   [(set (pc)
 783         (if_then_else (lt (cc0)
 784                           (const_int 0))
 785                       (label_ref (match_operand 0 "" ""))
 786                       (pc)))]
 787   ""
 788   "")
 789
 790 (define_expand "bltu"
 791   [(set (pc)
 792         (if_then_else (ltu (cc0)
 793                            (const_int 0))
 794                       (label_ref (match_operand 0 "" ""))
 795                       (pc)))]
 796   ""
 797   "")
 798
 799 (define_expand "bgt"
 800   [(set (pc)
 801         (if_then_else (gt (cc0)
 802                           (const_int 0))
 803                       (label_ref (match_operand 0 "" ""))
 804                       (pc)))]
 805   ""
 806   "")
 807
 808 (define_expand "bgtu"
 809   [(set (pc)
 810         (if_then_else (gtu (cc0)
 811                            (const_int 0))
 812                       (label_ref (match_operand 0 "" ""))
 813                       (pc)))]
 814   ""
 815   "")
 816
 817 (define_expand "beq"
 818   [(set (pc)
 819         (if_then_else (eq (cc0)
 820                           (const_int 0))
 821                       (label_ref (match_operand 0 "" ""))
 822                       (pc)))]
 823   ""
 824   "")
 825
 826 (define_expand "bne"
 827   [(set (pc)
 828         (if_then_else (ne (cc0)
 829                           (const_int 0))
 830                       (label_ref (match_operand 0 "" ""))
 831                       (pc)))]
 832   ""
 833   "")
 834
 835 (define_insn "*branch_normal"
 836   [(set (pc)
 837         (if_then_else (match_operator 1 "comparison_operator"
 838                                       [(cc0) (const_int 0)])
 839                       (label_ref (match_operand 0 "" ""))
 840                       (pc)))]
 841   ""
 842   "*
 843 {
 844   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
 845       && (GET_CODE (operands[1]) == GT
 846           || GET_CODE (operands[1]) == GE
 847           || GET_CODE (operands[1]) == LE
 848           || GET_CODE (operands[1]) == LT))
 849     return 0;
 850
 851   if (get_attr_length (insn) == 2)
 852     return \"b%b1 %l0\";
 853   else
 854     return \"b%B1 .+6 ; jr %l0\";
 855 }"
 856  [(set (attr "length")
 857     (if_then_else (lt (abs (minus (match_dup 0) (pc)))
 858                       (const_int 256))
 859                   (const_int 2)
 860                   (const_int 6)))
 861   (set_attr "cc" "none")])
 862
 863 (define_insn "*branch_invert"
 864   [(set (pc)
 865         (if_then_else (match_operator 1 "comparison_operator"
 866                                       [(cc0) (const_int 0)])
 867                       (pc)
 868                       (label_ref (match_operand 0 "" ""))))]
 869   ""
 870   "*
 871 {
 872   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
 873       && (GET_CODE (operands[1]) == GT
 874           || GET_CODE (operands[1]) == GE
 875           || GET_CODE (operands[1]) == LE
 876           || GET_CODE (operands[1]) == LT))
 877     return 0;
 878   if (get_attr_length (insn) == 2)
 879     return \"b%B1 %l0\";
 880   else
 881     return \"b%b1 .+6 ; jr %l0\";
 882 }"
 883  [(set (attr "length")
 884     (if_then_else (lt (abs (minus (match_dup 0) (pc)))
 885                       (const_int 256))
 886                   (const_int 2)
 887                   (const_int 6)))
 888   (set_attr "cc" "none")])
 889
 890 ;; Unconditional and other jump instructions.
 891
 892 (define_insn "jump"
 893   [(set (pc)
 894         (label_ref (match_operand 0 "" "")))]
 895   ""
 896   "*
 897 {
 898   if (get_attr_length (insn) == 2)
 899     return \"br %0\";
 900   else
 901     return \"jr %0\";
 902 }"
 903  [(set (attr "length")
 904     (if_then_else (lt (abs (minus (match_dup 0) (pc)))
 905                       (const_int 256))
 906                   (const_int 2)
 907                   (const_int 4)))
 908   (set_attr "cc" "none")])
 909
 910 (define_insn "indirect_jump"
 911   [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
 912   ""
 913   "jmp %0"
 914   [(set_attr "length" "2")
 915    (set_attr "cc" "none")])
 916
 917 (define_insn "tablejump"
 918   [(set (pc) (match_operand:SI 0 "register_operand" "r"))
 919    (use (label_ref (match_operand 1 "" "")))]
 920   ""
 921   "jmp  %0"
 922   [(set_attr "length" "2")
 923    (set_attr "cc" "none")])
 924
 925 (define_expand "casesi"
 926   [(match_operand:SI 0 "register_operand" "")
 927    (match_operand:SI 1 "register_operand" "")
 928    (match_operand:SI 2 "register_operand" "")
 929    (match_operand 3 "" "") (match_operand 4 "" "")]
 930   ""
 931   "
 932 {
 933   rtx reg = gen_reg_rtx (SImode);
 934   rtx tableaddress = gen_reg_rtx (SImode);
 935   rtx mem;
 936
 937   /* Subtract the lower bound from the index.  */
 938   emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
 939   /* Compare the result against the number of table entries.  */
 940   emit_insn (gen_cmpsi (reg, operands[2]));
 941   /* Branch to the default label if out of range of the table.  */
 942   emit_jump_insn (gen_bgtu (operands[4]));
 943
 944   /* Shift index for the table array access.  */
 945   emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
 946   /* Load the table address into a pseudo.  */
 947   emit_insn (gen_movsi (tableaddress,
 948                         gen_rtx_LABEL_REF (VOIDmode, operands[3])));
 949   /* Add the table address to the index.  */
 950   emit_insn (gen_addsi3 (reg, reg, tableaddress));
 951   /* Load the table entry.  */
 952   mem = gen_rtx_MEM (CASE_VECTOR_MODE, reg);
 953   RTX_UNCHANGING_P (mem);
 954   if (! TARGET_BIG_SWITCH)
 955     {
 956       rtx reg2 = gen_reg_rtx (HImode);
 957       emit_insn (gen_movhi (reg2, mem));
 958       emit_insn (gen_extendhisi2 (reg, reg2));
 959     }
 960   else
 961     emit_insn (gen_movsi (reg, mem));
 962   /* Add the table address.  */
 963   emit_insn (gen_addsi3 (reg, reg, tableaddress));
 964   /* Branch to the switch label.  */
 965   emit_jump_insn (gen_tablejump (reg, operands[3]));
 966   DONE;
 967 }")
 968
 969 ;; Call subroutine with no return value.
 970
 971 (define_expand "call"
 972   [(call (match_operand:QI 0 "general_operand" "")
 973          (match_operand:SI 1 "general_operand" ""))]
 974   ""
 975   "
 976 {
 977   if (! call_address_operand (XEXP (operands[0], 0))
 978       || TARGET_LONG_CALLS)
 979     XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
 980   if (TARGET_LONG_CALLS)
 981     emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1]));
 982   else
 983     emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
 984
 985   DONE;
 986 }")
 987
 988 (define_insn "call_internal_short"
 989   [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
 990          (match_operand:SI 1 "general_operand" "g,g"))
 991    (clobber (reg:SI 31))]
 992   "! TARGET_LONG_CALLS"
 993   "@
 994   jarl %0,r31
 995   jarl .+4,r31 ; add 4,r31 ; jmp %0"
 996   [(set_attr "length" "4,8")]
 997 )
 998
 999 (define_insn "call_internal_long"
1000   [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
1001          (match_operand:SI 1 "general_operand" "g,g"))
1002    (clobber (reg:SI 31))]
1003   "TARGET_LONG_CALLS"
1004   "*
1005   {
1006   if (which_alternative == 0)
1007     {
1008       if (GET_CODE (operands[0]) == REG)
1009         return \"jarl %0,r31\";
1010       else
1011         return \"movhi hi(%0), r0, r11 ; movea lo(%0), r11, r11 ; jarl .+4,r31 ; add 4, r31 ; jmp r11\";
1012     }
1013   else
1014     return \"jarl .+4,r31 ; add 4,r31 ; jmp %0\";
1015   }"
1016   [(set_attr "length" "16,8")]
1017 )
1018
1019 ;; Call subroutine, returning value in operand 0
1020 ;; (which must be a hard register).
1021
1022 (define_expand "call_value"
1023   [(set (match_operand 0 "" "")
1024         (call (match_operand:QI 1 "general_operand" "")
1025               (match_operand:SI 2 "general_operand" "")))]
1026   ""
1027   "
1028 {
1029   if (! call_address_operand (XEXP (operands[1], 0))
1030       || TARGET_LONG_CALLS)
1031     XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1032   if (TARGET_LONG_CALLS)
1033     emit_call_insn (gen_call_value_internal_long (operands[0],
1034                                                   XEXP (operands[1], 0),
1035                                                   operands[2]));
1036   else
1037     emit_call_insn (gen_call_value_internal_short (operands[0],
1038                                                    XEXP (operands[1], 0),
1039                                                    operands[2]));
1040   DONE;
1041 }")
1042
1043 (define_insn "call_value_internal_short"
1044   [(set (match_operand 0 "" "=r,r")
1045         (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1046               (match_operand:SI 2 "general_operand" "g,g")))
1047    (clobber (reg:SI 31))]
1048   "! TARGET_LONG_CALLS"
1049   "@
1050   jarl %1,r31
1051   jarl .+4,r31 ; add 4,r31 ; jmp %1"
1052   [(set_attr "length" "4,8")]
1053 )
1054
1055 (define_insn "call_value_internal_long"
1056   [(set (match_operand 0 "" "=r,r")
1057         (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1058               (match_operand:SI 2 "general_operand" "g,g")))
1059    (clobber (reg:SI 31))]
1060   "TARGET_LONG_CALLS"
1061   "*
1062   {
1063   if (which_alternative == 0)
1064     {
1065       if (GET_CODE (operands[1]) == REG)
1066         return \"jarl %1, r31\";
1067       else
1068       /* Reload can generate this pattern... */
1069         return \"movhi hi(%1), r0, r11 ; movea lo(%1), r11, r11 ; jarl .+4, r31 ; add 4, r31 ; jmp r11\";
1070     }
1071   else
1072     return \"jarl .+4, r31 ; add 4, r31 ; jmp %1\";
1073   }"
1074   [(set_attr "length" "16,8")]
1075 )
1076
1077 (define_insn "nop"
1078   [(const_int 0)]
1079   ""
1080   "nop"
1081   [(set_attr "length" "2")
1082    (set_attr "cc" "none")])
1083 \f
1084 ;; ----------------------------------------------------------------------
1085 ;; EXTEND INSTRUCTIONS
1086 ;; ----------------------------------------------------------------------
1087
1088
1089 (define_insn "zero_extendhisi2"
1090   [(set (match_operand:SI 0 "register_operand" "=r")
1091         (zero_extend:SI
1092          (match_operand:HI 1 "register_operand" "r")))]
1093   ""
1094   "andi 65535,%1,%0"
1095   [(set_attr "length" "4")
1096    (set_attr "cc" "set_znv")])
1097
1098
1099 (define_insn "zero_extendqisi2"
1100   [(set (match_operand:SI 0 "register_operand" "=r")
1101         (zero_extend:SI
1102          (match_operand:QI 1 "register_operand" "r")))]
1103   ""
1104   "andi 255,%1,%0"
1105   [(set_attr "length" "4")
1106    (set_attr "cc" "set_znv")])
1107
1108 ;;- sign extension instructions
1109
1110
1111 ;; ??? This is missing a sign extend from memory pattern to match the ld.h
1112 ;; instruction.
1113
1114 (define_expand "extendhisi2"
1115   [(set (match_dup 2)
1116         (ashift:SI (match_operand:HI 1 "register_operand" "")
1117                    (const_int 16)))
1118    (set (match_operand:SI 0 "register_operand" "")
1119        (ashiftrt:SI (match_dup 2)
1120                      (const_int 16)))]
1121   ""
1122   "
1123 {
1124   operands[1] = gen_lowpart (SImode, operands[1]);
1125   operands[2] = gen_reg_rtx (SImode);
1126 }")
1127
1128
1129 ;; ??? This is missing a sign extend from memory pattern to match the ld.b
1130 ;; instruction.
1131
1132 (define_expand "extendqisi2"
1133   [(set (match_dup 2)
1134         (ashift:SI (match_operand:QI 1 "register_operand" "")
1135                    (const_int 24)))
1136    (set (match_operand:SI 0 "register_operand" "")
1137         (ashiftrt:SI (match_dup 2)
1138                      (const_int 24)))]
1139   ""
1140   "
1141 {
1142   operands[1] = gen_lowpart (SImode, operands[1]);
1143   operands[2] = gen_reg_rtx (SImode);
1144 }")
1145 \f
1146 ;; ----------------------------------------------------------------------
1147 ;; SHIFTS
1148 ;; ----------------------------------------------------------------------
1149
1150 (define_insn "ashlsi3"
1151   [(set (match_operand:SI 0 "register_operand" "=r,r")
1152         (ashift:SI
1153          (match_operand:SI 1 "register_operand" "0,0")
1154          (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1155   ""
1156   "@
1157   shl %2,%0
1158   shl %2,%0"
1159   [(set_attr "length" "4,2")
1160    (set_attr "cc" "set_znv")])
1161
1162 (define_insn "lshrsi3"
1163   [(set (match_operand:SI 0 "register_operand" "=r,r")
1164         (lshiftrt:SI
1165          (match_operand:SI 1 "register_operand" "0,0")
1166          (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1167   ""
1168   "@
1169   shr %2,%0
1170   shr %2,%0"
1171   [(set_attr "length" "4,2")
1172    (set_attr "cc" "set_znv")])
1173
1174 (define_insn "ashrsi3"
1175   [(set (match_operand:SI 0 "register_operand" "=r,r")
1176         (ashiftrt:SI
1177          (match_operand:SI 1 "register_operand" "0,0")
1178          (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1179   ""
1180   "@
1181   sar %2,%0
1182   sar %2,%0"
1183   [(set_attr "length" "4,2")
1184    (set_attr "cc" "set_znv")])
1185
1186 ;; ----------------------------------------------------------------------
1187 ;; PROLOGUE/EPILOGUE
1188 ;; ----------------------------------------------------------------------
1189 (define_expand "prologue"
1190   [(const_int 0)]
1191   ""
1192   "expand_prologue (); DONE;")
1193
1194 (define_expand "epilogue"
1195   [(return)]
1196   ""
1197   "
1198 {
1199   /* Try to use the trivial return first.  Else use the
1200      full epilogue.  */
1201   if (0)
1202     emit_jump_insn (gen_return ());
1203   else
1204     expand_epilogue ();
1205   DONE;
1206 }")
1207
1208 (define_insn "return"
1209   [(return)]
1210   "reload_completed && compute_frame_size (get_frame_size (), (long *)0) == 0"
1211   "jmp [r31]"
1212   [(set_attr "length" "2")
1213    (set_attr "cc" "none")])
1214
1215 (define_insn "return_internal"
1216   [(return)
1217    (use (reg:SI 31))]
1218   ""
1219   "jmp [r31]"
1220   [(set_attr "length" "2")
1221    (set_attr "cc" "none")])
1222
1223
1224 \f
1225 ;; ----------------------------------------------------------------------
1226 ;; HELPER INSTRUCTIONS for saving the prologue and epilog registers
1227 ;; ----------------------------------------------------------------------
1228
1229 ;; This pattern will match a stack adjust RTX followed by any number of push
1230 ;; RTXs.  These RTXs will then be turned into a suitable call to a worker
1231 ;; function.
1232
1233
1234 (define_insn ""
1235  [(match_parallel 0 "pattern_is_ok_for_prologue"
1236    [(set (reg:SI 3)
1237          (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1238     (set (mem:SI (plus:SI (reg:SI 3)
1239                            (match_operand:SI 2 "immediate_operand" "i")))
1240          (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
1241  "TARGET_PROLOG_FUNCTION"
1242  "* return construct_save_jarl (operands[0]);
1243  "
1244  [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1245                                      (const_string "16")
1246                                      (const_string "4")))
1247   (set_attr "cc"     "clobber")])
1248
1249 ;; This pattern will match a return RTX followed by any number of pop RTXs
1250 ;; and possible a stack adjustment as well.  These RTXs will be turned into
1251 ;; a suitable call to a worker function.
1252
1253 (define_insn ""
1254 [(match_parallel 0 "pattern_is_ok_for_epilogue"
1255    [(return)
1256     (set (reg:SI 3)
1257          (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1258     (set (match_operand:SI 2 "register_is_ok_for_epilogue" "=r")
1259          (mem:SI (plus:SI (reg:SI 3)
1260                           (match_operand:SI 3 "immediate_operand" "i"))))])]
1261  "TARGET_PROLOG_FUNCTION && TARGET_V850"
1262  "* return construct_restore_jr (operands[0]);
1263  "
1264  [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1265                                      (const_string "12")
1266                                      (const_string "4")))
1267   (set_attr "cc"     "clobber")])
1268
1269 ;; Initialize an interrupt function.  Do not depend on TARGET_PROLOG_FUNCTION.
1270 (define_insn "save_interrupt"
1271   [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -16)))
1272    (set (mem:SI (reg:SI 3)) (reg:SI 30))
1273    (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 10))
1274    (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 4))
1275    (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1))]
1276   "TARGET_V850 && ! TARGET_LONG_CALLS"
1277   "add -16, sp ; st.w r10, 12[sp] ; jarl __save_interrupt, r10"
1278   [(set_attr "length" "12")
1279    (set_attr "cc" "clobber")])
1280
1281 ;; Restore r1, r4, r10, and return from the interrupt
1282 (define_insn "restore_interrupt"
1283   [(return)
1284    (set (reg:SI 3) (plus:SI (reg:SI 3) (const_int 16)))
1285    (set (reg:SI 30) (mem:SI (plus:SI (reg:SI 3) (const_int 12))))
1286    (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 8))))
1287    (set (reg:SI 4)  (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
1288    (set (reg:SI 1)  (mem:SI (reg:SI 3)))]
1289   ""
1290   "jr __return_interrupt"
1291   [(set_attr "length" "4")
1292    (set_attr "cc" "clobber")])
1293
1294
1295 ;; Save all registers except for the registers saved in save_interrupt when
1296 ;; an interrupt function makes a call.
1297 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1298 ;; all of memory.  This blocks insns from being moved across this point.
1299 ;; This is needed because the rest of the compiler is not ready to handle
1300 ;; insns this complicated.
1301
1302 (define_insn "save_all_interrupt"
1303   [(unspec_volatile [(const_int 0)] 0)]
1304   "TARGET_V850 && ! TARGET_LONG_CALLS"
1305   "jarl __save_all_interrupt,r10"
1306   [(set_attr "length" "4")
1307    (set_attr "cc" "clobber")])
1308
1309
1310 ;; Restore all registers saved when an interrupt function makes a call.
1311 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1312 ;; all of memory.  This blocks insns from being moved across this point.
1313 ;; This is needed because the rest of the compiler is not ready to handle
1314 ;; insns this complicated.
1315
1316 (define_insn "restore_all_interrupt"
1317   [(unspec_volatile [(const_int 0)] 1)]
1318   "TARGET_V850 && ! TARGET_LONG_CALLS"
1319   "jarl __restore_all_interrupt,r10"
1320   [(set_attr "length" "4")
1321    (set_attr "cc" "clobber")])
1322
1323 ;; Save r6-r9 for a variable argument function
1324 (define_insn "save_r6_r9"
1325   [(set (mem:SI (reg:SI 3)) (reg:SI 6))
1326    (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
1327    (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
1328    (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
1329    (clobber (reg:SI 10))]
1330   "TARGET_PROLOG_FUNCTION && ! TARGET_LONG_CALLS"
1331   "jarl __save_r6_r9,r10"
1332   [(set_attr "length" "4")
1333    (set_attr "cc" "clobber")])
1334