gcc/config/v850/v850.md

   1 ;; GCC machine description for NEC V850
   2 ;; Copyright (C) 1996, 1997, 1999 Free Software Foundation, Inc.
   3
   4 ;;   Contributed by Jeff Law (law@cygnus.com).
   5
   6 ;; This file is part of GNU CC.
   7
   8 ;; GNU CC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 2, or (at your option)
  11 ;; any later version.
  12
  13 ;; GNU CC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GNU CC; see the file COPYING.  If not, write to
  20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  21 ;; Boston, MA 02111-1307, USA.
  22
  23 ;; The original PO technology requires these to be ordered by speed,
  24 ;; so that assigner will pick the fastest.
  25
  26 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
  27
  28 ;; The V851 manual states that the instruction address space is 16M;
  29 ;; the various branch/call instructions only have a 22bit offset (4M range).
  30 ;;
  31 ;; One day we'll probably need to handle calls to targets more than 4M
  32 ;; away.
  33
  34 ;; The size of instructions in bytes.
  35
  36 (define_attr "length" ""
  37   (const_int 200))
  38
  39 (define_attr "long_calls" "yes,no"
  40   (const (if_then_else (symbol_ref "TARGET_LONG_CALLS")
  41                        (const_string "yes")
  42                        (const_string "no"))))
  43
  44 ;; Types of instructions (for scheduling purposes).
  45
  46 (define_attr "type" "load,mult,other"
  47   (const_string "other"))
  48
  49 ;; Condition code settings.
  50 ;; none - insn does not affect cc
  51 ;; none_0hit - insn does not affect cc but it does modify operand 0
  52 ;;      This attribute is used to keep track of when operand 0 changes.
  53 ;;      See the description of NOTICE_UPDATE_CC for more info.
  54 ;; set_znv - sets z,n,v to usable values; c is unknown.
  55 ;; set_zn  - sets z,n to usable values; v,c is unknown.
  56 ;; compare - compare instruction
  57 ;; clobber - value of cc is unknown
  58 (define_attr "cc" "none,none_0hit,set_zn,set_znv,compare,clobber"
  59   (const_string "clobber"))
  60 \f
  61 ;; Function units for the V850.  As best as I can tell, there's
  62 ;; a traditional memory load/use stall as well as a stall if
  63 ;; the result of a multiply is used too early.
  64 ;;
  65 (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
  66 (define_function_unit "mult"   1 0 (eq_attr "type" "mult") 2 0)
  67
  68 \f
  69 ;; ----------------------------------------------------------------------
  70 ;; MOVE INSTRUCTIONS
  71 ;; ----------------------------------------------------------------------
  72
  73 ;; movqi
  74
  75 (define_expand "movqi"
  76   [(set (match_operand:QI 0 "general_operand" "")
  77         (match_operand:QI 1 "general_operand" ""))]
  78   ""
  79   "
  80 {
  81   /* One of the ops has to be in a register or 0 */
  82   if (!register_operand (operand0, QImode)
  83       && !reg_or_0_operand (operand1, QImode))
  84     operands[1] = copy_to_mode_reg (QImode, operand1);
  85 }")
  86
  87 (define_insn "*movqi_internal"
  88   [(set (match_operand:QI 0 "general_operand" "=r,r,r,Q,r,m,m")
  89         (match_operand:QI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
  90   "register_operand (operands[0], QImode)
  91    || reg_or_0_operand (operands[1], QImode)"
  92   "* return output_move_single (operands);"
  93   [(set_attr "length" "2,4,2,2,4,4,4")
  94    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
  95    (set_attr "type" "other,other,load,other,load,other,other")])
  96
  97 ;; movhi
  98
  99 (define_expand "movhi"
 100   [(set (match_operand:HI 0 "general_operand" "")
 101         (match_operand:HI 1 "general_operand" ""))]
 102   ""
 103   "
 104 {
 105   /* One of the ops has to be in a register or 0 */
 106   if (!register_operand (operand0, HImode)
 107       && !reg_or_0_operand (operand1, HImode))
 108     operands[1] = copy_to_mode_reg (HImode, operand1);
 109 }")
 110
 111 (define_insn "*movhi_internal"
 112   [(set (match_operand:HI 0 "general_operand" "=r,r,r,Q,r,m,m")
 113         (match_operand:HI 1 "general_operand" "Jr,n,Q,Ir,m,r,I"))]
 114   "register_operand (operands[0], HImode)
 115    || reg_or_0_operand (operands[1], HImode)"
 116   "* return output_move_single (operands);"
 117   [(set_attr "length" "2,4,2,2,4,4,4")
 118    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 119    (set_attr "type" "other,other,load,other,load,other,other")])
 120
 121 ;; movsi and helpers
 122
 123 (define_insn "*movsi_high"
 124   [(set (match_operand:SI 0 "register_operand" "=r")
 125         (high:SI (match_operand 1 "" "")))]
 126   ""
 127   "movhi hi(%1),%.,%0"
 128   [(set_attr "length" "4")
 129    (set_attr "cc" "none_0hit")
 130    (set_attr "type" "other")])
 131
 132 (define_insn "*movsi_lo"
 133   [(set (match_operand:SI 0 "register_operand" "=r")
 134         (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 135                    (match_operand:SI 2 "immediate_operand" "i")))]
 136   ""
 137   "movea lo(%2),%1,%0"
 138   [(set_attr "length" "4")
 139    (set_attr "cc" "none_0hit")
 140    (set_attr "type" "other")])
 141
 142 (define_expand "movsi"
 143   [(set (match_operand:SI 0 "general_operand" "")
 144         (match_operand:SI 1 "general_operand" ""))]
 145   ""
 146   "
 147 {
 148   /* One of the ops has to be in a register or 0 */
 149   if (!register_operand (operand0, SImode)
 150       && !reg_or_0_operand (operand1, SImode))
 151     operands[1] = copy_to_mode_reg (SImode, operand1);
 152
 153   /* Some constants, as well as symbolic operands
 154      must be done with HIGH & LO_SUM patterns.  */
 155   if (CONSTANT_P (operands[1])
 156       && GET_CODE (operands[1]) != HIGH
 157       && !special_symbolref_operand (operands[1], VOIDmode)
 158       && !(GET_CODE (operands[1]) == CONST_INT
 159            && (CONST_OK_FOR_J (INTVAL (operands[1]))
 160                || CONST_OK_FOR_K (INTVAL (operands[1]))
 161                || CONST_OK_FOR_L (INTVAL (operands[1])))))
 162     {
 163       rtx high;
 164       rtx temp;
 165
 166       if (reload_in_progress || reload_completed)
 167         temp = operands[0];
 168       else
 169         temp = gen_reg_rtx (SImode);
 170
 171       emit_insn (gen_rtx (SET, SImode, temp,
 172                           gen_rtx (HIGH, SImode, operand1)));
 173       emit_insn (gen_rtx (SET, SImode, operand0,
 174                           gen_rtx (LO_SUM, SImode, temp, operand1)));
 175       DONE;
 176     }
 177 }")
 178
 179 (define_insn "*movsi_internal"
 180   [(set (match_operand:SI 0 "general_operand" "=r,r,r,r,Q,r,r,m,m")
 181         (match_operand:SI 1 "movsi_source_operand" "Jr,K,L,Q,Ir,m,R,r,I"))]
 182   "register_operand (operands[0], SImode)
 183    || reg_or_0_operand (operands[1], SImode)"
 184   "* return output_move_single (operands);"
 185   [(set_attr "length" "2,4,4,2,2,4,4,4,4")
 186    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 187    (set_attr "type" "other,other,other,load,other,load,other,other,other")])
 188
 189
 190
 191 (define_expand "movdi"
 192   [(set (match_operand:DI 0 "general_operand" "")
 193         (match_operand:DI 1 "general_operand" ""))]
 194   ""
 195   "
 196 {
 197   /* One of the ops has to be in a register or 0 */
 198   if (!register_operand (operand0, DImode)
 199       && !reg_or_0_operand (operand1, DImode))
 200     operands[1] = copy_to_mode_reg (DImode, operand1);
 201 }")
 202
 203 (define_insn "*movdi_internal"
 204   [(set (match_operand:DI 0 "general_operand" "=r,r,r,r,r,m,m,r")
 205         (match_operand:DI 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
 206   "register_operand (operands[0], DImode)
 207    || reg_or_0_operand (operands[1], DImode)"
 208   "* return output_move_double (operands);"
 209   [(set_attr "length" "4,8,8,16,8,8,8,16")
 210    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 211    (set_attr "type" "other,other,other,other,load,other,other,other")])
 212
 213 (define_expand "movsf"
 214   [(set (match_operand:SF 0 "general_operand" "")
 215         (match_operand:SF 1 "general_operand" ""))]
 216   ""
 217   "
 218 {
 219   /* One of the ops has to be in a register or 0 */
 220   if (!register_operand (operand0, SFmode)
 221       && !reg_or_0_operand (operand1, SFmode))
 222     operands[1] = copy_to_mode_reg (SFmode, operand1);
 223 }")
 224
 225 (define_insn "*movsf_internal"
 226   [(set (match_operand:SF 0 "general_operand" "=r,r,r,r,r,Q,r,m,m,r")
 227         (match_operand:SF 1 "general_operand" "Jr,K,L,n,Q,Ir,m,r,IG,iF"))]
 228   "register_operand (operands[0], SFmode)
 229    || reg_or_0_operand (operands[1], SFmode)"
 230   "* return output_move_single (operands);"
 231   [(set_attr "length" "2,4,4,8,2,2,4,4,4,8")
 232    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 233    (set_attr "type" "other,other,other,other,load,other,load,other,other,other")])
 234
 235 (define_expand "movdf"
 236   [(set (match_operand:DF 0 "general_operand" "")
 237         (match_operand:DF 1 "general_operand" ""))]
 238   ""
 239   "
 240 {
 241   /* One of the ops has to be in a register or 0 */
 242   if (!register_operand (operand0, DFmode)
 243       && !reg_or_0_operand (operand1, DFmode))
 244     operands[1] = copy_to_mode_reg (DFmode, operand1);
 245 }")
 246
 247 (define_insn "*movdf_internal"
 248   [(set (match_operand:DF 0 "general_operand" "=r,r,r,r,r,m,m,r")
 249         (match_operand:DF 1 "general_operand" "Jr,K,L,i,m,r,IG,iF"))]
 250   "register_operand (operands[0], DFmode)
 251    || reg_or_0_operand (operands[1], DFmode)"
 252   "* return output_move_double (operands);"
 253   [(set_attr "length" "4,8,8,16,8,8,8,16")
 254    (set_attr "cc" "none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit,none_0hit")
 255    (set_attr "type" "other,other,other,other,load,other,other,other")])
 256
 257 \f
 258 ;; ----------------------------------------------------------------------
 259 ;; TEST INSTRUCTIONS
 260 ;; ----------------------------------------------------------------------
 261
 262 (define_insn "*v850_tst1"
 263   [(set (cc0) (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
 264                                (const_int 1)
 265                                (match_operand:QI 1 "const_int_operand" "n")))]
 266   ""
 267   "tst1 %1,%0"
 268   [(set_attr "length" "4")
 269    (set_attr "cc" "clobber")])
 270
 271 ;; This replaces ld.b;sar;andi with tst1;setf nz.
 272
 273 ;; ??? The zero_extract sets the Z bit to the opposite of what one would
 274 ;; expect.  This perhaps should be wrapped in a (eq: X (const_int 0)).
 275
 276 (define_split
 277   [(set (match_operand:SI 0 "register_operand" "")
 278         (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
 279                          (const_int 1)
 280                          (match_operand 2 "const_int_operand" "")))]
 281   ""
 282   [(set (cc0) (zero_extract:SI (match_dup 1)
 283                                (const_int 1)
 284                                (match_dup 2)))
 285    (set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
 286
 287 (define_insn "tstsi"
 288   [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
 289   ""
 290   "cmp %.,%0"
 291   [(set_attr "length" "2")
 292    (set_attr "cc" "set_znv")])
 293
 294 (define_insn "cmpsi"
 295   [(set (cc0)
 296         (compare (match_operand:SI 0 "register_operand" "r,r")
 297                  (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
 298   ""
 299   "@
 300   cmp %1,%0
 301   cmp %1,%0"
 302   [(set_attr "length" "2,2")
 303    (set_attr "cc" "compare")])
 304 \f
 305 ;; ----------------------------------------------------------------------
 306 ;; ADD INSTRUCTIONS
 307 ;; ----------------------------------------------------------------------
 308
 309 (define_insn "addsi3"
 310   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 311         (plus:SI (match_operand:SI 1 "register_operand" "%0,r,r")
 312                  (match_operand:SI 2 "nonmemory_operand" "rJ,K,U")))]
 313   ""
 314   "@
 315    add %2,%0
 316    addi %2,%1,%0
 317    addi %O2(%P2),%1,%0"
 318   [(set_attr "length" "2,4,4")
 319    (set_attr "cc" "set_zn,set_zn,set_zn")])
 320
 321 ;; ----------------------------------------------------------------------
 322 ;; SUBTRACT INSTRUCTIONS
 323 ;; ----------------------------------------------------------------------
 324
 325 (define_insn "subsi3"
 326   [(set (match_operand:SI 0 "register_operand" "=r,r")
 327         (minus:SI (match_operand:SI 1 "register_operand" "0,r")
 328                   (match_operand:SI 2 "register_operand" "r,0")))]
 329   ""
 330   "@
 331   sub %2,%0
 332   subr %1,%0"
 333   [(set_attr "length" "2,2")
 334    (set_attr "cc" "set_zn")])
 335
 336 (define_insn "negsi2"
 337   [(set (match_operand:SI 0 "register_operand" "=r")
 338         (neg:SI (match_operand:SI 1 "register_operand" "0")))]
 339   ""
 340   "subr %.,%0"
 341   [(set_attr "length" "2")
 342    (set_attr "cc" "set_zn")])
 343
 344 ;; ----------------------------------------------------------------------
 345 ;; MULTIPLY INSTRUCTIONS
 346 ;; ----------------------------------------------------------------------
 347
 348 (define_expand "mulhisi3"
 349   [(set (match_operand:SI 0 "register_operand" "")
 350         (mult:SI
 351           (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
 352           (sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
 353   ""
 354   "")
 355
 356 (define_insn "*mulhisi3_internal1"
 357   [(set (match_operand:SI 0 "register_operand" "=r")
 358         (mult:SI
 359           (sign_extend:SI (match_operand:HI 1 "register_operand" "%0"))
 360           (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
 361   ""
 362   "mulh %2,%0"
 363   [(set_attr "length" "2")
 364    (set_attr "cc" "none_0hit")
 365    (set_attr "type" "mult")])
 366
 367 ;; ??? Sign extending constants isn't valid.  Fix?
 368
 369 (define_insn "*mulhisi3_internal2"
 370   [(set (match_operand:SI 0 "register_operand" "=r,r")
 371         (mult:SI
 372           (sign_extend:SI (match_operand:HI 1 "register_operand" "%0,r"))
 373           (sign_extend:SI (match_operand 2 "const_int_operand" "J,K"))))]
 374   ""
 375   "@
 376    mulh %2,%0
 377    mulhi %2,%1,%0"
 378   [(set_attr "length" "2,4")
 379    (set_attr "cc" "none_0hit,none_0hit")
 380    (set_attr "type" "mult")])
 381
 382 \f
 383 ;; ----------------------------------------------------------------------
 384 ;; AND INSTRUCTIONS
 385 ;; ----------------------------------------------------------------------
 386
 387 (define_insn "*v850_clr1_1"
 388   [(set (match_operand:QI 0 "memory_operand" "=m")
 389         (subreg:QI
 390           (and:SI (subreg:SI (match_dup 0) 0)
 391                   (match_operand:QI 1 "not_power_of_two_operand" "")) 0))]
 392   ""
 393   "*
 394 {
 395   rtx xoperands[2];
 396   xoperands[0] = operands[0];
 397   xoperands[1] = GEN_INT (~INTVAL (operands[1]) & 0xff);
 398   output_asm_insn (\"clr1 %M1,%0\", xoperands);
 399   return \"\";
 400 }"
 401   [(set_attr "length" "4")
 402    (set_attr "cc" "clobber")])
 403
 404 (define_insn "*v850_clr1_2"
 405   [(set (match_operand:HI 0 "indirect_operand" "=m")
 406         (subreg:HI
 407           (and:SI (subreg:SI (match_dup 0) 0)
 408                   (match_operand:HI 1 "not_power_of_two_operand" "")) 0))]
 409   ""
 410   "*
 411 {
 412   int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffff);
 413
 414   rtx xoperands[2];
 415   xoperands[0] = gen_rtx (MEM, QImode,
 416                           plus_constant (XEXP (operands[0], 0), log2 / 8));
 417   xoperands[1] = GEN_INT (log2 % 8);
 418   output_asm_insn (\"clr1 %1,%0\", xoperands);
 419   return \"\";
 420 }"
 421   [(set_attr "length" "4")
 422    (set_attr "cc" "clobber")])
 423
 424 (define_insn "*v850_clr1_3"
 425   [(set (match_operand:SI 0 "indirect_operand" "=m")
 426         (and:SI (match_dup 0)
 427                 (match_operand:SI 1 "not_power_of_two_operand" "")))]
 428   ""
 429   "*
 430 {
 431   int log2 = exact_log2 (~INTVAL (operands[1]) & 0xffffffff);
 432
 433   rtx xoperands[2];
 434   xoperands[0] = gen_rtx (MEM, QImode,
 435                           plus_constant (XEXP (operands[0], 0), log2 / 8));
 436   xoperands[1] = GEN_INT (log2 % 8);
 437   output_asm_insn (\"clr1 %1,%0\", xoperands);
 438   return \"\";
 439 }"
 440   [(set_attr "length" "4")
 441    (set_attr "cc" "clobber")])
 442
 443 (define_insn "andsi3"
 444   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 445         (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
 446                 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
 447   ""
 448   "@
 449   and %2,%0
 450   and %.,%0
 451   andi %2,%1,%0"
 452   [(set_attr "length" "2,2,4")
 453    (set_attr "cc" "set_znv")])
 454
 455 ;; ----------------------------------------------------------------------
 456 ;; OR INSTRUCTIONS
 457 ;; ----------------------------------------------------------------------
 458
 459 (define_insn "*v850_set1_1"
 460   [(set (match_operand:QI 0 "memory_operand" "=m")
 461         (subreg:QI (ior:SI (subreg:SI (match_dup 0) 0)
 462                            (match_operand 1 "power_of_two_operand" "")) 0))]
 463   ""
 464   "set1 %M1,%0"
 465   [(set_attr "length" "4")
 466    (set_attr "cc" "clobber")])
 467
 468 (define_insn "*v850_set1_2"
 469   [(set (match_operand:HI 0 "indirect_operand" "=m")
 470         (subreg:HI (ior:SI (subreg:SI (match_dup 0) 0)
 471                            (match_operand 1 "power_of_two_operand" "")) 0))]
 472   ""
 473   "*
 474 {
 475   int log2 = exact_log2 (INTVAL (operands[1]));
 476
 477   if (log2 < 8)
 478     return \"set1 %M1,%0\";
 479   else
 480     {
 481       rtx xoperands[2];
 482       xoperands[0] = gen_rtx (MEM, QImode,
 483                               plus_constant (XEXP (operands[0], 0), log2 / 8));
 484       xoperands[1] = GEN_INT (log2 % 8);
 485       output_asm_insn (\"set1 %1,%0\", xoperands);
 486     }
 487   return \"\";
 488 }"
 489   [(set_attr "length" "4")
 490    (set_attr "cc" "clobber")])
 491
 492 (define_insn "*v850_set1_3"
 493   [(set (match_operand:SI 0 "indirect_operand" "=m")
 494         (ior:SI (match_dup 0)
 495                 (match_operand 1 "power_of_two_operand" "")))]
 496   ""
 497   "*
 498 {
 499   int log2 = exact_log2 (INTVAL (operands[1]));
 500
 501   if (log2 < 8)
 502     return \"set1 %M1,%0\";
 503   else
 504     {
 505       rtx xoperands[2];
 506       xoperands[0] = gen_rtx (MEM, QImode,
 507                               plus_constant (XEXP (operands[0], 0), log2 / 8));
 508       xoperands[1] = GEN_INT (log2 % 8);
 509       output_asm_insn (\"set1 %1,%0\", xoperands);
 510     }
 511   return \"\";
 512 }"
 513   [(set_attr "length" "4")
 514    (set_attr "cc" "clobber")])
 515
 516 (define_insn "iorsi3"
 517   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 518         (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
 519                 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
 520   ""
 521   "@
 522   or %2,%0
 523   or %.,%0
 524   ori %2,%1,%0"
 525   [(set_attr "length" "2,2,4")
 526    (set_attr "cc" "set_znv")])
 527
 528 ;; ----------------------------------------------------------------------
 529 ;; XOR INSTRUCTIONS
 530 ;; ----------------------------------------------------------------------
 531
 532 (define_insn "*v850_not1_1"
 533   [(set (match_operand:QI 0 "memory_operand" "=m")
 534         (subreg:QI (xor:SI (subreg:SI (match_dup 0) 0)
 535                            (match_operand 1 "power_of_two_operand" "")) 0))]
 536   ""
 537   "not1 %M1,%0"
 538   [(set_attr "length" "4")
 539    (set_attr "cc" "clobber")])
 540
 541 (define_insn "*v850_not1_2"
 542   [(set (match_operand:HI 0 "indirect_operand" "=m")
 543         (subreg:HI (xor:SI (subreg:SI (match_dup 0) 0)
 544                            (match_operand 1 "power_of_two_operand" "")) 0))]
 545   ""
 546   "*
 547 {
 548   int log2 = exact_log2 (INTVAL (operands[1]));
 549
 550   if (log2 < 8)
 551     return \"not1 %M1,%0\";
 552   else
 553     {
 554       rtx xoperands[2];
 555       xoperands[0] = gen_rtx (MEM, QImode,
 556                               plus_constant (XEXP (operands[0], 0), log2 / 8));
 557       xoperands[1] = GEN_INT (log2 % 8);
 558       output_asm_insn (\"not1 %1,%0\", xoperands);
 559     }
 560   return \"\";
 561 }"
 562   [(set_attr "length" "4")
 563    (set_attr "cc" "clobber")])
 564
 565 (define_insn "*v850_not1_3"
 566   [(set (match_operand:SI 0 "indirect_operand" "=m")
 567         (xor:SI (match_dup 0)
 568                 (match_operand 1 "power_of_two_operand" "")))]
 569   ""
 570   "*
 571 {
 572   int log2 = exact_log2 (INTVAL (operands[1]));
 573
 574   if (log2 < 8)
 575     return \"not1 %M1,%0\";
 576   else
 577     {
 578       rtx xoperands[2];
 579       xoperands[0] = gen_rtx (MEM, QImode,
 580                               plus_constant (XEXP (operands[0], 0), log2 / 8));
 581       xoperands[1] = GEN_INT (log2 % 8);
 582       output_asm_insn (\"not1 %1,%0\", xoperands);
 583     }
 584   return \"\";
 585 }"
 586   [(set_attr "length" "4")
 587    (set_attr "cc" "clobber")])
 588
 589 (define_insn "xorsi3"
 590   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 591         (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
 592                 (match_operand:SI 2 "nonmemory_operand" "r,I,M")))]
 593   ""
 594   "@
 595   xor %2,%0
 596   xor %.,%0
 597   xori %2,%1,%0"
 598   [(set_attr "length" "2,2,4")
 599    (set_attr "cc" "set_znv")])
 600 \f
 601 ;; ----------------------------------------------------------------------
 602 ;; NOT INSTRUCTIONS
 603 ;; ----------------------------------------------------------------------
 604
 605 (define_insn "one_cmplsi2"
 606   [(set (match_operand:SI 0 "register_operand" "=r")
 607         (not:SI (match_operand:SI 1 "register_operand" "r")))]
 608   ""
 609   "not %1,%0"
 610   [(set_attr "length" "2")
 611    (set_attr "cc" "set_znv")])
 612 \f
 613 ;; -----------------------------------------------------------------
 614 ;; BIT FIELDS
 615 ;; -----------------------------------------------------------------
 616
 617 ;; ??? Is it worth defining insv and extv for the V850 series?!?
 618
 619 ;; An insv pattern would be useful, but does not get used because
 620 ;; store_bit_field never calls insv when storing a constant value into a
 621 ;; single-bit bitfield.
 622
 623 ;; extv/extzv patterns would be useful, but do not get used because
 624 ;; optimize_bitfield_compare in fold-const usually converts single
 625 ;; bit extracts into an AND with a mask.
 626
 627 ;; -----------------------------------------------------------------
 628 ;; Scc INSTRUCTIONS
 629 ;; -----------------------------------------------------------------
 630
 631 (define_insn "sle"
 632   [(set (match_operand:SI 0 "register_operand" "=r")
 633         (le:SI (cc0) (const_int 0)))]
 634   ""
 635   "*
 636 {
 637   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 638     return 0;
 639
 640   return \"setf le,%0\";
 641 }"
 642   [(set_attr "length" "4")
 643    (set_attr "cc" "none_0hit")])
 644
 645 (define_insn "sleu"
 646   [(set (match_operand:SI 0 "register_operand" "=r")
 647         (leu:SI (cc0) (const_int 0)))]
 648   ""
 649   "setf nh,%0"
 650   [(set_attr "length" "4")
 651    (set_attr "cc" "none_0hit")])
 652
 653 (define_insn "sge"
 654   [(set (match_operand:SI 0 "register_operand" "=r")
 655         (ge:SI (cc0) (const_int 0)))]
 656   ""
 657   "*
 658 {
 659   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 660     return 0;
 661
 662   return \"setf ge,%0\";
 663 }"
 664   [(set_attr "length" "4")
 665    (set_attr "cc" "none_0hit")])
 666
 667 (define_insn "sgeu"
 668   [(set (match_operand:SI 0 "register_operand" "=r")
 669         (geu:SI (cc0) (const_int 0)))]
 670   ""
 671   "setf nl,%0"
 672   [(set_attr "length" "4")
 673    (set_attr "cc" "none_0hit")])
 674
 675 (define_insn "slt"
 676   [(set (match_operand:SI 0 "register_operand" "=r")
 677         (lt:SI (cc0) (const_int 0)))]
 678   ""
 679   "*
 680 {
 681   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 682     return 0;
 683
 684   return \"setf lt,%0\";
 685 }"
 686   [(set_attr "length" "4")
 687    (set_attr "cc" "none_0hit")])
 688
 689 (define_insn "sltu"
 690   [(set (match_operand:SI 0 "register_operand" "=r")
 691         (ltu:SI (cc0) (const_int 0)))]
 692   ""
 693   "setf l,%0"
 694   [(set_attr "length" "4")
 695    (set_attr "cc" "none_0hit")])
 696
 697 (define_insn "sgt"
 698   [(set (match_operand:SI 0 "register_operand" "=r")
 699         (gt:SI (cc0) (const_int 0)))]
 700   ""
 701   "*
 702 {
 703   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
 704     return 0;
 705
 706   return \"setf gt,%0\";
 707 }"
 708   [(set_attr "length" "4")
 709    (set_attr "cc" "none_0hit")])
 710
 711 (define_insn "sgtu"
 712   [(set (match_operand:SI 0 "register_operand" "=r")
 713         (gtu:SI (cc0) (const_int 0)))]
 714   ""
 715   "setf h,%0"
 716   [(set_attr "length" "4")
 717    (set_attr "cc" "none_0hit")])
 718
 719 (define_insn "seq"
 720   [(set (match_operand:SI 0 "register_operand" "=r")
 721         (eq:SI (cc0) (const_int 0)))]
 722   ""
 723   "setf z,%0"
 724   [(set_attr "length" "4")
 725    (set_attr "cc" "none_0hit")])
 726
 727 (define_insn "sne"
 728   [(set (match_operand:SI 0 "register_operand" "=r")
 729         (ne:SI (cc0) (const_int 0)))]
 730   ""
 731   "setf nz,%0"
 732   [(set_attr "length" "4")
 733    (set_attr "cc" "none_0hit")])
 734
 735 \f
 736 ;; ----------------------------------------------------------------------
 737 ;; JUMP INSTRUCTIONS
 738 ;; ----------------------------------------------------------------------
 739
 740 ;; Conditional jump instructions
 741
 742 (define_expand "ble"
 743   [(set (pc)
 744         (if_then_else (le (cc0)
 745                           (const_int 0))
 746                       (label_ref (match_operand 0 "" ""))
 747                       (pc)))]
 748   ""
 749   "")
 750
 751 (define_expand "bleu"
 752   [(set (pc)
 753         (if_then_else (leu (cc0)
 754                            (const_int 0))
 755                       (label_ref (match_operand 0 "" ""))
 756                       (pc)))]
 757   ""
 758   "")
 759
 760 (define_expand "bge"
 761   [(set (pc)
 762         (if_then_else (ge (cc0)
 763                           (const_int 0))
 764                       (label_ref (match_operand 0 "" ""))
 765                       (pc)))]
 766   ""
 767   "")
 768
 769 (define_expand "bgeu"
 770   [(set (pc)
 771         (if_then_else (geu (cc0)
 772                            (const_int 0))
 773                       (label_ref (match_operand 0 "" ""))
 774                       (pc)))]
 775   ""
 776   "")
 777
 778 (define_expand "blt"
 779   [(set (pc)
 780         (if_then_else (lt (cc0)
 781                           (const_int 0))
 782                       (label_ref (match_operand 0 "" ""))
 783                       (pc)))]
 784   ""
 785   "")
 786
 787 (define_expand "bltu"
 788   [(set (pc)
 789         (if_then_else (ltu (cc0)
 790                            (const_int 0))
 791                       (label_ref (match_operand 0 "" ""))
 792                       (pc)))]
 793   ""
 794   "")
 795
 796 (define_expand "bgt"
 797   [(set (pc)
 798         (if_then_else (gt (cc0)
 799                           (const_int 0))
 800                       (label_ref (match_operand 0 "" ""))
 801                       (pc)))]
 802   ""
 803   "")
 804
 805 (define_expand "bgtu"
 806   [(set (pc)
 807         (if_then_else (gtu (cc0)
 808                            (const_int 0))
 809                       (label_ref (match_operand 0 "" ""))
 810                       (pc)))]
 811   ""
 812   "")
 813
 814 (define_expand "beq"
 815   [(set (pc)
 816         (if_then_else (eq (cc0)
 817                           (const_int 0))
 818                       (label_ref (match_operand 0 "" ""))
 819                       (pc)))]
 820   ""
 821   "")
 822
 823 (define_expand "bne"
 824   [(set (pc)
 825         (if_then_else (ne (cc0)
 826                           (const_int 0))
 827                       (label_ref (match_operand 0 "" ""))
 828                       (pc)))]
 829   ""
 830   "")
 831
 832 (define_insn "*branch_normal"
 833   [(set (pc)
 834         (if_then_else (match_operator 1 "comparison_operator"
 835                                       [(cc0) (const_int 0)])
 836                       (label_ref (match_operand 0 "" ""))
 837                       (pc)))]
 838   ""
 839   "*
 840 {
 841   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
 842       && (GET_CODE (operands[1]) == GT
 843           || GET_CODE (operands[1]) == GE
 844           || GET_CODE (operands[1]) == LE
 845           || GET_CODE (operands[1]) == LT))
 846     return 0;
 847
 848   if (get_attr_length (insn) == 2)
 849     return \"b%b1 %l0\";
 850   else
 851     return \"b%B1 .+6\n\tjr %l0\";
 852 }"
 853  [(set (attr "length")
 854     (if_then_else (lt (abs (minus (match_dup 0) (pc)))
 855                       (const_int 256))
 856                   (const_int 2)
 857                   (const_int 6)))
 858   (set_attr "cc" "none")])
 859
 860 (define_insn "*branch_invert"
 861   [(set (pc)
 862         (if_then_else (match_operator 1 "comparison_operator"
 863                                       [(cc0) (const_int 0)])
 864                       (pc)
 865                       (label_ref (match_operand 0 "" ""))))]
 866   ""
 867   "*
 868 {
 869   if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
 870       && (GET_CODE (operands[1]) == GT
 871           || GET_CODE (operands[1]) == GE
 872           || GET_CODE (operands[1]) == LE
 873           || GET_CODE (operands[1]) == LT))
 874     return 0;
 875   if (get_attr_length (insn) == 2)
 876     return \"b%B1 %l0\";
 877   else
 878     return \"b%b1 .+6\n\tjr %l0\";
 879 }"
 880  [(set (attr "length")
 881     (if_then_else (lt (abs (minus (match_dup 0) (pc)))
 882                       (const_int 256))
 883                   (const_int 2)
 884                   (const_int 6)))
 885   (set_attr "cc" "none")])
 886
 887 ;; Unconditional and other jump instructions.
 888
 889 (define_insn "jump"
 890   [(set (pc)
 891         (label_ref (match_operand 0 "" "")))]
 892   ""
 893   "*
 894 {
 895   if (get_attr_length (insn) == 2)
 896     return \"br %0\";
 897   else
 898     return \"jr %0\";
 899 }"
 900  [(set (attr "length")
 901     (if_then_else (lt (abs (minus (match_dup 0) (pc)))
 902                       (const_int 256))
 903                   (const_int 2)
 904                   (const_int 4)))
 905   (set_attr "cc" "none")])
 906
 907 (define_insn "indirect_jump"
 908   [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
 909   ""
 910   "jmp %0"
 911   [(set_attr "length" "2")
 912    (set_attr "cc" "none")])
 913
 914 (define_insn "tablejump"
 915   [(set (pc) (match_operand:SI 0 "register_operand" "r"))
 916    (use (label_ref (match_operand 1 "" "")))]
 917   ""
 918   "jmp  %0"
 919   [(set_attr "length" "2")
 920    (set_attr "cc" "none")])
 921
 922 (define_expand "casesi"
 923   [(match_operand:SI 0 "register_operand" "")
 924    (match_operand:SI 1 "register_operand" "")
 925    (match_operand:SI 2 "register_operand" "")
 926    (match_operand 3 "" "") (match_operand 4 "" "")]
 927   ""
 928   "
 929 {
 930   rtx reg = gen_reg_rtx (SImode);
 931   rtx tableaddress = gen_reg_rtx (SImode);
 932   rtx mem;
 933
 934   /* Subtract the lower bound from the index.  */
 935   emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
 936   /* Compare the result against the number of table entries.  */
 937   emit_insn (gen_cmpsi (reg, operands[2]));
 938   /* Branch to the default label if out of range of the table.  */
 939   emit_jump_insn (gen_bgtu (operands[4]));
 940
 941   /* Shift index for the table array access.  */
 942   emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
 943   /* Load the table address into a pseudo.  */
 944   emit_insn (gen_movsi (tableaddress,
 945                         gen_rtx (LABEL_REF, VOIDmode, operands[3])));
 946   /* Add the table address to the index.  */
 947   emit_insn (gen_addsi3 (reg, reg, tableaddress));
 948   /* Load the table entry.  */
 949   mem = gen_rtx (MEM, CASE_VECTOR_MODE, reg);
 950   RTX_UNCHANGING_P (mem);
 951   if (! TARGET_BIG_SWITCH)
 952     {
 953       rtx reg2 = gen_reg_rtx (HImode);
 954       emit_insn (gen_movhi (reg2, mem));
 955       emit_insn (gen_extendhisi2 (reg, reg2));
 956     }
 957   else
 958     emit_insn (gen_movsi (reg, mem));
 959   /* Add the table address.  */
 960   emit_insn (gen_addsi3 (reg, reg, tableaddress));
 961   /* Branch to the switch label.  */
 962   emit_jump_insn (gen_tablejump (reg, operands[3]));
 963   DONE;
 964 }")
 965
 966 ;; Call subroutine with no return value.
 967
 968 (define_expand "call"
 969   [(call (match_operand:QI 0 "general_operand" "")
 970          (match_operand:SI 1 "general_operand" ""))]
 971   ""
 972   "
 973 {
 974   if (! call_address_operand (XEXP (operands[0], 0))
 975       || TARGET_LONG_CALLS)
 976     XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
 977   if (TARGET_LONG_CALLS)
 978     emit_call_insn (gen_call_internal_long (XEXP (operands[0], 0), operands[1]));
 979   else
 980     emit_call_insn (gen_call_internal_short (XEXP (operands[0], 0), operands[1]));
 981
 982   DONE;
 983 }")
 984
 985 (define_insn "call_internal_short"
 986   [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
 987          (match_operand:SI 1 "general_operand" "g,g"))
 988    (clobber (reg:SI 31))]
 989   "! TARGET_LONG_CALLS"
 990   "@
 991   jarl %0,r31
 992   jarl .+4,r31\\n\tadd 4,r31\\n\tjmp %0"
 993   [(set_attr "length" "4,8")]
 994 )
 995
 996 (define_insn "call_internal_long"
 997   [(call (mem:QI (match_operand:SI 0 "call_address_operand" "S,r"))
 998          (match_operand:SI 1 "general_operand" "g,g"))
 999    (clobber (reg:SI 31))]
1000   "TARGET_LONG_CALLS"
1001   "*
1002   {
1003   if (which_alternative == 0)
1004     {
1005       if (GET_CODE (operands[0]) == REG)
1006         return \"jarl %0,r31\";
1007       else
1008         return \"movhi hi(%0), r0, r11\\n\tmovea lo(%0), r11, r11\\n\tjarl .+4,r31\\n\tadd 4, r31\\n\tjmp r11\";
1009     }
1010   else
1011     return \"jarl .+4,r31\\n\tadd 4,r31\\n\tjmp %0\";
1012   }"
1013   [(set_attr "length" "16,8")]
1014 )
1015
1016 ;; Call subroutine, returning value in operand 0
1017 ;; (which must be a hard register).
1018
1019 (define_expand "call_value"
1020   [(set (match_operand 0 "" "")
1021         (call (match_operand:QI 1 "general_operand" "")
1022               (match_operand:SI 2 "general_operand" "")))]
1023   ""
1024   "
1025 {
1026   if (! call_address_operand (XEXP (operands[1], 0))
1027       || TARGET_LONG_CALLS)
1028     XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
1029   if (TARGET_LONG_CALLS)
1030     emit_call_insn (gen_call_value_internal_long (operands[0],
1031                                                   XEXP (operands[1], 0),
1032                                                   operands[2]));
1033   else
1034     emit_call_insn (gen_call_value_internal_short (operands[0],
1035                                                    XEXP (operands[1], 0),
1036                                                    operands[2]));
1037   DONE;
1038 }")
1039
1040 (define_insn "call_value_internal_short"
1041   [(set (match_operand 0 "" "=r,r")
1042         (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1043               (match_operand:SI 2 "general_operand" "g,g")))
1044    (clobber (reg:SI 31))]
1045   "! TARGET_LONG_CALLS"
1046   "@
1047   jarl %1,r31
1048   jarl .+4,r31\\n\tadd 4,r31\\n\tjmp %1"
1049   [(set_attr "length" "4,8")]
1050 )
1051
1052 (define_insn "call_value_internal_long"
1053   [(set (match_operand 0 "" "=r,r")
1054         (call (mem:QI (match_operand:SI 1 "call_address_operand" "S,r"))
1055               (match_operand:SI 2 "general_operand" "g,g")))
1056    (clobber (reg:SI 31))]
1057   "TARGET_LONG_CALLS"
1058   "*
1059   {
1060   if (which_alternative == 0)
1061     {
1062       if (GET_CODE (operands[1]) == REG)
1063         return \"jarl %1, r31\";
1064       else
1065       /* Reload can generate this pattern... */
1066         return \"movhi hi(%1), r0, r11\\n\tmovea lo(%1), r11, r11\\n\tjarl .+4, r31\\n\tadd 4, r31\\n\tjmp r11\";
1067     }
1068   else
1069     return \"jarl .+4, r31\\n\tadd 4, r31\\n\tjmp %1\";
1070   }"
1071   [(set_attr "length" "16,8")]
1072 )
1073
1074 (define_insn "nop"
1075   [(const_int 0)]
1076   ""
1077   "nop"
1078   [(set_attr "length" "2")
1079    (set_attr "cc" "none")])
1080 \f
1081 ;; ----------------------------------------------------------------------
1082 ;; EXTEND INSTRUCTIONS
1083 ;; ----------------------------------------------------------------------
1084
1085
1086 (define_insn "zero_extendhisi2"
1087   [(set (match_operand:SI 0 "register_operand" "=r")
1088         (zero_extend:SI
1089          (match_operand:HI 1 "register_operand" "r")))]
1090   ""
1091   "andi 65535,%1,%0"
1092   [(set_attr "length" "4")
1093    (set_attr "cc" "set_znv")])
1094
1095
1096 (define_insn "zero_extendqisi2"
1097   [(set (match_operand:SI 0 "register_operand" "=r")
1098         (zero_extend:SI
1099          (match_operand:QI 1 "register_operand" "r")))]
1100   ""
1101   "andi 255,%1,%0"
1102   [(set_attr "length" "4")
1103    (set_attr "cc" "set_znv")])
1104
1105 ;;- sign extension instructions
1106
1107
1108 ;; ??? This is missing a sign extend from memory pattern to match the ld.h
1109 ;; instruction.
1110
1111 (define_expand "extendhisi2"
1112   [(set (match_dup 2)
1113         (ashift:SI (match_operand:HI 1 "register_operand" "")
1114                    (const_int 16)))
1115    (set (match_operand:SI 0 "register_operand" "")
1116        (ashiftrt:SI (match_dup 2)
1117                      (const_int 16)))]
1118   ""
1119   "
1120 {
1121   operands[1] = gen_lowpart (SImode, operands[1]);
1122   operands[2] = gen_reg_rtx (SImode);
1123 }")
1124
1125
1126 ;; ??? This is missing a sign extend from memory pattern to match the ld.b
1127 ;; instruction.
1128
1129 (define_expand "extendqisi2"
1130   [(set (match_dup 2)
1131         (ashift:SI (match_operand:QI 1 "register_operand" "")
1132                    (const_int 24)))
1133    (set (match_operand:SI 0 "register_operand" "")
1134         (ashiftrt:SI (match_dup 2)
1135                      (const_int 24)))]
1136   ""
1137   "
1138 {
1139   operands[1] = gen_lowpart (SImode, operands[1]);
1140   operands[2] = gen_reg_rtx (SImode);
1141 }")
1142 \f
1143 ;; ----------------------------------------------------------------------
1144 ;; SHIFTS
1145 ;; ----------------------------------------------------------------------
1146
1147 (define_insn "ashlsi3"
1148   [(set (match_operand:SI 0 "register_operand" "=r,r")
1149         (ashift:SI
1150          (match_operand:SI 1 "register_operand" "0,0")
1151          (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1152   ""
1153   "@
1154   shl %2,%0
1155   shl %2,%0"
1156   [(set_attr "length" "4,2")
1157    (set_attr "cc" "set_znv")])
1158
1159 (define_insn "lshrsi3"
1160   [(set (match_operand:SI 0 "register_operand" "=r,r")
1161         (lshiftrt:SI
1162          (match_operand:SI 1 "register_operand" "0,0")
1163          (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1164   ""
1165   "@
1166   shr %2,%0
1167   shr %2,%0"
1168   [(set_attr "length" "4,2")
1169    (set_attr "cc" "set_znv")])
1170
1171 (define_insn "ashrsi3"
1172   [(set (match_operand:SI 0 "register_operand" "=r,r")
1173         (ashiftrt:SI
1174          (match_operand:SI 1 "register_operand" "0,0")
1175          (match_operand:SI 2 "nonmemory_operand" "r,N")))]
1176   ""
1177   "@
1178   sar %2,%0
1179   sar %2,%0"
1180   [(set_attr "length" "4,2")
1181    (set_attr "cc" "set_znv")])
1182
1183 ;; ----------------------------------------------------------------------
1184 ;; PROLOGUE/EPILOGUE
1185 ;; ----------------------------------------------------------------------
1186 (define_expand "prologue"
1187   [(const_int 0)]
1188   ""
1189   "expand_prologue (); DONE;")
1190
1191 (define_expand "epilogue"
1192   [(return)]
1193   ""
1194   "
1195 {
1196   /* Try to use the trivial return first.  Else use the
1197      full epilogue.  */
1198   if (0)
1199     emit_jump_insn (gen_return ());
1200   else
1201     expand_epilogue ();
1202   DONE;
1203 }")
1204
1205 (define_insn "return"
1206   [(return)]
1207   "reload_completed && compute_frame_size (get_frame_size (), (long *)0) == 0"
1208   "jmp [r31]"
1209   [(set_attr "length" "2")
1210    (set_attr "cc" "none")])
1211
1212 (define_insn "return_internal"
1213   [(return)
1214    (use (reg:SI 31))]
1215   ""
1216   "jmp [r31]"
1217   [(set_attr "length" "2")
1218    (set_attr "cc" "none")])
1219
1220
1221 \f
1222 ;; ----------------------------------------------------------------------
1223 ;; HELPER INSTRUCTIONS for saving the prologue and epilog registers
1224 ;; ----------------------------------------------------------------------
1225
1226 ;; This pattern will match a stack adjust RTX followed by any number of push
1227 ;; RTXs.  These RTXs will then be turned into a suitable call to a worker
1228 ;; function.
1229
1230
1231 (define_insn ""
1232  [(match_parallel 0 "pattern_is_ok_for_prologue"
1233    [(set (reg:SI 3)
1234          (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1235     (set (mem:SI (plus:SI (reg:SI 3)
1236                            (match_operand:SI 2 "immediate_operand" "i")))
1237          (match_operand:SI 3 "register_is_ok_for_epilogue" "r"))])]
1238  "TARGET_PROLOG_FUNCTION"
1239  "* return construct_save_jarl (operands[0]);
1240  "
1241  [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1242                                      (const_string "16")
1243                                      (const_string "4")))
1244   (set_attr "cc"     "clobber")])
1245
1246 ;; This pattern will match a return RTX followed by any number of pop RTXs
1247 ;; and possible a stack adjustment as well.  These RTXs will be turned into
1248 ;; a suitable call to a worker function.
1249
1250 (define_insn ""
1251 [(match_parallel 0 "pattern_is_ok_for_epilogue"
1252    [(return)
1253     (set (reg:SI 3)
1254          (plus:SI (reg:SI 3) (match_operand:SI 1 "immediate_operand" "i")))
1255     (set (match_operand:SI 2 "register_is_ok_for_epilogue" "r")
1256          (mem:SI (plus:SI (reg:SI 3)
1257                           (match_operand:SI 3 "immediate_operand" "i"))))])]
1258  "TARGET_PROLOG_FUNCTION && TARGET_V850"
1259  "* return construct_restore_jr (operands[0]);
1260  "
1261  [(set (attr "length") (if_then_else (eq_attr "long_calls" "yes")
1262                                      (const_string "12")
1263                                      (const_string "4")))
1264   (set_attr "cc"     "clobber")])
1265
1266 ;; Initialize an interrupt function.  Do not depend on TARGET_PROLOG_FUNCTION.
1267 (define_insn "save_interrupt"
1268   [(set (reg:SI 3) (plus:SI (reg:SI 3) (const_int -16)))
1269    (set (mem:SI (reg:SI 3)) (reg:SI 30))
1270    (set (mem:SI (plus:SI (reg:SI 3) (const_int -4))) (reg:SI 10))
1271    (set (mem:SI (plus:SI (reg:SI 3) (const_int -8))) (reg:SI 4))
1272    (set (mem:SI (plus:SI (reg:SI 3) (const_int -12))) (reg:SI 1))]
1273   "TARGET_V850 && ! TARGET_LONG_CALLS"
1274   "add -16,sp\n\tst.w r10,12[sp]\n\tjarl __save_interrupt,r10"
1275   [(set_attr "length" "12")
1276    (set_attr "cc" "clobber")])
1277
1278 ;; Restore r1, r4, r10, and return from the interrupt
1279 (define_insn "restore_interrupt"
1280   [(return)
1281    (set (reg:SI 3) (plus:SI (reg:SI 3) (const_int 16)))
1282    (set (reg:SI 30) (mem:SI (plus:SI (reg:SI 3) (const_int 12))))
1283    (set (reg:SI 10) (mem:SI (plus:SI (reg:SI 3) (const_int 8))))
1284    (set (reg:SI 4)  (mem:SI (plus:SI (reg:SI 3) (const_int 4))))
1285    (set (reg:SI 1)  (mem:SI (reg:SI 3)))]
1286   ""
1287   "jr __return_interrupt"
1288   [(set_attr "length" "4")
1289    (set_attr "cc" "clobber")])
1290
1291
1292 ;; Save all registers except for the registers saved in save_interrupt when
1293 ;; an interrupt function makes a call.
1294 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1295 ;; all of memory.  This blocks insns from being moved across this point.
1296 ;; This is needed because the rest of the compiler is not ready to handle
1297 ;; insns this complicated.
1298
1299 (define_insn "save_all_interrupt"
1300   [(unspec_volatile [(const_int 0)] 0)]
1301   "TARGET_V850 && ! TARGET_LONG_CALLS"
1302   "jarl __save_all_interrupt,r10"
1303   [(set_attr "length" "4")
1304    (set_attr "cc" "clobber")])
1305
1306
1307 ;; Restore all registers saved when an interrupt function makes a call.
1308 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1309 ;; all of memory.  This blocks insns from being moved across this point.
1310 ;; This is needed because the rest of the compiler is not ready to handle
1311 ;; insns this complicated.
1312
1313 (define_insn "restore_all_interrupt"
1314   [(unspec_volatile [(const_int 0)] 1)]
1315   "TARGET_V850 && ! TARGET_LONG_CALLS"
1316   "jarl __restore_all_interrupt,r10"
1317   [(set_attr "length" "4")
1318    (set_attr "cc" "clobber")])
1319
1320 ;; Save r6-r9 for a variable argument function
1321 (define_insn "save_r6_r9"
1322   [(set (mem:SI (reg:SI 3)) (reg:SI 6))
1323    (set (mem:SI (plus:SI (reg:SI 3) (const_int 4))) (reg:SI 7))
1324    (set (mem:SI (plus:SI (reg:SI 3) (const_int 8))) (reg:SI 8))
1325    (set (mem:SI (plus:SI (reg:SI 3) (const_int 12))) (reg:SI 9))
1326    (clobber (reg:SI 10))]
1327   "TARGET_PROLOG_FUNCTION && ! TARGET_LONG_CALLS"
1328   "jarl __save_r6_r9,r10"
1329   [(set_attr "length" "4")
1330    (set_attr "cc" "clobber")])
1331