1 /* Subroutines for insn-output.c for VAX.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
30 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
35 #include "insn-attr.h"
41 #include "diagnostic-core.h"
44 #include "tm-constrs.h"
47 #include "target-def.h"
49 static void vax_option_override (void);
50 static bool vax_legitimate_address_p (enum machine_mode
, rtx
, bool);
51 static void vax_file_start (void);
52 static void vax_init_libfuncs (void);
53 static void vax_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
55 static int vax_address_cost_1 (rtx
);
56 static int vax_address_cost (rtx
, enum machine_mode
, addr_space_t
, bool);
57 static bool vax_rtx_costs (rtx
, int, int, int, int *, bool);
58 static rtx
vax_function_arg (cumulative_args_t
, enum machine_mode
,
60 static void vax_function_arg_advance (cumulative_args_t
, enum machine_mode
,
62 static rtx
vax_struct_value_rtx (tree
, int);
63 static rtx
vax_builtin_setjmp_frame_value (void);
64 static void vax_asm_trampoline_template (FILE *);
65 static void vax_trampoline_init (rtx
, tree
, rtx
);
66 static int vax_return_pops_args (tree
, tree
, int);
67 static bool vax_mode_dependent_address_p (const_rtx
, addr_space_t
);
69 /* Initialize the GCC target structure. */
70 #undef TARGET_ASM_ALIGNED_HI_OP
71 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
73 #undef TARGET_ASM_FILE_START
74 #define TARGET_ASM_FILE_START vax_file_start
75 #undef TARGET_ASM_FILE_START_APP_OFF
76 #define TARGET_ASM_FILE_START_APP_OFF true
78 #undef TARGET_INIT_LIBFUNCS
79 #define TARGET_INIT_LIBFUNCS vax_init_libfuncs
81 #undef TARGET_ASM_OUTPUT_MI_THUNK
82 #define TARGET_ASM_OUTPUT_MI_THUNK vax_output_mi_thunk
83 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
84 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
86 #undef TARGET_RTX_COSTS
87 #define TARGET_RTX_COSTS vax_rtx_costs
88 #undef TARGET_ADDRESS_COST
89 #define TARGET_ADDRESS_COST vax_address_cost
91 #undef TARGET_PROMOTE_PROTOTYPES
92 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
94 #undef TARGET_FUNCTION_ARG
95 #define TARGET_FUNCTION_ARG vax_function_arg
96 #undef TARGET_FUNCTION_ARG_ADVANCE
97 #define TARGET_FUNCTION_ARG_ADVANCE vax_function_arg_advance
99 #undef TARGET_STRUCT_VALUE_RTX
100 #define TARGET_STRUCT_VALUE_RTX vax_struct_value_rtx
102 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
103 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE vax_builtin_setjmp_frame_value
105 #undef TARGET_LEGITIMATE_ADDRESS_P
106 #define TARGET_LEGITIMATE_ADDRESS_P vax_legitimate_address_p
107 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
108 #define TARGET_MODE_DEPENDENT_ADDRESS_P vax_mode_dependent_address_p
110 #undef TARGET_FRAME_POINTER_REQUIRED
111 #define TARGET_FRAME_POINTER_REQUIRED hook_bool_void_true
113 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
114 #define TARGET_ASM_TRAMPOLINE_TEMPLATE vax_asm_trampoline_template
115 #undef TARGET_TRAMPOLINE_INIT
116 #define TARGET_TRAMPOLINE_INIT vax_trampoline_init
117 #undef TARGET_RETURN_POPS_ARGS
118 #define TARGET_RETURN_POPS_ARGS vax_return_pops_args
120 #undef TARGET_OPTION_OVERRIDE
121 #define TARGET_OPTION_OVERRIDE vax_option_override
123 struct gcc_target targetm
= TARGET_INITIALIZER
;
125 /* Set global variables as needed for the options enabled. */
128 vax_option_override (void)
130 /* We're VAX floating point, not IEEE floating point. */
132 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
134 #ifdef SUBTARGET_OVERRIDE_OPTIONS
135 SUBTARGET_OVERRIDE_OPTIONS
;
140 vax_add_reg_cfa_offset (rtx insn
, int offset
, rtx src
)
144 x
= plus_constant (Pmode
, frame_pointer_rtx
, offset
);
145 x
= gen_rtx_MEM (SImode
, x
);
146 x
= gen_rtx_SET (VOIDmode
, x
, src
);
147 add_reg_note (insn
, REG_CFA_OFFSET
, x
);
150 /* Generate the assembly code for function entry. FILE is a stdio
151 stream to output the code to. SIZE is an int: how many units of
152 temporary storage to allocate.
154 Refer to the array `regs_ever_live' to determine which registers to
155 save; `regs_ever_live[I]' is nonzero if register number I is ever
156 used in the function. This function is responsible for knowing
157 which registers should not be saved even if used. */
160 vax_expand_prologue (void)
167 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
168 if (df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
171 insn
= emit_insn (gen_procedure_entry_mask (GEN_INT (mask
)));
172 RTX_FRAME_RELATED_P (insn
) = 1;
174 /* The layout of the CALLG/S stack frame is follows:
179 ... Registers saved as specified by MASK
189 The rest of the prologue will adjust the SP for the local frame. */
191 vax_add_reg_cfa_offset (insn
, 4, arg_pointer_rtx
);
192 vax_add_reg_cfa_offset (insn
, 8, frame_pointer_rtx
);
193 vax_add_reg_cfa_offset (insn
, 12, pc_rtx
);
196 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
197 if (mask
& (1 << regno
))
199 vax_add_reg_cfa_offset (insn
, offset
, gen_rtx_REG (SImode
, regno
));
203 /* Because add_reg_note pushes the notes, adding this last means that
204 it will be processed first. This is required to allow the other
205 notes be interpreted properly. */
206 add_reg_note (insn
, REG_CFA_DEF_CFA
,
207 plus_constant (Pmode
, frame_pointer_rtx
, offset
));
209 /* Allocate the local stack frame. */
210 size
= get_frame_size ();
211 size
-= STARTING_FRAME_OFFSET
;
212 emit_insn (gen_addsi3 (stack_pointer_rtx
,
213 stack_pointer_rtx
, GEN_INT (-size
)));
215 /* Do not allow instructions referencing local stack memory to be
216 scheduled before the frame is allocated. This is more pedantic
217 than anything else, given that VAX does not currently have a
218 scheduling description. */
219 emit_insn (gen_blockage ());
222 /* When debugging with stabs, we want to output an extra dummy label
223 so that gas can distinguish between D_float and G_float prior to
224 processing the .stabs directive identifying type double. */
226 vax_file_start (void)
228 default_file_start ();
230 if (write_symbols
== DBX_DEBUG
)
231 fprintf (asm_out_file
, "___vax_%c_doubles:\n", ASM_DOUBLE_CHAR
);
234 /* We can use the BSD C library routines for the libgcc calls that are
235 still generated, since that's what they boil down to anyways. When
236 ELF, avoid the user's namespace. */
239 vax_init_libfuncs (void)
241 if (TARGET_BSD_DIVMOD
)
243 set_optab_libfunc (udiv_optab
, SImode
, TARGET_ELF
? "*__udiv" : "*udiv");
244 set_optab_libfunc (umod_optab
, SImode
, TARGET_ELF
? "*__urem" : "*urem");
248 /* This is like nonimmediate_operand with a restriction on the type of MEM. */
251 split_quadword_operands (rtx insn
, enum rtx_code code
, rtx
* operands
,
256 for (i
= 0; i
< n
; i
++)
259 for (i
= 0; i
< n
; i
++)
261 if (MEM_P (operands
[i
])
262 && (GET_CODE (XEXP (operands
[i
], 0)) == PRE_DEC
263 || GET_CODE (XEXP (operands
[i
], 0)) == POST_INC
))
265 rtx addr
= XEXP (operands
[i
], 0);
266 operands
[i
] = low
[i
] = gen_rtx_MEM (SImode
, addr
);
268 else if (optimize_size
&& MEM_P (operands
[i
])
269 && REG_P (XEXP (operands
[i
], 0))
270 && (code
!= MINUS
|| operands
[1] != const0_rtx
)
271 && find_regno_note (insn
, REG_DEAD
,
272 REGNO (XEXP (operands
[i
], 0))))
274 low
[i
] = gen_rtx_MEM (SImode
,
275 gen_rtx_POST_INC (Pmode
,
276 XEXP (operands
[i
], 0)));
277 operands
[i
] = gen_rtx_MEM (SImode
, XEXP (operands
[i
], 0));
281 low
[i
] = operand_subword (operands
[i
], 0, 0, DImode
);
282 operands
[i
] = operand_subword (operands
[i
], 1, 0, DImode
);
288 print_operand_address (FILE * file
, rtx addr
)
291 rtx reg1
, breg
, ireg
;
295 switch (GET_CODE (addr
))
299 addr
= XEXP (addr
, 0);
303 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
307 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
311 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
315 /* There can be either two or three things added here. One must be a
316 REG. One can be either a REG or a MULT of a REG and an appropriate
317 constant, and the third can only be a constant or a MEM.
319 We get these two or three things and put the constant or MEM in
320 OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have
321 a register and can't tell yet if it is a base or index register,
324 reg1
= 0; ireg
= 0; breg
= 0; offset
= 0;
326 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
327 || MEM_P (XEXP (addr
, 0)))
329 offset
= XEXP (addr
, 0);
330 addr
= XEXP (addr
, 1);
332 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
333 || MEM_P (XEXP (addr
, 1)))
335 offset
= XEXP (addr
, 1);
336 addr
= XEXP (addr
, 0);
338 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
340 ireg
= XEXP (addr
, 1);
341 addr
= XEXP (addr
, 0);
343 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
345 ireg
= XEXP (addr
, 0);
346 addr
= XEXP (addr
, 1);
348 else if (REG_P (XEXP (addr
, 1)))
350 reg1
= XEXP (addr
, 1);
351 addr
= XEXP (addr
, 0);
353 else if (REG_P (XEXP (addr
, 0)))
355 reg1
= XEXP (addr
, 0);
356 addr
= XEXP (addr
, 1);
368 else if (GET_CODE (addr
) == MULT
)
372 gcc_assert (GET_CODE (addr
) == PLUS
);
373 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
374 || MEM_P (XEXP (addr
, 0)))
378 if (CONST_INT_P (offset
))
379 offset
= plus_constant (Pmode
, XEXP (addr
, 0),
383 gcc_assert (CONST_INT_P (XEXP (addr
, 0)));
384 offset
= plus_constant (Pmode
, offset
,
385 INTVAL (XEXP (addr
, 0)));
388 offset
= XEXP (addr
, 0);
390 else if (REG_P (XEXP (addr
, 0)))
393 ireg
= reg1
, breg
= XEXP (addr
, 0), reg1
= 0;
395 reg1
= XEXP (addr
, 0);
399 gcc_assert (GET_CODE (XEXP (addr
, 0)) == MULT
);
401 ireg
= XEXP (addr
, 0);
404 if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
405 || MEM_P (XEXP (addr
, 1)))
409 if (CONST_INT_P (offset
))
410 offset
= plus_constant (Pmode
, XEXP (addr
, 1),
414 gcc_assert (CONST_INT_P (XEXP (addr
, 1)));
415 offset
= plus_constant (Pmode
, offset
,
416 INTVAL (XEXP (addr
, 1)));
419 offset
= XEXP (addr
, 1);
421 else if (REG_P (XEXP (addr
, 1)))
424 ireg
= reg1
, breg
= XEXP (addr
, 1), reg1
= 0;
426 reg1
= XEXP (addr
, 1);
430 gcc_assert (GET_CODE (XEXP (addr
, 1)) == MULT
);
432 ireg
= XEXP (addr
, 1);
436 /* If REG1 is nonzero, figure out if it is a base or index register. */
440 || (flag_pic
&& GET_CODE (addr
) == SYMBOL_REF
)
443 || (flag_pic
&& symbolic_operand (offset
, SImode
)))))
454 if (flag_pic
&& symbolic_operand (offset
, SImode
))
459 output_operand_lossage ("symbol used with both base and indexed registers");
462 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
463 if (flag_pic
> 1 && GET_CODE (offset
) == CONST
464 && GET_CODE (XEXP (XEXP (offset
, 0), 0)) == SYMBOL_REF
465 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (offset
, 0), 0)))
468 output_operand_lossage ("symbol with offset used in PIC mode");
472 /* symbol(reg) isn't PIC, but symbol[reg] is. */
481 output_address (offset
);
485 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
489 if (GET_CODE (ireg
) == MULT
)
490 ireg
= XEXP (ireg
, 0);
491 gcc_assert (REG_P (ireg
));
492 fprintf (file
, "[%s]", reg_names
[REGNO (ireg
)]);
497 output_addr_const (file
, addr
);
502 print_operand (FILE *file
, rtx x
, int code
)
505 fputc (ASM_DOUBLE_CHAR
, file
);
506 else if (code
== '|')
507 fputs (REGISTER_PREFIX
, file
);
508 else if (code
== 'c')
509 fputs (cond_name (x
), file
);
510 else if (code
== 'C')
511 fputs (rev_cond_name (x
), file
);
512 else if (code
== 'D' && CONST_INT_P (x
) && INTVAL (x
) < 0)
513 fprintf (file
, "$" NEG_HWI_PRINT_HEX16
, INTVAL (x
));
514 else if (code
== 'P' && CONST_INT_P (x
))
515 fprintf (file
, "$" HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
) + 1);
516 else if (code
== 'N' && CONST_INT_P (x
))
517 fprintf (file
, "$" HOST_WIDE_INT_PRINT_DEC
, ~ INTVAL (x
));
518 /* rotl instruction cannot deal with negative arguments. */
519 else if (code
== 'R' && CONST_INT_P (x
))
520 fprintf (file
, "$" HOST_WIDE_INT_PRINT_DEC
, 32 - INTVAL (x
));
521 else if (code
== 'H' && CONST_INT_P (x
))
522 fprintf (file
, "$%d", (int) (0xffff & ~ INTVAL (x
)));
523 else if (code
== 'h' && CONST_INT_P (x
))
524 fprintf (file
, "$%d", (short) - INTVAL (x
));
525 else if (code
== 'B' && CONST_INT_P (x
))
526 fprintf (file
, "$%d", (int) (0xff & ~ INTVAL (x
)));
527 else if (code
== 'b' && CONST_INT_P (x
))
528 fprintf (file
, "$%d", (int) (0xff & - INTVAL (x
)));
529 else if (code
== 'M' && CONST_INT_P (x
))
530 fprintf (file
, "$%d", ~((1 << INTVAL (x
)) - 1));
531 else if (code
== 'x' && CONST_INT_P (x
))
532 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
534 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
536 output_address (XEXP (x
, 0));
537 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == SFmode
)
540 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (x
),
541 sizeof (dstr
), 0, 1);
542 fprintf (file
, "$0f%s", dstr
);
544 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) == DFmode
)
547 real_to_decimal (dstr
, CONST_DOUBLE_REAL_VALUE (x
),
548 sizeof (dstr
), 0, 1);
549 fprintf (file
, "$0%c%s", ASM_DOUBLE_CHAR
, dstr
);
553 if (flag_pic
> 1 && symbolic_operand (x
, SImode
))
556 output_operand_lossage ("symbol used as immediate operand");
559 output_addr_const (file
, x
);
566 switch (GET_CODE (op
))
595 rev_cond_name (rtx op
)
597 switch (GET_CODE (op
))
626 vax_float_literal (rtx c
)
628 enum machine_mode mode
;
629 REAL_VALUE_TYPE r
, s
;
632 if (GET_CODE (c
) != CONST_DOUBLE
)
637 if (c
== const_tiny_rtx
[(int) mode
][0]
638 || c
== const_tiny_rtx
[(int) mode
][1]
639 || c
== const_tiny_rtx
[(int) mode
][2])
642 REAL_VALUE_FROM_CONST_DOUBLE (r
, c
);
644 for (i
= 0; i
< 7; i
++)
648 REAL_VALUE_FROM_INT (s
, x
, 0, mode
);
650 if (REAL_VALUES_EQUAL (r
, s
))
652 ok
= exact_real_inverse (mode
, &s
);
654 if (REAL_VALUES_EQUAL (r
, s
))
661 /* Return the cost in cycles of a memory address, relative to register
664 Each of the following adds the indicated number of cycles:
668 1 - indexing and/or offset(register)
673 vax_address_cost_1 (rtx addr
)
675 int reg
= 0, indexed
= 0, indir
= 0, offset
= 0, predec
= 0;
676 rtx plus_op0
= 0, plus_op1
= 0;
678 switch (GET_CODE (addr
))
688 indexed
= 1; /* 2 on VAX 2 */
691 /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */
693 offset
= (unsigned HOST_WIDE_INT
)(INTVAL(addr
)+128) > 256;
697 offset
= 1; /* 2 on VAX 2 */
699 case LABEL_REF
: /* this is probably a byte offset from the pc */
705 plus_op1
= XEXP (addr
, 0);
707 plus_op0
= XEXP (addr
, 0);
708 addr
= XEXP (addr
, 1);
711 indir
= 2; /* 3 on VAX 2 */
712 addr
= XEXP (addr
, 0);
718 /* Up to 3 things can be added in an address. They are stored in
719 plus_op0, plus_op1, and addr. */
733 /* Indexing and register+offset can both be used (except on a VAX 2)
734 without increasing execution time over either one alone. */
735 if (reg
&& indexed
&& offset
)
736 return reg
+ indir
+ offset
+ predec
;
737 return reg
+ indexed
+ indir
+ offset
+ predec
;
741 vax_address_cost (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
,
742 addr_space_t as ATTRIBUTE_UNUSED
,
743 bool speed ATTRIBUTE_UNUSED
)
745 return (1 + (REG_P (x
) ? 0 : vax_address_cost_1 (x
)));
748 /* Cost of an expression on a VAX. This version has costs tuned for the
749 CVAX chip (found in the VAX 3 series) with comments for variations on
752 FIXME: The costs need review, particularly for TRUNCATE, FLOAT_EXTEND
753 and FLOAT_TRUNCATE. We need a -mcpu option to allow provision of
754 costs on a per cpu basis. */
757 vax_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
758 int *total
, bool speed ATTRIBUTE_UNUSED
)
760 enum machine_mode mode
= GET_MODE (x
);
761 int i
= 0; /* may be modified in switch */
762 const char *fmt
= GET_RTX_FORMAT (code
); /* may be modified in switch */
766 /* On a VAX, constants from 0..63 are cheap because they can use the
767 1 byte literal constant format. Compare to -1 should be made cheap
768 so that decrement-and-branch insns can be formed more easily (if
769 the value -1 is copied to a register some decrement-and-branch
770 patterns will not match). */
777 if (outer_code
== AND
)
779 *total
= ((unsigned HOST_WIDE_INT
) ~INTVAL (x
) <= 077) ? 1 : 2;
782 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) <= 077
783 || (outer_code
== COMPARE
785 || ((outer_code
== PLUS
|| outer_code
== MINUS
)
786 && (unsigned HOST_WIDE_INT
) -INTVAL (x
) <= 077))
800 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
801 *total
= vax_float_literal (x
) ? 5 : 8;
803 *total
= ((CONST_DOUBLE_HIGH (x
) == 0
804 && (unsigned HOST_WIDE_INT
) CONST_DOUBLE_LOW (x
) < 64)
805 || (outer_code
== PLUS
806 && CONST_DOUBLE_HIGH (x
) == -1
807 && (unsigned HOST_WIDE_INT
)-CONST_DOUBLE_LOW (x
) < 64))
813 return true; /* Implies register operand. */
817 return true; /* Implies register operand. */
823 *total
= 16; /* 4 on VAX 9000 */
826 *total
= 9; /* 4 on VAX 9000, 12 on VAX 2 */
829 *total
= 16; /* 6 on VAX 9000, 28 on VAX 2 */
834 *total
= 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */
837 *total
= MAX_COST
; /* Mode is not supported. */
845 *total
= MAX_COST
; /* Mode is not supported. */
853 *total
= 30; /* Highly variable. */
854 else if (mode
== DFmode
)
855 /* divide takes 28 cycles if the result is not zero, 13 otherwise */
858 *total
= 11; /* 25 on VAX 2 */
868 *total
= MAX_COST
; /* Mode is not supported. */
875 *total
= (6 /* 4 on VAX 9000 */
876 + (mode
== DFmode
) + (GET_MODE (XEXP (x
, 0)) != SImode
));
880 *total
= 7; /* 17 on VAX 2 */
889 *total
= 10; /* 6 on VAX 9000 */
894 *total
= 6; /* 5 on VAX 2, 4 on VAX 9000 */
895 if (CONST_INT_P (XEXP (x
, 1)))
896 fmt
= "e"; /* all constant rotate counts are short */
901 *total
= (mode
== DFmode
) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */
902 /* Small integer operands can use subl2 and addl2. */
903 if ((CONST_INT_P (XEXP (x
, 1)))
904 && (unsigned HOST_WIDE_INT
)(INTVAL (XEXP (x
, 1)) + 63) < 127)
914 /* AND is special because the first operand is complemented. */
916 if (CONST_INT_P (XEXP (x
, 0)))
918 if ((unsigned HOST_WIDE_INT
)~INTVAL (XEXP (x
, 0)) > 63)
928 else if (mode
== SFmode
)
930 else if (mode
== DImode
)
946 if (mode
== DImode
|| mode
== DFmode
)
947 *total
= 5; /* 7 on VAX 2 */
949 *total
= 3; /* 4 on VAX 2 */
951 if (!REG_P (x
) && GET_CODE (x
) != POST_INC
)
952 *total
+= vax_address_cost_1 (x
);
958 *total
= 3; /* FIXME: Costs need to be checked */
965 /* Now look inside the expression. Operands which are not registers or
966 short constants add to the cost.
968 FMT and I may have been adjusted in the switch above for instructions
969 which require special handling. */
971 while (*fmt
++ == 'e')
973 rtx op
= XEXP (x
, i
);
976 code
= GET_CODE (op
);
978 /* A NOT is likely to be found as the first operand of an AND
979 (in which case the relevant cost is of the operand inside
980 the not) and not likely to be found anywhere else. */
982 op
= XEXP (op
, 0), code
= GET_CODE (op
);
987 if ((unsigned HOST_WIDE_INT
)INTVAL (op
) > 63
988 && GET_MODE (x
) != QImode
)
989 *total
+= 1; /* 2 on VAX 2 */
994 *total
+= 1; /* 2 on VAX 2 */
997 if (GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
999 /* Registers are faster than floating point constants -- even
1000 those constants which can be encoded in a single byte. */
1001 if (vax_float_literal (op
))
1004 *total
+= (GET_MODE (x
) == DFmode
) ? 3 : 2;
1008 if (CONST_DOUBLE_HIGH (op
) != 0
1009 || (unsigned HOST_WIDE_INT
)CONST_DOUBLE_LOW (op
) > 63)
1014 *total
+= 1; /* 2 on VAX 2 */
1015 if (!REG_P (XEXP (op
, 0)))
1016 *total
+= vax_address_cost_1 (XEXP (op
, 0));
1029 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
1030 Used for C++ multiple inheritance.
1031 .mask ^m<r2,r3,r4,r5,r6,r7,r8,r9,r10,r11> #conservative entry mask
1032 addl2 $DELTA, 4(ap) #adjust first argument
1033 jmp FUNCTION+2 #jump beyond FUNCTION's entry mask
1037 vax_output_mi_thunk (FILE * file
,
1038 tree thunk ATTRIBUTE_UNUSED
,
1039 HOST_WIDE_INT delta
,
1040 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1043 fprintf (file
, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC
, delta
);
1044 asm_fprintf (file
, ",4(%Rap)\n");
1045 fprintf (file
, "\tjmp ");
1046 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
1047 fprintf (file
, "+2\n");
1051 vax_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
1052 int incoming ATTRIBUTE_UNUSED
)
1054 return gen_rtx_REG (Pmode
, VAX_STRUCT_VALUE_REGNUM
);
1058 vax_builtin_setjmp_frame_value (void)
1060 return hard_frame_pointer_rtx
;
1063 /* Worker function for NOTICE_UPDATE_CC. */
1066 vax_notice_update_cc (rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
1068 if (GET_CODE (exp
) == SET
)
1070 if (GET_CODE (SET_SRC (exp
)) == CALL
)
1072 else if (GET_CODE (SET_DEST (exp
)) != ZERO_EXTRACT
1073 && GET_CODE (SET_DEST (exp
)) != PC
)
1075 cc_status
.flags
= 0;
1076 /* The integer operations below don't set carry or
1077 set it in an incompatible way. That's ok though
1078 as the Z bit is all we need when doing unsigned
1079 comparisons on the result of these insns (since
1080 they're always with 0). Set CC_NO_OVERFLOW to
1081 generate the correct unsigned branches. */
1082 switch (GET_CODE (SET_SRC (exp
)))
1085 if (GET_MODE_CLASS (GET_MODE (exp
)) == MODE_FLOAT
)
1093 cc_status
.flags
= CC_NO_OVERFLOW
;
1098 cc_status
.value1
= SET_DEST (exp
);
1099 cc_status
.value2
= SET_SRC (exp
);
1102 else if (GET_CODE (exp
) == PARALLEL
1103 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
1105 if (GET_CODE (SET_SRC (XVECEXP (exp
, 0, 0))) == CALL
)
1107 else if (GET_CODE (SET_DEST (XVECEXP (exp
, 0, 0))) != PC
)
1109 cc_status
.flags
= 0;
1110 cc_status
.value1
= SET_DEST (XVECEXP (exp
, 0, 0));
1111 cc_status
.value2
= SET_SRC (XVECEXP (exp
, 0, 0));
1114 /* PARALLELs whose first element sets the PC are aob,
1115 sob insns. They do change the cc's. */
1120 if (cc_status
.value1
&& REG_P (cc_status
.value1
)
1122 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1123 cc_status
.value2
= 0;
1124 if (cc_status
.value1
&& MEM_P (cc_status
.value1
)
1126 && MEM_P (cc_status
.value2
))
1127 cc_status
.value2
= 0;
1128 /* Actual condition, one line up, should be that value2's address
1129 depends on value1, but that is too much of a pain. */
1132 /* Output integer move instructions. */
1135 vax_output_int_move (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
,
1136 enum machine_mode mode
)
1139 const char *pattern_hi
, *pattern_lo
;
1144 if (operands
[1] == const0_rtx
)
1146 if (TARGET_QMATH
&& optimize_size
1147 && (CONST_INT_P (operands
[1])
1148 || GET_CODE (operands
[1]) == CONST_DOUBLE
))
1150 unsigned HOST_WIDE_INT hval
, lval
;
1153 if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1155 gcc_assert (HOST_BITS_PER_WIDE_INT
!= 64);
1157 /* Make sure only the low 32 bits are valid. */
1158 lval
= CONST_DOUBLE_LOW (operands
[1]) & 0xffffffff;
1159 hval
= CONST_DOUBLE_HIGH (operands
[1]) & 0xffffffff;
1163 lval
= INTVAL (operands
[1]);
1167 /* Here we see if we are trying to see if the 64bit value is really
1168 a 6bit shifted some arbitrary amount. If so, we can use ashq to
1169 shift it to the correct value saving 7 bytes (1 addr-mode-byte +
1170 8 bytes - 1 shift byte - 1 short literal byte. */
1172 && (n
= exact_log2 (lval
& (- lval
))) != -1
1173 && (lval
>> n
) < 64)
1177 /* On 32bit platforms, if the 6bits didn't overflow into the
1178 upper 32bit value that value better be 0. If we have
1179 overflowed, make sure it wasn't too much. */
1180 if (HOST_BITS_PER_WIDE_INT
== 32 && hval
!= 0)
1182 if (n
<= 26 || hval
>= ((unsigned)1 << (n
- 26)))
1183 n
= 0; /* failure */
1185 lval
|= hval
<< (32 - n
);
1187 /* If n is 0, then ashq is not the best way to emit this. */
1190 operands
[1] = GEN_INT (lval
);
1191 operands
[2] = GEN_INT (n
);
1192 return "ashq %2,%D1,%0";
1194 #if HOST_BITS_PER_WIDE_INT == 32
1196 /* On 32bit platforms, if the low 32bit value is 0, checkout the
1197 upper 32bit value. */
1199 && (n
= exact_log2 (hval
& (- hval
)) - 1) != -1
1200 && (hval
>> n
) < 64)
1202 operands
[1] = GEN_INT (hval
>> n
);
1203 operands
[2] = GEN_INT (n
+ 32);
1204 return "ashq %2,%D1,%0";
1210 && (!MEM_P (operands
[0])
1211 || GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
1212 || GET_CODE (XEXP (operands
[0], 0)) == POST_INC
1213 || !illegal_addsub_di_memory_operand (operands
[0], DImode
))
1214 && ((CONST_INT_P (operands
[1])
1215 && (unsigned HOST_WIDE_INT
) INTVAL (operands
[1]) >= 64)
1216 || GET_CODE (operands
[1]) == CONST_DOUBLE
))
1218 hi
[0] = operands
[0];
1219 hi
[1] = operands
[1];
1221 split_quadword_operands (insn
, SET
, hi
, lo
, 2);
1223 pattern_lo
= vax_output_int_move (NULL
, lo
, SImode
);
1224 pattern_hi
= vax_output_int_move (NULL
, hi
, SImode
);
1226 /* The patterns are just movl/movl or pushl/pushl then a movq will
1227 be shorter (1 opcode byte + 1 addrmode byte + 8 immediate value
1228 bytes .vs. 2 opcode bytes + 2 addrmode bytes + 8 immediate value
1230 if ((!strncmp (pattern_lo
, "movl", 4)
1231 && !strncmp (pattern_hi
, "movl", 4))
1232 || (!strncmp (pattern_lo
, "pushl", 5)
1233 && !strncmp (pattern_hi
, "pushl", 5)))
1234 return "movq %1,%0";
1236 if (MEM_P (operands
[0])
1237 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
)
1239 output_asm_insn (pattern_hi
, hi
);
1240 operands
[0] = lo
[0];
1241 operands
[1] = lo
[1];
1242 operands
[2] = lo
[2];
1247 output_asm_insn (pattern_lo
, lo
);
1248 operands
[0] = hi
[0];
1249 operands
[1] = hi
[1];
1250 operands
[2] = hi
[2];
1254 return "movq %1,%0";
1257 if (symbolic_operand (operands
[1], SImode
))
1259 if (push_operand (operands
[0], SImode
))
1260 return "pushab %a1";
1261 return "movab %a1,%0";
1264 if (operands
[1] == const0_rtx
)
1266 if (push_operand (operands
[1], SImode
))
1271 if (CONST_INT_P (operands
[1])
1272 && (unsigned HOST_WIDE_INT
) INTVAL (operands
[1]) >= 64)
1274 HOST_WIDE_INT i
= INTVAL (operands
[1]);
1276 if ((unsigned HOST_WIDE_INT
)(~i
) < 64)
1277 return "mcoml %N1,%0";
1278 if ((unsigned HOST_WIDE_INT
)i
< 0x100)
1279 return "movzbl %1,%0";
1280 if (i
>= -0x80 && i
< 0)
1281 return "cvtbl %1,%0";
1283 && (n
= exact_log2 (i
& (-i
))) != -1
1284 && ((unsigned HOST_WIDE_INT
)i
>> n
) < 64)
1286 operands
[1] = GEN_INT ((unsigned HOST_WIDE_INT
)i
>> n
);
1287 operands
[2] = GEN_INT (n
);
1288 return "ashl %2,%1,%0";
1290 if ((unsigned HOST_WIDE_INT
)i
< 0x10000)
1291 return "movzwl %1,%0";
1292 if (i
>= -0x8000 && i
< 0)
1293 return "cvtwl %1,%0";
1295 if (push_operand (operands
[0], SImode
))
1297 return "movl %1,%0";
1300 if (CONST_INT_P (operands
[1]))
1302 HOST_WIDE_INT i
= INTVAL (operands
[1]);
1305 else if ((unsigned HOST_WIDE_INT
)i
< 64)
1306 return "movw %1,%0";
1307 else if ((unsigned HOST_WIDE_INT
)~i
< 64)
1308 return "mcomw %H1,%0";
1309 else if ((unsigned HOST_WIDE_INT
)i
< 256)
1310 return "movzbw %1,%0";
1311 else if (i
>= -0x80 && i
< 0)
1312 return "cvtbw %1,%0";
1314 return "movw %1,%0";
1317 if (CONST_INT_P (operands
[1]))
1319 HOST_WIDE_INT i
= INTVAL (operands
[1]);
1322 else if ((unsigned HOST_WIDE_INT
)~i
< 64)
1323 return "mcomb %B1,%0";
1325 return "movb %1,%0";
1332 /* Output integer add instructions.
1334 The space-time-opcode tradeoffs for addition vary by model of VAX.
1336 On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
1337 but it not faster on other models.
1339 "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
1340 faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if
1341 a register is used in an address too soon after it is set.
1342 Compromise by using movab only when it is shorter than the add
1343 or the base register in the address is one of sp, ap, and fp,
1344 which are not modified very often. */
1347 vax_output_int_add (rtx insn
, rtx
*operands
, enum machine_mode mode
)
1354 const char *pattern
;
1358 if (TARGET_QMATH
&& 0)
1361 split_quadword_operands (insn
, PLUS
, operands
, low
, 3);
1365 gcc_assert (rtx_equal_p (operands
[0], operands
[1]));
1366 #ifdef NO_EXTERNAL_INDIRECT_ADDRESSS
1367 gcc_assert (!flag_pic
|| !external_memory_operand (low
[2], SImode
));
1368 gcc_assert (!flag_pic
|| !external_memory_operand (low
[0], SImode
));
1371 /* No reason to add a 0 to the low part and thus no carry, so just
1372 emit the appropriate add/sub instruction. */
1373 if (low
[2] == const0_rtx
)
1374 return vax_output_int_add (NULL
, operands
, SImode
);
1376 /* Are we doing addition or subtraction? */
1377 sub
= CONST_INT_P (operands
[2]) && INTVAL (operands
[2]) < 0;
1379 /* We can't use vax_output_int_add since some the patterns don't
1380 modify the carry bit. */
1383 if (low
[2] == constm1_rtx
)
1384 pattern
= "decl %0";
1386 pattern
= "subl2 $%n2,%0";
1390 if (low
[2] == const1_rtx
)
1391 pattern
= "incl %0";
1393 pattern
= "addl2 %2,%0";
1395 output_asm_insn (pattern
, low
);
1397 /* In 2's complement, -n = ~n + 1. Since we are dealing with
1398 two 32bit parts, we complement each and then add one to
1399 low part. We know that the low part can't overflow since
1400 it's value can never be 0. */
1402 return "sbwc %N2,%0";
1403 return "adwc %2,%0";
1406 /* Add low parts. */
1407 if (rtx_equal_p (operands
[0], operands
[1]))
1409 if (low
[2] == const0_rtx
)
1410 /* Should examine operand, punt if not POST_INC. */
1411 pattern
= "tstl %0", carry
= 0;
1412 else if (low
[2] == const1_rtx
)
1413 pattern
= "incl %0";
1415 pattern
= "addl2 %2,%0";
1419 if (low
[2] == const0_rtx
)
1420 pattern
= "movl %1,%0", carry
= 0;
1422 pattern
= "addl3 %2,%1,%0";
1425 output_asm_insn (pattern
, low
);
1427 /* If CARRY is 0, we don't have any carry value to worry about. */
1428 return get_insn_template (CODE_FOR_addsi3
, insn
);
1429 /* %0 = C + %1 + %2 */
1430 if (!rtx_equal_p (operands
[0], operands
[1]))
1431 output_asm_insn ((operands
[1] == const0_rtx
1433 : "movl %1,%0"), operands
);
1434 return "adwc %2,%0";
1438 if (rtx_equal_p (operands
[0], operands
[1]))
1440 if (operands
[2] == const1_rtx
)
1442 if (operands
[2] == constm1_rtx
)
1444 if (CONST_INT_P (operands
[2])
1445 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1446 return "subl2 $%n2,%0";
1447 if (CONST_INT_P (operands
[2])
1448 && (unsigned HOST_WIDE_INT
) INTVAL (operands
[2]) >= 64
1449 && REG_P (operands
[1])
1450 && ((INTVAL (operands
[2]) < 32767 && INTVAL (operands
[2]) > -32768)
1451 || REGNO (operands
[1]) > 11))
1452 return "movab %c2(%1),%0";
1453 if (REG_P (operands
[0]) && symbolic_operand (operands
[2], SImode
))
1454 return "movab %a2[%0],%0";
1455 return "addl2 %2,%0";
1458 if (rtx_equal_p (operands
[0], operands
[2]))
1460 if (REG_P (operands
[0]) && symbolic_operand (operands
[1], SImode
))
1461 return "movab %a1[%0],%0";
1462 return "addl2 %1,%0";
1465 if (CONST_INT_P (operands
[2])
1466 && INTVAL (operands
[2]) < 32767
1467 && INTVAL (operands
[2]) > -32768
1468 && REG_P (operands
[1])
1469 && push_operand (operands
[0], SImode
))
1470 return "pushab %c2(%1)";
1472 if (CONST_INT_P (operands
[2])
1473 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1474 return "subl3 $%n2,%1,%0";
1476 if (CONST_INT_P (operands
[2])
1477 && (unsigned HOST_WIDE_INT
) INTVAL (operands
[2]) >= 64
1478 && REG_P (operands
[1])
1479 && ((INTVAL (operands
[2]) < 32767 && INTVAL (operands
[2]) > -32768)
1480 || REGNO (operands
[1]) > 11))
1481 return "movab %c2(%1),%0";
1483 /* Add this if using gcc on a VAX 3xxx:
1484 if (REG_P (operands[1]) && REG_P (operands[2]))
1485 return "movab (%1)[%2],%0";
1488 if (REG_P (operands
[1]) && symbolic_operand (operands
[2], SImode
))
1490 if (push_operand (operands
[0], SImode
))
1491 return "pushab %a2[%1]";
1492 return "movab %a2[%1],%0";
1495 if (REG_P (operands
[2]) && symbolic_operand (operands
[1], SImode
))
1497 if (push_operand (operands
[0], SImode
))
1498 return "pushab %a1[%2]";
1499 return "movab %a1[%2],%0";
1502 if (flag_pic
&& REG_P (operands
[0])
1503 && symbolic_operand (operands
[2], SImode
))
1504 return "movab %a2,%0;addl2 %1,%0";
1507 && (symbolic_operand (operands
[1], SImode
)
1508 || symbolic_operand (operands
[1], SImode
)))
1511 return "addl3 %1,%2,%0";
1514 if (rtx_equal_p (operands
[0], operands
[1]))
1516 if (operands
[2] == const1_rtx
)
1518 if (operands
[2] == constm1_rtx
)
1520 if (CONST_INT_P (operands
[2])
1521 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1522 return "subw2 $%n2,%0";
1523 return "addw2 %2,%0";
1525 if (rtx_equal_p (operands
[0], operands
[2]))
1526 return "addw2 %1,%0";
1527 if (CONST_INT_P (operands
[2])
1528 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1529 return "subw3 $%n2,%1,%0";
1530 return "addw3 %1,%2,%0";
1533 if (rtx_equal_p (operands
[0], operands
[1]))
1535 if (operands
[2] == const1_rtx
)
1537 if (operands
[2] == constm1_rtx
)
1539 if (CONST_INT_P (operands
[2])
1540 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1541 return "subb2 $%n2,%0";
1542 return "addb2 %2,%0";
1544 if (rtx_equal_p (operands
[0], operands
[2]))
1545 return "addb2 %1,%0";
1546 if (CONST_INT_P (operands
[2])
1547 && (unsigned HOST_WIDE_INT
) (- INTVAL (operands
[2])) < 64)
1548 return "subb3 $%n2,%1,%0";
1549 return "addb3 %1,%2,%0";
1557 vax_output_int_subtract (rtx insn
, rtx
*operands
, enum machine_mode mode
)
1564 const char *pattern
;
1567 if (TARGET_QMATH
&& 0)
1570 split_quadword_operands (insn
, MINUS
, operands
, low
, 3);
1574 if (operands
[1] == const0_rtx
&& low
[1] == const0_rtx
)
1576 /* Negation is tricky. It's basically complement and increment.
1577 Negate hi, then lo, and subtract the carry back. */
1578 if ((MEM_P (low
[0]) && GET_CODE (XEXP (low
[0], 0)) == POST_INC
)
1579 || (MEM_P (operands
[0])
1580 && GET_CODE (XEXP (operands
[0], 0)) == POST_INC
))
1581 fatal_insn ("illegal operand detected", insn
);
1582 output_asm_insn ("mnegl %2,%0", operands
);
1583 output_asm_insn ("mnegl %2,%0", low
);
1584 return "sbwc $0,%0";
1586 gcc_assert (rtx_equal_p (operands
[0], operands
[1]));
1587 gcc_assert (rtx_equal_p (low
[0], low
[1]));
1588 if (low
[2] == const1_rtx
)
1589 output_asm_insn ("decl %0", low
);
1591 output_asm_insn ("subl2 %2,%0", low
);
1592 return "sbwc %2,%0";
1595 /* Subtract low parts. */
1596 if (rtx_equal_p (operands
[0], operands
[1]))
1598 if (low
[2] == const0_rtx
)
1599 pattern
= 0, carry
= 0;
1600 else if (low
[2] == constm1_rtx
)
1601 pattern
= "decl %0";
1603 pattern
= "subl2 %2,%0";
1607 if (low
[2] == constm1_rtx
)
1608 pattern
= "decl %0";
1609 else if (low
[2] == const0_rtx
)
1610 pattern
= get_insn_template (CODE_FOR_movsi
, insn
), carry
= 0;
1612 pattern
= "subl3 %2,%1,%0";
1615 output_asm_insn (pattern
, low
);
1618 if (!rtx_equal_p (operands
[0], operands
[1]))
1619 return "movl %1,%0;sbwc %2,%0";
1620 return "sbwc %2,%0";
1621 /* %0 = %2 - %1 - C */
1623 return get_insn_template (CODE_FOR_subsi3
, insn
);
1631 /* True if X is an rtx for a constant that is a valid address. */
1634 legitimate_constant_address_p (rtx x
)
1636 if (GET_CODE (x
) == LABEL_REF
|| GET_CODE (x
) == SYMBOL_REF
1637 || CONST_INT_P (x
) || GET_CODE (x
) == HIGH
)
1639 if (GET_CODE (x
) != CONST
)
1641 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
1643 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1644 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (x
, 0), 0)))
1650 /* The other macros defined here are used only in legitimate_address_p (). */
1652 /* Nonzero if X is a hard reg that can be used as an index
1653 or, if not strict, if it is a pseudo reg. */
1654 #define INDEX_REGISTER_P(X, STRICT) \
1655 (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))
1657 /* Nonzero if X is a hard reg that can be used as a base reg
1658 or, if not strict, if it is a pseudo reg. */
1659 #define BASE_REGISTER_P(X, STRICT) \
1660 (REG_P (X) && (!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))
1662 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
1664 /* Re-definition of CONSTANT_ADDRESS_P, which is true only when there
1665 are no SYMBOL_REFs for external symbols present. */
1668 indirectable_constant_address_p (rtx x
, bool indirect
)
1670 if (GET_CODE (x
) == SYMBOL_REF
)
1671 return !flag_pic
|| SYMBOL_REF_LOCAL_P (x
) || !indirect
;
1673 if (GET_CODE (x
) == CONST
)
1675 || GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
1676 || SYMBOL_REF_LOCAL_P (XEXP (XEXP (x
, 0), 0));
1678 return CONSTANT_ADDRESS_P (x
);
1681 #else /* not NO_EXTERNAL_INDIRECT_ADDRESS */
1684 indirectable_constant_address_p (rtx x
, bool indirect ATTRIBUTE_UNUSED
)
1686 return CONSTANT_ADDRESS_P (x
);
1689 #endif /* not NO_EXTERNAL_INDIRECT_ADDRESS */
1691 /* True if X is an address which can be indirected. External symbols
1692 could be in a sharable image library, so we disallow those. */
1695 indirectable_address_p (rtx x
, bool strict
, bool indirect
)
1697 if (indirectable_constant_address_p (x
, indirect
)
1698 || BASE_REGISTER_P (x
, strict
))
1700 if (GET_CODE (x
) != PLUS
1701 || !BASE_REGISTER_P (XEXP (x
, 0), strict
)
1702 || (flag_pic
&& !CONST_INT_P (XEXP (x
, 1))))
1704 return indirectable_constant_address_p (XEXP (x
, 1), indirect
);
1707 /* Return true if x is a valid address not using indexing.
1708 (This much is the easy part.) */
1710 nonindexed_address_p (rtx x
, bool strict
)
1715 if (! reload_in_progress
1716 || reg_equiv_mem (REGNO (x
)) == 0
1717 || indirectable_address_p (reg_equiv_mem (REGNO (x
)), strict
, false))
1720 if (indirectable_constant_address_p (x
, false))
1722 if (indirectable_address_p (x
, strict
, false))
1724 xfoo0
= XEXP (x
, 0);
1725 if (MEM_P (x
) && indirectable_address_p (xfoo0
, strict
, true))
1727 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1728 && BASE_REGISTER_P (xfoo0
, strict
))
1733 /* True if PROD is either a reg times size of mode MODE and MODE is less
1734 than or equal 8 bytes, or just a reg if MODE is one byte. */
1737 index_term_p (rtx prod
, enum machine_mode mode
, bool strict
)
1741 if (GET_MODE_SIZE (mode
) == 1)
1742 return BASE_REGISTER_P (prod
, strict
);
1744 if (GET_CODE (prod
) != MULT
|| GET_MODE_SIZE (mode
) > 8)
1747 xfoo0
= XEXP (prod
, 0);
1748 xfoo1
= XEXP (prod
, 1);
1750 if (CONST_INT_P (xfoo0
)
1751 && INTVAL (xfoo0
) == (int)GET_MODE_SIZE (mode
)
1752 && INDEX_REGISTER_P (xfoo1
, strict
))
1755 if (CONST_INT_P (xfoo1
)
1756 && INTVAL (xfoo1
) == (int)GET_MODE_SIZE (mode
)
1757 && INDEX_REGISTER_P (xfoo0
, strict
))
1763 /* Return true if X is the sum of a register
1764 and a valid index term for mode MODE. */
1766 reg_plus_index_p (rtx x
, enum machine_mode mode
, bool strict
)
1770 if (GET_CODE (x
) != PLUS
)
1773 xfoo0
= XEXP (x
, 0);
1774 xfoo1
= XEXP (x
, 1);
1776 if (BASE_REGISTER_P (xfoo0
, strict
) && index_term_p (xfoo1
, mode
, strict
))
1779 if (BASE_REGISTER_P (xfoo1
, strict
) && index_term_p (xfoo0
, mode
, strict
))
1785 /* Return true if xfoo0 and xfoo1 constitute a valid indexed address. */
1787 indexable_address_p (rtx xfoo0
, rtx xfoo1
, enum machine_mode mode
, bool strict
)
1789 if (!CONSTANT_ADDRESS_P (xfoo0
))
1791 if (BASE_REGISTER_P (xfoo1
, strict
))
1792 return !flag_pic
|| mode
== QImode
;
1793 if (flag_pic
&& symbolic_operand (xfoo0
, SImode
))
1795 return reg_plus_index_p (xfoo1
, mode
, strict
);
1798 /* legitimate_address_p returns true if it recognizes an RTL expression "x"
1799 that is a valid memory address for an instruction.
1800 The MODE argument is the machine mode for the MEM expression
1801 that wants to use this address. */
1803 vax_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1807 if (nonindexed_address_p (x
, strict
))
1810 if (GET_CODE (x
) != PLUS
)
1813 /* Handle <address>[index] represented with index-sum outermost */
1815 xfoo0
= XEXP (x
, 0);
1816 xfoo1
= XEXP (x
, 1);
1818 if (index_term_p (xfoo0
, mode
, strict
)
1819 && nonindexed_address_p (xfoo1
, strict
))
1822 if (index_term_p (xfoo1
, mode
, strict
)
1823 && nonindexed_address_p (xfoo0
, strict
))
1826 /* Handle offset(reg)[index] with offset added outermost */
1828 if (indexable_address_p (xfoo0
, xfoo1
, mode
, strict
)
1829 || indexable_address_p (xfoo1
, xfoo0
, mode
, strict
))
1835 /* Return true if x (a legitimate address expression) has an effect that
1836 depends on the machine mode it is used for. On the VAX, the predecrement
1837 and postincrement address depend thus (the amount of decrement or
1838 increment being the length of the operand) and all indexed address depend
1839 thus (because the index scale factor is the length of the operand). */
1842 vax_mode_dependent_address_p (const_rtx x
, addr_space_t as ATTRIBUTE_UNUSED
)
1846 /* Auto-increment cases are now dealt with generically in recog.c. */
1847 if (GET_CODE (x
) != PLUS
)
1850 xfoo0
= XEXP (x
, 0);
1851 xfoo1
= XEXP (x
, 1);
1853 if (CONST_INT_P (xfoo0
) && REG_P (xfoo1
))
1855 if (CONST_INT_P (xfoo1
) && REG_P (xfoo0
))
1857 if (!flag_pic
&& CONSTANT_ADDRESS_P (xfoo0
) && REG_P (xfoo1
))
1859 if (!flag_pic
&& CONSTANT_ADDRESS_P (xfoo1
) && REG_P (xfoo0
))
1866 fixup_mathdi_operand (rtx x
, enum machine_mode mode
)
1868 if (illegal_addsub_di_memory_operand (x
, mode
))
1870 rtx addr
= XEXP (x
, 0);
1871 rtx temp
= gen_reg_rtx (Pmode
);
1873 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
1874 if (GET_CODE (addr
) == CONST
&& flag_pic
)
1876 offset
= XEXP (XEXP (addr
, 0), 1);
1877 addr
= XEXP (XEXP (addr
, 0), 0);
1880 emit_move_insn (temp
, addr
);
1882 temp
= gen_rtx_PLUS (Pmode
, temp
, offset
);
1883 x
= gen_rtx_MEM (DImode
, temp
);
1889 vax_expand_addsub_di_operands (rtx
* operands
, enum rtx_code code
)
1891 int hi_only
= operand_subword (operands
[2], 0, 0, DImode
) == const0_rtx
;
1894 rtx (*gen_old_insn
)(rtx
, rtx
, rtx
);
1895 rtx (*gen_si_insn
)(rtx
, rtx
, rtx
);
1896 rtx (*gen_insn
)(rtx
, rtx
, rtx
);
1900 gen_old_insn
= gen_adddi3_old
;
1901 gen_si_insn
= gen_addsi3
;
1902 gen_insn
= gen_adcdi3
;
1904 else if (code
== MINUS
)
1906 gen_old_insn
= gen_subdi3_old
;
1907 gen_si_insn
= gen_subsi3
;
1908 gen_insn
= gen_sbcdi3
;
1913 /* If this is addition (thus operands are commutative) and if there is one
1914 addend that duplicates the desination, we want that addend to be the
1917 && rtx_equal_p (operands
[0], operands
[2])
1918 && !rtx_equal_p (operands
[1], operands
[2]))
1921 operands
[2] = operands
[1];
1927 emit_insn ((*gen_old_insn
) (operands
[0], operands
[1], operands
[2]));
1931 if (!rtx_equal_p (operands
[0], operands
[1])
1932 && (REG_P (operands
[0]) && MEM_P (operands
[1])))
1934 emit_move_insn (operands
[0], operands
[1]);
1935 operands
[1] = operands
[0];
1938 operands
[0] = fixup_mathdi_operand (operands
[0], DImode
);
1939 operands
[1] = fixup_mathdi_operand (operands
[1], DImode
);
1940 operands
[2] = fixup_mathdi_operand (operands
[2], DImode
);
1942 if (!rtx_equal_p (operands
[0], operands
[1]))
1943 emit_move_insn (operand_subword (operands
[0], 0, 0, DImode
),
1944 operand_subword (operands
[1], 0, 0, DImode
));
1946 emit_insn ((*gen_si_insn
) (operand_subword (operands
[0], 1, 0, DImode
),
1947 operand_subword (operands
[1], 1, 0, DImode
),
1948 operand_subword (operands
[2], 1, 0, DImode
)));
1952 /* If are adding the same value together, that's really a multiply by 2,
1953 and that's just a left shift of 1. */
1954 if (rtx_equal_p (operands
[1], operands
[2]))
1956 gcc_assert (code
!= MINUS
);
1957 emit_insn (gen_ashldi3 (operands
[0], operands
[1], const1_rtx
));
1961 operands
[0] = fixup_mathdi_operand (operands
[0], DImode
);
1963 /* If an operand is the same as operand[0], use the operand[0] rtx
1964 because fixup will an equivalent rtx but not an equal one. */
1966 if (rtx_equal_p (operands
[0], operands
[1]))
1967 operands
[1] = operands
[0];
1969 operands
[1] = fixup_mathdi_operand (operands
[1], DImode
);
1971 if (rtx_equal_p (operands
[0], operands
[2]))
1972 operands
[2] = operands
[0];
1974 operands
[2] = fixup_mathdi_operand (operands
[2], DImode
);
1976 /* If we are subtracting not from ourselves [d = a - b], and because the
1977 carry ops are two operand only, we would need to do a move prior to
1978 the subtract. And if d == b, we would need a temp otherwise
1979 [d = a, d -= d] and we end up with 0. Instead we rewrite d = a - b
1980 into d = -b, d += a. Since -b can never overflow, even if b == d,
1983 If we are doing addition, since the carry ops are two operand, if
1984 we aren't adding to ourselves, move the first addend to the
1985 destination first. */
1987 gcc_assert (operands
[1] != const0_rtx
|| code
== MINUS
);
1988 if (!rtx_equal_p (operands
[0], operands
[1]) && operands
[1] != const0_rtx
)
1990 if (code
== MINUS
&& CONSTANT_P (operands
[1]))
1992 temp
= gen_reg_rtx (DImode
);
1993 emit_insn (gen_sbcdi3 (operands
[0], const0_rtx
, operands
[2]));
1995 gen_insn
= gen_adcdi3
;
1996 operands
[2] = operands
[1];
1997 operands
[1] = operands
[0];
2000 emit_move_insn (operands
[0], operands
[1]);
2003 /* Subtracting a constant will have been rewritten to an addition of the
2004 negative of that constant before we get here. */
2005 gcc_assert (!CONSTANT_P (operands
[2]) || code
== PLUS
);
2006 emit_insn ((*gen_insn
) (operands
[0], operands
[1], operands
[2]));
2011 adjacent_operands_p (rtx lo
, rtx hi
, enum machine_mode mode
)
2013 HOST_WIDE_INT lo_offset
;
2014 HOST_WIDE_INT hi_offset
;
2016 if (GET_CODE (lo
) != GET_CODE (hi
))
2020 return mode
== SImode
&& REGNO (lo
) + 1 == REGNO (hi
);
2021 if (CONST_INT_P (lo
))
2022 return INTVAL (hi
) == 0 && 0 <= INTVAL (lo
) && INTVAL (lo
) < 64;
2023 if (CONST_INT_P (lo
))
2024 return mode
!= SImode
;
2029 if (MEM_VOLATILE_P (lo
) || MEM_VOLATILE_P (hi
))
2035 if (GET_CODE (lo
) == POST_INC
/* || GET_CODE (lo) == PRE_DEC */)
2036 return rtx_equal_p (lo
, hi
);
2038 switch (GET_CODE (lo
))
2048 if (!CONST_INT_P (XEXP (lo
, 1)))
2050 lo_offset
= INTVAL (XEXP (lo
, 1));
2057 switch (GET_CODE (hi
))
2067 if (!CONST_INT_P (XEXP (hi
, 1)))
2069 hi_offset
= INTVAL (XEXP (hi
, 1));
2076 if (GET_CODE (lo
) == MULT
|| GET_CODE (lo
) == PLUS
)
2079 return rtx_equal_p (lo
, hi
)
2080 && hi_offset
- lo_offset
== GET_MODE_SIZE (mode
);
2083 /* Output assembler code for a block containing the constant parts
2084 of a trampoline, leaving space for the variable parts. */
2086 /* On the VAX, the trampoline contains an entry mask and two instructions:
2088 movl $STATIC,r0 (store the functions static chain)
2089 jmp *$FUNCTION (jump to function code at address FUNCTION) */
2092 vax_asm_trampoline_template (FILE *f ATTRIBUTE_UNUSED
)
2094 assemble_aligned_integer (2, const0_rtx
);
2095 assemble_aligned_integer (2, GEN_INT (0x8fd0));
2096 assemble_aligned_integer (4, const0_rtx
);
2097 assemble_aligned_integer (1, GEN_INT (0x50 + STATIC_CHAIN_REGNUM
));
2098 assemble_aligned_integer (2, GEN_INT (0x9f17));
2099 assemble_aligned_integer (4, const0_rtx
);
2102 /* We copy the register-mask from the function's pure code
2103 to the start of the trampoline. */
2106 vax_trampoline_init (rtx m_tramp
, tree fndecl
, rtx cxt
)
2108 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2111 emit_block_move (m_tramp
, assemble_trampoline_template (),
2112 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
2114 mem
= adjust_address (m_tramp
, HImode
, 0);
2115 emit_move_insn (mem
, gen_const_mem (HImode
, fnaddr
));
2117 mem
= adjust_address (m_tramp
, SImode
, 4);
2118 emit_move_insn (mem
, cxt
);
2119 mem
= adjust_address (m_tramp
, SImode
, 11);
2120 emit_move_insn (mem
, plus_constant (Pmode
, fnaddr
, 2));
2121 emit_insn (gen_sync_istream ());
2124 /* Value is the number of bytes of arguments automatically
2125 popped when returning from a subroutine call.
2126 FUNDECL is the declaration node of the function (as a tree),
2127 FUNTYPE is the data type of the function (as a tree),
2128 or for a library call it is an identifier node for the subroutine name.
2129 SIZE is the number of bytes of arguments passed on the stack.
2131 On the VAX, the RET insn pops a maximum of 255 args for any function. */
2134 vax_return_pops_args (tree fundecl ATTRIBUTE_UNUSED
,
2135 tree funtype ATTRIBUTE_UNUSED
, int size
)
2137 return size
> 255 * 4 ? 0 : size
;
2140 /* Define where to put the arguments to a function.
2141 Value is zero to push the argument on the stack,
2142 or a hard register in which to store the argument.
2144 MODE is the argument's machine mode.
2145 TYPE is the data type of the argument (as a tree).
2146 This is null for libcalls where that information may
2148 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2149 the preceding args and about the function being called.
2150 NAMED is nonzero if this argument is a named parameter
2151 (otherwise it is an extra parameter matching an ellipsis). */
2153 /* On the VAX all args are pushed. */
2156 vax_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
2157 enum machine_mode mode ATTRIBUTE_UNUSED
,
2158 const_tree type ATTRIBUTE_UNUSED
,
2159 bool named ATTRIBUTE_UNUSED
)
2164 /* Update the data in CUM to advance over an argument of mode MODE and
2165 data type TYPE. (TYPE is null for libcalls where that information
2166 may not be available.) */
2169 vax_function_arg_advance (cumulative_args_t cum_v
, enum machine_mode mode
,
2170 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2172 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2174 *cum
+= (mode
!= BLKmode
2175 ? (GET_MODE_SIZE (mode
) + 3) & ~3
2176 : (int_size_in_bytes (type
) + 3) & ~3);