1 /* Subroutines for insn-output.c for VAX.
2 Copyright (C) 1987, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2004
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
35 #include "insn-attr.h"
44 #include "target-def.h"
46 static void vax_output_function_prologue (FILE *, HOST_WIDE_INT
);
47 static void vax_file_start (void);
48 static void vax_init_libfuncs (void);
49 static void vax_output_mi_thunk (FILE *, tree
, HOST_WIDE_INT
,
51 static int vax_address_cost_1 (rtx
);
52 static int vax_address_cost (rtx
);
53 static bool vax_rtx_costs (rtx
, int, int, int *);
54 static rtx
vax_struct_value_rtx (tree
, int);
56 /* Initialize the GCC target structure. */
57 #undef TARGET_ASM_ALIGNED_HI_OP
58 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
60 #undef TARGET_ASM_FUNCTION_PROLOGUE
61 #define TARGET_ASM_FUNCTION_PROLOGUE vax_output_function_prologue
63 #undef TARGET_ASM_FILE_START
64 #define TARGET_ASM_FILE_START vax_file_start
65 #undef TARGET_ASM_FILE_START_APP_OFF
66 #define TARGET_ASM_FILE_START_APP_OFF true
68 #undef TARGET_INIT_LIBFUNCS
69 #define TARGET_INIT_LIBFUNCS vax_init_libfuncs
71 #undef TARGET_ASM_OUTPUT_MI_THUNK
72 #define TARGET_ASM_OUTPUT_MI_THUNK vax_output_mi_thunk
73 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
74 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
76 #undef TARGET_DEFAULT_TARGET_FLAGS
77 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_DEFAULT
79 #undef TARGET_RTX_COSTS
80 #define TARGET_RTX_COSTS vax_rtx_costs
81 #undef TARGET_ADDRESS_COST
82 #define TARGET_ADDRESS_COST vax_address_cost
84 #undef TARGET_PROMOTE_PROTOTYPES
85 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
87 #undef TARGET_STRUCT_VALUE_RTX
88 #define TARGET_STRUCT_VALUE_RTX vax_struct_value_rtx
90 struct gcc_target targetm
= TARGET_INITIALIZER
;
92 /* Set global variables as needed for the options enabled. */
95 override_options (void)
97 /* We're VAX floating point, not IEEE floating point. */
99 REAL_MODE_FORMAT (DFmode
) = &vax_g_format
;
102 /* Generate the assembly code for function entry. FILE is a stdio
103 stream to output the code to. SIZE is an int: how many units of
104 temporary storage to allocate.
106 Refer to the array `regs_ever_live' to determine which registers to
107 save; `regs_ever_live[I]' is nonzero if register number I is ever
108 used in the function. This function is responsible for knowing
109 which registers should not be saved even if used. */
112 vax_output_function_prologue (FILE * file
, HOST_WIDE_INT size
)
115 register int mask
= 0;
117 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
118 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
121 fprintf (file
, "\t.word 0x%x\n", mask
);
123 if (dwarf2out_do_frame ())
125 const char *label
= dwarf2out_cfi_label ();
128 for (regno
= FIRST_PSEUDO_REGISTER
-1; regno
>= 0; --regno
)
129 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
130 dwarf2out_reg_save (label
, regno
, offset
-= 4);
132 dwarf2out_reg_save (label
, PC_REGNUM
, offset
-= 4);
133 dwarf2out_reg_save (label
, FRAME_POINTER_REGNUM
, offset
-= 4);
134 dwarf2out_reg_save (label
, ARG_POINTER_REGNUM
, offset
-= 4);
135 dwarf2out_def_cfa (label
, FRAME_POINTER_REGNUM
, -(offset
- 4));
138 size
-= STARTING_FRAME_OFFSET
;
140 asm_fprintf (file
, "\tmovab %wd(%Rsp),%Rsp\n", -size
);
142 asm_fprintf (file
, "\tsubl2 $%wd,%Rsp\n", size
);
145 /* When debugging with stabs, we want to output an extra dummy label
146 so that gas can distinguish between D_float and G_float prior to
147 processing the .stabs directive identifying type double. */
149 vax_file_start (void)
151 default_file_start ();
153 if (write_symbols
== DBX_DEBUG
)
154 fprintf (asm_out_file
, "___vax_%c_doubles:\n", ASM_DOUBLE_CHAR
);
157 /* We can use the BSD C library routines for the libgcc calls that are
158 still generated, since that's what they boil down to anyways. When
159 ELF, avoid the user's namespace. */
162 vax_init_libfuncs (void)
164 set_optab_libfunc (udiv_optab
, SImode
, TARGET_ELF
? "*__udiv" : "*udiv");
165 set_optab_libfunc (umod_optab
, SImode
, TARGET_ELF
? "*__urem" : "*urem");
168 /* This is like nonimmediate_operand with a restriction on the type of MEM. */
171 split_quadword_operands (rtx
* operands
, rtx
* low
, int n ATTRIBUTE_UNUSED
)
174 /* Split operands. */
176 low
[0] = low
[1] = low
[2] = 0;
177 for (i
= 0; i
< 3; i
++)
180 /* it's already been figured out */;
181 else if (GET_CODE (operands
[i
]) == MEM
182 && (GET_CODE (XEXP (operands
[i
], 0)) == POST_INC
))
184 rtx addr
= XEXP (operands
[i
], 0);
185 operands
[i
] = low
[i
] = gen_rtx_MEM (SImode
, addr
);
186 if (which_alternative
== 0 && i
== 0)
188 addr
= XEXP (operands
[i
], 0);
189 operands
[i
+1] = low
[i
+1] = gen_rtx_MEM (SImode
, addr
);
194 low
[i
] = operand_subword (operands
[i
], 0, 0, DImode
);
195 operands
[i
] = operand_subword (operands
[i
], 1, 0, DImode
);
201 print_operand_address (FILE * file
, register rtx addr
)
203 register rtx reg1
, breg
, ireg
;
207 switch (GET_CODE (addr
))
211 addr
= XEXP (addr
, 0);
215 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
219 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
223 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
227 /* There can be either two or three things added here. One must be a
228 REG. One can be either a REG or a MULT of a REG and an appropriate
229 constant, and the third can only be a constant or a MEM.
231 We get these two or three things and put the constant or MEM in
232 OFFSET, the MULT or REG in IREG, and the REG in BREG. If we have
233 a register and can't tell yet if it is a base or index register,
236 reg1
= 0; ireg
= 0; breg
= 0; offset
= 0;
238 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
239 || GET_CODE (XEXP (addr
, 0)) == MEM
)
241 offset
= XEXP (addr
, 0);
242 addr
= XEXP (addr
, 1);
244 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
245 || GET_CODE (XEXP (addr
, 1)) == MEM
)
247 offset
= XEXP (addr
, 1);
248 addr
= XEXP (addr
, 0);
250 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
252 ireg
= XEXP (addr
, 1);
253 addr
= XEXP (addr
, 0);
255 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
257 ireg
= XEXP (addr
, 0);
258 addr
= XEXP (addr
, 1);
260 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
262 reg1
= XEXP (addr
, 1);
263 addr
= XEXP (addr
, 0);
265 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
267 reg1
= XEXP (addr
, 0);
268 addr
= XEXP (addr
, 1);
273 if (GET_CODE (addr
) == REG
)
280 else if (GET_CODE (addr
) == MULT
)
282 else if (GET_CODE (addr
) == PLUS
)
284 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
285 || GET_CODE (XEXP (addr
, 0)) == MEM
)
289 if (GET_CODE (offset
) == CONST_INT
)
290 offset
= plus_constant (XEXP (addr
, 0), INTVAL (offset
));
291 else if (GET_CODE (XEXP (addr
, 0)) == CONST_INT
)
292 offset
= plus_constant (offset
, INTVAL (XEXP (addr
, 0)));
296 offset
= XEXP (addr
, 0);
298 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
301 ireg
= reg1
, breg
= XEXP (addr
, 0), reg1
= 0;
303 reg1
= XEXP (addr
, 0);
305 else if (GET_CODE (XEXP (addr
, 0)) == MULT
)
309 ireg
= XEXP (addr
, 0);
314 if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
315 || GET_CODE (XEXP (addr
, 1)) == MEM
)
319 if (GET_CODE (offset
) == CONST_INT
)
320 offset
= plus_constant (XEXP (addr
, 1), INTVAL (offset
));
321 else if (GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
322 offset
= plus_constant (offset
, INTVAL (XEXP (addr
, 1)));
326 offset
= XEXP (addr
, 1);
328 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
331 ireg
= reg1
, breg
= XEXP (addr
, 1), reg1
= 0;
333 reg1
= XEXP (addr
, 1);
335 else if (GET_CODE (XEXP (addr
, 1)) == MULT
)
339 ireg
= XEXP (addr
, 1);
347 /* If REG1 is nonzero, figure out if it is a base or index register. */
350 if (breg
!= 0 || (offset
&& GET_CODE (offset
) == MEM
))
361 output_address (offset
);
364 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
368 if (GET_CODE (ireg
) == MULT
)
369 ireg
= XEXP (ireg
, 0);
370 if (GET_CODE (ireg
) != REG
)
372 fprintf (file
, "[%s]", reg_names
[REGNO (ireg
)]);
377 output_addr_const (file
, addr
);
382 rev_cond_name (rtx op
)
384 switch (GET_CODE (op
))
413 vax_float_literal(register rtx c
)
415 register enum machine_mode mode
;
416 REAL_VALUE_TYPE r
, s
;
419 if (GET_CODE (c
) != CONST_DOUBLE
)
424 if (c
== const_tiny_rtx
[(int) mode
][0]
425 || c
== const_tiny_rtx
[(int) mode
][1]
426 || c
== const_tiny_rtx
[(int) mode
][2])
429 REAL_VALUE_FROM_CONST_DOUBLE (r
, c
);
431 for (i
= 0; i
< 7; i
++)
434 REAL_VALUE_FROM_INT (s
, x
, 0, mode
);
436 if (REAL_VALUES_EQUAL (r
, s
))
438 if (!exact_real_inverse (mode
, &s
))
440 if (REAL_VALUES_EQUAL (r
, s
))
447 /* Return the cost in cycles of a memory address, relative to register
450 Each of the following adds the indicated number of cycles:
454 1 - indexing and/or offset(register)
459 vax_address_cost_1 (register rtx addr
)
461 int reg
= 0, indexed
= 0, indir
= 0, offset
= 0, predec
= 0;
462 rtx plus_op0
= 0, plus_op1
= 0;
464 switch (GET_CODE (addr
))
474 indexed
= 1; /* 2 on VAX 2 */
477 /* byte offsets cost nothing (on a VAX 2, they cost 1 cycle) */
479 offset
= (unsigned HOST_WIDE_INT
)(INTVAL(addr
)+128) > 256;
483 offset
= 1; /* 2 on VAX 2 */
485 case LABEL_REF
: /* this is probably a byte offset from the pc */
491 plus_op1
= XEXP (addr
, 0);
493 plus_op0
= XEXP (addr
, 0);
494 addr
= XEXP (addr
, 1);
497 indir
= 2; /* 3 on VAX 2 */
498 addr
= XEXP (addr
, 0);
504 /* Up to 3 things can be added in an address. They are stored in
505 plus_op0, plus_op1, and addr. */
519 /* Indexing and register+offset can both be used (except on a VAX 2)
520 without increasing execution time over either one alone. */
521 if (reg
&& indexed
&& offset
)
522 return reg
+ indir
+ offset
+ predec
;
523 return reg
+ indexed
+ indir
+ offset
+ predec
;
527 vax_address_cost (rtx x
)
529 return (1 + (GET_CODE (x
) == REG
? 0 : vax_address_cost_1 (x
)));
532 /* Cost of an expression on a VAX. This version has costs tuned for the
533 CVAX chip (found in the VAX 3 series) with comments for variations on
536 FIXME: The costs need review, particularly for TRUNCATE, FLOAT_EXTEND
537 and FLOAT_TRUNCATE. We need a -mcpu option to allow provision of
538 costs on a per cpu basis. */
541 vax_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
543 enum machine_mode mode
= GET_MODE (x
);
544 int i
= 0; /* may be modified in switch */
545 const char *fmt
= GET_RTX_FORMAT (code
); /* may be modified in switch */
549 /* On a VAX, constants from 0..63 are cheap because they can use the
550 1 byte literal constant format. Compare to -1 should be made cheap
551 so that decrement-and-branch insns can be formed more easily (if
552 the value -1 is copied to a register some decrement-and-branch
553 patterns will not match). */
557 if (outer_code
== AND
)
559 *total
= ((unsigned HOST_WIDE_INT
) ~INTVAL (x
) <= 077) ? 1 : 2;
562 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) <= 077
563 || (outer_code
== COMPARE
565 || ((outer_code
== PLUS
|| outer_code
== MINUS
)
566 && (unsigned HOST_WIDE_INT
) -INTVAL (x
) <= 077))
580 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
581 *total
= vax_float_literal (x
) ? 5 : 8;
583 *total
= ((CONST_DOUBLE_HIGH (x
) == 0
584 && (unsigned HOST_WIDE_INT
) CONST_DOUBLE_LOW (x
) < 64)
585 || (outer_code
== PLUS
586 && CONST_DOUBLE_HIGH (x
) == -1
587 && (unsigned HOST_WIDE_INT
)-CONST_DOUBLE_LOW (x
) < 64))
593 return true; /* Implies register operand. */
597 return true; /* Implies register operand. */
603 *total
= 16; /* 4 on VAX 9000 */
606 *total
= 9; /* 4 on VAX 9000, 12 on VAX 2 */
609 *total
= 16; /* 6 on VAX 9000, 28 on VAX 2 */
614 *total
= 10; /* 3-4 on VAX 9000, 20-28 on VAX 2 */
617 *total
= MAX_COST
; /* Mode is not supported. */
625 *total
= MAX_COST
; /* Mode is not supported. */
633 *total
= 30; /* Highly variable. */
634 else if (mode
== DFmode
)
635 /* divide takes 28 cycles if the result is not zero, 13 otherwise */
638 *total
= 11; /* 25 on VAX 2 */
648 *total
= MAX_COST
; /* Mode is not supported. */
655 *total
= (6 /* 4 on VAX 9000 */
656 + (mode
== DFmode
) + (GET_MODE (XEXP (x
, 0)) != SImode
));
660 *total
= 7; /* 17 on VAX 2 */
669 *total
= 10; /* 6 on VAX 9000 */
674 *total
= 6; /* 5 on VAX 2, 4 on VAX 9000 */
675 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
676 fmt
= "e"; /* all constant rotate counts are short */
681 *total
= (mode
== DFmode
) ? 13 : 8; /* 6/8 on VAX 9000, 16/15 on VAX 2 */
682 /* Small integer operands can use subl2 and addl2. */
683 if ((GET_CODE (XEXP (x
, 1)) == CONST_INT
)
684 && (unsigned HOST_WIDE_INT
)(INTVAL (XEXP (x
, 1)) + 63) < 127)
694 /* AND is special because the first operand is complemented. */
696 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
698 if ((unsigned HOST_WIDE_INT
)~INTVAL (XEXP (x
, 0)) > 63)
708 else if (mode
== SFmode
)
710 else if (mode
== DImode
)
726 if (mode
== DImode
|| mode
== DFmode
)
727 *total
= 5; /* 7 on VAX 2 */
729 *total
= 3; /* 4 on VAX 2 */
731 if (GET_CODE (x
) != REG
&& GET_CODE (x
) != POST_INC
)
732 *total
+= vax_address_cost_1 (x
);
738 *total
= 3; /* FIXME: Costs need to be checked */
745 /* Now look inside the expression. Operands which are not registers or
746 short constants add to the cost.
748 FMT and I may have been adjusted in the switch above for instructions
749 which require special handling. */
751 while (*fmt
++ == 'e')
753 rtx op
= XEXP (x
, i
);
756 code
= GET_CODE (op
);
758 /* A NOT is likely to be found as the first operand of an AND
759 (in which case the relevant cost is of the operand inside
760 the not) and not likely to be found anywhere else. */
762 op
= XEXP (op
, 0), code
= GET_CODE (op
);
767 if ((unsigned HOST_WIDE_INT
)INTVAL (op
) > 63
768 && GET_MODE (x
) != QImode
)
769 *total
+= 1; /* 2 on VAX 2 */
774 *total
+= 1; /* 2 on VAX 2 */
777 if (GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
779 /* Registers are faster than floating point constants -- even
780 those constants which can be encoded in a single byte. */
781 if (vax_float_literal (op
))
784 *total
+= (GET_MODE (x
) == DFmode
) ? 3 : 2;
788 if (CONST_DOUBLE_HIGH (op
) != 0
789 || (unsigned)CONST_DOUBLE_LOW (op
) > 63)
794 *total
+= 1; /* 2 on VAX 2 */
795 if (GET_CODE (XEXP (op
, 0)) != REG
)
796 *total
+= vax_address_cost_1 (XEXP (op
, 0));
809 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
810 Used for C++ multiple inheritance.
811 .mask ^m<r2,r3,r4,r5,r6,r7,r8,r9,r10,r11> #conservative entry mask
812 addl2 $DELTA, 4(ap) #adjust first argument
813 jmp FUNCTION+2 #jump beyond FUNCTION's entry mask
817 vax_output_mi_thunk (FILE * file
,
818 tree thunk ATTRIBUTE_UNUSED
,
820 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
823 fprintf (file
, "\t.word 0x0ffc\n\taddl2 $" HOST_WIDE_INT_PRINT_DEC
, delta
);
824 asm_fprintf (file
, ",4(%Rap)\n");
825 fprintf (file
, "\tjmp ");
826 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
827 fprintf (file
, "+2\n");
831 vax_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
832 int incoming ATTRIBUTE_UNUSED
)
834 return gen_rtx_REG (Pmode
, VAX_STRUCT_VALUE_REGNUM
);
837 /* Worker function for NOTICE_UPDATE_CC. */
840 vax_notice_update_cc (rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
842 if (GET_CODE (exp
) == SET
)
844 if (GET_CODE (SET_SRC (exp
)) == CALL
)
846 else if (GET_CODE (SET_DEST (exp
)) != ZERO_EXTRACT
847 && GET_CODE (SET_DEST (exp
)) != PC
)
850 /* The integer operations below don't set carry or
851 set it in an incompatible way. That's ok though
852 as the Z bit is all we need when doing unsigned
853 comparisons on the result of these insns (since
854 they're always with 0). Set CC_NO_OVERFLOW to
855 generate the correct unsigned branches. */
856 switch (GET_CODE (SET_SRC (exp
)))
859 if (GET_MODE_CLASS (GET_MODE (exp
)) == MODE_FLOAT
)
867 cc_status
.flags
= CC_NO_OVERFLOW
;
872 cc_status
.value1
= SET_DEST (exp
);
873 cc_status
.value2
= SET_SRC (exp
);
876 else if (GET_CODE (exp
) == PARALLEL
877 && GET_CODE (XVECEXP (exp
, 0, 0)) == SET
)
879 if (GET_CODE (SET_SRC (XVECEXP (exp
, 0, 0))) == CALL
)
881 else if (GET_CODE (SET_DEST (XVECEXP (exp
, 0, 0))) != PC
)
884 cc_status
.value1
= SET_DEST (XVECEXP (exp
, 0, 0));
885 cc_status
.value2
= SET_SRC (XVECEXP (exp
, 0, 0));
888 /* PARALLELs whose first element sets the PC are aob,
889 sob insns. They do change the cc's. */
894 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
896 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
897 cc_status
.value2
= 0;
898 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
900 && GET_CODE (cc_status
.value2
) == MEM
)
901 cc_status
.value2
= 0;
902 /* Actual condition, one line up, should be that value2's address
903 depends on value1, but that is too much of a pain. */
906 /* Output integer move instructions. */
909 vax_output_int_move (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
,
910 enum machine_mode mode
)
915 if (GET_CODE (operands
[1]) == SYMBOL_REF
|| GET_CODE (operands
[1]) == CONST
)
917 if (push_operand (operands
[0], SImode
))
919 return "movab %a1,%0";
921 if (operands
[1] == const0_rtx
)
923 if (GET_CODE (operands
[1]) == CONST_INT
924 && (unsigned) INTVAL (operands
[1]) >= 64)
926 int i
= INTVAL (operands
[1]);
927 if ((unsigned)(~i
) < 64)
928 return "mcoml %N1,%0";
929 if ((unsigned)i
< 0x100)
930 return "movzbl %1,%0";
931 if (i
>= -0x80 && i
< 0)
932 return "cvtbl %1,%0";
933 if ((unsigned)i
< 0x10000)
934 return "movzwl %1,%0";
935 if (i
>= -0x8000 && i
< 0)
936 return "cvtwl %1,%0";
938 if (push_operand (operands
[0], SImode
))
943 if (GET_CODE (operands
[1]) == CONST_INT
)
945 int i
= INTVAL (operands
[1]);
948 else if ((unsigned int)i
< 64)
950 else if ((unsigned int)~i
< 64)
951 return "mcomw %H1,%0";
952 else if ((unsigned int)i
< 256)
953 return "movzbw %1,%0";
958 if (GET_CODE (operands
[1]) == CONST_INT
)
960 int i
= INTVAL (operands
[1]);
963 else if ((unsigned int)~i
< 64)
964 return "mcomb %B1,%0";
973 /* Output integer add instructions.
975 The space-time-opcode tradeoffs for addition vary by model of VAX.
977 On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
978 but it not faster on other models.
980 "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
981 faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if
982 a register is used in an address too soon after it is set.
983 Compromise by using movab only when it is shorter than the add
984 or the base register in the address is one of sp, ap, and fp,
985 which are not modified very often. */
988 vax_output_int_add (rtx insn ATTRIBUTE_UNUSED
, rtx
*operands
,
989 enum machine_mode mode
)
994 if (rtx_equal_p (operands
[0], operands
[1]))
996 if (operands
[2] == const1_rtx
)
998 if (operands
[2] == constm1_rtx
)
1000 if (GET_CODE (operands
[2]) == CONST_INT
1001 && (unsigned) (- INTVAL (operands
[2])) < 64)
1002 return "subl2 $%n2,%0";
1003 if (GET_CODE (operands
[2]) == CONST_INT
1004 && (unsigned) INTVAL (operands
[2]) >= 64
1005 && GET_CODE (operands
[1]) == REG
1006 && ((INTVAL (operands
[2]) < 32767 && INTVAL (operands
[2]) > -32768)
1007 || REGNO (operands
[1]) > 11))
1008 return "movab %c2(%1),%0";
1009 return "addl2 %2,%0";
1012 if (rtx_equal_p (operands
[0], operands
[2]))
1013 return "addl2 %1,%0";
1015 if (GET_CODE (operands
[2]) == CONST_INT
1016 && INTVAL (operands
[2]) < 32767
1017 && INTVAL (operands
[2]) > -32768
1018 && GET_CODE (operands
[1]) == REG
1019 && push_operand (operands
[0], SImode
))
1020 return "pushab %c2(%1)";
1022 if (GET_CODE (operands
[2]) == CONST_INT
1023 && (unsigned) (- INTVAL (operands
[2])) < 64)
1024 return "subl3 $%n2,%1,%0";
1026 if (GET_CODE (operands
[2]) == CONST_INT
1027 && (unsigned) INTVAL (operands
[2]) >= 64
1028 && GET_CODE (operands
[1]) == REG
1029 && ((INTVAL (operands
[2]) < 32767 && INTVAL (operands
[2]) > -32768)
1030 || REGNO (operands
[1]) > 11))
1031 return "movab %c2(%1),%0";
1033 /* Add this if using gcc on a VAX 3xxx:
1034 if (REG_P (operands[1]) && REG_P (operands[2]))
1035 return "movab (%1)[%2],%0";
1037 return "addl3 %1,%2,%0";
1040 if (rtx_equal_p (operands
[0], operands
[1]))
1042 if (operands
[2] == const1_rtx
)
1044 if (operands
[2] == constm1_rtx
)
1046 if (GET_CODE (operands
[2]) == CONST_INT
1047 && (unsigned) (- INTVAL (operands
[2])) < 64)
1048 return "subw2 $%n2,%0";
1049 return "addw2 %2,%0";
1051 if (rtx_equal_p (operands
[0], operands
[2]))
1052 return "addw2 %1,%0";
1053 if (GET_CODE (operands
[2]) == CONST_INT
1054 && (unsigned) (- INTVAL (operands
[2])) < 64)
1055 return "subw3 $%n2,%1,%0";
1056 return "addw3 %1,%2,%0";
1059 if (rtx_equal_p (operands
[0], operands
[1]))
1061 if (operands
[2] == const1_rtx
)
1063 if (operands
[2] == constm1_rtx
)
1065 if (GET_CODE (operands
[2]) == CONST_INT
1066 && (unsigned) (- INTVAL (operands
[2])) < 64)
1067 return "subb2 $%n2,%0";
1068 return "addb2 %2,%0";
1070 if (rtx_equal_p (operands
[0], operands
[2]))
1071 return "addb2 %1,%0";
1072 if (GET_CODE (operands
[2]) == CONST_INT
1073 && (unsigned) (- INTVAL (operands
[2])) < 64)
1074 return "subb3 $%n2,%1,%0";
1075 return "addb3 %1,%2,%0";
1082 /* Output a conditional branch. */
1084 vax_output_conditional_branch (enum rtx_code code
)
1088 case EQ
: return "jeql %l0";
1089 case NE
: return "jneq %l0";
1090 case GT
: return "jgtr %l0";
1091 case LT
: return "jlss %l0";
1092 case GTU
: return "jgtru %l0";
1093 case LTU
: return "jlssu %l0";
1094 case GE
: return "jgeq %l0";
1095 case LE
: return "jleq %l0";
1096 case GEU
: return "jgequ %l0";
1097 case LEU
: return "jlequ %l0";
1103 /* 1 if X is an rtx for a constant that is a valid address. */
1106 legitimate_constant_address_p (rtx x
)
1108 return (GET_CODE (x
) == LABEL_REF
|| GET_CODE (x
) == SYMBOL_REF
1109 || GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST
1110 || GET_CODE (x
) == HIGH
);
1113 /* Nonzero if the constant value X is a legitimate general operand.
1114 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1117 legitimate_constant_p (rtx x ATTRIBUTE_UNUSED
)
1122 /* The other macros defined here are used only in legitimate_address_p (). */
1124 /* Nonzero if X is a hard reg that can be used as an index
1125 or, if not strict, if it is a pseudo reg. */
1126 #define INDEX_REGISTER_P(X, STRICT) \
1127 (GET_CODE (X) == REG && (!(STRICT) || REGNO_OK_FOR_INDEX_P (REGNO (X))))
1129 /* Nonzero if X is a hard reg that can be used as a base reg
1130 or, if not strict, if it is a pseudo reg. */
1131 #define BASE_REGISTER_P(X, STRICT) \
1132 (GET_CODE (X) == REG && (!(STRICT) || REGNO_OK_FOR_BASE_P (REGNO (X))))
1134 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
1136 /* Re-definition of CONSTANT_ADDRESS_P, which is true only when there
1137 are no SYMBOL_REFs for external symbols present. */
1140 indirectable_constant_address_p (rtx x
)
1142 if (!CONSTANT_ADDRESS_P (x
))
1144 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP ((x
), 0)) == PLUS
)
1145 x
= XEXP (XEXP (x
, 0), 0);
1146 if (GET_CODE (x
) == SYMBOL_REF
&& !SYMBOL_REF_LOCAL_P (x
))
1152 #else /* not NO_EXTERNAL_INDIRECT_ADDRESS */
1155 indirectable_constant_address_p (rtx x
)
1157 return CONSTANT_ADDRESS_P (x
);
1160 #endif /* not NO_EXTERNAL_INDIRECT_ADDRESS */
1162 /* Nonzero if X is an address which can be indirected. External symbols
1163 could be in a sharable image library, so we disallow those. */
1166 indirectable_address_p(rtx x
, int strict
)
1168 if (indirectable_constant_address_p (x
))
1170 if (BASE_REGISTER_P (x
, strict
))
1172 if (GET_CODE (x
) == PLUS
1173 && BASE_REGISTER_P (XEXP (x
, 0), strict
)
1174 && indirectable_constant_address_p (XEXP (x
, 1)))
1179 /* Return 1 if x is a valid address not using indexing.
1180 (This much is the easy part.) */
1182 nonindexed_address_p (rtx x
, int strict
)
1185 if (GET_CODE (x
) == REG
)
1187 extern rtx
*reg_equiv_mem
;
1188 if (! reload_in_progress
1189 || reg_equiv_mem
[REGNO (x
)] == 0
1190 || indirectable_address_p (reg_equiv_mem
[REGNO (x
)], strict
))
1193 if (indirectable_constant_address_p (x
))
1195 if (indirectable_address_p (x
, strict
))
1197 xfoo0
= XEXP (x
, 0);
1198 if (GET_CODE (x
) == MEM
&& indirectable_address_p (xfoo0
, strict
))
1200 if ((GET_CODE (x
) == PRE_DEC
|| GET_CODE (x
) == POST_INC
)
1201 && BASE_REGISTER_P (xfoo0
, strict
))
1206 /* 1 if PROD is either a reg times size of mode MODE and MODE is less
1207 than or equal 8 bytes, or just a reg if MODE is one byte. */
1210 index_term_p (rtx prod
, enum machine_mode mode
, int strict
)
1214 if (GET_MODE_SIZE (mode
) == 1)
1215 return BASE_REGISTER_P (prod
, strict
);
1217 if (GET_CODE (prod
) != MULT
|| GET_MODE_SIZE (mode
) > 8)
1220 xfoo0
= XEXP (prod
, 0);
1221 xfoo1
= XEXP (prod
, 1);
1223 if (GET_CODE (xfoo0
) == CONST_INT
1224 && INTVAL (xfoo0
) == (int)GET_MODE_SIZE (mode
)
1225 && INDEX_REGISTER_P (xfoo1
, strict
))
1228 if (GET_CODE (xfoo1
) == CONST_INT
1229 && INTVAL (xfoo1
) == (int)GET_MODE_SIZE (mode
)
1230 && INDEX_REGISTER_P (xfoo0
, strict
))
1236 /* Return 1 if X is the sum of a register
1237 and a valid index term for mode MODE. */
1239 reg_plus_index_p (rtx x
, enum machine_mode mode
, int strict
)
1243 if (GET_CODE (x
) != PLUS
)
1246 xfoo0
= XEXP (x
, 0);
1247 xfoo1
= XEXP (x
, 1);
1249 if (BASE_REGISTER_P (xfoo0
, strict
) && index_term_p (xfoo1
, mode
, strict
))
1252 if (BASE_REGISTER_P (xfoo1
, strict
) && index_term_p (xfoo0
, mode
, strict
))
1258 /* legitimate_address_p returns 1 if it recognizes an RTL expression "x"
1259 that is a valid memory address for an instruction.
1260 The MODE argument is the machine mode for the MEM expression
1261 that wants to use this address. */
1263 legitimate_address_p (enum machine_mode mode
, rtx x
, int strict
)
1267 if (nonindexed_address_p (x
, strict
))
1270 if (GET_CODE (x
) != PLUS
)
1273 /* Handle <address>[index] represented with index-sum outermost */
1275 xfoo0
= XEXP (x
, 0);
1276 xfoo1
= XEXP (x
, 1);
1278 if (index_term_p (xfoo0
, mode
, strict
)
1279 && nonindexed_address_p (xfoo1
, strict
))
1282 if (index_term_p (xfoo1
, mode
, strict
)
1283 && nonindexed_address_p (xfoo0
, strict
))
1286 /* Handle offset(reg)[index] with offset added outermost */
1288 if (indirectable_constant_address_p (xfoo0
)
1289 && (BASE_REGISTER_P (xfoo1
, strict
)
1290 || reg_plus_index_p (xfoo1
, mode
, strict
)))
1293 if (indirectable_constant_address_p (xfoo1
)
1294 && (BASE_REGISTER_P (xfoo0
, strict
)
1295 || reg_plus_index_p (xfoo0
, mode
, strict
)))
1301 /* Return 1 if x (a legitimate address expression) has an effect that
1302 depends on the machine mode it is used for. On the VAX, the predecrement
1303 and postincrement address depend thus (the amount of decrement or
1304 increment being the length of the operand) and all indexed address depend
1305 thus (because the index scale factor is the length of the operand). */
1308 vax_mode_dependent_address_p (rtx x
)
1312 if (GET_CODE (x
) == POST_INC
|| GET_CODE (x
) == PRE_DEC
)
1314 if (GET_CODE (x
) != PLUS
)
1317 xfoo0
= XEXP (x
, 0);
1318 xfoo1
= XEXP (x
, 1);
1320 if (CONSTANT_ADDRESS_P (xfoo0
) && GET_CODE (xfoo1
) == REG
)
1322 if (CONSTANT_ADDRESS_P (xfoo1
) && GET_CODE (xfoo0
) == REG
)