gcc/config/vax/vax.md

   1 ;; Machine description for GNU compiler, Vax Version
   2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000
   3 ;; Free Software Foundation, Inc.
   4
   5 ;; This file is part of GNU CC.
   6
   7 ;; GNU CC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11
  12 ;; GNU CC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GNU CC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  20 ;; Boston, MA 02111-1307, USA.
  21
  22
  23 ;;- Instruction patterns.  When multiple patterns apply,
  24 ;;- the first one in the file is chosen.
  25 ;;-
  26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
  27 ;;-
  28 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
  29 ;;- updates for most instructions.
  30
  31 ;; We don't want to allow a constant operand for test insns because
  32 ;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
  33 ;; be folded while optimizing anyway.
  34
  35 (define_insn "tstsi"
  36   [(set (cc0)
  37         (match_operand:SI 0 "nonimmediate_operand" "g"))]
  38   ""
  39   "tstl %0")
  40
  41 (define_insn "tsthi"
  42   [(set (cc0)
  43         (match_operand:HI 0 "nonimmediate_operand" "g"))]
  44   ""
  45   "tstw %0")
  46
  47 (define_insn "tstqi"
  48   [(set (cc0)
  49         (match_operand:QI 0 "nonimmediate_operand" "g"))]
  50   ""
  51   "tstb %0")
  52
  53 (define_insn "tstdf"
  54   [(set (cc0)
  55         (match_operand:DF 0 "general_operand" "gF"))]
  56   ""
  57   "tst%# %0")
  58
  59 (define_insn "tstsf"
  60   [(set (cc0)
  61         (match_operand:SF 0 "general_operand" "gF"))]
  62   ""
  63   "tstf %0")
  64
  65 (define_insn "cmpsi"
  66   [(set (cc0)
  67         (compare (match_operand:SI 0 "nonimmediate_operand" "g")
  68                  (match_operand:SI 1 "general_operand" "g")))]
  69   ""
  70   "cmpl %0,%1")
  71
  72 (define_insn "cmphi"
  73   [(set (cc0)
  74         (compare (match_operand:HI 0 "nonimmediate_operand" "g")
  75                  (match_operand:HI 1 "general_operand" "g")))]
  76   ""
  77   "cmpw %0,%1")
  78
  79 (define_insn "cmpqi"
  80   [(set (cc0)
  81         (compare (match_operand:QI 0 "nonimmediate_operand" "g")
  82                  (match_operand:QI 1 "general_operand" "g")))]
  83   ""
  84   "cmpb %0,%1")
  85
  86 (define_insn "cmpdf"
  87   [(set (cc0)
  88         (compare (match_operand:DF 0 "general_operand" "gF,gF")
  89                  (match_operand:DF 1 "general_operand" "G,gF")))]
  90   ""
  91   "@
  92    tst%# %0
  93    cmp%# %0,%1")
  94
  95 (define_insn "cmpsf"
  96   [(set (cc0)
  97         (compare (match_operand:SF 0 "general_operand" "gF,gF")
  98                  (match_operand:SF 1 "general_operand" "G,gF")))]
  99   ""
 100   "@
 101    tstf %0
 102    cmpf %0,%1")
 103
 104 (define_insn ""
 105   [(set (cc0)
 106         (and:SI (match_operand:SI 0 "general_operand" "g")
 107                 (match_operand:SI 1 "general_operand" "g")))]
 108   ""
 109   "bitl %0,%1")
 110
 111 (define_insn ""
 112   [(set (cc0)
 113         (and:HI (match_operand:HI 0 "general_operand" "g")
 114                 (match_operand:HI 1 "general_operand" "g")))]
 115   ""
 116   "bitw %0,%1")
 117
 118 (define_insn ""
 119   [(set (cc0)
 120         (and:QI (match_operand:QI 0 "general_operand" "g")
 121                 (match_operand:QI 1 "general_operand" "g")))]
 122   ""
 123   "bitb %0,%1")
 124
 125 ;; The vax has no sCOND insns.  It does have add/subtract with carry
 126 ;; which could be used to implement the sltu and sgeu patterns.  However,
 127 ;; to do this properly requires a complete rewrite of the compare insns
 128 ;; to keep them together with the sltu/sgeu insns until after the
 129 ;; reload pass is complete.  The previous implementation didn't do this
 130 ;; and has been deleted.
 131
 132 \f
 133 (define_insn "movdf"
 134   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
 135         (match_operand:DF 1 "general_operand" "G,gF"))]
 136   ""
 137   "@
 138    clr%# %0
 139    mov%# %1,%0")
 140
 141 (define_insn "movsf"
 142   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
 143         (match_operand:SF 1 "general_operand" "G,gF"))]
 144   ""
 145   "@
 146    clrf %0
 147    movf %1,%0")
 148
 149 ;; Some vaxes don't support this instruction.
 150 ;;(define_insn "movti"
 151 ;;  [(set (match_operand:TI 0 "general_operand" "=g")
 152 ;;      (match_operand:TI 1 "general_operand" "g"))]
 153 ;;  ""
 154 ;;  "movh %1,%0")
 155
 156 (define_insn "movdi"
 157   [(set (match_operand:DI 0 "nonimmediate_operand" "=g,g")
 158         (match_operand:DI 1 "general_operand" "I,g"))]
 159   ""
 160   "@
 161    clrq %0
 162    movq %D1,%0")
 163
 164 ;; The VAX move instructions have space-time tradeoffs.  On a microVAX
 165 ;; register-register mov instructions take 3 bytes and 2 CPU cycles.  clrl
 166 ;; takes 2 bytes and 3 cycles.  mov from constant to register takes 2 cycles
 167 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
 168 ;; constant.  movz, mneg, and mcom are as fast as mov, so movzwl is faster
 169 ;; than movl for positive constants that fit in 16 bits but not 6 bits.  cvt
 170 ;; instructions take 4 cycles.  inc takes 3 cycles.  The machine description
 171 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
 172 ;; instead of movl).
 173
 174 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
 175 ;; but on a VAX 9000 most move and add instructions with one constant
 176 ;; operand take 1 cycle).
 177
 178 ;;  Loads of constants between 64 and 128 used to be done with
 179 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
 180
 181 (define_insn "movsi"
 182   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 183         (match_operand:SI 1 "general_operand" "g"))]
 184   ""
 185   "*
 186 {
 187   rtx link;
 188   if (operands[1] == const1_rtx
 189       && (link = find_reg_note (insn, REG_WAS_0, 0))
 190       /* Make sure the insn that stored the 0 is still present.  */
 191       && ! INSN_DELETED_P (XEXP (link, 0))
 192       && GET_CODE (XEXP (link, 0)) != NOTE
 193       /* Make sure cross jumping didn't happen here.  */
 194       && no_labels_between_p (XEXP (link, 0), insn)
 195       /* Make sure the reg hasn't been clobbered.  */
 196       && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
 197     return \"incl %0\";
 198   if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
 199     {
 200       if (push_operand (operands[0], SImode))
 201         return \"pushab %a1\";
 202       return \"movab %a1,%0\";
 203     }
 204   if (operands[1] == const0_rtx)
 205     return \"clrl %0\";
 206   if (GET_CODE (operands[1]) == CONST_INT
 207       && (unsigned) INTVAL (operands[1]) >= 64)
 208     {
 209       int i = INTVAL (operands[1]);
 210       if ((unsigned)(~i) < 64)
 211         return \"mcoml %N1,%0\";
 212       if ((unsigned)i < 0x100)
 213         return \"movzbl %1,%0\";
 214       if (i >= -0x80 && i < 0)
 215         return \"cvtbl %1,%0\";
 216       if ((unsigned)i < 0x10000)
 217         return \"movzwl %1,%0\";
 218       if (i >= -0x8000 && i < 0)
 219         return \"cvtwl %1,%0\";
 220     }
 221   if (push_operand (operands[0], SImode))
 222     return \"pushl %1\";
 223   return \"movl %1,%0\";
 224 }")
 225
 226 (define_insn "movhi"
 227   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 228         (match_operand:HI 1 "general_operand" "g"))]
 229   ""
 230   "*
 231 {
 232   rtx link;
 233   if (operands[1] == const1_rtx
 234       && (link = find_reg_note (insn, REG_WAS_0, 0))
 235       /* Make sure the insn that stored the 0 is still present.  */
 236       && ! INSN_DELETED_P (XEXP (link, 0))
 237       && GET_CODE (XEXP (link, 0)) != NOTE
 238       /* Make sure cross jumping didn't happen here.  */
 239       && no_labels_between_p (XEXP (link, 0), insn)
 240       /* Make sure the reg hasn't been clobbered.  */
 241       && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
 242     return \"incw %0\";
 243
 244   if (GET_CODE (operands[1]) == CONST_INT)
 245     {
 246       int i = INTVAL (operands[1]);
 247       if (i == 0)
 248         return \"clrw %0\";
 249       else if ((unsigned int)i < 64)
 250         return \"movw %1,%0\";
 251       else if ((unsigned int)~i < 64)
 252         return \"mcomw %H1,%0\";
 253       else if ((unsigned int)i < 256)
 254         return \"movzbw %1,%0\";
 255     }
 256   return \"movw %1,%0\";
 257 }")
 258
 259 (define_insn "movstricthi"
 260   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
 261         (match_operand:HI 1 "general_operand" "g"))]
 262   ""
 263   "*
 264 {
 265   if (GET_CODE (operands[1]) == CONST_INT)
 266     {
 267       int i = INTVAL (operands[1]);
 268       if (i == 0)
 269         return \"clrw %0\";
 270       else if ((unsigned int)i < 64)
 271         return \"movw %1,%0\";
 272       else if ((unsigned int)~i < 64)
 273         return \"mcomw %H1,%0\";
 274       else if ((unsigned int)i < 256)
 275         return \"movzbw %1,%0\";
 276     }
 277   return \"movw %1,%0\";
 278 }")
 279
 280 (define_insn "movqi"
 281   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 282         (match_operand:QI 1 "general_operand" "g"))]
 283   ""
 284   "*
 285 {
 286   rtx link;
 287   if (operands[1] == const1_rtx
 288       && (link = find_reg_note (insn, REG_WAS_0, 0))
 289       /* Make sure the insn that stored the 0 is still present.  */
 290       && ! INSN_DELETED_P (XEXP (link, 0))
 291       && GET_CODE (XEXP (link, 0)) != NOTE
 292       /* Make sure cross jumping didn't happen here.  */
 293       && no_labels_between_p (XEXP (link, 0), insn)
 294       /* Make sure the reg hasn't been clobbered.  */
 295       && ! reg_set_between_p (operands[0], XEXP (link, 0), insn))
 296     return \"incb %0\";
 297
 298   if (GET_CODE (operands[1]) == CONST_INT)
 299     {
 300       int i = INTVAL (operands[1]);
 301       if (i == 0)
 302         return \"clrb %0\";
 303       else if ((unsigned int)~i < 64)
 304         return \"mcomb %B1,%0\";
 305     }
 306   return \"movb %1,%0\";
 307 }")
 308
 309 (define_insn "movstrictqi"
 310   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
 311         (match_operand:QI 1 "general_operand" "g"))]
 312   ""
 313   "*
 314 {
 315   if (GET_CODE (operands[1]) == CONST_INT)
 316     {
 317       int i = INTVAL (operands[1]);
 318       if (i == 0)
 319         return \"clrb %0\";
 320       else if ((unsigned int)~i < 64)
 321         return \"mcomb %B1,%0\";
 322     }
 323   return \"movb %1,%0\";
 324 }")
 325
 326 ;; This is here to accept 4 arguments and pass the first 3 along
 327 ;; to the movstrhi1 pattern that really does the work.
 328 (define_expand "movstrhi"
 329   [(set (match_operand:BLK 0 "general_operand" "=g")
 330         (match_operand:BLK 1 "general_operand" "g"))
 331    (use (match_operand:HI 2 "general_operand" "g"))
 332    (match_operand 3 "" "")]
 333   ""
 334   "
 335   emit_insn (gen_movstrhi1 (operands[0], operands[1], operands[2]));
 336   DONE;
 337 ")
 338
 339 ;; The definition of this insn does not really explain what it does,
 340 ;; but it should suffice
 341 ;; that anything generated as this insn will be recognized as one
 342 ;; and that it won't successfully combine with anything.
 343 (define_insn "movstrhi1"
 344   [(set (match_operand:BLK 0 "memory_operand" "=m")
 345         (match_operand:BLK 1 "memory_operand" "m"))
 346    (use (match_operand:HI 2 "general_operand" "g"))
 347    (clobber (reg:SI 0))
 348    (clobber (reg:SI 1))
 349    (clobber (reg:SI 2))
 350    (clobber (reg:SI 3))
 351    (clobber (reg:SI 4))
 352    (clobber (reg:SI 5))]
 353   ""
 354   "movc3 %2,%1,%0")
 355 \f
 356 ;; Extension and truncation insns.
 357
 358 (define_insn "truncsiqi2"
 359   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 360         (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
 361   ""
 362   "cvtlb %1,%0")
 363
 364 (define_insn "truncsihi2"
 365   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 366         (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
 367   ""
 368   "cvtlw %1,%0")
 369
 370 (define_insn "trunchiqi2"
 371   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 372         (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
 373   ""
 374   "cvtwb %1,%0")
 375
 376 (define_insn "extendhisi2"
 377   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 378         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
 379   ""
 380   "cvtwl %1,%0")
 381
 382 (define_insn "extendqihi2"
 383   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 384         (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
 385   ""
 386   "cvtbw %1,%0")
 387
 388 (define_insn "extendqisi2"
 389   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 390         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
 391   ""
 392   "cvtbl %1,%0")
 393
 394 (define_insn "extendsfdf2"
 395   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
 396         (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
 397   ""
 398   "cvtf%# %1,%0")
 399
 400 (define_insn "truncdfsf2"
 401   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
 402         (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
 403   ""
 404   "cvt%#f %1,%0")
 405
 406 (define_insn "zero_extendhisi2"
 407   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 408         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
 409   ""
 410   "movzwl %1,%0")
 411
 412 (define_insn "zero_extendqihi2"
 413   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 414         (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
 415   ""
 416   "movzbw %1,%0")
 417
 418 (define_insn "zero_extendqisi2"
 419   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 420         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
 421   ""
 422   "movzbl %1,%0")
 423 \f
 424 ;; Fix-to-float conversion insns.
 425
 426 (define_insn "floatsisf2"
 427   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
 428         (float:SF (match_operand:SI 1 "nonimmediate_operand" "g")))]
 429   ""
 430   "cvtlf %1,%0")
 431
 432 (define_insn "floatsidf2"
 433   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
 434         (float:DF (match_operand:SI 1 "nonimmediate_operand" "g")))]
 435   ""
 436   "cvtl%# %1,%0")
 437
 438 (define_insn "floathisf2"
 439   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
 440         (float:SF (match_operand:HI 1 "nonimmediate_operand" "g")))]
 441   ""
 442   "cvtwf %1,%0")
 443
 444 (define_insn "floathidf2"
 445   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
 446         (float:DF (match_operand:HI 1 "nonimmediate_operand" "g")))]
 447   ""
 448   "cvtw%# %1,%0")
 449
 450 (define_insn "floatqisf2"
 451   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
 452         (float:SF (match_operand:QI 1 "nonimmediate_operand" "g")))]
 453   ""
 454   "cvtbf %1,%0")
 455
 456 (define_insn "floatqidf2"
 457   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
 458         (float:DF (match_operand:QI 1 "nonimmediate_operand" "g")))]
 459   ""
 460   "cvtb%# %1,%0")
 461 \f
 462 ;; Float-to-fix conversion insns.
 463
 464 (define_insn "fix_truncsfqi2"
 465   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 466         (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
 467   ""
 468   "cvtfb %1,%0")
 469
 470 (define_insn "fix_truncsfhi2"
 471   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 472         (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
 473   ""
 474   "cvtfw %1,%0")
 475
 476 (define_insn "fix_truncsfsi2"
 477   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 478         (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
 479   ""
 480   "cvtfl %1,%0")
 481
 482 (define_insn "fix_truncdfqi2"
 483   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 484         (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
 485   ""
 486   "cvt%#b %1,%0")
 487
 488 (define_insn "fix_truncdfhi2"
 489   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 490         (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
 491   ""
 492   "cvt%#w %1,%0")
 493
 494 (define_insn "fix_truncdfsi2"
 495   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 496         (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
 497   ""
 498   "cvt%#l %1,%0")
 499 \f
 500 ;;- All kinds of add instructions.
 501
 502 (define_insn "adddf3"
 503   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g,g")
 504         (plus:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
 505                  (match_operand:DF 2 "general_operand" "gF,0,gF")))]
 506   ""
 507   "@
 508    add%#2 %2,%0
 509    add%#2 %1,%0
 510    add%#3 %1,%2,%0")
 511
 512 (define_insn "addsf3"
 513   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g,g")
 514         (plus:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
 515                  (match_operand:SF 2 "general_operand" "gF,0,gF")))]
 516   ""
 517   "@
 518    addf2 %2,%0
 519    addf2 %1,%0
 520    addf3 %1,%2,%0")
 521
 522 /* The space-time-opcode tradeoffs for addition vary by model of VAX.
 523
 524    On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
 525    but it not faster on other models.
 526
 527    "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
 528    faster on a VAX 3, but some VAXes (e.g. VAX 9000) will stall if
 529    a register is used in an address too soon after it is set.
 530    Compromise by using movab only when it is shorter than the add
 531    or the base register in the address is one of sp, ap, and fp,
 532    which are not modified very often.  */
 533
 534
 535 (define_insn "addsi3"
 536   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 537         (plus:SI (match_operand:SI 1 "general_operand" "g")
 538                  (match_operand:SI 2 "general_operand" "g")))]
 539   ""
 540   "*
 541 {
 542   if (rtx_equal_p (operands[0], operands[1]))
 543     {
 544       if (operands[2] == const1_rtx)
 545         return \"incl %0\";
 546       if (operands[2] == constm1_rtx)
 547         return \"decl %0\";
 548       if (GET_CODE (operands[2]) == CONST_INT
 549           && (unsigned) (- INTVAL (operands[2])) < 64)
 550         return \"subl2 $%n2,%0\";
 551       if (GET_CODE (operands[2]) == CONST_INT
 552           && (unsigned) INTVAL (operands[2]) >= 64
 553           && GET_CODE (operands[1]) == REG
 554           && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
 555               || REGNO (operands[1]) > 11))
 556         return \"movab %c2(%1),%0\";
 557       return \"addl2 %2,%0\";
 558     }
 559   if (rtx_equal_p (operands[0], operands[2]))
 560     return \"addl2 %1,%0\";
 561
 562   if (GET_CODE (operands[2]) == CONST_INT
 563       && INTVAL (operands[2]) < 32767
 564       && INTVAL (operands[2]) > -32768
 565       && GET_CODE (operands[1]) == REG
 566       && push_operand (operands[0], SImode))
 567     return \"pushab %c2(%1)\";
 568
 569   if (GET_CODE (operands[2]) == CONST_INT
 570       && (unsigned) (- INTVAL (operands[2])) < 64)
 571     return \"subl3 $%n2,%1,%0\";
 572
 573   if (GET_CODE (operands[2]) == CONST_INT
 574       && (unsigned) INTVAL (operands[2]) >= 64
 575       && GET_CODE (operands[1]) == REG
 576       && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
 577           || REGNO (operands[1]) > 11))
 578     return \"movab %c2(%1),%0\";
 579
 580   /* Add this if using gcc on a VAX 3xxx:
 581   if (REG_P (operands[1]) && REG_P (operands[2]))
 582     return \"movab (%1)[%2],%0\";
 583   */
 584   return \"addl3 %1,%2,%0\";
 585 }")
 586
 587 (define_insn "addhi3"
 588   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 589         (plus:HI (match_operand:HI 1 "general_operand" "g")
 590                  (match_operand:HI 2 "general_operand" "g")))]
 591   ""
 592   "*
 593 {
 594   if (rtx_equal_p (operands[0], operands[1]))
 595     {
 596       if (operands[2] == const1_rtx)
 597         return \"incw %0\";
 598       if (operands[2] == constm1_rtx)
 599         return \"decw %0\";
 600       if (GET_CODE (operands[2]) == CONST_INT
 601           && (unsigned) (- INTVAL (operands[2])) < 64)
 602         return \"subw2 $%n2,%0\";
 603       return \"addw2 %2,%0\";
 604     }
 605   if (rtx_equal_p (operands[0], operands[2]))
 606     return \"addw2 %1,%0\";
 607   if (GET_CODE (operands[2]) == CONST_INT
 608       && (unsigned) (- INTVAL (operands[2])) < 64)
 609     return \"subw3 $%n2,%1,%0\";
 610   return \"addw3 %1,%2,%0\";
 611 }")
 612
 613 (define_insn "addqi3"
 614   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 615         (plus:QI (match_operand:QI 1 "general_operand" "g")
 616                  (match_operand:QI 2 "general_operand" "g")))]
 617   ""
 618   "*
 619 {
 620   if (rtx_equal_p (operands[0], operands[1]))
 621     {
 622       if (operands[2] == const1_rtx)
 623         return \"incb %0\";
 624       if (operands[2] == constm1_rtx)
 625         return \"decb %0\";
 626       if (GET_CODE (operands[2]) == CONST_INT
 627           && (unsigned) (- INTVAL (operands[2])) < 64)
 628         return \"subb2 $%n2,%0\";
 629       return \"addb2 %2,%0\";
 630     }
 631   if (rtx_equal_p (operands[0], operands[2]))
 632     return \"addb2 %1,%0\";
 633   if (GET_CODE (operands[2]) == CONST_INT
 634       && (unsigned) (- INTVAL (operands[2])) < 64)
 635     return \"subb3 $%n2,%1,%0\";
 636   return \"addb3 %1,%2,%0\";
 637 }")
 638
 639 ;; The add-with-carry (adwc) instruction only accepts two operands.
 640 (define_insn "adddi3"
 641   [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
 642         (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
 643                  (match_operand:DI 2 "general_operand" "Fro,F")))]
 644   ""
 645   "*
 646 {
 647   rtx low[3];
 648   const char *pattern;
 649   int carry = 1;
 650
 651   split_quadword_operands (operands, low, 3);
 652   /* Add low parts.  */
 653   if (rtx_equal_p (operands[0], operands[1]))
 654     {
 655       if (low[2] == const0_rtx)
 656         /* Should examine operand, punt if not POST_INC.  */
 657         pattern = \"tstl %0\", carry = 0;
 658       else if (low[2] == const1_rtx)
 659         pattern = \"incl %0\";
 660       else
 661         pattern = \"addl2 %2,%0\";
 662     }
 663   else
 664     {
 665       if (low[2] == const0_rtx)
 666         pattern = \"movl %1,%0\", carry = 0;
 667       else
 668         pattern = \"addl3 %2,%1,%0\";
 669     }
 670   if (pattern)
 671     output_asm_insn (pattern, low);
 672   if (!carry)
 673     /* If CARRY is 0, we don't have any carry value to worry about.  */
 674     return get_insn_template (CODE_FOR_addsi3, insn);
 675   /* %0 = C + %1 + %2 */
 676   if (!rtx_equal_p (operands[0], operands[1]))
 677     output_asm_insn ((operands[1] == const0_rtx
 678                       ? \"clrl %0\"
 679                       : \"movl %1,%0\"), operands);
 680   return \"adwc %2,%0\";
 681 }")
 682 \f
 683 ;;- All kinds of subtract instructions.
 684
 685 (define_insn "subdf3"
 686   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
 687         (minus:DF (match_operand:DF 1 "general_operand" "0,gF")
 688                   (match_operand:DF 2 "general_operand" "gF,gF")))]
 689   ""
 690   "@
 691    sub%#2 %2,%0
 692    sub%#3 %2,%1,%0")
 693
 694 (define_insn "subsf3"
 695   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
 696         (minus:SF (match_operand:SF 1 "general_operand" "0,gF")
 697                   (match_operand:SF 2 "general_operand" "gF,gF")))]
 698   ""
 699   "@
 700    subf2 %2,%0
 701    subf3 %2,%1,%0")
 702
 703 (define_insn "subsi3"
 704   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
 705         (minus:SI (match_operand:SI 1 "general_operand" "0,g")
 706                   (match_operand:SI 2 "general_operand" "g,g")))]
 707   ""
 708   "@
 709    subl2 %2,%0
 710    subl3 %2,%1,%0")
 711
 712 (define_insn "subhi3"
 713   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
 714         (minus:HI (match_operand:HI 1 "general_operand" "0,g")
 715                   (match_operand:HI 2 "general_operand" "g,g")))]
 716   ""
 717   "@
 718    subw2 %2,%0
 719    subw3 %2,%1,%0")
 720
 721 (define_insn "subqi3"
 722   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
 723         (minus:QI (match_operand:QI 1 "general_operand" "0,g")
 724                   (match_operand:QI 2 "general_operand" "g,g")))]
 725   ""
 726   "@
 727    subb2 %2,%0
 728    subb3 %2,%1,%0")
 729
 730 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
 731 (define_insn "subdi3"
 732   [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
 733         (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
 734                   (match_operand:DI 2 "general_operand" "For,F")))]
 735   ""
 736   "*
 737 {
 738   rtx low[3];
 739   const char *pattern;
 740   int carry = 1;
 741
 742   split_quadword_operands (operands, low, 3);
 743   /* Subtract low parts.  */
 744   if (rtx_equal_p (operands[0], operands[1]))
 745     {
 746       if (low[2] == const0_rtx)
 747         pattern = 0, carry = 0;
 748       else if (low[2] == constm1_rtx)
 749         pattern = \"decl %0\";
 750       else
 751         pattern = \"subl2 %2,%0\";
 752     }
 753   else
 754     {
 755       if (low[2] == constm1_rtx)
 756         pattern = \"decl %0\";
 757       else if (low[2] == const0_rtx)
 758         pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0;
 759       else
 760         pattern = \"subl3 %2,%1,%0\";
 761     }
 762   if (pattern)
 763     output_asm_insn (pattern, low);
 764   if (carry)
 765     {
 766       if (!rtx_equal_p (operands[0], operands[1]))
 767         return \"movl %1,%0\;sbwc %2,%0\";
 768       return \"sbwc %2,%0\";
 769       /* %0 = %2 - %1 - C */
 770     }
 771   return get_insn_template (CODE_FOR_subsi3, insn);
 772 }")
 773 \f
 774 ;;- Multiply instructions.
 775
 776 (define_insn "muldf3"
 777   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g,g")
 778         (mult:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
 779                  (match_operand:DF 2 "general_operand" "gF,0,gF")))]
 780   ""
 781   "@
 782    mul%#2 %2,%0
 783    mul%#2 %1,%0
 784    mul%#3 %1,%2,%0")
 785
 786 (define_insn "mulsf3"
 787   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g,g")
 788         (mult:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
 789                  (match_operand:SF 2 "general_operand" "gF,0,gF")))]
 790   ""
 791   "@
 792    mulf2 %2,%0
 793    mulf2 %1,%0
 794    mulf3 %1,%2,%0")
 795
 796 (define_insn "mulsi3"
 797   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
 798         (mult:SI (match_operand:SI 1 "general_operand" "0,g,g")
 799                  (match_operand:SI 2 "general_operand" "g,0,g")))]
 800   ""
 801   "@
 802    mull2 %2,%0
 803    mull2 %1,%0
 804    mull3 %1,%2,%0")
 805
 806 (define_insn "mulhi3"
 807   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,")
 808         (mult:HI (match_operand:HI 1 "general_operand" "0,g,g")
 809                  (match_operand:HI 2 "general_operand" "g,0,g")))]
 810   ""
 811   "@
 812    mulw2 %2,%0
 813    mulw2 %1,%0
 814    mulw3 %1,%2,%0")
 815
 816 (define_insn "mulqi3"
 817   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
 818         (mult:QI (match_operand:QI 1 "general_operand" "0,g,g")
 819                  (match_operand:QI 2 "general_operand" "g,0,g")))]
 820   ""
 821   "@
 822    mulb2 %2,%0
 823    mulb2 %1,%0
 824    mulb3 %1,%2,%0")
 825
 826 (define_insn "mulsidi3"
 827   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 828         (mult:DI (sign_extend:DI
 829                   (match_operand:SI 1 "nonimmediate_operand" "g"))
 830                  (sign_extend:DI
 831                   (match_operand:SI 2 "nonimmediate_operand" "g"))))]
 832   ""
 833   "emul %1,%2,$0,%0")
 834
 835 (define_insn ""
 836   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 837         (plus:DI
 838          (mult:DI (sign_extend:DI
 839                    (match_operand:SI 1 "nonimmediate_operand" "g"))
 840                   (sign_extend:DI
 841                    (match_operand:SI 2 "nonimmediate_operand" "g")))
 842          (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
 843   ""
 844   "emul %1,%2,%3,%0")
 845
 846 ;; 'F' constraint means type CONST_DOUBLE
 847 (define_insn ""
 848   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 849         (plus:DI
 850          (mult:DI (sign_extend:DI
 851                    (match_operand:SI 1 "nonimmediate_operand" "g"))
 852                   (sign_extend:DI
 853                    (match_operand:SI 2 "nonimmediate_operand" "g")))
 854          (match_operand:DI 3 "immediate_operand" "F")))]
 855   "GET_CODE (operands[3]) == CONST_DOUBLE
 856     && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
 857   "*
 858 {
 859   if (CONST_DOUBLE_HIGH (operands[3]))
 860     operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
 861   return \"emul %1,%2,%3,%0\";
 862 }")
 863 \f
 864 ;;- Divide instructions.
 865
 866 (define_insn "divdf3"
 867   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
 868         (div:DF (match_operand:DF 1 "general_operand" "0,gF")
 869                 (match_operand:DF 2 "general_operand" "gF,gF")))]
 870   ""
 871   "@
 872    div%#2 %2,%0
 873    div%#3 %2,%1,%0")
 874
 875 (define_insn "divsf3"
 876   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
 877         (div:SF (match_operand:SF 1 "general_operand" "0,gF")
 878                 (match_operand:SF 2 "general_operand" "gF,gF")))]
 879   ""
 880   "@
 881    divf2 %2,%0
 882    divf3 %2,%1,%0")
 883
 884 (define_insn "divsi3"
 885   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
 886         (div:SI (match_operand:SI 1 "general_operand" "0,g")
 887                 (match_operand:SI 2 "general_operand" "g,g")))]
 888   ""
 889   "@
 890    divl2 %2,%0
 891    divl3 %2,%1,%0")
 892
 893 (define_insn "divhi3"
 894   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
 895         (div:HI (match_operand:HI 1 "general_operand" "0,g")
 896                 (match_operand:HI 2 "general_operand" "g,g")))]
 897   ""
 898   "@
 899    divw2 %2,%0
 900    divw3 %2,%1,%0")
 901
 902 (define_insn "divqi3"
 903   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
 904         (div:QI (match_operand:QI 1 "general_operand" "0,g")
 905                 (match_operand:QI 2 "general_operand" "g,g")))]
 906   ""
 907   "@
 908    divb2 %2,%0
 909    divb3 %2,%1,%0")
 910
 911 ;This is left out because it is very slow;
 912 ;we are better off programming around the "lack" of this insn.
 913 ;(define_insn "divmoddisi4"
 914 ;  [(set (match_operand:SI 0 "general_operand" "=g")
 915 ;       (div:SI (match_operand:DI 1 "general_operand" "g")
 916 ;               (match_operand:SI 2 "general_operand" "g")))
 917 ;   (set (match_operand:SI 3 "general_operand" "=g")
 918 ;       (mod:SI (match_operand:DI 1 "general_operand" "g")
 919 ;               (match_operand:SI 2 "general_operand" "g")))]
 920 ;  ""
 921 ;  "ediv %2,%1,%0,%3")
 922 \f
 923 ;; Bit-and on the vax is done with a clear-bits insn.
 924 (define_expand "andsi3"
 925   [(set (match_operand:SI 0 "general_operand" "=g")
 926         (and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
 927                 (match_operand:SI 2 "general_operand" "g")))]
 928   ""
 929   "
 930 {
 931   rtx op1 = operands[1];
 932
 933   /* If there is a constant argument, complement that one.  */
 934   if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
 935     {
 936       operands[1] = operands[2];
 937       operands[2] = op1;
 938       op1 = operands[1];
 939     }
 940
 941   if (GET_CODE (op1) == CONST_INT)
 942     operands[1] = GEN_INT (~INTVAL (op1));
 943   else
 944     operands[1] = expand_unop (SImode, one_cmpl_optab, op1, 0, 1);
 945 }")
 946
 947 (define_expand "andhi3"
 948   [(set (match_operand:HI 0 "general_operand" "=g")
 949         (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
 950                 (match_operand:HI 2 "general_operand" "g")))]
 951   ""
 952   "
 953 {
 954   rtx op1 = operands[1];
 955
 956   if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
 957     {
 958       operands[1] = operands[2];
 959       operands[2] = op1;
 960       op1 = operands[1];
 961     }
 962
 963   if (GET_CODE (op1) == CONST_INT)
 964     operands[1] = GEN_INT (65535 & ~INTVAL (op1));
 965   else
 966     operands[1] = expand_unop (HImode, one_cmpl_optab, op1, 0, 1);
 967 }")
 968
 969 (define_expand "andqi3"
 970   [(set (match_operand:QI 0 "general_operand" "=g")
 971         (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
 972                 (match_operand:QI 2 "general_operand" "g")))]
 973   ""
 974   "
 975 {
 976   rtx op1 = operands[1];
 977
 978   if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
 979     {
 980      operands[1] = operands[2];
 981      operands[2] = op1;
 982      op1 = operands[1];
 983    }
 984
 985   if (GET_CODE (op1) == CONST_INT)
 986     operands[1] = GEN_INT (255 & ~INTVAL (op1));
 987   else
 988     operands[1] = expand_unop (QImode, one_cmpl_optab, op1, 0, 1);
 989 }")
 990
 991 (define_insn ""
 992   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
 993         (and:SI (not:SI (match_operand:SI 1 "general_operand" "g,g"))
 994                 (match_operand:SI 2 "general_operand" "0,g")))]
 995   ""
 996   "@
 997    bicl2 %1,%0
 998    bicl3 %1,%2,%0")
 999
1000 (define_insn ""
1001   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
1002         (and:HI (not:HI (match_operand:HI 1 "general_operand" "g,g"))
1003                 (match_operand:HI 2 "general_operand" "0,g")))]
1004   ""
1005   "@
1006    bicw2 %1,%0
1007    bicw3 %1,%2,%0")
1008
1009 (define_insn ""
1010   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
1011         (and:QI (not:QI (match_operand:QI 1 "general_operand" "g,g"))
1012                 (match_operand:QI 2 "general_operand" "0,g")))]
1013   ""
1014   "@
1015    bicb2 %1,%0
1016    bicb3 %1,%2,%0")
1017
1018 ;; The following used to be needed because constant propagation can
1019 ;; create them starting from the bic insn patterns above.  This is no
1020 ;; longer a problem.  However, having these patterns allows optimization
1021 ;; opportunities in combine.c.
1022
1023 (define_insn ""
1024   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
1025         (and:SI (match_operand:SI 1 "general_operand" "0,g")
1026                 (match_operand:SI 2 "const_int_operand" "n,n")))]
1027   ""
1028   "@
1029    bicl2 %N2,%0
1030    bicl3 %N2,%1,%0")
1031
1032 (define_insn ""
1033   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
1034         (and:HI (match_operand:HI 1 "general_operand" "0,g")
1035                 (match_operand:HI 2 "const_int_operand" "n,n")))]
1036   ""
1037   "@
1038    bicw2 %H2,%0
1039    bicw3 %H2,%1,%0")
1040
1041 (define_insn ""
1042   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
1043         (and:QI (match_operand:QI 1 "general_operand" "0,g")
1044                 (match_operand:QI 2 "const_int_operand" "n,n")))]
1045   ""
1046   "@
1047    bicb2 %B2,%0
1048    bicb3 %B2,%1,%0")
1049 \f
1050 ;;- Bit set instructions.
1051
1052 (define_insn "iorsi3"
1053   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
1054         (ior:SI (match_operand:SI 1 "general_operand" "0,g,g")
1055                 (match_operand:SI 2 "general_operand" "g,0,g")))]
1056   ""
1057   "@
1058    bisl2 %2,%0
1059    bisl2 %1,%0
1060    bisl3 %2,%1,%0")
1061
1062 (define_insn "iorhi3"
1063   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,g")
1064         (ior:HI (match_operand:HI 1 "general_operand" "0,g,g")
1065                 (match_operand:HI 2 "general_operand" "g,0,g")))]
1066   ""
1067   "@
1068    bisw2 %2,%0
1069    bisw2 %1,%0
1070    bisw3 %2,%1,%0")
1071
1072 (define_insn "iorqi3"
1073   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
1074         (ior:QI (match_operand:QI 1 "general_operand" "0,g,g")
1075                 (match_operand:QI 2 "general_operand" "g,0,g")))]
1076   ""
1077   "@
1078    bisb2 %2,%0
1079    bisb2 %1,%0
1080    bisb3 %2,%1,%0")
1081
1082 ;;- xor instructions.
1083
1084 (define_insn "xorsi3"
1085   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
1086         (xor:SI (match_operand:SI 1 "general_operand" "0,g,g")
1087                 (match_operand:SI 2 "general_operand" "g,0,g")))]
1088   ""
1089   "@
1090    xorl2 %2,%0
1091    xorl2 %1,%0
1092    xorl3 %2,%1,%0")
1093
1094 (define_insn "xorhi3"
1095   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,g")
1096         (xor:HI (match_operand:HI 1 "general_operand" "0,g,g")
1097                 (match_operand:HI 2 "general_operand" "g,0,g")))]
1098   ""
1099   "@
1100    xorw2 %2,%0
1101    xorw2 %1,%0
1102    xorw3 %2,%1,%0")
1103
1104 (define_insn "xorqi3"
1105   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
1106         (xor:QI (match_operand:QI 1 "general_operand" "0,g,g")
1107                 (match_operand:QI 2 "general_operand" "g,0,g")))]
1108   ""
1109   "@
1110    xorb2 %2,%0
1111    xorb2 %1,%0
1112    xorb3 %2,%1,%0")
1113 \f
1114 (define_insn "negdf2"
1115   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
1116         (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1117   ""
1118   "mneg%# %1,%0")
1119
1120 (define_insn "negsf2"
1121   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
1122         (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1123   ""
1124   "mnegf %1,%0")
1125
1126 (define_insn "negsi2"
1127   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1128         (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1129   ""
1130   "mnegl %1,%0")
1131
1132 (define_insn "neghi2"
1133   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1134         (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1135   ""
1136   "mnegw %1,%0")
1137
1138 (define_insn "negqi2"
1139   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
1140         (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1141   ""
1142   "mnegb %1,%0")
1143 \f
1144 (define_insn "one_cmplsi2"
1145   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1146         (not:SI (match_operand:SI 1 "general_operand" "g")))]
1147   ""
1148   "mcoml %1,%0")
1149
1150 (define_insn "one_cmplhi2"
1151   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1152         (not:HI (match_operand:HI 1 "general_operand" "g")))]
1153   ""
1154   "mcomw %1,%0")
1155
1156 (define_insn "one_cmplqi2"
1157   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
1158         (not:QI (match_operand:QI 1 "general_operand" "g")))]
1159   ""
1160   "mcomb %1,%0")
1161 \f
1162 ;; Arithmetic right shift on the vax works by negating the shift count,
1163 ;; then emitting a right shift with the shift count negated.  This means
1164 ;; that all actual shift counts in the RTL will be positive.  This
1165 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1166 ;; which isn't valid.
1167 (define_expand "ashrsi3"
1168   [(set (match_operand:SI 0 "general_operand" "=g")
1169         (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1170                    (match_operand:QI 2 "general_operand" "g")))]
1171   ""
1172   "
1173 {
1174   if (GET_CODE (operands[2]) != CONST_INT)
1175     operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1176 }")
1177
1178 (define_insn ""
1179   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1180         (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1181                      (match_operand:QI 2 "const_int_operand" "n")))]
1182   ""
1183   "ashl $%n2,%1,%0")
1184
1185 (define_insn ""
1186   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1187         (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1188                      (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1189   ""
1190   "ashl %2,%1,%0")
1191
1192 (define_insn "ashlsi3"
1193   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1194         (ashift:SI (match_operand:SI 1 "general_operand" "g")
1195                    (match_operand:QI 2 "general_operand" "g")))]
1196   ""
1197   "*
1198 {
1199   if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1200     return \"addl2 %0,%0\";
1201   if (GET_CODE (operands[1]) == REG
1202       && GET_CODE (operands[2]) == CONST_INT)
1203     {
1204       int i = INTVAL (operands[2]);
1205       if (i == 1)
1206         return \"addl3 %1,%1,%0\";
1207       if (i == 2)
1208         return \"moval 0[%1],%0\";
1209       if (i == 3)
1210         return \"movad 0[%1],%0\";
1211     }
1212   return \"ashl %2,%1,%0\";
1213 }")
1214
1215 ;; Arithmetic right shift on the vax works by negating the shift count.
1216 (define_expand "ashrdi3"
1217   [(set (match_operand:DI 0 "general_operand" "=g")
1218         (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1219                      (match_operand:QI 2 "general_operand" "g")))]
1220   ""
1221   "
1222 {
1223   operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1224 }")
1225
1226 (define_insn "ashldi3"
1227   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1228         (ashift:DI (match_operand:DI 1 "general_operand" "g")
1229                    (match_operand:QI 2 "general_operand" "g")))]
1230   ""
1231   "ashq %2,%1,%0")
1232
1233 (define_insn ""
1234   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1235         (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1236                      (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1237   ""
1238   "ashq %2,%1,%0")
1239
1240 ;; We used to have expand_shift handle logical right shifts by using extzv,
1241 ;; but this make it very difficult to do lshrdi3.  Since the VAX is the
1242 ;; only machine with this kludge, it's better to just do this with a
1243 ;; define_expand and remove that case from expand_shift.
1244
1245 (define_expand "lshrsi3"
1246   [(set (match_dup 3)
1247         (minus:QI (const_int 32)
1248                   (match_dup 4)))
1249    (set (match_operand:SI 0 "general_operand" "=g")
1250         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1251                          (match_dup 3)
1252                          (match_operand:SI 2 "register_operand" "g")))]
1253   ""
1254   "
1255 {
1256   operands[3] = gen_reg_rtx (QImode);
1257   operands[4] = gen_lowpart (QImode, operands[2]);
1258 }")
1259
1260 ;; Rotate right on the vax works by negating the shift count.
1261 (define_expand "rotrsi3"
1262   [(set (match_operand:SI 0 "general_operand" "=g")
1263         (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1264                      (match_operand:QI 2 "general_operand" "g")))]
1265   ""
1266   "
1267 {
1268   if (GET_CODE (operands[2]) != CONST_INT)
1269     operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1270 }")
1271
1272 (define_insn "rotlsi3"
1273   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1274         (rotate:SI (match_operand:SI 1 "general_operand" "g")
1275                    (match_operand:QI 2 "general_operand" "g")))]
1276   ""
1277   "rotl %2,%1,%0")
1278
1279 (define_insn ""
1280   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1281         (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1282                      (match_operand:QI 2 "const_int_operand" "n")))]
1283   ""
1284   "rotl %R2,%1,%0")
1285
1286 (define_insn ""
1287   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1288         (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1289                      (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1290   ""
1291   "rotl %2,%1,%0")
1292
1293 ;This insn is probably slower than a multiply and an add.
1294 ;(define_insn ""
1295 ;  [(set (match_operand:SI 0 "general_operand" "=g")
1296 ;       (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1297 ;                         (match_operand:SI 2 "general_operand" "g"))
1298 ;                (match_operand:SI 3 "general_operand" "g")))]
1299 ;  ""
1300 ;  "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1301 \f
1302 ;; Special cases of bit-field insns which we should
1303 ;; recognize in preference to the general case.
1304 ;; These handle aligned 8-bit and 16-bit fields,
1305 ;; which can usually be done with move instructions.
1306
1307 (define_insn ""
1308   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
1309                          (match_operand:QI 1 "const_int_operand" "n")
1310                          (match_operand:SI 2 "const_int_operand" "n"))
1311         (match_operand:SI 3 "general_operand" "g"))]
1312    "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1313    && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1314    && (GET_CODE (operands[0]) == REG
1315        || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1316   "*
1317 {
1318   if (REG_P (operands[0]))
1319     {
1320       if (INTVAL (operands[2]) != 0)
1321         return \"insv %3,%2,%1,%0\";
1322     }
1323   else
1324     operands[0]
1325       = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
1326
1327   CC_STATUS_INIT;
1328   if (INTVAL (operands[1]) == 8)
1329     return \"movb %3,%0\";
1330   return \"movw %3,%0\";
1331 }")
1332
1333 (define_insn ""
1334   [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
1335         (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1336                          (match_operand:QI 2 "const_int_operand" "n")
1337                          (match_operand:SI 3 "const_int_operand" "n")))]
1338   "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1339    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1340    && (GET_CODE (operands[1]) == REG
1341        || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1342   "*
1343 {
1344   if (REG_P (operands[1]))
1345     {
1346       if (INTVAL (operands[3]) != 0)
1347         return \"extzv %3,%2,%1,%0\";
1348     }
1349   else
1350     operands[1]
1351       = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1352
1353   if (INTVAL (operands[2]) == 8)
1354     return \"movzbl %1,%0\";
1355   return \"movzwl %1,%0\";
1356 }")
1357
1358 (define_insn ""
1359   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1360         (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1361                          (match_operand:QI 2 "const_int_operand" "n")
1362                          (match_operand:SI 3 "const_int_operand" "n")))]
1363   "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1364    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1365    && (GET_CODE (operands[1]) == REG
1366        || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1367   "*
1368 {
1369   if (REG_P (operands[1]))
1370     {
1371       if (INTVAL (operands[3]) != 0)
1372         return \"extv %3,%2,%1,%0\";
1373     }
1374   else
1375     operands[1]
1376       = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1377
1378   if (INTVAL (operands[2]) == 8)
1379     return \"cvtbl %1,%0\";
1380   return \"cvtwl %1,%0\";
1381 }")
1382 \f
1383 ;; Register-only SImode cases of bit-field insns.
1384
1385 (define_insn ""
1386   [(set (cc0)
1387         (compare
1388          (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1389                           (match_operand:QI 1 "general_operand" "g")
1390                           (match_operand:SI 2 "general_operand" "g"))
1391          (match_operand:SI 3 "general_operand" "g")))]
1392   ""
1393   "cmpv %2,%1,%0,%3")
1394
1395 (define_insn ""
1396   [(set (cc0)
1397         (compare
1398          (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1399                           (match_operand:QI 1 "general_operand" "g")
1400                           (match_operand:SI 2 "general_operand" "g"))
1401          (match_operand:SI 3 "general_operand" "g")))]
1402   ""
1403   "cmpzv %2,%1,%0,%3")
1404
1405 ;; When the field position and size are constant and the destination
1406 ;; is a register, extv and extzv are much slower than a rotate followed
1407 ;; by a bicl or sign extension.  Because we might end up choosing ext[z]v
1408 ;; anyway, we can't allow immediate values for the primary source operand.
1409
1410 (define_insn ""
1411   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1412         (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1413                          (match_operand:QI 2 "general_operand" "g")
1414                          (match_operand:SI 3 "general_operand" "g")))]
1415   ""
1416   "*
1417 {
1418   if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1419       || GET_CODE (operands[0]) != REG
1420       || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
1421     return \"extv %3,%2,%1,%0\";
1422   if (INTVAL (operands[2]) == 8)
1423     return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1424   return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1425 }")
1426
1427 (define_insn ""
1428   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1429         (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1430                          (match_operand:QI 2 "general_operand" "g")
1431                          (match_operand:SI 3 "general_operand" "g")))]
1432   ""
1433   "*
1434 {
1435   if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1436       || GET_CODE (operands[0]) != REG)
1437     return \"extzv %3,%2,%1,%0\";
1438   if (INTVAL (operands[2]) == 8)
1439     return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1440   if (INTVAL (operands[2]) == 16)
1441     return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1442   if (INTVAL (operands[3]) & 31)
1443     return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1444   if (rtx_equal_p (operands[0], operands[1]))
1445     return \"bicl2 %M2,%0\";
1446   return \"bicl3 %M2,%1,%0\";
1447 }")
1448
1449 ;; Non-register cases.
1450 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1451 ;; don't match these (and therefore match the cases above instead).
1452
1453 (define_insn ""
1454   [(set (cc0)
1455         (compare
1456          (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
1457                           (match_operand:QI 1 "general_operand" "g")
1458                           (match_operand:SI 2 "general_operand" "g"))
1459          (match_operand:SI 3 "general_operand" "g")))]
1460   ""
1461   "cmpv %2,%1,%0,%3")
1462
1463 (define_insn ""
1464   [(set (cc0)
1465         (compare
1466          (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1467                           (match_operand:QI 1 "general_operand" "g")
1468                           (match_operand:SI 2 "general_operand" "g"))
1469          (match_operand:SI 3 "general_operand" "g")))]
1470   ""
1471   "cmpzv %2,%1,%0,%3")
1472
1473 (define_insn "extv"
1474   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1475         (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
1476                          (match_operand:QI 2 "general_operand" "g")
1477                          (match_operand:SI 3 "general_operand" "g")))]
1478   ""
1479   "*
1480 {
1481   if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1482       || GET_CODE (operands[3]) != CONST_INT
1483       || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
1484       || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1485       || side_effects_p (operands[1])
1486       || (GET_CODE (operands[1]) == MEM
1487           && mode_dependent_address_p (XEXP (operands[1], 0))))
1488     return \"extv %3,%2,%1,%0\";
1489   if (INTVAL (operands[2]) == 8)
1490     return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1491   return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1492 }")
1493
1494 (define_expand "extzv"
1495   [(set (match_operand:SI 0 "general_operand" "")
1496         (zero_extract:SI (match_operand:SI 1 "general_operand" "")
1497                          (match_operand:QI 2 "general_operand" "")
1498                          (match_operand:SI 3 "general_operand" "")))]
1499   ""
1500   "")
1501
1502 (define_insn ""
1503   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1504         (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
1505                          (match_operand:QI 2 "general_operand" "g")
1506                          (match_operand:SI 3 "general_operand" "g")))]
1507   ""
1508   "*
1509 {
1510   if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1511       || GET_CODE (operands[3]) != CONST_INT
1512       || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1513       || side_effects_p (operands[1])
1514       || (GET_CODE (operands[1]) == MEM
1515           && mode_dependent_address_p (XEXP (operands[1], 0))))
1516     return \"extzv %3,%2,%1,%0\";
1517   if (INTVAL (operands[2]) == 8)
1518     return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1519   if (INTVAL (operands[2]) == 16)
1520     return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1521   return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1522 }")
1523
1524 (define_expand "insv"
1525   [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
1526                          (match_operand:QI 1 "general_operand" "")
1527                          (match_operand:SI 2 "general_operand" ""))
1528         (match_operand:SI 3 "general_operand" ""))]
1529   ""
1530   "")
1531
1532 (define_insn ""
1533   [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
1534                          (match_operand:QI 1 "general_operand" "g")
1535                          (match_operand:SI 2 "general_operand" "g"))
1536         (match_operand:SI 3 "general_operand" "g"))]
1537   ""
1538   "insv %3,%2,%1,%0")
1539
1540 (define_insn ""
1541   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1542                          (match_operand:QI 1 "general_operand" "g")
1543                          (match_operand:SI 2 "general_operand" "g"))
1544         (match_operand:SI 3 "general_operand" "g"))]
1545   ""
1546   "insv %3,%2,%1,%0")
1547 \f
1548 (define_insn "jump"
1549   [(set (pc)
1550         (label_ref (match_operand 0 "" "")))]
1551   ""
1552   "jbr %l0")
1553
1554 (define_insn "beq"
1555   [(set (pc)
1556         (if_then_else (eq (cc0)
1557                           (const_int 0))
1558                       (label_ref (match_operand 0 "" ""))
1559                       (pc)))]
1560   ""
1561   "jeql %l0")
1562
1563 (define_insn "bne"
1564   [(set (pc)
1565         (if_then_else (ne (cc0)
1566                           (const_int 0))
1567                       (label_ref (match_operand 0 "" ""))
1568                       (pc)))]
1569   ""
1570   "jneq %l0")
1571
1572 (define_insn "bgt"
1573   [(set (pc)
1574         (if_then_else (gt (cc0)
1575                           (const_int 0))
1576                       (label_ref (match_operand 0 "" ""))
1577                       (pc)))]
1578   ""
1579   "jgtr %l0")
1580
1581 (define_insn "bgtu"
1582   [(set (pc)
1583         (if_then_else (gtu (cc0)
1584                            (const_int 0))
1585                       (label_ref (match_operand 0 "" ""))
1586                       (pc)))]
1587   ""
1588   "jgtru %l0")
1589
1590 (define_insn "blt"
1591   [(set (pc)
1592         (if_then_else (lt (cc0)
1593                           (const_int 0))
1594                       (label_ref (match_operand 0 "" ""))
1595                       (pc)))]
1596   ""
1597   "jlss %l0")
1598
1599 (define_insn "bltu"
1600   [(set (pc)
1601         (if_then_else (ltu (cc0)
1602                            (const_int 0))
1603                       (label_ref (match_operand 0 "" ""))
1604                       (pc)))]
1605   ""
1606   "jlssu %l0")
1607
1608 (define_insn "bge"
1609   [(set (pc)
1610         (if_then_else (ge (cc0)
1611                           (const_int 0))
1612                       (label_ref (match_operand 0 "" ""))
1613                       (pc)))]
1614   ""
1615   "jgeq %l0")
1616
1617 (define_insn "bgeu"
1618   [(set (pc)
1619         (if_then_else (geu (cc0)
1620                            (const_int 0))
1621                       (label_ref (match_operand 0 "" ""))
1622                       (pc)))]
1623   ""
1624   "jgequ %l0")
1625
1626 (define_insn "ble"
1627   [(set (pc)
1628         (if_then_else (le (cc0)
1629                           (const_int 0))
1630                       (label_ref (match_operand 0 "" ""))
1631                       (pc)))]
1632   ""
1633   "jleq %l0")
1634
1635 (define_insn "bleu"
1636   [(set (pc)
1637         (if_then_else (leu (cc0)
1638                            (const_int 0))
1639                       (label_ref (match_operand 0 "" ""))
1640                       (pc)))]
1641   ""
1642   "jlequ %l0")
1643
1644 ;; Recognize reversed jumps.
1645 (define_insn ""
1646   [(set (pc)
1647         (if_then_else (match_operator 0 "comparison_operator"
1648                                       [(cc0)
1649                                        (const_int 0)])
1650                       (pc)
1651                       (label_ref (match_operand 1 "" ""))))]
1652   ""
1653   "j%C0 %l1") ; %C0 negates condition
1654 \f
1655 ;; Recognize jbs, jlbs, jbc and jlbc instructions.  Note that the operand
1656 ;; of jlbs and jlbc insns are SImode in the hardware.  However, if it is
1657 ;; memory, we use QImode in the insn.  So we can't use those instructions
1658 ;; for mode-dependent addresses.
1659
1660 (define_insn ""
1661   [(set (pc)
1662         (if_then_else
1663          (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1664                               (const_int 1)
1665                               (match_operand:SI 1 "general_operand" "I,g"))
1666              (const_int 0))
1667          (label_ref (match_operand 2 "" ""))
1668          (pc)))]
1669   ""
1670   "@
1671    jlbs %0,%l2
1672    jbs %1,%0,%l2")
1673
1674 (define_insn ""
1675   [(set (pc)
1676         (if_then_else
1677          (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1678                               (const_int 1)
1679                               (match_operand:SI 1 "general_operand" "I,g"))
1680              (const_int 0))
1681          (label_ref (match_operand 2 "" ""))
1682          (pc)))]
1683   ""
1684   "@
1685    jlbc %0,%l2
1686    jbc %1,%0,%l2")
1687
1688 (define_insn ""
1689   [(set (pc)
1690         (if_then_else
1691          (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1692                               (const_int 1)
1693                               (match_operand:SI 1 "general_operand" "I,g"))
1694              (const_int 0))
1695          (label_ref (match_operand 2 "" ""))
1696          (pc)))]
1697   ""
1698   "@
1699    jlbs %0,%l2
1700    jbs %1,%0,%l2")
1701
1702 (define_insn ""
1703   [(set (pc)
1704         (if_then_else
1705          (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1706                               (const_int 1)
1707                               (match_operand:SI 1 "general_operand" "I,g"))
1708              (const_int 0))
1709          (label_ref (match_operand 2 "" ""))
1710          (pc)))]
1711   ""
1712   "@
1713    jlbc %0,%l2
1714    jbc %1,%0,%l2")
1715 \f
1716 ;; Subtract-and-jump and Add-and-jump insns.
1717 ;; These are not used when output is for the Unix assembler
1718 ;; because it does not know how to modify them to reach far.
1719
1720 ;; Normal sob insns.
1721
1722 (define_insn ""
1723   [(set (pc)
1724         (if_then_else
1725          (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1726                       (const_int -1))
1727              (const_int 0))
1728          (label_ref (match_operand 1 "" ""))
1729          (pc)))
1730    (set (match_dup 0)
1731         (plus:SI (match_dup 0)
1732                  (const_int -1)))]
1733   "!TARGET_UNIX_ASM"
1734   "jsobgtr %0,%l1")
1735
1736 (define_insn ""
1737   [(set (pc)
1738         (if_then_else
1739          (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1740                       (const_int -1))
1741              (const_int 0))
1742          (label_ref (match_operand 1 "" ""))
1743          (pc)))
1744    (set (match_dup 0)
1745         (plus:SI (match_dup 0)
1746                  (const_int -1)))]
1747   "!TARGET_UNIX_ASM"
1748   "jsobgeq %0,%l1")
1749
1750 ;; Normal aob insns.  Define a version for when operands[1] is a constant.
1751 (define_insn ""
1752   [(set (pc)
1753         (if_then_else
1754          (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1755                       (const_int 1))
1756              (match_operand:SI 1 "general_operand" "g"))
1757          (label_ref (match_operand 2 "" ""))
1758          (pc)))
1759    (set (match_dup 0)
1760         (plus:SI (match_dup 0)
1761                  (const_int 1)))]
1762   "!TARGET_UNIX_ASM"
1763   "jaoblss %1,%0,%l2")
1764
1765 (define_insn ""
1766   [(set (pc)
1767         (if_then_else
1768          (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1769              (match_operand:SI 1 "general_operand" "g"))
1770          (label_ref (match_operand 2 "" ""))
1771          (pc)))
1772    (set (match_dup 0)
1773         (plus:SI (match_dup 0)
1774                  (const_int 1)))]
1775   "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1776   "jaoblss %P1,%0,%l2")
1777
1778 (define_insn ""
1779   [(set (pc)
1780         (if_then_else
1781          (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1782                       (const_int 1))
1783              (match_operand:SI 1 "general_operand" "g"))
1784          (label_ref (match_operand 2 "" ""))
1785          (pc)))
1786    (set (match_dup 0)
1787         (plus:SI (match_dup 0)
1788                  (const_int 1)))]
1789   "!TARGET_UNIX_ASM"
1790   "jaobleq %1,%0,%l2")
1791
1792 (define_insn ""
1793   [(set (pc)
1794         (if_then_else
1795          (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1796              (match_operand:SI 1 "general_operand" "g"))
1797          (label_ref (match_operand 2 "" ""))
1798          (pc)))
1799    (set (match_dup 0)
1800         (plus:SI (match_dup 0)
1801                  (const_int 1)))]
1802   "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1803   "jaobleq %P1,%0,%l2")
1804
1805 ;; Something like a sob insn, but compares against -1.
1806 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1807
1808 (define_insn ""
1809   [(set (pc)
1810         (if_then_else
1811          (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1812              (const_int 0))
1813          (label_ref (match_operand 1 "" ""))
1814          (pc)))
1815    (set (match_dup 0)
1816         (plus:SI (match_dup 0)
1817                  (const_int -1)))]
1818   ""
1819   "decl %0\;jgequ %l1")
1820 \f
1821 ;; Note that operand 1 is total size of args, in bytes,
1822 ;; and what the call insn wants is the number of words.
1823 ;; It is used in the call instruction as a byte, but in the addl2 as
1824 ;; a word.  Since the only time we actually use it in the call instruction
1825 ;; is when it is a constant, SImode (for addl2) is the proper mode.
1826 (define_expand "call_pop"
1827   [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1828                     (match_operand:SI 1 "const_int_operand" ""))
1829               (set (reg:SI 14)
1830                    (plus:SI (reg:SI 14)
1831                             (match_operand:SI 3 "immediate_operand" "")))])]
1832   ""
1833   "
1834 {
1835   if (INTVAL (operands[1]) > 255 * 4)
1836     abort ();
1837   operands[1] = GEN_INT ((INTVAL (operands[1]) + 3)/ 4);
1838 }")
1839
1840 (define_insn "*call_pop"
1841   [(call (match_operand:QI 0 "memory_operand" "m")
1842          (match_operand:SI 1 "const_int_operand" "n"))
1843    (set (reg:SI 14) (plus:SI (reg:SI 14)
1844                              (match_operand:SI 2 "immediate_operand" "i")))]
1845   ""
1846   "calls %1,%0")
1847
1848 (define_expand "call_value_pop"
1849   [(parallel [(set (match_operand 0 "" "")
1850                    (call (match_operand:QI 1 "memory_operand" "")
1851                          (match_operand:SI 2 "const_int_operand" "")))
1852               (set (reg:SI 14)
1853                    (plus:SI (reg:SI 14)
1854                             (match_operand:SI 4 "immediate_operand" "")))])]
1855   ""
1856   "
1857 {
1858   if (INTVAL (operands[2]) > 255 * 4)
1859     abort ();
1860   operands[2] = GEN_INT ((INTVAL (operands[2]) + 3)/ 4);
1861 }")
1862
1863 (define_insn "*call_value_pop"
1864   [(set (match_operand 0 "" "")
1865         (call (match_operand:QI 1 "memory_operand" "m")
1866               (match_operand:SI 2 "const_int_operand" "n")))
1867    (set (reg:SI 14) (plus:SI (reg:SI 14)
1868                              (match_operand:SI 3 "immediate_operand" "i")))]
1869   ""
1870   "calls %2,%1")
1871
1872 ;; Define another set of these for the case of functions with no operands.
1873 ;; These will allow the optimizers to do a slightly better job.
1874 (define_insn "call"
1875   [(call (match_operand:QI 0 "memory_operand" "m")
1876          (const_int 0))]
1877   ""
1878   "calls $0,%0")
1879
1880 (define_insn "call_value"
1881   [(set (match_operand 0 "" "")
1882         (call (match_operand:QI 1 "memory_operand" "m")
1883               (const_int 0)))]
1884   ""
1885   "calls $0,%1")
1886
1887 ;; Call subroutine returning any type.
1888
1889 (define_expand "untyped_call"
1890   [(parallel [(call (match_operand 0 "" "")
1891                   (const_int 0))
1892             (match_operand 1 "" "")
1893             (match_operand 2 "" "")])]
1894   ""
1895   "
1896 {
1897   int i;
1898
1899   emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1900
1901   for (i = 0; i < XVECLEN (operands[2], 0); i++)
1902     {
1903       rtx set = XVECEXP (operands[2], 0, i);
1904       emit_move_insn (SET_DEST (set), SET_SRC (set));
1905     }
1906
1907   /* The optimizer does not know that the call sets the function value
1908      registers we stored in the result block.  We avoid problems by
1909      claiming that all hard registers are used and clobbered at this
1910      point.  */
1911   emit_insn (gen_blockage ());
1912
1913   DONE;
1914 }")
1915
1916 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1917 ;; all of memory.  This blocks insns from being moved across this point.
1918
1919 (define_insn "blockage"
1920   [(unspec_volatile [(const_int 0)] 0)]
1921   ""
1922   "")
1923
1924 (define_insn "return"
1925   [(return)]
1926   ""
1927   "ret")
1928
1929 (define_insn "nop"
1930   [(const_int 0)]
1931   ""
1932   "nop")
1933
1934 ;; This had a wider constraint once, and it had trouble.
1935 ;; If you are tempted to try `g', please don't--it's not worth
1936 ;; the risk we will reopen the same bug.
1937 (define_insn "indirect_jump"
1938   [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1939   ""
1940   "jmp (%0)")
1941
1942 ;; This is here to accept 5 arguments (as passed by expand_end_case)
1943 ;; and pass the first 4 along to the casesi1 pattern that really does the work.
1944 (define_expand "casesi"
1945   [(set (pc)
1946         (if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
1947                                      (match_operand:SI 1 "general_operand" "g"))
1948                            (match_operand:SI 2 "general_operand" "g"))
1949                       (plus:SI (sign_extend:SI
1950                                 (mem:HI
1951                                  (plus:SI (pc)
1952                                           (mult:SI (minus:SI (match_dup 0)
1953                                                              (match_dup 1))
1954                                                    (const_int 2)))))
1955                                (label_ref:SI (match_operand 3 "" "")))
1956                       (pc)))
1957    (match_operand 4 "" "")]
1958   ""
1959   "
1960   emit_insn (gen_casesi1 (operands[0], operands[1], operands[2], operands[3]));
1961   DONE;
1962 ")
1963
1964 (define_insn "casesi1"
1965   [(set (pc)
1966         (if_then_else (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
1967                                      (match_operand:SI 1 "general_operand" "g"))
1968                            (match_operand:SI 2 "general_operand" "g"))
1969                       (plus:SI (sign_extend:SI
1970                                 (mem:HI
1971                                  (plus:SI (pc)
1972                                           (mult:SI (minus:SI (match_dup 0)
1973                                                              (match_dup 1))
1974                                                    (const_int 2)))))
1975                                (label_ref:SI (match_operand 3 "" "")))
1976                       (pc)))]
1977   ""
1978   "casel %0,%1,%2")
1979
1980 ;; This used to arise from the preceding by simplification
1981 ;; if operand 1 is zero.  Perhaps it is no longer necessary.
1982 (define_insn ""
1983   [(set (pc)
1984         (if_then_else (leu (match_operand:SI 0 "general_operand" "g")
1985                            (match_operand:SI 1 "general_operand" "g"))
1986                       (plus:SI (sign_extend:SI
1987                                 (mem:HI
1988                                  (plus:SI (pc)
1989                                           (mult:SI (minus:SI (match_dup 0)
1990                                                              (const_int 0))
1991                                                    (const_int 2)))))
1992                                (label_ref:SI (match_operand 2 "" "")))
1993                       (pc)))]
1994   ""
1995   "casel %0,$0,%1")
1996 \f
1997 ;;- load or push effective address
1998 ;; These come after the move and add/sub patterns
1999 ;; because we don't want pushl $1 turned into pushad 1.
2000 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
2001
2002 ;; It does not work to use constraints to distinguish pushes from moves,
2003 ;; because < matches any autodecrement, not just a push.
2004
2005 (define_insn ""
2006   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2007         (match_operand:QI 1 "address_operand" "p"))]
2008   ""
2009   "*
2010 {
2011   if (push_operand (operands[0], SImode))
2012     return \"pushab %a1\";
2013   else
2014     return \"movab %a1,%0\";
2015 }")
2016
2017 (define_insn ""
2018   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2019         (match_operand:HI 1 "address_operand" "p"))]
2020   ""
2021   "*
2022 {
2023   if (push_operand (operands[0], SImode))
2024     return \"pushaw %a1\";
2025   else
2026     return \"movaw %a1,%0\";
2027 }")
2028
2029 (define_insn ""
2030   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2031         (match_operand:SI 1 "address_operand" "p"))]
2032   ""
2033   "*
2034 {
2035   if (push_operand (operands[0], SImode))
2036     return \"pushal %a1\";
2037   else
2038     return \"moval %a1,%0\";
2039 }")
2040
2041 (define_insn ""
2042   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2043         (match_operand:DI 1 "address_operand" "p"))]
2044   ""
2045   "*
2046 {
2047   if (push_operand (operands[0], SImode))
2048     return \"pushaq %a1\";
2049   else
2050     return \"movaq %a1,%0\";
2051 }")
2052
2053 (define_insn ""
2054   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2055         (match_operand:SF 1 "address_operand" "p"))]
2056   ""
2057   "*
2058 {
2059   if (push_operand (operands[0], SImode))
2060     return \"pushaf %a1\";
2061   else
2062     return \"movaf %a1,%0\";
2063 }")
2064
2065 (define_insn ""
2066   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2067         (match_operand:DF 1 "address_operand" "p"))]
2068   ""
2069   "*
2070 {
2071   if (push_operand (operands[0], SImode))
2072     return \"pushad %a1\";
2073   else
2074     return \"movad %a1,%0\";
2075 }")
2076 \f
2077 ;; These used to be peepholes, but it is more straightforward to do them
2078 ;; as single insns.  However, we must force the output to be a register
2079 ;; if it is not an offsettable address so that we know that we can assign
2080 ;; to it twice.
2081
2082 ;; If we had a good way of evaluating the relative costs, these could be
2083 ;; machine-independent.
2084
2085 ;; Optimize   extzv ...,z;    andl2 ...,z
2086 ;; or         ashl ...,z;     andl2 ...,z
2087 ;; with other operands constant.  This is what the combiner converts the
2088 ;; above sequences to before attempting to recognize the new insn.
2089
2090 (define_insn ""
2091   [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2092         (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
2093                              (match_operand:QI 2 "const_int_operand" "n"))
2094                 (match_operand:SI 3 "const_int_operand" "n")))]
2095   "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
2096   "*
2097 {
2098   unsigned long mask1 = INTVAL (operands[3]);
2099   unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
2100
2101   if ((mask1 & mask2) != mask1)
2102     operands[3] = GEN_INT (mask1 & mask2);
2103
2104   return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
2105 }")
2106
2107 ;; left-shift and mask
2108 ;; The only case where `ashl' is better is if the mask only turns off
2109 ;; bits that the ashl would anyways, in which case it should have been
2110 ;; optimized away.
2111
2112 (define_insn ""
2113   [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2114         (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
2115                            (match_operand:QI 2 "const_int_operand" "n"))
2116                 (match_operand:SI 3 "const_int_operand" "n")))]
2117   ""
2118   "*
2119 {
2120   operands[3]
2121     = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
2122   return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
2123 }")