1 ;; Machine description for GNU compiler, VAX Version
2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
3 ;; 2002, 2004, 2005 Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
23 ;;- Instruction patterns. When multiple patterns apply,
24 ;;- the first one in the file is chosen.
26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
29 ;;- updates for most instructions.
31 ;; UNSPEC_VOLATILE usage:
34 [(VUNSPEC_BLOCKAGE 0) ; `blockage' insn to prevent scheduling across an
36 (VUNSPEC_SYNC_ISTREAM 1) ; sequence of insns to sync the I-stream
40 ;; We don't want to allow a constant operand for test insns because
41 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
42 ;; be folded while optimizing anyway.
46 (match_operand:SI 0 "nonimmediate_operand" "g"))]
52 (match_operand:HI 0 "nonimmediate_operand" "g"))]
58 (match_operand:QI 0 "nonimmediate_operand" "g"))]
64 (match_operand:DF 0 "general_operand" "gF"))]
70 (match_operand:SF 0 "general_operand" "gF"))]
76 (compare (match_operand:SI 0 "nonimmediate_operand" "g")
77 (match_operand:SI 1 "general_operand" "g")))]
83 (compare (match_operand:HI 0 "nonimmediate_operand" "g")
84 (match_operand:HI 1 "general_operand" "g")))]
90 (compare (match_operand:QI 0 "nonimmediate_operand" "g")
91 (match_operand:QI 1 "general_operand" "g")))]
97 (compare (match_operand:DF 0 "general_operand" "gF,gF")
98 (match_operand:DF 1 "general_operand" "G,gF")))]
106 (compare (match_operand:SF 0 "general_operand" "gF,gF")
107 (match_operand:SF 1 "general_operand" "G,gF")))]
115 (and:SI (match_operand:SI 0 "general_operand" "g")
116 (match_operand:SI 1 "general_operand" "g")))]
122 (and:HI (match_operand:HI 0 "general_operand" "g")
123 (match_operand:HI 1 "general_operand" "g")))]
129 (and:QI (match_operand:QI 0 "general_operand" "g")
130 (match_operand:QI 1 "general_operand" "g")))]
134 ;; The VAX has no sCOND insns. It does have add/subtract with carry
135 ;; which could be used to implement the sltu and sgeu patterns. However,
136 ;; to do this properly requires a complete rewrite of the compare insns
137 ;; to keep them together with the sltu/sgeu insns until after the
138 ;; reload pass is complete. The previous implementation didn't do this
139 ;; and has been deleted.
143 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
144 (match_operand:DF 1 "general_operand" "G,gF"))]
151 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
152 (match_operand:SF 1 "general_operand" "G,gF"))]
158 ;; Some VAXen don't support this instruction.
159 ;;(define_insn "movti"
160 ;; [(set (match_operand:TI 0 "general_operand" "=g")
161 ;; (match_operand:TI 1 "general_operand" "g"))]
166 [(set (match_operand:DI 0 "nonimmediate_operand" "=g,g")
167 (match_operand:DI 1 "general_operand" "I,g"))]
173 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
174 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
175 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
176 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
177 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
178 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
179 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description
180 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
183 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
184 ;; but on a VAX 9000 most move and add instructions with one constant
185 ;; operand take 1 cycle).
187 ;; Loads of constants between 64 and 128 used to be done with
188 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
191 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
192 (match_operand:SI 1 "general_operand" "g"))]
196 if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
198 if (push_operand (operands[0], SImode))
199 return \"pushab %a1\";
200 return \"movab %a1,%0\";
202 if (operands[1] == const0_rtx)
204 if (GET_CODE (operands[1]) == CONST_INT
205 && (unsigned) INTVAL (operands[1]) >= 64)
207 int i = INTVAL (operands[1]);
208 if ((unsigned)(~i) < 64)
209 return \"mcoml %N1,%0\";
210 if ((unsigned)i < 0x100)
211 return \"movzbl %1,%0\";
212 if (i >= -0x80 && i < 0)
213 return \"cvtbl %1,%0\";
214 if ((unsigned)i < 0x10000)
215 return \"movzwl %1,%0\";
216 if (i >= -0x8000 && i < 0)
217 return \"cvtwl %1,%0\";
219 if (push_operand (operands[0], SImode))
221 return \"movl %1,%0\";
225 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
226 (match_operand:HI 1 "general_operand" "g"))]
230 if (GET_CODE (operands[1]) == CONST_INT)
232 int i = INTVAL (operands[1]);
235 else if ((unsigned int)i < 64)
236 return \"movw %1,%0\";
237 else if ((unsigned int)~i < 64)
238 return \"mcomw %H1,%0\";
239 else if ((unsigned int)i < 256)
240 return \"movzbw %1,%0\";
242 return \"movw %1,%0\";
245 (define_insn "movstricthi"
246 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
247 (match_operand:HI 1 "general_operand" "g"))]
251 if (GET_CODE (operands[1]) == CONST_INT)
253 int i = INTVAL (operands[1]);
256 else if ((unsigned int)i < 64)
257 return \"movw %1,%0\";
258 else if ((unsigned int)~i < 64)
259 return \"mcomw %H1,%0\";
260 else if ((unsigned int)i < 256)
261 return \"movzbw %1,%0\";
263 return \"movw %1,%0\";
267 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
268 (match_operand:QI 1 "general_operand" "g"))]
272 if (GET_CODE (operands[1]) == CONST_INT)
274 int i = INTVAL (operands[1]);
277 else if ((unsigned int)~i < 64)
278 return \"mcomb %B1,%0\";
280 return \"movb %1,%0\";
283 (define_insn "movstrictqi"
284 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
285 (match_operand:QI 1 "general_operand" "g"))]
289 if (GET_CODE (operands[1]) == CONST_INT)
291 int i = INTVAL (operands[1]);
294 else if ((unsigned int)~i < 64)
295 return \"mcomb %B1,%0\";
297 return \"movb %1,%0\";
300 ;; This is here to accept 4 arguments and pass the first 3 along
301 ;; to the movmemhi1 pattern that really does the work.
302 (define_expand "movmemhi"
303 [(set (match_operand:BLK 0 "general_operand" "=g")
304 (match_operand:BLK 1 "general_operand" "g"))
305 (use (match_operand:HI 2 "general_operand" "g"))
306 (match_operand 3 "" "")]
309 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
313 ;; The definition of this insn does not really explain what it does,
314 ;; but it should suffice
315 ;; that anything generated as this insn will be recognized as one
316 ;; and that it won't successfully combine with anything.
317 (define_insn "movmemhi1"
318 [(set (match_operand:BLK 0 "memory_operand" "=m")
319 (match_operand:BLK 1 "memory_operand" "m"))
320 (use (match_operand:HI 2 "general_operand" "g"))
326 (clobber (reg:SI 5))]
330 ;; Extension and truncation insns.
332 (define_insn "truncsiqi2"
333 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
334 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
338 (define_insn "truncsihi2"
339 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
340 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
344 (define_insn "trunchiqi2"
345 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
346 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
350 (define_insn "extendhisi2"
351 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
352 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
356 (define_insn "extendqihi2"
357 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
358 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
362 (define_insn "extendqisi2"
363 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
364 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
368 (define_insn "extendsfdf2"
369 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
370 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
374 (define_insn "truncdfsf2"
375 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
376 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
380 (define_insn "zero_extendhisi2"
381 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
382 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
386 (define_insn "zero_extendqihi2"
387 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
388 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
392 (define_insn "zero_extendqisi2"
393 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
394 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
398 ;; Fix-to-float conversion insns.
400 (define_insn "floatsisf2"
401 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
402 (float:SF (match_operand:SI 1 "nonimmediate_operand" "g")))]
406 (define_insn "floatsidf2"
407 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
408 (float:DF (match_operand:SI 1 "nonimmediate_operand" "g")))]
412 (define_insn "floathisf2"
413 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
414 (float:SF (match_operand:HI 1 "nonimmediate_operand" "g")))]
418 (define_insn "floathidf2"
419 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
420 (float:DF (match_operand:HI 1 "nonimmediate_operand" "g")))]
424 (define_insn "floatqisf2"
425 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
426 (float:SF (match_operand:QI 1 "nonimmediate_operand" "g")))]
430 (define_insn "floatqidf2"
431 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
432 (float:DF (match_operand:QI 1 "nonimmediate_operand" "g")))]
436 ;; Float-to-fix conversion insns.
438 (define_insn "fix_truncsfqi2"
439 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
440 (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
444 (define_insn "fix_truncsfhi2"
445 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
446 (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
450 (define_insn "fix_truncsfsi2"
451 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
452 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
456 (define_insn "fix_truncdfqi2"
457 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
458 (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
462 (define_insn "fix_truncdfhi2"
463 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
464 (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
468 (define_insn "fix_truncdfsi2"
469 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
470 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
474 ;;- All kinds of add instructions.
476 (define_insn "adddf3"
477 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g,g")
478 (plus:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
479 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
486 (define_insn "addsf3"
487 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g,g")
488 (plus:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
489 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
496 /* The space-time-opcode tradeoffs for addition vary by model of VAX.
498 On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
499 but it not faster on other models.
501 "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
502 faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if
503 a register is used in an address too soon after it is set.
504 Compromise by using movab only when it is shorter than the add
505 or the base register in the address is one of sp, ap, and fp,
506 which are not modified very often. */
509 (define_insn "addsi3"
510 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
511 (plus:SI (match_operand:SI 1 "general_operand" "g")
512 (match_operand:SI 2 "general_operand" "g")))]
516 if (rtx_equal_p (operands[0], operands[1]))
518 if (operands[2] == const1_rtx)
520 if (operands[2] == constm1_rtx)
522 if (GET_CODE (operands[2]) == CONST_INT
523 && (unsigned) (- INTVAL (operands[2])) < 64)
524 return \"subl2 $%n2,%0\";
525 if (GET_CODE (operands[2]) == CONST_INT
526 && (unsigned) INTVAL (operands[2]) >= 64
527 && GET_CODE (operands[1]) == REG
528 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
529 || REGNO (operands[1]) > 11))
530 return \"movab %c2(%1),%0\";
531 return \"addl2 %2,%0\";
533 if (rtx_equal_p (operands[0], operands[2]))
534 return \"addl2 %1,%0\";
536 if (GET_CODE (operands[2]) == CONST_INT
537 && INTVAL (operands[2]) < 32767
538 && INTVAL (operands[2]) > -32768
539 && GET_CODE (operands[1]) == REG
540 && push_operand (operands[0], SImode))
541 return \"pushab %c2(%1)\";
543 if (GET_CODE (operands[2]) == CONST_INT
544 && (unsigned) (- INTVAL (operands[2])) < 64)
545 return \"subl3 $%n2,%1,%0\";
547 if (GET_CODE (operands[2]) == CONST_INT
548 && (unsigned) INTVAL (operands[2]) >= 64
549 && GET_CODE (operands[1]) == REG
550 && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
551 || REGNO (operands[1]) > 11))
552 return \"movab %c2(%1),%0\";
554 /* Add this if using gcc on a VAX 3xxx:
555 if (REG_P (operands[1]) && REG_P (operands[2]))
556 return \"movab (%1)[%2],%0\";
558 return \"addl3 %1,%2,%0\";
561 (define_insn "addhi3"
562 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
563 (plus:HI (match_operand:HI 1 "general_operand" "g")
564 (match_operand:HI 2 "general_operand" "g")))]
568 if (rtx_equal_p (operands[0], operands[1]))
570 if (operands[2] == const1_rtx)
572 if (operands[2] == constm1_rtx)
574 if (GET_CODE (operands[2]) == CONST_INT
575 && (unsigned) (- INTVAL (operands[2])) < 64)
576 return \"subw2 $%n2,%0\";
577 return \"addw2 %2,%0\";
579 if (rtx_equal_p (operands[0], operands[2]))
580 return \"addw2 %1,%0\";
581 if (GET_CODE (operands[2]) == CONST_INT
582 && (unsigned) (- INTVAL (operands[2])) < 64)
583 return \"subw3 $%n2,%1,%0\";
584 return \"addw3 %1,%2,%0\";
587 (define_insn "addqi3"
588 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
589 (plus:QI (match_operand:QI 1 "general_operand" "g")
590 (match_operand:QI 2 "general_operand" "g")))]
594 if (rtx_equal_p (operands[0], operands[1]))
596 if (operands[2] == const1_rtx)
598 if (operands[2] == constm1_rtx)
600 if (GET_CODE (operands[2]) == CONST_INT
601 && (unsigned) (- INTVAL (operands[2])) < 64)
602 return \"subb2 $%n2,%0\";
603 return \"addb2 %2,%0\";
605 if (rtx_equal_p (operands[0], operands[2]))
606 return \"addb2 %1,%0\";
607 if (GET_CODE (operands[2]) == CONST_INT
608 && (unsigned) (- INTVAL (operands[2])) < 64)
609 return \"subb3 $%n2,%1,%0\";
610 return \"addb3 %1,%2,%0\";
613 ;; The add-with-carry (adwc) instruction only accepts two operands.
614 (define_insn "adddi3"
615 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
616 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
617 (match_operand:DI 2 "general_operand" "Fro,F")))]
625 split_quadword_operands (operands, low, 3);
627 if (rtx_equal_p (operands[0], operands[1]))
629 if (low[2] == const0_rtx)
630 /* Should examine operand, punt if not POST_INC. */
631 pattern = \"tstl %0\", carry = 0;
632 else if (low[2] == const1_rtx)
633 pattern = \"incl %0\";
635 pattern = \"addl2 %2,%0\";
639 if (low[2] == const0_rtx)
640 pattern = \"movl %1,%0\", carry = 0;
642 pattern = \"addl3 %2,%1,%0\";
645 output_asm_insn (pattern, low);
647 /* If CARRY is 0, we don't have any carry value to worry about. */
648 return get_insn_template (CODE_FOR_addsi3, insn);
649 /* %0 = C + %1 + %2 */
650 if (!rtx_equal_p (operands[0], operands[1]))
651 output_asm_insn ((operands[1] == const0_rtx
653 : \"movl %1,%0\"), operands);
654 return \"adwc %2,%0\";
657 ;;- All kinds of subtract instructions.
659 (define_insn "subdf3"
660 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
661 (minus:DF (match_operand:DF 1 "general_operand" "0,gF")
662 (match_operand:DF 2 "general_operand" "gF,gF")))]
668 (define_insn "subsf3"
669 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
670 (minus:SF (match_operand:SF 1 "general_operand" "0,gF")
671 (match_operand:SF 2 "general_operand" "gF,gF")))]
677 (define_insn "subsi3"
678 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
679 (minus:SI (match_operand:SI 1 "general_operand" "0,g")
680 (match_operand:SI 2 "general_operand" "g,g")))]
686 (define_insn "subhi3"
687 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
688 (minus:HI (match_operand:HI 1 "general_operand" "0,g")
689 (match_operand:HI 2 "general_operand" "g,g")))]
695 (define_insn "subqi3"
696 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
697 (minus:QI (match_operand:QI 1 "general_operand" "0,g")
698 (match_operand:QI 2 "general_operand" "g,g")))]
704 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
705 (define_insn "subdi3"
706 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
707 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
708 (match_operand:DI 2 "general_operand" "For,F")))]
716 split_quadword_operands (operands, low, 3);
717 /* Subtract low parts. */
718 if (rtx_equal_p (operands[0], operands[1]))
720 if (low[2] == const0_rtx)
721 pattern = 0, carry = 0;
722 else if (low[2] == constm1_rtx)
723 pattern = \"decl %0\";
725 pattern = \"subl2 %2,%0\";
729 if (low[2] == constm1_rtx)
730 pattern = \"decl %0\";
731 else if (low[2] == const0_rtx)
732 pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0;
734 pattern = \"subl3 %2,%1,%0\";
737 output_asm_insn (pattern, low);
740 if (!rtx_equal_p (operands[0], operands[1]))
741 return \"movl %1,%0\;sbwc %2,%0\";
742 return \"sbwc %2,%0\";
743 /* %0 = %2 - %1 - C */
745 return get_insn_template (CODE_FOR_subsi3, insn);
748 ;;- Multiply instructions.
750 (define_insn "muldf3"
751 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g,g")
752 (mult:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
753 (match_operand:DF 2 "general_operand" "gF,0,gF")))]
760 (define_insn "mulsf3"
761 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g,g")
762 (mult:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
763 (match_operand:SF 2 "general_operand" "gF,0,gF")))]
770 (define_insn "mulsi3"
771 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
772 (mult:SI (match_operand:SI 1 "general_operand" "0,g,g")
773 (match_operand:SI 2 "general_operand" "g,0,g")))]
780 (define_insn "mulhi3"
781 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,")
782 (mult:HI (match_operand:HI 1 "general_operand" "0,g,g")
783 (match_operand:HI 2 "general_operand" "g,0,g")))]
790 (define_insn "mulqi3"
791 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
792 (mult:QI (match_operand:QI 1 "general_operand" "0,g,g")
793 (match_operand:QI 2 "general_operand" "g,0,g")))]
800 (define_insn "mulsidi3"
801 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
802 (mult:DI (sign_extend:DI
803 (match_operand:SI 1 "nonimmediate_operand" "g"))
805 (match_operand:SI 2 "nonimmediate_operand" "g"))))]
810 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
812 (mult:DI (sign_extend:DI
813 (match_operand:SI 1 "nonimmediate_operand" "g"))
815 (match_operand:SI 2 "nonimmediate_operand" "g")))
816 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
820 ;; 'F' constraint means type CONST_DOUBLE
822 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
824 (mult:DI (sign_extend:DI
825 (match_operand:SI 1 "nonimmediate_operand" "g"))
827 (match_operand:SI 2 "nonimmediate_operand" "g")))
828 (match_operand:DI 3 "immediate_operand" "F")))]
829 "GET_CODE (operands[3]) == CONST_DOUBLE
830 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
833 if (CONST_DOUBLE_HIGH (operands[3]))
834 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
835 return \"emul %1,%2,%3,%0\";
838 ;;- Divide instructions.
840 (define_insn "divdf3"
841 [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
842 (div:DF (match_operand:DF 1 "general_operand" "0,gF")
843 (match_operand:DF 2 "general_operand" "gF,gF")))]
849 (define_insn "divsf3"
850 [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
851 (div:SF (match_operand:SF 1 "general_operand" "0,gF")
852 (match_operand:SF 2 "general_operand" "gF,gF")))]
858 (define_insn "divsi3"
859 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
860 (div:SI (match_operand:SI 1 "general_operand" "0,g")
861 (match_operand:SI 2 "general_operand" "g,g")))]
867 (define_insn "divhi3"
868 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
869 (div:HI (match_operand:HI 1 "general_operand" "0,g")
870 (match_operand:HI 2 "general_operand" "g,g")))]
876 (define_insn "divqi3"
877 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
878 (div:QI (match_operand:QI 1 "general_operand" "0,g")
879 (match_operand:QI 2 "general_operand" "g,g")))]
885 ;This is left out because it is very slow;
886 ;we are better off programming around the "lack" of this insn.
887 ;(define_insn "divmoddisi4"
888 ; [(set (match_operand:SI 0 "general_operand" "=g")
889 ; (div:SI (match_operand:DI 1 "general_operand" "g")
890 ; (match_operand:SI 2 "general_operand" "g")))
891 ; (set (match_operand:SI 3 "general_operand" "=g")
892 ; (mod:SI (match_operand:DI 1 "general_operand" "g")
893 ; (match_operand:SI 2 "general_operand" "g")))]
895 ; "ediv %2,%1,%0,%3")
897 ;; Bit-and on the VAX is done with a clear-bits insn.
898 (define_expand "andsi3"
899 [(set (match_operand:SI 0 "nonimmediate_operand" "")
900 (and:SI (not:SI (match_operand:SI 1 "general_operand" ""))
901 (match_operand:SI 2 "general_operand" "")))]
905 rtx op1 = operands[1];
907 /* If there is a constant argument, complement that one. */
908 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
910 operands[1] = operands[2];
915 if (GET_CODE (op1) == CONST_INT)
916 operands[1] = GEN_INT (~INTVAL (op1));
918 operands[1] = expand_unop (SImode, one_cmpl_optab, op1, 0, 1);
921 (define_expand "andhi3"
922 [(set (match_operand:HI 0 "nonimmediate_operand" "")
923 (and:HI (not:HI (match_operand:HI 1 "general_operand" ""))
924 (match_operand:HI 2 "general_operand" "")))]
928 rtx op1 = operands[1];
930 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
932 operands[1] = operands[2];
937 if (GET_CODE (op1) == CONST_INT)
938 operands[1] = GEN_INT (~INTVAL (op1));
940 operands[1] = expand_unop (HImode, one_cmpl_optab, op1, 0, 1);
943 (define_expand "andqi3"
944 [(set (match_operand:QI 0 "nonimmediate_operand" "")
945 (and:QI (not:QI (match_operand:QI 1 "general_operand" ""))
946 (match_operand:QI 2 "general_operand" "")))]
950 rtx op1 = operands[1];
952 if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
954 operands[1] = operands[2];
959 if (GET_CODE (op1) == CONST_INT)
960 operands[1] = GEN_INT (~INTVAL (op1));
962 operands[1] = expand_unop (QImode, one_cmpl_optab, op1, 0, 1);
966 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
967 (and:SI (not:SI (match_operand:SI 1 "general_operand" "g,g"))
968 (match_operand:SI 2 "general_operand" "0,g")))]
975 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
976 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g,g"))
977 (match_operand:HI 2 "general_operand" "0,g")))]
984 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
985 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g,g"))
986 (match_operand:QI 2 "general_operand" "0,g")))]
992 ;; The following used to be needed because constant propagation can
993 ;; create them starting from the bic insn patterns above. This is no
994 ;; longer a problem. However, having these patterns allows optimization
995 ;; opportunities in combine.c.
998 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
999 (and:SI (match_operand:SI 1 "general_operand" "0,g")
1000 (match_operand:SI 2 "const_int_operand" "n,n")))]
1007 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
1008 (and:HI (match_operand:HI 1 "general_operand" "0,g")
1009 (match_operand:HI 2 "const_int_operand" "n,n")))]
1016 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
1017 (and:QI (match_operand:QI 1 "general_operand" "0,g")
1018 (match_operand:QI 2 "const_int_operand" "n,n")))]
1024 ;;- Bit set instructions.
1026 (define_insn "iorsi3"
1027 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
1028 (ior:SI (match_operand:SI 1 "general_operand" "0,g,g")
1029 (match_operand:SI 2 "general_operand" "g,0,g")))]
1036 (define_insn "iorhi3"
1037 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,g")
1038 (ior:HI (match_operand:HI 1 "general_operand" "0,g,g")
1039 (match_operand:HI 2 "general_operand" "g,0,g")))]
1046 (define_insn "iorqi3"
1047 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
1048 (ior:QI (match_operand:QI 1 "general_operand" "0,g,g")
1049 (match_operand:QI 2 "general_operand" "g,0,g")))]
1056 ;;- xor instructions.
1058 (define_insn "xorsi3"
1059 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
1060 (xor:SI (match_operand:SI 1 "general_operand" "0,g,g")
1061 (match_operand:SI 2 "general_operand" "g,0,g")))]
1068 (define_insn "xorhi3"
1069 [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,g")
1070 (xor:HI (match_operand:HI 1 "general_operand" "0,g,g")
1071 (match_operand:HI 2 "general_operand" "g,0,g")))]
1078 (define_insn "xorqi3"
1079 [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
1080 (xor:QI (match_operand:QI 1 "general_operand" "0,g,g")
1081 (match_operand:QI 2 "general_operand" "g,0,g")))]
1088 (define_insn "negdf2"
1089 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
1090 (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1094 (define_insn "negsf2"
1095 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
1096 (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1100 (define_insn "negsi2"
1101 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1102 (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1106 (define_insn "neghi2"
1107 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1108 (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1112 (define_insn "negqi2"
1113 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
1114 (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1118 (define_insn "one_cmplsi2"
1119 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1120 (not:SI (match_operand:SI 1 "general_operand" "g")))]
1124 (define_insn "one_cmplhi2"
1125 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1126 (not:HI (match_operand:HI 1 "general_operand" "g")))]
1130 (define_insn "one_cmplqi2"
1131 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
1132 (not:QI (match_operand:QI 1 "general_operand" "g")))]
1136 ;; Arithmetic right shift on the VAX works by negating the shift count,
1137 ;; then emitting a right shift with the shift count negated. This means
1138 ;; that all actual shift counts in the RTL will be positive. This
1139 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1140 ;; which isn't valid.
1141 (define_expand "ashrsi3"
1142 [(set (match_operand:SI 0 "general_operand" "=g")
1143 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1144 (match_operand:QI 2 "general_operand" "g")))]
1148 if (GET_CODE (operands[2]) != CONST_INT)
1149 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1153 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1154 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1155 (match_operand:QI 2 "const_int_operand" "n")))]
1160 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1161 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1162 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1166 (define_insn "ashlsi3"
1167 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1168 (ashift:SI (match_operand:SI 1 "general_operand" "g")
1169 (match_operand:QI 2 "general_operand" "g")))]
1173 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1174 return \"addl2 %0,%0\";
1175 if (GET_CODE (operands[1]) == REG
1176 && GET_CODE (operands[2]) == CONST_INT)
1178 int i = INTVAL (operands[2]);
1180 return \"addl3 %1,%1,%0\";
1182 return \"moval 0[%1],%0\";
1184 return \"movad 0[%1],%0\";
1186 return \"ashl %2,%1,%0\";
1189 ;; Arithmetic right shift on the VAX works by negating the shift count.
1190 (define_expand "ashrdi3"
1191 [(set (match_operand:DI 0 "general_operand" "=g")
1192 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1193 (match_operand:QI 2 "general_operand" "g")))]
1197 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1200 (define_insn "ashldi3"
1201 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1202 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1203 (match_operand:QI 2 "general_operand" "g")))]
1208 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1209 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1210 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1214 ;; We used to have expand_shift handle logical right shifts by using extzv,
1215 ;; but this make it very difficult to do lshrdi3. Since the VAX is the
1216 ;; only machine with this kludge, it's better to just do this with a
1217 ;; define_expand and remove that case from expand_shift.
1219 (define_expand "lshrsi3"
1221 (minus:QI (const_int 32)
1223 (set (match_operand:SI 0 "general_operand" "=g")
1224 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1226 (match_operand:SI 2 "register_operand" "g")))]
1230 operands[3] = gen_reg_rtx (QImode);
1231 operands[4] = gen_lowpart (QImode, operands[2]);
1234 ;; Rotate right on the VAX works by negating the shift count.
1235 (define_expand "rotrsi3"
1236 [(set (match_operand:SI 0 "general_operand" "=g")
1237 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1238 (match_operand:QI 2 "general_operand" "g")))]
1242 if (GET_CODE (operands[2]) != CONST_INT)
1243 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1246 (define_insn "rotlsi3"
1247 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1248 (rotate:SI (match_operand:SI 1 "general_operand" "g")
1249 (match_operand:QI 2 "general_operand" "g")))]
1254 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1255 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1256 (match_operand:QI 2 "const_int_operand" "n")))]
1261 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1262 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1263 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1267 ;This insn is probably slower than a multiply and an add.
1269 ; [(set (match_operand:SI 0 "general_operand" "=g")
1270 ; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1271 ; (match_operand:SI 2 "general_operand" "g"))
1272 ; (match_operand:SI 3 "general_operand" "g")))]
1274 ; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1276 ;; Special cases of bit-field insns which we should
1277 ;; recognize in preference to the general case.
1278 ;; These handle aligned 8-bit and 16-bit fields,
1279 ;; which can usually be done with move instructions.
1282 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
1283 (match_operand:QI 1 "const_int_operand" "n")
1284 (match_operand:SI 2 "const_int_operand" "n"))
1285 (match_operand:SI 3 "general_operand" "g"))]
1286 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1287 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1288 && (GET_CODE (operands[0]) == REG
1289 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1292 if (REG_P (operands[0]))
1294 if (INTVAL (operands[2]) != 0)
1295 return \"insv %3,%2,%1,%0\";
1299 = adjust_address (operands[0],
1300 INTVAL (operands[1]) == 8 ? QImode : HImode,
1301 INTVAL (operands[2]) / 8);
1304 if (INTVAL (operands[1]) == 8)
1305 return \"movb %3,%0\";
1306 return \"movw %3,%0\";
1310 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
1311 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1312 (match_operand:QI 2 "const_int_operand" "n")
1313 (match_operand:SI 3 "const_int_operand" "n")))]
1314 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1315 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1316 && (GET_CODE (operands[1]) == REG
1317 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1320 if (REG_P (operands[1]))
1322 if (INTVAL (operands[3]) != 0)
1323 return \"extzv %3,%2,%1,%0\";
1327 = adjust_address (operands[1],
1328 INTVAL (operands[2]) == 8 ? QImode : HImode,
1329 INTVAL (operands[3]) / 8);
1331 if (INTVAL (operands[2]) == 8)
1332 return \"movzbl %1,%0\";
1333 return \"movzwl %1,%0\";
1337 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1338 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1339 (match_operand:QI 2 "const_int_operand" "n")
1340 (match_operand:SI 3 "const_int_operand" "n")))]
1341 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1342 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1343 && (GET_CODE (operands[1]) == REG
1344 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1347 if (REG_P (operands[1]))
1349 if (INTVAL (operands[3]) != 0)
1350 return \"extv %3,%2,%1,%0\";
1354 = adjust_address (operands[1],
1355 INTVAL (operands[2]) == 8 ? QImode : HImode,
1356 INTVAL (operands[3]) / 8);
1358 if (INTVAL (operands[2]) == 8)
1359 return \"cvtbl %1,%0\";
1360 return \"cvtwl %1,%0\";
1363 ;; Register-only SImode cases of bit-field insns.
1368 (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1369 (match_operand:QI 1 "general_operand" "g")
1370 (match_operand:SI 2 "general_operand" "g"))
1371 (match_operand:SI 3 "general_operand" "g")))]
1378 (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1379 (match_operand:QI 1 "general_operand" "g")
1380 (match_operand:SI 2 "general_operand" "g"))
1381 (match_operand:SI 3 "general_operand" "g")))]
1383 "cmpzv %2,%1,%0,%3")
1385 ;; When the field position and size are constant and the destination
1386 ;; is a register, extv and extzv are much slower than a rotate followed
1387 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v
1388 ;; anyway, we can't allow immediate values for the primary source operand.
1391 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1392 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1393 (match_operand:QI 2 "general_operand" "g")
1394 (match_operand:SI 3 "general_operand" "g")))]
1398 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1399 || GET_CODE (operands[0]) != REG
1400 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
1401 return \"extv %3,%2,%1,%0\";
1402 if (INTVAL (operands[2]) == 8)
1403 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1404 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1408 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1409 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1410 (match_operand:QI 2 "general_operand" "g")
1411 (match_operand:SI 3 "general_operand" "g")))]
1415 if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1416 || GET_CODE (operands[0]) != REG)
1417 return \"extzv %3,%2,%1,%0\";
1418 if (INTVAL (operands[2]) == 8)
1419 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1420 if (INTVAL (operands[2]) == 16)
1421 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1422 if (INTVAL (operands[3]) & 31)
1423 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1424 if (rtx_equal_p (operands[0], operands[1]))
1425 return \"bicl2 %M2,%0\";
1426 return \"bicl3 %M2,%1,%0\";
1429 ;; Non-register cases.
1430 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1431 ;; don't match these (and therefore match the cases above instead).
1436 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
1437 (match_operand:QI 1 "general_operand" "g")
1438 (match_operand:SI 2 "general_operand" "g"))
1439 (match_operand:SI 3 "general_operand" "g")))]
1446 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1447 (match_operand:QI 1 "general_operand" "g")
1448 (match_operand:SI 2 "general_operand" "g"))
1449 (match_operand:SI 3 "general_operand" "g")))]
1451 "cmpzv %2,%1,%0,%3")
1454 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1455 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
1456 (match_operand:QI 2 "general_operand" "g")
1457 (match_operand:SI 3 "general_operand" "g")))]
1461 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1462 || GET_CODE (operands[3]) != CONST_INT
1463 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
1464 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1465 || side_effects_p (operands[1])
1466 || (GET_CODE (operands[1]) == MEM
1467 && mode_dependent_address_p (XEXP (operands[1], 0))))
1468 return \"extv %3,%2,%1,%0\";
1469 if (INTVAL (operands[2]) == 8)
1470 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1471 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1474 (define_expand "extzv"
1475 [(set (match_operand:SI 0 "general_operand" "")
1476 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
1477 (match_operand:QI 2 "general_operand" "")
1478 (match_operand:SI 3 "general_operand" "")))]
1483 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1484 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
1485 (match_operand:QI 2 "general_operand" "g")
1486 (match_operand:SI 3 "general_operand" "g")))]
1490 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1491 || GET_CODE (operands[3]) != CONST_INT
1492 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1493 || side_effects_p (operands[1])
1494 || (GET_CODE (operands[1]) == MEM
1495 && mode_dependent_address_p (XEXP (operands[1], 0))))
1496 return \"extzv %3,%2,%1,%0\";
1497 if (INTVAL (operands[2]) == 8)
1498 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1499 if (INTVAL (operands[2]) == 16)
1500 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1501 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1504 (define_expand "insv"
1505 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
1506 (match_operand:QI 1 "general_operand" "")
1507 (match_operand:SI 2 "general_operand" ""))
1508 (match_operand:SI 3 "general_operand" ""))]
1513 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
1514 (match_operand:QI 1 "general_operand" "g")
1515 (match_operand:SI 2 "general_operand" "g"))
1516 (match_operand:SI 3 "general_operand" "g"))]
1521 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1522 (match_operand:QI 1 "general_operand" "g")
1523 (match_operand:SI 2 "general_operand" "g"))
1524 (match_operand:SI 3 "general_operand" "g"))]
1530 (label_ref (match_operand 0 "" "")))]
1536 (if_then_else (eq (cc0)
1538 (label_ref (match_operand 0 "" ""))
1545 (if_then_else (ne (cc0)
1547 (label_ref (match_operand 0 "" ""))
1554 (if_then_else (gt (cc0)
1556 (label_ref (match_operand 0 "" ""))
1563 (if_then_else (gtu (cc0)
1565 (label_ref (match_operand 0 "" ""))
1572 (if_then_else (lt (cc0)
1574 (label_ref (match_operand 0 "" ""))
1581 (if_then_else (ltu (cc0)
1583 (label_ref (match_operand 0 "" ""))
1590 (if_then_else (ge (cc0)
1592 (label_ref (match_operand 0 "" ""))
1599 (if_then_else (geu (cc0)
1601 (label_ref (match_operand 0 "" ""))
1608 (if_then_else (le (cc0)
1610 (label_ref (match_operand 0 "" ""))
1617 (if_then_else (leu (cc0)
1619 (label_ref (match_operand 0 "" ""))
1624 ;; Recognize reversed jumps.
1627 (if_then_else (match_operator 0 "comparison_operator"
1631 (label_ref (match_operand 1 "" ""))))]
1633 "j%C0 %l1") ; %C0 negates condition
1635 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
1636 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
1637 ;; memory, we use QImode in the insn. So we can't use those instructions
1638 ;; for mode-dependent addresses.
1643 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1645 (match_operand:SI 1 "general_operand" "I,g"))
1647 (label_ref (match_operand 2 "" ""))
1657 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1659 (match_operand:SI 1 "general_operand" "I,g"))
1661 (label_ref (match_operand 2 "" ""))
1671 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1673 (match_operand:SI 1 "general_operand" "I,g"))
1675 (label_ref (match_operand 2 "" ""))
1685 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1687 (match_operand:SI 1 "general_operand" "I,g"))
1689 (label_ref (match_operand 2 "" ""))
1696 ;; Subtract-and-jump and Add-and-jump insns.
1697 ;; These are not used when output is for the Unix assembler
1698 ;; because it does not know how to modify them to reach far.
1700 ;; Normal sob insns.
1705 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1708 (label_ref (match_operand 1 "" ""))
1711 (plus:SI (match_dup 0)
1719 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1722 (label_ref (match_operand 1 "" ""))
1725 (plus:SI (match_dup 0)
1730 ;; Normal aob insns. Define a version for when operands[1] is a constant.
1734 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1736 (match_operand:SI 1 "general_operand" "g"))
1737 (label_ref (match_operand 2 "" ""))
1740 (plus:SI (match_dup 0)
1743 "jaoblss %1,%0,%l2")
1748 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1749 (match_operand:SI 1 "general_operand" "g"))
1750 (label_ref (match_operand 2 "" ""))
1753 (plus:SI (match_dup 0)
1755 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1756 "jaoblss %P1,%0,%l2")
1761 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1763 (match_operand:SI 1 "general_operand" "g"))
1764 (label_ref (match_operand 2 "" ""))
1767 (plus:SI (match_dup 0)
1770 "jaobleq %1,%0,%l2")
1775 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1776 (match_operand:SI 1 "general_operand" "g"))
1777 (label_ref (match_operand 2 "" ""))
1780 (plus:SI (match_dup 0)
1782 "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1783 "jaobleq %P1,%0,%l2")
1785 ;; Something like a sob insn, but compares against -1.
1786 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1791 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1793 (label_ref (match_operand 1 "" ""))
1796 (plus:SI (match_dup 0)
1799 "decl %0\;jgequ %l1")
1801 (define_expand "call_pop"
1802 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1803 (match_operand:SI 1 "const_int_operand" ""))
1805 (plus:SI (reg:SI 14)
1806 (match_operand:SI 3 "immediate_operand" "")))])]
1809 if (INTVAL (operands[3]) > 255 * 4 || INTVAL (operands[3]) % 4)
1812 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1813 during EH unwinding. We must include the argument count pushed by
1814 the calls instruction. */
1815 operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
1818 (define_insn "*call_pop"
1819 [(call (match_operand:QI 0 "memory_operand" "m")
1820 (match_operand:SI 1 "const_int_operand" "n"))
1821 (set (reg:SI 14) (plus:SI (reg:SI 14)
1822 (match_operand:SI 2 "immediate_operand" "i")))]
1825 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
1826 return "calls %1,%0";
1829 (define_expand "call_value_pop"
1830 [(parallel [(set (match_operand 0 "" "")
1831 (call (match_operand:QI 1 "memory_operand" "")
1832 (match_operand:SI 2 "const_int_operand" "")))
1834 (plus:SI (reg:SI 14)
1835 (match_operand:SI 4 "immediate_operand" "")))])]
1838 if (INTVAL (operands[4]) > 255 * 4 || INTVAL (operands[4]) % 4)
1841 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1842 during EH unwinding. We must include the argument count pushed by
1843 the calls instruction. */
1844 operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
1847 (define_insn "*call_value_pop"
1848 [(set (match_operand 0 "" "")
1849 (call (match_operand:QI 1 "memory_operand" "m")
1850 (match_operand:SI 2 "const_int_operand" "n")))
1851 (set (reg:SI 14) (plus:SI (reg:SI 14)
1852 (match_operand:SI 3 "immediate_operand" "i")))]
1856 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
1857 return \"calls %2,%1\";
1860 (define_expand "call"
1861 [(call (match_operand:QI 0 "memory_operand" "")
1862 (match_operand:SI 1 "const_int_operand" ""))]
1866 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1867 during EH unwinding. We must include the argument count pushed by
1868 the calls instruction. */
1869 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
1872 (define_insn "*call"
1873 [(call (match_operand:QI 0 "memory_operand" "m")
1874 (match_operand:SI 1 "const_int_operand" ""))]
1878 (define_expand "call_value"
1879 [(set (match_operand 0 "" "")
1880 (call (match_operand:QI 1 "memory_operand" "")
1881 (match_operand:SI 2 "const_int_operand" "")))]
1885 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1886 during EH unwinding. We must include the argument count pushed by
1887 the calls instruction. */
1888 operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
1891 (define_insn "*call_value"
1892 [(set (match_operand 0 "" "")
1893 (call (match_operand:QI 1 "memory_operand" "m")
1894 (match_operand:SI 2 "const_int_operand" "")))]
1898 ;; Call subroutine returning any type.
1900 (define_expand "untyped_call"
1901 [(parallel [(call (match_operand 0 "" "")
1903 (match_operand 1 "" "")
1904 (match_operand 2 "" "")])]
1910 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1912 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1914 rtx set = XVECEXP (operands[2], 0, i);
1915 emit_move_insn (SET_DEST (set), SET_SRC (set));
1918 /* The optimizer does not know that the call sets the function value
1919 registers we stored in the result block. We avoid problems by
1920 claiming that all hard registers are used and clobbered at this
1922 emit_insn (gen_blockage ());
1927 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1928 ;; all of memory. This blocks insns from being moved across this point.
1930 (define_insn "blockage"
1931 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
1935 (define_insn "return"
1940 (define_expand "epilogue"
1945 emit_jump_insn (gen_return ());
1954 ;; This had a wider constraint once, and it had trouble.
1955 ;; If you are tempted to try `g', please don't--it's not worth
1956 ;; the risk we will reopen the same bug.
1957 (define_insn "indirect_jump"
1958 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1962 ;; This is here to accept 5 arguments (as passed by expand_end_case)
1963 ;; and pass the first 4 along to the casesi1 pattern that really does
1964 ;; the actual casesi work. We emit a jump here to the default label
1965 ;; _before_ the casesi so that we can be sure that the casesi never
1967 ;; This is suboptimal perhaps, but so is much of the rest of this
1968 ;; machine description. For what it's worth, HPPA uses the same trick.
1970 ;; operand 0 is index
1971 ;; operand 1 is the minimum bound (a const_int)
1972 ;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
1973 ;; operand 3 is CODE_LABEL for the table;
1974 ;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
1977 ;; i = index - minimum_bound
1978 ;; if (i > (maximum_bound - minimum_bound + 1) goto default;
1979 ;; casesi (i, 0, table);
1981 (define_expand "casesi"
1982 [(match_operand:SI 0 "general_operand" "")
1983 (match_operand:SI 1 "general_operand" "")
1984 (match_operand:SI 2 "general_operand" "")
1985 (match_operand 3 "" "")
1986 (match_operand 4 "" "")]
1989 /* i = index - minimum_bound;
1990 But only if the lower bound is not already zero. */
1991 if (operands[1] != const0_rtx)
1993 rtx index = gen_reg_rtx (SImode);
1994 emit_insn (gen_addsi3 (index,
1996 GEN_INT (-INTVAL (operands[1]))));
1997 operands[0] = index;
2000 /* if (i > (maximum_bound - minimum_bound + 1) goto default; */
2001 emit_insn (gen_cmpsi (operands[0], operands[2]));
2002 emit_jump_insn (gen_bgtu (operands[4]));
2004 /* casesi (i, 0, table); */
2005 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
2009 ;; This insn is a bit of a lier. It actually falls through if no case
2010 ;; matches. But, we prevent that from ever happening by emitting a jump
2011 ;; before this, see the define_expand above.
2012 (define_insn "casesi1"
2013 [(match_operand:SI 1 "const_int_operand" "n")
2015 (plus:SI (sign_extend:SI
2016 (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "g")
2019 (label_ref:SI (match_operand 2 "" ""))))]
2023 ;;- load or push effective address
2024 ;; These come after the move and add/sub patterns
2025 ;; because we don't want pushl $1 turned into pushad 1.
2026 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
2028 ;; It does not work to use constraints to distinguish pushes from moves,
2029 ;; because < matches any autodecrement, not just a push.
2032 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2033 (match_operand:QI 1 "address_operand" "p"))]
2037 if (push_operand (operands[0], SImode))
2038 return \"pushab %a1\";
2040 return \"movab %a1,%0\";
2044 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2045 (match_operand:HI 1 "address_operand" "p"))]
2049 if (push_operand (operands[0], SImode))
2050 return \"pushaw %a1\";
2052 return \"movaw %a1,%0\";
2056 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2057 (match_operand:SI 1 "address_operand" "p"))]
2061 if (push_operand (operands[0], SImode))
2062 return \"pushal %a1\";
2064 return \"moval %a1,%0\";
2068 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2069 (match_operand:DI 1 "address_operand" "p"))]
2073 if (push_operand (operands[0], SImode))
2074 return \"pushaq %a1\";
2076 return \"movaq %a1,%0\";
2080 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2081 (match_operand:SF 1 "address_operand" "p"))]
2085 if (push_operand (operands[0], SImode))
2086 return \"pushaf %a1\";
2088 return \"movaf %a1,%0\";
2092 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2093 (match_operand:DF 1 "address_operand" "p"))]
2097 if (push_operand (operands[0], SImode))
2098 return \"pushad %a1\";
2100 return \"movad %a1,%0\";
2103 ;; These used to be peepholes, but it is more straightforward to do them
2104 ;; as single insns. However, we must force the output to be a register
2105 ;; if it is not an offsettable address so that we know that we can assign
2108 ;; If we had a good way of evaluating the relative costs, these could be
2109 ;; machine-independent.
2111 ;; Optimize extzv ...,z; andl2 ...,z
2112 ;; or ashl ...,z; andl2 ...,z
2113 ;; with other operands constant. This is what the combiner converts the
2114 ;; above sequences to before attempting to recognize the new insn.
2117 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2118 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
2119 (match_operand:QI 2 "const_int_operand" "n"))
2120 (match_operand:SI 3 "const_int_operand" "n")))]
2121 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
2124 unsigned long mask1 = INTVAL (operands[3]);
2125 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
2127 if ((mask1 & mask2) != mask1)
2128 operands[3] = GEN_INT (mask1 & mask2);
2130 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
2133 ;; left-shift and mask
2134 ;; The only case where `ashl' is better is if the mask only turns off
2135 ;; bits that the ashl would anyways, in which case it should have been
2139 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2140 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
2141 (match_operand:QI 2 "const_int_operand" "n"))
2142 (match_operand:SI 3 "const_int_operand" "n")))]
2147 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
2148 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
2151 ;; Instruction sequence to sync the VAX instruction stream.
2152 (define_insn "sync_istream"
2153 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
2155 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")