gcc/config/vax/vax.md

   1 ;; Machine description for GNU compiler, VAX Version
   2 ;; Copyright (C) 1987, 1988, 1991, 1994, 1995, 1996, 1998, 1999, 2000, 2001,
   3 ;; 2002 Free Software Foundation, Inc.
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify
   8 ;; it under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 2, or (at your option)
  10 ;; any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful,
  13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ;; GNU General Public License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to
  19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
  20 ;; Boston, MA 02111-1307, USA.
  21
  22
  23 ;;- Instruction patterns.  When multiple patterns apply,
  24 ;;- the first one in the file is chosen.
  25 ;;-
  26 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
  27 ;;-
  28 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
  29 ;;- updates for most instructions.
  30
  31 ;; UNSPEC_VOLATILE usage:
  32
  33 (define_constants
  34   [(VUNSPEC_BLOCKAGE 0)     ; `blockage' insn to prevent scheduling across an
  35                             ;   insn in the code.
  36    (VUNSPEC_SYNC_ISTREAM 1) ; sequence of insns to sync the I-stream
  37   ]
  38 )
  39
  40 ;; We don't want to allow a constant operand for test insns because
  41 ;; (set (cc0) (const_int foo)) has no mode information.  Such insns will
  42 ;; be folded while optimizing anyway.
  43
  44 (define_insn "tstsi"
  45   [(set (cc0)
  46         (match_operand:SI 0 "nonimmediate_operand" "g"))]
  47   ""
  48   "tstl %0")
  49
  50 (define_insn "tsthi"
  51   [(set (cc0)
  52         (match_operand:HI 0 "nonimmediate_operand" "g"))]
  53   ""
  54   "tstw %0")
  55
  56 (define_insn "tstqi"
  57   [(set (cc0)
  58         (match_operand:QI 0 "nonimmediate_operand" "g"))]
  59   ""
  60   "tstb %0")
  61
  62 (define_insn "tstdf"
  63   [(set (cc0)
  64         (match_operand:DF 0 "general_operand" "gF"))]
  65   ""
  66   "tst%# %0")
  67
  68 (define_insn "tstsf"
  69   [(set (cc0)
  70         (match_operand:SF 0 "general_operand" "gF"))]
  71   ""
  72   "tstf %0")
  73
  74 (define_insn "cmpsi"
  75   [(set (cc0)
  76         (compare (match_operand:SI 0 "nonimmediate_operand" "g")
  77                  (match_operand:SI 1 "general_operand" "g")))]
  78   ""
  79   "cmpl %0,%1")
  80
  81 (define_insn "cmphi"
  82   [(set (cc0)
  83         (compare (match_operand:HI 0 "nonimmediate_operand" "g")
  84                  (match_operand:HI 1 "general_operand" "g")))]
  85   ""
  86   "cmpw %0,%1")
  87
  88 (define_insn "cmpqi"
  89   [(set (cc0)
  90         (compare (match_operand:QI 0 "nonimmediate_operand" "g")
  91                  (match_operand:QI 1 "general_operand" "g")))]
  92   ""
  93   "cmpb %0,%1")
  94
  95 (define_insn "cmpdf"
  96   [(set (cc0)
  97         (compare (match_operand:DF 0 "general_operand" "gF,gF")
  98                  (match_operand:DF 1 "general_operand" "G,gF")))]
  99   ""
 100   "@
 101    tst%# %0
 102    cmp%# %0,%1")
 103
 104 (define_insn "cmpsf"
 105   [(set (cc0)
 106         (compare (match_operand:SF 0 "general_operand" "gF,gF")
 107                  (match_operand:SF 1 "general_operand" "G,gF")))]
 108   ""
 109   "@
 110    tstf %0
 111    cmpf %0,%1")
 112
 113 (define_insn ""
 114   [(set (cc0)
 115         (and:SI (match_operand:SI 0 "general_operand" "g")
 116                 (match_operand:SI 1 "general_operand" "g")))]
 117   ""
 118   "bitl %0,%1")
 119
 120 (define_insn ""
 121   [(set (cc0)
 122         (and:HI (match_operand:HI 0 "general_operand" "g")
 123                 (match_operand:HI 1 "general_operand" "g")))]
 124   ""
 125   "bitw %0,%1")
 126
 127 (define_insn ""
 128   [(set (cc0)
 129         (and:QI (match_operand:QI 0 "general_operand" "g")
 130                 (match_operand:QI 1 "general_operand" "g")))]
 131   ""
 132   "bitb %0,%1")
 133
 134 ;; The VAX has no sCOND insns.  It does have add/subtract with carry
 135 ;; which could be used to implement the sltu and sgeu patterns.  However,
 136 ;; to do this properly requires a complete rewrite of the compare insns
 137 ;; to keep them together with the sltu/sgeu insns until after the
 138 ;; reload pass is complete.  The previous implementation didn't do this
 139 ;; and has been deleted.
 140
 141 \f
 142 (define_insn "movdf"
 143   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
 144         (match_operand:DF 1 "general_operand" "G,gF"))]
 145   ""
 146   "@
 147    clr%# %0
 148    mov%# %1,%0")
 149
 150 (define_insn "movsf"
 151   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
 152         (match_operand:SF 1 "general_operand" "G,gF"))]
 153   ""
 154   "@
 155    clrf %0
 156    movf %1,%0")
 157
 158 ;; Some VAXen don't support this instruction.
 159 ;;(define_insn "movti"
 160 ;;  [(set (match_operand:TI 0 "general_operand" "=g")
 161 ;;      (match_operand:TI 1 "general_operand" "g"))]
 162 ;;  ""
 163 ;;  "movh %1,%0")
 164
 165 (define_insn "movdi"
 166   [(set (match_operand:DI 0 "nonimmediate_operand" "=g,g")
 167         (match_operand:DI 1 "general_operand" "I,g"))]
 168   ""
 169   "@
 170    clrq %0
 171    movq %D1,%0")
 172
 173 ;; The VAX move instructions have space-time tradeoffs.  On a MicroVAX
 174 ;; register-register mov instructions take 3 bytes and 2 CPU cycles.  clrl
 175 ;; takes 2 bytes and 3 cycles.  mov from constant to register takes 2 cycles
 176 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
 177 ;; constant.  movz, mneg, and mcom are as fast as mov, so movzwl is faster
 178 ;; than movl for positive constants that fit in 16 bits but not 6 bits.  cvt
 179 ;; instructions take 4 cycles.  inc takes 3 cycles.  The machine description
 180 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
 181 ;; instead of movl).
 182
 183 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
 184 ;; but on a VAX 9000 most move and add instructions with one constant
 185 ;; operand take 1 cycle).
 186
 187 ;;  Loads of constants between 64 and 128 used to be done with
 188 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
 189
 190 (define_insn "movsi"
 191   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 192         (match_operand:SI 1 "general_operand" "g"))]
 193   ""
 194   "*
 195 {
 196   if (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
 197     {
 198       if (push_operand (operands[0], SImode))
 199         return \"pushab %a1\";
 200       return \"movab %a1,%0\";
 201     }
 202   if (operands[1] == const0_rtx)
 203     return \"clrl %0\";
 204   if (GET_CODE (operands[1]) == CONST_INT
 205       && (unsigned) INTVAL (operands[1]) >= 64)
 206     {
 207       int i = INTVAL (operands[1]);
 208       if ((unsigned)(~i) < 64)
 209         return \"mcoml %N1,%0\";
 210       if ((unsigned)i < 0x100)
 211         return \"movzbl %1,%0\";
 212       if (i >= -0x80 && i < 0)
 213         return \"cvtbl %1,%0\";
 214       if ((unsigned)i < 0x10000)
 215         return \"movzwl %1,%0\";
 216       if (i >= -0x8000 && i < 0)
 217         return \"cvtwl %1,%0\";
 218     }
 219   if (push_operand (operands[0], SImode))
 220     return \"pushl %1\";
 221   return \"movl %1,%0\";
 222 }")
 223
 224 (define_insn "movhi"
 225   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 226         (match_operand:HI 1 "general_operand" "g"))]
 227   ""
 228   "*
 229 {
 230   if (GET_CODE (operands[1]) == CONST_INT)
 231     {
 232       int i = INTVAL (operands[1]);
 233       if (i == 0)
 234         return \"clrw %0\";
 235       else if ((unsigned int)i < 64)
 236         return \"movw %1,%0\";
 237       else if ((unsigned int)~i < 64)
 238         return \"mcomw %H1,%0\";
 239       else if ((unsigned int)i < 256)
 240         return \"movzbw %1,%0\";
 241     }
 242   return \"movw %1,%0\";
 243 }")
 244
 245 (define_insn "movstricthi"
 246   [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g"))
 247         (match_operand:HI 1 "general_operand" "g"))]
 248   ""
 249   "*
 250 {
 251   if (GET_CODE (operands[1]) == CONST_INT)
 252     {
 253       int i = INTVAL (operands[1]);
 254       if (i == 0)
 255         return \"clrw %0\";
 256       else if ((unsigned int)i < 64)
 257         return \"movw %1,%0\";
 258       else if ((unsigned int)~i < 64)
 259         return \"mcomw %H1,%0\";
 260       else if ((unsigned int)i < 256)
 261         return \"movzbw %1,%0\";
 262     }
 263   return \"movw %1,%0\";
 264 }")
 265
 266 (define_insn "movqi"
 267   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 268         (match_operand:QI 1 "general_operand" "g"))]
 269   ""
 270   "*
 271 {
 272   if (GET_CODE (operands[1]) == CONST_INT)
 273     {
 274       int i = INTVAL (operands[1]);
 275       if (i == 0)
 276         return \"clrb %0\";
 277       else if ((unsigned int)~i < 64)
 278         return \"mcomb %B1,%0\";
 279     }
 280   return \"movb %1,%0\";
 281 }")
 282
 283 (define_insn "movstrictqi"
 284   [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g"))
 285         (match_operand:QI 1 "general_operand" "g"))]
 286   ""
 287   "*
 288 {
 289   if (GET_CODE (operands[1]) == CONST_INT)
 290     {
 291       int i = INTVAL (operands[1]);
 292       if (i == 0)
 293         return \"clrb %0\";
 294       else if ((unsigned int)~i < 64)
 295         return \"mcomb %B1,%0\";
 296     }
 297   return \"movb %1,%0\";
 298 }")
 299
 300 ;; This is here to accept 4 arguments and pass the first 3 along
 301 ;; to the movstrhi1 pattern that really does the work.
 302 (define_expand "movstrhi"
 303   [(set (match_operand:BLK 0 "general_operand" "=g")
 304         (match_operand:BLK 1 "general_operand" "g"))
 305    (use (match_operand:HI 2 "general_operand" "g"))
 306    (match_operand 3 "" "")]
 307   ""
 308   "
 309   emit_insn (gen_movstrhi1 (operands[0], operands[1], operands[2]));
 310   DONE;
 311 ")
 312
 313 ;; The definition of this insn does not really explain what it does,
 314 ;; but it should suffice
 315 ;; that anything generated as this insn will be recognized as one
 316 ;; and that it won't successfully combine with anything.
 317 (define_insn "movstrhi1"
 318   [(set (match_operand:BLK 0 "memory_operand" "=m")
 319         (match_operand:BLK 1 "memory_operand" "m"))
 320    (use (match_operand:HI 2 "general_operand" "g"))
 321    (clobber (reg:SI 0))
 322    (clobber (reg:SI 1))
 323    (clobber (reg:SI 2))
 324    (clobber (reg:SI 3))
 325    (clobber (reg:SI 4))
 326    (clobber (reg:SI 5))]
 327   ""
 328   "movc3 %2,%1,%0")
 329 \f
 330 ;; Extension and truncation insns.
 331
 332 (define_insn "truncsiqi2"
 333   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 334         (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "g")))]
 335   ""
 336   "cvtlb %1,%0")
 337
 338 (define_insn "truncsihi2"
 339   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 340         (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "g")))]
 341   ""
 342   "cvtlw %1,%0")
 343
 344 (define_insn "trunchiqi2"
 345   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 346         (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
 347   ""
 348   "cvtwb %1,%0")
 349
 350 (define_insn "extendhisi2"
 351   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 352         (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
 353   ""
 354   "cvtwl %1,%0")
 355
 356 (define_insn "extendqihi2"
 357   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 358         (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
 359   ""
 360   "cvtbw %1,%0")
 361
 362 (define_insn "extendqisi2"
 363   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 364         (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
 365   ""
 366   "cvtbl %1,%0")
 367
 368 (define_insn "extendsfdf2"
 369   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
 370         (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
 371   ""
 372   "cvtf%# %1,%0")
 373
 374 (define_insn "truncdfsf2"
 375   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
 376         (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
 377   ""
 378   "cvt%#f %1,%0")
 379
 380 (define_insn "zero_extendhisi2"
 381   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 382         (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
 383   ""
 384   "movzwl %1,%0")
 385
 386 (define_insn "zero_extendqihi2"
 387   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 388         (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
 389   ""
 390   "movzbw %1,%0")
 391
 392 (define_insn "zero_extendqisi2"
 393   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 394         (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
 395   ""
 396   "movzbl %1,%0")
 397 \f
 398 ;; Fix-to-float conversion insns.
 399
 400 (define_insn "floatsisf2"
 401   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
 402         (float:SF (match_operand:SI 1 "nonimmediate_operand" "g")))]
 403   ""
 404   "cvtlf %1,%0")
 405
 406 (define_insn "floatsidf2"
 407   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
 408         (float:DF (match_operand:SI 1 "nonimmediate_operand" "g")))]
 409   ""
 410   "cvtl%# %1,%0")
 411
 412 (define_insn "floathisf2"
 413   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
 414         (float:SF (match_operand:HI 1 "nonimmediate_operand" "g")))]
 415   ""
 416   "cvtwf %1,%0")
 417
 418 (define_insn "floathidf2"
 419   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
 420         (float:DF (match_operand:HI 1 "nonimmediate_operand" "g")))]
 421   ""
 422   "cvtw%# %1,%0")
 423
 424 (define_insn "floatqisf2"
 425   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
 426         (float:SF (match_operand:QI 1 "nonimmediate_operand" "g")))]
 427   ""
 428   "cvtbf %1,%0")
 429
 430 (define_insn "floatqidf2"
 431   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
 432         (float:DF (match_operand:QI 1 "nonimmediate_operand" "g")))]
 433   ""
 434   "cvtb%# %1,%0")
 435 \f
 436 ;; Float-to-fix conversion insns.
 437
 438 (define_insn "fix_truncsfqi2"
 439   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 440         (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
 441   ""
 442   "cvtfb %1,%0")
 443
 444 (define_insn "fix_truncsfhi2"
 445   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 446         (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
 447   ""
 448   "cvtfw %1,%0")
 449
 450 (define_insn "fix_truncsfsi2"
 451   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 452         (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "gF"))))]
 453   ""
 454   "cvtfl %1,%0")
 455
 456 (define_insn "fix_truncdfqi2"
 457   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 458         (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
 459   ""
 460   "cvt%#b %1,%0")
 461
 462 (define_insn "fix_truncdfhi2"
 463   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 464         (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
 465   ""
 466   "cvt%#w %1,%0")
 467
 468 (define_insn "fix_truncdfsi2"
 469   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 470         (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "gF"))))]
 471   ""
 472   "cvt%#l %1,%0")
 473 \f
 474 ;;- All kinds of add instructions.
 475
 476 (define_insn "adddf3"
 477   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g,g")
 478         (plus:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
 479                  (match_operand:DF 2 "general_operand" "gF,0,gF")))]
 480   ""
 481   "@
 482    add%#2 %2,%0
 483    add%#2 %1,%0
 484    add%#3 %1,%2,%0")
 485
 486 (define_insn "addsf3"
 487   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g,g")
 488         (plus:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
 489                  (match_operand:SF 2 "general_operand" "gF,0,gF")))]
 490   ""
 491   "@
 492    addf2 %2,%0
 493    addf2 %1,%0
 494    addf3 %1,%2,%0")
 495
 496 /* The space-time-opcode tradeoffs for addition vary by model of VAX.
 497
 498    On a VAX 3 "movab (r1)[r2],r3" is faster than "addl3 r1,r2,r3",
 499    but it not faster on other models.
 500
 501    "movab #(r1),r2" is usually shorter than "addl3 #,r1,r2", and is
 502    faster on a VAX 3, but some VAXen (e.g. VAX 9000) will stall if
 503    a register is used in an address too soon after it is set.
 504    Compromise by using movab only when it is shorter than the add
 505    or the base register in the address is one of sp, ap, and fp,
 506    which are not modified very often.  */
 507
 508
 509 (define_insn "addsi3"
 510   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
 511         (plus:SI (match_operand:SI 1 "general_operand" "g")
 512                  (match_operand:SI 2 "general_operand" "g")))]
 513   ""
 514   "*
 515 {
 516   if (rtx_equal_p (operands[0], operands[1]))
 517     {
 518       if (operands[2] == const1_rtx)
 519         return \"incl %0\";
 520       if (operands[2] == constm1_rtx)
 521         return \"decl %0\";
 522       if (GET_CODE (operands[2]) == CONST_INT
 523           && (unsigned) (- INTVAL (operands[2])) < 64)
 524         return \"subl2 $%n2,%0\";
 525       if (GET_CODE (operands[2]) == CONST_INT
 526           && (unsigned) INTVAL (operands[2]) >= 64
 527           && GET_CODE (operands[1]) == REG
 528           && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
 529               || REGNO (operands[1]) > 11))
 530         return \"movab %c2(%1),%0\";
 531       return \"addl2 %2,%0\";
 532     }
 533   if (rtx_equal_p (operands[0], operands[2]))
 534     return \"addl2 %1,%0\";
 535
 536   if (GET_CODE (operands[2]) == CONST_INT
 537       && INTVAL (operands[2]) < 32767
 538       && INTVAL (operands[2]) > -32768
 539       && GET_CODE (operands[1]) == REG
 540       && push_operand (operands[0], SImode))
 541     return \"pushab %c2(%1)\";
 542
 543   if (GET_CODE (operands[2]) == CONST_INT
 544       && (unsigned) (- INTVAL (operands[2])) < 64)
 545     return \"subl3 $%n2,%1,%0\";
 546
 547   if (GET_CODE (operands[2]) == CONST_INT
 548       && (unsigned) INTVAL (operands[2]) >= 64
 549       && GET_CODE (operands[1]) == REG
 550       && ((INTVAL (operands[2]) < 32767 && INTVAL (operands[2]) > -32768)
 551           || REGNO (operands[1]) > 11))
 552     return \"movab %c2(%1),%0\";
 553
 554   /* Add this if using gcc on a VAX 3xxx:
 555   if (REG_P (operands[1]) && REG_P (operands[2]))
 556     return \"movab (%1)[%2],%0\";
 557   */
 558   return \"addl3 %1,%2,%0\";
 559 }")
 560
 561 (define_insn "addhi3"
 562   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
 563         (plus:HI (match_operand:HI 1 "general_operand" "g")
 564                  (match_operand:HI 2 "general_operand" "g")))]
 565   ""
 566   "*
 567 {
 568   if (rtx_equal_p (operands[0], operands[1]))
 569     {
 570       if (operands[2] == const1_rtx)
 571         return \"incw %0\";
 572       if (operands[2] == constm1_rtx)
 573         return \"decw %0\";
 574       if (GET_CODE (operands[2]) == CONST_INT
 575           && (unsigned) (- INTVAL (operands[2])) < 64)
 576         return \"subw2 $%n2,%0\";
 577       return \"addw2 %2,%0\";
 578     }
 579   if (rtx_equal_p (operands[0], operands[2]))
 580     return \"addw2 %1,%0\";
 581   if (GET_CODE (operands[2]) == CONST_INT
 582       && (unsigned) (- INTVAL (operands[2])) < 64)
 583     return \"subw3 $%n2,%1,%0\";
 584   return \"addw3 %1,%2,%0\";
 585 }")
 586
 587 (define_insn "addqi3"
 588   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
 589         (plus:QI (match_operand:QI 1 "general_operand" "g")
 590                  (match_operand:QI 2 "general_operand" "g")))]
 591   ""
 592   "*
 593 {
 594   if (rtx_equal_p (operands[0], operands[1]))
 595     {
 596       if (operands[2] == const1_rtx)
 597         return \"incb %0\";
 598       if (operands[2] == constm1_rtx)
 599         return \"decb %0\";
 600       if (GET_CODE (operands[2]) == CONST_INT
 601           && (unsigned) (- INTVAL (operands[2])) < 64)
 602         return \"subb2 $%n2,%0\";
 603       return \"addb2 %2,%0\";
 604     }
 605   if (rtx_equal_p (operands[0], operands[2]))
 606     return \"addb2 %1,%0\";
 607   if (GET_CODE (operands[2]) == CONST_INT
 608       && (unsigned) (- INTVAL (operands[2])) < 64)
 609     return \"subb3 $%n2,%1,%0\";
 610   return \"addb3 %1,%2,%0\";
 611 }")
 612
 613 ;; The add-with-carry (adwc) instruction only accepts two operands.
 614 (define_insn "adddi3"
 615   [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
 616         (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
 617                  (match_operand:DI 2 "general_operand" "Fro,F")))]
 618   ""
 619   "*
 620 {
 621   rtx low[3];
 622   const char *pattern;
 623   int carry = 1;
 624
 625   split_quadword_operands (operands, low, 3);
 626   /* Add low parts.  */
 627   if (rtx_equal_p (operands[0], operands[1]))
 628     {
 629       if (low[2] == const0_rtx)
 630         /* Should examine operand, punt if not POST_INC.  */
 631         pattern = \"tstl %0\", carry = 0;
 632       else if (low[2] == const1_rtx)
 633         pattern = \"incl %0\";
 634       else
 635         pattern = \"addl2 %2,%0\";
 636     }
 637   else
 638     {
 639       if (low[2] == const0_rtx)
 640         pattern = \"movl %1,%0\", carry = 0;
 641       else
 642         pattern = \"addl3 %2,%1,%0\";
 643     }
 644   if (pattern)
 645     output_asm_insn (pattern, low);
 646   if (!carry)
 647     /* If CARRY is 0, we don't have any carry value to worry about.  */
 648     return get_insn_template (CODE_FOR_addsi3, insn);
 649   /* %0 = C + %1 + %2 */
 650   if (!rtx_equal_p (operands[0], operands[1]))
 651     output_asm_insn ((operands[1] == const0_rtx
 652                       ? \"clrl %0\"
 653                       : \"movl %1,%0\"), operands);
 654   return \"adwc %2,%0\";
 655 }")
 656 \f
 657 ;;- All kinds of subtract instructions.
 658
 659 (define_insn "subdf3"
 660   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
 661         (minus:DF (match_operand:DF 1 "general_operand" "0,gF")
 662                   (match_operand:DF 2 "general_operand" "gF,gF")))]
 663   ""
 664   "@
 665    sub%#2 %2,%0
 666    sub%#3 %2,%1,%0")
 667
 668 (define_insn "subsf3"
 669   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
 670         (minus:SF (match_operand:SF 1 "general_operand" "0,gF")
 671                   (match_operand:SF 2 "general_operand" "gF,gF")))]
 672   ""
 673   "@
 674    subf2 %2,%0
 675    subf3 %2,%1,%0")
 676
 677 (define_insn "subsi3"
 678   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
 679         (minus:SI (match_operand:SI 1 "general_operand" "0,g")
 680                   (match_operand:SI 2 "general_operand" "g,g")))]
 681   ""
 682   "@
 683    subl2 %2,%0
 684    subl3 %2,%1,%0")
 685
 686 (define_insn "subhi3"
 687   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
 688         (minus:HI (match_operand:HI 1 "general_operand" "0,g")
 689                   (match_operand:HI 2 "general_operand" "g,g")))]
 690   ""
 691   "@
 692    subw2 %2,%0
 693    subw3 %2,%1,%0")
 694
 695 (define_insn "subqi3"
 696   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
 697         (minus:QI (match_operand:QI 1 "general_operand" "0,g")
 698                   (match_operand:QI 2 "general_operand" "g,g")))]
 699   ""
 700   "@
 701    subb2 %2,%0
 702    subb3 %2,%1,%0")
 703
 704 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
 705 (define_insn "subdi3"
 706   [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
 707         (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
 708                   (match_operand:DI 2 "general_operand" "For,F")))]
 709   ""
 710   "*
 711 {
 712   rtx low[3];
 713   const char *pattern;
 714   int carry = 1;
 715
 716   split_quadword_operands (operands, low, 3);
 717   /* Subtract low parts.  */
 718   if (rtx_equal_p (operands[0], operands[1]))
 719     {
 720       if (low[2] == const0_rtx)
 721         pattern = 0, carry = 0;
 722       else if (low[2] == constm1_rtx)
 723         pattern = \"decl %0\";
 724       else
 725         pattern = \"subl2 %2,%0\";
 726     }
 727   else
 728     {
 729       if (low[2] == constm1_rtx)
 730         pattern = \"decl %0\";
 731       else if (low[2] == const0_rtx)
 732         pattern = get_insn_template (CODE_FOR_movsi, insn), carry = 0;
 733       else
 734         pattern = \"subl3 %2,%1,%0\";
 735     }
 736   if (pattern)
 737     output_asm_insn (pattern, low);
 738   if (carry)
 739     {
 740       if (!rtx_equal_p (operands[0], operands[1]))
 741         return \"movl %1,%0\;sbwc %2,%0\";
 742       return \"sbwc %2,%0\";
 743       /* %0 = %2 - %1 - C */
 744     }
 745   return get_insn_template (CODE_FOR_subsi3, insn);
 746 }")
 747 \f
 748 ;;- Multiply instructions.
 749
 750 (define_insn "muldf3"
 751   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g,g")
 752         (mult:DF (match_operand:DF 1 "general_operand" "0,gF,gF")
 753                  (match_operand:DF 2 "general_operand" "gF,0,gF")))]
 754   ""
 755   "@
 756    mul%#2 %2,%0
 757    mul%#2 %1,%0
 758    mul%#3 %1,%2,%0")
 759
 760 (define_insn "mulsf3"
 761   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g,g")
 762         (mult:SF (match_operand:SF 1 "general_operand" "0,gF,gF")
 763                  (match_operand:SF 2 "general_operand" "gF,0,gF")))]
 764   ""
 765   "@
 766    mulf2 %2,%0
 767    mulf2 %1,%0
 768    mulf3 %1,%2,%0")
 769
 770 (define_insn "mulsi3"
 771   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
 772         (mult:SI (match_operand:SI 1 "general_operand" "0,g,g")
 773                  (match_operand:SI 2 "general_operand" "g,0,g")))]
 774   ""
 775   "@
 776    mull2 %2,%0
 777    mull2 %1,%0
 778    mull3 %1,%2,%0")
 779
 780 (define_insn "mulhi3"
 781   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,")
 782         (mult:HI (match_operand:HI 1 "general_operand" "0,g,g")
 783                  (match_operand:HI 2 "general_operand" "g,0,g")))]
 784   ""
 785   "@
 786    mulw2 %2,%0
 787    mulw2 %1,%0
 788    mulw3 %1,%2,%0")
 789
 790 (define_insn "mulqi3"
 791   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
 792         (mult:QI (match_operand:QI 1 "general_operand" "0,g,g")
 793                  (match_operand:QI 2 "general_operand" "g,0,g")))]
 794   ""
 795   "@
 796    mulb2 %2,%0
 797    mulb2 %1,%0
 798    mulb3 %1,%2,%0")
 799
 800 (define_insn "mulsidi3"
 801   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 802         (mult:DI (sign_extend:DI
 803                   (match_operand:SI 1 "nonimmediate_operand" "g"))
 804                  (sign_extend:DI
 805                   (match_operand:SI 2 "nonimmediate_operand" "g"))))]
 806   ""
 807   "emul %1,%2,$0,%0")
 808
 809 (define_insn ""
 810   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 811         (plus:DI
 812          (mult:DI (sign_extend:DI
 813                    (match_operand:SI 1 "nonimmediate_operand" "g"))
 814                   (sign_extend:DI
 815                    (match_operand:SI 2 "nonimmediate_operand" "g")))
 816          (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))]
 817   ""
 818   "emul %1,%2,%3,%0")
 819
 820 ;; 'F' constraint means type CONST_DOUBLE
 821 (define_insn ""
 822   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
 823         (plus:DI
 824          (mult:DI (sign_extend:DI
 825                    (match_operand:SI 1 "nonimmediate_operand" "g"))
 826                   (sign_extend:DI
 827                    (match_operand:SI 2 "nonimmediate_operand" "g")))
 828          (match_operand:DI 3 "immediate_operand" "F")))]
 829   "GET_CODE (operands[3]) == CONST_DOUBLE
 830     && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
 831   "*
 832 {
 833   if (CONST_DOUBLE_HIGH (operands[3]))
 834     operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
 835   return \"emul %1,%2,%3,%0\";
 836 }")
 837 \f
 838 ;;- Divide instructions.
 839
 840 (define_insn "divdf3"
 841   [(set (match_operand:DF 0 "nonimmediate_operand" "=g,g")
 842         (div:DF (match_operand:DF 1 "general_operand" "0,gF")
 843                 (match_operand:DF 2 "general_operand" "gF,gF")))]
 844   ""
 845   "@
 846    div%#2 %2,%0
 847    div%#3 %2,%1,%0")
 848
 849 (define_insn "divsf3"
 850   [(set (match_operand:SF 0 "nonimmediate_operand" "=g,g")
 851         (div:SF (match_operand:SF 1 "general_operand" "0,gF")
 852                 (match_operand:SF 2 "general_operand" "gF,gF")))]
 853   ""
 854   "@
 855    divf2 %2,%0
 856    divf3 %2,%1,%0")
 857
 858 (define_insn "divsi3"
 859   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
 860         (div:SI (match_operand:SI 1 "general_operand" "0,g")
 861                 (match_operand:SI 2 "general_operand" "g,g")))]
 862   ""
 863   "@
 864    divl2 %2,%0
 865    divl3 %2,%1,%0")
 866
 867 (define_insn "divhi3"
 868   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
 869         (div:HI (match_operand:HI 1 "general_operand" "0,g")
 870                 (match_operand:HI 2 "general_operand" "g,g")))]
 871   ""
 872   "@
 873    divw2 %2,%0
 874    divw3 %2,%1,%0")
 875
 876 (define_insn "divqi3"
 877   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
 878         (div:QI (match_operand:QI 1 "general_operand" "0,g")
 879                 (match_operand:QI 2 "general_operand" "g,g")))]
 880   ""
 881   "@
 882    divb2 %2,%0
 883    divb3 %2,%1,%0")
 884
 885 ;This is left out because it is very slow;
 886 ;we are better off programming around the "lack" of this insn.
 887 ;(define_insn "divmoddisi4"
 888 ;  [(set (match_operand:SI 0 "general_operand" "=g")
 889 ;       (div:SI (match_operand:DI 1 "general_operand" "g")
 890 ;               (match_operand:SI 2 "general_operand" "g")))
 891 ;   (set (match_operand:SI 3 "general_operand" "=g")
 892 ;       (mod:SI (match_operand:DI 1 "general_operand" "g")
 893 ;               (match_operand:SI 2 "general_operand" "g")))]
 894 ;  ""
 895 ;  "ediv %2,%1,%0,%3")
 896 \f
 897 ;; Bit-and on the VAX is done with a clear-bits insn.
 898 (define_expand "andsi3"
 899   [(set (match_operand:SI 0 "nonimmediate_operand" "")
 900         (and:SI (not:SI (match_operand:SI 1 "general_operand" ""))
 901                 (match_operand:SI 2 "general_operand" "")))]
 902   ""
 903   "
 904 {
 905   rtx op1 = operands[1];
 906
 907   /* If there is a constant argument, complement that one.  */
 908   if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
 909     {
 910       operands[1] = operands[2];
 911       operands[2] = op1;
 912       op1 = operands[1];
 913     }
 914
 915   if (GET_CODE (op1) == CONST_INT)
 916     operands[1] = GEN_INT (~INTVAL (op1));
 917   else
 918     operands[1] = expand_unop (SImode, one_cmpl_optab, op1, 0, 1);
 919 }")
 920
 921 (define_expand "andhi3"
 922   [(set (match_operand:HI 0 "nonimmediate_operand" "")
 923         (and:HI (not:HI (match_operand:HI 1 "general_operand" ""))
 924                 (match_operand:HI 2 "general_operand" "")))]
 925   ""
 926   "
 927 {
 928   rtx op1 = operands[1];
 929
 930   if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
 931     {
 932       operands[1] = operands[2];
 933       operands[2] = op1;
 934       op1 = operands[1];
 935     }
 936
 937   if (GET_CODE (op1) == CONST_INT)
 938     operands[1] = GEN_INT (~INTVAL (op1));
 939   else
 940     operands[1] = expand_unop (HImode, one_cmpl_optab, op1, 0, 1);
 941 }")
 942
 943 (define_expand "andqi3"
 944   [(set (match_operand:QI 0 "nonimmediate_operand" "")
 945         (and:QI (not:QI (match_operand:QI 1 "general_operand" ""))
 946                 (match_operand:QI 2 "general_operand" "")))]
 947   ""
 948   "
 949 {
 950   rtx op1 = operands[1];
 951
 952   if (GET_CODE (operands[2]) == CONST_INT && GET_CODE (op1) != CONST_INT)
 953     {
 954      operands[1] = operands[2];
 955      operands[2] = op1;
 956      op1 = operands[1];
 957    }
 958
 959   if (GET_CODE (op1) == CONST_INT)
 960     operands[1] = GEN_INT (~INTVAL (op1));
 961   else
 962     operands[1] = expand_unop (QImode, one_cmpl_optab, op1, 0, 1);
 963 }")
 964
 965 (define_insn ""
 966   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
 967         (and:SI (not:SI (match_operand:SI 1 "general_operand" "g,g"))
 968                 (match_operand:SI 2 "general_operand" "0,g")))]
 969   ""
 970   "@
 971    bicl2 %1,%0
 972    bicl3 %1,%2,%0")
 973
 974 (define_insn ""
 975   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
 976         (and:HI (not:HI (match_operand:HI 1 "general_operand" "g,g"))
 977                 (match_operand:HI 2 "general_operand" "0,g")))]
 978   ""
 979   "@
 980    bicw2 %1,%0
 981    bicw3 %1,%2,%0")
 982
 983 (define_insn ""
 984   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
 985         (and:QI (not:QI (match_operand:QI 1 "general_operand" "g,g"))
 986                 (match_operand:QI 2 "general_operand" "0,g")))]
 987   ""
 988   "@
 989    bicb2 %1,%0
 990    bicb3 %1,%2,%0")
 991
 992 ;; The following used to be needed because constant propagation can
 993 ;; create them starting from the bic insn patterns above.  This is no
 994 ;; longer a problem.  However, having these patterns allows optimization
 995 ;; opportunities in combine.c.
 996
 997 (define_insn ""
 998   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g")
 999         (and:SI (match_operand:SI 1 "general_operand" "0,g")
1000                 (match_operand:SI 2 "const_int_operand" "n,n")))]
1001   ""
1002   "@
1003    bicl2 %N2,%0
1004    bicl3 %N2,%1,%0")
1005
1006 (define_insn ""
1007   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g")
1008         (and:HI (match_operand:HI 1 "general_operand" "0,g")
1009                 (match_operand:HI 2 "const_int_operand" "n,n")))]
1010   ""
1011   "@
1012    bicw2 %H2,%0
1013    bicw3 %H2,%1,%0")
1014
1015 (define_insn ""
1016   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g")
1017         (and:QI (match_operand:QI 1 "general_operand" "0,g")
1018                 (match_operand:QI 2 "const_int_operand" "n,n")))]
1019   ""
1020   "@
1021    bicb2 %B2,%0
1022    bicb3 %B2,%1,%0")
1023 \f
1024 ;;- Bit set instructions.
1025
1026 (define_insn "iorsi3"
1027   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
1028         (ior:SI (match_operand:SI 1 "general_operand" "0,g,g")
1029                 (match_operand:SI 2 "general_operand" "g,0,g")))]
1030   ""
1031   "@
1032    bisl2 %2,%0
1033    bisl2 %1,%0
1034    bisl3 %2,%1,%0")
1035
1036 (define_insn "iorhi3"
1037   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,g")
1038         (ior:HI (match_operand:HI 1 "general_operand" "0,g,g")
1039                 (match_operand:HI 2 "general_operand" "g,0,g")))]
1040   ""
1041   "@
1042    bisw2 %2,%0
1043    bisw2 %1,%0
1044    bisw3 %2,%1,%0")
1045
1046 (define_insn "iorqi3"
1047   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
1048         (ior:QI (match_operand:QI 1 "general_operand" "0,g,g")
1049                 (match_operand:QI 2 "general_operand" "g,0,g")))]
1050   ""
1051   "@
1052    bisb2 %2,%0
1053    bisb2 %1,%0
1054    bisb3 %2,%1,%0")
1055
1056 ;;- xor instructions.
1057
1058 (define_insn "xorsi3"
1059   [(set (match_operand:SI 0 "nonimmediate_operand" "=g,g,g")
1060         (xor:SI (match_operand:SI 1 "general_operand" "0,g,g")
1061                 (match_operand:SI 2 "general_operand" "g,0,g")))]
1062   ""
1063   "@
1064    xorl2 %2,%0
1065    xorl2 %1,%0
1066    xorl3 %2,%1,%0")
1067
1068 (define_insn "xorhi3"
1069   [(set (match_operand:HI 0 "nonimmediate_operand" "=g,g,g")
1070         (xor:HI (match_operand:HI 1 "general_operand" "0,g,g")
1071                 (match_operand:HI 2 "general_operand" "g,0,g")))]
1072   ""
1073   "@
1074    xorw2 %2,%0
1075    xorw2 %1,%0
1076    xorw3 %2,%1,%0")
1077
1078 (define_insn "xorqi3"
1079   [(set (match_operand:QI 0 "nonimmediate_operand" "=g,g,g")
1080         (xor:QI (match_operand:QI 1 "general_operand" "0,g,g")
1081                 (match_operand:QI 2 "general_operand" "g,0,g")))]
1082   ""
1083   "@
1084    xorb2 %2,%0
1085    xorb2 %1,%0
1086    xorb3 %2,%1,%0")
1087 \f
1088 (define_insn "negdf2"
1089   [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
1090         (neg:DF (match_operand:DF 1 "general_operand" "gF")))]
1091   ""
1092   "mneg%# %1,%0")
1093
1094 (define_insn "negsf2"
1095   [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
1096         (neg:SF (match_operand:SF 1 "general_operand" "gF")))]
1097   ""
1098   "mnegf %1,%0")
1099
1100 (define_insn "negsi2"
1101   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1102         (neg:SI (match_operand:SI 1 "general_operand" "g")))]
1103   ""
1104   "mnegl %1,%0")
1105
1106 (define_insn "neghi2"
1107   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1108         (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1109   ""
1110   "mnegw %1,%0")
1111
1112 (define_insn "negqi2"
1113   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
1114         (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1115   ""
1116   "mnegb %1,%0")
1117 \f
1118 (define_insn "one_cmplsi2"
1119   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1120         (not:SI (match_operand:SI 1 "general_operand" "g")))]
1121   ""
1122   "mcoml %1,%0")
1123
1124 (define_insn "one_cmplhi2"
1125   [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
1126         (not:HI (match_operand:HI 1 "general_operand" "g")))]
1127   ""
1128   "mcomw %1,%0")
1129
1130 (define_insn "one_cmplqi2"
1131   [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
1132         (not:QI (match_operand:QI 1 "general_operand" "g")))]
1133   ""
1134   "mcomb %1,%0")
1135 \f
1136 ;; Arithmetic right shift on the VAX works by negating the shift count,
1137 ;; then emitting a right shift with the shift count negated.  This means
1138 ;; that all actual shift counts in the RTL will be positive.  This
1139 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1140 ;; which isn't valid.
1141 (define_expand "ashrsi3"
1142   [(set (match_operand:SI 0 "general_operand" "=g")
1143         (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1144                    (match_operand:QI 2 "general_operand" "g")))]
1145   ""
1146   "
1147 {
1148   if (GET_CODE (operands[2]) != CONST_INT)
1149     operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1150 }")
1151
1152 (define_insn ""
1153   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1154         (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1155                      (match_operand:QI 2 "const_int_operand" "n")))]
1156   ""
1157   "ashl $%n2,%1,%0")
1158
1159 (define_insn ""
1160   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1161         (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1162                      (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1163   ""
1164   "ashl %2,%1,%0")
1165
1166 (define_insn "ashlsi3"
1167   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1168         (ashift:SI (match_operand:SI 1 "general_operand" "g")
1169                    (match_operand:QI 2 "general_operand" "g")))]
1170   ""
1171   "*
1172 {
1173   if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1174     return \"addl2 %0,%0\";
1175   if (GET_CODE (operands[1]) == REG
1176       && GET_CODE (operands[2]) == CONST_INT)
1177     {
1178       int i = INTVAL (operands[2]);
1179       if (i == 1)
1180         return \"addl3 %1,%1,%0\";
1181       if (i == 2)
1182         return \"moval 0[%1],%0\";
1183       if (i == 3)
1184         return \"movad 0[%1],%0\";
1185     }
1186   return \"ashl %2,%1,%0\";
1187 }")
1188
1189 ;; Arithmetic right shift on the VAX works by negating the shift count.
1190 (define_expand "ashrdi3"
1191   [(set (match_operand:DI 0 "general_operand" "=g")
1192         (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1193                      (match_operand:QI 2 "general_operand" "g")))]
1194   ""
1195   "
1196 {
1197   operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1198 }")
1199
1200 (define_insn "ashldi3"
1201   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1202         (ashift:DI (match_operand:DI 1 "general_operand" "g")
1203                    (match_operand:QI 2 "general_operand" "g")))]
1204   ""
1205   "ashq %2,%1,%0")
1206
1207 (define_insn ""
1208   [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1209         (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1210                      (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1211   ""
1212   "ashq %2,%1,%0")
1213
1214 ;; We used to have expand_shift handle logical right shifts by using extzv,
1215 ;; but this make it very difficult to do lshrdi3.  Since the VAX is the
1216 ;; only machine with this kludge, it's better to just do this with a
1217 ;; define_expand and remove that case from expand_shift.
1218
1219 (define_expand "lshrsi3"
1220   [(set (match_dup 3)
1221         (minus:QI (const_int 32)
1222                   (match_dup 4)))
1223    (set (match_operand:SI 0 "general_operand" "=g")
1224         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1225                          (match_dup 3)
1226                          (match_operand:SI 2 "register_operand" "g")))]
1227   ""
1228   "
1229 {
1230   operands[3] = gen_reg_rtx (QImode);
1231   operands[4] = gen_lowpart (QImode, operands[2]);
1232 }")
1233
1234 ;; Rotate right on the VAX works by negating the shift count.
1235 (define_expand "rotrsi3"
1236   [(set (match_operand:SI 0 "general_operand" "=g")
1237         (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1238                      (match_operand:QI 2 "general_operand" "g")))]
1239   ""
1240   "
1241 {
1242   if (GET_CODE (operands[2]) != CONST_INT)
1243     operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1244 }")
1245
1246 (define_insn "rotlsi3"
1247   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1248         (rotate:SI (match_operand:SI 1 "general_operand" "g")
1249                    (match_operand:QI 2 "general_operand" "g")))]
1250   ""
1251   "rotl %2,%1,%0")
1252
1253 (define_insn ""
1254   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1255         (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1256                      (match_operand:QI 2 "const_int_operand" "n")))]
1257   ""
1258   "rotl %R2,%1,%0")
1259
1260 (define_insn ""
1261   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1262         (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1263                      (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1264   ""
1265   "rotl %2,%1,%0")
1266
1267 ;This insn is probably slower than a multiply and an add.
1268 ;(define_insn ""
1269 ;  [(set (match_operand:SI 0 "general_operand" "=g")
1270 ;       (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1271 ;                         (match_operand:SI 2 "general_operand" "g"))
1272 ;                (match_operand:SI 3 "general_operand" "g")))]
1273 ;  ""
1274 ;  "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1275 \f
1276 ;; Special cases of bit-field insns which we should
1277 ;; recognize in preference to the general case.
1278 ;; These handle aligned 8-bit and 16-bit fields,
1279 ;; which can usually be done with move instructions.
1280
1281 (define_insn ""
1282   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro")
1283                          (match_operand:QI 1 "const_int_operand" "n")
1284                          (match_operand:SI 2 "const_int_operand" "n"))
1285         (match_operand:SI 3 "general_operand" "g"))]
1286    "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1287    && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1288    && (GET_CODE (operands[0]) == REG
1289        || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
1290   "*
1291 {
1292   if (REG_P (operands[0]))
1293     {
1294       if (INTVAL (operands[2]) != 0)
1295         return \"insv %3,%2,%1,%0\";
1296     }
1297   else
1298     operands[0]
1299       = adjust_address (operands[0],
1300                         INTVAL (operands[1]) == 8 ? QImode : HImode,
1301                         INTVAL (operands[2]) / 8);
1302
1303   CC_STATUS_INIT;
1304   if (INTVAL (operands[1]) == 8)
1305     return \"movb %3,%0\";
1306   return \"movw %3,%0\";
1307 }")
1308
1309 (define_insn ""
1310   [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
1311         (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1312                          (match_operand:QI 2 "const_int_operand" "n")
1313                          (match_operand:SI 3 "const_int_operand" "n")))]
1314   "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1315    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1316    && (GET_CODE (operands[1]) == REG
1317        || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1318   "*
1319 {
1320   if (REG_P (operands[1]))
1321     {
1322       if (INTVAL (operands[3]) != 0)
1323         return \"extzv %3,%2,%1,%0\";
1324     }
1325   else
1326     operands[1]
1327       = adjust_address (operands[1],
1328                         INTVAL (operands[2]) == 8 ? QImode : HImode,
1329                         INTVAL (operands[3]) / 8);
1330
1331   if (INTVAL (operands[2]) == 8)
1332     return \"movzbl %1,%0\";
1333   return \"movzwl %1,%0\";
1334 }")
1335
1336 (define_insn ""
1337   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1338         (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1339                          (match_operand:QI 2 "const_int_operand" "n")
1340                          (match_operand:SI 3 "const_int_operand" "n")))]
1341   "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1342    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1343    && (GET_CODE (operands[1]) == REG
1344        || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
1345   "*
1346 {
1347   if (REG_P (operands[1]))
1348     {
1349       if (INTVAL (operands[3]) != 0)
1350         return \"extv %3,%2,%1,%0\";
1351     }
1352   else
1353     operands[1]
1354       = adjust_address (operands[1],
1355                         INTVAL (operands[2]) == 8 ? QImode : HImode,
1356                         INTVAL (operands[3]) / 8);
1357
1358   if (INTVAL (operands[2]) == 8)
1359     return \"cvtbl %1,%0\";
1360   return \"cvtwl %1,%0\";
1361 }")
1362 \f
1363 ;; Register-only SImode cases of bit-field insns.
1364
1365 (define_insn ""
1366   [(set (cc0)
1367         (compare
1368          (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
1369                           (match_operand:QI 1 "general_operand" "g")
1370                           (match_operand:SI 2 "general_operand" "g"))
1371          (match_operand:SI 3 "general_operand" "g")))]
1372   ""
1373   "cmpv %2,%1,%0,%3")
1374
1375 (define_insn ""
1376   [(set (cc0)
1377         (compare
1378          (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1379                           (match_operand:QI 1 "general_operand" "g")
1380                           (match_operand:SI 2 "general_operand" "g"))
1381          (match_operand:SI 3 "general_operand" "g")))]
1382   ""
1383   "cmpzv %2,%1,%0,%3")
1384
1385 ;; When the field position and size are constant and the destination
1386 ;; is a register, extv and extzv are much slower than a rotate followed
1387 ;; by a bicl or sign extension.  Because we might end up choosing ext[z]v
1388 ;; anyway, we can't allow immediate values for the primary source operand.
1389
1390 (define_insn ""
1391   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1392         (sign_extract:SI (match_operand:SI 1 "register_operand" "ro")
1393                          (match_operand:QI 2 "general_operand" "g")
1394                          (match_operand:SI 3 "general_operand" "g")))]
1395   ""
1396   "*
1397 {
1398   if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1399       || GET_CODE (operands[0]) != REG
1400       || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
1401     return \"extv %3,%2,%1,%0\";
1402   if (INTVAL (operands[2]) == 8)
1403     return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1404   return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1405 }")
1406
1407 (define_insn ""
1408   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1409         (zero_extract:SI (match_operand:SI 1 "register_operand" "ro")
1410                          (match_operand:QI 2 "general_operand" "g")
1411                          (match_operand:SI 3 "general_operand" "g")))]
1412   ""
1413   "*
1414 {
1415   if (GET_CODE (operands[3]) != CONST_INT || GET_CODE (operands[2]) != CONST_INT
1416       || GET_CODE (operands[0]) != REG)
1417     return \"extzv %3,%2,%1,%0\";
1418   if (INTVAL (operands[2]) == 8)
1419     return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1420   if (INTVAL (operands[2]) == 16)
1421     return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1422   if (INTVAL (operands[3]) & 31)
1423     return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1424   if (rtx_equal_p (operands[0], operands[1]))
1425     return \"bicl2 %M2,%0\";
1426   return \"bicl3 %M2,%1,%0\";
1427 }")
1428
1429 ;; Non-register cases.
1430 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1431 ;; don't match these (and therefore match the cases above instead).
1432
1433 (define_insn ""
1434   [(set (cc0)
1435         (compare
1436          (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
1437                           (match_operand:QI 1 "general_operand" "g")
1438                           (match_operand:SI 2 "general_operand" "g"))
1439          (match_operand:SI 3 "general_operand" "g")))]
1440   ""
1441   "cmpv %2,%1,%0,%3")
1442
1443 (define_insn ""
1444   [(set (cc0)
1445         (compare
1446          (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm")
1447                           (match_operand:QI 1 "general_operand" "g")
1448                           (match_operand:SI 2 "general_operand" "g"))
1449          (match_operand:SI 3 "general_operand" "g")))]
1450   ""
1451   "cmpzv %2,%1,%0,%3")
1452
1453 (define_insn "extv"
1454   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1455         (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
1456                          (match_operand:QI 2 "general_operand" "g")
1457                          (match_operand:SI 3 "general_operand" "g")))]
1458   ""
1459   "*
1460 {
1461   if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1462       || GET_CODE (operands[3]) != CONST_INT
1463       || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
1464       || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1465       || side_effects_p (operands[1])
1466       || (GET_CODE (operands[1]) == MEM
1467           && mode_dependent_address_p (XEXP (operands[1], 0))))
1468     return \"extv %3,%2,%1,%0\";
1469   if (INTVAL (operands[2]) == 8)
1470     return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1471   return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1472 }")
1473
1474 (define_expand "extzv"
1475   [(set (match_operand:SI 0 "general_operand" "")
1476         (zero_extract:SI (match_operand:SI 1 "general_operand" "")
1477                          (match_operand:QI 2 "general_operand" "")
1478                          (match_operand:SI 3 "general_operand" "")))]
1479   ""
1480   "")
1481
1482 (define_insn ""
1483   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1484         (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
1485                          (match_operand:QI 2 "general_operand" "g")
1486                          (match_operand:SI 3 "general_operand" "g")))]
1487   ""
1488   "*
1489 {
1490   if (GET_CODE (operands[0]) != REG || GET_CODE (operands[2]) != CONST_INT
1491       || GET_CODE (operands[3]) != CONST_INT
1492       || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
1493       || side_effects_p (operands[1])
1494       || (GET_CODE (operands[1]) == MEM
1495           && mode_dependent_address_p (XEXP (operands[1], 0))))
1496     return \"extzv %3,%2,%1,%0\";
1497   if (INTVAL (operands[2]) == 8)
1498     return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1499   if (INTVAL (operands[2]) == 16)
1500     return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1501   return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1502 }")
1503
1504 (define_expand "insv"
1505   [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
1506                          (match_operand:QI 1 "general_operand" "")
1507                          (match_operand:SI 2 "general_operand" ""))
1508         (match_operand:SI 3 "general_operand" ""))]
1509   ""
1510   "")
1511
1512 (define_insn ""
1513   [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g")
1514                          (match_operand:QI 1 "general_operand" "g")
1515                          (match_operand:SI 2 "general_operand" "g"))
1516         (match_operand:SI 3 "general_operand" "g"))]
1517   ""
1518   "insv %3,%2,%1,%0")
1519
1520 (define_insn ""
1521   [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1522                          (match_operand:QI 1 "general_operand" "g")
1523                          (match_operand:SI 2 "general_operand" "g"))
1524         (match_operand:SI 3 "general_operand" "g"))]
1525   ""
1526   "insv %3,%2,%1,%0")
1527 \f
1528 (define_insn "jump"
1529   [(set (pc)
1530         (label_ref (match_operand 0 "" "")))]
1531   ""
1532   "jbr %l0")
1533
1534 (define_insn "beq"
1535   [(set (pc)
1536         (if_then_else (eq (cc0)
1537                           (const_int 0))
1538                       (label_ref (match_operand 0 "" ""))
1539                       (pc)))]
1540   ""
1541   "jeql %l0")
1542
1543 (define_insn "bne"
1544   [(set (pc)
1545         (if_then_else (ne (cc0)
1546                           (const_int 0))
1547                       (label_ref (match_operand 0 "" ""))
1548                       (pc)))]
1549   ""
1550   "jneq %l0")
1551
1552 (define_insn "bgt"
1553   [(set (pc)
1554         (if_then_else (gt (cc0)
1555                           (const_int 0))
1556                       (label_ref (match_operand 0 "" ""))
1557                       (pc)))]
1558   ""
1559   "jgtr %l0")
1560
1561 (define_insn "bgtu"
1562   [(set (pc)
1563         (if_then_else (gtu (cc0)
1564                            (const_int 0))
1565                       (label_ref (match_operand 0 "" ""))
1566                       (pc)))]
1567   ""
1568   "jgtru %l0")
1569
1570 (define_insn "blt"
1571   [(set (pc)
1572         (if_then_else (lt (cc0)
1573                           (const_int 0))
1574                       (label_ref (match_operand 0 "" ""))
1575                       (pc)))]
1576   ""
1577   "jlss %l0")
1578
1579 (define_insn "bltu"
1580   [(set (pc)
1581         (if_then_else (ltu (cc0)
1582                            (const_int 0))
1583                       (label_ref (match_operand 0 "" ""))
1584                       (pc)))]
1585   ""
1586   "jlssu %l0")
1587
1588 (define_insn "bge"
1589   [(set (pc)
1590         (if_then_else (ge (cc0)
1591                           (const_int 0))
1592                       (label_ref (match_operand 0 "" ""))
1593                       (pc)))]
1594   ""
1595   "jgeq %l0")
1596
1597 (define_insn "bgeu"
1598   [(set (pc)
1599         (if_then_else (geu (cc0)
1600                            (const_int 0))
1601                       (label_ref (match_operand 0 "" ""))
1602                       (pc)))]
1603   ""
1604   "jgequ %l0")
1605
1606 (define_insn "ble"
1607   [(set (pc)
1608         (if_then_else (le (cc0)
1609                           (const_int 0))
1610                       (label_ref (match_operand 0 "" ""))
1611                       (pc)))]
1612   ""
1613   "jleq %l0")
1614
1615 (define_insn "bleu"
1616   [(set (pc)
1617         (if_then_else (leu (cc0)
1618                            (const_int 0))
1619                       (label_ref (match_operand 0 "" ""))
1620                       (pc)))]
1621   ""
1622   "jlequ %l0")
1623
1624 ;; Recognize reversed jumps.
1625 (define_insn ""
1626   [(set (pc)
1627         (if_then_else (match_operator 0 "comparison_operator"
1628                                       [(cc0)
1629                                        (const_int 0)])
1630                       (pc)
1631                       (label_ref (match_operand 1 "" ""))))]
1632   ""
1633   "j%C0 %l1") ; %C0 negates condition
1634 \f
1635 ;; Recognize jbs, jlbs, jbc and jlbc instructions.  Note that the operand
1636 ;; of jlbs and jlbc insns are SImode in the hardware.  However, if it is
1637 ;; memory, we use QImode in the insn.  So we can't use those instructions
1638 ;; for mode-dependent addresses.
1639
1640 (define_insn ""
1641   [(set (pc)
1642         (if_then_else
1643          (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1644                               (const_int 1)
1645                               (match_operand:SI 1 "general_operand" "I,g"))
1646              (const_int 0))
1647          (label_ref (match_operand 2 "" ""))
1648          (pc)))]
1649   ""
1650   "@
1651    jlbs %0,%l2
1652    jbs %1,%0,%l2")
1653
1654 (define_insn ""
1655   [(set (pc)
1656         (if_then_else
1657          (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
1658                               (const_int 1)
1659                               (match_operand:SI 1 "general_operand" "I,g"))
1660              (const_int 0))
1661          (label_ref (match_operand 2 "" ""))
1662          (pc)))]
1663   ""
1664   "@
1665    jlbc %0,%l2
1666    jbc %1,%0,%l2")
1667
1668 (define_insn ""
1669   [(set (pc)
1670         (if_then_else
1671          (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1672                               (const_int 1)
1673                               (match_operand:SI 1 "general_operand" "I,g"))
1674              (const_int 0))
1675          (label_ref (match_operand 2 "" ""))
1676          (pc)))]
1677   ""
1678   "@
1679    jlbs %0,%l2
1680    jbs %1,%0,%l2")
1681
1682 (define_insn ""
1683   [(set (pc)
1684         (if_then_else
1685          (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
1686                               (const_int 1)
1687                               (match_operand:SI 1 "general_operand" "I,g"))
1688              (const_int 0))
1689          (label_ref (match_operand 2 "" ""))
1690          (pc)))]
1691   ""
1692   "@
1693    jlbc %0,%l2
1694    jbc %1,%0,%l2")
1695 \f
1696 ;; Subtract-and-jump and Add-and-jump insns.
1697 ;; These are not used when output is for the Unix assembler
1698 ;; because it does not know how to modify them to reach far.
1699
1700 ;; Normal sob insns.
1701
1702 (define_insn ""
1703   [(set (pc)
1704         (if_then_else
1705          (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1706                       (const_int -1))
1707              (const_int 0))
1708          (label_ref (match_operand 1 "" ""))
1709          (pc)))
1710    (set (match_dup 0)
1711         (plus:SI (match_dup 0)
1712                  (const_int -1)))]
1713   "!TARGET_UNIX_ASM"
1714   "jsobgtr %0,%l1")
1715
1716 (define_insn ""
1717   [(set (pc)
1718         (if_then_else
1719          (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1720                       (const_int -1))
1721              (const_int 0))
1722          (label_ref (match_operand 1 "" ""))
1723          (pc)))
1724    (set (match_dup 0)
1725         (plus:SI (match_dup 0)
1726                  (const_int -1)))]
1727   "!TARGET_UNIX_ASM"
1728   "jsobgeq %0,%l1")
1729
1730 ;; Normal aob insns.  Define a version for when operands[1] is a constant.
1731 (define_insn ""
1732   [(set (pc)
1733         (if_then_else
1734          (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1735                       (const_int 1))
1736              (match_operand:SI 1 "general_operand" "g"))
1737          (label_ref (match_operand 2 "" ""))
1738          (pc)))
1739    (set (match_dup 0)
1740         (plus:SI (match_dup 0)
1741                  (const_int 1)))]
1742   "!TARGET_UNIX_ASM"
1743   "jaoblss %1,%0,%l2")
1744
1745 (define_insn ""
1746   [(set (pc)
1747         (if_then_else
1748          (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
1749              (match_operand:SI 1 "general_operand" "g"))
1750          (label_ref (match_operand 2 "" ""))
1751          (pc)))
1752    (set (match_dup 0)
1753         (plus:SI (match_dup 0)
1754                  (const_int 1)))]
1755   "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1756   "jaoblss %P1,%0,%l2")
1757
1758 (define_insn ""
1759   [(set (pc)
1760         (if_then_else
1761          (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
1762                       (const_int 1))
1763              (match_operand:SI 1 "general_operand" "g"))
1764          (label_ref (match_operand 2 "" ""))
1765          (pc)))
1766    (set (match_dup 0)
1767         (plus:SI (match_dup 0)
1768                  (const_int 1)))]
1769   "!TARGET_UNIX_ASM"
1770   "jaobleq %1,%0,%l2")
1771
1772 (define_insn ""
1773   [(set (pc)
1774         (if_then_else
1775          (le (match_operand:SI 0 "nonimmediate_operand" "+g")
1776              (match_operand:SI 1 "general_operand" "g"))
1777          (label_ref (match_operand 2 "" ""))
1778          (pc)))
1779    (set (match_dup 0)
1780         (plus:SI (match_dup 0)
1781                  (const_int 1)))]
1782   "!TARGET_UNIX_ASM && GET_CODE (operands[1]) == CONST_INT"
1783   "jaobleq %P1,%0,%l2")
1784
1785 ;; Something like a sob insn, but compares against -1.
1786 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
1787
1788 (define_insn ""
1789   [(set (pc)
1790         (if_then_else
1791          (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
1792              (const_int 0))
1793          (label_ref (match_operand 1 "" ""))
1794          (pc)))
1795    (set (match_dup 0)
1796         (plus:SI (match_dup 0)
1797                  (const_int -1)))]
1798   ""
1799   "decl %0\;jgequ %l1")
1800 \f
1801 (define_expand "call_pop"
1802   [(parallel [(call (match_operand:QI 0 "memory_operand" "")
1803                     (match_operand:SI 1 "const_int_operand" ""))
1804               (set (reg:SI 14)
1805                    (plus:SI (reg:SI 14)
1806                             (match_operand:SI 3 "immediate_operand" "")))])]
1807   ""
1808 {
1809   if (INTVAL (operands[3]) > 255 * 4 || INTVAL (operands[3]) % 4)
1810     abort ();
1811
1812   /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1813      during EH unwinding.  We must include the argument count pushed by
1814      the calls instruction.  */
1815   operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
1816 })
1817
1818 (define_insn "*call_pop"
1819   [(call (match_operand:QI 0 "memory_operand" "m")
1820          (match_operand:SI 1 "const_int_operand" "n"))
1821    (set (reg:SI 14) (plus:SI (reg:SI 14)
1822                              (match_operand:SI 2 "immediate_operand" "i")))]
1823   ""
1824 {
1825   operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
1826   return "calls %1,%0";
1827 })
1828
1829 (define_expand "call_value_pop"
1830   [(parallel [(set (match_operand 0 "" "")
1831                    (call (match_operand:QI 1 "memory_operand" "")
1832                          (match_operand:SI 2 "const_int_operand" "")))
1833               (set (reg:SI 14)
1834                    (plus:SI (reg:SI 14)
1835                             (match_operand:SI 4 "immediate_operand" "")))])]
1836   ""
1837 {
1838   if (INTVAL (operands[4]) > 255 * 4 || INTVAL (operands[4]) % 4)
1839     abort ();
1840
1841   /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1842      during EH unwinding.  We must include the argument count pushed by
1843      the calls instruction.  */
1844   operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
1845 })
1846
1847 (define_insn "*call_value_pop"
1848   [(set (match_operand 0 "" "")
1849         (call (match_operand:QI 1 "memory_operand" "m")
1850               (match_operand:SI 2 "const_int_operand" "n")))
1851    (set (reg:SI 14) (plus:SI (reg:SI 14)
1852                              (match_operand:SI 3 "immediate_operand" "i")))]
1853   ""
1854   "*
1855 {
1856   operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
1857   return \"calls %2,%1\";
1858 }")
1859
1860 (define_expand "call"
1861   [(call (match_operand:QI 0 "memory_operand" "")
1862       (match_operand:SI 1 "const_int_operand" ""))]
1863   ""
1864   "
1865 {
1866   /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
1867      during EH unwinding.  We must include the argument count pushed by
1868      the calls instruction.  */
1869   operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
1870 }")
1871
1872 (define_insn "*call"
1873    [(call (match_operand:QI 0 "memory_operand" "m")
1874        (match_operand:SI 1 "const_int_operand" ""))]
1875   ""
1876   "calls $0,%0")
1877
1878 (define_expand "call_value"
1879   [(set (match_operand 0 "" "")
1880       (call (match_operand:QI 1 "memory_operand" "")
1881             (match_operand:SI 2 "const_int_operand" "")))]
1882   ""
1883   "
1884 {
1885   /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
1886      during EH unwinding.  We must include the argument count pushed by
1887      the calls instruction.  */
1888   operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
1889 }")
1890
1891 (define_insn "*call_value"
1892   [(set (match_operand 0 "" "")
1893         (call (match_operand:QI 1 "memory_operand" "m")
1894               (match_operand:SI 2 "const_int_operand" "")))]
1895   ""
1896   "calls $0,%1")
1897
1898 ;; Call subroutine returning any type.
1899
1900 (define_expand "untyped_call"
1901   [(parallel [(call (match_operand 0 "" "")
1902                   (const_int 0))
1903             (match_operand 1 "" "")
1904             (match_operand 2 "" "")])]
1905   ""
1906   "
1907 {
1908   int i;
1909
1910   emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
1911
1912   for (i = 0; i < XVECLEN (operands[2], 0); i++)
1913     {
1914       rtx set = XVECEXP (operands[2], 0, i);
1915       emit_move_insn (SET_DEST (set), SET_SRC (set));
1916     }
1917
1918   /* The optimizer does not know that the call sets the function value
1919      registers we stored in the result block.  We avoid problems by
1920      claiming that all hard registers are used and clobbered at this
1921      point.  */
1922   emit_insn (gen_blockage ());
1923
1924   DONE;
1925 }")
1926
1927 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
1928 ;; all of memory.  This blocks insns from being moved across this point.
1929
1930 (define_insn "blockage"
1931   [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
1932   ""
1933   "")
1934
1935 (define_insn "return"
1936   [(return)]
1937   ""
1938   "ret")
1939
1940 (define_expand "epilogue"
1941   [(return)]
1942   ""
1943   "
1944 {
1945   emit_jump_insn (gen_return ());
1946   DONE;
1947 }")
1948
1949 (define_insn "nop"
1950   [(const_int 0)]
1951   ""
1952   "nop")
1953
1954 ;; This had a wider constraint once, and it had trouble.
1955 ;; If you are tempted to try `g', please don't--it's not worth
1956 ;; the risk we will reopen the same bug.
1957 (define_insn "indirect_jump"
1958   [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1959   ""
1960   "jmp (%0)")
1961
1962 ;; This is here to accept 5 arguments (as passed by expand_end_case)
1963 ;; and pass the first 4 along to the casesi1 pattern that really does the work.
1964 (define_expand "casesi"
1965   [(match_operand:SI 0 "general_operand" "")    ; index
1966    (match_operand:SI 1 "general_operand" "")    ; lower
1967    (match_operand:SI 2 "general_operand" "")    ; upper-lower
1968    (match_operand 3 "" "")                      ; table label
1969    (match_operand 4 "" "")]                     ; default label
1970   ""
1971 {
1972   emit_jump_insn (gen_casesi1 (operands[0], operands[1],
1973                                operands[2], operands[3]));
1974   DONE;
1975 })
1976
1977 (define_insn "casesi1"
1978   [(set (pc)
1979         (if_then_else
1980          (leu (minus:SI (match_operand:SI 0 "general_operand" "g")
1981                         (match_operand:SI 1 "general_operand" "g"))
1982               (match_operand:SI 2 "general_operand" "g"))
1983          (plus:SI (sign_extend:SI
1984                    (mem:HI (plus:SI (mult:SI (minus:SI (match_dup 0)
1985                                                        (match_dup 1))
1986                                              (const_int 2))
1987                                     (pc))))
1988                   (label_ref:SI (match_operand 3 "" "")))
1989          (pc)))]
1990   ""
1991   "casel %0,%1,%2")
1992
1993 ;; This can arise by simplification when operand 1 is a constant int.
1994 (define_insn ""
1995   [(set (pc)
1996         (if_then_else
1997          (leu (plus:SI (match_operand:SI 0 "general_operand" "g")
1998                        (match_operand:SI 1 "const_int_operand" "n"))
1999               (match_operand:SI 2 "general_operand" "g"))
2000          (plus:SI (sign_extend:SI
2001                    (mem:HI (plus:SI (mult:SI (plus:SI (match_dup 0)
2002                                                       (match_dup 1))
2003                                              (const_int 2))
2004                                     (pc))))
2005                   (label_ref:SI (match_operand 3 "" "")))
2006          (pc)))]
2007   ""
2008   "*
2009 {
2010   operands[1] = GEN_INT (-INTVAL (operands[1]));
2011   return \"casel %0,%1,%2\";
2012 }")
2013
2014 ;; This can arise by simplification when the base for the case insn is zero.
2015 (define_insn ""
2016   [(set (pc)
2017         (if_then_else (leu (match_operand:SI 0 "general_operand" "g")
2018                            (match_operand:SI 1 "general_operand" "g"))
2019                       (plus:SI (sign_extend:SI
2020                                 (mem:HI (plus:SI (mult:SI (match_dup 0)
2021                                                           (const_int 2))
2022                                         (pc))))
2023                                (label_ref:SI (match_operand 2 "" "")))
2024                       (pc)))]
2025   ""
2026   "casel %0,$0,%1")
2027 \f
2028 ;;- load or push effective address
2029 ;; These come after the move and add/sub patterns
2030 ;; because we don't want pushl $1 turned into pushad 1.
2031 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
2032
2033 ;; It does not work to use constraints to distinguish pushes from moves,
2034 ;; because < matches any autodecrement, not just a push.
2035
2036 (define_insn ""
2037   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2038         (match_operand:QI 1 "address_operand" "p"))]
2039   ""
2040   "*
2041 {
2042   if (push_operand (operands[0], SImode))
2043     return \"pushab %a1\";
2044   else
2045     return \"movab %a1,%0\";
2046 }")
2047
2048 (define_insn ""
2049   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2050         (match_operand:HI 1 "address_operand" "p"))]
2051   ""
2052   "*
2053 {
2054   if (push_operand (operands[0], SImode))
2055     return \"pushaw %a1\";
2056   else
2057     return \"movaw %a1,%0\";
2058 }")
2059
2060 (define_insn ""
2061   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2062         (match_operand:SI 1 "address_operand" "p"))]
2063   ""
2064   "*
2065 {
2066   if (push_operand (operands[0], SImode))
2067     return \"pushal %a1\";
2068   else
2069     return \"moval %a1,%0\";
2070 }")
2071
2072 (define_insn ""
2073   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2074         (match_operand:DI 1 "address_operand" "p"))]
2075   ""
2076   "*
2077 {
2078   if (push_operand (operands[0], SImode))
2079     return \"pushaq %a1\";
2080   else
2081     return \"movaq %a1,%0\";
2082 }")
2083
2084 (define_insn ""
2085   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2086         (match_operand:SF 1 "address_operand" "p"))]
2087   ""
2088   "*
2089 {
2090   if (push_operand (operands[0], SImode))
2091     return \"pushaf %a1\";
2092   else
2093     return \"movaf %a1,%0\";
2094 }")
2095
2096 (define_insn ""
2097   [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2098         (match_operand:DF 1 "address_operand" "p"))]
2099   ""
2100   "*
2101 {
2102   if (push_operand (operands[0], SImode))
2103     return \"pushad %a1\";
2104   else
2105     return \"movad %a1,%0\";
2106 }")
2107 \f
2108 ;; These used to be peepholes, but it is more straightforward to do them
2109 ;; as single insns.  However, we must force the output to be a register
2110 ;; if it is not an offsettable address so that we know that we can assign
2111 ;; to it twice.
2112
2113 ;; If we had a good way of evaluating the relative costs, these could be
2114 ;; machine-independent.
2115
2116 ;; Optimize   extzv ...,z;    andl2 ...,z
2117 ;; or         ashl ...,z;     andl2 ...,z
2118 ;; with other operands constant.  This is what the combiner converts the
2119 ;; above sequences to before attempting to recognize the new insn.
2120
2121 (define_insn ""
2122   [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2123         (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
2124                              (match_operand:QI 2 "const_int_operand" "n"))
2125                 (match_operand:SI 3 "const_int_operand" "n")))]
2126   "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
2127   "*
2128 {
2129   unsigned long mask1 = INTVAL (operands[3]);
2130   unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
2131
2132   if ((mask1 & mask2) != mask1)
2133     operands[3] = GEN_INT (mask1 & mask2);
2134
2135   return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
2136 }")
2137
2138 ;; left-shift and mask
2139 ;; The only case where `ashl' is better is if the mask only turns off
2140 ;; bits that the ashl would anyways, in which case it should have been
2141 ;; optimized away.
2142
2143 (define_insn ""
2144   [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
2145         (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "g")
2146                            (match_operand:QI 2 "const_int_operand" "n"))
2147                 (match_operand:SI 3 "const_int_operand" "n")))]
2148   ""
2149   "*
2150 {
2151   operands[3]
2152     = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
2153   return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
2154 }")
2155
2156 ;; Instruction sequence to sync the VAX instruction stream.
2157 (define_insn "sync_istream"
2158   [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
2159   ""
2160   "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")