1 ;; Machine description for GNU compiler, VAX Version
2 ;; Copyright (C) 1987-2021 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
21 ;;- Instruction patterns. When multiple patterns apply,
22 ;;- the first one in the file is chosen.
24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et al.
26 ;; UNSPEC_VOLATILE usage:
28 (define_c_enum "unspecv" [
29 VUNSPEC_BLOCKAGE ; 'blockage' insn to prevent scheduling across an
31 VUNSPEC_SYNC_ISTREAM ; sequence of insns to sync the I-stream
32 VUNSPEC_PEM ; 'procedure_entry_mask' insn.
36 [(VAX_AP_REGNUM 12) ; Register 12 contains the argument pointer
37 (VAX_FP_REGNUM 13) ; Register 13 contains the frame pointer
38 (VAX_SP_REGNUM 14) ; Register 14 contains the stack pointer
39 (VAX_PC_REGNUM 15) ; Register 15 contains the program counter
40 (VAX_PSL_REGNUM 16) ; Register 16 contains the processor status
41 ; and condition codes in particular
45 ;; Integer modes supported on VAX, with a mapping from machine mode
46 ;; to mnemonic suffix. DImode is always a special case.
47 (define_mode_iterator VAXint [QI HI SI])
48 (define_mode_iterator VAXintQH [QI HI])
49 (define_mode_iterator VAXintQHSD [QI HI SI DI])
50 (define_mode_attr isfx [(QI "b") (HI "w") (SI "l") (DI "q")])
52 ;; Similar for float modes supported on VAX.
53 (define_mode_iterator VAXfp [SF DF])
54 (define_mode_attr fsfx [(SF "f") (DF "%#")])
56 ;; Some output patterns want integer immediates with a prefix...
57 (define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")])
59 (define_mode_iterator VAXcc [CC CCN CCNZ CCZ])
60 (define_mode_iterator VAXccnz [CCN CCNZ CCZ])
61 (define_mode_attr cc [(CC "cc") (CCN "ccn") (CCNZ "ccnz") (CCZ "ccz")])
63 (define_code_iterator any_extract [sign_extract zero_extract])
66 (include "constraints.md")
67 (include "predicates.md")
69 ;; Make instructions that set the N, N+Z, and Z condition codes respectively.
70 (define_subst "subst_<cc>"
71 [(set (match_operand 0 "")
73 (clobber (reg:CC VAX_PSL_REGNUM))]
75 [(set (reg:VAXccnz VAX_PSL_REGNUM)
76 (compare:VAXccnz (match_dup 1)
81 (define_subst "subst_f<cc>"
82 [(set (match_operand:VAXfp 0 "")
83 (match_operand:VAXfp 1 ""))
84 (clobber (reg:CC VAX_PSL_REGNUM))]
86 [(set (reg:VAXccnz VAX_PSL_REGNUM)
87 (compare:VAXccnz (match_dup 1)
88 (const_double_zero:VAXfp)))
92 ;; Select all from the attributes below that apply to a given insn that
93 ;; has a clobber on CC for the comparison elimination pass to use it in
94 ;; place of a subsequent comparison instruction matching the mode used
95 ;; by a comparison operator in branch.
97 ;; For example a branch doing `eq' in SImode will use `*cmpsi_ccz', so
98 ;; to eliminate it a `*movsi_ccz', etc. pattern will be required via the
99 ;; `ccz' substitution. Analogously for the other CC modes.
101 ;; The general `cc' mode, which sets all of the C, N, V and Z condition
102 ;; codes, has to be handled specially as it makes no sense for the usual
103 ;; comparison against zero, so no substitution has been defined for it.
104 (define_subst_attr "ccn" "subst_ccn" "" "_ccn")
105 (define_subst_attr "ccnz" "subst_ccnz" "" "_ccnz")
106 (define_subst_attr "ccz" "subst_ccz" "" "_ccz")
107 (define_subst_attr "fccn" "subst_fccn" "" "_ccn")
108 (define_subst_attr "fccnz" "subst_fccnz" "" "_ccnz")
109 (define_subst_attr "fccz" "subst_fccz" "" "_ccz")
111 (define_insn "*cmp<VAXint:mode>_<VAXcc:mode>"
112 [(set (reg:VAXcc VAX_PSL_REGNUM)
113 (compare:VAXcc (match_operand:VAXint 0 "general_operand" "nrmT,nrmT")
114 (match_operand:VAXint 1 "general_operand" "I,nrmT")))]
118 cmp<VAXint:isfx> %0,%1")
120 ;; We don't have a CMPQ instruction, but we can set the N and Z condition
121 ;; codes with MOVQ, and also this comparison can be folded into a preceding
122 ;; operation by the post-reload comparison elimination pass.
123 (define_insn "*cmpdi_<VAXccnz:mode>"
124 [(set (reg:VAXccnz VAX_PSL_REGNUM)
125 (compare:VAXccnz (match_operand:DI 0 "general_operand" "r,nmT")
126 (match_operand:DI 1 "const_zero_operand" "I,I")))
127 (clobber (match_scratch:DI 2 "=X,r"))]
133 (define_insn "*cmp<VAXfp:mode>_<VAXccnz:mode>"
134 [(set (reg:VAXccnz VAX_PSL_REGNUM)
135 (compare:VAXccnz (match_operand:VAXfp 0 "general_operand" "gF,gF")
136 (match_operand:VAXfp 1 "general_operand" "G,gF")))]
140 cmp<VAXfp:fsfx> %0,%1")
142 (define_insn "*bit<VAXint:mode>_<VAXccnz:mode>"
143 [(set (reg:VAXccnz VAX_PSL_REGNUM)
145 (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT")
146 (match_operand:VAXint 1 "general_operand" "nrmT"))
149 "bit<VAXint:isfx> %0,%1")
151 ;; The VAX has no sCOND insns. It does have add/subtract with carry
152 ;; which could be used to implement the sltu and sgeu patterns. However,
153 ;; to do this properly requires a complete rewrite of the compare insns
154 ;; to keep them together with the sltu/sgeu insns until after the
155 ;; reload pass is complete. The previous implementation didn't do this
156 ;; and has been deleted.
159 (define_insn_and_split "mov<mode>"
160 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
161 (match_operand:VAXfp 1 "general_operand" "G,gF"))]
168 (clobber (reg:CC VAX_PSL_REGNUM))])]
171 (define_insn "*mov<mode><fccn><fccnz><fccz>"
172 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
173 (match_operand:VAXfp 1 "general_operand" "G,gF"))
174 (clobber (reg:CC VAX_PSL_REGNUM))]
178 mov<VAXfp:fsfx> %1,%0")
180 ;; Some VAXen don't support this instruction.
181 ;;(define_insn_and_split "movti"
182 ;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g")
183 ;; (match_operand:TI 1 "general_operand" "g"))]
186 ;; "reload_completed"
188 ;; [(set (match_dup 0)
190 ;; (clobber (reg:CC VAX_PSL_REGNUM))])]
193 ;;(define_insn "*movti<ccn><ccnz><ccz>"
194 ;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g")
195 ;; (match_operand:TI 1 "general_operand" "g"))
196 ;; (clobber (reg:CC VAX_PSL_REGNUM))]
197 ;; "reload_completed"
200 (define_insn_and_split "movdi"
201 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
202 (match_operand:DI 1 "general_operand" "g"))]
209 (clobber (reg:CC VAX_PSL_REGNUM))])]
212 ;; In some cases `vax_output_int_move' splits a `DImode' move into a pair
213 ;; of `SImode' moves, in which case the flags aren't usefully set. Have
214 ;; separate patterns then, for the cases where the move may and may not be
215 ;; split each. We use the outer condition only so in some cases we will
216 ;; fail to notice the move does not actually get split, but this is OK.
217 (define_insn "*movdi_maybe_split"
218 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
219 (match_operand:DI 1 "general_operand" "g"))
220 (clobber (reg:CC VAX_PSL_REGNUM))]
221 "reload_completed && vax_maybe_split_dimode_move (operands)"
222 "* return vax_output_int_move (insn, operands, DImode);")
224 (define_insn "*movdi_unsplit<ccn><ccnz><ccz>"
225 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
226 (match_operand:DI 1 "general_operand" "g"))
227 (clobber (reg:CC VAX_PSL_REGNUM))]
228 "reload_completed && !vax_maybe_split_dimode_move (operands)"
229 "* return vax_output_int_move (insn, operands, DImode);")
231 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX
232 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl
233 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles
234 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword
235 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster
236 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt
237 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description
238 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl
241 ;; Cycle counts for other models may vary (on a VAX 750 they are similar,
242 ;; but on a VAX 9000 most move and add instructions with one constant
243 ;; operand take 1 cycle).
245 ;; Loads of constants between 64 and 128 used to be done with
246 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space.
248 (define_expand "movsi"
249 [(set (match_operand:SI 0 "nonimmediate_operand" "")
250 (match_operand:SI 1 "general_operand" ""))]
254 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS
256 && GET_CODE (operands[1]) == CONST
257 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
258 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
260 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
261 rtx const_int = XEXP (XEXP (operands[1], 0), 1);
262 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
263 emit_move_insn (temp, symbol_ref);
264 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int));
270 (define_insn_and_split "movsi_2"
271 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
272 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))]
279 (clobber (reg:CC VAX_PSL_REGNUM))])]
282 (define_insn "*movsi_2<ccn><ccnz><ccz>"
283 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
284 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))
285 (clobber (reg:CC VAX_PSL_REGNUM))]
287 "* return vax_output_int_move (insn, operands, SImode);")
289 (define_insn_and_split "mov<mode>"
290 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
291 (match_operand:VAXintQH 1 "general_operand" "g"))]
298 (clobber (reg:CC VAX_PSL_REGNUM))])]
301 (define_insn "*mov<mode><ccn><ccnz><ccz>"
302 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g")
303 (match_operand:VAXintQH 1 "general_operand" "g"))
304 (clobber (reg:CC VAX_PSL_REGNUM))]
306 "* return vax_output_int_move (insn, operands, <MODE>mode);")
308 (define_insn_and_split "movstricthi"
309 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
310 (match_operand:HI 1 "general_operand" "g"))]
315 [(set (strict_low_part (match_dup 0))
317 (clobber (reg:CC VAX_PSL_REGNUM))])]
320 (define_insn "*movstricthi<ccn><ccnz><ccz>"
321 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
322 (match_operand:HI 1 "general_operand" "g"))
323 (clobber (reg:CC VAX_PSL_REGNUM))]
327 if (CONST_INT_P (operands[1]))
329 int i = INTVAL (operands[1]);
332 else if ((unsigned int)i < 64)
333 return \"movw %1,%0\";
334 else if ((unsigned int)~i < 64)
335 return \"mcomw %H1,%0\";
336 else if ((unsigned int)i < 256)
337 return \"movzbw %1,%0\";
339 return \"movw %1,%0\";
342 (define_insn_and_split "movstrictqi"
343 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
344 (match_operand:QI 1 "general_operand" "g"))]
349 [(set (strict_low_part (match_dup 0))
351 (clobber (reg:CC VAX_PSL_REGNUM))])]
354 (define_insn "*movstrictqi<ccn><ccnz><ccz>"
355 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
356 (match_operand:QI 1 "general_operand" "g"))
357 (clobber (reg:CC VAX_PSL_REGNUM))]
361 if (CONST_INT_P (operands[1]))
363 int i = INTVAL (operands[1]);
366 else if ((unsigned int)~i < 64)
367 return \"mcomb %B1,%0\";
369 return \"movb %1,%0\";
372 ;; This is here to accept 4 arguments and pass the first 3 along
373 ;; to the movmemhi1 pattern that really does the work.
374 (define_expand "cpymemhi"
375 [(set (match_operand:BLK 0 "memory_operand" "")
376 (match_operand:BLK 1 "memory_operand" ""))
377 (use (match_operand:HI 2 "general_operand" ""))
378 (match_operand 3 "" "")]
382 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
386 (define_expand "movmemhi"
387 [(set (match_operand:BLK 0 "memory_operand" "")
388 (match_operand:BLK 1 "memory_operand" ""))
389 (use (match_operand:HI 2 "general_operand" ""))
390 (match_operand 3 "" "")]
394 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2]));
398 ;; The definition of this insn does not really explain what it does,
399 ;; but it should suffice
400 ;; that anything generated as this insn will be recognized as one
401 ;; and that it won't successfully combine with anything.
403 (define_insn_and_split "movmemhi1"
404 [(set (match_operand:BLK 0 "memory_operand" "=o")
405 (match_operand:BLK 1 "memory_operand" "o"))
406 (use (match_operand:HI 2 "general_operand" "g"))
412 (clobber (reg:SI 5))]
426 (clobber (reg:CC VAX_PSL_REGNUM))])]
429 (define_insn "*movmemhi1"
430 [(set (match_operand:BLK 0 "memory_operand" "=o")
431 (match_operand:BLK 1 "memory_operand" "o"))
432 (use (match_operand:HI 2 "general_operand" "g"))
439 (clobber (reg:CC VAX_PSL_REGNUM))]
443 ;; Extension and truncation insns.
445 (define_insn_and_split "truncsiqi2"
446 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
447 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
453 (truncate:QI (match_dup 1)))
454 (clobber (reg:CC VAX_PSL_REGNUM))])]
457 (define_insn "*truncsiqi2<ccn><ccnz><ccz>"
458 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
459 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))
460 (clobber (reg:CC VAX_PSL_REGNUM))]
464 (define_insn_and_split "truncsihi2"
465 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
466 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))]
472 (truncate:HI (match_dup 1)))
473 (clobber (reg:CC VAX_PSL_REGNUM))])]
476 (define_insn "*truncsihi2<ccn><ccnz><ccz>"
477 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
478 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))
479 (clobber (reg:CC VAX_PSL_REGNUM))]
483 (define_insn_and_split "trunchiqi2"
484 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
485 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
491 (truncate:QI (match_dup 1)))
492 (clobber (reg:CC VAX_PSL_REGNUM))])]
495 (define_insn "*trunchiqi2<ccn><ccnz><ccz>"
496 [(set (match_operand:QI 0 "nonimmediate_operand" "=g")
497 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))
498 (clobber (reg:CC VAX_PSL_REGNUM))]
502 (define_insn_and_split "extendhisi2"
503 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
504 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
510 (sign_extend:SI (match_dup 1)))
511 (clobber (reg:CC VAX_PSL_REGNUM))])]
514 (define_insn "*extendhisi2<ccn><ccnz><ccz>"
515 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
516 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))
517 (clobber (reg:CC VAX_PSL_REGNUM))]
521 (define_insn_and_split "extendqihi2"
522 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
523 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
529 (sign_extend:HI (match_dup 1)))
530 (clobber (reg:CC VAX_PSL_REGNUM))])]
533 (define_insn "*extendqihi2<ccn><ccnz><ccz>"
534 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
535 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))
536 (clobber (reg:CC VAX_PSL_REGNUM))]
540 (define_insn_and_split "extendqisi2"
541 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
542 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
548 (sign_extend:SI (match_dup 1)))
549 (clobber (reg:CC VAX_PSL_REGNUM))])]
552 (define_insn "*extendqisi2<ccn><ccnz><ccz>"
553 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
554 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
555 (clobber (reg:CC VAX_PSL_REGNUM))]
559 (define_insn_and_split "extendsfdf2"
560 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
561 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))]
567 (float_extend:DF (match_dup 1)))
568 (clobber (reg:CC VAX_PSL_REGNUM))])]
571 (define_insn "*extendsfdf2<fccn><fccnz><fccz>"
572 [(set (match_operand:DF 0 "nonimmediate_operand" "=g")
573 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))
574 (clobber (reg:CC VAX_PSL_REGNUM))]
578 (define_insn_and_split "truncdfsf2"
579 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
580 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))]
586 (float_truncate:SF (match_dup 1)))
587 (clobber (reg:CC VAX_PSL_REGNUM))])]
590 (define_insn "*truncdfsf2<fccn><fccnz><fccz>"
591 [(set (match_operand:SF 0 "nonimmediate_operand" "=g")
592 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))
593 (clobber (reg:CC VAX_PSL_REGNUM))]
597 (define_insn_and_split "zero_extendhisi2"
598 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
599 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
605 (zero_extend:SI (match_dup 1)))
606 (clobber (reg:CC VAX_PSL_REGNUM))])]
609 (define_insn "*zero_extendhisi2<ccn><ccnz><ccz>"
610 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
611 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))
612 (clobber (reg:CC VAX_PSL_REGNUM))]
616 (define_insn_and_split "zero_extendqihi2"
617 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
618 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
624 (zero_extend:HI (match_dup 1)))
625 (clobber (reg:CC VAX_PSL_REGNUM))])]
628 (define_insn "*zero_extendqihi2<ccn><ccnz><ccz>"
629 [(set (match_operand:HI 0 "nonimmediate_operand" "=g")
630 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))
631 (clobber (reg:CC VAX_PSL_REGNUM))]
635 (define_insn_and_split "zero_extendqisi2"
636 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
637 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
643 (zero_extend:SI (match_dup 1)))
644 (clobber (reg:CC VAX_PSL_REGNUM))])]
647 (define_insn "*zero_extendqisi2<ccn><ccnz><ccz>"
648 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
649 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))
650 (clobber (reg:CC VAX_PSL_REGNUM))]
654 ;; Fix-to-float conversion insns.
656 (define_insn_and_split "float<VAXint:mode><VAXfp:mode>2"
657 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
658 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))]
664 (float:VAXfp (match_dup 1)))
665 (clobber (reg:CC VAX_PSL_REGNUM))])]
668 (define_insn "*float<VAXint:mode><VAXfp:mode>2<fccn><fccnz><fccz>"
669 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
670 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))
671 (clobber (reg:CC VAX_PSL_REGNUM))]
673 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0")
675 ;; Float-to-fix conversion insns.
677 (define_insn_and_split "fix_trunc<VAXfp:mode><VAXint:mode>2"
678 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
679 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))]
685 (fix:VAXint (match_dup 1)))
686 (clobber (reg:CC VAX_PSL_REGNUM))])]
689 (define_insn "*fix_trunc<VAXfp:mode><VAXint:mode>2<ccn><ccnz><ccz>"
690 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
691 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))
692 (clobber (reg:CC VAX_PSL_REGNUM))]
694 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0")
696 (define_expand "fixuns_trunc<VAXfp:mode><VAXint:mode>2"
697 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
698 (fix:VAXint (match_operand:VAXfp 1 "general_operand")))]
701 ;;- All kinds of add instructions.
703 (define_insn_and_split "add<mode>3"
704 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
705 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
706 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
712 (plus:VAXfp (match_dup 1)
714 (clobber (reg:CC VAX_PSL_REGNUM))])]
717 (define_insn "*add<mode>3<fccn><fccnz><fccz>"
718 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
719 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
720 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))
721 (clobber (reg:CC VAX_PSL_REGNUM))]
724 add<VAXfp:fsfx>2 %2,%0
725 add<VAXfp:fsfx>2 %1,%0
726 add<VAXfp:fsfx>3 %1,%2,%0")
728 (define_insn_and_split "add<mode>3"
729 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
730 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
731 (match_operand:VAXint 2 "general_operand" "nrmT")))]
737 (plus:VAXint (match_dup 1)
739 (clobber (reg:CC VAX_PSL_REGNUM))])]
742 (define_insn "*add<mode>3<ccn><ccnz><ccz>"
743 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
744 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")
745 (match_operand:VAXint 2 "general_operand" "nrmT")))
746 (clobber (reg:CC VAX_PSL_REGNUM))]
748 "* return vax_output_int_add (insn, operands, <MODE>mode);")
750 (define_expand "adddi3"
751 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
752 (plus:DI (match_operand:DI 1 "general_operand" "g")
753 (match_operand:DI 2 "general_operand" "g")))]
754 "!reload_in_progress"
755 "vax_expand_addsub_di_operands (operands, PLUS); DONE;")
757 (define_insn_and_split "adcdi3"
758 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
759 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
760 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))]
763 "&& reload_completed"
766 (plus:DI (match_dup 1)
768 (clobber (reg:CC VAX_PSL_REGNUM))])]
771 (define_insn "*adcdi3<ccn>"
772 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr")
773 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0")
774 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))
775 (clobber (reg:CC VAX_PSL_REGNUM))]
776 "TARGET_QMATH && reload_completed"
777 "* return vax_output_int_add (insn, operands, DImode);")
779 ;; The add-with-carry (adwc) instruction only accepts two operands.
780 (define_insn_and_split "adddi3_old"
781 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
782 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
783 (match_operand:DI 2 "general_operand" "Fsro,Fs")))]
786 "&& reload_completed"
789 (plus:DI (match_dup 1)
791 (clobber (reg:CC VAX_PSL_REGNUM))])]
794 (define_insn "*adddi3_old<ccn>"
795 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>")
796 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>")
797 (match_operand:DI 2 "general_operand" "Fsro,Fs")))
798 (clobber (reg:CC VAX_PSL_REGNUM))]
799 "!TARGET_QMATH && reload_completed"
800 "* return vax_output_int_add (insn, operands, DImode);")
802 ;;- All kinds of subtract instructions.
804 (define_insn_and_split "sub<mode>3"
805 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
806 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
807 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
813 (minus:VAXfp (match_dup 1)
815 (clobber (reg:CC VAX_PSL_REGNUM))])]
818 (define_insn "*sub<mode>3<fccn><fccnz><fccz>"
819 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
820 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
821 (match_operand:VAXfp 2 "general_operand" "gF,gF")))
822 (clobber (reg:CC VAX_PSL_REGNUM))]
825 sub<VAXfp:fsfx>2 %2,%0
826 sub<VAXfp:fsfx>3 %2,%1,%0")
828 (define_insn_and_split "sub<mode>3"
829 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
830 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
831 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
837 (minus:VAXint (match_dup 1)
839 (clobber (reg:CC VAX_PSL_REGNUM))])]
842 (define_insn "*sub<mode>3<ccn><ccnz><ccz>"
843 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
844 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
845 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))
846 (clobber (reg:CC VAX_PSL_REGNUM))]
849 sub<VAXint:isfx>2 %2,%0
850 sub<VAXint:isfx>3 %2,%1,%0")
852 (define_insn "*sub<mode>3_cc"
853 [(set (reg:CC VAX_PSL_REGNUM)
854 (compare:CC (match_operand:VAXint 1 "general_operand" "0,nrmT")
855 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))
856 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
857 (minus:VAXint (match_dup 1)
861 sub<VAXint:isfx>2 %2,%0
862 sub<VAXint:isfx>3 %2,%1,%0")
864 (define_expand "subdi3"
865 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
866 (minus:DI (match_operand:DI 1 "general_operand" "g")
867 (match_operand:DI 2 "general_operand" "g")))]
868 "!reload_in_progress"
869 "vax_expand_addsub_di_operands (operands, MINUS); DONE;")
871 (define_insn_and_split "sbcdi3"
872 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr")
873 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
874 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))]
877 "&& reload_completed"
880 (minus:DI (match_dup 1)
882 (clobber (reg:CC VAX_PSL_REGNUM))])]
885 (define_insn "*sbcdi3<ccn>"
886 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,Rr")
887 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I")
888 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))
889 (clobber (reg:CC VAX_PSL_REGNUM))]
890 "TARGET_QMATH && reload_completed"
891 "* return vax_output_int_subtract (insn, operands, DImode);")
893 ;; The subtract-with-carry (sbwc) instruction only takes two operands.
894 (define_insn_and_split "subdi3_old"
895 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
896 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
897 (match_operand:DI 2 "general_operand" "Fsor,Fs")))]
900 "&& reload_completed"
903 (minus:DI (match_dup 1)
905 (clobber (reg:CC VAX_PSL_REGNUM))])]
908 (define_insn "*subdi3_old<ccn>"
909 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>")
910 (minus:DI (match_operand:DI 1 "general_operand" "0,or>")
911 (match_operand:DI 2 "general_operand" "Fsor,Fs")))
912 (clobber (reg:CC VAX_PSL_REGNUM))]
913 "!TARGET_QMATH && reload_completed"
914 "* return vax_output_int_subtract (insn, operands, DImode);")
916 ;;- Multiply instructions.
918 (define_insn_and_split "mul<mode>3"
919 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
920 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
921 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))]
927 (mult:VAXfp (match_dup 1)
929 (clobber (reg:CC VAX_PSL_REGNUM))])]
932 (define_insn "*mul<mode>3<fccn><fccnz><fccz>"
933 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g")
934 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF")
935 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))
936 (clobber (reg:CC VAX_PSL_REGNUM))]
939 mul<VAXfp:fsfx>2 %2,%0
940 mul<VAXfp:fsfx>2 %1,%0
941 mul<VAXfp:fsfx>3 %1,%2,%0")
943 (define_insn_and_split "mul<mode>3"
944 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
945 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
946 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
952 (mult:VAXint (match_dup 1)
954 (clobber (reg:CC VAX_PSL_REGNUM))])]
957 (define_insn "*mul<mode>3<ccn><ccnz><ccz>"
958 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
959 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
960 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))
961 (clobber (reg:CC VAX_PSL_REGNUM))]
964 mul<VAXint:isfx>2 %2,%0
965 mul<VAXint:isfx>2 %1,%0
966 mul<VAXint:isfx>3 %1,%2,%0")
968 (define_insn_and_split "mulsidi3"
969 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
971 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
972 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))))]
979 (sign_extend:DI (match_dup 1))
980 (sign_extend:DI (match_dup 2))))
981 (clobber (reg:CC VAX_PSL_REGNUM))])]
984 (define_insn "*mulsidi3<ccn><ccnz><ccz>"
985 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
987 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
988 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))))
989 (clobber (reg:CC VAX_PSL_REGNUM))]
993 (define_insn_and_split "*maddsidi4"
994 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
997 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
998 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
999 (sign_extend:DI (match_operand:SI 3 "general_operand" "g"))))]
1007 (sign_extend:DI (match_dup 1))
1008 (sign_extend:DI (match_dup 2)))
1009 (sign_extend:DI (match_dup 3))))
1010 (clobber (reg:CC VAX_PSL_REGNUM))])]
1013 (define_insn "*maddsidi4_2<ccn><ccnz><ccz>"
1014 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1017 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1018 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1019 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))
1020 (clobber (reg:CC VAX_PSL_REGNUM))]
1024 ;; 'F' constraint means type CONST_DOUBLE
1025 (define_insn_and_split "*maddsidi4_const"
1026 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1029 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1030 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1031 (match_operand:DI 3 "immediate_operand" "F")))]
1032 "GET_CODE (operands[3]) == CONST_DOUBLE
1033 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
1035 "&& reload_completed"
1040 (sign_extend:DI (match_dup 1))
1041 (sign_extend:DI (match_dup 2)))
1043 (clobber (reg:CC VAX_PSL_REGNUM))])]
1046 (define_insn "*maddsidi4_const_2<ccn><ccnz><ccz>"
1047 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1050 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT"))
1051 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))
1052 (match_operand:DI 3 "immediate_operand" "F")))
1053 (clobber (reg:CC VAX_PSL_REGNUM))]
1054 "GET_CODE (operands[3]) == CONST_DOUBLE
1055 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)
1056 && reload_completed"
1059 if (CONST_DOUBLE_HIGH (operands[3]))
1060 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3]));
1061 return \"emul %1,%2,%3,%0\";
1064 ;;- Divide instructions.
1066 (define_insn_and_split "div<mode>3"
1067 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
1068 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
1069 (match_operand:VAXfp 2 "general_operand" "gF,gF")))]
1075 (div:VAXfp (match_dup 1)
1077 (clobber (reg:CC VAX_PSL_REGNUM))])]
1080 (define_insn "*div<mode>3<fccn><fccnz><fccz>"
1081 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g")
1082 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF")
1083 (match_operand:VAXfp 2 "general_operand" "gF,gF")))
1084 (clobber (reg:CC VAX_PSL_REGNUM))]
1087 div<VAXfp:fsfx>2 %2,%0
1088 div<VAXfp:fsfx>3 %2,%1,%0")
1090 (define_insn_and_split "div<mode>3"
1091 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1092 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1093 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))]
1099 (div:VAXint (match_dup 1)
1101 (clobber (reg:CC VAX_PSL_REGNUM))])]
1104 (define_insn "*div<mode>3<ccn><ccnz><ccz>"
1105 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1106 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1107 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))
1108 (clobber (reg:CC VAX_PSL_REGNUM))]
1111 div<VAXint:isfx>2 %2,%0
1112 div<VAXint:isfx>3 %2,%1,%0")
1114 ;; This is left out because it is very slow;
1115 ;; we are better off programming around the "lack" of this insn.
1116 ;;(define_insn_and_split "divmoddisi4"
1117 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1118 ;; (div:SI (match_operand:DI 1 "general_operand" "g")
1119 ;; (match_operand:SI 2 "general_operand" "g")))
1120 ;; (set (match_operand:SI 3 "nonimmediate_operand" "=g")
1121 ;; (mod:SI (match_dup 1)
1125 ;; "reload_completed"
1127 ;; [(set (match_dup 0)
1128 ;; (div:SI (match_dup 1)
1130 ;; (set (match_dup 3)
1131 ;; (mod:SI (match_dup 1)
1133 ;; (clobber (reg:CC VAX_PSL_REGNUM))])]
1136 ;;(define_insn "*divmoddisi4<ccn><ccnz><ccz>"
1137 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1138 ;; (div:SI (match_operand:DI 1 "general_operand" "g")
1139 ;; (match_operand:SI 2 "general_operand" "g")))
1140 ;; (set (match_operand:SI 3 "nonimmediate_operand" "=g")
1141 ;; (mod:SI (match_dup 1)
1143 ;; (clobber (reg:CC VAX_PSL_REGNUM))]
1144 ;; "reload_completed"
1145 ;; "ediv %2,%1,%0,%3")
1147 ;; Bit-and on the VAX is done with a clear-bits insn.
1148 (define_expand "and<mode>3"
1149 [(set (match_operand:VAXint 0 "nonimmediate_operand" "")
1150 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" ""))
1151 (match_operand:VAXint 2 "general_operand" "")))]
1155 rtx op1 = operands[1];
1157 /* If there is a constant argument, complement that one. */
1158 if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1))
1160 operands[1] = operands[2];
1165 if (CONST_INT_P (op1))
1166 operands[1] = GEN_INT (~INTVAL (op1));
1168 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1);
1171 (define_insn_and_split "*and<mode>3"
1172 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1173 (and:VAXint (not:VAXint
1174 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
1175 (match_operand:VAXint 2 "general_operand" "0,nrmT")))]
1181 (and:VAXint (not:VAXint
1184 (clobber (reg:CC VAX_PSL_REGNUM))])]
1187 (define_insn "*and<mode>3_2<ccn><ccnz><ccz>"
1188 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1189 (and:VAXint (not:VAXint
1190 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT"))
1191 (match_operand:VAXint 2 "general_operand" "0,nrmT")))
1192 (clobber (reg:CC VAX_PSL_REGNUM))]
1195 bic<VAXint:isfx>2 %1,%0
1196 bic<VAXint:isfx>3 %1,%2,%0")
1198 ;; The following used to be needed because constant propagation can
1199 ;; create them starting from the bic insn patterns above. This is no
1200 ;; longer a problem. However, having these patterns allows optimization
1201 ;; opportunities in combine.c.
1203 (define_insn_and_split "*and<mode>3_const_int"
1204 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1205 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1206 (match_operand:VAXint 2 "const_int_operand" "n,n")))]
1212 (and:VAXint (match_dup 1)
1214 (clobber (reg:CC VAX_PSL_REGNUM))])]
1217 (define_insn "*and<mode>3_2_const_int<ccn><ccnz><ccz>"
1218 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1219 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT")
1220 (match_operand:VAXint 2 "const_int_operand" "n,n")))
1221 (clobber (reg:CC VAX_PSL_REGNUM))]
1224 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0
1225 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0")
1227 ;; We have no direct AND operation and consequently the RTL sequence
1228 ;; the "and<mode>3" pattern produces does not match the instruction
1229 ;; the "*bit<mode>" pattern does for the purpose of the compare
1230 ;; elimination pass. Try to get rid of the extra operation by hand
1231 ;; and where the sequence is used to set the condition codes only
1232 ;; convert MNEG/BIC => BIT.
1235 [(set (match_operand:VAXint 0 "register_operand")
1236 (not:VAXint (match_operand:VAXint 1 "general_operand")))
1237 (clobber (reg:CC VAX_PSL_REGNUM))])
1239 [(set (reg:VAXccnz VAX_PSL_REGNUM)
1241 (and:VAXint (not:VAXint (match_dup 0))
1242 (match_operand:VAXint 3 "general_operand"))
1244 (set (match_operand:VAXint 2 "register_operand")
1245 (and:VAXint (not:VAXint (match_dup 0))
1247 "peep2_reg_dead_p (2, operands[0]) && peep2_reg_dead_p (2, operands[2])"
1248 [(set (reg:VAXccnz VAX_PSL_REGNUM)
1250 (and:VAXint (match_dup 1)
1255 ;;- Bit set instructions.
1257 (define_insn_and_split "ior<mode>3"
1258 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1259 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1260 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
1266 (ior:VAXint (match_dup 1)
1268 (clobber (reg:CC VAX_PSL_REGNUM))])]
1271 (define_insn "*ior<mode>3<ccn><ccnz><ccz>"
1272 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1273 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1274 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))
1275 (clobber (reg:CC VAX_PSL_REGNUM))]
1278 bis<VAXint:isfx>2 %2,%0
1279 bis<VAXint:isfx>2 %1,%0
1280 bis<VAXint:isfx>3 %2,%1,%0")
1282 ;;- xor instructions.
1284 (define_insn_and_split "xor<mode>3"
1285 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1286 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1287 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))]
1293 (xor:VAXint (match_dup 1)
1295 (clobber (reg:CC VAX_PSL_REGNUM))])]
1298 (define_insn "*xor<mode>3<ccn><ccnz><ccz>"
1299 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g")
1300 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT")
1301 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))
1302 (clobber (reg:CC VAX_PSL_REGNUM))]
1305 xor<VAXint:isfx>2 %2,%0
1306 xor<VAXint:isfx>2 %1,%0
1307 xor<VAXint:isfx>3 %2,%1,%0")
1309 (define_insn_and_split "neg<mode>2"
1310 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
1311 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))]
1317 (neg:VAXfp (match_dup 1)))
1318 (clobber (reg:CC VAX_PSL_REGNUM))])]
1321 (define_insn "*neg<mode>2<fccn><fccnz><fccz>"
1322 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g")
1323 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))
1324 (clobber (reg:CC VAX_PSL_REGNUM))]
1326 "mneg<VAXfp:fsfx> %1,%0")
1328 (define_insn_and_split "neg<mode>2"
1329 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1330 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
1336 (neg:VAXint (match_dup 1)))
1337 (clobber (reg:CC VAX_PSL_REGNUM))])]
1340 (define_insn "*neg<mode>2<ccn><ccnz><ccz>"
1341 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1342 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))
1343 (clobber (reg:CC VAX_PSL_REGNUM))]
1345 "mneg<VAXint:isfx> %1,%0")
1347 (define_insn "*neg<mode>2_cc"
1348 [(set (reg:CC VAX_PSL_REGNUM)
1349 (compare:CC (const_int 0)
1351 (match_operand:VAXint 1 "general_operand" "0,nrmT"))))
1352 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g")
1353 (neg:VAXint (match_dup 1)))]
1355 "mneg<VAXint:isfx> %1,%0")
1357 (define_insn_and_split "one_cmpl<mode>2"
1358 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1359 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))]
1365 (not:VAXint (match_dup 1)))
1366 (clobber (reg:CC VAX_PSL_REGNUM))])]
1369 (define_insn "*one_cmpl<mode>2<ccn><ccnz><ccz>"
1370 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g")
1371 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))
1372 (clobber (reg:CC VAX_PSL_REGNUM))]
1374 "mcom<VAXint:isfx> %1,%0")
1376 ;; Arithmetic right shift on the VAX works by negating the shift count,
1377 ;; then emitting a right shift with the shift count negated. This means
1378 ;; that all actual shift counts in the RTL will be positive. This
1379 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions,
1380 ;; which isn't valid.
1381 (define_expand "ashrsi3"
1382 [(set (match_operand:SI 0 "general_operand" "=g")
1383 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1384 (match_operand:QI 2 "general_operand" "g")))]
1388 if (! CONST_INT_P(operands[2]))
1389 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1392 (define_insn_and_split "*ashlnegsi3_const_int"
1393 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1394 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1395 (match_operand:QI 2 "const_int_operand" "n")))]
1401 (ashiftrt:SI (match_dup 1)
1403 (clobber (reg:CC VAX_PSL_REGNUM))])]
1406 (define_insn "*ashlnegsi3_const_int_2<ccn><ccnz><ccz>"
1407 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1408 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1409 (match_operand:QI 2 "const_int_operand" "n")))
1410 (clobber (reg:CC VAX_PSL_REGNUM))]
1414 (define_insn_and_split "*ashlnegsi3"
1415 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1416 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1417 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1423 (ashiftrt:SI (match_dup 1)
1424 (neg:QI (match_dup 2))))
1425 (clobber (reg:CC VAX_PSL_REGNUM))])]
1428 (define_insn "*ashlnegsi3_2<ccn><ccnz><ccz>"
1429 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1430 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
1431 (neg:QI (match_operand:QI 2 "general_operand" "g"))))
1432 (clobber (reg:CC VAX_PSL_REGNUM))]
1436 (define_insn_and_split "ashlsi3"
1437 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1438 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
1439 (match_operand:QI 2 "general_operand" "g")))]
1445 (ashift:SI (match_dup 1)
1447 (clobber (reg:CC VAX_PSL_REGNUM))])]
1450 (define_insn "*ashlsi3<ccn><ccnz><ccz>"
1451 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1452 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
1453 (match_operand:QI 2 "general_operand" "g")))
1454 (clobber (reg:CC VAX_PSL_REGNUM))]
1458 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
1459 return \"addl2 %0,%0\";
1460 if (REG_P (operands[1]) && CONST_INT_P (operands[2]))
1462 int i = INTVAL (operands[2]);
1464 return \"addl3 %1,%1,%0\";
1465 if (i == 2 && !optimize_size)
1467 if (push_operand (operands[0], SImode))
1468 return \"pushal 0[%1]\";
1469 return \"moval 0[%1],%0\";
1471 if (i == 3 && !optimize_size)
1473 if (push_operand (operands[0], SImode))
1474 return \"pushaq 0[%1]\";
1475 return \"movaq 0[%1],%0\";
1478 return \"ashl %2,%1,%0\";
1481 ;; Arithmetic right shift on the VAX works by negating the shift count.
1482 (define_expand "ashrdi3"
1483 [(set (match_operand:DI 0 "general_operand" "=g")
1484 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1485 (match_operand:QI 2 "general_operand" "g")))]
1489 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1492 (define_insn_and_split "ashldi3"
1493 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1494 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1495 (match_operand:QI 2 "general_operand" "g")))]
1501 (ashift:DI (match_dup 1)
1503 (clobber (reg:CC VAX_PSL_REGNUM))])]
1506 (define_insn "*ashldi3<ccn><ccnz><ccz>"
1507 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1508 (ashift:DI (match_operand:DI 1 "general_operand" "g")
1509 (match_operand:QI 2 "general_operand" "g")))
1510 (clobber (reg:CC VAX_PSL_REGNUM))]
1514 (define_insn_and_split "*ashlnegdi3"
1515 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1516 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1517 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1523 (ashiftrt:DI (match_dup 1)
1524 (neg:QI (match_dup 2))))
1525 (clobber (reg:CC VAX_PSL_REGNUM))])]
1528 (define_insn "*ashlnegdi3_2<ccn><ccnz><ccz>"
1529 [(set (match_operand:DI 0 "nonimmediate_operand" "=g")
1530 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g")
1531 (neg:QI (match_operand:QI 2 "general_operand" "g"))))
1532 (clobber (reg:CC VAX_PSL_REGNUM))]
1536 ;; We used to have expand_shift handle logical right shifts by using extzv,
1537 ;; but this make it very difficult to do lshrdi3. Since the VAX is the
1538 ;; only machine with this kludge, it's better to just do this with a
1539 ;; define_expand and remove that case from expand_shift.
1541 (define_expand "lshrsi3"
1543 (minus:QI (const_int 32)
1545 (set (match_operand:SI 0 "nonimmediate_operand" "=g")
1546 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1548 (match_operand:SI 2 "register_operand" "g")))]
1552 operands[3] = gen_reg_rtx (QImode);
1553 operands[4] = gen_lowpart (QImode, operands[2]);
1556 ;; Rotate right on the VAX works by negating the shift count.
1557 (define_expand "rotrsi3"
1558 [(set (match_operand:SI 0 "general_operand" "=g")
1559 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1560 (match_operand:QI 2 "general_operand" "g")))]
1564 if (! CONST_INT_P (operands[2]))
1565 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
1568 (define_insn_and_split "rotlsi3"
1569 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1570 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
1571 (match_operand:QI 2 "general_operand" "g")))]
1577 (rotate:SI (match_dup 1)
1579 (clobber (reg:CC VAX_PSL_REGNUM))])]
1582 (define_insn "*rotlsi3<ccn><ccnz><ccz>"
1583 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1584 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT")
1585 (match_operand:QI 2 "general_operand" "g")))
1586 (clobber (reg:CC VAX_PSL_REGNUM))]
1590 (define_insn_and_split "*rotrsi3_const_int"
1591 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1592 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1593 (match_operand:QI 2 "const_int_operand" "n")))]
1599 (rotatert:SI (match_dup 1)
1601 (clobber (reg:CC VAX_PSL_REGNUM))])]
1604 (define_insn "*rotrsi3_const_int_2<ccn><ccnz><ccz>"
1605 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1606 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1607 (match_operand:QI 2 "const_int_operand" "n")))
1608 (clobber (reg:CC VAX_PSL_REGNUM))]
1612 (define_insn_and_split "*rotrnegsi3"
1613 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1614 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1615 (neg:QI (match_operand:QI 2 "general_operand" "g"))))]
1621 (rotatert:SI (match_dup 1)
1622 (neg:QI (match_dup 2))))
1623 (clobber (reg:CC VAX_PSL_REGNUM))])]
1626 (define_insn "*rotrnegsi3_2<ccn><ccnz><ccz>"
1627 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1628 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT")
1629 (neg:QI (match_operand:QI 2 "general_operand" "g"))))
1630 (clobber (reg:CC VAX_PSL_REGNUM))]
1634 ;; This insn is probably slower than a multiply and an add.
1635 ;;(define_insn_and_split "*amulsi4"
1636 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1637 ;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1638 ;; (match_operand:SI 2 "general_operand" "g"))
1639 ;; (match_operand:SI 3 "general_operand" "g")))]
1642 ;; "reload_completed"
1644 ;; [(set (match_dup 0)
1645 ;; (mult:SI (plus:SI (match_dup 1)
1648 ;; (clobber (reg:CC VAX_PSL_REGNUM))])]
1651 ;;(define_insn "*amulsi4_2<ccn><ccnz><ccz>"
1652 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1653 ;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g")
1654 ;; (match_operand:SI 2 "general_operand" "g"))
1655 ;; (match_operand:SI 3 "general_operand" "g")))
1656 ;; (clobber (reg:CC VAX_PSL_REGNUM))]
1657 ;; "reload_completed"
1658 ;; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0")
1660 ;; Special cases of bit-field insns which we should
1661 ;; recognize in preference to the general case.
1662 ;; These handle aligned 8-bit and 16-bit fields
1663 ;; that can be done with move or convert instructions.
1665 (define_insn_and_split "*insv_aligned"
1666 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
1667 (match_operand:QI 1 "const_int_operand" "n")
1668 (match_operand:SI 2 "const_int_operand" "n"))
1669 (match_operand:SI 3 "general_operand" "g"))]
1670 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1671 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1672 && (!MEM_P (operands[0])
1674 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0),
1676 && !mode_dependent_address_p (XEXP (operands[0], 0),
1677 MEM_ADDR_SPACE (operands[0]))))
1678 && (!(REG_P (operands[0])
1679 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
1680 || INTVAL (operands[2]) == 0)"
1682 "&& reload_completed"
1684 [(set (zero_extract:SI (match_dup 0)
1688 (clobber (reg:CC VAX_PSL_REGNUM))])]
1691 (define_insn "*insv_aligned_2<ccn><ccnz><ccz>"
1692 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
1693 (match_operand:QI 1 "const_int_operand" "n")
1694 (match_operand:SI 2 "const_int_operand" "n"))
1695 (match_operand:SI 3 "general_operand" "g"))
1696 (clobber (reg:CC VAX_PSL_REGNUM))]
1697 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1698 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
1699 && (!MEM_P (operands[0])
1701 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0),
1703 && !mode_dependent_address_p (XEXP (operands[0], 0),
1704 MEM_ADDR_SPACE (operands[0]))))
1705 && (!(REG_P (operands[0])
1706 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0]))))
1707 || INTVAL (operands[2]) == 0)
1708 && reload_completed"
1711 if (!REG_P (operands[0]))
1713 = adjust_address (operands[0],
1714 INTVAL (operands[1]) == 8 ? QImode : HImode,
1715 INTVAL (operands[2]) / 8);
1717 gcc_assert (INTVAL (operands[2]) == 0);
1719 if (INTVAL (operands[1]) == 8)
1720 return \"movb %3,%0\";
1721 return \"movw %3,%0\";
1724 (define_insn_and_split "*extzv_aligned"
1725 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
1726 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1727 (match_operand:QI 2 "const_int_operand" "n")
1728 (match_operand:SI 3 "const_int_operand" "n")))]
1729 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1730 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1731 && (!MEM_P (operands[1])
1733 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1735 && !mode_dependent_address_p (XEXP (operands[1], 0),
1736 MEM_ADDR_SPACE (operands[1]))))
1737 && (!(REG_P (operands[1])
1738 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1739 || INTVAL (operands[3]) == 0)"
1741 "&& reload_completed"
1744 (zero_extract:SI (match_dup 1)
1747 (clobber (reg:CC VAX_PSL_REGNUM))])]
1750 (define_insn "*extzv_aligned_2<ccn><ccnz><ccz>"
1751 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g")
1752 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1753 (match_operand:QI 2 "const_int_operand" "n")
1754 (match_operand:SI 3 "const_int_operand" "n")))
1755 (clobber (reg:CC VAX_PSL_REGNUM))]
1756 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1757 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1758 && (!MEM_P (operands[1])
1760 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1762 && !mode_dependent_address_p (XEXP (operands[1], 0),
1763 MEM_ADDR_SPACE (operands[1]))))
1764 && (!(REG_P (operands[1])
1765 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1766 || INTVAL (operands[3]) == 0)
1767 && reload_completed"
1770 if (!REG_P (operands[1]))
1772 = adjust_address (operands[1],
1773 INTVAL (operands[2]) == 8 ? QImode : HImode,
1774 INTVAL (operands[3]) / 8);
1776 gcc_assert (INTVAL (operands[3]) == 0);
1778 if (INTVAL (operands[2]) == 8)
1779 return \"movzbl %1,%0\";
1780 return \"movzwl %1,%0\";
1783 (define_insn_and_split "*extv_aligned"
1784 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1785 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1786 (match_operand:QI 2 "const_int_operand" "n")
1787 (match_operand:SI 3 "const_int_operand" "n")))]
1788 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1789 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1790 && (!MEM_P (operands[1])
1792 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1794 && !mode_dependent_address_p (XEXP (operands[1], 0),
1795 MEM_ADDR_SPACE (operands[1]))))
1796 && (!(REG_P (operands[1])
1797 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1798 || INTVAL (operands[3]) == 0)"
1800 "&& reload_completed"
1803 (sign_extract:SI (match_dup 1)
1806 (clobber (reg:CC VAX_PSL_REGNUM))])]
1809 (define_insn "*extv_aligned_2<ccn><ccnz><ccz>"
1810 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1811 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1812 (match_operand:QI 2 "const_int_operand" "n")
1813 (match_operand:SI 3 "const_int_operand" "n")))
1814 (clobber (reg:CC VAX_PSL_REGNUM))]
1815 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1816 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
1817 && (!MEM_P (operands[1])
1819 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0),
1821 && !mode_dependent_address_p (XEXP (operands[1], 0),
1822 MEM_ADDR_SPACE (operands[1]))))
1823 && (!(REG_P (operands[1])
1824 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))
1825 || INTVAL (operands[3]) == 0)
1826 && reload_completed"
1829 if (!REG_P (operands[1]))
1831 = adjust_address (operands[1],
1832 INTVAL (operands[2]) == 8 ? QImode : HImode,
1833 INTVAL (operands[3]) / 8);
1835 gcc_assert (INTVAL (operands[3]) == 0);
1837 if (INTVAL (operands[2]) == 8)
1838 return \"cvtbl %1,%0\";
1839 return \"cvtwl %1,%0\";
1842 ;; Register and non-offsettable-memory SImode cases of bit-field insns.
1844 (define_insn "*cmpv_<mode>"
1845 [(set (reg:VAXcc VAX_PSL_REGNUM)
1847 (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro")
1848 (match_operand:QI 1 "general_operand" "g")
1849 (match_operand:SI 2 "general_operand" "nrmT"))
1850 (match_operand:SI 3 "general_operand" "nrmT")))]
1854 (define_insn "*cmpzv_<mode>"
1855 [(set (reg:VAXcc VAX_PSL_REGNUM)
1857 (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro")
1858 (match_operand:QI 1 "general_operand" "g")
1859 (match_operand:SI 2 "general_operand" "nrmT"))
1860 (match_operand:SI 3 "general_operand" "nrmT")))]
1862 "cmpzv %2,%1,%0,%3")
1864 ;; When the field position and size are constant and the destination
1865 ;; is a register, extv and extzv are much slower than a rotate followed
1866 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v
1867 ;; anyway, we can't allow immediate values for the primary source operand.
1869 (define_insn_and_split "*extv_non_const"
1870 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1871 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1872 (match_operand:QI 2 "general_operand" "g")
1873 (match_operand:SI 3 "general_operand" "nrmT")))]
1879 (sign_extract:SI (match_dup 1)
1882 (clobber (reg:CC VAX_PSL_REGNUM))])]
1885 (define_insn "*extv_non_const_2<ccn><ccnz><ccz>"
1886 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1887 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1888 (match_operand:QI 2 "general_operand" "g")
1889 (match_operand:SI 3 "general_operand" "nrmT")))
1890 (clobber (reg:CC VAX_PSL_REGNUM))]
1894 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
1895 || ! REG_P (operands[0])
1896 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16))
1897 return \"extv %3,%2,%1,%0\";
1898 if (INTVAL (operands[2]) == 8)
1899 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
1900 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
1903 (define_insn_and_split "*extzv_non_const"
1904 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1905 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1906 (match_operand:QI 2 "general_operand" "g")
1907 (match_operand:SI 3 "general_operand" "nrmT")))]
1913 (zero_extract:SI (match_dup 1)
1916 (clobber (reg:CC VAX_PSL_REGNUM))])]
1919 (define_insn "*extzv_non_const_2<ccn><ccnz><ccz>"
1920 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1921 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro")
1922 (match_operand:QI 2 "general_operand" "g")
1923 (match_operand:SI 3 "general_operand" "nrmT")))
1924 (clobber (reg:CC VAX_PSL_REGNUM))]
1928 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2])
1929 || ! REG_P (operands[0]))
1930 return \"extzv %3,%2,%1,%0\";
1931 if (INTVAL (operands[2]) == 8)
1932 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
1933 if (INTVAL (operands[2]) == 16)
1934 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
1935 if (INTVAL (operands[3]) & 31)
1936 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
1937 if (rtx_equal_p (operands[0], operands[1]))
1938 return \"bicl2 %M2,%0\";
1939 return \"bicl3 %M2,%1,%0\";
1942 ;; Non-register cases.
1943 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases
1944 ;; don't match these (and therefore match the cases above instead).
1946 (define_insn "*cmpv_2_<mode>"
1947 [(set (reg:VAXcc VAX_PSL_REGNUM)
1949 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m")
1950 (match_operand:QI 1 "general_operand" "g")
1951 (match_operand:SI 2 "general_operand" "nrmT"))
1952 (match_operand:SI 3 "general_operand" "nrmT")))]
1956 (define_insn "*cmpzv_2_<mode>"
1957 [(set (reg:VAXcc VAX_PSL_REGNUM)
1959 (zero_extract:SI (match_operand:QI 0 "memory_operand" "m")
1960 (match_operand:QI 1 "general_operand" "g")
1961 (match_operand:SI 2 "general_operand" "nrmT"))
1962 (match_operand:SI 3 "general_operand" "nrmT")))]
1964 "cmpzv %2,%1,%0,%3")
1966 (define_expand "extv"
1967 [(set (match_operand:SI 0 "general_operand" "")
1968 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
1969 (match_operand:QI 2 "general_operand" "")
1970 (match_operand:SI 3 "general_operand" "")))]
1974 (define_insn_and_split "*extv"
1975 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1976 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
1977 (match_operand:QI 2 "general_operand" "g")
1978 (match_operand:SI 3 "general_operand" "nrmT")))]
1984 (sign_extract:SI (match_dup 1)
1987 (clobber (reg:CC VAX_PSL_REGNUM))])]
1990 (define_insn "*extv_2<ccn><ccnz><ccz>"
1991 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
1992 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m")
1993 (match_operand:QI 2 "general_operand" "g")
1994 (match_operand:SI 3 "general_operand" "nrmT")))
1995 (clobber (reg:CC VAX_PSL_REGNUM))]
1999 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
2000 || !CONST_INT_P (operands[3])
2001 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)
2002 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
2003 || side_effects_p (operands[1])
2004 || (MEM_P (operands[1])
2005 && mode_dependent_address_p (XEXP (operands[1], 0),
2006 MEM_ADDR_SPACE (operands[1]))))
2007 return \"extv %3,%2,%1,%0\";
2008 if (INTVAL (operands[2]) == 8)
2009 return \"rotl %R3,%1,%0\;cvtbl %0,%0\";
2010 return \"rotl %R3,%1,%0\;cvtwl %0,%0\";
2013 (define_expand "extzv"
2014 [(set (match_operand:SI 0 "general_operand" "")
2015 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
2016 (match_operand:QI 2 "general_operand" "")
2017 (match_operand:SI 3 "general_operand" "")))]
2021 (define_insn_and_split "*extzv"
2022 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2023 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
2024 (match_operand:QI 2 "general_operand" "g")
2025 (match_operand:SI 3 "general_operand" "nrmT")))]
2031 (zero_extract:SI (match_dup 1)
2034 (clobber (reg:CC VAX_PSL_REGNUM))])]
2037 (define_insn "*extzv_2<ccn><ccnz><ccz>"
2038 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2039 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m")
2040 (match_operand:QI 2 "general_operand" "g")
2041 (match_operand:SI 3 "general_operand" "nrmT")))
2042 (clobber (reg:CC VAX_PSL_REGNUM))]
2046 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2])
2047 || !CONST_INT_P (operands[3])
2048 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32
2049 || side_effects_p (operands[1])
2050 || (MEM_P (operands[1])
2051 && mode_dependent_address_p (XEXP (operands[1], 0),
2052 MEM_ADDR_SPACE (operands[1]))))
2053 return \"extzv %3,%2,%1,%0\";
2054 if (INTVAL (operands[2]) == 8)
2055 return \"rotl %R3,%1,%0\;movzbl %0,%0\";
2056 if (INTVAL (operands[2]) == 16)
2057 return \"rotl %R3,%1,%0\;movzwl %0,%0\";
2058 if (MEM_P (operands[1])
2059 && GET_CODE (XEXP (operands[1], 0)) == PLUS
2060 && REG_P (XEXP (XEXP (operands[1], 0), 0))
2061 && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
2062 && CONST_INT_P (operands[2])
2063 && CONST_INT_P (operands[3]))
2065 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1));
2066 HOST_WIDE_INT l = INTVAL (operands[2]);
2067 HOST_WIDE_INT v = INTVAL (operands[3]);
2068 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
2071 tmp = XEXP (XEXP (operands[1], 0), 0);
2073 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
2074 operands[1] = gen_rtx_MEM (QImode, tmp);
2075 operands[3] = GEN_INT (v + (o & 3) * 8);
2078 return \"extzv %3,%2,%1,%0\";
2080 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\";
2083 ;; Combine EXTV/CMPL and EXTZV/CMPL sequences where the output of
2084 ;; extraction is used for the comparison only into CMPV and CMPZV
2088 [(set (match_operand:SI 0 "register_operand")
2089 (any_extract:SI (match_operand 1 "general_operand")
2090 (match_operand:QI 2 "general_operand")
2091 (match_operand:SI 3 "general_operand")))
2092 (clobber (reg:CC VAX_PSL_REGNUM))])
2093 (set (reg:VAXcc VAX_PSL_REGNUM)
2094 (compare:VAXcc (match_dup 0)
2095 (match_operand:SI 4 "general_operand")))]
2096 "peep2_reg_dead_p (2, operands[0])"
2097 [(set (reg:VAXcc VAX_PSL_REGNUM)
2099 (any_extract:SI (match_dup 1)
2105 (define_expand "insv"
2106 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
2107 (match_operand:QI 1 "general_operand" "")
2108 (match_operand:SI 2 "general_operand" ""))
2109 (match_operand:SI 3 "general_operand" ""))]
2113 ;; This one actually doesn't change CC.
2114 (define_insn "*insv"
2115 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
2116 (match_operand:QI 1 "general_operand" "g")
2117 (match_operand:SI 2 "general_operand" "nrmT"))
2118 (match_operand:SI 3 "general_operand" "nrmT"))]
2122 if (MEM_P (operands[0])
2123 && GET_CODE (XEXP (operands[0], 0)) == PLUS
2124 && REG_P (XEXP (XEXP (operands[0], 0), 0))
2125 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1))
2126 && CONST_INT_P (operands[1])
2127 && CONST_INT_P (operands[2]))
2129 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1));
2130 HOST_WIDE_INT v = INTVAL (operands[2]);
2131 HOST_WIDE_INT l = INTVAL (operands[1]);
2132 if ((o & 3) && (o & 3) * 8 + v + l <= 32)
2135 tmp = XEXP (XEXP (operands[0], 0), 0);
2137 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3));
2138 operands[0] = gen_rtx_MEM (QImode, tmp);
2139 operands[2] = GEN_INT (v + (o & 3) * 8);
2142 return \"insv %3,%2,%1,%0\";
2145 ;; This one actually doesn't change CC.
2146 (define_insn "*insv_2"
2147 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro")
2148 (match_operand:QI 1 "general_operand" "g")
2149 (match_operand:SI 2 "general_operand" "nrmT"))
2150 (match_operand:SI 3 "general_operand" "nrmT"))]
2154 ;; Unconditional jump
2157 (label_ref (match_operand 0 "" "")))]
2161 ;; Conditional jumps
2163 (define_expand "cbranch<mode>4"
2166 (match_operator 0 "ordered_comparison_operator"
2167 [(match_operand:VAXint 1 "general_operand" "")
2168 (match_operand:VAXint 2 "general_operand" "")])
2169 (label_ref (match_operand 3 "" ""))
2174 (define_insn_and_split "*cbranch<VAXint:mode>4_<VAXcc:mode>"
2177 (match_operator 0 "vax_<cc>_comparison_operator"
2178 [(match_operand:VAXint 1 "general_operand" "nrmT")
2179 (match_operand:VAXint 2 "general_operand" "nrmT")])
2180 (label_ref (match_operand 3 "" ""))
2185 [(set (reg:VAXcc VAX_PSL_REGNUM)
2186 (compare:VAXcc (match_dup 1) (match_dup 2)))
2189 (match_op_dup 0 [(reg:VAXcc VAX_PSL_REGNUM)
2191 (label_ref (match_operand 3 "" ""))
2195 (define_expand "cbranch<mode>4"
2198 (match_operator 0 "ordered_comparison_operator"
2199 [(match_operand:VAXfp 1 "general_operand" "")
2200 (match_operand:VAXfp 2 "general_operand" "")])
2201 (label_ref (match_operand 3 "" ""))
2206 (define_insn_and_split "*cbranch<VAXfp:mode>4_<VAXccnz:mode>"
2209 (match_operator 0 "vax_<cc>_comparison_operator"
2210 [(match_operand:VAXfp 1 "general_operand" "gF")
2211 (match_operand:VAXfp 2 "general_operand" "gF")])
2212 (label_ref (match_operand 3 "" ""))
2217 [(set (reg:VAXccnz VAX_PSL_REGNUM)
2218 (compare:VAXccnz (match_dup 1) (match_dup 2)))
2221 (match_op_dup 0 [(reg:VAXccnz VAX_PSL_REGNUM)
2223 (label_ref (match_operand 3 "" ""))
2227 (define_insn "*branch_<mode>"
2229 (if_then_else (match_operator 0 "vax_<cc>_comparison_operator"
2230 [(reg:VAXcc VAX_PSL_REGNUM)
2232 (label_ref (match_operand 1 "" ""))
2237 ;; Recognize reversed jumps.
2238 (define_insn "*branch_<mode>_reversed"
2240 (if_then_else (match_operator 0 "vax_<cc>_comparison_operator"
2241 [(reg:VAXcc VAX_PSL_REGNUM)
2244 (label_ref (match_operand 1 "" ""))))]
2246 "j%K0 %l1") ; %K0 negates condition
2248 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand
2249 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is
2250 ;; memory, we use QImode in the insn. So we can't use those instructions
2251 ;; for mode-dependent addresses.
2256 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
2258 (match_operand:SI 1 "general_operand" "I,nrmT"))
2260 (label_ref (match_operand 2 "" ""))
2270 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g")
2272 (match_operand:SI 1 "general_operand" "I,nrmT"))
2274 (label_ref (match_operand 2 "" ""))
2284 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
2286 (match_operand:SI 1 "general_operand" "I,nrmT"))
2288 (label_ref (match_operand 2 "" ""))
2298 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r")
2300 (match_operand:SI 1 "general_operand" "I,nrmT"))
2302 (label_ref (match_operand 2 "" ""))
2309 ;; Subtract-and-jump and Add-and-jump insns.
2310 ;; These are not used when output is for the Unix assembler
2311 ;; because it does not know how to modify them to reach far.
2313 ;; Normal sob insns.
2315 (define_insn_and_split "*jsobgtr"
2318 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2321 (label_ref (match_operand 1 "" ""))
2324 (plus:SI (match_dup 0)
2328 "&& reload_completed"
2332 (gt (plus:SI (match_dup 0)
2335 (label_ref (match_dup 1))
2338 (plus:SI (match_dup 0)
2340 (clobber (reg:CC VAX_PSL_REGNUM))])]
2343 (define_insn "*jsobgtr_2"
2346 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2349 (label_ref (match_operand 1 "" ""))
2352 (plus:SI (match_dup 0)
2354 (clobber (reg:CC VAX_PSL_REGNUM))]
2355 "!TARGET_UNIX_ASM && reload_completed"
2358 (define_insn_and_split "*jsobgeq"
2361 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2364 (label_ref (match_operand 1 "" ""))
2367 (plus:SI (match_dup 0)
2371 "&& reload_completed"
2375 (ge (plus:SI (match_dup 0)
2378 (label_ref (match_dup 1))
2381 (plus:SI (match_dup 0)
2383 (clobber (reg:CC VAX_PSL_REGNUM))])]
2386 (define_insn "*jsobgeq_2"
2389 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2392 (label_ref (match_operand 1 "" ""))
2395 (plus:SI (match_dup 0)
2397 (clobber (reg:CC VAX_PSL_REGNUM))]
2398 "!TARGET_UNIX_ASM && reload_completed"
2401 ;; Normal aob insns. Define a version for when operands[1] is a constant.
2402 (define_insn_and_split "*jaoblss"
2405 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2407 (match_operand:SI 1 "general_operand" "nrmT"))
2408 (label_ref (match_operand 2 "" ""))
2411 (plus:SI (match_dup 0)
2415 "&& reload_completed"
2419 (lt (plus:SI (match_dup 0)
2422 (label_ref (match_dup 2))
2425 (plus:SI (match_dup 0)
2427 (clobber (reg:CC VAX_PSL_REGNUM))])]
2430 (define_insn "*jaoblss_2"
2433 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2435 (match_operand:SI 1 "general_operand" "nrmT"))
2436 (label_ref (match_operand 2 "" ""))
2439 (plus:SI (match_dup 0)
2441 (clobber (reg:CC VAX_PSL_REGNUM))]
2442 "!TARGET_UNIX_ASM && reload_completed"
2443 "jaoblss %1,%0,%l2")
2445 (define_insn_and_split "*jaoblss_const"
2448 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
2449 (match_operand:SI 1 "general_operand" "nrmT"))
2450 (label_ref (match_operand 2 "" ""))
2453 (plus:SI (match_dup 0)
2455 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
2457 "&& reload_completed"
2463 (label_ref (match_dup 2))
2466 (plus:SI (match_dup 0)
2468 (clobber (reg:CC VAX_PSL_REGNUM))])]
2471 (define_insn "*jaoblss_const_2"
2474 (lt (match_operand:SI 0 "nonimmediate_operand" "+g")
2475 (match_operand:SI 1 "general_operand" "nrmT"))
2476 (label_ref (match_operand 2 "" ""))
2479 (plus:SI (match_dup 0)
2481 (clobber (reg:CC VAX_PSL_REGNUM))]
2482 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed"
2483 "jaoblss %P1,%0,%l2")
2485 (define_insn_and_split "*jaobleq"
2488 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2490 (match_operand:SI 1 "general_operand" "nrmT"))
2491 (label_ref (match_operand 2 "" ""))
2494 (plus:SI (match_dup 0)
2498 "&& reload_completed"
2502 (le (plus:SI (match_dup 0)
2505 (label_ref (match_dup 2))
2508 (plus:SI (match_dup 0)
2510 (clobber (reg:CC VAX_PSL_REGNUM))])]
2513 (define_insn "*jaobleq_2"
2516 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g")
2518 (match_operand:SI 1 "general_operand" "nrmT"))
2519 (label_ref (match_operand 2 "" ""))
2522 (plus:SI (match_dup 0)
2524 (clobber (reg:CC VAX_PSL_REGNUM))]
2525 "!TARGET_UNIX_ASM && reload_completed"
2526 "jaobleq %1,%0,%l2")
2528 (define_insn_and_split "*jaobleq_const"
2531 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
2532 (match_operand:SI 1 "general_operand" "nrmT"))
2533 (label_ref (match_operand 2 "" ""))
2536 (plus:SI (match_dup 0)
2538 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])"
2540 "&& reload_completed"
2546 (label_ref (match_dup 2))
2549 (plus:SI (match_dup 0)
2551 (clobber (reg:CC VAX_PSL_REGNUM))])]
2554 (define_insn "*jaobleq_const_2"
2557 (le (match_operand:SI 0 "nonimmediate_operand" "+g")
2558 (match_operand:SI 1 "general_operand" "nrmT"))
2559 (label_ref (match_operand 2 "" ""))
2562 (plus:SI (match_dup 0)
2564 (clobber (reg:CC VAX_PSL_REGNUM))]
2565 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed"
2566 "jaobleq %P1,%0,%l2")
2568 ;; Something like a sob insn, but compares against -1.
2569 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.
2571 (define_insn_and_split "*jsobneq_minus_one"
2574 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
2576 (label_ref (match_operand 1 "" ""))
2579 (plus:SI (match_dup 0)
2589 (label_ref (match_dup 1))
2592 (plus:SI (match_dup 0)
2594 (clobber (reg:CC VAX_PSL_REGNUM))])]
2597 (define_insn "*jsobneq_minus_one_2"
2600 (ne (match_operand:SI 0 "nonimmediate_operand" "+g")
2602 (label_ref (match_operand 1 "" ""))
2605 (plus:SI (match_dup 0)
2607 (clobber (reg:CC VAX_PSL_REGNUM))]
2609 "decl %0\;jgequ %l1")
2611 (define_expand "call_pop"
2612 [(parallel [(call (match_operand:QI 0 "memory_operand" "")
2613 (match_operand:SI 1 "const_int_operand" ""))
2614 (set (reg:SI VAX_SP_REGNUM)
2615 (plus:SI (reg:SI VAX_SP_REGNUM)
2616 (match_operand:SI 3 "immediate_operand" "")))])]
2619 gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0);
2621 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
2622 during EH unwinding. We must include the argument count pushed by
2623 the calls instruction. */
2624 operands[1] = GEN_INT (INTVAL (operands[3]) + 4);
2627 (define_insn "*call_pop"
2628 [(call (match_operand:QI 0 "memory_operand" "m")
2629 (match_operand:SI 1 "const_int_operand" "n"))
2630 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
2631 (match_operand:SI 2 "immediate_operand" "i")))]
2634 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4);
2635 return "calls %1,%0";
2638 (define_expand "call_value_pop"
2639 [(parallel [(set (match_operand 0 "" "")
2640 (call (match_operand:QI 1 "memory_operand" "")
2641 (match_operand:SI 2 "const_int_operand" "")))
2642 (set (reg:SI VAX_SP_REGNUM)
2643 (plus:SI (reg:SI VAX_SP_REGNUM)
2644 (match_operand:SI 4 "immediate_operand" "")))])]
2647 gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0);
2649 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
2650 during EH unwinding. We must include the argument count pushed by
2651 the calls instruction. */
2652 operands[2] = GEN_INT (INTVAL (operands[4]) + 4);
2655 (define_insn "*call_value_pop"
2656 [(set (match_operand 0 "" "")
2657 (call (match_operand:QI 1 "memory_operand" "m")
2658 (match_operand:SI 2 "const_int_operand" "n")))
2659 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM)
2660 (match_operand:SI 3 "immediate_operand" "i")))]
2664 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4);
2665 return \"calls %2,%1\";
2668 (define_expand "call"
2669 [(call (match_operand:QI 0 "memory_operand" "")
2670 (match_operand:SI 1 "const_int_operand" ""))]
2674 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size
2675 during EH unwinding. We must include the argument count pushed by
2676 the calls instruction. */
2677 operands[1] = GEN_INT (INTVAL (operands[1]) + 4);
2680 (define_insn "*call"
2681 [(call (match_operand:QI 0 "memory_operand" "m")
2682 (match_operand:SI 1 "const_int_operand" ""))]
2686 (define_expand "call_value"
2687 [(set (match_operand 0 "" "")
2688 (call (match_operand:QI 1 "memory_operand" "")
2689 (match_operand:SI 2 "const_int_operand" "")))]
2693 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size
2694 during EH unwinding. We must include the argument count pushed by
2695 the calls instruction. */
2696 operands[2] = GEN_INT (INTVAL (operands[2]) + 4);
2699 (define_insn "*call_value"
2700 [(set (match_operand 0 "" "")
2701 (call (match_operand:QI 1 "memory_operand" "m")
2702 (match_operand:SI 2 "const_int_operand" "")))]
2706 ;; Call subroutine returning any type.
2708 (define_expand "untyped_call"
2709 [(parallel [(call (match_operand 0 "" "")
2711 (match_operand 1 "" "")
2712 (match_operand 2 "" "")])]
2718 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx));
2720 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2722 rtx set = XVECEXP (operands[2], 0, i);
2723 emit_move_insn (SET_DEST (set), SET_SRC (set));
2726 /* The optimizer does not know that the call sets the function value
2727 registers we stored in the result block. We avoid problems by
2728 claiming that all hard registers are used and clobbered at this
2730 emit_insn (gen_blockage ());
2735 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2736 ;; all of memory. This blocks insns from being moved across this point.
2738 (define_insn "blockage"
2739 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
2743 (define_insn "procedure_entry_mask"
2744 [(unspec_volatile [(match_operand 0 "const_int_operand")] VUNSPEC_PEM)]
2748 (define_insn "return"
2753 (define_expand "prologue"
2757 vax_expand_prologue ();
2761 (define_expand "epilogue"
2766 emit_jump_insn (gen_return ());
2775 ;; This had a wider constraint once, and it had trouble.
2776 ;; If you are tempted to try `g', please don't--it's not worth
2777 ;; the risk we will reopen the same bug.
2778 (define_insn "indirect_jump"
2779 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2783 ;; This is here to accept 5 arguments (as passed by expand_end_case)
2784 ;; and pass the first 4 along to the casesi1 pattern that really does
2785 ;; the actual casesi work. We emit a jump here to the default label
2786 ;; _before_ the casesi so that we can be sure that the casesi never
2788 ;; This is suboptimal perhaps, but so is much of the rest of this
2789 ;; machine description. For what it's worth, HPPA uses the same trick.
2791 ;; operand 0 is index
2792 ;; operand 1 is the minimum bound (a const_int)
2793 ;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int)
2794 ;; operand 3 is CODE_LABEL for the table;
2795 ;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default).
2798 ;; i = index - minimum_bound
2799 ;; if (i > (maximum_bound - minimum_bound + 1) goto default;
2800 ;; casesi (i, 0, table);
2802 (define_expand "casesi"
2803 [(match_operand:SI 0 "general_operand" "")
2804 (match_operand:SI 1 "general_operand" "")
2805 (match_operand:SI 2 "general_operand" "")
2806 (match_operand 3 "" "")
2807 (match_operand 4 "" "")]
2812 /* i = index - minimum_bound;
2813 But only if the lower bound is not already zero. */
2814 if (operands[1] != const0_rtx)
2816 rtx index = gen_reg_rtx (SImode);
2817 emit_insn (gen_addsi3 (index,
2819 gen_int_mode (-INTVAL (operands[1]), SImode)));
2820 operands[0] = index;
2823 /* if (i > (maximum_bound - minimum_bound + 1)) goto default; */
2824 test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]);
2825 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4]));
2827 /* casesi (i, 0, table); */
2828 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3]));
2832 ;; This insn is a bit of a lier. It actually falls through if no case
2833 ;; matches. But, we prevent that from ever happening by emitting a jump
2834 ;; before this, see the define_expand above.
2835 (define_insn_and_split "casesi1"
2836 [(match_operand:SI 1 "const_int_operand" "n")
2838 (plus:SI (sign_extend:SI
2841 (match_operand:SI 0 "general_operand" "nrmT")
2844 (label_ref:SI (match_operand 2 "" ""))))]
2851 (plus:SI (sign_extend:SI
2857 (label_ref:SI (match_dup 2))))
2858 (clobber (reg:CC VAX_PSL_REGNUM))])]
2861 (define_insn "*casesi1"
2862 [(match_operand:SI 1 "const_int_operand" "n")
2864 (plus:SI (sign_extend:SI
2867 (match_operand:SI 0 "general_operand" "nrmT")
2870 (label_ref:SI (match_operand 2 "" ""))))
2871 (clobber (reg:CC VAX_PSL_REGNUM))]
2875 (define_insn_and_split "*pushsym"
2876 [(set (match_operand:SI 0 "push_operand" "=g")
2877 (match_operand:SI 1 "pic_symbolic_operand" "A"))]
2884 (clobber (reg:CC VAX_PSL_REGNUM))])]
2887 (define_insn "*pushsym_2<ccn><ccnz><ccz>"
2888 [(set (match_operand:SI 0 "push_operand" "=g")
2889 (match_operand:SI 1 "pic_symbolic_operand" "A"))
2890 (clobber (reg:CC VAX_PSL_REGNUM))]
2894 (define_insn_and_split "*movsym"
2895 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2896 (match_operand:SI 1 "pic_symbolic_operand" "A"))]
2903 (clobber (reg:CC VAX_PSL_REGNUM))])]
2906 (define_insn "*movsym_2<ccn><ccnz><ccz>"
2907 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2908 (match_operand:SI 1 "pic_symbolic_operand" "A"))
2909 (clobber (reg:CC VAX_PSL_REGNUM))]
2913 (define_insn_and_split "*pushsymreg"
2914 [(set (match_operand:SI 0 "push_operand" "=g")
2915 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2916 (match_operand:SI 2 "pic_symbolic_operand" "A")))]
2919 "&& reload_completed"
2922 (plus:SI (match_dup 1)
2924 (clobber (reg:CC VAX_PSL_REGNUM))])]
2927 (define_insn "*pushsymreg_2<ccn><ccnz><ccz>"
2928 [(set (match_operand:SI 0 "push_operand" "=g")
2929 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2930 (match_operand:SI 2 "pic_symbolic_operand" "A")))
2931 (clobber (reg:CC VAX_PSL_REGNUM))]
2932 "flag_pic && reload_completed"
2935 (define_insn_and_split "*movsymreg"
2936 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2937 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2938 (match_operand:SI 2 "pic_symbolic_operand" "A")))]
2941 "&& reload_completed"
2944 (plus:SI (match_dup 1)
2946 (clobber (reg:CC VAX_PSL_REGNUM))])]
2949 (define_insn "*movsymreg_2<ccn><ccnz><ccz>"
2950 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2951 (plus:SI (match_operand:SI 1 "register_operand" "%r")
2952 (match_operand:SI 2 "pic_symbolic_operand" "A")))
2953 (clobber (reg:CC VAX_PSL_REGNUM))]
2954 "flag_pic && reload_completed"
2957 ;;- load or push effective address
2958 ;; These come after the move and add/sub patterns
2959 ;; because we don't want pushl $1 turned into pushad 1.
2960 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.
2962 ;; It does not work to use constraints to distinguish pushes from moves,
2963 ;; because < matches any autodecrement, not just a push.
2965 (define_insn_and_split "pushaddr<mode>"
2966 [(set (match_operand:SI 0 "push_operand" "=g")
2967 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
2974 (clobber (reg:CC VAX_PSL_REGNUM))])]
2977 (define_insn "*pushaddr<mode><ccn><ccnz><ccz>"
2978 [(set (match_operand:SI 0 "push_operand" "=g")
2979 (match_operand:VAXintQHSD 1 "address_operand" "p"))
2980 (clobber (reg:CC VAX_PSL_REGNUM))]
2982 "pusha<VAXintQHSD:isfx> %a1")
2984 (define_insn_and_split "movaddr<mode>"
2985 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2986 (match_operand:VAXintQHSD 1 "address_operand" "p"))]
2993 (clobber (reg:CC VAX_PSL_REGNUM))])]
2996 (define_insn "*movaddr<mode><ccn><ccnz><ccz>"
2997 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
2998 (match_operand:VAXintQHSD 1 "address_operand" "p"))
2999 (clobber (reg:CC VAX_PSL_REGNUM))]
3001 "mova<VAXintQHSD:isfx> %a1,%0")
3003 (define_insn_and_split "pushaddr<mode>"
3004 [(set (match_operand:SI 0 "push_operand" "=g")
3005 (match_operand:VAXfp 1 "address_operand" "p"))]
3012 (clobber (reg:CC VAX_PSL_REGNUM))])]
3015 (define_insn "*pushaddr<mode><ccn><ccnz><ccz>"
3016 [(set (match_operand:SI 0 "push_operand" "=g")
3017 (match_operand:VAXfp 1 "address_operand" "p"))
3018 (clobber (reg:CC VAX_PSL_REGNUM))]
3020 "pusha<VAXfp:fsfx> %a1")
3022 (define_insn_and_split "movaddr<mode>"
3023 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
3024 (match_operand:VAXfp 1 "address_operand" "p"))]
3031 (clobber (reg:CC VAX_PSL_REGNUM))])]
3034 (define_insn "*movaddr<mode>"
3035 [(set (match_operand:SI 0 "nonimmediate_operand" "=g")
3036 (match_operand:VAXfp 1 "address_operand" "p"))
3037 (clobber (reg:CC VAX_PSL_REGNUM))]
3039 "mova<VAXfp:fsfx> %a1,%0")
3041 ;; These used to be peepholes, but it is more straightforward to do them
3042 ;; as single insns. However, we must force the output to be a register
3043 ;; if it is not an offsettable address so that we know that we can assign
3046 ;; If we had a good way of evaluating the relative costs, these could be
3047 ;; machine-independent.
3049 ;; Optimize extzv ...,z; andl2 ...,z
3050 ;; or ashl ...,z; andl2 ...,z
3051 ;; with other operands constant. This is what the combiner converts the
3052 ;; above sequences to before attempting to recognize the new insn.
3054 (define_insn_and_split "*andashlnegsi4"
3055 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3056 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
3057 (match_operand:QI 2 "const_int_operand" "n"))
3058 (match_operand:SI 3 "const_int_operand" "n")))]
3059 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0"
3061 "&& reload_completed"
3064 (and:SI (ashiftrt:SI (match_dup 1)
3067 (clobber (reg:CC VAX_PSL_REGNUM))])]
3070 (define_insn "*andashlnegsi4_2<ccn><ccnz><ccz>"
3071 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3072 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT")
3073 (match_operand:QI 2 "const_int_operand" "n"))
3074 (match_operand:SI 3 "const_int_operand" "n")))
3075 (clobber (reg:CC VAX_PSL_REGNUM))]
3076 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0
3077 && reload_completed"
3080 unsigned long mask1 = INTVAL (operands[3]);
3081 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1;
3083 if ((mask1 & mask2) != mask1)
3084 operands[3] = GEN_INT (mask1 & mask2);
3086 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\";
3089 ;; left-shift and mask
3090 ;; The only case where `ashl' is better is if the mask only turns off
3091 ;; bits that the ashl would anyways, in which case it should have been
3094 (define_insn_and_split "*andashlsi4"
3095 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3096 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
3097 (match_operand:QI 2 "const_int_operand" "n"))
3098 (match_operand:SI 3 "const_int_operand" "n")))]
3104 (and:SI (ashift:SI (match_dup 1)
3107 (clobber (reg:CC VAX_PSL_REGNUM))])]
3110 (define_insn "*andashlsi4_2<ccn><ccnz><ccz>"
3111 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
3112 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT")
3113 (match_operand:QI 2 "const_int_operand" "n"))
3114 (match_operand:SI 3 "const_int_operand" "n")))
3115 (clobber (reg:CC VAX_PSL_REGNUM))]
3120 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1));
3121 return \"rotl %2,%1,%0\;bicl2 %N3,%0\";
3124 ;; Instruction sequence to sync the VAX instruction stream.
3125 (define_insn "sync_istream"
3126 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)]
3128 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei")
3130 (define_expand "nonlocal_goto"
3131 [(use (match_operand 0 "general_operand" ""))
3132 (use (match_operand 1 "general_operand" ""))
3133 (use (match_operand 2 "general_operand" ""))
3134 (use (match_operand 3 "general_operand" ""))]
3137 rtx lab = operands[1];
3138 rtx stack = operands[2];
3139 rtx fp = operands[3];
3141 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)));
3142 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx));
3144 emit_move_insn (hard_frame_pointer_rtx, fp);
3145 emit_stack_restore (SAVE_NONLOCAL, stack);
3147 emit_use (hard_frame_pointer_rtx);
3148 emit_use (stack_pointer_rtx);
3150 /* We'll convert this to direct jump via a peephole optimization. */
3151 emit_indirect_jump (copy_to_reg (lab));
3156 (include "builtins.md")