1 /* Output routines for Visium.
2 Copyright (C) 2002-2016 Free Software Foundation, Inc.
3 Contributed by C.Nettleton, J.P.Parkes and P.Garbett.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
28 #include "gimple-expr.h"
31 #include "stringpool.h"
37 #include "diagnostic-core.h"
40 #include "fold-const.h"
41 #include "stor-layout.h"
45 #include "insn-attr.h"
49 #include "langhooks.h"
51 #include "tm-constrs.h"
53 #include "tree-pass.h"
57 /* This file should be included last. */
58 #include "target-def.h"
60 /* Enumeration of indexes into machine_libfunc_table. */
61 enum machine_libfunc_index
71 MLTI_set_trampoline_parity
,
76 struct GTY(()) machine_libfuncs
81 /* The table of Visium-specific libfuncs. */
82 static GTY(()) struct machine_libfuncs visium_libfuncs
;
84 #define vlt visium_libfuncs.table
86 /* Accessor macros for visium_libfuncs. */
87 #define long_int_memcpy_libfunc (vlt[MLTI_long_int_memcpy])
88 #define wrd_memcpy_libfunc (vlt[MLTI_wrd_memcpy])
89 #define byt_memcpy_libfunc (vlt[MLTI_byt_memcpy])
90 #define long_int_memset_libfunc (vlt[MLTI_long_int_memset])
91 #define wrd_memset_libfunc (vlt[MLTI_wrd_memset])
92 #define byt_memset_libfunc (vlt[MLTI_byt_memset])
93 #define set_trampoline_parity_libfunc (vlt[MLTI_set_trampoline_parity])
95 /* Machine specific function data. */
96 struct GTY (()) machine_function
98 /* Size of the frame of the function. */
101 /* Size of the reg parm save area, non-zero only for functions with variable
102 argument list. We cannot use the crtl->args.pretend_args_size machinery
103 for this purpose because this size is added to virtual_incoming_args_rtx
104 to give the location of the first parameter passed by the caller on the
105 stack and virtual_incoming_args_rtx is also the location of the first
106 parameter on the stack. So crtl->args.pretend_args_size can be non-zero
107 only if the first non-register named parameter is not passed entirely on
108 the stack and this runs afoul of the need to have a reg parm save area
109 even with a variable argument list starting on the stack because of the
110 separate handling of general and floating-point registers. */
111 int reg_parm_save_area_size
;
113 /* True if we have created an rtx which relies on the frame pointer. */
116 /* True if we have exposed the flags register. From this moment on, we
117 cannot generate simple operations for integer registers. We could
118 use reload_completed for this purpose, but this would cripple the
119 postreload CSE and GCSE passes which run before postreload split. */
123 #define visium_frame_size cfun->machine->frame_size
124 #define visium_reg_parm_save_area_size cfun->machine->reg_parm_save_area_size
125 #define visium_frame_needed cfun->machine->frame_needed
126 #define visium_flags_exposed cfun->machine->flags_exposed
128 /* 1 if the next opcode is to be specially indented. */
129 int visium_indent_opcode
= 0;
131 /* Register number used for long branches when LR isn't available. It
132 must be a call-used register since it isn't saved on function entry.
133 We do not care whether the branch is predicted or not on the GR6,
134 given how unlikely it is to have a long branch in a leaf function. */
135 static unsigned int long_branch_regnum
= 31;
137 static tree
visium_handle_interrupt_attr (tree
*, tree
, tree
, int, bool *);
138 static inline bool current_function_saves_fp (void);
139 static inline bool current_function_saves_lr (void);
140 static inline bool current_function_has_lr_slot (void);
142 /* Supported attributes:
143 interrupt -- specifies this function is an interrupt handler. */
144 static const struct attribute_spec visium_attribute_table
[] =
146 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
147 affects_type_identity } */
148 {"interrupt", 0, 0, true, false, false, visium_handle_interrupt_attr
, false},
149 {NULL
, 0, 0, false, false, false, NULL
, false}
152 static struct machine_function
*visium_init_machine_status (void);
154 /* Target hooks and TARGET_INITIALIZER */
156 static bool visium_pass_by_reference (cumulative_args_t
, enum machine_mode
,
159 static rtx
visium_function_arg (cumulative_args_t
, enum machine_mode
,
162 static void visium_function_arg_advance (cumulative_args_t
, enum machine_mode
,
165 static bool visium_return_in_memory (const_tree
, const_tree fntype
);
167 static rtx
visium_function_value (const_tree
, const_tree fn_decl_or_type
,
170 static rtx
visium_libcall_value (enum machine_mode
, const_rtx
);
172 static void visium_setup_incoming_varargs (cumulative_args_t
,
176 static void visium_va_start (tree valist
, rtx nextarg
);
178 static tree
visium_gimplify_va_arg (tree
, tree
, gimple_seq
*, gimple_seq
*);
180 static bool visium_function_ok_for_sibcall (tree
, tree
);
182 static bool visium_frame_pointer_required (void);
184 static tree
visium_build_builtin_va_list (void);
186 static rtx_insn
*visium_md_asm_adjust (vec
<rtx
> &, vec
<rtx
> &,
188 vec
<rtx
> &, HARD_REG_SET
&);
190 static bool visium_legitimate_constant_p (enum machine_mode
, rtx
);
192 static bool visium_legitimate_address_p (enum machine_mode
, rtx
, bool);
194 static bool visium_print_operand_punct_valid_p (unsigned char);
195 static void visium_print_operand (FILE *, rtx
, int);
196 static void visium_print_operand_address (FILE *, machine_mode
, rtx
);
198 static void visium_conditional_register_usage (void);
200 static rtx
visium_legitimize_address (rtx
, rtx
, enum machine_mode
);
202 static reg_class_t
visium_secondary_reload (bool, rtx
, reg_class_t
,
204 secondary_reload_info
*);
206 static bool visium_class_likely_spilled_p (reg_class_t
);
208 static void visium_trampoline_init (rtx
, tree
, rtx
);
210 static int visium_issue_rate (void);
212 static int visium_adjust_priority (rtx_insn
*, int);
214 static int visium_adjust_cost (rtx_insn
*, int, rtx_insn
*, int, unsigned int);
216 static int visium_register_move_cost (enum machine_mode
, reg_class_t
,
219 static int visium_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
221 static bool visium_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
223 static void visium_option_override (void);
225 static void visium_init_libfuncs (void);
227 static unsigned int visium_reorg (void);
229 /* Setup the global target hooks structure. */
231 #undef TARGET_MAX_ANCHOR_OFFSET
232 #define TARGET_MAX_ANCHOR_OFFSET 31
234 #undef TARGET_PASS_BY_REFERENCE
235 #define TARGET_PASS_BY_REFERENCE visium_pass_by_reference
237 #undef TARGET_FUNCTION_ARG
238 #define TARGET_FUNCTION_ARG visium_function_arg
240 #undef TARGET_FUNCTION_ARG_ADVANCE
241 #define TARGET_FUNCTION_ARG_ADVANCE visium_function_arg_advance
243 #undef TARGET_RETURN_IN_MEMORY
244 #define TARGET_RETURN_IN_MEMORY visium_return_in_memory
246 #undef TARGET_FUNCTION_VALUE
247 #define TARGET_FUNCTION_VALUE visium_function_value
249 #undef TARGET_LIBCALL_VALUE
250 #define TARGET_LIBCALL_VALUE visium_libcall_value
252 #undef TARGET_SETUP_INCOMING_VARARGS
253 #define TARGET_SETUP_INCOMING_VARARGS visium_setup_incoming_varargs
255 #undef TARGET_EXPAND_BUILTIN_VA_START
256 #define TARGET_EXPAND_BUILTIN_VA_START visium_va_start
258 #undef TARGET_BUILD_BUILTIN_VA_LIST
259 #define TARGET_BUILD_BUILTIN_VA_LIST visium_build_builtin_va_list
261 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
262 #define TARGET_GIMPLIFY_VA_ARG_EXPR visium_gimplify_va_arg
264 #undef TARGET_LEGITIMATE_CONSTANT_P
265 #define TARGET_LEGITIMATE_CONSTANT_P visium_legitimate_constant_p
268 #define TARGET_LRA_P hook_bool_void_false
270 #undef TARGET_LEGITIMATE_ADDRESS_P
271 #define TARGET_LEGITIMATE_ADDRESS_P visium_legitimate_address_p
273 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
274 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P visium_print_operand_punct_valid_p
275 #undef TARGET_PRINT_OPERAND
276 #define TARGET_PRINT_OPERAND visium_print_operand
277 #undef TARGET_PRINT_OPERAND_ADDRESS
278 #define TARGET_PRINT_OPERAND_ADDRESS visium_print_operand_address
280 #undef TARGET_ATTRIBUTE_TABLE
281 #define TARGET_ATTRIBUTE_TABLE visium_attribute_table
283 #undef TARGET_ADDRESS_COST
284 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
286 #undef TARGET_STRICT_ARGUMENT_NAMING
287 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
289 #undef TARGET_SCHED_ISSUE_RATE
290 #define TARGET_SCHED_ISSUE_RATE visium_issue_rate
292 #undef TARGET_SCHED_ADJUST_PRIORITY
293 #define TARGET_SCHED_ADJUST_PRIORITY visium_adjust_priority
295 #undef TARGET_SCHED_ADJUST_COST
296 #define TARGET_SCHED_ADJUST_COST visium_adjust_cost
298 #undef TARGET_MEMORY_MOVE_COST
299 #define TARGET_MEMORY_MOVE_COST visium_memory_move_cost
301 #undef TARGET_REGISTER_MOVE_COST
302 #define TARGET_REGISTER_MOVE_COST visium_register_move_cost
304 #undef TARGET_RTX_COSTS
305 #define TARGET_RTX_COSTS visium_rtx_costs
307 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
308 #define TARGET_FUNCTION_OK_FOR_SIBCALL visium_function_ok_for_sibcall
310 #undef TARGET_FRAME_POINTER_REQUIRED
311 #define TARGET_FRAME_POINTER_REQUIRED visium_frame_pointer_required
313 #undef TARGET_SECONDARY_RELOAD
314 #define TARGET_SECONDARY_RELOAD visium_secondary_reload
316 #undef TARGET_CLASS_LIKELY_SPILLED_P
317 #define TARGET_CLASS_LIKELY_SPILLED_P visium_class_likely_spilled_p
319 #undef TARGET_LEGITIMIZE_ADDRESS
320 #define TARGET_LEGITIMIZE_ADDRESS visium_legitimize_address
322 #undef TARGET_OPTION_OVERRIDE
323 #define TARGET_OPTION_OVERRIDE visium_option_override
325 #undef TARGET_INIT_LIBFUNCS
326 #define TARGET_INIT_LIBFUNCS visium_init_libfuncs
328 #undef TARGET_CONDITIONAL_REGISTER_USAGE
329 #define TARGET_CONDITIONAL_REGISTER_USAGE visium_conditional_register_usage
331 #undef TARGET_TRAMPOLINE_INIT
332 #define TARGET_TRAMPOLINE_INIT visium_trampoline_init
334 #undef TARGET_MD_ASM_ADJUST
335 #define TARGET_MD_ASM_ADJUST visium_md_asm_adjust
337 #undef TARGET_FLAGS_REGNUM
338 #define TARGET_FLAGS_REGNUM FLAGS_REGNUM
340 struct gcc_target targetm
= TARGET_INITIALIZER
;
344 const pass_data pass_data_visium_reorg
=
348 OPTGROUP_NONE
, /* optinfo_flags */
349 TV_MACH_DEP
, /* tv_id */
350 0, /* properties_required */
351 0, /* properties_provided */
352 0, /* properties_destroyed */
353 0, /* todo_flags_start */
354 0, /* todo_flags_finish */
357 class pass_visium_reorg
: public rtl_opt_pass
360 pass_visium_reorg(gcc::context
*ctxt
)
361 : rtl_opt_pass(pass_data_visium_reorg
, ctxt
)
364 /* opt_pass methods: */
365 virtual unsigned int execute (function
*)
367 return visium_reorg ();
370 }; // class pass_work_around_errata
375 make_pass_visium_reorg (gcc::context
*ctxt
)
377 return new pass_visium_reorg (ctxt
);
380 /* Options override for Visium. */
383 visium_option_override (void)
386 warning (OPT_fpic
, "-fpic is not supported");
388 warning (OPT_fPIC
, "-fPIC is not supported");
390 /* MCM is the default in the GR5/GR6 era. */
391 target_flags
|= MASK_MCM
;
393 /* FPU is the default with MCM, but don't override an explicit option. */
394 if ((target_flags_explicit
& MASK_FPU
) == 0)
395 target_flags
|= MASK_FPU
;
397 /* The supervisor mode is the default. */
398 if ((target_flags_explicit
& MASK_SV_MODE
) == 0)
399 target_flags
|= MASK_SV_MODE
;
401 /* The GR6 has the Block Move Instructions and an IEEE-compliant FPU. */
402 if (visium_cpu_and_features
== PROCESSOR_GR6
)
404 target_flags
|= MASK_BMI
;
405 if (target_flags
& MASK_FPU
)
406 target_flags
|= MASK_FPU_IEEE
;
409 /* Set -mtune from -mcpu if not specified. */
410 if (!global_options_set
.x_visium_cpu
)
411 visium_cpu
= visium_cpu_and_features
;
413 /* Align functions on 256-byte (32-quadword) for GR5 and 64-byte (8-quadword)
414 boundaries for GR6 so they start a new burst mode window. */
415 if (align_functions
== 0)
417 if (visium_cpu
== PROCESSOR_GR6
)
418 align_functions
= 64;
420 align_functions
= 256;
422 /* Allow the size of compilation units to double because of inlining.
423 In practice the global size of the object code is hardly affected
424 because the additional instructions will take up the padding. */
425 maybe_set_param_value (PARAM_INLINE_UNIT_GROWTH
, 100,
426 global_options
.x_param_values
,
427 global_options_set
.x_param_values
);
430 /* Likewise for loops. */
431 if (align_loops
== 0)
433 if (visium_cpu
== PROCESSOR_GR6
)
438 /* But not if they are too far away from a 256-byte boundary. */
439 align_loops_max_skip
= 31;
443 /* Align all jumps on quadword boundaries for the burst mode, and even
444 on 8-quadword boundaries for GR6 so they start a new window. */
445 if (align_jumps
== 0)
447 if (visium_cpu
== PROCESSOR_GR6
)
453 /* We register a machine-specific pass. This pass must be scheduled as
454 late as possible so that we have the (essentially) final form of the
455 insn stream to work on. Registering the pass must be done at start up.
456 It's convenient to do it here. */
457 opt_pass
*visium_reorg_pass
= make_pass_visium_reorg (g
);
458 struct register_pass_info insert_pass_visium_reorg
=
460 visium_reorg_pass
, /* pass */
461 "dbr", /* reference_pass_name */
462 1, /* ref_pass_instance_number */
463 PASS_POS_INSERT_AFTER
/* po_op */
465 register_pass (&insert_pass_visium_reorg
);
468 /* Register the Visium-specific libfuncs with the middle-end. */
471 visium_init_libfuncs (void)
474 long_int_memcpy_libfunc
= init_one_libfunc ("__long_int_memcpy");
475 wrd_memcpy_libfunc
= init_one_libfunc ("__wrd_memcpy");
476 byt_memcpy_libfunc
= init_one_libfunc ("__byt_memcpy");
478 long_int_memset_libfunc
= init_one_libfunc ("__long_int_memset");
479 wrd_memset_libfunc
= init_one_libfunc ("__wrd_memset");
480 byt_memset_libfunc
= init_one_libfunc ("__byt_memset");
482 set_trampoline_parity_libfunc
= init_one_libfunc ("__set_trampoline_parity");
485 /* Return the number of instructions that can issue on the same cycle. */
488 visium_issue_rate (void)
503 /* Return the adjusted PRIORITY of INSN. */
506 visium_adjust_priority (rtx_insn
*insn
, int priority
)
508 /* On the GR5, we slightly increase the priority of writes in order to avoid
509 scheduling a read on the next cycle. This is necessary in addition to the
510 associated insn reservation because there are no data dependencies.
511 We also slightly increase the priority of reads from ROM in order to group
512 them as much as possible. These reads are a bit problematic because they
513 conflict with the instruction fetches, i.e. the data and instruction buses
514 tread on each other's toes when they are executed. */
515 if (visium_cpu
== PROCESSOR_GR5
518 && recog_memoized (insn
) >= 0)
520 enum attr_type attr_type
= get_attr_type (insn
);
521 if (attr_type
== TYPE_REG_MEM
522 || (attr_type
== TYPE_MEM_REG
523 && MEM_READONLY_P (SET_SRC (PATTERN (insn
)))))
530 /* Adjust the cost of a scheduling dependency. Return the new cost of
531 a dependency LINK of INSN on DEP_INSN. COST is the current cost. */
534 visium_adjust_cost (rtx_insn
*insn
, int dep_type
, rtx_insn
*dep_insn
, int cost
,
537 enum attr_type attr_type
;
539 /* Don't adjust costs for true dependencies as they are described with
540 bypasses. But we make an exception for the first scheduling pass to
541 help the subsequent postreload compare elimination pass. */
542 if (dep_type
== REG_DEP_TRUE
)
544 if (!reload_completed
545 && recog_memoized (insn
) >= 0
546 && get_attr_type (insn
) == TYPE_CMP
)
548 rtx pat
= PATTERN (insn
);
549 gcc_assert (GET_CODE (pat
) == SET
);
550 rtx src
= SET_SRC (pat
);
552 /* Only the branches can be modified by the postreload compare
553 elimination pass, not the cstores because they accept only
554 unsigned comparison operators and they are eliminated if
555 one of the operands is zero. */
556 if (GET_CODE (src
) == IF_THEN_ELSE
557 && XEXP (XEXP (src
, 0), 1) == const0_rtx
558 && recog_memoized (dep_insn
) >= 0)
560 enum attr_type dep_attr_type
= get_attr_type (dep_insn
);
562 /* The logical instructions use CCmode and thus work with any
563 comparison operator, whereas the arithmetic instructions use
564 CC_NOOVmode and thus work with only a small subset. */
565 if (dep_attr_type
== TYPE_LOGIC
566 || (dep_attr_type
== TYPE_ARITH
567 && visium_noov_operator (XEXP (src
, 0),
568 GET_MODE (XEXP (src
, 0)))))
576 if (recog_memoized (insn
) < 0)
579 attr_type
= get_attr_type (insn
);
581 /* Anti dependency: DEP_INSN reads a register that INSN writes some
583 if (dep_type
== REG_DEP_ANTI
)
585 /* On the GR5, the latency of FP instructions needs to be taken into
586 account for every dependency involving a write. */
587 if (attr_type
== TYPE_REG_FP
&& visium_cpu
== PROCESSOR_GR5
)
590 rtx pat
= PATTERN (insn
);
591 rtx dep_pat
= PATTERN (dep_insn
);
593 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
594 /* If this happens, we have to extend this to schedule
595 optimally. Return 0 for now. */
598 if (reg_mentioned_p (SET_DEST (pat
), SET_SRC (dep_pat
)))
600 if (recog_memoized (dep_insn
) < 0)
603 switch (get_attr_type (dep_insn
))
611 /* A fload can't be issued until a preceding arithmetic
612 operation has finished if the target of the fload is
613 any of the sources (or destination) of the arithmetic
614 operation. Note that the latency may be (much)
615 greater than this if the preceding instruction
616 concerned is in a queue. */
617 return insn_default_latency (dep_insn
);
625 /* On the GR6, we try to make sure that the link register is restored
626 sufficiently ahead of the return as to yield a correct prediction
627 from the branch predictor. By default there is no true dependency
628 but an anti dependency between them, so we simply reuse it. */
629 else if (attr_type
== TYPE_RET
&& visium_cpu
== PROCESSOR_GR6
)
631 rtx dep_pat
= PATTERN (dep_insn
);
632 if (GET_CODE (dep_pat
) == SET
633 && REG_P (SET_DEST (dep_pat
))
634 && REGNO (SET_DEST (dep_pat
)) == LINK_REGNUM
)
638 /* For other anti dependencies, the cost is 0. */
642 /* Output dependency: DEP_INSN writes a register that INSN writes some
644 else if (dep_type
== REG_DEP_OUTPUT
)
646 /* On the GR5, the latency of FP instructions needs to be taken into
647 account for every dependency involving a write. */
648 if (attr_type
== TYPE_REG_FP
&& visium_cpu
== PROCESSOR_GR5
)
651 rtx pat
= PATTERN (insn
);
652 rtx dep_pat
= PATTERN (dep_insn
);
654 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
655 /* If this happens, we have to extend this to schedule
656 optimally. Return 0 for now. */
659 if (reg_mentioned_p (SET_DEST (pat
), SET_DEST (dep_pat
)))
661 if (recog_memoized (dep_insn
) < 0)
664 switch (get_attr_type (dep_insn
))
672 /* A fload can't be issued until a preceding arithmetic
673 operation has finished if the target of the fload is
674 the destination of the arithmetic operation. Note that
675 the latency may be (much) greater than this if the
676 preceding instruction concerned is in a queue. */
677 return insn_default_latency (dep_insn
);
685 /* For other output dependencies, the cost is 0. */
692 /* Handle an "interrupt_handler" attribute; arguments as in
693 struct attribute_spec.handler. */
696 visium_handle_interrupt_attr (tree
*node
, tree name
,
697 tree args ATTRIBUTE_UNUSED
,
698 int flags ATTRIBUTE_UNUSED
,
701 if (TREE_CODE (*node
) != FUNCTION_DECL
)
703 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
705 *no_add_attrs
= true;
707 else if (!TARGET_SV_MODE
)
709 error ("an interrupt handler cannot be compiled with -muser-mode");
710 *no_add_attrs
= true;
716 /* Return non-zero if the current function is an interrupt function. */
719 visium_interrupt_function_p (void)
722 lookup_attribute ("interrupt",
723 DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
726 /* Conditionally modify the settings of the register file. */
729 visium_conditional_register_usage (void)
731 /* If the supervisor mode is disabled, mask some general registers. */
734 if (visium_cpu_and_features
== PROCESSOR_GR5
)
736 fixed_regs
[24] = call_used_regs
[24] = 1;
737 fixed_regs
[25] = call_used_regs
[25] = 1;
738 fixed_regs
[26] = call_used_regs
[26] = 1;
739 fixed_regs
[27] = call_used_regs
[27] = 1;
740 fixed_regs
[28] = call_used_regs
[28] = 1;
741 call_really_used_regs
[24] = 0;
742 call_really_used_regs
[25] = 0;
743 call_really_used_regs
[26] = 0;
744 call_really_used_regs
[27] = 0;
745 call_really_used_regs
[28] = 0;
748 fixed_regs
[31] = call_used_regs
[31] = 1;
749 call_really_used_regs
[31] = 0;
751 /* We also need to change the long-branch register. */
752 if (visium_cpu_and_features
== PROCESSOR_GR5
)
753 long_branch_regnum
= 20;
755 long_branch_regnum
= 28;
758 /* If the FPU is disabled, mask the FP registers. */
761 for (int i
= FP_FIRST_REGNUM
; i
<= FP_LAST_REGNUM
; i
++)
763 fixed_regs
[i
] = call_used_regs
[i
] = 1;
764 call_really_used_regs
[i
] = 0;
769 /* Prepend to CLOBBERS hard registers that are automatically clobbered for
770 an asm We do this for the FLAGS to maintain source compatibility with
771 the original cc0-based compiler. */
774 visium_md_asm_adjust (vec
<rtx
> &/*outputs*/, vec
<rtx
> &/*inputs*/,
775 vec
<const char *> &/*constraints*/,
776 vec
<rtx
> &clobbers
, HARD_REG_SET
&clobbered_regs
)
778 clobbers
.safe_push (gen_rtx_REG (CCmode
, FLAGS_REGNUM
));
779 SET_HARD_REG_BIT (clobbered_regs
, FLAGS_REGNUM
);
783 /* Return true if X is a legitimate constant for a MODE immediate operand.
784 X is guaranteed to satisfy the CONSTANT_P predicate. */
787 visium_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
788 rtx x ATTRIBUTE_UNUSED
)
793 /* Compute the alignment for a variable. The alignment of an aggregate is
794 set to be at least that of a scalar less than or equal to it in size. */
797 visium_data_alignment (tree type
, unsigned int align
)
799 if (AGGREGATE_TYPE_P (type
)
801 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
&& align
< 32)
803 if (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 32)
806 if (TREE_INT_CST_LOW (TYPE_SIZE (type
)) >= 16 && align
< 16)
813 /* Helper function for HARD_REGNO_RENAME_OK (FROM, TO). Return non-zero if
814 it is OK to rename a hard register FROM to another hard register TO. */
817 visium_hard_regno_rename_ok (unsigned int from ATTRIBUTE_UNUSED
,
820 /* If the function doesn't save LR, then the long-branch register will be
821 used for long branches so we need to know whether it is live before the
822 frame layout is computed. */
823 if (!current_function_saves_lr () && to
== long_branch_regnum
)
826 /* Interrupt functions can only use registers that have already been
827 saved by the prologue, even if they would normally be call-clobbered. */
829 && !df_regs_ever_live_p (to
)
830 && visium_interrupt_function_p ())
836 /* Return true if it is ok to do sibling call optimization for the specified
837 call expression EXP. DECL will be the called function, or NULL if this
838 is an indirect call. */
841 visium_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
842 tree exp ATTRIBUTE_UNUSED
)
844 return !visium_interrupt_function_p ();
847 /* Prepare operands for a move define_expand in MODE. */
850 prepare_move_operands (rtx
*operands
, enum machine_mode mode
)
852 /* If the output is not a register, the input must be. */
853 if (GET_CODE (operands
[0]) == MEM
&& !reg_or_0_operand (operands
[1], mode
))
854 operands
[1] = force_reg (mode
, operands
[1]);
857 /* Return true if the operands are valid for a simple move insn. */
860 ok_for_simple_move_operands (rtx
*operands
, enum machine_mode mode
)
862 /* One of the operands must be a register. */
863 if (!register_operand (operands
[0], mode
)
864 && !reg_or_0_operand (operands
[1], mode
))
867 /* Once the flags are exposed, no simple moves between integer registers. */
868 if (visium_flags_exposed
869 && gpc_reg_operand (operands
[0], mode
)
870 && gpc_reg_operand (operands
[1], mode
))
876 /* Return true if the operands are valid for a simple move strict insn. */
879 ok_for_simple_move_strict_operands (rtx
*operands
, enum machine_mode mode
)
881 /* Once the flags are exposed, no simple moves between integer registers.
882 Note that, in QImode only, a zero source counts as an integer register
883 since it will be emitted as r0. */
884 if (visium_flags_exposed
885 && gpc_reg_operand (operands
[0], mode
)
886 && (gpc_reg_operand (operands
[1], mode
)
887 || (mode
== QImode
&& operands
[1] == const0_rtx
)))
893 /* Return true if the operands are valid for a simple arithmetic or logical
897 ok_for_simple_arith_logic_operands (rtx
*, enum machine_mode
)
899 /* Once the flags are exposed, no simple arithmetic or logical operations
900 between integer registers. */
901 return !visium_flags_exposed
;
904 /* Return non-zero if a branch or call instruction will be emitting a nop
905 into its delay slot. */
908 empty_delay_slot (rtx_insn
*insn
)
912 /* If no previous instruction (should not happen), return true. */
913 if (PREV_INSN (insn
) == NULL
)
916 seq
= NEXT_INSN (PREV_INSN (insn
));
917 if (GET_CODE (PATTERN (seq
)) == SEQUENCE
)
923 /* Wrapper around single_set which returns the first SET of a pair if the
924 second SET is to the flags register. */
927 single_set_and_flags (rtx_insn
*insn
)
929 if (multiple_sets (insn
))
931 rtx pat
= PATTERN (insn
);
932 if (XVECLEN (pat
, 0) == 2
933 && GET_CODE (XVECEXP (pat
, 0, 1)) == SET
934 && REG_P (SET_DEST (XVECEXP (pat
, 0, 1)))
935 && REGNO (SET_DEST (XVECEXP (pat
, 0, 1))) == FLAGS_REGNUM
)
936 return XVECEXP (pat
, 0, 0);
939 return single_set (insn
);
942 /* This is called with OUT_INSN an instruction setting a (base) register
943 and IN_INSN a read or a write. Return 1 if these instructions together
944 constitute a pipeline hazard.
946 On the original architecture, a pipeline data hazard occurs when the Dest
947 of one instruction becomes the SrcA for an immediately following READ or
948 WRITE instruction with a non-zero index (indexing occurs at the decode
949 stage and so a NOP must be inserted in-between for this to work).
956 On the MCM, the non-zero index condition is lifted but the hazard is
957 patched up by the hardware through the injection of wait states:
962 We nevertheless try to schedule instructions around this. */
965 gr5_hazard_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
967 rtx out_set
, in_set
, dest
, memexpr
;
968 unsigned int out_reg
, in_reg
;
970 /* A CALL is storage register class, but the link register is of no
972 if (GET_CODE (out_insn
) == CALL_INSN
)
975 out_set
= single_set_and_flags (out_insn
);
976 dest
= SET_DEST (out_set
);
978 /* Should be no stall/hazard if OUT_INSN is MEM := ???. This only
979 occurs prior to reload. */
980 if (GET_CODE (dest
) == MEM
)
983 if (GET_CODE (dest
) == STRICT_LOW_PART
)
984 dest
= XEXP (dest
, 0);
985 if (GET_CODE (dest
) == SUBREG
)
986 dest
= SUBREG_REG (dest
);
987 out_reg
= REGNO (dest
);
989 in_set
= single_set_and_flags (in_insn
);
991 /* If IN_INSN is MEM := MEM, it's the source that counts. */
992 if (GET_CODE (SET_SRC (in_set
)) == MEM
)
993 memexpr
= XEXP (SET_SRC (in_set
), 0);
995 memexpr
= XEXP (SET_DEST (in_set
), 0);
997 if (GET_CODE (memexpr
) == PLUS
)
999 memexpr
= XEXP (memexpr
, 0);
1000 if (GET_CODE (memexpr
) == SUBREG
)
1001 in_reg
= REGNO (SUBREG_REG (memexpr
));
1003 in_reg
= REGNO (memexpr
);
1005 if (in_reg
== out_reg
)
1008 else if (TARGET_MCM
)
1010 if (GET_CODE (memexpr
) == STRICT_LOW_PART
)
1011 memexpr
= XEXP (memexpr
, 0);
1012 if (GET_CODE (memexpr
) == SUBREG
)
1013 memexpr
= SUBREG_REG (memexpr
);
1014 in_reg
= REGNO (memexpr
);
1016 if (in_reg
== out_reg
)
1023 /* Return true if INSN is an empty asm instruction. */
1026 empty_asm_p (rtx insn
)
1028 rtx body
= PATTERN (insn
);
1031 if (GET_CODE (body
) == ASM_INPUT
)
1032 templ
= XSTR (body
, 0);
1033 else if (asm_noperands (body
) >= 0)
1034 templ
= decode_asm_operands (body
, NULL
, NULL
, NULL
, NULL
, NULL
);
1038 return (templ
&& templ
[0] == '\0');
1041 /* Insert a NOP immediately before INSN wherever there is a pipeline hazard.
1042 LAST_REG records the register set in the last insn and LAST_INSN_CALL
1043 records whether the last insn was a call insn. */
1046 gr5_avoid_hazard (rtx_insn
*insn
, unsigned int *last_reg
, bool *last_insn_call
)
1048 unsigned int dest_reg
= 0;
1051 switch (GET_CODE (insn
))
1055 *last_insn_call
= true;
1059 /* If this is an empty asm, just skip it. */
1060 if (!empty_asm_p (insn
))
1063 *last_insn_call
= false;
1068 /* If this is an empty asm, just skip it. */
1069 if (empty_asm_p (insn
))
1077 set
= single_set_and_flags (insn
);
1078 if (set
!= NULL_RTX
)
1080 rtx dest
= SET_DEST (set
);
1081 const bool double_p
= GET_MODE_SIZE (GET_MODE (dest
)) > UNITS_PER_WORD
;
1084 if (GET_CODE (SET_SRC (set
)) == MEM
)
1086 memrtx
= XEXP (SET_SRC (set
), 0);
1087 if (GET_CODE (dest
) == STRICT_LOW_PART
)
1088 dest
= XEXP (dest
, 0);
1090 dest_reg
= REGNO (dest
);
1092 /* If this is a DI or DF mode memory to register
1093 copy, then if rd = rs we get
1098 otherwise the order is
1105 unsigned int base_reg
;
1107 if (GET_CODE (memrtx
) == PLUS
)
1108 base_reg
= REGNO (XEXP (memrtx
, 0));
1110 base_reg
= REGNO (memrtx
);
1112 if (dest_reg
!= base_reg
)
1117 else if (GET_CODE (dest
) == MEM
)
1118 memrtx
= XEXP (dest
, 0);
1120 else if (GET_MODE_CLASS (GET_MODE (dest
)) != MODE_CC
)
1122 if (GET_CODE (dest
) == STRICT_LOW_PART
1123 ||GET_CODE (dest
) == ZERO_EXTRACT
)
1124 dest
= XEXP (dest
, 0);
1125 dest_reg
= REGNO (dest
);
1127 if (GET_CODE (SET_SRC (set
)) == REG
)
1129 unsigned int srcreg
= REGNO (SET_SRC (set
));
1131 /* Check for rs := rs, which will be deleted. */
1132 if (srcreg
== dest_reg
)
1135 /* In the case of a DI or DF mode move from register to
1136 register there is overlap if rd = rs + 1 in which case
1137 the order of the copies is reversed :
1142 if (double_p
&& dest_reg
!= srcreg
+ 1)
1147 /* If this is the delay slot of a call insn, any register it sets
1149 if (*last_insn_call
)
1152 /* If the previous insn sets the value of a register, and this insn
1153 uses a base register, check for the pipeline hazard where it is
1154 the same register in each case. */
1155 if (*last_reg
!= 0 && memrtx
!= NULL_RTX
)
1157 unsigned int reg
= 0;
1159 /* Check for an index (original architecture). */
1160 if (GET_CODE (memrtx
) == PLUS
)
1161 reg
= REGNO (XEXP (memrtx
, 0));
1163 /* Check for an MCM target or rs := [rs], in DI or DF mode. */
1164 else if (TARGET_MCM
|| (double_p
&& REGNO (memrtx
) == dest_reg
))
1165 reg
= REGNO (memrtx
);
1167 /* Remove any pipeline hazard by inserting a NOP. */
1168 if (reg
== *last_reg
)
1172 "inserting nop before insn %d\n", INSN_UID (insn
));
1173 emit_insn_after (gen_hazard_nop (), prev_active_insn (insn
));
1174 emit_insn_after (gen_blockage (), insn
);
1178 *last_reg
= dest_reg
;
1181 *last_insn_call
= false;
1184 /* Go through the instruction stream and insert nops where necessary to avoid
1185 pipeline hazards. There are two cases:
1187 1. On the original architecture, it is invalid to set the value of a
1188 (base) register and then use it in an address with a non-zero index
1189 in the next instruction.
1191 2. On the MCM, setting the value of a (base) register and then using
1192 it in address (including with zero index) in the next instruction
1193 will result in a pipeline stall of 3 cycles. */
1196 gr5_hazard_avoidance (void)
1198 unsigned int last_reg
= 0;
1199 bool last_insn_call
= false;
1202 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1205 rtx pat
= PATTERN (insn
);
1207 if (GET_CODE (pat
) == SEQUENCE
)
1209 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
1210 gr5_avoid_hazard (as_a
<rtx_insn
*> (XVECEXP (pat
, 0, i
)),
1211 &last_reg
, &last_insn_call
);
1214 else if (GET_CODE (insn
) == CALL_INSN
)
1216 /* This call is going to get a nop in its delay slot. */
1218 last_insn_call
= false;
1222 gr5_avoid_hazard (insn
, &last_reg
, &last_insn_call
);
1225 else if (GET_CODE (insn
) == BARRIER
)
1229 /* Perform a target-specific pass over the instruction stream. The compiler
1230 will run it at all optimization levels, just after the point at which it
1231 normally does delayed-branch scheduling. */
1236 if (visium_cpu
== PROCESSOR_GR5
)
1237 gr5_hazard_avoidance ();
1241 /* Return true if an argument must be passed by indirect reference. */
1244 visium_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
1245 enum machine_mode mode ATTRIBUTE_UNUSED
,
1247 bool named ATTRIBUTE_UNUSED
)
1249 return type
&& (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
);
1252 /* Define how arguments are passed.
1254 A range of general registers and floating registers is available
1255 for passing arguments. When the class of registers which an
1256 argument would normally use is exhausted, that argument, is passed
1257 in the overflow region of the stack. No argument is split between
1258 registers and stack.
1260 Arguments of type float or _Complex float go in FP registers if FP
1261 hardware is available. If there is no FP hardware, arguments of
1262 type float go in general registers. All other arguments are passed
1263 in general registers. */
1266 visium_function_arg (cumulative_args_t pcum_v
, enum machine_mode mode
,
1267 const_tree type ATTRIBUTE_UNUSED
,
1268 bool named ATTRIBUTE_UNUSED
)
1271 CUMULATIVE_ARGS
*ca
= get_cumulative_args (pcum_v
);
1273 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1274 if (mode
== VOIDmode
)
1277 /* Scalar or complex single precision floating point arguments are returned
1278 in floating registers. */
1280 && ((GET_MODE_CLASS (mode
) == MODE_FLOAT
1281 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
)
1282 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
1283 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
* 2)))
1285 if (ca
->frcount
+ size
<= MAX_ARGS_IN_FP_REGISTERS
)
1286 return gen_rtx_REG (mode
, FP_ARG_FIRST
+ ca
->frcount
);
1291 if (ca
->grcount
+ size
<= MAX_ARGS_IN_GP_REGISTERS
)
1292 return gen_rtx_REG (mode
, ca
->grcount
+ GP_ARG_FIRST
);
1297 /* Update the summarizer variable pointed to by PCUM_V to advance past an
1298 argument in the argument list. The values MODE, TYPE and NAMED describe
1299 that argument. Once this is done, the variable CUM is suitable for
1300 analyzing the _following_ argument with visium_function_arg. */
1303 visium_function_arg_advance (cumulative_args_t pcum_v
,
1304 enum machine_mode mode
,
1305 const_tree type ATTRIBUTE_UNUSED
,
1308 int size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1310 CUMULATIVE_ARGS
*ca
= get_cumulative_args (pcum_v
);
1312 /* Scalar or complex single precision floating point arguments are returned
1313 in floating registers. */
1315 && ((GET_MODE_CLASS (mode
) == MODE_FLOAT
1316 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
)
1317 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
1318 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
* 2)))
1320 if (ca
->frcount
+ size
<= MAX_ARGS_IN_FP_REGISTERS
)
1321 ca
->frcount
+= size
;
1325 ca
->frcount
= MAX_ARGS_IN_FP_REGISTERS
;
1330 /* Everything else goes in a general register, if enough are
1332 if (ca
->grcount
+ size
<= MAX_ARGS_IN_GP_REGISTERS
)
1333 ca
->grcount
+= size
;
1337 ca
->grcount
= MAX_ARGS_IN_GP_REGISTERS
;
1342 ca
->stack_words
+= stack_size
;
1345 /* Specify whether to return the return value in memory. */
1348 visium_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1350 return (AGGREGATE_TYPE_P (type
) || TREE_CODE (type
) == VECTOR_TYPE
);
1353 /* Define how scalar values are returned. */
1356 visium_function_value_1 (enum machine_mode mode
)
1358 /* Scalar or complex single precision floating point values
1359 are returned in floating register f1. */
1361 && ((GET_MODE_CLASS (mode
) == MODE_FLOAT
1362 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
)
1363 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
1364 && GET_MODE_SIZE (mode
) <= UNITS_PER_HWFPVALUE
* 2)))
1365 return gen_rtx_REG (mode
, FP_RETURN_REGNUM
);
1367 /* All others are returned in r1. */
1368 return gen_rtx_REG (mode
, RETURN_REGNUM
);
1371 /* Return an RTX representing the place where a function returns or receives
1372 a value of data type RET_TYPE. */
1375 visium_function_value (const_tree ret_type
,
1376 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1377 bool outgoing ATTRIBUTE_UNUSED
)
1379 return visium_function_value_1 (TYPE_MODE (ret_type
));
1382 /* Return an RTX representing the place where the library function result will
1386 visium_libcall_value (enum machine_mode mode
, const_rtx fun ATTRIBUTE_UNUSED
)
1388 return visium_function_value_1 (mode
);
1391 /* Store the anonymous register arguments into the stack so that all the
1392 arguments appear to have been passed consecutively on the stack. */
1395 visium_setup_incoming_varargs (cumulative_args_t pcum_v
,
1396 enum machine_mode mode
,
1398 int *pretend_size ATTRIBUTE_UNUSED
,
1401 cumulative_args_t local_args_so_far
;
1402 CUMULATIVE_ARGS local_copy
;
1403 CUMULATIVE_ARGS
*locargs
;
1404 int gp_saved
, fp_saved
, size
;
1406 /* Create an internal cumulative_args_t pointer to internally define
1407 storage to ensure calling TARGET_FUNCTION_ARG_ADVANCE does not
1408 make global changes. */
1409 local_args_so_far
.p
= &local_copy
;
1410 locargs
= get_cumulative_args (pcum_v
);
1413 local_args_so_far
.magic
= CUMULATIVE_ARGS_MAGIC
;
1416 local_copy
.grcount
= locargs
->grcount
;
1417 local_copy
.frcount
= locargs
->frcount
;
1418 local_copy
.stack_words
= locargs
->stack_words
;
1420 /* The caller has advanced ARGS_SO_FAR up to, but not beyond, the last named
1421 argument. Advance a local copy of ARGS_SO_FAR past the last "real" named
1422 argument, to find out how many registers are left over. */
1423 TARGET_FUNCTION_ARG_ADVANCE (local_args_so_far
, mode
, type
, 1);
1425 /* Find how many registers we need to save. */
1426 locargs
= get_cumulative_args (local_args_so_far
);
1427 gp_saved
= MAX_ARGS_IN_GP_REGISTERS
- locargs
->grcount
;
1428 fp_saved
= (TARGET_FPU
? MAX_ARGS_IN_FP_REGISTERS
- locargs
->frcount
: 0);
1429 size
= (gp_saved
* UNITS_PER_WORD
) + (fp_saved
* UNITS_PER_HWFPVALUE
);
1431 if (!no_rtl
&& size
> 0)
1433 /* To avoid negative offsets, which are not valid addressing modes on
1434 the Visium, we create a base register for the pretend args. */
1437 plus_constant (Pmode
, virtual_incoming_args_rtx
, -size
));
1442 = gen_rtx_MEM (BLKmode
,
1443 plus_constant (Pmode
,
1445 fp_saved
* UNITS_PER_HWFPVALUE
));
1446 MEM_NOTRAP_P (mem
) = 1;
1447 set_mem_alias_set (mem
, get_varargs_alias_set ());
1448 move_block_from_reg (locargs
->grcount
+ GP_ARG_FIRST
, mem
, gp_saved
);
1453 rtx mem
= gen_rtx_MEM (BLKmode
, ptr
);
1454 MEM_NOTRAP_P (mem
) = 1;
1455 set_mem_alias_set (mem
, get_varargs_alias_set ());
1456 gcc_assert (UNITS_PER_WORD
== UNITS_PER_HWFPVALUE
);
1457 move_block_from_reg (locargs
->frcount
+ FP_ARG_FIRST
, mem
, fp_saved
);
1461 visium_reg_parm_save_area_size
= size
;
1464 /* Define the `__builtin_va_list' type for the ABI. */
1467 visium_build_builtin_va_list (void)
1469 tree f_ovfl
, f_gbase
, f_fbase
, f_gbytes
, f_fbytes
, record
;
1471 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
1472 f_ovfl
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
1473 get_identifier ("__overflow_argptr"), ptr_type_node
);
1474 f_gbase
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
1475 get_identifier ("__gpr_base"), ptr_type_node
);
1476 f_fbase
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
1477 get_identifier ("__fpr_base"), ptr_type_node
);
1478 f_gbytes
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
1479 get_identifier ("__gpr_bytes"),
1480 short_unsigned_type_node
);
1481 f_fbytes
= build_decl (BUILTINS_LOCATION
, FIELD_DECL
,
1482 get_identifier ("__fpr_bytes"),
1483 short_unsigned_type_node
);
1485 DECL_FIELD_CONTEXT (f_ovfl
) = record
;
1486 DECL_FIELD_CONTEXT (f_gbase
) = record
;
1487 DECL_FIELD_CONTEXT (f_fbase
) = record
;
1488 DECL_FIELD_CONTEXT (f_gbytes
) = record
;
1489 DECL_FIELD_CONTEXT (f_fbytes
) = record
;
1490 TYPE_FIELDS (record
) = f_ovfl
;
1491 TREE_CHAIN (f_ovfl
) = f_gbase
;
1492 TREE_CHAIN (f_gbase
) = f_fbase
;
1493 TREE_CHAIN (f_fbase
) = f_gbytes
;
1494 TREE_CHAIN (f_gbytes
) = f_fbytes
;
1495 layout_type (record
);
1500 /* Implement `va_start' for varargs and stdarg. */
1503 visium_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
1505 const CUMULATIVE_ARGS
*ca
= &crtl
->args
.info
;
1506 int gp_saved
= MAX_ARGS_IN_GP_REGISTERS
- ca
->grcount
;
1507 int fp_saved
= (TARGET_FPU
? MAX_ARGS_IN_FP_REGISTERS
- ca
->frcount
: 0);
1508 int named_stack_size
= ca
->stack_words
* UNITS_PER_WORD
, offset
;
1509 tree f_ovfl
, f_gbase
, f_fbase
, f_gbytes
, f_fbytes
;
1510 tree ovfl
, gbase
, gbytes
, fbase
, fbytes
, t
;
1512 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
1513 f_gbase
= TREE_CHAIN (f_ovfl
);
1514 f_fbase
= TREE_CHAIN (f_gbase
);
1515 f_gbytes
= TREE_CHAIN (f_fbase
);
1516 f_fbytes
= TREE_CHAIN (f_gbytes
);
1517 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
, NULL_TREE
);
1518 gbase
= build3 (COMPONENT_REF
, TREE_TYPE (f_gbase
), valist
, f_gbase
,
1520 fbase
= build3 (COMPONENT_REF
, TREE_TYPE (f_fbase
), valist
, f_fbase
,
1522 gbytes
= build3 (COMPONENT_REF
, TREE_TYPE (f_gbytes
), valist
, f_gbytes
,
1524 fbytes
= build3 (COMPONENT_REF
, TREE_TYPE (f_fbytes
), valist
, f_fbytes
,
1527 /* Store the stacked vararg pointer in the OVFL member. */
1528 t
= make_tree (TREE_TYPE (ovfl
), virtual_incoming_args_rtx
);
1529 t
= fold_build_pointer_plus_hwi (t
, named_stack_size
);
1530 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), ovfl
, t
);
1531 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
1533 /* Store the base address of the GPR save area into GBASE. */
1534 t
= make_tree (TREE_TYPE (gbase
), virtual_incoming_args_rtx
);
1535 offset
= MAX_ARGS_IN_GP_REGISTERS
* UNITS_PER_WORD
;
1536 t
= fold_build_pointer_plus_hwi (t
, -offset
);
1537 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gbase
), gbase
, t
);
1538 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
1540 /* Store the base address of the FPR save area into FBASE. */
1543 t
= make_tree (TREE_TYPE (fbase
), virtual_incoming_args_rtx
);
1544 offset
= gp_saved
* UNITS_PER_WORD
1545 + MAX_ARGS_IN_FP_REGISTERS
* UNITS_PER_HWFPVALUE
;
1546 t
= fold_build_pointer_plus_hwi (t
, -offset
);
1547 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fbase
), fbase
, t
);
1548 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
1551 /* Fill in the GBYTES member. */
1552 t
= build2 (MODIFY_EXPR
, TREE_TYPE (gbytes
), gbytes
,
1553 size_int (gp_saved
* UNITS_PER_WORD
));
1554 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
1556 /* Fill in the FBYTES member. */
1557 t
= build2 (MODIFY_EXPR
, TREE_TYPE (fbytes
),
1558 fbytes
, size_int (fp_saved
* UNITS_PER_HWFPVALUE
));
1559 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
1562 /* Implement `va_arg'. */
1565 visium_gimplify_va_arg (tree valist
, tree type
, gimple_seq
*pre_p
,
1568 tree f_ovfl
, f_gbase
, f_fbase
, f_gbytes
, f_fbytes
;
1569 tree ovfl
, base
, bytes
;
1570 HOST_WIDE_INT size
, rsize
;
1571 const bool by_reference_p
1572 = pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
1573 const bool float_reg_arg_p
1574 = (TARGET_FPU
&& !by_reference_p
1575 && ((GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_FLOAT
1576 && GET_MODE_SIZE (TYPE_MODE (type
)) <= UNITS_PER_HWFPVALUE
)
1577 || (GET_MODE_CLASS (TYPE_MODE (type
)) == MODE_COMPLEX_FLOAT
1578 && (GET_MODE_SIZE (TYPE_MODE (type
))
1579 <= UNITS_PER_HWFPVALUE
* 2))));
1580 const int max_save_area_size
1581 = (float_reg_arg_p
? MAX_ARGS_IN_FP_REGISTERS
* UNITS_PER_HWFPVALUE
1582 : MAX_ARGS_IN_GP_REGISTERS
* UNITS_PER_WORD
);
1584 tree lab_false
, lab_over
, addr
;
1585 tree ptrtype
= build_pointer_type (type
);
1589 t
= visium_gimplify_va_arg (valist
, ptrtype
, pre_p
, post_p
);
1590 return build_va_arg_indirect_ref (t
);
1593 size
= int_size_in_bytes (type
);
1594 rsize
= (size
+ UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
1595 f_ovfl
= TYPE_FIELDS (va_list_type_node
);
1596 f_gbase
= TREE_CHAIN (f_ovfl
);
1597 f_fbase
= TREE_CHAIN (f_gbase
);
1598 f_gbytes
= TREE_CHAIN (f_fbase
);
1599 f_fbytes
= TREE_CHAIN (f_gbytes
);
1601 /* We maintain separate pointers and offsets for floating-point and
1602 general registers, but we need similar code in both cases.
1606 BYTES be the number of unused bytes in the register save area.
1607 BASE be the base address of the register save area.
1608 OFFS be the current offset into the register save area. Either
1609 MAX_ARGS_IN_GP_REGISTERS * UNITS_PER_WORD - bytes or
1610 MAX_ARGS_IN_FP_REGISTERS * UNITS_PER_HWFPVALUE - bytes
1611 depending upon whether the argument is in general or floating
1613 ADDR_RTX be the address of the argument.
1614 RSIZE be the size in bytes of the argument.
1615 OVFL be the pointer to the stack overflow area.
1617 The code we want is:
1619 1: if (bytes >= rsize)
1621 3: addr_rtx = base + offs;
1633 addr
= create_tmp_var (ptr_type_node
, "addr");
1634 lab_false
= create_artificial_label (UNKNOWN_LOCATION
);
1635 lab_over
= create_artificial_label (UNKNOWN_LOCATION
);
1636 if (float_reg_arg_p
)
1637 bytes
= build3 (COMPONENT_REF
, TREE_TYPE (f_fbytes
), unshare_expr (valist
),
1638 f_fbytes
, NULL_TREE
);
1640 bytes
= build3 (COMPONENT_REF
, TREE_TYPE (f_gbytes
), unshare_expr (valist
),
1641 f_gbytes
, NULL_TREE
);
1643 /* [1] Emit code to branch if bytes < rsize. */
1644 t
= fold_convert (TREE_TYPE (bytes
), size_int (rsize
));
1645 t
= build2 (LT_EXPR
, boolean_type_node
, bytes
, t
);
1646 u
= build1 (GOTO_EXPR
, void_type_node
, lab_false
);
1647 t
= build3 (COND_EXPR
, void_type_node
, t
, u
, NULL_TREE
);
1648 gimplify_and_add (t
, pre_p
);
1650 /* [3] Emit code for: addr_rtx = base + offs, where
1651 offs = max_save_area_size - bytes. */
1652 t
= fold_convert (sizetype
, bytes
);
1653 offs
= build2 (MINUS_EXPR
, sizetype
, size_int (max_save_area_size
), t
);
1654 if (float_reg_arg_p
)
1655 base
= build3 (COMPONENT_REF
, TREE_TYPE (f_fbase
), valist
, f_fbase
,
1658 base
= build3 (COMPONENT_REF
, TREE_TYPE (f_gbase
), valist
, f_gbase
,
1661 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (base
), base
, offs
);
1662 t
= build2 (MODIFY_EXPR
, void_type_node
, addr
, t
);
1663 gimplify_and_add (t
, pre_p
);
1665 /* [4] Emit code for: bytes -= rsize. */
1666 t
= fold_convert (TREE_TYPE (bytes
), size_int (rsize
));
1667 t
= build2 (MINUS_EXPR
, TREE_TYPE (bytes
), bytes
, t
);
1668 t
= build2 (MODIFY_EXPR
, TREE_TYPE (bytes
), bytes
, t
);
1669 gimplify_and_add (t
, pre_p
);
1671 /* [6] Emit code to branch over the else clause, then the label. */
1672 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
1673 gimplify_and_add (t
, pre_p
);
1674 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
1675 gimplify_and_add (t
, pre_p
);
1677 /* [8] Emit code for: bytes = 0. */
1678 t
= fold_convert (TREE_TYPE (bytes
), size_int (0));
1679 t
= build2 (MODIFY_EXPR
, TREE_TYPE (bytes
), unshare_expr (bytes
), t
);
1680 gimplify_and_add (t
, pre_p
);
1682 /* [9] Emit code for: addr_rtx = ovfl. */
1683 ovfl
= build3 (COMPONENT_REF
, TREE_TYPE (f_ovfl
), valist
, f_ovfl
, NULL_TREE
);
1684 t
= build2 (MODIFY_EXPR
, void_type_node
, addr
, ovfl
);
1685 gimplify_and_add (t
, pre_p
);
1687 /* [10] Emit code for: ovfl += rsize. */
1688 t
= build2 (POINTER_PLUS_EXPR
, TREE_TYPE (ovfl
), ovfl
, size_int (rsize
));
1689 t
= build2 (MODIFY_EXPR
, TREE_TYPE (ovfl
), unshare_expr (ovfl
), t
);
1690 gimplify_and_add (t
, pre_p
);
1691 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
1692 gimplify_and_add (t
, pre_p
);
1693 addr
= fold_convert (ptrtype
, addr
);
1695 return build_va_arg_indirect_ref (addr
);
1698 /* Return true if OP is an offset suitable for use as a displacement in the
1699 address of a memory access in mode MODE. */
1702 rtx_ok_for_offset_p (enum machine_mode mode
, rtx op
)
1704 if (!CONST_INT_P (op
) || INTVAL (op
) < 0)
1710 return INTVAL (op
) <= 31;
1713 return (INTVAL (op
) % 2) == 0 && INTVAL (op
) < 63;
1717 return (INTVAL (op
) % 4) == 0 && INTVAL (op
) < 127;
1721 return (INTVAL (op
) % 4) == 0 && INTVAL (op
) < 123;
1728 /* Return whether X is a legitimate memory address for a memory operand
1731 Legitimate addresses are defined in two variants: a strict variant
1732 and a non-strict one. The STRICT parameter chooses which variant
1733 is desired by the caller.
1735 The strict variant is used in the reload pass. It must be defined
1736 so that any pseudo-register that has not been allocated a hard
1737 register is considered a memory reference. This is because in
1738 contexts where some kind of register is required, a
1739 pseudo-register with no hard register must be rejected. For
1740 non-hard registers, the strict variant should look up the
1741 `reg_renumber' array; it should then proceed using the hard
1742 register number in the array, or treat the pseudo as a memory
1743 reference if the array holds `-1'.
1745 The non-strict variant is used in other passes. It must be
1746 defined to accept all pseudo-registers in every context where some
1747 kind of register is required. */
1750 visium_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1755 /* If X is base+disp, check that we have an appropriate offset. */
1756 if (GET_CODE (x
) == PLUS
)
1758 if (!rtx_ok_for_offset_p (mode
, XEXP (x
, 1)))
1765 /* Now check the base: it must be either a register or a subreg thereof. */
1766 if (GET_CODE (base
) == SUBREG
)
1767 base
= SUBREG_REG (base
);
1771 regno
= REGNO (base
);
1773 /* For the strict variant, the register must be REGNO_OK_FOR_BASE_P. */
1775 return REGNO_OK_FOR_BASE_P (regno
);
1777 /* For the non-strict variant, the register may also be a pseudo. */
1778 return BASE_REGISTER_P (regno
) || regno
>= FIRST_PSEUDO_REGISTER
;
1781 /* Try machine-dependent ways of modifying an illegitimate address
1782 to be legitimate. If we find one, return the new, valid address.
1783 This macro is used in only one place: `memory_address' in explow.c.
1785 OLDX is the address as it was before break_out_memory_refs was called.
1786 In some cases it is useful to look at this to decide what needs to be done.
1788 MODE and WIN are passed so that this macro can use
1789 GO_IF_LEGITIMATE_ADDRESS.
1791 It is always safe for this macro to do nothing. It exists to recognize
1792 opportunities to optimize the output.
1796 memory (reg + <out of range int>)
1800 base_int = <out of range int> & ~mask
1801 ptr_reg = reg + base_int
1802 memory (ptr_reg + <out of range int> - base_int)
1804 Thus ptr_reg is a base register for a range of addresses,
1805 which should help CSE.
1807 For a 1 byte reference mask is 0x1f
1808 for a 2 byte reference mask is 0x3f
1809 For a 4 byte reference mask is 0x7f
1811 This reflects the indexing range of the processor.
1813 For a > 4 byte reference the mask is 0x7f provided all of the words
1814 can be accessed with the base address obtained. Otherwise a mask
1817 On rare occasions an unaligned base register value with an
1818 unaligned offset is generated. Unaligned offsets are left alone for
1822 visium_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1823 enum machine_mode mode
)
1825 if (GET_CODE (x
) == PLUS
1826 && GET_CODE (XEXP (x
, 1)) == CONST_INT
1827 && GET_CODE (XEXP (x
, 0)) == REG
&& mode
!= BLKmode
)
1829 int offset
= INTVAL (XEXP (x
, 1));
1830 int size
= GET_MODE_SIZE (mode
);
1831 int mask
= (size
== 1 ? 0x1f : (size
== 2 ? 0x3f : 0x7f));
1832 int mask1
= (size
== 1 ? 0 : (size
== 2 ? 1 : 3));
1833 int offset_base
= offset
& ~mask
;
1835 /* Check that all of the words can be accessed. */
1836 if (4 < size
&& 0x80 < size
+ offset
- offset_base
)
1837 offset_base
= offset
& ~0x3f;
1838 if (offset_base
!= 0 && offset_base
!= offset
&& (offset
& mask1
) == 0)
1840 rtx ptr_reg
= force_reg (Pmode
,
1841 gen_rtx_PLUS (Pmode
,
1843 GEN_INT (offset_base
)));
1845 return plus_constant (Pmode
, ptr_reg
, offset
- offset_base
);
1852 /* Perform a similar function to visium_legitimize_address, but this time
1853 for reload. Generating new registers is not an option here. Parts
1854 that need reloading are indicated by calling push_reload. */
1857 visium_legitimize_reload_address (rtx x
, enum machine_mode mode
, int opnum
,
1858 int type
, int ind ATTRIBUTE_UNUSED
)
1860 rtx newrtx
, tem
= NULL_RTX
;
1862 if (mode
== BLKmode
)
1865 if (optimize
&& GET_CODE (x
) == PLUS
)
1866 tem
= simplify_binary_operation (PLUS
, GET_MODE (x
), XEXP (x
, 0),
1869 newrtx
= tem
? tem
: x
;
1870 if (GET_CODE (newrtx
) == PLUS
1871 && GET_CODE (XEXP (newrtx
, 1)) == CONST_INT
1872 && GET_CODE (XEXP (newrtx
, 0)) == REG
1873 && BASE_REGISTER_P (REGNO (XEXP (newrtx
, 0))))
1875 int offset
= INTVAL (XEXP (newrtx
, 1));
1876 int size
= GET_MODE_SIZE (mode
);
1877 int mask
= (size
== 1 ? 0x1f : (size
== 2 ? 0x3f : 0x7f));
1878 int mask1
= (size
== 1 ? 0 : (size
== 2 ? 1 : 3));
1879 int offset_base
= offset
& ~mask
;
1881 /* Check that all of the words can be accessed. */
1882 if (4 < size
&& 0x80 < size
+ offset
- offset_base
)
1883 offset_base
= offset
& ~0x3f;
1885 if (offset_base
&& (offset
& mask1
) == 0)
1887 rtx temp
= gen_rtx_PLUS (Pmode
,
1888 XEXP (newrtx
, 0), GEN_INT (offset_base
));
1890 x
= gen_rtx_PLUS (Pmode
, temp
, GEN_INT (offset
- offset_base
));
1891 push_reload (XEXP (x
, 0), 0, &XEXP (x
, 0), 0,
1892 BASE_REG_CLASS
, Pmode
, VOIDmode
, 0, 0, opnum
,
1893 (enum reload_type
) type
);
1901 /* Return the cost of moving data of mode MODE from a register in class FROM to
1902 one in class TO. A value of 2 is the default; other values are interpreted
1903 relative to that. */
1906 visium_register_move_cost (enum machine_mode mode
, reg_class_t from
,
1909 const int numwords
= (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
) ? 1 : 2;
1911 if (from
== MDB
|| to
== MDB
)
1913 else if (from
== MDC
|| to
== MDC
|| (from
== FP_REGS
) != (to
== FP_REGS
))
1914 return 4 * numwords
;
1916 return 2 * numwords
;
1919 /* Return the cost of moving data of mode MODE between a register of class
1920 CLASS and memory. IN is zero if the value is to be written to memory,
1921 non-zero if it is to be read in. This cost is relative to those in
1922 visium_register_move_cost. */
1925 visium_memory_move_cost (enum machine_mode mode
,
1926 reg_class_t to ATTRIBUTE_UNUSED
,
1929 /* Moving data in can be from PROM and this is expensive. */
1932 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
1938 /* Moving data out is mostly to RAM and should be cheaper. */
1941 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
1948 /* Return the relative costs of expression X. */
1951 visium_rtx_costs (rtx x
, machine_mode mode
, int outer_code ATTRIBUTE_UNUSED
,
1952 int opno ATTRIBUTE_UNUSED
, int *total
,
1953 bool speed ATTRIBUTE_UNUSED
)
1955 int code
= GET_CODE (x
);
1960 /* Small integers are as cheap as registers. 4-byte values can
1961 be fetched as immediate constants - let's give that the cost
1962 of an extra insn. */
1963 *total
= COSTS_N_INSNS (!satisfies_constraint_J (x
));
1969 *total
= COSTS_N_INSNS (2);
1975 split_double (x
, &high
, &low
);
1978 (!satisfies_constraint_J (high
) + !satisfies_constraint_J (low
));
1983 *total
= COSTS_N_INSNS (3);
1991 *total
= COSTS_N_INSNS (64);
1993 *total
= COSTS_N_INSNS (32);
1999 /* DImode operations are performed directly on the ALU. */
2001 *total
= COSTS_N_INSNS (2);
2003 *total
= COSTS_N_INSNS (1);
2009 /* DImode operations are performed on the EAM instead. */
2011 *total
= COSTS_N_INSNS (3);
2013 *total
= COSTS_N_INSNS (1);
2017 /* This matches the btst pattern. */
2018 if (GET_CODE (XEXP (x
, 0)) == ZERO_EXTRACT
2019 && XEXP (x
, 1) == const0_rtx
2020 && XEXP (XEXP (x
, 0), 1) == const1_rtx
2021 && satisfies_constraint_K (XEXP (XEXP (x
, 0), 2)))
2022 *total
= COSTS_N_INSNS (1);
2030 /* Split a double move of OPERANDS in MODE. */
2033 visium_split_double_move (rtx
*operands
, enum machine_mode mode
)
2037 /* Check register to register with overlap. */
2038 if (GET_CODE (operands
[0]) == REG
2039 && GET_CODE (operands
[1]) == REG
2040 && REGNO (operands
[0]) == REGNO (operands
[1]) + 1)
2043 /* Check memory to register where the base reg overlaps the destination. */
2044 if (GET_CODE (operands
[0]) == REG
&& GET_CODE (operands
[1]) == MEM
)
2046 rtx op
= XEXP (operands
[1], 0);
2048 if (GET_CODE (op
) == SUBREG
)
2049 op
= SUBREG_REG (op
);
2051 if (GET_CODE (op
) == REG
&& REGNO (op
) == REGNO (operands
[0]))
2054 if (GET_CODE (op
) == PLUS
)
2056 rtx x
= XEXP (op
, 0);
2057 rtx y
= XEXP (op
, 1);
2059 if (GET_CODE (x
) == REG
&& REGNO (x
) == REGNO (operands
[0]))
2062 if (GET_CODE (y
) == REG
&& REGNO (y
) == REGNO (operands
[0]))
2069 operands
[2] = operand_subword (operands
[0], 1, 1, mode
);
2070 operands
[3] = operand_subword (operands
[1], 1, 1, mode
);
2071 operands
[4] = operand_subword (operands
[0], 0, 1, mode
);
2072 operands
[5] = operand_subword (operands
[1], 0, 1, mode
);
2076 operands
[2] = operand_subword (operands
[0], 0, 1, mode
);
2077 operands
[3] = operand_subword (operands
[1], 0, 1, mode
);
2078 operands
[4] = operand_subword (operands
[0], 1, 1, mode
);
2079 operands
[5] = operand_subword (operands
[1], 1, 1, mode
);
2083 /* Split a double addition or subtraction of operands. */
2086 visium_split_double_add (enum rtx_code code
, rtx op0
, rtx op1
, rtx op2
)
2088 rtx op3
= gen_lowpart (SImode
, op0
);
2089 rtx op4
= gen_lowpart (SImode
, op1
);
2091 rtx op6
= gen_highpart (SImode
, op0
);
2092 rtx op7
= (op1
== const0_rtx
? op1
: gen_highpart (SImode
, op1
));
2096 /* If operand #2 is a small constant, then its high part is null. */
2097 if (CONST_INT_P (op2
))
2099 HOST_WIDE_INT val
= INTVAL (op2
);
2103 code
= (code
== MINUS
? PLUS
: MINUS
);
2107 op5
= gen_int_mode (val
, SImode
);
2112 op5
= gen_lowpart (SImode
, op2
);
2113 op8
= gen_highpart (SImode
, op2
);
2116 /* This is the {add,sub,neg}si3_insn_set_flags pattern. */
2117 if (op4
== const0_rtx
)
2118 x
= gen_rtx_NEG (SImode
, op5
);
2120 x
= gen_rtx_fmt_ee (code
, SImode
, op4
, op5
);
2121 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
2122 XVECEXP (pat
, 0, 0) = gen_rtx_SET (op3
, x
);
2123 flags
= gen_rtx_REG (CC_NOOVmode
, FLAGS_REGNUM
);
2124 x
= gen_rtx_COMPARE (CC_NOOVmode
, shallow_copy_rtx (x
), const0_rtx
);
2125 XVECEXP (pat
, 0, 1) = gen_rtx_SET (flags
, x
);
2128 /* This is the plus_[plus_]sltu_flags or minus_[minus_]sltu_flags pattern. */
2129 if (op8
== const0_rtx
)
2132 x
= gen_rtx_fmt_ee (code
, SImode
, op7
, op8
);
2133 x
= gen_rtx_fmt_ee (code
, SImode
, x
, gen_rtx_LTU (SImode
, flags
, const0_rtx
));
2134 pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
2135 XVECEXP (pat
, 0, 0) = gen_rtx_SET (op6
, x
);
2136 flags
= gen_rtx_REG (CCmode
, FLAGS_REGNUM
);
2137 XVECEXP (pat
, 0, 1) = gen_rtx_CLOBBER (VOIDmode
, flags
);
2140 visium_flags_exposed
= true;
2143 /* Expand a copysign of OPERANDS in MODE. */
2146 visium_expand_copysign (rtx
*operands
, enum machine_mode mode
)
2148 rtx op0
= operands
[0];
2149 rtx op1
= operands
[1];
2150 rtx op2
= operands
[2];
2151 rtx mask
= force_reg (SImode
, GEN_INT (0x7fffffff));
2154 /* We manually handle SFmode because the abs and neg instructions of
2155 the FPU on the MCM have a non-standard behavior wrt NaNs. */
2156 gcc_assert (mode
== SFmode
);
2158 /* First get all the non-sign bits of op1. */
2159 if (GET_CODE (op1
) == CONST_DOUBLE
)
2161 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op1
)))
2162 op1
= simplify_unary_operation (ABS
, mode
, op1
, mode
);
2163 if (op1
!= CONST0_RTX (mode
))
2166 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op1
), l
);
2167 op1
= force_reg (SImode
, gen_int_mode (l
, SImode
));
2172 op1
= copy_to_mode_reg (SImode
, gen_lowpart (SImode
, op1
));
2173 op1
= force_reg (SImode
, gen_rtx_AND (SImode
, op1
, mask
));
2176 /* Then get the sign bit of op2. */
2177 mask
= force_reg (SImode
, gen_rtx_NOT (SImode
, mask
));
2178 op2
= copy_to_mode_reg (SImode
, gen_lowpart (SImode
, op2
));
2179 op2
= force_reg (SImode
, gen_rtx_AND (SImode
, op2
, mask
));
2181 /* Finally OR the two values. */
2182 if (op1
== CONST0_RTX (SFmode
))
2185 x
= force_reg (SImode
, gen_rtx_IOR (SImode
, op1
, op2
));
2187 /* And move the result to the destination. */
2188 emit_insn (gen_rtx_SET (op0
, gen_lowpart (SFmode
, x
)));
2191 /* Expand a cstore of OPERANDS in MODE for EQ/NE/LTU/GTU/GEU/LEU. We generate
2192 the result in the C flag and use the ADC/SUBC instructions to write it into
2193 the destination register.
2195 It would also be possible to implement support for LT/GT/LE/GE by means of
2196 the RFLAG instruction followed by some shifts, but this can pessimize the
2200 visium_expand_int_cstore (rtx
*operands
, enum machine_mode mode
)
2202 enum rtx_code code
= GET_CODE (operands
[1]);
2203 rtx op0
= operands
[0], op1
= operands
[2], op2
= operands
[3], sltu
;
2204 bool reverse
= false;
2210 /* We use a special comparison to get the result in the C flag. */
2211 if (op2
!= const0_rtx
)
2212 op1
= force_reg (mode
, gen_rtx_XOR (mode
, op1
, op2
));
2213 op1
= gen_rtx_NOT (mode
, op1
);
2221 /* The result is naturally in the C flag modulo a couple of tricks. */
2222 code
= reverse_condition (code
);
2225 /* ... fall through ... */
2241 /* We need either a single ADC or a SUBC and a PLUS. */
2242 sltu
= gen_rtx_LTU (SImode
, op1
, op2
);
2246 rtx tmp
= copy_to_mode_reg (SImode
, gen_rtx_NEG (SImode
, sltu
));
2247 emit_insn (gen_add3_insn (op0
, tmp
, const1_rtx
));
2250 emit_insn (gen_rtx_SET (op0
, sltu
));
2253 /* Expand a cstore of OPERANDS in MODE for LT/GT/UNGE/UNLE. We generate the
2254 result in the C flag and use the ADC/SUBC instructions to write it into
2255 the destination register. */
2258 visium_expand_fp_cstore (rtx
*operands
,
2259 enum machine_mode mode ATTRIBUTE_UNUSED
)
2261 enum rtx_code code
= GET_CODE (operands
[1]);
2262 rtx op0
= operands
[0], op1
= operands
[2], op2
= operands
[3], slt
;
2263 bool reverse
= false;
2269 /* The result is naturally in the C flag modulo a couple of tricks. */
2270 code
= reverse_condition_maybe_unordered (code
);
2273 /* ... fall through ... */
2289 /* We need either a single ADC or a SUBC and a PLUS. */
2290 slt
= gen_rtx_LT (SImode
, op1
, op2
);
2294 rtx tmp
= copy_to_mode_reg (SImode
, gen_rtx_NEG (SImode
, slt
));
2295 emit_insn (gen_add3_insn (op0
, tmp
, const1_rtx
));
2298 emit_insn (gen_rtx_SET (op0
, slt
));
2301 /* Split a compare-and-store with CODE, operands OP2 and OP3, combined with
2302 operation with OP_CODE, operands OP0 and OP1. */
2305 visium_split_cstore (enum rtx_code op_code
, rtx op0
, rtx op1
,
2306 enum rtx_code code
, rtx op2
, rtx op3
)
2308 enum machine_mode cc_mode
= visium_select_cc_mode (code
, op2
, op3
);
2310 /* If a FP cstore was reversed, then it was originally UNGE/UNLE. */
2311 if (cc_mode
== CCFPEmode
&& (op_code
== NEG
|| op_code
== MINUS
))
2314 rtx flags
= gen_rtx_REG (cc_mode
, FLAGS_REGNUM
);
2315 rtx x
= gen_rtx_COMPARE (cc_mode
, op2
, op3
);
2316 x
= gen_rtx_SET (flags
, x
);
2319 x
= gen_rtx_fmt_ee (code
, SImode
, flags
, const0_rtx
);
2325 x
= gen_rtx_NEG (SImode
, x
);
2329 x
= gen_rtx_fmt_ee (op_code
, SImode
, op1
, x
);
2335 rtx pat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (2));
2336 XVECEXP (pat
, 0, 0) = gen_rtx_SET (op0
, x
);
2337 flags
= gen_rtx_REG (CCmode
, FLAGS_REGNUM
);
2338 XVECEXP (pat
, 0, 1) = gen_rtx_CLOBBER (VOIDmode
, flags
);
2341 visium_flags_exposed
= true;
2344 /* Generate a call to a library function to move BYTES_RTX bytes from SRC with
2345 address SRC_REG to DST with address DST_REG in 4-byte chunks. */
2348 expand_block_move_4 (rtx dst
, rtx dst_reg
, rtx src
, rtx src_reg
, rtx bytes_rtx
)
2350 unsigned HOST_WIDE_INT bytes
= UINTVAL (bytes_rtx
);
2351 unsigned int rem
= bytes
% 4;
2358 emit_move_insn (regno_reg_rtx
[1], dst_reg
);
2359 emit_move_insn (regno_reg_rtx
[2], src_reg
);
2360 emit_move_insn (regno_reg_rtx
[3], bytes_rtx
);
2362 insn
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (8));
2363 XVECEXP (insn
, 0, 0)
2364 = gen_rtx_SET (replace_equiv_address_nv (dst
, regno_reg_rtx
[1]),
2365 replace_equiv_address_nv (src
, regno_reg_rtx
[2]));
2366 XVECEXP (insn
, 0, 1) = gen_rtx_USE (VOIDmode
, regno_reg_rtx
[3]);
2367 for (i
= 1; i
<= 6; i
++)
2368 XVECEXP (insn
, 0, 1 + i
)
2369 = gen_rtx_CLOBBER (VOIDmode
, regno_reg_rtx
[i
]);
2373 emit_library_call (long_int_memcpy_libfunc
, LCT_NORMAL
, VOIDmode
, 3,
2376 convert_to_mode (TYPE_MODE (sizetype
),
2377 GEN_INT (bytes
>> 2),
2378 TYPE_UNSIGNED (sizetype
)),
2379 TYPE_MODE (sizetype
));
2383 dst
= replace_equiv_address_nv (dst
, dst_reg
);
2384 src
= replace_equiv_address_nv (src
, src_reg
);
2389 emit_move_insn (adjust_address_nv (dst
, HImode
, bytes
),
2390 adjust_address_nv (src
, HImode
, bytes
));
2396 emit_move_insn (adjust_address_nv (dst
, QImode
, bytes
),
2397 adjust_address_nv (src
, QImode
, bytes
));
2400 /* Generate a call to a library function to move BYTES_RTX bytes from SRC with
2401 address SRC_REG to DST with address DST_REG in 2-bytes chunks. */
2404 expand_block_move_2 (rtx dst
, rtx dst_reg
, rtx src
, rtx src_reg
, rtx bytes_rtx
)
2406 unsigned HOST_WIDE_INT bytes
= UINTVAL (bytes_rtx
);
2407 unsigned int rem
= bytes
% 2;
2409 emit_library_call (wrd_memcpy_libfunc
, LCT_NORMAL
, VOIDmode
, 3,
2412 convert_to_mode (TYPE_MODE (sizetype
),
2413 GEN_INT (bytes
>> 1),
2414 TYPE_UNSIGNED (sizetype
)),
2415 TYPE_MODE (sizetype
));
2419 dst
= replace_equiv_address_nv (dst
, dst_reg
);
2420 src
= replace_equiv_address_nv (src
, src_reg
);
2423 emit_move_insn (adjust_address_nv (dst
, QImode
, bytes
),
2424 adjust_address_nv (src
, QImode
, bytes
));
2427 /* Generate a call to a library function to move BYTES_RTX bytes from address
2428 SRC_REG to address DST_REG in 1-byte chunks. */
2431 expand_block_move_1 (rtx dst_reg
, rtx src_reg
, rtx bytes_rtx
)
2433 emit_library_call (byt_memcpy_libfunc
, LCT_NORMAL
, VOIDmode
, 3,
2436 convert_to_mode (TYPE_MODE (sizetype
),
2438 TYPE_UNSIGNED (sizetype
)),
2439 TYPE_MODE (sizetype
));
2442 /* Generate a call to a library function to set BYTES_RTX bytes of DST with
2443 address DST_REG to VALUE_RTX in 4-byte chunks. */
2446 expand_block_set_4 (rtx dst
, rtx dst_reg
, rtx value_rtx
, rtx bytes_rtx
)
2448 unsigned HOST_WIDE_INT bytes
= UINTVAL (bytes_rtx
);
2449 unsigned int rem
= bytes
% 4;
2451 value_rtx
= convert_to_mode (Pmode
, value_rtx
, 1);
2452 emit_library_call (long_int_memset_libfunc
, LCT_NORMAL
, VOIDmode
, 3,
2455 convert_to_mode (TYPE_MODE (sizetype
),
2456 GEN_INT (bytes
>> 2),
2457 TYPE_UNSIGNED (sizetype
)),
2458 TYPE_MODE (sizetype
));
2462 dst
= replace_equiv_address_nv (dst
, dst_reg
);
2467 if (CONST_INT_P (value_rtx
))
2469 const unsigned HOST_WIDE_INT value
= UINTVAL (value_rtx
) & 0xff;
2470 emit_move_insn (adjust_address_nv (dst
, HImode
, bytes
),
2471 gen_int_mode ((value
<< 8) | value
, HImode
));
2475 rtx temp
= convert_to_mode (QImode
, value_rtx
, 1);
2476 emit_move_insn (adjust_address_nv (dst
, QImode
, bytes
), temp
);
2477 emit_move_insn (adjust_address_nv (dst
, QImode
, bytes
+ 1), temp
);
2484 emit_move_insn (adjust_address_nv (dst
, QImode
, bytes
),
2485 convert_to_mode (QImode
, value_rtx
, 1));
2488 /* Generate a call to a library function to set BYTES_RTX bytes of DST with
2489 address DST_REG to VALUE_RTX in 2-byte chunks. */
2492 expand_block_set_2 (rtx dst
, rtx dst_reg
, rtx value_rtx
, rtx bytes_rtx
)
2494 unsigned HOST_WIDE_INT bytes
= UINTVAL (bytes_rtx
);
2495 unsigned int rem
= bytes
% 2;
2497 value_rtx
= convert_to_mode (Pmode
, value_rtx
, 1);
2498 emit_library_call (wrd_memset_libfunc
, LCT_NORMAL
, VOIDmode
, 3,
2501 convert_to_mode (TYPE_MODE (sizetype
),
2502 GEN_INT (bytes
>> 1),
2503 TYPE_UNSIGNED (sizetype
)),
2504 TYPE_MODE (sizetype
));
2508 dst
= replace_equiv_address_nv (dst
, dst_reg
);
2511 emit_move_insn (adjust_address_nv (dst
, QImode
, bytes
),
2512 convert_to_mode (QImode
, value_rtx
, 1));
2515 /* Generate a call to a library function to set BYTES_RTX bytes at address
2516 DST_REG to VALUE_RTX in 1-byte chunks. */
2519 expand_block_set_1 (rtx dst_reg
, rtx value_rtx
, rtx bytes_rtx
)
2521 value_rtx
= convert_to_mode (Pmode
, value_rtx
, 1);
2522 emit_library_call (byt_memset_libfunc
, LCT_NORMAL
, VOIDmode
, 3,
2525 convert_to_mode (TYPE_MODE (sizetype
),
2527 TYPE_UNSIGNED (sizetype
)),
2528 TYPE_MODE (sizetype
));
2531 /* Expand string/block move operations.
2533 operands[0] is the pointer to the destination.
2534 operands[1] is the pointer to the source.
2535 operands[2] is the number of bytes to move.
2536 operands[3] is the alignment.
2538 Return 1 upon success, 0 otherwise. */
2541 visium_expand_block_move (rtx
*operands
)
2543 rtx dst
= operands
[0];
2544 rtx src
= operands
[1];
2545 rtx bytes_rtx
= operands
[2];
2546 rtx align_rtx
= operands
[3];
2547 const int align
= INTVAL (align_rtx
);
2548 rtx dst_reg
, src_reg
;
2549 tree dst_expr
, src_expr
;
2551 /* We only handle a fixed number of bytes for now. */
2552 if (!CONST_INT_P (bytes_rtx
) || INTVAL (bytes_rtx
) <= 0)
2555 /* Copy the addresses into scratch registers. */
2556 dst_reg
= copy_addr_to_reg (XEXP (dst
, 0));
2557 src_reg
= copy_addr_to_reg (XEXP (src
, 0));
2559 /* Move the data with the appropriate granularity. */
2561 expand_block_move_4 (dst
, dst_reg
, src
, src_reg
, bytes_rtx
);
2562 else if (align
>= 2)
2563 expand_block_move_2 (dst
, dst_reg
, src
, src_reg
, bytes_rtx
);
2565 expand_block_move_1 (dst_reg
, src_reg
, bytes_rtx
);
2567 /* Since DST and SRC are passed to a libcall, mark the corresponding
2568 tree EXPR as addressable. */
2569 dst_expr
= MEM_EXPR (dst
);
2570 src_expr
= MEM_EXPR (src
);
2572 mark_addressable (dst_expr
);
2574 mark_addressable (src_expr
);
2579 /* Expand string/block set operations.
2581 operands[0] is the pointer to the destination.
2582 operands[1] is the number of bytes to set.
2583 operands[2] is the source value.
2584 operands[3] is the alignment.
2586 Return 1 upon success, 0 otherwise. */
2589 visium_expand_block_set (rtx
*operands
)
2591 rtx dst
= operands
[0];
2592 rtx bytes_rtx
= operands
[1];
2593 rtx value_rtx
= operands
[2];
2594 rtx align_rtx
= operands
[3];
2595 const int align
= INTVAL (align_rtx
);
2599 /* We only handle a fixed number of bytes for now. */
2600 if (!CONST_INT_P (bytes_rtx
) || INTVAL (bytes_rtx
) <= 0)
2603 /* Copy the address into a scratch register. */
2604 dst_reg
= copy_addr_to_reg (XEXP (dst
, 0));
2606 /* Set the data with the appropriate granularity. */
2608 expand_block_set_4 (dst
, dst_reg
, value_rtx
, bytes_rtx
);
2609 else if (align
>= 2)
2610 expand_block_set_2 (dst
, dst_reg
, value_rtx
, bytes_rtx
);
2612 expand_block_set_1 (dst_reg
, value_rtx
, bytes_rtx
);
2614 /* Since DST is passed to a libcall, mark the corresponding
2615 tree EXPR as addressable. */
2616 dst_expr
= MEM_EXPR (dst
);
2618 mark_addressable (dst_expr
);
2623 /* Initialize a trampoline. M_TRAMP is an RTX for the memory block for the
2624 trampoline, FNDECL is the FUNCTION_DECL for the nested function and
2625 STATIC_CHAIN is an RTX for the static chain value that should be passed
2626 to the function when it is called. */
2629 visium_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
2631 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2632 rtx addr
= XEXP (m_tramp
, 0);
2634 /* The trampoline initialization sequence is:
2636 moviu r9,%u FUNCTION
2637 movil r9,%l FUNCTION
2642 We don't use r0 as the destination register of the branch because we want
2643 the Branch Pre-decode Logic of the GR6 to use the Address Load Array to
2644 predict the branch target. */
2646 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (Pmode
, addr
, 0)),
2647 plus_constant (SImode
,
2648 expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
2652 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (Pmode
, addr
, 4)),
2653 plus_constant (SImode
,
2654 expand_and (SImode
, fnaddr
, GEN_INT (0xffff),
2658 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (Pmode
, addr
, 8)),
2659 plus_constant (SImode
,
2660 expand_shift (RSHIFT_EXPR
, SImode
,
2665 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (Pmode
, addr
, 12)),
2666 gen_int_mode (0xff892404, SImode
));
2668 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (Pmode
, addr
, 16)),
2669 plus_constant (SImode
,
2670 expand_and (SImode
, static_chain
,
2671 GEN_INT (0xffff), NULL_RTX
),
2674 emit_library_call (set_trampoline_parity_libfunc
, LCT_NORMAL
, VOIDmode
, 1,
2678 /* Return true if the current function must have and use a frame pointer. */
2681 visium_frame_pointer_required (void)
2683 /* The frame pointer is required if the function isn't leaf to be able to
2684 do manual stack unwinding. */
2688 /* If the stack pointer is dynamically modified in the function, it cannot
2689 serve as the frame pointer. */
2690 if (!crtl
->sp_is_unchanging
)
2693 /* If the function receives nonlocal gotos, it needs to save the frame
2694 pointer in the nonlocal_goto_save_area object. */
2695 if (cfun
->has_nonlocal_label
)
2698 /* The frame also needs to be established in some special cases. */
2699 if (visium_frame_needed
)
2705 /* Profiling support. Just a call to MCOUNT is needed. No labelled counter
2706 location is involved. Proper support for __builtin_return_address is also
2707 required, which is fairly straightforward provided a frame gets created. */
2710 visium_profile_hook (void)
2712 visium_frame_needed
= true;
2713 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "mcount"), LCT_NORMAL
,
2717 /* A C expression whose value is RTL representing the address in a stack frame
2718 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2719 an RTL expression for the address of the stack frame itself.
2721 If you don't define this macro, the default is to return the value of
2722 FRAMEADDR--that is, the stack frame address is also the address of the stack
2723 word that points to the previous frame. */
2726 visium_dynamic_chain_address (rtx frame
)
2728 /* This is the default, but we need to make sure the frame gets created. */
2729 visium_frame_needed
= true;
2733 /* A C expression whose value is RTL representing the value of the return
2734 address for the frame COUNT steps up from the current frame, after the
2735 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2736 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2739 The value of the expression must always be the correct address when COUNT is
2740 zero, but may be `NULL_RTX' if there is not way to determine the return
2741 address of other frames. */
2744 visium_return_addr_rtx (int count
, rtx frame ATTRIBUTE_UNUSED
)
2746 /* Dont try to compute anything other than frame zero. */
2750 visium_frame_needed
= true;
2752 gen_frame_mem (Pmode
, plus_constant (Pmode
, hard_frame_pointer_rtx
, 4));
2755 /* Helper function for EH_RETURN_HANDLER_RTX. Return the RTX representing a
2756 location in which to store the address of an exception handler to which we
2760 visium_eh_return_handler_rtx (void)
2763 = gen_frame_mem (SImode
, plus_constant (Pmode
, hard_frame_pointer_rtx
, 4));
2764 MEM_VOLATILE_P (mem
) = 1;
2768 static struct machine_function
*
2769 visium_init_machine_status (void)
2771 return ggc_cleared_alloc
<machine_function
> ();
2774 /* The per-function data machinery is needed to indicate when a frame
2778 visium_init_expanders (void)
2780 init_machine_status
= visium_init_machine_status
;
2783 /* Given a comparison code (EQ, NE, etc.) and the operands of a COMPARE,
2784 return the mode to be used for the comparison. */
2787 visium_select_cc_mode (enum rtx_code code
, rtx op0
, rtx op1
)
2789 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_FLOAT
)
2809 /* These 2 comparison codes are not supported. */
2817 if (op1
!= const0_rtx
)
2820 switch (GET_CODE (op0
))
2828 /* The V flag may be set differently from a COMPARE with zero.
2829 The consequence is that a comparison operator testing V must
2830 be turned into another operator not testing V and yielding
2831 the same result for a comparison with zero. That's possible
2832 for GE/LT which become NC/NS respectively, but not for GT/LE
2833 for which the altered operator doesn't exist on the Visium. */
2837 /* This is a btst, the result is in C instead of Z. */
2841 /* This is a degenerate case, typically an uninitialized variable. */
2842 gcc_assert (op0
== constm1_rtx
);
2852 /* Pretend that the flags are set as for a COMPARE with zero.
2853 That's mostly true, except for the 2 right shift insns that
2854 will set the C flag. But the C flag is relevant only for
2855 the unsigned comparison operators and they are eliminated
2856 when applied to a comparison with zero. */
2864 /* Split a compare-and-branch with CODE, operands OP0 and OP1, and LABEL. */
2867 visium_split_cbranch (enum rtx_code code
, rtx op0
, rtx op1
, rtx label
)
2869 enum machine_mode cc_mode
= visium_select_cc_mode (code
, op0
, op1
);
2870 rtx flags
= gen_rtx_REG (cc_mode
, FLAGS_REGNUM
);
2872 rtx x
= gen_rtx_COMPARE (cc_mode
, op0
, op1
);
2873 x
= gen_rtx_SET (flags
, x
);
2876 x
= gen_rtx_fmt_ee (code
, VOIDmode
, flags
, const0_rtx
);
2877 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
, gen_rtx_LABEL_REF (Pmode
, label
),
2879 x
= gen_rtx_SET (pc_rtx
, x
);
2882 visium_flags_exposed
= true;
2885 /* Branch instructions on the Visium.
2887 Setting aside the interrupt-handling specific instructions, the ISA has
2888 two branch instructions: BRR and BRA. The former is used to implement
2889 short branches (+/- 2^17) within functions and its target is encoded in
2890 the instruction. The latter is used to implement all the other types
2891 of control flow changes and its target might not be statically known
2892 or even easily predictable at run time. Here's a complete summary of
2893 the patterns that generate a BRA instruction:
2903 Among these patterns, only the return (5) and the long branch (6) can be
2904 conditional; all the other patterns are always unconditional.
2906 The following algorithm can be used to identify the pattern for which
2907 the BRA instruction was generated and work out its target:
2909 A. If the source is r21 and the destination is r0, this is a return (5)
2910 and the target is the caller (i.e. the value of r21 on function's
2913 B. If the source is rN, N != 21 and the destination is r0, this is either
2914 an indirect jump or a table jump (1, 2) and the target is not easily
2917 C. If the source is rN, N != 21 and the destination is r21, this is a call
2918 (3) and the target is given by the preceding MOVIL/MOVIU pair for rN,
2919 unless this is an indirect call in which case the target is not easily
2922 D. If the source is rN, N != 21 and the destination is also rN, this is
2923 either a sibling call or a trampoline (4, 7) and the target is given
2924 by the preceding MOVIL/MOVIU pair for rN.
2926 E. If the source is r21 and the destination is also r21, this is a long
2927 branch (6) and the target is given by the preceding MOVIL/MOVIU pair
2930 The other combinations are not used. This implementation has been devised
2931 to accommodate the branch predictor of the GR6 but is used unconditionally
2932 by the compiler, i.e. including for earlier processors. */
2934 /* Output a conditional/unconditional branch to LABEL. COND is the string
2935 condition. INSN is the instruction. */
2938 output_branch (rtx label
, const char *cond
, rtx_insn
*insn
)
2944 operands
[0] = label
;
2946 /* If the length of the instruction is greater than 8, then this is a
2947 long branch and we need to work harder to emit it properly. */
2948 if (get_attr_length (insn
) > 8)
2952 /* If the link register has been saved, then we use it. */
2953 if (current_function_saves_lr ())
2955 operands
[1] = regno_reg_rtx
[LINK_REGNUM
];
2959 /* Or else, if the long-branch register isn't live, we use it. */
2960 else if (!df_regs_ever_live_p (long_branch_regnum
))
2962 operands
[1] = regno_reg_rtx
[long_branch_regnum
];
2966 /* Otherwise, we will use the long-branch register but we need to
2967 spill it to the stack and reload it at the end. We should have
2968 reserved the LR slot for this purpose. */
2971 operands
[1] = regno_reg_rtx
[long_branch_regnum
];
2973 gcc_assert (current_function_has_lr_slot ());
2976 /* First emit the spill to the stack:
2979 write.l [1](sp),reg */
2984 rtx_insn
*delay
= NEXT_INSN (insn
);
2988 final_scan_insn (delay
, asm_out_file
, optimize
, 0, &seen
);
2989 PATTERN (delay
) = gen_blockage ();
2990 INSN_CODE (delay
) = -1;
2993 if (current_function_saves_fp ())
2994 output_asm_insn ("write.l 1(sp),%1", operands
);
2996 output_asm_insn ("write.l (sp),%1", operands
);
2999 /* Then emit the core sequence:
3005 We don't use r0 as the destination register of the branch because we
3006 want the Branch Pre-decode Logic of the GR6 to use the Address Load
3007 Array to predict the branch target. */
3008 output_asm_insn ("moviu %1,%%u %0", operands
);
3009 output_asm_insn ("movil %1,%%l %0", operands
);
3010 strcpy (str
, "bra ");
3012 strcat (str
, ",%1,%1");
3015 strcat (str
, "\t\t;long branch");
3016 output_asm_insn (str
, operands
);
3018 /* Finally emit the reload:
3020 read.l reg,[1](sp) */
3023 if (current_function_saves_fp ())
3024 output_asm_insn (" read.l %1,1(sp)", operands
);
3026 output_asm_insn (" read.l %1,(sp)", operands
);
3030 /* Or else, if the label is PC, then this is a return. */
3031 else if (label
== pc_rtx
)
3033 strcpy (str
, "bra ");
3035 strcat (str
, ",r21,r0%#\t\t;return");
3036 output_asm_insn (str
, operands
);
3039 /* Otherwise, this is a short branch. */
3042 strcpy (str
, "brr ");
3044 strcat (str
, ",%0%#");
3045 output_asm_insn (str
, operands
);
3051 /* Output an unconditional branch to LABEL. INSN is the instruction. */
3054 output_ubranch (rtx label
, rtx_insn
*insn
)
3056 return output_branch (label
, "tr", insn
);
3059 /* Output a conditional branch to LABEL. CODE is the comparison code.
3060 CC_MODE is the mode of the CC register. REVERSED is non-zero if we
3061 should reverse the sense of the comparison. INSN is the instruction. */
3064 output_cbranch (rtx label
, enum rtx_code code
, enum machine_mode cc_mode
,
3065 int reversed
, rtx_insn
*insn
)
3071 if (cc_mode
== CCFPmode
|| cc_mode
== CCFPEmode
)
3072 code
= reverse_condition_maybe_unordered (code
);
3074 code
= reverse_condition (code
);
3080 if (cc_mode
== CC_BTSTmode
)
3087 if (cc_mode
== CC_BTSTmode
)
3094 if (cc_mode
== CC_NOOVmode
)
3105 if (cc_mode
== CCFPmode
|| cc_mode
== CCFPEmode
)
3112 if (cc_mode
== CCFPmode
|| cc_mode
== CCFPEmode
)
3114 else if (cc_mode
== CC_NOOVmode
)
3160 /* These 2 comparison codes are not supported. */
3167 return output_branch (label
, cond
, insn
);
3170 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */
3173 visium_print_operand_punct_valid_p (unsigned char code
)
3178 /* Implement TARGET_PRINT_OPERAND. Output to stdio stream FILE the assembler
3179 syntax for an instruction operand OP subject to the modifier LETTER. */
3182 visium_print_operand (FILE *file
, rtx op
, int letter
)
3187 /* Output an insn in a delay slot. */
3189 visium_indent_opcode
= 1;
3191 fputs ("\n\t nop", file
);
3195 /* Print LS 8 bits of operand. */
3196 fprintf (file
, HOST_WIDE_INT_PRINT_UNSIGNED
, UINTVAL (op
) & 0xff);
3200 /* Print LS 16 bits of operand. */
3201 fprintf (file
, HOST_WIDE_INT_PRINT_UNSIGNED
, UINTVAL (op
) & 0xffff);
3205 /* Print MS 16 bits of operand. */
3207 HOST_WIDE_INT_PRINT_UNSIGNED
, (UINTVAL (op
) >> 16) & 0xffff);
3211 /* It's either a register or zero. */
3212 if (GET_CODE (op
) == REG
)
3213 fputs (reg_names
[REGNO (op
)], file
);
3215 fputs (reg_names
[0], file
);
3219 /* It's either a FP register or zero. */
3220 if (GET_CODE (op
) == REG
)
3221 fputs (reg_names
[REGNO (op
)], file
);
3223 fputs (reg_names
[FP_FIRST_REGNUM
], file
);
3227 switch (GET_CODE (op
))
3231 fputs (reg_names
[REGNO (op
) + 1], file
);
3233 fputs (reg_names
[REGNO (op
)], file
);
3239 output_addr_const (file
, op
);
3243 visium_print_operand_address (file
, GET_MODE (op
), XEXP (op
, 0));
3247 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (op
));
3251 asm_fprintf (file
, "%LL%d", CODE_LABEL_NUMBER (op
));
3255 visium_print_operand (file
, XEXP (op
, 1), letter
);
3259 fatal_insn ("illegal operand ", op
);
3263 /* Implement TARGET_PRINT_OPERAND_ADDRESS. Output to stdio stream FILE the
3264 assembler syntax for an instruction operand that is a memory reference
3265 whose address is ADDR. */
3268 visium_print_operand_address (FILE *file
, enum machine_mode mode
, rtx addr
)
3270 switch (GET_CODE (addr
))
3274 fprintf (file
, "(%s)", reg_names
[true_regnum (addr
)]);
3279 rtx x
= XEXP (addr
, 0), y
= XEXP (addr
, 1);
3281 switch (GET_CODE (x
))
3285 if (CONST_INT_P (y
))
3287 unsigned int regno
= true_regnum (x
);
3288 HOST_WIDE_INT val
= INTVAL (y
);
3306 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
"(%s)", val
,
3310 fatal_insn ("illegal operand address (1)", addr
);
3314 if (CONSTANT_P (x
) && CONSTANT_P (y
))
3315 output_addr_const (file
, addr
);
3317 fatal_insn ("illegal operand address (2)", addr
);
3327 output_addr_const (file
, addr
);
3331 if (NOTE_KIND (addr
) != NOTE_INSN_DELETED_LABEL
)
3332 fatal_insn ("illegal operand address (3)", addr
);
3336 asm_fprintf (file
, "%LL%d", CODE_LABEL_NUMBER (addr
));
3340 fatal_insn ("illegal operand address (4)", addr
);
3345 /* The Visium stack frames look like:
3347 Before call After call
3348 +-----------------------+ +-----------------------+
3350 high | previous | | previous |
3351 mem | frame | | frame |
3353 +-----------------------+ +-----------------------+
3355 | arguments on stack | | arguments on stack |
3357 SP+0->+-----------------------+ +-----------------------+
3358 | reg parm save area, |
3359 | only created for |
3360 | variable argument |
3362 +-----------------------+
3364 | register save area |
3366 +-----------------------+
3370 FP+8->+-----------------------+
3372 FP+4->+-----------------------+
3374 FP+0->+-----------------------+
3376 | alloca allocations |
3378 +-----------------------+
3380 low | arguments on stack |
3382 SP+0->+-----------------------+
3385 1) The "reg parm save area" does not exist for non variable argument fns.
3386 2) The FP register is not saved if `frame_pointer_needed' is zero and it
3387 is not altered in the current function.
3388 3) The return address is not saved if there is no frame pointer and the
3389 current function is leaf.
3390 4) If the return address is not saved and the static chain register is
3391 live in the function, we allocate the return address slot to be able
3392 to spill the register for a long branch. */
3394 /* Define the register classes for local purposes. */
3395 enum reg_type
{ general
, mdb
, mdc
, floating
, last_type
};
3397 #define GET_REG_TYPE(regno) \
3398 (GP_REGISTER_P (regno) ? general : \
3399 (regno) == MDB_REGNUM ? mdb : \
3400 (regno) == MDC_REGNUM ? mdc : \
3403 /* First regno of each register type. */
3404 const int first_regno
[last_type
] = {0, MDB_REGNUM
, MDC_REGNUM
, FP_FIRST_REGNUM
};
3406 /* Size in bytes of each register type. */
3407 const int reg_type_size
[last_type
] = {4, 8, 4, 4};
3409 /* Structure to be filled in by visium_compute_frame_size. */
3410 struct visium_frame_info
3412 unsigned int save_area_size
; /* # bytes in the reg parm save area. */
3413 unsigned int reg_size1
; /* # bytes to store first block of regs. */
3414 unsigned int reg_size2
; /* # bytes to store second block of regs. */
3415 unsigned int max_reg1
; /* max. regno in first block */
3416 unsigned int var_size
; /* # bytes that variables take up. */
3417 unsigned int save_fp
; /* Nonzero if fp must be saved. */
3418 unsigned int save_lr
; /* Nonzero if lr must be saved. */
3419 unsigned int lr_slot
; /* Nonzero if the lr slot is needed. */
3420 unsigned int combine
; /* Nonzero if we can combine the allocation of
3421 variables and regs. */
3422 unsigned int interrupt
; /* Nonzero if the function is an interrupt
3424 unsigned int mask
[last_type
]; /* Masks of saved regs: gp, mdb, mdc, fp */
3427 /* Current frame information calculated by visium_compute_frame_size. */
3428 static struct visium_frame_info current_frame_info
;
3430 /* Accessor for current_frame_info.save_fp. */
3433 current_function_saves_fp (void)
3435 return current_frame_info
.save_fp
!= 0;
3438 /* Accessor for current_frame_info.save_lr. */
3441 current_function_saves_lr (void)
3443 return current_frame_info
.save_lr
!= 0;
3446 /* Accessor for current_frame_info.lr_slot. */
3449 current_function_has_lr_slot (void)
3451 return current_frame_info
.lr_slot
!= 0;
3454 /* Return non-zero if register REGNO needs to be saved in the frame. */
3457 visium_save_reg_p (int interrupt
, int regno
)
3461 case HARD_FRAME_POINTER_REGNUM
:
3462 /* This register is call-saved but handled specially. */
3466 /* This register is fixed but can be modified. */
3471 /* These registers are fixed and hold the interrupt context. */
3472 return (interrupt
!= 0);
3475 /* The other fixed registers are either immutable or special. */
3476 if (fixed_regs
[regno
])
3485 if (df_regs_ever_live_p (regno
))
3488 else if (call_used_regs
[regno
])
3491 /* To save mdb requires two temporary registers. To save mdc or
3492 any of the floating registers requires one temporary
3493 register. If this is an interrupt routine, the temporary
3494 registers need to be saved as well. These temporary registers
3495 are call used, so we only need deal with the case of leaf
3497 if (regno
== PROLOGUE_TMP_REGNUM
)
3499 if (df_regs_ever_live_p (MDB_REGNUM
)
3500 || df_regs_ever_live_p (MDC_REGNUM
))
3503 for (int i
= FP_FIRST_REGNUM
; i
<= FP_LAST_REGNUM
; i
++)
3504 if (df_regs_ever_live_p (i
))
3508 else if (regno
== PROLOGUE_TMP_REGNUM
+ 1)
3510 if (df_regs_ever_live_p (MDB_REGNUM
))
3515 return df_regs_ever_live_p (regno
) && !call_used_regs
[regno
];
3518 /* Compute the frame size required by the function. This function is called
3519 during the reload pass and also by visium_expand_prologue. */
3522 visium_compute_frame_size (int size
)
3524 const int save_area_size
= visium_reg_parm_save_area_size
;
3525 const int var_size
= VISIUM_STACK_ALIGN (size
);
3527 = frame_pointer_needed
|| df_regs_ever_live_p (HARD_FRAME_POINTER_REGNUM
);
3528 const int save_lr
= frame_pointer_needed
|| !crtl
->is_leaf
;
3529 const int lr_slot
= !save_lr
&& df_regs_ever_live_p (long_branch_regnum
);
3530 const int local_frame_offset
3531 = (save_fp
+ save_lr
+ lr_slot
) * UNITS_PER_WORD
;
3532 const int interrupt
= visium_interrupt_function_p ();
3533 unsigned int mask
[last_type
];
3542 memset (mask
, 0, last_type
* sizeof (unsigned int));
3544 /* The registers may need stacking in 2 blocks since only 32 32-bit words
3545 can be indexed from a given base address. */
3546 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3548 if (visium_save_reg_p (interrupt
, regno
))
3550 enum reg_type reg_type
= GET_REG_TYPE (regno
);
3551 int mask_bit
= 1 << (regno
- first_regno
[reg_type
]);
3552 int nbytes
= reg_type_size
[reg_type
];
3554 if (reg_size1
+ nbytes
> 32 * UNITS_PER_WORD
)
3557 reg_size1
+= nbytes
;
3559 mask
[reg_type
] |= mask_bit
;
3563 for (regno
= max_reg1
+ 1; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3565 if (visium_save_reg_p (interrupt
, regno
))
3567 enum reg_type reg_type
= GET_REG_TYPE (regno
);
3568 int mask_bit
= 1 << (regno
- first_regno
[reg_type
]);
3569 int nbytes
= reg_type_size
[reg_type
];
3571 reg_size2
+= nbytes
;
3572 mask
[reg_type
] |= mask_bit
;
3576 reg_size
= reg_size2
? reg_size2
: reg_size1
;
3577 combine
= (local_frame_offset
+ var_size
+ reg_size
) <= 32 * UNITS_PER_WORD
;
3579 = local_frame_offset
+ var_size
+ reg_size2
+ reg_size1
+ save_area_size
;
3581 current_frame_info
.save_area_size
= save_area_size
;
3582 current_frame_info
.reg_size1
= reg_size1
;
3583 current_frame_info
.max_reg1
= max_reg1
;
3584 current_frame_info
.reg_size2
= reg_size2
;
3585 current_frame_info
.var_size
= var_size
;
3586 current_frame_info
.save_fp
= save_fp
;
3587 current_frame_info
.save_lr
= save_lr
;
3588 current_frame_info
.lr_slot
= lr_slot
;
3589 current_frame_info
.combine
= combine
;
3590 current_frame_info
.interrupt
= interrupt
;
3592 memcpy (current_frame_info
.mask
, mask
, last_type
* sizeof (unsigned int));
3597 /* Helper function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). Define
3598 the offset between two registers, one to be eliminated, and the other its
3599 replacement, at the start of a routine. */
3602 visium_initial_elimination_offset (int from
, int to ATTRIBUTE_UNUSED
)
3604 const int save_fp
= current_frame_info
.save_fp
;
3605 const int save_lr
= current_frame_info
.save_lr
;
3606 const int lr_slot
= current_frame_info
.lr_slot
;
3609 if (from
== FRAME_POINTER_REGNUM
)
3610 offset
= (save_fp
+ save_lr
+ lr_slot
) * UNITS_PER_WORD
;
3611 else if (from
== ARG_POINTER_REGNUM
)
3612 offset
= visium_compute_frame_size (get_frame_size ());
3619 /* For an interrupt handler, we may be saving call-clobbered registers.
3620 Say the epilogue uses these in addition to the link register. */
3623 visium_epilogue_uses (int regno
)
3625 if (regno
== LINK_REGNUM
)
3628 if (reload_completed
)
3630 enum reg_type reg_type
= GET_REG_TYPE (regno
);
3631 int mask_bit
= 1 << (regno
- first_regno
[reg_type
]);
3633 return (current_frame_info
.mask
[reg_type
] & mask_bit
) != 0;
3639 /* Wrapper around emit_insn that sets RTX_FRAME_RELATED_P on the insn. */
3642 emit_frame_insn (rtx x
)
3645 RTX_FRAME_RELATED_P (x
) = 1;
3649 /* Allocate ALLOC bytes on the stack and save the registers LOW_REGNO to
3650 HIGH_REGNO at OFFSET from the stack pointer. */
3653 visium_save_regs (int alloc
, int offset
, int low_regno
, int high_regno
)
3655 /* If this is an interrupt handler function, then mark the register
3656 stores as volatile. This will prevent the instruction scheduler
3657 from scrambling the order of register saves. */
3658 const int volatile_p
= current_frame_info
.interrupt
;
3661 /* Allocate the stack space. */
3662 emit_frame_insn (gen_addsi3_flags (stack_pointer_rtx
, stack_pointer_rtx
,
3665 for (regno
= low_regno
; regno
<= high_regno
; regno
++)
3667 enum reg_type reg_type
= GET_REG_TYPE (regno
);
3668 int mask_bit
= 1 << (regno
- first_regno
[reg_type
]);
3671 if (current_frame_info
.mask
[reg_type
] & mask_bit
)
3673 offset
-= reg_type_size
[reg_type
];
3679 = gen_frame_mem (SImode
,
3680 plus_constant (Pmode
,
3681 stack_pointer_rtx
, offset
));
3682 MEM_VOLATILE_P (mem
) = volatile_p
;
3683 emit_frame_insn (gen_movsi (mem
, gen_rtx_REG (SImode
, regno
)));
3689 rtx tmp
= gen_rtx_REG (DImode
, PROLOGUE_TMP_REGNUM
);
3691 = gen_frame_mem (DImode
,
3692 plus_constant (Pmode
,
3693 stack_pointer_rtx
, offset
));
3694 rtx reg
= gen_rtx_REG (DImode
, regno
);
3695 MEM_VOLATILE_P (mem
) = volatile_p
;
3696 emit_insn (gen_movdi (tmp
, reg
));
3697 /* Do not generate CFI if in interrupt handler. */
3699 emit_insn (gen_movdi (mem
, tmp
));
3702 insn
= emit_frame_insn (gen_movdi (mem
, tmp
));
3703 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3704 gen_rtx_SET (mem
, reg
));
3711 rtx tmp
= gen_rtx_REG (SImode
, PROLOGUE_TMP_REGNUM
);
3713 = gen_frame_mem (SImode
,
3714 plus_constant (Pmode
,
3715 stack_pointer_rtx
, offset
));
3716 rtx reg
= gen_rtx_REG (SImode
, regno
);
3717 MEM_VOLATILE_P (mem
) = volatile_p
;
3718 emit_insn (gen_movsi (tmp
, reg
));
3719 insn
= emit_frame_insn (gen_movsi (mem
, tmp
));
3720 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3721 gen_rtx_SET (mem
, reg
));
3727 rtx tmp
= gen_rtx_REG (SFmode
, PROLOGUE_TMP_REGNUM
);
3729 = gen_frame_mem (SFmode
,
3730 plus_constant (Pmode
,
3731 stack_pointer_rtx
, offset
));
3732 rtx reg
= gen_rtx_REG (SFmode
, regno
);
3733 MEM_VOLATILE_P (mem
) = volatile_p
;
3734 emit_insn (gen_movsf (tmp
, reg
));
3735 insn
= emit_frame_insn (gen_movsf (mem
, tmp
));
3736 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3737 gen_rtx_SET (mem
, reg
));
3748 /* This function generates the code for function entry. */
3751 visium_expand_prologue (void)
3753 const int frame_size
= visium_compute_frame_size (get_frame_size ());
3754 const int save_area_size
= current_frame_info
.save_area_size
;
3755 const int reg_size1
= current_frame_info
.reg_size1
;
3756 const int max_reg1
= current_frame_info
.max_reg1
;
3757 const int reg_size2
= current_frame_info
.reg_size2
;
3758 const int var_size
= current_frame_info
.var_size
;
3759 const int save_fp
= current_frame_info
.save_fp
;
3760 const int save_lr
= current_frame_info
.save_lr
;
3761 const int lr_slot
= current_frame_info
.lr_slot
;
3762 const int local_frame_offset
3763 = (save_fp
+ save_lr
+ lr_slot
) * UNITS_PER_WORD
;
3764 const int combine
= current_frame_info
.combine
;
3769 /* Save the frame size for future references. */
3770 visium_frame_size
= frame_size
;
3772 if (flag_stack_usage_info
)
3773 current_function_static_stack_size
= frame_size
;
3775 /* If the registers have to be stacked in 2 blocks, stack the first one. */
3778 visium_save_regs (reg_size1
+ save_area_size
, reg_size1
, 0, max_reg1
);
3779 reg_size
= reg_size2
;
3780 first_reg
= max_reg1
+ 1;
3781 fsize
= local_frame_offset
+ var_size
+ reg_size2
;
3785 reg_size
= reg_size1
;
3787 fsize
= local_frame_offset
+ var_size
+ reg_size1
+ save_area_size
;
3790 /* If we can't combine register stacking with variable allocation, partially
3791 allocate and stack the (remaining) registers now. */
3792 if (reg_size
&& !combine
)
3793 visium_save_regs (fsize
- local_frame_offset
- var_size
, reg_size
,
3794 first_reg
, FIRST_PSEUDO_REGISTER
- 1);
3796 /* If we can combine register stacking with variable allocation, fully
3797 allocate and stack the (remaining) registers now. */
3798 if (reg_size
&& combine
)
3799 visium_save_regs (fsize
, local_frame_offset
+ var_size
+ reg_size
,
3800 first_reg
, FIRST_PSEUDO_REGISTER
- 1);
3802 /* Otherwise space may still need to be allocated for the variables. */
3805 const int alloc_size
= reg_size
? local_frame_offset
+ var_size
: fsize
;
3807 if (alloc_size
> 65535)
3809 rtx tmp
= gen_rtx_REG (SImode
, PROLOGUE_TMP_REGNUM
), insn
;
3810 emit_insn (gen_movsi (tmp
, GEN_INT (alloc_size
)));
3811 insn
= emit_frame_insn (gen_subsi3_flags (stack_pointer_rtx
,
3814 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
3815 gen_rtx_SET (stack_pointer_rtx
,
3816 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
3817 GEN_INT (-alloc_size
))));
3820 emit_frame_insn (gen_addsi3_flags (stack_pointer_rtx
,
3822 GEN_INT (-alloc_size
)));
3826 emit_frame_insn (gen_movsi (gen_frame_mem (SImode
, stack_pointer_rtx
),
3827 hard_frame_pointer_rtx
));
3829 if (frame_pointer_needed
)
3830 emit_frame_insn (gen_stack_save ());
3836 /* Normally the frame pointer and link register get saved via
3841 Indexing off sp rather than fp to store the link register
3842 avoids presenting the instruction scheduler with an initial
3843 pipeline hazard. If however the frame is needed for eg.
3844 __builtin_return_address which needs to retrieve the saved
3845 value of the link register from the stack at fp + 4 then
3846 indexing from sp can confuse the dataflow, causing the link
3847 register to be retrieved before it has been saved. */
3848 if (cfun
->machine
->frame_needed
)
3849 base_rtx
= hard_frame_pointer_rtx
;
3851 base_rtx
= stack_pointer_rtx
;
3853 mem
= gen_frame_mem (SImode
,
3854 plus_constant (Pmode
,
3855 base_rtx
, save_fp
* UNITS_PER_WORD
));
3856 emit_frame_insn (gen_movsi (mem
, gen_rtx_REG (SImode
, LINK_REGNUM
)));
3860 static GTY(()) rtx cfa_restores
;
3862 /* Queue a REG_CFA_RESTORE note until next stack manipulation insn. */
3865 visium_add_cfa_restore_note (rtx reg
)
3867 cfa_restores
= alloc_reg_note (REG_CFA_RESTORE
, reg
, cfa_restores
);
3870 /* Add queued REG_CFA_RESTORE notes to INSN, if any. */
3873 visium_add_queued_cfa_restore_notes (rtx insn
)
3878 for (last
= cfa_restores
; XEXP (last
, 1); last
= XEXP (last
, 1))
3880 XEXP (last
, 1) = REG_NOTES (insn
);
3881 REG_NOTES (insn
) = cfa_restores
;
3882 cfa_restores
= NULL_RTX
;
3885 /* Restore the registers LOW_REGNO to HIGH_REGNO from the save area at OFFSET
3886 from the stack pointer and pop DEALLOC bytes off the stack. */
3889 visium_restore_regs (int dealloc
, int offset
, int high_regno
, int low_regno
)
3891 /* If this is an interrupt handler function, then mark the register
3892 restores as volatile. This will prevent the instruction scheduler
3893 from scrambling the order of register restores. */
3894 const int volatile_p
= current_frame_info
.interrupt
;
3895 int r30_offset
= -1;
3898 for (regno
= high_regno
; regno
>= low_regno
; --regno
)
3900 enum reg_type reg_type
= GET_REG_TYPE (regno
);
3901 int mask_bit
= 1 << (regno
- first_regno
[reg_type
]);
3903 if (current_frame_info
.mask
[reg_type
] & mask_bit
)
3908 /* Postpone restoring the interrupted context registers
3909 until last, since they need to be preceded by a dsi. */
3912 else if (regno
== 30)
3913 r30_offset
= offset
;
3917 = gen_frame_mem (SImode
,
3918 plus_constant (Pmode
,
3921 rtx reg
= gen_rtx_REG (SImode
, regno
);
3922 MEM_VOLATILE_P (mem
) = volatile_p
;
3923 emit_insn (gen_movsi (reg
, mem
));
3924 visium_add_cfa_restore_note (reg
);
3930 rtx tmp
= gen_rtx_REG (DImode
, PROLOGUE_TMP_REGNUM
);
3932 = gen_frame_mem (DImode
,
3933 plus_constant (Pmode
,
3934 stack_pointer_rtx
, offset
));
3935 rtx reg
= gen_rtx_REG (DImode
, regno
);
3936 MEM_VOLATILE_P (mem
) = volatile_p
;
3937 emit_insn (gen_movdi (tmp
, mem
));
3938 emit_insn (gen_movdi (reg
, tmp
));
3939 /* Do not generate CFI if in interrupt handler. */
3941 visium_add_cfa_restore_note (reg
);
3947 rtx tmp
= gen_rtx_REG (SImode
, PROLOGUE_TMP_REGNUM
);
3949 = gen_frame_mem (SImode
,
3950 plus_constant (Pmode
,
3951 stack_pointer_rtx
, offset
));
3952 rtx reg
= gen_rtx_REG (SImode
, regno
);
3953 MEM_VOLATILE_P (mem
) = volatile_p
;
3954 emit_insn (gen_movsi (tmp
, mem
));
3955 emit_insn (gen_movsi (reg
, tmp
));
3956 visium_add_cfa_restore_note (reg
);
3962 rtx tmp
= gen_rtx_REG (SFmode
, PROLOGUE_TMP_REGNUM
);
3964 = gen_frame_mem (SFmode
,
3965 plus_constant (Pmode
,
3966 stack_pointer_rtx
, offset
));
3967 rtx reg
= gen_rtx_REG (SFmode
, regno
);
3968 MEM_VOLATILE_P (mem
) = volatile_p
;
3969 emit_insn (gen_movsf (tmp
, mem
));
3970 emit_insn (gen_movsf (reg
, tmp
));
3971 visium_add_cfa_restore_note (reg
);
3979 offset
+= reg_type_size
[reg_type
];
3983 /* If the interrupted context needs to be restored, precede the
3984 restores of r29 and r30 by a dsi. */
3985 if (r30_offset
>= 0)
3987 emit_insn (gen_dsi ());
3988 emit_move_insn (gen_rtx_REG (SImode
, 30),
3989 gen_frame_mem (SImode
,
3990 plus_constant (Pmode
,
3993 emit_move_insn (gen_rtx_REG (SImode
, 29),
3994 gen_frame_mem (SImode
,
3995 plus_constant (Pmode
,
4000 /* Deallocate the stack space. */
4001 rtx insn
= emit_frame_insn (gen_stack_pop (GEN_INT (dealloc
)));
4002 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4003 gen_rtx_SET (stack_pointer_rtx
,
4004 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4005 GEN_INT (dealloc
))));
4006 visium_add_queued_cfa_restore_notes (insn
);
4009 /* This function generates the code for function exit. */
4012 visium_expand_epilogue (void)
4014 const int save_area_size
= current_frame_info
.save_area_size
;
4015 const int reg_size1
= current_frame_info
.reg_size1
;
4016 const int max_reg1
= current_frame_info
.max_reg1
;
4017 const int reg_size2
= current_frame_info
.reg_size2
;
4018 const int var_size
= current_frame_info
.var_size
;
4019 const int restore_fp
= current_frame_info
.save_fp
;
4020 const int restore_lr
= current_frame_info
.save_lr
;
4021 const int lr_slot
= current_frame_info
.lr_slot
;
4022 const int local_frame_offset
4023 = (restore_fp
+ restore_lr
+ lr_slot
) * UNITS_PER_WORD
;
4024 const int combine
= current_frame_info
.combine
;
4029 /* Do not bother restoring the stack pointer if it hasn't been changed in
4030 the function since it was saved _after_ the allocation of the frame. */
4031 if (!crtl
->sp_is_unchanging
)
4032 emit_insn (gen_stack_restore ());
4034 /* Restore the frame pointer if necessary. The usual code would be:
4039 but for the MCM this constitutes a stall/hazard so it is changed to:
4044 if the stack pointer has actually been restored. */
4049 if (TARGET_MCM
&& !crtl
->sp_is_unchanging
)
4050 src
= gen_frame_mem (SImode
, hard_frame_pointer_rtx
);
4052 src
= gen_frame_mem (SImode
, stack_pointer_rtx
);
4054 rtx insn
= emit_frame_insn (gen_movsi (hard_frame_pointer_rtx
, src
));
4055 add_reg_note (insn
, REG_CFA_ADJUST_CFA
,
4056 gen_rtx_SET (stack_pointer_rtx
,
4057 hard_frame_pointer_rtx
));
4058 visium_add_cfa_restore_note (hard_frame_pointer_rtx
);
4061 /* Restore the link register if necessary. */
4064 rtx mem
= gen_frame_mem (SImode
,
4065 plus_constant (Pmode
,
4067 restore_fp
* UNITS_PER_WORD
));
4068 rtx reg
= gen_rtx_REG (SImode
, LINK_REGNUM
);
4069 emit_insn (gen_movsi (reg
, mem
));
4070 visium_add_cfa_restore_note (reg
);
4073 /* If we have two blocks of registers, deal with the second one first. */
4076 reg_size
= reg_size2
;
4077 last_reg
= max_reg1
+ 1;
4078 fsize
= local_frame_offset
+ var_size
+ reg_size2
;
4082 reg_size
= reg_size1
;
4084 fsize
= local_frame_offset
+ var_size
+ reg_size1
+ save_area_size
;
4087 /* If the variable allocation could be combined with register stacking,
4088 restore the (remaining) registers and fully deallocate now. */
4089 if (reg_size
&& combine
)
4090 visium_restore_regs (fsize
, local_frame_offset
+ var_size
,
4091 FIRST_PSEUDO_REGISTER
- 1, last_reg
);
4093 /* Otherwise deallocate the variables first. */
4096 const int pop_size
= reg_size
? local_frame_offset
+ var_size
: fsize
;
4099 if (pop_size
> 65535)
4101 rtx tmp
= gen_rtx_REG (SImode
, PROLOGUE_TMP_REGNUM
);
4102 emit_move_insn (tmp
, GEN_INT (pop_size
));
4103 insn
= emit_frame_insn (gen_stack_pop (tmp
));
4106 insn
= emit_frame_insn (gen_stack_pop (GEN_INT (pop_size
)));
4107 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
,
4108 gen_rtx_SET (stack_pointer_rtx
,
4109 gen_rtx_PLUS (Pmode
, stack_pointer_rtx
,
4110 GEN_INT (pop_size
))));
4111 visium_add_queued_cfa_restore_notes (insn
);
4114 /* If the variable allocation couldn't be combined with register stacking,
4115 restore the (remaining) registers now and partially deallocate. */
4116 if (reg_size
&& !combine
)
4117 visium_restore_regs (fsize
- local_frame_offset
- var_size
, 0,
4118 FIRST_PSEUDO_REGISTER
- 1, last_reg
);
4120 /* If the first block of registers has yet to be restored, do it now. */
4122 visium_restore_regs (reg_size1
+ save_area_size
, 0, max_reg1
, 0);
4124 /* If this is an exception return, make the necessary stack adjustment. */
4125 if (crtl
->calls_eh_return
)
4126 emit_insn (gen_stack_pop (EH_RETURN_STACKADJ_RTX
));
4129 /* Return true if it is appropriate to emit `return' instructions in the
4130 body of a function. */
4133 visium_can_use_return_insn_p (void)
4135 return reload_completed
4136 && visium_frame_size
== 0
4137 && !visium_interrupt_function_p ();
4140 /* Return the register class required for an intermediate register used to
4141 copy a register of RCLASS from/to X. If no such intermediate register is
4142 required, return NO_REGS. If more than one such intermediate register is
4143 required, describe the one that is closest in the copy chain to the reload
4147 visium_secondary_reload (bool in_p ATTRIBUTE_UNUSED
, rtx x
,
4149 enum machine_mode mode ATTRIBUTE_UNUSED
,
4150 secondary_reload_info
*sri ATTRIBUTE_UNUSED
)
4152 int regno
= true_regnum (x
);
4154 /* For MDB, MDC and FP_REGS, a general register is needed for a move to
4156 if (regno
== -1 && (rclass
== MDB
|| rclass
== MDC
|| rclass
== FP_REGS
))
4157 return GENERAL_REGS
;
4159 /* Moves between MDB, MDC and FP_REGS also require a general register. */
4160 else if (((regno
== R_MDB
|| regno
== R_MDC
) && rclass
== FP_REGS
)
4161 || (FP_REGISTER_P (regno
) && (rclass
== MDB
|| rclass
== MDC
)))
4162 return GENERAL_REGS
;
4164 /* Finally an (unlikely ?) move between MDB and MDC needs a general reg. */
4165 else if ((regno
== R_MDB
&& rclass
== MDC
)
4166 || (rclass
== MDB
&& regno
== R_MDC
))
4167 return GENERAL_REGS
;
4172 /* Return true if pseudos that have been assigned to registers of RCLASS
4173 would likely be spilled because registers of RCLASS are needed for
4177 visium_class_likely_spilled_p (reg_class_t rclass ATTRIBUTE_UNUSED
)
4179 /* Return false for classes R1, R2 and R3, which are intended to be used
4180 only in the source code in conjunction with block move instructions. */
4184 /* Return the register number if OP is a REG or a SUBREG of a REG, and
4185 INVALID_REGNUM in all the other cases. */
4188 reg_or_subreg_regno (rtx op
)
4192 if (GET_CODE (op
) == REG
)
4194 else if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == REG
)
4196 if (REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
4197 regno
= subreg_regno (op
);
4199 regno
= REGNO (SUBREG_REG (op
));
4202 regno
= INVALID_REGNUM
;
4207 #include "gt-visium.h"