1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
34 #include "insn-attr.h"
35 #include "insn-codes.h"
49 #include "target-def.h"
50 #include "langhooks.h"
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
74 /* Cached operands, and operator to compare for use in set/branch on
78 /* what type of branch to use */
79 enum cmp_type branch_type
;
81 /* Array giving truth value on whether or not a given hard register
82 can support a given mode. */
83 char xtensa_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
85 /* Current frame size calculated by compute_frame_size. */
86 unsigned xtensa_current_frame_size
;
88 /* Largest block move to handle in-line. */
89 #define LARGEST_MOVE_RATIO 15
91 /* Define the structure for the machine field in struct function. */
92 struct machine_function
GTY(())
94 int accesses_prev_frame
;
98 rtx set_frame_ptr_insn
;
101 /* Vector, indexed by hard register number, which contains 1 for a
102 register that is allowable in a candidate for leaf function
105 const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
] =
107 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
109 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
113 /* Map hard register number to register class */
114 const enum reg_class xtensa_regno_to_class
[FIRST_PSEUDO_REGISTER
] =
116 RL_REGS
, SP_REG
, RL_REGS
, RL_REGS
,
117 RL_REGS
, RL_REGS
, RL_REGS
, GR_REGS
,
118 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
119 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
120 AR_REGS
, AR_REGS
, BR_REGS
,
121 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
122 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
123 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
124 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
128 static enum internal_test
map_test_to_internal_test (enum rtx_code
);
129 static rtx
gen_int_relational (enum rtx_code
, rtx
, rtx
, int *);
130 static rtx
gen_float_relational (enum rtx_code
, rtx
, rtx
);
131 static rtx
gen_conditional_move (rtx
);
132 static rtx
fixup_subreg_mem (rtx
);
133 static struct machine_function
* xtensa_init_machine_status (void);
134 static bool xtensa_return_in_msb (const_tree
);
135 static void printx (FILE *, signed int);
136 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT
);
137 static rtx
xtensa_builtin_saveregs (void);
138 static unsigned int xtensa_multibss_section_type_flags (tree
, const char *,
139 int) ATTRIBUTE_UNUSED
;
140 static section
*xtensa_select_rtx_section (enum machine_mode
, rtx
,
141 unsigned HOST_WIDE_INT
);
142 static bool xtensa_rtx_costs (rtx
, int, int, int *);
143 static tree
xtensa_build_builtin_va_list (void);
144 static bool xtensa_return_in_memory (const_tree
, const_tree
);
145 static tree
xtensa_gimplify_va_arg_expr (tree
, tree
, gimple_seq
*,
147 static rtx
xtensa_function_value (const_tree
, const_tree
, bool);
148 static void xtensa_init_builtins (void);
149 static tree
xtensa_fold_builtin (tree
, tree
, bool);
150 static rtx
xtensa_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
151 static void xtensa_va_start (tree
, rtx
);
153 static const int reg_nonleaf_alloc_order
[FIRST_PSEUDO_REGISTER
] =
157 /* This macro generates the assembly code for function exit,
158 on machines that need it. If FUNCTION_EPILOGUE is not defined
159 then individual return instructions are generated for each
160 return statement. Args are same as for FUNCTION_PROLOGUE. */
162 #undef TARGET_ASM_FUNCTION_EPILOGUE
163 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
165 /* These hooks specify assembly directives for creating certain kinds
166 of integer object. */
168 #undef TARGET_ASM_ALIGNED_SI_OP
169 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
171 #undef TARGET_ASM_SELECT_RTX_SECTION
172 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
174 #undef TARGET_DEFAULT_TARGET_FLAGS
175 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
177 #undef TARGET_RTX_COSTS
178 #define TARGET_RTX_COSTS xtensa_rtx_costs
179 #undef TARGET_ADDRESS_COST
180 #define TARGET_ADDRESS_COST hook_int_rtx_0
182 #undef TARGET_BUILD_BUILTIN_VA_LIST
183 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
185 #undef TARGET_EXPAND_BUILTIN_VA_START
186 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start
188 #undef TARGET_PROMOTE_FUNCTION_ARGS
189 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
190 #undef TARGET_PROMOTE_FUNCTION_RETURN
191 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
192 #undef TARGET_PROMOTE_PROTOTYPES
193 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
195 #undef TARGET_RETURN_IN_MEMORY
196 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
197 #undef TARGET_FUNCTION_VALUE
198 #define TARGET_FUNCTION_VALUE xtensa_function_value
199 #undef TARGET_SPLIT_COMPLEX_ARG
200 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
201 #undef TARGET_MUST_PASS_IN_STACK
202 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
204 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
205 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
206 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
207 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
209 #undef TARGET_RETURN_IN_MSB
210 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
212 #undef TARGET_INIT_BUILTINS
213 #define TARGET_INIT_BUILTINS xtensa_init_builtins
214 #undef TARGET_FOLD_BUILTIN
215 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
216 #undef TARGET_EXPAND_BUILTIN
217 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
219 struct gcc_target targetm
= TARGET_INITIALIZER
;
222 /* Functions to test Xtensa immediate operand validity. */
225 xtensa_simm8 (HOST_WIDE_INT v
)
227 return v
>= -128 && v
<= 127;
232 xtensa_simm8x256 (HOST_WIDE_INT v
)
234 return (v
& 255) == 0 && (v
>= -32768 && v
<= 32512);
239 xtensa_simm12b (HOST_WIDE_INT v
)
241 return v
>= -2048 && v
<= 2047;
246 xtensa_uimm8 (HOST_WIDE_INT v
)
248 return v
>= 0 && v
<= 255;
253 xtensa_uimm8x2 (HOST_WIDE_INT v
)
255 return (v
& 1) == 0 && (v
>= 0 && v
<= 510);
260 xtensa_uimm8x4 (HOST_WIDE_INT v
)
262 return (v
& 3) == 0 && (v
>= 0 && v
<= 1020);
267 xtensa_b4const (HOST_WIDE_INT v
)
294 xtensa_b4const_or_zero (HOST_WIDE_INT v
)
298 return xtensa_b4const (v
);
303 xtensa_b4constu (HOST_WIDE_INT v
)
330 xtensa_mask_immediate (HOST_WIDE_INT v
)
332 #define MAX_MASK_SIZE 16
335 for (mask_size
= 1; mask_size
<= MAX_MASK_SIZE
; mask_size
++)
348 /* This is just like the standard true_regnum() function except that it
349 works even when reg_renumber is not initialized. */
352 xt_true_regnum (rtx x
)
354 if (GET_CODE (x
) == REG
)
357 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
358 && reg_renumber
[REGNO (x
)] >= 0)
359 return reg_renumber
[REGNO (x
)];
362 if (GET_CODE (x
) == SUBREG
)
364 int base
= xt_true_regnum (SUBREG_REG (x
));
365 if (base
>= 0 && base
< FIRST_PSEUDO_REGISTER
)
366 return base
+ subreg_regno_offset (REGNO (SUBREG_REG (x
)),
367 GET_MODE (SUBREG_REG (x
)),
368 SUBREG_BYTE (x
), GET_MODE (x
));
375 xtensa_valid_move (enum machine_mode mode
, rtx
*operands
)
377 /* Either the destination or source must be a register, and the
378 MAC16 accumulator doesn't count. */
380 if (register_operand (operands
[0], mode
))
382 int dst_regnum
= xt_true_regnum (operands
[0]);
384 /* The stack pointer can only be assigned with a MOVSP opcode. */
385 if (dst_regnum
== STACK_POINTER_REGNUM
)
386 return (mode
== SImode
387 && register_operand (operands
[1], mode
)
388 && !ACC_REG_P (xt_true_regnum (operands
[1])));
390 if (!ACC_REG_P (dst_regnum
))
393 if (register_operand (operands
[1], mode
))
395 int src_regnum
= xt_true_regnum (operands
[1]);
396 if (!ACC_REG_P (src_regnum
))
404 smalloffset_mem_p (rtx op
)
406 if (GET_CODE (op
) == MEM
)
408 rtx addr
= XEXP (op
, 0);
409 if (GET_CODE (addr
) == REG
)
410 return BASE_REG_P (addr
, 0);
411 if (GET_CODE (addr
) == PLUS
)
413 rtx offset
= XEXP (addr
, 0);
415 if (GET_CODE (offset
) != CONST_INT
)
416 offset
= XEXP (addr
, 1);
417 if (GET_CODE (offset
) != CONST_INT
)
420 val
= INTVAL (offset
);
421 return (val
& 3) == 0 && (val
>= 0 && val
<= 60);
429 constantpool_address_p (rtx addr
)
433 if (GET_CODE (addr
) == CONST
)
437 /* Only handle (PLUS (SYM, OFFSET)) form. */
438 addr
= XEXP (addr
, 0);
439 if (GET_CODE (addr
) != PLUS
)
442 /* Make sure the address is word aligned. */
443 offset
= XEXP (addr
, 1);
444 if ((GET_CODE (offset
) != CONST_INT
)
445 || ((INTVAL (offset
) & 3) != 0))
448 sym
= XEXP (addr
, 0);
451 if ((GET_CODE (sym
) == SYMBOL_REF
)
452 && CONSTANT_POOL_ADDRESS_P (sym
))
459 constantpool_mem_p (rtx op
)
461 if (GET_CODE (op
) == SUBREG
)
462 op
= SUBREG_REG (op
);
463 if (GET_CODE (op
) == MEM
)
464 return constantpool_address_p (XEXP (op
, 0));
470 xtensa_extend_reg (rtx dst
, rtx src
)
472 rtx temp
= gen_reg_rtx (SImode
);
473 rtx shift
= GEN_INT (BITS_PER_WORD
- GET_MODE_BITSIZE (GET_MODE (src
)));
475 /* Generate paradoxical subregs as needed so that the modes match. */
476 src
= simplify_gen_subreg (SImode
, src
, GET_MODE (src
), 0);
477 dst
= simplify_gen_subreg (SImode
, dst
, GET_MODE (dst
), 0);
479 emit_insn (gen_ashlsi3 (temp
, src
, shift
));
480 emit_insn (gen_ashrsi3 (dst
, temp
, shift
));
485 xtensa_mem_offset (unsigned v
, enum machine_mode mode
)
490 /* Handle the worst case for block moves. See xtensa_expand_block_move
491 where we emit an optimized block move operation if the block can be
492 moved in < "move_ratio" pieces. The worst case is when the block is
493 aligned but has a size of (3 mod 4) (does this happen?) so that the
494 last piece requires a byte load/store. */
495 return (xtensa_uimm8 (v
)
496 && xtensa_uimm8 (v
+ MOVE_MAX
* LARGEST_MOVE_RATIO
));
499 return xtensa_uimm8 (v
);
502 return xtensa_uimm8x2 (v
);
505 return (xtensa_uimm8x4 (v
) && xtensa_uimm8x4 (v
+ 4));
511 return xtensa_uimm8x4 (v
);
515 /* Make normal rtx_code into something we can index from an array. */
517 static enum internal_test
518 map_test_to_internal_test (enum rtx_code test_code
)
520 enum internal_test test
= ITEST_MAX
;
525 case EQ
: test
= ITEST_EQ
; break;
526 case NE
: test
= ITEST_NE
; break;
527 case GT
: test
= ITEST_GT
; break;
528 case GE
: test
= ITEST_GE
; break;
529 case LT
: test
= ITEST_LT
; break;
530 case LE
: test
= ITEST_LE
; break;
531 case GTU
: test
= ITEST_GTU
; break;
532 case GEU
: test
= ITEST_GEU
; break;
533 case LTU
: test
= ITEST_LTU
; break;
534 case LEU
: test
= ITEST_LEU
; break;
541 /* Generate the code to compare two integer values. The return value is
542 the comparison expression. */
545 gen_int_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
546 rtx cmp0
, /* first operand to compare */
547 rtx cmp1
, /* second operand to compare */
548 int *p_invert
/* whether branch needs to reverse test */)
552 enum rtx_code test_code
; /* test code to use in insn */
553 bool (*const_range_p
) (HOST_WIDE_INT
); /* range check function */
554 int const_add
; /* constant to add (convert LE -> LT) */
555 int reverse_regs
; /* reverse registers in test */
556 int invert_const
; /* != 0 if invert value if cmp1 is constant */
557 int invert_reg
; /* != 0 if invert value if cmp1 is register */
558 int unsignedp
; /* != 0 for unsigned comparisons. */
561 static struct cmp_info info
[ (int)ITEST_MAX
] = {
563 { EQ
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* EQ */
564 { NE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* NE */
566 { LT
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* GT */
567 { GE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* GE */
568 { LT
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* LT */
569 { GE
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* LE */
571 { LTU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* GTU */
572 { GEU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* GEU */
573 { LTU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* LTU */
574 { GEU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* LEU */
577 enum internal_test test
;
578 enum machine_mode mode
;
579 struct cmp_info
*p_info
;
581 test
= map_test_to_internal_test (test_code
);
582 gcc_assert (test
!= ITEST_MAX
);
584 p_info
= &info
[ (int)test
];
586 mode
= GET_MODE (cmp0
);
587 if (mode
== VOIDmode
)
588 mode
= GET_MODE (cmp1
);
590 /* Make sure we can handle any constants given to us. */
591 if (GET_CODE (cmp1
) == CONST_INT
)
593 HOST_WIDE_INT value
= INTVAL (cmp1
);
594 unsigned HOST_WIDE_INT uvalue
= (unsigned HOST_WIDE_INT
)value
;
596 /* if the immediate overflows or does not fit in the immediate field,
597 spill it to a register */
599 if ((p_info
->unsignedp
?
600 (uvalue
+ p_info
->const_add
> uvalue
) :
601 (value
+ p_info
->const_add
> value
)) != (p_info
->const_add
> 0))
603 cmp1
= force_reg (mode
, cmp1
);
605 else if (!(p_info
->const_range_p
) (value
+ p_info
->const_add
))
607 cmp1
= force_reg (mode
, cmp1
);
610 else if ((GET_CODE (cmp1
) != REG
) && (GET_CODE (cmp1
) != SUBREG
))
612 cmp1
= force_reg (mode
, cmp1
);
615 /* See if we need to invert the result. */
616 *p_invert
= ((GET_CODE (cmp1
) == CONST_INT
)
617 ? p_info
->invert_const
618 : p_info
->invert_reg
);
620 /* Comparison to constants, may involve adding 1 to change a LT into LE.
621 Comparison between two registers, may involve switching operands. */
622 if (GET_CODE (cmp1
) == CONST_INT
)
624 if (p_info
->const_add
!= 0)
625 cmp1
= GEN_INT (INTVAL (cmp1
) + p_info
->const_add
);
628 else if (p_info
->reverse_regs
)
635 return gen_rtx_fmt_ee (p_info
->test_code
, VOIDmode
, cmp0
, cmp1
);
639 /* Generate the code to compare two float values. The return value is
640 the comparison expression. */
643 gen_float_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
644 rtx cmp0
, /* first operand to compare */
645 rtx cmp1
/* second operand to compare */)
647 rtx (*gen_fn
) (rtx
, rtx
, rtx
);
649 int reverse_regs
, invert
;
653 case EQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_seq_sf
; break;
654 case NE
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_seq_sf
; break;
655 case LE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sle_sf
; break;
656 case GT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_slt_sf
; break;
657 case LT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_slt_sf
; break;
658 case GE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sle_sf
; break;
659 case UNEQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_suneq_sf
; break;
660 case LTGT
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_suneq_sf
; break;
661 case UNLE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunle_sf
; break;
662 case UNGT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
663 case UNLT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunlt_sf
; break;
664 case UNGE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sunle_sf
; break;
666 reverse_regs
= 0; invert
= 0; gen_fn
= gen_sunordered_sf
; break;
668 reverse_regs
= 0; invert
= 1; gen_fn
= gen_sunordered_sf
; break;
670 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
671 reverse_regs
= 0; invert
= 0; gen_fn
= 0; /* avoid compiler warnings */
681 brtmp
= gen_rtx_REG (CCmode
, FPCC_REGNUM
);
682 emit_insn (gen_fn (brtmp
, cmp0
, cmp1
));
684 return gen_rtx_fmt_ee (invert
? EQ
: NE
, VOIDmode
, brtmp
, const0_rtx
);
689 xtensa_expand_conditional_branch (rtx
*operands
, enum rtx_code test_code
)
691 enum cmp_type type
= branch_type
;
692 rtx cmp0
= branch_cmp
[0];
693 rtx cmp1
= branch_cmp
[1];
702 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
706 cmp
= gen_int_relational (test_code
, cmp0
, cmp1
, &invert
);
710 if (!TARGET_HARD_FLOAT
)
711 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
,
714 cmp
= gen_float_relational (test_code
, cmp0
, cmp1
);
718 /* Generate the branch. */
720 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
729 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
730 gen_rtx_IF_THEN_ELSE (VOIDmode
, cmp
,
737 gen_conditional_move (rtx cmp
)
739 enum rtx_code code
= GET_CODE (cmp
);
740 rtx op0
= branch_cmp
[0];
741 rtx op1
= branch_cmp
[1];
743 if (branch_type
== CMP_SI
)
745 /* Jump optimization calls get_condition() which canonicalizes
746 comparisons like (GE x <const>) to (GT x <const-1>).
747 Transform those comparisons back to GE, since that is the
748 comparison supported in Xtensa. We shouldn't have to
749 transform <LE x const> comparisons, because neither
750 xtensa_expand_conditional_branch() nor get_condition() will
753 if ((code
== GT
) && (op1
== constm1_rtx
))
758 cmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
760 if (boolean_operator (cmp
, VOIDmode
))
762 /* Swap the operands to make const0 second. */
763 if (op0
== const0_rtx
)
769 /* If not comparing against zero, emit a comparison (subtract). */
770 if (op1
!= const0_rtx
)
772 op0
= expand_binop (SImode
, sub_optab
, op0
, op1
,
773 0, 0, OPTAB_LIB_WIDEN
);
777 else if (branch_operator (cmp
, VOIDmode
))
779 /* Swap the operands to make const0 second. */
780 if (op0
== const0_rtx
)
787 case LT
: code
= GE
; break;
788 case GE
: code
= LT
; break;
789 default: gcc_unreachable ();
793 if (op1
!= const0_rtx
)
799 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
802 if (TARGET_HARD_FLOAT
&& (branch_type
== CMP_SF
))
803 return gen_float_relational (code
, op0
, op1
);
810 xtensa_expand_conditional_move (rtx
*operands
, int isflt
)
813 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
815 if (!(cmp
= gen_conditional_move (operands
[1])))
819 gen_fn
= (branch_type
== CMP_SI
820 ? gen_movsfcc_internal0
821 : gen_movsfcc_internal1
);
823 gen_fn
= (branch_type
== CMP_SI
824 ? gen_movsicc_internal0
825 : gen_movsicc_internal1
);
827 emit_insn (gen_fn (operands
[0], XEXP (cmp
, 0),
828 operands
[2], operands
[3], cmp
));
834 xtensa_expand_scc (rtx
*operands
)
836 rtx dest
= operands
[0];
837 rtx cmp
= operands
[1];
838 rtx one_tmp
, zero_tmp
;
839 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
841 if (!(cmp
= gen_conditional_move (cmp
)))
844 one_tmp
= gen_reg_rtx (SImode
);
845 zero_tmp
= gen_reg_rtx (SImode
);
846 emit_insn (gen_movsi (one_tmp
, const_true_rtx
));
847 emit_insn (gen_movsi (zero_tmp
, const0_rtx
));
849 gen_fn
= (branch_type
== CMP_SI
850 ? gen_movsicc_internal0
851 : gen_movsicc_internal1
);
852 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), one_tmp
, zero_tmp
, cmp
));
857 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
858 for the output, i.e., the input operands are twice as big as MODE. */
861 xtensa_split_operand_pair (rtx operands
[4], enum machine_mode mode
)
863 switch (GET_CODE (operands
[1]))
866 operands
[3] = gen_rtx_REG (mode
, REGNO (operands
[1]) + 1);
867 operands
[2] = gen_rtx_REG (mode
, REGNO (operands
[1]));
871 operands
[3] = adjust_address (operands
[1], mode
, GET_MODE_SIZE (mode
));
872 operands
[2] = adjust_address (operands
[1], mode
, 0);
877 split_double (operands
[1], &operands
[2], &operands
[3]);
884 switch (GET_CODE (operands
[0]))
887 operands
[1] = gen_rtx_REG (mode
, REGNO (operands
[0]) + 1);
888 operands
[0] = gen_rtx_REG (mode
, REGNO (operands
[0]));
892 operands
[1] = adjust_address (operands
[0], mode
, GET_MODE_SIZE (mode
));
893 operands
[0] = adjust_address (operands
[0], mode
, 0);
902 /* Emit insns to move operands[1] into operands[0].
903 Return 1 if we have written out everything that needs to be done to
904 do the move. Otherwise, return 0 and the caller will emit the move
908 xtensa_emit_move_sequence (rtx
*operands
, enum machine_mode mode
)
910 if (CONSTANT_P (operands
[1])
911 && (GET_CODE (operands
[1]) != CONST_INT
912 || !xtensa_simm12b (INTVAL (operands
[1]))))
915 operands
[1] = force_const_mem (SImode
, operands
[1]);
917 /* PC-relative loads are always SImode, and CONST16 is only
918 supported in the movsi pattern, so add a SUBREG for any other
923 if (register_operand (operands
[0], mode
))
925 operands
[0] = simplify_gen_subreg (SImode
, operands
[0], mode
, 0);
926 emit_move_insn (operands
[0], operands
[1]);
931 operands
[1] = force_reg (SImode
, operands
[1]);
932 operands
[1] = gen_lowpart_SUBREG (mode
, operands
[1]);
937 if (!(reload_in_progress
| reload_completed
)
938 && !xtensa_valid_move (mode
, operands
))
939 operands
[1] = force_reg (mode
, operands
[1]);
941 operands
[1] = xtensa_copy_incoming_a7 (operands
[1]);
943 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
944 instruction won't be recognized after reload, so we remove the
945 subreg and adjust mem accordingly. */
946 if (reload_in_progress
)
948 operands
[0] = fixup_subreg_mem (operands
[0]);
949 operands
[1] = fixup_subreg_mem (operands
[1]);
956 fixup_subreg_mem (rtx x
)
958 if (GET_CODE (x
) == SUBREG
959 && GET_CODE (SUBREG_REG (x
)) == REG
960 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
)
963 gen_rtx_SUBREG (GET_MODE (x
),
964 reg_equiv_mem
[REGNO (SUBREG_REG (x
))],
966 x
= alter_subreg (&temp
);
972 /* Check if an incoming argument in a7 is expected to be used soon and
973 if OPND is a register or register pair that includes a7. If so,
974 create a new pseudo and copy a7 into that pseudo at the very
975 beginning of the function, followed by the special "set_frame_ptr"
976 unspec_volatile insn. The return value is either the original
977 operand, if it is not a7, or the new pseudo containing a copy of
978 the incoming argument. This is necessary because the register
979 allocator will ignore conflicts with a7 and may either assign some
980 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
981 the incoming argument in a7. By copying the argument out of a7 as
982 the very first thing, and then immediately following that with an
983 unspec_volatile to keep the scheduler away, we should avoid any
984 problems. Putting the set_frame_ptr insn at the beginning, with
985 only the a7 copy before it, also makes it easier for the prologue
986 expander to initialize the frame pointer after the a7 copy and to
987 fix up the a7 copy to use the stack pointer instead of the frame
991 xtensa_copy_incoming_a7 (rtx opnd
)
995 enum machine_mode mode
;
997 if (!cfun
->machine
->need_a7_copy
)
1000 /* This function should never be called again once a7 has been copied. */
1001 gcc_assert (!cfun
->machine
->set_frame_ptr_insn
);
1003 mode
= GET_MODE (opnd
);
1005 /* The operand using a7 may come in a later instruction, so just return
1006 the original operand if it doesn't use a7. */
1008 if (GET_CODE (reg
) == SUBREG
)
1010 gcc_assert (SUBREG_BYTE (reg
) == 0);
1011 reg
= SUBREG_REG (reg
);
1013 if (GET_CODE (reg
) != REG
1014 || REGNO (reg
) > A7_REG
1015 || REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) <= A7_REG
)
1018 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1019 gcc_assert (REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) - 1 == A7_REG
);
1021 cfun
->machine
->need_a7_copy
= false;
1023 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1024 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1027 tmp
= gen_reg_rtx (mode
);
1033 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 0),
1034 gen_rtx_REG (SImode
, A7_REG
- 1)));
1035 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 4),
1036 gen_raw_REG (SImode
, A7_REG
)));
1039 emit_insn (gen_movsf_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1042 emit_insn (gen_movsi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1045 emit_insn (gen_movhi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1048 emit_insn (gen_movqi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1054 cfun
->machine
->set_frame_ptr_insn
= emit_insn (gen_set_frame_ptr ());
1055 entry_insns
= get_insns ();
1058 if (cfun
->machine
->vararg_a7
)
1060 /* This is called from within builtin_saveregs, which will insert the
1061 saveregs code at the function entry, ahead of anything placed at
1062 the function entry now. Instead, save the sequence to be inserted
1063 at the beginning of the saveregs code. */
1064 cfun
->machine
->vararg_a7_copy
= entry_insns
;
1068 /* Put entry_insns after the NOTE that starts the function. If
1069 this is inside a start_sequence, make the outer-level insn
1070 chain current, so the code is placed at the start of the
1072 push_topmost_sequence ();
1073 /* Do not use entry_of_function() here. This is called from within
1074 expand_function_start, when the CFG still holds GIMPLE. */
1075 emit_insn_after (entry_insns
, get_insns ());
1076 pop_topmost_sequence ();
1083 /* Try to expand a block move operation to a sequence of RTL move
1084 instructions. If not optimizing, or if the block size is not a
1085 constant, or if the block is too large, the expansion fails and GCC
1086 falls back to calling memcpy().
1088 operands[0] is the destination
1089 operands[1] is the source
1090 operands[2] is the length
1091 operands[3] is the alignment */
1094 xtensa_expand_block_move (rtx
*operands
)
1096 static const enum machine_mode mode_from_align
[] =
1098 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1101 rtx dst_mem
= operands
[0];
1102 rtx src_mem
= operands
[1];
1103 HOST_WIDE_INT bytes
, align
;
1104 int num_pieces
, move_ratio
;
1106 enum machine_mode mode
[2];
1115 /* If this is not a fixed size move, just call memcpy. */
1116 if (!optimize
|| (GET_CODE (operands
[2]) != CONST_INT
))
1119 bytes
= INTVAL (operands
[2]);
1120 align
= INTVAL (operands
[3]);
1122 /* Anything to move? */
1126 if (align
> MOVE_MAX
)
1129 /* Decide whether to expand inline based on the optimization level. */
1132 move_ratio
= LARGEST_MOVE_RATIO
;
1133 num_pieces
= (bytes
/ align
) + (bytes
% align
); /* Close enough anyway. */
1134 if (num_pieces
> move_ratio
)
1137 x
= XEXP (dst_mem
, 0);
1140 x
= force_reg (Pmode
, x
);
1141 dst_mem
= replace_equiv_address (dst_mem
, x
);
1144 x
= XEXP (src_mem
, 0);
1147 x
= force_reg (Pmode
, x
);
1148 src_mem
= replace_equiv_address (src_mem
, x
);
1151 active
[0] = active
[1] = false;
1162 next_amount
= (bytes
>= 4 ? 4 : (bytes
>= 2 ? 2 : 1));
1163 next_amount
= MIN (next_amount
, align
);
1165 amount
[next
] = next_amount
;
1166 mode
[next
] = mode_from_align
[next_amount
];
1167 temp
[next
] = gen_reg_rtx (mode
[next
]);
1169 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1170 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1172 offset_ld
+= next_amount
;
1173 bytes
-= next_amount
;
1174 active
[next
] = true;
1179 active
[phase
] = false;
1181 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1182 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1184 offset_st
+= amount
[phase
];
1187 while (active
[next
]);
1194 xtensa_expand_nonlocal_goto (rtx
*operands
)
1196 rtx goto_handler
= operands
[1];
1197 rtx containing_fp
= operands
[3];
1199 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1200 is too big to generate in-line. */
1202 if (GET_CODE (containing_fp
) != REG
)
1203 containing_fp
= force_reg (Pmode
, containing_fp
);
1205 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_nonlocal_goto"),
1207 containing_fp
, Pmode
,
1208 goto_handler
, Pmode
);
1212 static struct machine_function
*
1213 xtensa_init_machine_status (void)
1215 return GGC_CNEW (struct machine_function
);
1219 /* Shift VAL of mode MODE left by COUNT bits. */
1222 xtensa_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
1224 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
1225 NULL_RTX
, 1, OPTAB_DIRECT
);
1226 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
1227 NULL_RTX
, 1, OPTAB_DIRECT
);
1231 /* Structure to hold the initial parameters for a compare_and_swap operation
1232 in HImode and QImode. */
1234 struct alignment_context
1236 rtx memsi
; /* SI aligned memory location. */
1237 rtx shift
; /* Bit offset with regard to lsb. */
1238 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
1239 rtx modemaski
; /* ~modemask */
1243 /* Initialize structure AC for word access to HI and QI mode memory. */
1246 init_alignment_context (struct alignment_context
*ac
, rtx mem
)
1248 enum machine_mode mode
= GET_MODE (mem
);
1249 rtx byteoffset
= NULL_RTX
;
1250 bool aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
1253 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
1256 /* Alignment is unknown. */
1259 /* Force the address into a register. */
1260 addr
= force_reg (Pmode
, XEXP (mem
, 0));
1262 /* Align it to SImode. */
1263 align
= expand_simple_binop (Pmode
, AND
, addr
,
1264 GEN_INT (-GET_MODE_SIZE (SImode
)),
1265 NULL_RTX
, 1, OPTAB_DIRECT
);
1267 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
1268 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
1269 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
1270 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
1272 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
1273 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
1274 NULL_RTX
, 1, OPTAB_DIRECT
);
1277 /* Calculate shiftcount. */
1278 if (TARGET_BIG_ENDIAN
)
1280 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
1282 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
1283 NULL_RTX
, 1, OPTAB_DIRECT
);
1288 ac
->shift
= NULL_RTX
;
1290 ac
->shift
= byteoffset
;
1293 if (ac
->shift
!= NULL_RTX
)
1295 /* Shift is the byte count, but we need the bitcount. */
1296 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
,
1297 GEN_INT (BITS_PER_UNIT
),
1298 NULL_RTX
, 1, OPTAB_DIRECT
);
1299 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
1300 GEN_INT (GET_MODE_MASK (mode
)),
1302 NULL_RTX
, 1, OPTAB_DIRECT
);
1305 ac
->modemask
= GEN_INT (GET_MODE_MASK (mode
));
1307 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
1311 /* Expand an atomic compare and swap operation for HImode and QImode.
1312 MEM is the memory location, CMP the old value to compare MEM with
1313 and NEW the value to set if CMP == MEM. */
1316 xtensa_expand_compare_and_swap (rtx target
, rtx mem
, rtx cmp
, rtx
new)
1318 enum machine_mode mode
= GET_MODE (mem
);
1319 struct alignment_context ac
;
1320 rtx tmp
, cmpv
, newv
, val
;
1321 rtx oldval
= gen_reg_rtx (SImode
);
1322 rtx res
= gen_reg_rtx (SImode
);
1323 rtx csloop
= gen_label_rtx ();
1324 rtx csend
= gen_label_rtx ();
1326 init_alignment_context (&ac
, mem
);
1328 if (ac
.shift
!= NULL_RTX
)
1330 cmp
= xtensa_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
1331 new = xtensa_expand_mask_and_shift (new, mode
, ac
.shift
);
1334 /* Load the surrounding word into VAL with the MEM value masked out. */
1335 val
= force_reg (SImode
, expand_simple_binop (SImode
, AND
, ac
.memsi
,
1336 ac
.modemaski
, NULL_RTX
, 1,
1338 emit_label (csloop
);
1340 /* Patch CMP and NEW into VAL at correct position. */
1341 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
1342 NULL_RTX
, 1, OPTAB_DIRECT
));
1343 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new, val
,
1344 NULL_RTX
, 1, OPTAB_DIRECT
));
1346 /* Jump to end if we're done. */
1347 emit_insn (gen_sync_compare_and_swapsi (res
, ac
.memsi
, cmpv
, newv
));
1348 emit_cmp_and_jump_insns (res
, cmpv
, EQ
, const0_rtx
, SImode
, true, csend
);
1350 /* Check for changes outside mode. */
1351 emit_move_insn (oldval
, val
);
1352 tmp
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
1353 val
, 1, OPTAB_DIRECT
);
1355 emit_move_insn (val
, tmp
);
1357 /* Loop internal if so. */
1358 emit_cmp_and_jump_insns (oldval
, val
, NE
, const0_rtx
, SImode
, true, csloop
);
1362 /* Return the correct part of the bitfield. */
1363 convert_move (target
,
1364 (ac
.shift
== NULL_RTX
? res
1365 : expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
1366 NULL_RTX
, 1, OPTAB_DIRECT
)),
1371 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1372 the default expansion works fine for SImode). MEM is the memory location
1373 and VAL the value to play with. If AFTER is true then store the value
1374 MEM holds after the operation, if AFTER is false then store the value MEM
1375 holds before the operation. If TARGET is zero then discard that value, else
1376 store it to TARGET. */
1379 xtensa_expand_atomic (enum rtx_code code
, rtx target
, rtx mem
, rtx val
,
1382 enum machine_mode mode
= GET_MODE (mem
);
1383 struct alignment_context ac
;
1384 rtx csloop
= gen_label_rtx ();
1386 rtx old
= gen_reg_rtx (SImode
);
1387 rtx
new = gen_reg_rtx (SImode
);
1388 rtx orig
= NULL_RTX
;
1390 init_alignment_context (&ac
, mem
);
1392 /* Prepare values before the compare-and-swap loop. */
1393 if (ac
.shift
!= NULL_RTX
)
1394 val
= xtensa_expand_mask_and_shift (val
, mode
, ac
.shift
);
1399 orig
= gen_reg_rtx (SImode
);
1400 convert_move (orig
, val
, 1);
1408 case MULT
: /* NAND */
1410 /* val = "11..1<val>11..1" */
1411 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
1412 NULL_RTX
, 1, OPTAB_DIRECT
);
1419 /* Load full word. Subsequent loads are performed by S32C1I. */
1420 cmp
= force_reg (SImode
, ac
.memsi
);
1422 emit_label (csloop
);
1423 emit_move_insn (old
, cmp
);
1429 val
= expand_simple_binop (SImode
, code
, old
, orig
,
1430 NULL_RTX
, 1, OPTAB_DIRECT
);
1431 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
1432 NULL_RTX
, 1, OPTAB_DIRECT
);
1435 tmp
= expand_simple_binop (SImode
, AND
, old
, ac
.modemaski
,
1436 NULL_RTX
, 1, OPTAB_DIRECT
);
1437 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
,
1438 new, 1, OPTAB_DIRECT
);
1444 tmp
= expand_simple_binop (SImode
, code
, old
, val
,
1445 new, 1, OPTAB_DIRECT
);
1448 case MULT
: /* NAND */
1449 tmp
= expand_simple_binop (SImode
, XOR
, old
, ac
.modemask
,
1450 NULL_RTX
, 1, OPTAB_DIRECT
);
1451 tmp
= expand_simple_binop (SImode
, AND
, tmp
, val
,
1452 new, 1, OPTAB_DIRECT
);
1460 emit_move_insn (new, tmp
);
1461 emit_insn (gen_sync_compare_and_swapsi (cmp
, ac
.memsi
, old
, new));
1462 emit_cmp_and_jump_insns (cmp
, old
, NE
, const0_rtx
, SImode
, true, csloop
);
1466 tmp
= (after
? new : cmp
);
1467 convert_move (target
,
1468 (ac
.shift
== NULL_RTX
? tmp
1469 : expand_simple_binop (SImode
, LSHIFTRT
, tmp
, ac
.shift
,
1470 NULL_RTX
, 1, OPTAB_DIRECT
)),
1477 xtensa_setup_frame_addresses (void)
1479 /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
1480 cfun
->machine
->accesses_prev_frame
= 1;
1483 (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_libgcc_window_spill"),
1488 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1489 a comment showing where the end of the loop is. However, if there is a
1490 label or a branch at the end of the loop then we need to place a nop
1491 there. If the loop ends with a label we need the nop so that branches
1492 targeting that label will target the nop (and thus remain in the loop),
1493 instead of targeting the instruction after the loop (and thus exiting
1494 the loop). If the loop ends with a branch, we need the nop in case the
1495 branch is targeting a location inside the loop. When the branch
1496 executes it will cause the loop count to be decremented even if it is
1497 taken (because it is the last instruction in the loop), so we need to
1498 nop after the branch to prevent the loop count from being decremented
1499 when the branch is taken. */
1502 xtensa_emit_loop_end (rtx insn
, rtx
*operands
)
1506 for (insn
= PREV_INSN (insn
); insn
&& !done
; insn
= PREV_INSN (insn
))
1508 switch (GET_CODE (insn
))
1515 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1521 rtx body
= PATTERN (insn
);
1523 if (GET_CODE (body
) == JUMP_INSN
)
1525 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1528 else if ((GET_CODE (body
) != USE
)
1529 && (GET_CODE (body
) != CLOBBER
))
1536 output_asm_insn ("# loop end for %0", operands
);
1541 xtensa_emit_branch (bool inverted
, bool immed
, rtx
*operands
)
1543 static char result
[64];
1547 code
= GET_CODE (operands
[3]);
1550 case EQ
: op
= inverted
? "ne" : "eq"; break;
1551 case NE
: op
= inverted
? "eq" : "ne"; break;
1552 case LT
: op
= inverted
? "ge" : "lt"; break;
1553 case GE
: op
= inverted
? "lt" : "ge"; break;
1554 case LTU
: op
= inverted
? "geu" : "ltu"; break;
1555 case GEU
: op
= inverted
? "ltu" : "geu"; break;
1556 default: gcc_unreachable ();
1561 if (INTVAL (operands
[1]) == 0)
1562 sprintf (result
, "b%sz%s\t%%0, %%2", op
,
1563 (TARGET_DENSITY
&& (code
== EQ
|| code
== NE
)) ? ".n" : "");
1565 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1568 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1575 xtensa_emit_bit_branch (bool inverted
, bool immed
, rtx
*operands
)
1577 static char result
[64];
1580 switch (GET_CODE (operands
[3]))
1582 case EQ
: op
= inverted
? "bs" : "bc"; break;
1583 case NE
: op
= inverted
? "bc" : "bs"; break;
1584 default: gcc_unreachable ();
1589 unsigned bitnum
= INTVAL (operands
[1]) & 0x1f;
1590 operands
[1] = GEN_INT (bitnum
);
1591 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1594 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1601 xtensa_emit_movcc (bool inverted
, bool isfp
, bool isbool
, rtx
*operands
)
1603 static char result
[64];
1607 code
= GET_CODE (operands
[4]);
1612 case EQ
: op
= inverted
? "t" : "f"; break;
1613 case NE
: op
= inverted
? "f" : "t"; break;
1614 default: gcc_unreachable ();
1621 case EQ
: op
= inverted
? "nez" : "eqz"; break;
1622 case NE
: op
= inverted
? "eqz" : "nez"; break;
1623 case LT
: op
= inverted
? "gez" : "ltz"; break;
1624 case GE
: op
= inverted
? "ltz" : "gez"; break;
1625 default: gcc_unreachable ();
1629 sprintf (result
, "mov%s%s\t%%0, %%%d, %%1",
1630 op
, isfp
? ".s" : "", inverted
? 3 : 2);
1636 xtensa_emit_call (int callop
, rtx
*operands
)
1638 static char result
[64];
1639 rtx tgt
= operands
[callop
];
1641 if (GET_CODE (tgt
) == CONST_INT
)
1642 sprintf (result
, "call8\t0x%lx", INTVAL (tgt
));
1643 else if (register_operand (tgt
, VOIDmode
))
1644 sprintf (result
, "callx8\t%%%d", callop
);
1646 sprintf (result
, "call8\t%%%d", callop
);
1653 xtensa_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
1655 /* Allow constant pool addresses. */
1656 if (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
1657 && ! TARGET_CONST16
&& constantpool_address_p (addr
))
1660 while (GET_CODE (addr
) == SUBREG
)
1661 addr
= SUBREG_REG (addr
);
1663 /* Allow base registers. */
1664 if (GET_CODE (addr
) == REG
&& BASE_REG_P (addr
, strict
))
1667 /* Check for "register + offset" addressing. */
1668 if (GET_CODE (addr
) == PLUS
)
1670 rtx xplus0
= XEXP (addr
, 0);
1671 rtx xplus1
= XEXP (addr
, 1);
1672 enum rtx_code code0
;
1673 enum rtx_code code1
;
1675 while (GET_CODE (xplus0
) == SUBREG
)
1676 xplus0
= SUBREG_REG (xplus0
);
1677 code0
= GET_CODE (xplus0
);
1679 while (GET_CODE (xplus1
) == SUBREG
)
1680 xplus1
= SUBREG_REG (xplus1
);
1681 code1
= GET_CODE (xplus1
);
1683 /* Swap operands if necessary so the register is first. */
1684 if (code0
!= REG
&& code1
== REG
)
1686 xplus0
= XEXP (addr
, 1);
1687 xplus1
= XEXP (addr
, 0);
1688 code0
= GET_CODE (xplus0
);
1689 code1
= GET_CODE (xplus1
);
1692 if (code0
== REG
&& BASE_REG_P (xplus0
, strict
)
1693 && code1
== CONST_INT
1694 && xtensa_mem_offset (INTVAL (xplus1
), mode
))
1703 xtensa_legitimize_address (rtx x
,
1704 rtx oldx ATTRIBUTE_UNUSED
,
1705 enum machine_mode mode
)
1707 if (GET_CODE (x
) == PLUS
)
1709 rtx plus0
= XEXP (x
, 0);
1710 rtx plus1
= XEXP (x
, 1);
1712 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1714 plus0
= XEXP (x
, 1);
1715 plus1
= XEXP (x
, 0);
1718 /* Try to split up the offset to use an ADDMI instruction. */
1719 if (GET_CODE (plus0
) == REG
1720 && GET_CODE (plus1
) == CONST_INT
1721 && !xtensa_mem_offset (INTVAL (plus1
), mode
)
1722 && !xtensa_simm8 (INTVAL (plus1
))
1723 && xtensa_mem_offset (INTVAL (plus1
) & 0xff, mode
)
1724 && xtensa_simm8x256 (INTVAL (plus1
) & ~0xff))
1726 rtx temp
= gen_reg_rtx (Pmode
);
1727 rtx addmi_offset
= GEN_INT (INTVAL (plus1
) & ~0xff);
1728 emit_insn (gen_rtx_SET (Pmode
, temp
,
1729 gen_rtx_PLUS (Pmode
, plus0
, addmi_offset
)));
1730 return gen_rtx_PLUS (Pmode
, temp
, GEN_INT (INTVAL (plus1
) & 0xff));
1738 /* Return the debugger register number to use for 'regno'. */
1741 xtensa_dbx_register_number (int regno
)
1745 if (GP_REG_P (regno
))
1747 regno
-= GP_REG_FIRST
;
1750 else if (BR_REG_P (regno
))
1752 regno
-= BR_REG_FIRST
;
1755 else if (FP_REG_P (regno
))
1757 regno
-= FP_REG_FIRST
;
1760 else if (ACC_REG_P (regno
))
1762 first
= 0x200; /* Start of Xtensa special registers. */
1763 regno
= 16; /* ACCLO is special register 16. */
1766 /* When optimizing, we sometimes get asked about pseudo-registers
1767 that don't represent hard registers. Return 0 for these. */
1771 return first
+ regno
;
1775 /* Argument support functions. */
1777 /* Initialize CUMULATIVE_ARGS for a function. */
1780 init_cumulative_args (CUMULATIVE_ARGS
*cum
, int incoming
)
1783 cum
->incoming
= incoming
;
1787 /* Advance the argument to the next argument position. */
1790 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
)
1795 arg_words
= &cum
->arg_words
;
1796 max
= MAX_ARGS_IN_REGISTERS
;
1798 words
= (((mode
!= BLKmode
)
1799 ? (int) GET_MODE_SIZE (mode
)
1800 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1802 if (*arg_words
< max
1803 && (targetm
.calls
.must_pass_in_stack (mode
, type
)
1804 || *arg_words
+ words
> max
))
1807 *arg_words
+= words
;
1811 /* Return an RTL expression containing the register for the given mode,
1812 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
1813 if this is an incoming argument to the current function. */
1816 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1819 int regbase
, words
, max
;
1823 arg_words
= &cum
->arg_words
;
1824 regbase
= (incoming_p
? GP_ARG_FIRST
: GP_OUTGOING_ARG_FIRST
);
1825 max
= MAX_ARGS_IN_REGISTERS
;
1827 words
= (((mode
!= BLKmode
)
1828 ? (int) GET_MODE_SIZE (mode
)
1829 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1831 if (type
&& (TYPE_ALIGN (type
) > BITS_PER_WORD
))
1833 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_WORD
;
1834 *arg_words
= (*arg_words
+ align
- 1) & -align
;
1837 if (*arg_words
+ words
> max
)
1840 regno
= regbase
+ *arg_words
;
1842 if (cum
->incoming
&& regno
<= A7_REG
&& regno
+ words
> A7_REG
)
1843 cfun
->machine
->need_a7_copy
= true;
1845 return gen_rtx_REG (mode
, regno
);
1850 function_arg_boundary (enum machine_mode mode
, tree type
)
1852 unsigned int alignment
;
1854 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
1855 if (alignment
< PARM_BOUNDARY
)
1856 alignment
= PARM_BOUNDARY
;
1857 if (alignment
> STACK_BOUNDARY
)
1858 alignment
= STACK_BOUNDARY
;
1864 xtensa_return_in_msb (const_tree valtype
)
1866 return (TARGET_BIG_ENDIAN
1867 && AGGREGATE_TYPE_P (valtype
)
1868 && int_size_in_bytes (valtype
) >= UNITS_PER_WORD
);
1873 override_options (void)
1876 enum machine_mode mode
;
1878 if (!TARGET_BOOLEANS
&& TARGET_HARD_FLOAT
)
1879 error ("boolean registers required for the floating-point option");
1881 /* Set up array giving whether a given register can hold a given mode. */
1882 for (mode
= VOIDmode
;
1883 mode
!= MAX_MACHINE_MODE
;
1884 mode
= (enum machine_mode
) ((int) mode
+ 1))
1886 int size
= GET_MODE_SIZE (mode
);
1887 enum mode_class
class = GET_MODE_CLASS (mode
);
1889 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1893 if (ACC_REG_P (regno
))
1894 temp
= (TARGET_MAC16
1895 && (class == MODE_INT
) && (size
<= UNITS_PER_WORD
));
1896 else if (GP_REG_P (regno
))
1897 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
1898 else if (FP_REG_P (regno
))
1899 temp
= (TARGET_HARD_FLOAT
&& (mode
== SFmode
));
1900 else if (BR_REG_P (regno
))
1901 temp
= (TARGET_BOOLEANS
&& (mode
== CCmode
));
1905 xtensa_hard_regno_mode_ok
[(int) mode
][regno
] = temp
;
1909 init_machine_status
= xtensa_init_machine_status
;
1911 /* Check PIC settings. PIC is only supported when using L32R
1912 instructions, and some targets need to always use PIC. */
1913 if (flag_pic
&& TARGET_CONST16
)
1914 error ("-f%s is not supported with CONST16 instructions",
1915 (flag_pic
> 1 ? "PIC" : "pic"));
1916 else if (XTENSA_ALWAYS_PIC
)
1919 error ("PIC is required but not supported with CONST16 instructions");
1922 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
1925 if (flag_pic
&& !flag_pie
)
1928 /* Hot/cold partitioning does not work on this architecture, because of
1929 constant pools (the load instruction cannot necessarily reach that far).
1930 Therefore disable it on this architecture. */
1931 if (flag_reorder_blocks_and_partition
)
1933 flag_reorder_blocks_and_partition
= 0;
1934 flag_reorder_blocks
= 1;
1939 /* A C compound statement to output to stdio stream STREAM the
1940 assembler syntax for an instruction operand X. X is an RTL
1943 CODE is a value that can be used to specify one of several ways
1944 of printing the operand. It is used when identical operands
1945 must be printed differently depending on the context. CODE
1946 comes from the '%' specification that was used to request
1947 printing of the operand. If the specification was just '%DIGIT'
1948 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
1949 is the ASCII code for LTR.
1951 If X is a register, this macro should print the register's name.
1952 The names can be found in an array 'reg_names' whose type is
1953 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
1955 When the machine description has a specification '%PUNCT' (a '%'
1956 followed by a punctuation character), this macro is called with
1957 a null pointer for X and the punctuation character for CODE.
1959 'a', 'c', 'l', and 'n' are reserved.
1961 The Xtensa specific codes are:
1963 'd' CONST_INT, print as signed decimal
1964 'x' CONST_INT, print as signed hexadecimal
1965 'K' CONST_INT, print number of bits in mask for EXTUI
1966 'R' CONST_INT, print (X & 0x1f)
1967 'L' CONST_INT, print ((32 - X) & 0x1f)
1968 'D' REG, print second register of double-word register operand
1969 'N' MEM, print address of next word following a memory operand
1970 'v' MEM, if memory reference is volatile, output a MEMW before it
1971 't' any constant, add "@h" suffix for top 16 bits
1972 'b' any constant, add "@l" suffix for bottom 16 bits
1976 printx (FILE *file
, signed int val
)
1978 /* Print a hexadecimal value in a nice way. */
1979 if ((val
> -0xa) && (val
< 0xa))
1980 fprintf (file
, "%d", val
);
1982 fprintf (file
, "-0x%x", -val
);
1984 fprintf (file
, "0x%x", val
);
1989 print_operand (FILE *file
, rtx x
, int letter
)
1992 error ("PRINT_OPERAND null pointer");
1997 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
1998 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
) + 1]);
2000 output_operand_lossage ("invalid %%D value");
2004 if (GET_CODE (x
) == MEM
)
2006 /* For a volatile memory reference, emit a MEMW before the
2008 if (MEM_VOLATILE_P (x
) && TARGET_SERIALIZE_VOLATILE
)
2009 fprintf (file
, "memw\n\t");
2012 output_operand_lossage ("invalid %%v value");
2016 if (GET_CODE (x
) == MEM
2017 && (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DImode
))
2019 x
= adjust_address (x
, GET_MODE (x
) == DFmode
? SFmode
: SImode
, 4);
2020 output_address (XEXP (x
, 0));
2023 output_operand_lossage ("invalid %%N value");
2027 if (GET_CODE (x
) == CONST_INT
)
2030 unsigned val
= INTVAL (x
);
2036 if ((val
!= 0) || (num_bits
== 0) || (num_bits
> 16))
2037 fatal_insn ("invalid mask", x
);
2039 fprintf (file
, "%d", num_bits
);
2042 output_operand_lossage ("invalid %%K value");
2046 if (GET_CODE (x
) == CONST_INT
)
2047 fprintf (file
, "%ld", (32 - INTVAL (x
)) & 0x1f);
2049 output_operand_lossage ("invalid %%L value");
2053 if (GET_CODE (x
) == CONST_INT
)
2054 fprintf (file
, "%ld", INTVAL (x
) & 0x1f);
2056 output_operand_lossage ("invalid %%R value");
2060 if (GET_CODE (x
) == CONST_INT
)
2061 printx (file
, INTVAL (x
));
2063 output_operand_lossage ("invalid %%x value");
2067 if (GET_CODE (x
) == CONST_INT
)
2068 fprintf (file
, "%ld", INTVAL (x
));
2070 output_operand_lossage ("invalid %%d value");
2075 if (GET_CODE (x
) == CONST_INT
)
2077 printx (file
, INTVAL (x
));
2078 fputs (letter
== 't' ? "@h" : "@l", file
);
2080 else if (GET_CODE (x
) == CONST_DOUBLE
)
2083 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2084 if (GET_MODE (x
) == SFmode
)
2087 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2088 fprintf (file
, "0x%08lx@%c", l
, letter
== 't' ? 'h' : 'l');
2091 output_operand_lossage ("invalid %%t/%%b value");
2093 else if (GET_CODE (x
) == CONST
)
2095 /* X must be a symbolic constant on ELF. Write an expression
2096 suitable for 'const16' that sets the high or low 16 bits. */
2097 if (GET_CODE (XEXP (x
, 0)) != PLUS
2098 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
2099 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
2100 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
2101 output_operand_lossage ("invalid %%t/%%b value");
2102 print_operand (file
, XEXP (XEXP (x
, 0), 0), 0);
2103 fputs (letter
== 't' ? "@h" : "@l", file
);
2104 /* There must be a non-alphanumeric character between 'h' or 'l'
2105 and the number. The '-' is added by print_operand() already. */
2106 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
2108 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
2112 output_addr_const (file
, x
);
2113 fputs (letter
== 't' ? "@h" : "@l", file
);
2118 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2119 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
)]);
2120 else if (GET_CODE (x
) == MEM
)
2121 output_address (XEXP (x
, 0));
2122 else if (GET_CODE (x
) == CONST_INT
)
2123 fprintf (file
, "%ld", INTVAL (x
));
2125 output_addr_const (file
, x
);
2130 /* A C compound statement to output to stdio stream STREAM the
2131 assembler syntax for an instruction operand that is a memory
2132 reference whose address is ADDR. ADDR is an RTL expression. */
2135 print_operand_address (FILE *file
, rtx addr
)
2138 error ("PRINT_OPERAND_ADDRESS, null pointer");
2140 switch (GET_CODE (addr
))
2143 fatal_insn ("invalid address", addr
);
2147 fprintf (file
, "%s, 0", reg_names
[REGNO (addr
)]);
2153 rtx offset
= (rtx
)0;
2154 rtx arg0
= XEXP (addr
, 0);
2155 rtx arg1
= XEXP (addr
, 1);
2157 if (GET_CODE (arg0
) == REG
)
2162 else if (GET_CODE (arg1
) == REG
)
2168 fatal_insn ("no register in address", addr
);
2170 if (CONSTANT_P (offset
))
2172 fprintf (file
, "%s, ", reg_names
[REGNO (reg
)]);
2173 output_addr_const (file
, offset
);
2176 fatal_insn ("address offset not a constant", addr
);
2184 output_addr_const (file
, addr
);
2191 xtensa_output_addr_const_extra (FILE *fp
, rtx x
)
2193 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
2195 switch (XINT (x
, 1))
2200 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2214 xtensa_output_literal (FILE *file
, rtx x
, enum machine_mode mode
, int labelno
)
2221 fprintf (file
, "\t.literal .LC%u, ", (unsigned) labelno
);
2223 switch (GET_MODE_CLASS (mode
))
2226 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
);
2228 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2232 REAL_VALUE_TO_TARGET_SINGLE (r
, value_long
[0]);
2233 if (HOST_BITS_PER_LONG
> 32)
2234 value_long
[0] &= 0xffffffff;
2235 fprintf (file
, "0x%08lx\n", value_long
[0]);
2239 REAL_VALUE_TO_TARGET_DOUBLE (r
, value_long
);
2240 if (HOST_BITS_PER_LONG
> 32)
2242 value_long
[0] &= 0xffffffff;
2243 value_long
[1] &= 0xffffffff;
2245 fprintf (file
, "0x%08lx, 0x%08lx\n",
2246 value_long
[0], value_long
[1]);
2256 case MODE_PARTIAL_INT
:
2257 size
= GET_MODE_SIZE (mode
);
2261 output_addr_const (file
, x
);
2266 split_double (x
, &first
, &second
);
2267 output_addr_const (file
, first
);
2269 output_addr_const (file
, second
);
2284 /* Return the bytes needed to compute the frame pointer from the current
2287 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2288 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2291 compute_frame_size (int size
)
2293 /* Add space for the incoming static chain value. */
2294 if (cfun
->static_chain_decl
!= NULL
)
2295 size
+= (1 * UNITS_PER_WORD
);
2297 xtensa_current_frame_size
=
2298 XTENSA_STACK_ALIGN (size
2299 + crtl
->outgoing_args_size
2300 + (WINDOW_SIZE
* UNITS_PER_WORD
));
2301 return xtensa_current_frame_size
;
2306 xtensa_frame_pointer_required (void)
2308 /* The code to expand builtin_frame_addr and builtin_return_addr
2309 currently uses the hard_frame_pointer instead of frame_pointer.
2310 This seems wrong but maybe it's necessary for other architectures.
2311 This function is derived from the i386 code. */
2313 if (cfun
->machine
->accesses_prev_frame
)
2320 /* minimum frame = reg save area (4 words) plus static chain (1 word)
2321 and the total number of words must be a multiple of 128 bits. */
2322 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD)
2325 xtensa_expand_prologue (void)
2327 HOST_WIDE_INT total_size
;
2331 total_size
= compute_frame_size (get_frame_size ());
2332 size_rtx
= GEN_INT (total_size
);
2334 if (total_size
< (1 << (12+3)))
2335 insn
= emit_insn (gen_entry (size_rtx
));
2338 /* Use a8 as a temporary since a0-a7 may be live. */
2339 rtx tmp_reg
= gen_rtx_REG (Pmode
, A8_REG
);
2340 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE
)));
2341 emit_move_insn (tmp_reg
, GEN_INT (total_size
- MIN_FRAME_SIZE
));
2342 emit_insn (gen_subsi3 (tmp_reg
, stack_pointer_rtx
, tmp_reg
));
2343 insn
= emit_insn (gen_movsi (stack_pointer_rtx
, tmp_reg
));
2346 if (frame_pointer_needed
)
2348 if (cfun
->machine
->set_frame_ptr_insn
)
2352 push_topmost_sequence ();
2353 first
= get_insns ();
2354 pop_topmost_sequence ();
2356 /* For all instructions prior to set_frame_ptr_insn, replace
2357 hard_frame_pointer references with stack_pointer. */
2359 insn
!= cfun
->machine
->set_frame_ptr_insn
;
2360 insn
= NEXT_INSN (insn
))
2364 PATTERN (insn
) = replace_rtx (copy_rtx (PATTERN (insn
)),
2365 hard_frame_pointer_rtx
,
2367 df_insn_rescan (insn
);
2372 insn
= emit_insn (gen_movsi (hard_frame_pointer_rtx
,
2373 stack_pointer_rtx
));
2376 /* Create a note to describe the CFA. Because this is only used to set
2377 DW_AT_frame_base for debug info, don't bother tracking changes through
2378 each instruction in the prologue. It just takes up space. */
2379 note_rtx
= gen_rtx_SET (VOIDmode
, (frame_pointer_needed
2380 ? hard_frame_pointer_rtx
2381 : stack_pointer_rtx
),
2382 plus_constant (stack_pointer_rtx
, -total_size
));
2383 RTX_FRAME_RELATED_P (insn
) = 1;
2384 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
2385 note_rtx
, REG_NOTES (insn
));
2389 /* Clear variables at function end. */
2392 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
2393 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
2395 xtensa_current_frame_size
= 0;
2400 xtensa_return_addr (int count
, rtx frame
)
2402 rtx result
, retaddr
, curaddr
, label
;
2405 retaddr
= gen_rtx_REG (Pmode
, A0_REG
);
2408 rtx addr
= plus_constant (frame
, -4 * UNITS_PER_WORD
);
2409 addr
= memory_address (Pmode
, addr
);
2410 retaddr
= gen_reg_rtx (Pmode
);
2411 emit_move_insn (retaddr
, gen_rtx_MEM (Pmode
, addr
));
2414 /* The 2 most-significant bits of the return address on Xtensa hold
2415 the register window size. To get the real return address, these
2416 bits must be replaced with the high bits from some address in the
2419 /* Get the 2 high bits of a local label in the code. */
2420 curaddr
= gen_reg_rtx (Pmode
);
2421 label
= gen_label_rtx ();
2423 LABEL_PRESERVE_P (label
) = 1;
2424 emit_move_insn (curaddr
, gen_rtx_LABEL_REF (Pmode
, label
));
2425 emit_insn (gen_lshrsi3 (curaddr
, curaddr
, GEN_INT (30)));
2426 emit_insn (gen_ashlsi3 (curaddr
, curaddr
, GEN_INT (30)));
2428 /* Clear the 2 high bits of the return address. */
2429 result
= gen_reg_rtx (Pmode
);
2430 emit_insn (gen_ashlsi3 (result
, retaddr
, GEN_INT (2)));
2431 emit_insn (gen_lshrsi3 (result
, result
, GEN_INT (2)));
2433 /* Combine them to get the result. */
2434 emit_insn (gen_iorsi3 (result
, result
, curaddr
));
2439 /* Create the va_list data type.
2441 This structure is set up by __builtin_saveregs. The __va_reg field
2442 points to a stack-allocated region holding the contents of the
2443 incoming argument registers. The __va_ndx field is an index
2444 initialized to the position of the first unnamed (variable)
2445 argument. This same index is also used to address the arguments
2446 passed in memory. Thus, the __va_stk field is initialized to point
2447 to the position of the first argument in memory offset to account
2448 for the arguments passed in registers and to account for the size
2449 of the argument registers not being 16-byte aligned. E.G., there
2450 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2451 for the first stack argument to have the maximal alignment of 16
2452 bytes, so we offset the __va_stk address by 32 bytes so that
2453 __va_stk[32] references the first argument on the stack. */
2456 xtensa_build_builtin_va_list (void)
2458 tree f_stk
, f_reg
, f_ndx
, record
, type_decl
;
2460 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
2461 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
2463 f_stk
= build_decl (FIELD_DECL
, get_identifier ("__va_stk"),
2465 f_reg
= build_decl (FIELD_DECL
, get_identifier ("__va_reg"),
2467 f_ndx
= build_decl (FIELD_DECL
, get_identifier ("__va_ndx"),
2470 DECL_FIELD_CONTEXT (f_stk
) = record
;
2471 DECL_FIELD_CONTEXT (f_reg
) = record
;
2472 DECL_FIELD_CONTEXT (f_ndx
) = record
;
2474 TREE_CHAIN (record
) = type_decl
;
2475 TYPE_NAME (record
) = type_decl
;
2476 TYPE_FIELDS (record
) = f_stk
;
2477 TREE_CHAIN (f_stk
) = f_reg
;
2478 TREE_CHAIN (f_reg
) = f_ndx
;
2480 layout_type (record
);
2485 /* Save the incoming argument registers on the stack. Returns the
2486 address of the saved registers. */
2489 xtensa_builtin_saveregs (void)
2492 int arg_words
= crtl
->args
.info
.arg_words
;
2493 int gp_left
= MAX_ARGS_IN_REGISTERS
- arg_words
;
2498 /* Allocate the general-purpose register space. */
2499 gp_regs
= assign_stack_local
2500 (BLKmode
, MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
, -1);
2501 set_mem_alias_set (gp_regs
, get_varargs_alias_set ());
2503 /* Now store the incoming registers. */
2504 cfun
->machine
->need_a7_copy
= true;
2505 cfun
->machine
->vararg_a7
= true;
2506 move_block_from_reg (GP_ARG_FIRST
+ arg_words
,
2507 adjust_address (gp_regs
, BLKmode
,
2508 arg_words
* UNITS_PER_WORD
),
2510 gcc_assert (cfun
->machine
->vararg_a7_copy
!= 0);
2511 emit_insn_before (cfun
->machine
->vararg_a7_copy
, get_insns ());
2513 return XEXP (gp_regs
, 0);
2517 /* Implement `va_start' for varargs and stdarg. We look at the
2518 current function to fill in an initial va_list. */
2521 xtensa_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
2529 arg_words
= crtl
->args
.info
.arg_words
;
2531 f_stk
= TYPE_FIELDS (va_list_type_node
);
2532 f_reg
= TREE_CHAIN (f_stk
);
2533 f_ndx
= TREE_CHAIN (f_reg
);
2535 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
2536 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), valist
, f_reg
, NULL_TREE
);
2537 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), valist
, f_ndx
, NULL_TREE
);
2539 /* Call __builtin_saveregs; save the result in __va_reg */
2540 u
= make_tree (sizetype
, expand_builtin_saveregs ());
2541 u
= fold_convert (ptr_type_node
, u
);
2542 t
= build2 (MODIFY_EXPR
, ptr_type_node
, reg
, u
);
2543 TREE_SIDE_EFFECTS (t
) = 1;
2544 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2546 /* Set the __va_stk member to ($arg_ptr - 32). */
2547 u
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
2548 u
= fold_build2 (POINTER_PLUS_EXPR
, ptr_type_node
, u
, size_int (-32));
2549 t
= build2 (MODIFY_EXPR
, ptr_type_node
, stk
, u
);
2550 TREE_SIDE_EFFECTS (t
) = 1;
2551 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2553 /* Set the __va_ndx member. If the first variable argument is on
2554 the stack, adjust __va_ndx by 2 words to account for the extra
2555 alignment offset for __va_stk. */
2556 if (arg_words
>= MAX_ARGS_IN_REGISTERS
)
2558 t
= build2 (MODIFY_EXPR
, integer_type_node
, ndx
,
2559 build_int_cst (integer_type_node
, arg_words
* UNITS_PER_WORD
));
2560 TREE_SIDE_EFFECTS (t
) = 1;
2561 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2565 /* Implement `va_arg'. */
2568 xtensa_gimplify_va_arg_expr (tree valist
, tree type
, gimple_seq
*pre_p
,
2569 gimple_seq
*post_p ATTRIBUTE_UNUSED
)
2574 tree type_size
, array
, orig_ndx
, addr
, size
, va_size
, t
;
2575 tree lab_false
, lab_over
, lab_false2
;
2578 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
2580 type
= build_pointer_type (type
);
2582 /* Handle complex values as separate real and imaginary parts. */
2583 if (TREE_CODE (type
) == COMPLEX_TYPE
)
2585 tree real_part
, imag_part
;
2587 real_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
2589 real_part
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
2591 imag_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
2593 imag_part
= get_initialized_tmp_var (imag_part
, pre_p
, NULL
);
2595 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
2598 f_stk
= TYPE_FIELDS (va_list_type_node
);
2599 f_reg
= TREE_CHAIN (f_stk
);
2600 f_ndx
= TREE_CHAIN (f_reg
);
2602 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
2603 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), valist
, f_reg
, NULL_TREE
);
2604 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), valist
, f_ndx
, NULL_TREE
);
2606 type_size
= size_in_bytes (type
);
2607 va_size
= round_up (type_size
, UNITS_PER_WORD
);
2608 gimplify_expr (&va_size
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
2611 /* First align __va_ndx if necessary for this arg:
2613 orig_ndx = (AP).__va_ndx;
2614 if (__alignof__ (TYPE) > 4 )
2615 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2616 & -__alignof__ (TYPE)); */
2618 orig_ndx
= get_initialized_tmp_var (ndx
, pre_p
, NULL
);
2620 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
2622 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_UNIT
;
2624 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
,
2625 build_int_cst (integer_type_node
, align
- 1));
2626 t
= build2 (BIT_AND_EXPR
, integer_type_node
, t
,
2627 build_int_cst (integer_type_node
, -align
));
2628 gimplify_assign (orig_ndx
, t
, pre_p
);
2632 /* Increment __va_ndx to point past the argument:
2634 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2636 t
= fold_convert (integer_type_node
, va_size
);
2637 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
, t
);
2638 gimplify_assign (ndx
, t
, pre_p
);
2641 /* Check if the argument is in registers:
2643 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2644 && !must_pass_in_stack (type))
2645 __array = (AP).__va_reg; */
2647 array
= create_tmp_var (ptr_type_node
, NULL
);
2650 if (!targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
2652 lab_false
= create_artificial_label ();
2653 lab_over
= create_artificial_label ();
2655 t
= build2 (GT_EXPR
, boolean_type_node
, ndx
,
2656 build_int_cst (integer_type_node
,
2657 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2658 t
= build3 (COND_EXPR
, void_type_node
, t
,
2659 build1 (GOTO_EXPR
, void_type_node
, lab_false
),
2661 gimplify_and_add (t
, pre_p
);
2663 gimplify_assign (array
, reg
, pre_p
);
2665 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
2666 gimplify_and_add (t
, pre_p
);
2668 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
2669 gimplify_and_add (t
, pre_p
);
2673 /* ...otherwise, the argument is on the stack (never split between
2674 registers and the stack -- change __va_ndx if necessary):
2678 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2679 (AP).__va_ndx = 32 + __va_size (TYPE);
2680 __array = (AP).__va_stk;
2683 lab_false2
= create_artificial_label ();
2685 t
= build2 (GT_EXPR
, boolean_type_node
, orig_ndx
,
2686 build_int_cst (integer_type_node
,
2687 MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2688 t
= build3 (COND_EXPR
, void_type_node
, t
,
2689 build1 (GOTO_EXPR
, void_type_node
, lab_false2
),
2691 gimplify_and_add (t
, pre_p
);
2693 t
= size_binop (PLUS_EXPR
, va_size
, size_int (32));
2694 t
= fold_convert (integer_type_node
, t
);
2695 gimplify_assign (ndx
, t
, pre_p
);
2697 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false2
);
2698 gimplify_and_add (t
, pre_p
);
2700 gimplify_assign (array
, stk
, pre_p
);
2704 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
2705 gimplify_and_add (t
, pre_p
);
2709 /* Given the base array pointer (__array) and index to the subsequent
2710 argument (__va_ndx), find the address:
2712 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2716 The results are endian-dependent because values smaller than one word
2717 are aligned differently. */
2720 if (BYTES_BIG_ENDIAN
&& TREE_CODE (type_size
) == INTEGER_CST
)
2722 t
= fold_build2 (GE_EXPR
, boolean_type_node
, type_size
,
2723 size_int (PARM_BOUNDARY
/ BITS_PER_UNIT
));
2724 t
= fold_build3 (COND_EXPR
, sizetype
, t
, va_size
, type_size
);
2730 t
= fold_convert (sizetype
, ndx
);
2731 t
= build2 (MINUS_EXPR
, sizetype
, t
, size
);
2732 addr
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, array
, t
);
2734 addr
= fold_convert (build_pointer_type (type
), addr
);
2736 addr
= build_va_arg_indirect_ref (addr
);
2737 return build_va_arg_indirect_ref (addr
);
2745 XTENSA_BUILTIN_UMULSIDI3
,
2751 xtensa_init_builtins (void)
2755 ftype
= build_function_type_list (unsigned_intDI_type_node
,
2756 unsigned_intSI_type_node
,
2757 unsigned_intSI_type_node
, NULL_TREE
);
2759 add_builtin_function ("__builtin_umulsidi3", ftype
,
2760 XTENSA_BUILTIN_UMULSIDI3
, BUILT_IN_MD
,
2761 "__umulsidi3", NULL_TREE
);
2766 xtensa_fold_builtin (tree fndecl
, tree arglist
, bool ignore ATTRIBUTE_UNUSED
)
2768 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
2771 if (fcode
== XTENSA_BUILTIN_UMULSIDI3
)
2773 arg0
= TREE_VALUE (arglist
);
2774 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
2775 if ((TREE_CODE (arg0
) == INTEGER_CST
&& TREE_CODE (arg1
) == INTEGER_CST
)
2776 || TARGET_MUL32_HIGH
)
2777 return fold_build2 (MULT_EXPR
, unsigned_intDI_type_node
,
2778 fold_convert (unsigned_intDI_type_node
, arg0
),
2779 fold_convert (unsigned_intDI_type_node
, arg1
));
2784 internal_error ("bad builtin code");
2790 xtensa_expand_builtin (tree exp
, rtx target
,
2791 rtx subtarget ATTRIBUTE_UNUSED
,
2792 enum machine_mode mode ATTRIBUTE_UNUSED
,
2795 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
2796 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
2798 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
2799 __umulsidi3 function when the Xtensa configuration can directly
2800 implement it. If not, just call the function. */
2801 if (fcode
== XTENSA_BUILTIN_UMULSIDI3
)
2802 return expand_call (exp
, target
, ignore
);
2804 internal_error ("bad builtin code");
2810 xtensa_preferred_reload_class (rtx x
, enum reg_class
class, int isoutput
)
2812 if (!isoutput
&& CONSTANT_P (x
) && GET_CODE (x
) == CONST_DOUBLE
)
2815 /* Don't use the stack pointer or hard frame pointer for reloads!
2816 The hard frame pointer would normally be OK except that it may
2817 briefly hold an incoming argument in the prologue, and reload
2818 won't know that it is live because the hard frame pointer is
2819 treated specially. */
2821 if (class == AR_REGS
|| class == GR_REGS
)
2829 xtensa_secondary_reload_class (enum reg_class
class,
2830 enum machine_mode mode ATTRIBUTE_UNUSED
,
2831 rtx x
, int isoutput
)
2835 if (GET_CODE (x
) == SIGN_EXTEND
)
2837 regno
= xt_true_regnum (x
);
2841 if ((class == FP_REGS
|| GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
2842 && constantpool_mem_p (x
))
2846 if (ACC_REG_P (regno
))
2847 return ((class == GR_REGS
|| class == RL_REGS
) ? NO_REGS
: RL_REGS
);
2848 if (class == ACC_REG
)
2849 return (GP_REG_P (regno
) ? NO_REGS
: RL_REGS
);
2856 order_regs_for_local_alloc (void)
2858 if (!leaf_function_p ())
2860 memcpy (reg_alloc_order
, reg_nonleaf_alloc_order
,
2861 FIRST_PSEUDO_REGISTER
* sizeof (int));
2865 int i
, num_arg_regs
;
2868 /* Use the AR registers in increasing order (skipping a0 and a1)
2869 but save the incoming argument registers for a last resort. */
2870 num_arg_regs
= crtl
->args
.info
.arg_words
;
2871 if (num_arg_regs
> MAX_ARGS_IN_REGISTERS
)
2872 num_arg_regs
= MAX_ARGS_IN_REGISTERS
;
2873 for (i
= GP_ARG_FIRST
; i
< 16 - num_arg_regs
; i
++)
2874 reg_alloc_order
[nxt
++] = i
+ num_arg_regs
;
2875 for (i
= 0; i
< num_arg_regs
; i
++)
2876 reg_alloc_order
[nxt
++] = GP_ARG_FIRST
+ i
;
2878 /* List the coprocessor registers in order. */
2879 for (i
= 0; i
< BR_REG_NUM
; i
++)
2880 reg_alloc_order
[nxt
++] = BR_REG_FIRST
+ i
;
2882 /* List the FP registers in order for now. */
2883 for (i
= 0; i
< 16; i
++)
2884 reg_alloc_order
[nxt
++] = FP_REG_FIRST
+ i
;
2886 /* GCC requires that we list *all* the registers.... */
2887 reg_alloc_order
[nxt
++] = 0; /* a0 = return address */
2888 reg_alloc_order
[nxt
++] = 1; /* a1 = stack pointer */
2889 reg_alloc_order
[nxt
++] = 16; /* pseudo frame pointer */
2890 reg_alloc_order
[nxt
++] = 17; /* pseudo arg pointer */
2892 reg_alloc_order
[nxt
++] = ACC_REG_FIRST
; /* MAC16 accumulator */
2897 /* Some Xtensa targets support multiple bss sections. If the section
2898 name ends with ".bss", add SECTION_BSS to the flags. */
2901 xtensa_multibss_section_type_flags (tree decl
, const char *name
, int reloc
)
2903 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
2906 suffix
= strrchr (name
, '.');
2907 if (suffix
&& strcmp (suffix
, ".bss") == 0)
2909 if (!decl
|| (TREE_CODE (decl
) == VAR_DECL
2910 && DECL_INITIAL (decl
) == NULL_TREE
))
2911 flags
|= SECTION_BSS
; /* @nobits */
2913 warning (0, "only uninitialized variables can be placed in a "
2921 /* The literal pool stays with the function. */
2924 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED
,
2925 rtx x ATTRIBUTE_UNUSED
,
2926 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
2928 return function_section (current_function_decl
);
2932 /* Compute a (partial) cost for rtx X. Return true if the complete
2933 cost has been computed, and false if subexpressions should be
2934 scanned. In either case, *TOTAL contains the cost result. */
2937 xtensa_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2945 if (xtensa_simm12b (INTVAL (x
)))
2952 if (xtensa_simm8 (INTVAL (x
))
2953 || xtensa_simm8x256 (INTVAL (x
)))
2960 if (xtensa_mask_immediate (INTVAL (x
)))
2967 if ((INTVAL (x
) == 0) || xtensa_b4const (INTVAL (x
)))
2978 /* No way to tell if X is the 2nd operand so be conservative. */
2981 if (xtensa_simm12b (INTVAL (x
)))
2983 else if (TARGET_CONST16
)
2984 *total
= COSTS_N_INSNS (2);
2993 *total
= COSTS_N_INSNS (2);
3000 *total
= COSTS_N_INSNS (4);
3008 (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
) ? 2 : 1;
3010 if (memory_address_p (GET_MODE (x
), XEXP ((x
), 0)))
3011 *total
= COSTS_N_INSNS (num_words
);
3013 *total
= COSTS_N_INSNS (2*num_words
);
3019 *total
= COSTS_N_INSNS (TARGET_NSA
? 5 : 50);
3023 *total
= COSTS_N_INSNS (TARGET_NSA
? 1 : 50);
3027 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 3 : 2);
3033 if (GET_MODE (x
) == DImode
)
3034 *total
= COSTS_N_INSNS (2);
3036 *total
= COSTS_N_INSNS (1);
3042 if (GET_MODE (x
) == DImode
)
3043 *total
= COSTS_N_INSNS (50);
3045 *total
= COSTS_N_INSNS (1);
3050 enum machine_mode xmode
= GET_MODE (x
);
3051 if (xmode
== SFmode
)
3052 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3053 else if (xmode
== DFmode
)
3054 *total
= COSTS_N_INSNS (50);
3056 *total
= COSTS_N_INSNS (4);
3063 enum machine_mode xmode
= GET_MODE (x
);
3064 if (xmode
== SFmode
)
3065 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3066 else if (xmode
== DFmode
|| xmode
== DImode
)
3067 *total
= COSTS_N_INSNS (50);
3069 *total
= COSTS_N_INSNS (1);
3074 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 4 : 2);
3079 enum machine_mode xmode
= GET_MODE (x
);
3080 if (xmode
== SFmode
)
3081 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 4 : 50);
3082 else if (xmode
== DFmode
)
3083 *total
= COSTS_N_INSNS (50);
3084 else if (xmode
== DImode
)
3085 *total
= COSTS_N_INSNS (TARGET_MUL32_HIGH
? 10 : 50);
3086 else if (TARGET_MUL32
)
3087 *total
= COSTS_N_INSNS (4);
3088 else if (TARGET_MAC16
)
3089 *total
= COSTS_N_INSNS (16);
3090 else if (TARGET_MUL16
)
3091 *total
= COSTS_N_INSNS (12);
3093 *total
= COSTS_N_INSNS (50);
3100 enum machine_mode xmode
= GET_MODE (x
);
3101 if (xmode
== SFmode
)
3103 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV
? 8 : 50);
3106 else if (xmode
== DFmode
)
3108 *total
= COSTS_N_INSNS (50);
3117 enum machine_mode xmode
= GET_MODE (x
);
3118 if (xmode
== DImode
)
3119 *total
= COSTS_N_INSNS (50);
3120 else if (TARGET_DIV32
)
3121 *total
= COSTS_N_INSNS (32);
3123 *total
= COSTS_N_INSNS (50);
3128 if (GET_MODE (x
) == SFmode
)
3129 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT
? 8 : 50);
3131 *total
= COSTS_N_INSNS (50);
3138 *total
= COSTS_N_INSNS (TARGET_MINMAX
? 1 : 50);
3143 *total
= COSTS_N_INSNS (TARGET_SEXT
? 1 : 2);
3148 *total
= COSTS_N_INSNS (1);
3156 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3159 xtensa_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3161 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)
3162 > 4 * UNITS_PER_WORD
);
3165 /* Worker function for TARGET_FUNCTION_VALUE. */
3168 xtensa_function_value (const_tree valtype
, const_tree func ATTRIBUTE_UNUSED
,
3171 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype
)
3172 && TYPE_PRECISION (valtype
) < BITS_PER_WORD
)
3173 ? SImode
: TYPE_MODE (valtype
),
3174 outgoing
? GP_OUTGOING_RETURN
: GP_RETURN
);
3177 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY
3178 instruction with a minimal stack frame in order to get some free
3179 registers. Once the actual call target is known, the proper stack frame
3180 size is extracted from the ENTRY instruction at the target and the
3181 current frame is adjusted to match. The trampoline then transfers
3182 control to the instruction following the ENTRY at the target. Note:
3183 this assumes that the target begins with an ENTRY instruction. */
3186 xtensa_trampoline_template (FILE *stream
)
3188 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3190 fprintf (stream
, "\t.begin no-transform\n");
3191 fprintf (stream
, "\tentry\tsp, %d\n", MIN_FRAME_SIZE
);
3195 /* Save the return address. */
3196 fprintf (stream
, "\tmov\ta10, a0\n");
3198 /* Use a CALL0 instruction to skip past the constants and in the
3199 process get the PC into A0. This allows PC-relative access to
3200 the constants without relying on L32R. */
3201 fprintf (stream
, "\tcall0\t.Lskipconsts\n");
3204 fprintf (stream
, "\tj\t.Lskipconsts\n");
3206 fprintf (stream
, "\t.align\t4\n");
3207 fprintf (stream
, ".Lchainval:%s0\n", integer_asm_op (4, TRUE
));
3208 fprintf (stream
, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE
));
3209 fprintf (stream
, ".Lskipconsts:\n");
3211 /* Load the static chain and function address from the trampoline. */
3214 fprintf (stream
, "\taddi\ta0, a0, 3\n");
3215 fprintf (stream
, "\tl32i\ta9, a0, 0\n");
3216 fprintf (stream
, "\tl32i\ta8, a0, 4\n");
3220 fprintf (stream
, "\tl32r\ta9, .Lchainval\n");
3221 fprintf (stream
, "\tl32r\ta8, .Lfnaddr\n");
3224 /* Store the static chain. */
3225 fprintf (stream
, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE
- 20);
3227 /* Set the proper stack pointer value. */
3228 fprintf (stream
, "\tl32i\ta9, a8, 0\n");
3229 fprintf (stream
, "\textui\ta9, a9, %d, 12\n",
3230 TARGET_BIG_ENDIAN
? 8 : 12);
3231 fprintf (stream
, "\tslli\ta9, a9, 3\n");
3232 fprintf (stream
, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE
);
3233 fprintf (stream
, "\tsub\ta9, sp, a9\n");
3234 fprintf (stream
, "\tmovsp\tsp, a9\n");
3237 /* Restore the return address. */
3238 fprintf (stream
, "\tmov\ta0, a10\n");
3240 /* Jump to the instruction following the ENTRY. */
3241 fprintf (stream
, "\taddi\ta8, a8, 3\n");
3242 fprintf (stream
, "\tjx\ta8\n");
3244 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */
3246 fprintf (stream
, "\t.byte\t0\n");
3248 fprintf (stream
, "\tnop\n");
3250 fprintf (stream
, "\t.end no-transform\n");
3255 xtensa_initialize_trampoline (rtx addr
, rtx func
, rtx chain
)
3257 bool use_call0
= (TARGET_CONST16
|| TARGET_ABSOLUTE_LITERALS
);
3258 int chain_off
= use_call0
? 12 : 8;
3259 int func_off
= use_call0
? 16 : 12;
3260 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (addr
, chain_off
)), chain
);
3261 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (addr
, func_off
)), func
);
3262 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_sync_caches"),
3263 0, VOIDmode
, 1, addr
, Pmode
);
3267 #include "gt-xtensa.h"