1 /* Subroutines for insn-output.c for Tensilica's Xtensa architecture.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
29 #include "basic-block.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
34 #include "insn-attr.h"
35 #include "insn-codes.h"
49 #include "target-def.h"
50 #include "langhooks.h"
51 #include "tree-gimple.h"
55 /* Enumeration for all of the relational tests, so that we can build
56 arrays indexed by the test type, and not worry about the order
74 /* Cached operands, and operator to compare for use in set/branch on
78 /* what type of branch to use */
79 enum cmp_type branch_type
;
81 /* Array giving truth value on whether or not a given hard register
82 can support a given mode. */
83 char xtensa_hard_regno_mode_ok
[(int) MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
85 /* Current frame size calculated by compute_frame_size. */
86 unsigned xtensa_current_frame_size
;
88 /* Largest block move to handle in-line. */
89 #define LARGEST_MOVE_RATIO 15
91 /* Define the structure for the machine field in struct function. */
92 struct machine_function
GTY(())
94 int accesses_prev_frame
;
97 rtx set_frame_ptr_insn
;
100 /* Vector, indexed by hard register number, which contains 1 for a
101 register that is allowable in a candidate for leaf function
104 const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
] =
106 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
108 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
112 /* Map hard register number to register class */
113 const enum reg_class xtensa_regno_to_class
[FIRST_PSEUDO_REGISTER
] =
115 RL_REGS
, SP_REG
, RL_REGS
, RL_REGS
,
116 RL_REGS
, RL_REGS
, RL_REGS
, GR_REGS
,
117 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
118 RL_REGS
, RL_REGS
, RL_REGS
, RL_REGS
,
119 AR_REGS
, AR_REGS
, BR_REGS
,
120 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
121 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
122 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
123 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
127 static enum internal_test
map_test_to_internal_test (enum rtx_code
);
128 static rtx
gen_int_relational (enum rtx_code
, rtx
, rtx
, int *);
129 static rtx
gen_float_relational (enum rtx_code
, rtx
, rtx
);
130 static rtx
gen_conditional_move (rtx
);
131 static rtx
fixup_subreg_mem (rtx
);
132 static struct machine_function
* xtensa_init_machine_status (void);
133 static bool xtensa_return_in_msb (tree
);
134 static void printx (FILE *, signed int);
135 static void xtensa_function_epilogue (FILE *, HOST_WIDE_INT
);
136 static rtx
xtensa_builtin_saveregs (void);
137 static unsigned int xtensa_multibss_section_type_flags (tree
, const char *,
138 int) ATTRIBUTE_UNUSED
;
139 static section
*xtensa_select_rtx_section (enum machine_mode
, rtx
,
140 unsigned HOST_WIDE_INT
);
141 static bool xtensa_rtx_costs (rtx
, int, int, int *);
142 static tree
xtensa_build_builtin_va_list (void);
143 static bool xtensa_return_in_memory (tree
, tree
);
144 static tree
xtensa_gimplify_va_arg_expr (tree
, tree
, tree
*, tree
*);
145 static void xtensa_init_builtins (void);
146 static tree
xtensa_fold_builtin (tree
, tree
, bool);
147 static rtx
xtensa_expand_builtin (tree
, rtx
, rtx
, enum machine_mode
, int);
149 static const int reg_nonleaf_alloc_order
[FIRST_PSEUDO_REGISTER
] =
153 /* This macro generates the assembly code for function exit,
154 on machines that need it. If FUNCTION_EPILOGUE is not defined
155 then individual return instructions are generated for each
156 return statement. Args are same as for FUNCTION_PROLOGUE. */
158 #undef TARGET_ASM_FUNCTION_EPILOGUE
159 #define TARGET_ASM_FUNCTION_EPILOGUE xtensa_function_epilogue
161 /* These hooks specify assembly directives for creating certain kinds
162 of integer object. */
164 #undef TARGET_ASM_ALIGNED_SI_OP
165 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
167 #undef TARGET_ASM_SELECT_RTX_SECTION
168 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section
170 #undef TARGET_DEFAULT_TARGET_FLAGS
171 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD)
173 #undef TARGET_RTX_COSTS
174 #define TARGET_RTX_COSTS xtensa_rtx_costs
175 #undef TARGET_ADDRESS_COST
176 #define TARGET_ADDRESS_COST hook_int_rtx_0
178 #undef TARGET_BUILD_BUILTIN_VA_LIST
179 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list
181 #undef TARGET_PROMOTE_FUNCTION_ARGS
182 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
183 #undef TARGET_PROMOTE_FUNCTION_RETURN
184 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
185 #undef TARGET_PROMOTE_PROTOTYPES
186 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
188 #undef TARGET_RETURN_IN_MEMORY
189 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory
190 #undef TARGET_SPLIT_COMPLEX_ARG
191 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
192 #undef TARGET_MUST_PASS_IN_STACK
193 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
195 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
196 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs
197 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
198 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr
200 #undef TARGET_RETURN_IN_MSB
201 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb
203 #undef TARGET_INIT_BUILTINS
204 #define TARGET_INIT_BUILTINS xtensa_init_builtins
205 #undef TARGET_FOLD_BUILTIN
206 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin
207 #undef TARGET_EXPAND_BUILTIN
208 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin
210 struct gcc_target targetm
= TARGET_INITIALIZER
;
213 /* Functions to test Xtensa immediate operand validity. */
216 xtensa_simm8 (HOST_WIDE_INT v
)
218 return v
>= -128 && v
<= 127;
223 xtensa_simm8x256 (HOST_WIDE_INT v
)
225 return (v
& 255) == 0 && (v
>= -32768 && v
<= 32512);
230 xtensa_simm12b (HOST_WIDE_INT v
)
232 return v
>= -2048 && v
<= 2047;
237 xtensa_uimm8 (HOST_WIDE_INT v
)
239 return v
>= 0 && v
<= 255;
244 xtensa_uimm8x2 (HOST_WIDE_INT v
)
246 return (v
& 1) == 0 && (v
>= 0 && v
<= 510);
251 xtensa_uimm8x4 (HOST_WIDE_INT v
)
253 return (v
& 3) == 0 && (v
>= 0 && v
<= 1020);
258 xtensa_b4const (HOST_WIDE_INT v
)
285 xtensa_b4const_or_zero (HOST_WIDE_INT v
)
289 return xtensa_b4const (v
);
294 xtensa_b4constu (HOST_WIDE_INT v
)
321 xtensa_mask_immediate (HOST_WIDE_INT v
)
323 #define MAX_MASK_SIZE 16
326 for (mask_size
= 1; mask_size
<= MAX_MASK_SIZE
; mask_size
++)
339 /* This is just like the standard true_regnum() function except that it
340 works even when reg_renumber is not initialized. */
343 xt_true_regnum (rtx x
)
345 if (GET_CODE (x
) == REG
)
348 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
349 && reg_renumber
[REGNO (x
)] >= 0)
350 return reg_renumber
[REGNO (x
)];
353 if (GET_CODE (x
) == SUBREG
)
355 int base
= xt_true_regnum (SUBREG_REG (x
));
356 if (base
>= 0 && base
< FIRST_PSEUDO_REGISTER
)
357 return base
+ subreg_regno_offset (REGNO (SUBREG_REG (x
)),
358 GET_MODE (SUBREG_REG (x
)),
359 SUBREG_BYTE (x
), GET_MODE (x
));
366 xtensa_valid_move (enum machine_mode mode
, rtx
*operands
)
368 /* Either the destination or source must be a register, and the
369 MAC16 accumulator doesn't count. */
371 if (register_operand (operands
[0], mode
))
373 int dst_regnum
= xt_true_regnum (operands
[0]);
375 /* The stack pointer can only be assigned with a MOVSP opcode. */
376 if (dst_regnum
== STACK_POINTER_REGNUM
)
377 return (mode
== SImode
378 && register_operand (operands
[1], mode
)
379 && !ACC_REG_P (xt_true_regnum (operands
[1])));
381 if (!ACC_REG_P (dst_regnum
))
384 if (register_operand (operands
[1], mode
))
386 int src_regnum
= xt_true_regnum (operands
[1]);
387 if (!ACC_REG_P (src_regnum
))
395 smalloffset_mem_p (rtx op
)
397 if (GET_CODE (op
) == MEM
)
399 rtx addr
= XEXP (op
, 0);
400 if (GET_CODE (addr
) == REG
)
401 return BASE_REG_P (addr
, 0);
402 if (GET_CODE (addr
) == PLUS
)
404 rtx offset
= XEXP (addr
, 0);
406 if (GET_CODE (offset
) != CONST_INT
)
407 offset
= XEXP (addr
, 1);
408 if (GET_CODE (offset
) != CONST_INT
)
411 val
= INTVAL (offset
);
412 return (val
& 3) == 0 && (val
>= 0 && val
<= 60);
420 constantpool_address_p (rtx addr
)
424 if (GET_CODE (addr
) == CONST
)
428 /* Only handle (PLUS (SYM, OFFSET)) form. */
429 addr
= XEXP (addr
, 0);
430 if (GET_CODE (addr
) != PLUS
)
433 /* Make sure the address is word aligned. */
434 offset
= XEXP (addr
, 1);
435 if ((GET_CODE (offset
) != CONST_INT
)
436 || ((INTVAL (offset
) & 3) != 0))
439 sym
= XEXP (addr
, 0);
442 if ((GET_CODE (sym
) == SYMBOL_REF
)
443 && CONSTANT_POOL_ADDRESS_P (sym
))
450 constantpool_mem_p (rtx op
)
452 if (GET_CODE (op
) == SUBREG
)
453 op
= SUBREG_REG (op
);
454 if (GET_CODE (op
) == MEM
)
455 return constantpool_address_p (XEXP (op
, 0));
461 xtensa_extend_reg (rtx dst
, rtx src
)
463 rtx temp
= gen_reg_rtx (SImode
);
464 rtx shift
= GEN_INT (BITS_PER_WORD
- GET_MODE_BITSIZE (GET_MODE (src
)));
466 /* Generate paradoxical subregs as needed so that the modes match. */
467 src
= simplify_gen_subreg (SImode
, src
, GET_MODE (src
), 0);
468 dst
= simplify_gen_subreg (SImode
, dst
, GET_MODE (dst
), 0);
470 emit_insn (gen_ashlsi3 (temp
, src
, shift
));
471 emit_insn (gen_ashrsi3 (dst
, temp
, shift
));
476 xtensa_mem_offset (unsigned v
, enum machine_mode mode
)
481 /* Handle the worst case for block moves. See xtensa_expand_block_move
482 where we emit an optimized block move operation if the block can be
483 moved in < "move_ratio" pieces. The worst case is when the block is
484 aligned but has a size of (3 mod 4) (does this happen?) so that the
485 last piece requires a byte load/store. */
486 return (xtensa_uimm8 (v
)
487 && xtensa_uimm8 (v
+ MOVE_MAX
* LARGEST_MOVE_RATIO
));
490 return xtensa_uimm8 (v
);
493 return xtensa_uimm8x2 (v
);
496 return (xtensa_uimm8x4 (v
) && xtensa_uimm8x4 (v
+ 4));
502 return xtensa_uimm8x4 (v
);
506 /* Make normal rtx_code into something we can index from an array. */
508 static enum internal_test
509 map_test_to_internal_test (enum rtx_code test_code
)
511 enum internal_test test
= ITEST_MAX
;
516 case EQ
: test
= ITEST_EQ
; break;
517 case NE
: test
= ITEST_NE
; break;
518 case GT
: test
= ITEST_GT
; break;
519 case GE
: test
= ITEST_GE
; break;
520 case LT
: test
= ITEST_LT
; break;
521 case LE
: test
= ITEST_LE
; break;
522 case GTU
: test
= ITEST_GTU
; break;
523 case GEU
: test
= ITEST_GEU
; break;
524 case LTU
: test
= ITEST_LTU
; break;
525 case LEU
: test
= ITEST_LEU
; break;
532 /* Generate the code to compare two integer values. The return value is
533 the comparison expression. */
536 gen_int_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
537 rtx cmp0
, /* first operand to compare */
538 rtx cmp1
, /* second operand to compare */
539 int *p_invert
/* whether branch needs to reverse test */)
543 enum rtx_code test_code
; /* test code to use in insn */
544 bool (*const_range_p
) (HOST_WIDE_INT
); /* range check function */
545 int const_add
; /* constant to add (convert LE -> LT) */
546 int reverse_regs
; /* reverse registers in test */
547 int invert_const
; /* != 0 if invert value if cmp1 is constant */
548 int invert_reg
; /* != 0 if invert value if cmp1 is register */
549 int unsignedp
; /* != 0 for unsigned comparisons. */
552 static struct cmp_info info
[ (int)ITEST_MAX
] = {
554 { EQ
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* EQ */
555 { NE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* NE */
557 { LT
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* GT */
558 { GE
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* GE */
559 { LT
, xtensa_b4const_or_zero
, 0, 0, 0, 0, 0 }, /* LT */
560 { GE
, xtensa_b4const_or_zero
, 1, 1, 1, 0, 0 }, /* LE */
562 { LTU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* GTU */
563 { GEU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* GEU */
564 { LTU
, xtensa_b4constu
, 0, 0, 0, 0, 1 }, /* LTU */
565 { GEU
, xtensa_b4constu
, 1, 1, 1, 0, 1 }, /* LEU */
568 enum internal_test test
;
569 enum machine_mode mode
;
570 struct cmp_info
*p_info
;
572 test
= map_test_to_internal_test (test_code
);
573 gcc_assert (test
!= ITEST_MAX
);
575 p_info
= &info
[ (int)test
];
577 mode
= GET_MODE (cmp0
);
578 if (mode
== VOIDmode
)
579 mode
= GET_MODE (cmp1
);
581 /* Make sure we can handle any constants given to us. */
582 if (GET_CODE (cmp1
) == CONST_INT
)
584 HOST_WIDE_INT value
= INTVAL (cmp1
);
585 unsigned HOST_WIDE_INT uvalue
= (unsigned HOST_WIDE_INT
)value
;
587 /* if the immediate overflows or does not fit in the immediate field,
588 spill it to a register */
590 if ((p_info
->unsignedp
?
591 (uvalue
+ p_info
->const_add
> uvalue
) :
592 (value
+ p_info
->const_add
> value
)) != (p_info
->const_add
> 0))
594 cmp1
= force_reg (mode
, cmp1
);
596 else if (!(p_info
->const_range_p
) (value
+ p_info
->const_add
))
598 cmp1
= force_reg (mode
, cmp1
);
601 else if ((GET_CODE (cmp1
) != REG
) && (GET_CODE (cmp1
) != SUBREG
))
603 cmp1
= force_reg (mode
, cmp1
);
606 /* See if we need to invert the result. */
607 *p_invert
= ((GET_CODE (cmp1
) == CONST_INT
)
608 ? p_info
->invert_const
609 : p_info
->invert_reg
);
611 /* Comparison to constants, may involve adding 1 to change a LT into LE.
612 Comparison between two registers, may involve switching operands. */
613 if (GET_CODE (cmp1
) == CONST_INT
)
615 if (p_info
->const_add
!= 0)
616 cmp1
= GEN_INT (INTVAL (cmp1
) + p_info
->const_add
);
619 else if (p_info
->reverse_regs
)
626 return gen_rtx_fmt_ee (p_info
->test_code
, VOIDmode
, cmp0
, cmp1
);
630 /* Generate the code to compare two float values. The return value is
631 the comparison expression. */
634 gen_float_relational (enum rtx_code test_code
, /* relational test (EQ, etc) */
635 rtx cmp0
, /* first operand to compare */
636 rtx cmp1
/* second operand to compare */)
638 rtx (*gen_fn
) (rtx
, rtx
, rtx
);
640 int reverse_regs
, invert
;
644 case EQ
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_seq_sf
; break;
645 case NE
: reverse_regs
= 0; invert
= 1; gen_fn
= gen_seq_sf
; break;
646 case LE
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_sle_sf
; break;
647 case GT
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_slt_sf
; break;
648 case LT
: reverse_regs
= 0; invert
= 0; gen_fn
= gen_slt_sf
; break;
649 case GE
: reverse_regs
= 1; invert
= 0; gen_fn
= gen_sle_sf
; break;
651 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
652 reverse_regs
= 0; invert
= 0; gen_fn
= 0; /* avoid compiler warnings */
662 brtmp
= gen_rtx_REG (CCmode
, FPCC_REGNUM
);
663 emit_insn (gen_fn (brtmp
, cmp0
, cmp1
));
665 return gen_rtx_fmt_ee (invert
? EQ
: NE
, VOIDmode
, brtmp
, const0_rtx
);
670 xtensa_expand_conditional_branch (rtx
*operands
, enum rtx_code test_code
)
672 enum cmp_type type
= branch_type
;
673 rtx cmp0
= branch_cmp
[0];
674 rtx cmp1
= branch_cmp
[1];
683 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
, cmp0
, cmp1
));
687 cmp
= gen_int_relational (test_code
, cmp0
, cmp1
, &invert
);
691 if (!TARGET_HARD_FLOAT
)
692 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code
, VOIDmode
,
695 cmp
= gen_float_relational (test_code
, cmp0
, cmp1
);
699 /* Generate the branch. */
701 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
710 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
711 gen_rtx_IF_THEN_ELSE (VOIDmode
, cmp
,
718 gen_conditional_move (rtx cmp
)
720 enum rtx_code code
= GET_CODE (cmp
);
721 rtx op0
= branch_cmp
[0];
722 rtx op1
= branch_cmp
[1];
724 if (branch_type
== CMP_SI
)
726 /* Jump optimization calls get_condition() which canonicalizes
727 comparisons like (GE x <const>) to (GT x <const-1>).
728 Transform those comparisons back to GE, since that is the
729 comparison supported in Xtensa. We shouldn't have to
730 transform <LE x const> comparisons, because neither
731 xtensa_expand_conditional_branch() nor get_condition() will
734 if ((code
== GT
) && (op1
== constm1_rtx
))
739 cmp
= gen_rtx_fmt_ee (code
, VOIDmode
, cc0_rtx
, const0_rtx
);
741 if (boolean_operator (cmp
, VOIDmode
))
743 /* Swap the operands to make const0 second. */
744 if (op0
== const0_rtx
)
750 /* If not comparing against zero, emit a comparison (subtract). */
751 if (op1
!= const0_rtx
)
753 op0
= expand_binop (SImode
, sub_optab
, op0
, op1
,
754 0, 0, OPTAB_LIB_WIDEN
);
758 else if (branch_operator (cmp
, VOIDmode
))
760 /* Swap the operands to make const0 second. */
761 if (op0
== const0_rtx
)
768 case LT
: code
= GE
; break;
769 case GE
: code
= LT
; break;
770 default: gcc_unreachable ();
774 if (op1
!= const0_rtx
)
780 return gen_rtx_fmt_ee (code
, VOIDmode
, op0
, op1
);
783 if (TARGET_HARD_FLOAT
&& (branch_type
== CMP_SF
))
784 return gen_float_relational (code
, op0
, op1
);
791 xtensa_expand_conditional_move (rtx
*operands
, int isflt
)
794 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
796 if (!(cmp
= gen_conditional_move (operands
[1])))
800 gen_fn
= (branch_type
== CMP_SI
801 ? gen_movsfcc_internal0
802 : gen_movsfcc_internal1
);
804 gen_fn
= (branch_type
== CMP_SI
805 ? gen_movsicc_internal0
806 : gen_movsicc_internal1
);
808 emit_insn (gen_fn (operands
[0], XEXP (cmp
, 0),
809 operands
[2], operands
[3], cmp
));
815 xtensa_expand_scc (rtx
*operands
)
817 rtx dest
= operands
[0];
818 rtx cmp
= operands
[1];
819 rtx one_tmp
, zero_tmp
;
820 rtx (*gen_fn
) (rtx
, rtx
, rtx
, rtx
, rtx
);
822 if (!(cmp
= gen_conditional_move (cmp
)))
825 one_tmp
= gen_reg_rtx (SImode
);
826 zero_tmp
= gen_reg_rtx (SImode
);
827 emit_insn (gen_movsi (one_tmp
, const_true_rtx
));
828 emit_insn (gen_movsi (zero_tmp
, const0_rtx
));
830 gen_fn
= (branch_type
== CMP_SI
831 ? gen_movsicc_internal0
832 : gen_movsicc_internal1
);
833 emit_insn (gen_fn (dest
, XEXP (cmp
, 0), one_tmp
, zero_tmp
, cmp
));
838 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is
839 for the output, i.e., the input operands are twice as big as MODE. */
842 xtensa_split_operand_pair (rtx operands
[4], enum machine_mode mode
)
844 switch (GET_CODE (operands
[1]))
847 operands
[3] = gen_rtx_REG (mode
, REGNO (operands
[1]) + 1);
848 operands
[2] = gen_rtx_REG (mode
, REGNO (operands
[1]));
852 operands
[3] = adjust_address (operands
[1], mode
, GET_MODE_SIZE (mode
));
853 operands
[2] = adjust_address (operands
[1], mode
, 0);
858 split_double (operands
[1], &operands
[2], &operands
[3]);
865 switch (GET_CODE (operands
[0]))
868 operands
[1] = gen_rtx_REG (mode
, REGNO (operands
[0]) + 1);
869 operands
[0] = gen_rtx_REG (mode
, REGNO (operands
[0]));
873 operands
[1] = adjust_address (operands
[0], mode
, GET_MODE_SIZE (mode
));
874 operands
[0] = adjust_address (operands
[0], mode
, 0);
883 /* Emit insns to move operands[1] into operands[0].
884 Return 1 if we have written out everything that needs to be done to
885 do the move. Otherwise, return 0 and the caller will emit the move
889 xtensa_emit_move_sequence (rtx
*operands
, enum machine_mode mode
)
891 if (CONSTANT_P (operands
[1])
892 && (GET_CODE (operands
[1]) != CONST_INT
893 || !xtensa_simm12b (INTVAL (operands
[1]))))
896 operands
[1] = force_const_mem (SImode
, operands
[1]);
898 /* PC-relative loads are always SImode, and CONST16 is only
899 supported in the movsi pattern, so add a SUBREG for any other
904 if (register_operand (operands
[0], mode
))
906 operands
[0] = simplify_gen_subreg (SImode
, operands
[0], mode
, 0);
907 emit_move_insn (operands
[0], operands
[1]);
912 operands
[1] = force_reg (SImode
, operands
[1]);
913 operands
[1] = gen_lowpart_SUBREG (mode
, operands
[1]);
918 if (!(reload_in_progress
| reload_completed
)
919 && !xtensa_valid_move (mode
, operands
))
920 operands
[1] = force_reg (mode
, operands
[1]);
922 operands
[1] = xtensa_copy_incoming_a7 (operands
[1]);
924 /* During reload we don't want to emit (subreg:X (mem:Y)) since that
925 instruction won't be recognized after reload, so we remove the
926 subreg and adjust mem accordingly. */
927 if (reload_in_progress
)
929 operands
[0] = fixup_subreg_mem (operands
[0]);
930 operands
[1] = fixup_subreg_mem (operands
[1]);
937 fixup_subreg_mem (rtx x
)
939 if (GET_CODE (x
) == SUBREG
940 && GET_CODE (SUBREG_REG (x
)) == REG
941 && REGNO (SUBREG_REG (x
)) >= FIRST_PSEUDO_REGISTER
)
944 gen_rtx_SUBREG (GET_MODE (x
),
945 reg_equiv_mem
[REGNO (SUBREG_REG (x
))],
947 x
= alter_subreg (&temp
);
953 /* Check if an incoming argument in a7 is expected to be used soon and
954 if OPND is a register or register pair that includes a7. If so,
955 create a new pseudo and copy a7 into that pseudo at the very
956 beginning of the function, followed by the special "set_frame_ptr"
957 unspec_volatile insn. The return value is either the original
958 operand, if it is not a7, or the new pseudo containing a copy of
959 the incoming argument. This is necessary because the register
960 allocator will ignore conflicts with a7 and may either assign some
961 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering
962 the incoming argument in a7. By copying the argument out of a7 as
963 the very first thing, and then immediately following that with an
964 unspec_volatile to keep the scheduler away, we should avoid any
965 problems. Putting the set_frame_ptr insn at the beginning, with
966 only the a7 copy before it, also makes it easier for the prologue
967 expander to initialize the frame pointer after the a7 copy and to
968 fix up the a7 copy to use the stack pointer instead of the frame
972 xtensa_copy_incoming_a7 (rtx opnd
)
976 enum machine_mode mode
;
978 if (!cfun
->machine
->need_a7_copy
)
981 /* This function should never be called again once a7 has been copied. */
982 gcc_assert (!cfun
->machine
->set_frame_ptr_insn
);
984 mode
= GET_MODE (opnd
);
986 /* The operand using a7 may come in a later instruction, so just return
987 the original operand if it doesn't use a7. */
989 if (GET_CODE (reg
) == SUBREG
)
991 gcc_assert (SUBREG_BYTE (reg
) == 0);
992 reg
= SUBREG_REG (reg
);
994 if (GET_CODE (reg
) != REG
995 || REGNO (reg
) > A7_REG
996 || REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) <= A7_REG
)
999 /* 1-word args will always be in a7; 2-word args in a6/a7. */
1000 gcc_assert (REGNO (reg
) + HARD_REGNO_NREGS (A7_REG
, mode
) - 1 == A7_REG
);
1002 cfun
->machine
->need_a7_copy
= false;
1004 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to
1005 create the REG for a7 so that hard_frame_pointer_rtx is not used. */
1007 push_to_sequence (entry_insns
);
1008 tmp
= gen_reg_rtx (mode
);
1014 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 0),
1015 gen_rtx_REG (SImode
, A7_REG
- 1)));
1016 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode
, tmp
, 4),
1017 gen_raw_REG (SImode
, A7_REG
)));
1020 emit_insn (gen_movsf_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1023 emit_insn (gen_movsi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1026 emit_insn (gen_movhi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1029 emit_insn (gen_movqi_internal (tmp
, gen_raw_REG (mode
, A7_REG
)));
1035 cfun
->machine
->set_frame_ptr_insn
= emit_insn (gen_set_frame_ptr ());
1036 entry_insns
= get_insns ();
1039 if (cfun
->machine
->vararg_a7
)
1041 /* This is called from within builtin_savereg, so we're already
1042 inside a start_sequence that will be placed at the start of
1044 emit_insn (entry_insns
);
1048 /* Put entry_insns after the NOTE that starts the function. If
1049 this is inside a start_sequence, make the outer-level insn
1050 chain current, so the code is placed at the start of the
1052 push_topmost_sequence ();
1053 emit_insn_after (entry_insns
, get_insns ());
1054 pop_topmost_sequence ();
1061 /* Try to expand a block move operation to a sequence of RTL move
1062 instructions. If not optimizing, or if the block size is not a
1063 constant, or if the block is too large, the expansion fails and GCC
1064 falls back to calling memcpy().
1066 operands[0] is the destination
1067 operands[1] is the source
1068 operands[2] is the length
1069 operands[3] is the alignment */
1072 xtensa_expand_block_move (rtx
*operands
)
1074 static const enum machine_mode mode_from_align
[] =
1076 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1079 rtx dst_mem
= operands
[0];
1080 rtx src_mem
= operands
[1];
1081 HOST_WIDE_INT bytes
, align
;
1082 int num_pieces
, move_ratio
;
1084 enum machine_mode mode
[2];
1093 /* If this is not a fixed size move, just call memcpy. */
1094 if (!optimize
|| (GET_CODE (operands
[2]) != CONST_INT
))
1097 bytes
= INTVAL (operands
[2]);
1098 align
= INTVAL (operands
[3]);
1100 /* Anything to move? */
1104 if (align
> MOVE_MAX
)
1107 /* Decide whether to expand inline based on the optimization level. */
1110 move_ratio
= LARGEST_MOVE_RATIO
;
1111 num_pieces
= (bytes
/ align
) + (bytes
% align
); /* Close enough anyway. */
1112 if (num_pieces
> move_ratio
)
1115 x
= XEXP (dst_mem
, 0);
1118 x
= force_reg (Pmode
, x
);
1119 dst_mem
= replace_equiv_address (dst_mem
, x
);
1122 x
= XEXP (src_mem
, 0);
1125 x
= force_reg (Pmode
, x
);
1126 src_mem
= replace_equiv_address (src_mem
, x
);
1129 active
[0] = active
[1] = false;
1140 next_amount
= (bytes
>= 4 ? 4 : (bytes
>= 2 ? 2 : 1));
1141 next_amount
= MIN (next_amount
, align
);
1143 amount
[next
] = next_amount
;
1144 mode
[next
] = mode_from_align
[next_amount
];
1145 temp
[next
] = gen_reg_rtx (mode
[next
]);
1147 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1148 emit_insn (gen_rtx_SET (VOIDmode
, temp
[next
], x
));
1150 offset_ld
+= next_amount
;
1151 bytes
-= next_amount
;
1152 active
[next
] = true;
1157 active
[phase
] = false;
1159 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1160 emit_insn (gen_rtx_SET (VOIDmode
, x
, temp
[phase
]));
1162 offset_st
+= amount
[phase
];
1165 while (active
[next
]);
1172 xtensa_expand_nonlocal_goto (rtx
*operands
)
1174 rtx goto_handler
= operands
[1];
1175 rtx containing_fp
= operands
[3];
1177 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
1178 is too big to generate in-line. */
1180 if (GET_CODE (containing_fp
) != REG
)
1181 containing_fp
= force_reg (Pmode
, containing_fp
);
1183 goto_handler
= copy_rtx (goto_handler
);
1184 validate_replace_rtx (virtual_stack_vars_rtx
, containing_fp
, goto_handler
);
1186 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_nonlocal_goto"),
1188 containing_fp
, Pmode
,
1189 goto_handler
, Pmode
);
1193 static struct machine_function
*
1194 xtensa_init_machine_status (void)
1196 return ggc_alloc_cleared (sizeof (struct machine_function
));
1200 /* Shift VAL of mode MODE left by COUNT bits. */
1203 xtensa_expand_mask_and_shift (rtx val
, enum machine_mode mode
, rtx count
)
1205 val
= expand_simple_binop (SImode
, AND
, val
, GEN_INT (GET_MODE_MASK (mode
)),
1206 NULL_RTX
, 1, OPTAB_DIRECT
);
1207 return expand_simple_binop (SImode
, ASHIFT
, val
, count
,
1208 NULL_RTX
, 1, OPTAB_DIRECT
);
1212 /* Structure to hold the initial parameters for a compare_and_swap operation
1213 in HImode and QImode. */
1215 struct alignment_context
1217 rtx memsi
; /* SI aligned memory location. */
1218 rtx shift
; /* Bit offset with regard to lsb. */
1219 rtx modemask
; /* Mask of the HQImode shifted by SHIFT bits. */
1220 rtx modemaski
; /* ~modemask */
1224 /* Initialize structure AC for word access to HI and QI mode memory. */
1227 init_alignment_context (struct alignment_context
*ac
, rtx mem
)
1229 enum machine_mode mode
= GET_MODE (mem
);
1230 rtx byteoffset
= NULL_RTX
;
1231 bool aligned
= (MEM_ALIGN (mem
) >= GET_MODE_BITSIZE (SImode
));
1234 ac
->memsi
= adjust_address (mem
, SImode
, 0); /* Memory is aligned. */
1237 /* Alignment is unknown. */
1240 /* Force the address into a register. */
1241 addr
= force_reg (Pmode
, XEXP (mem
, 0));
1243 /* Align it to SImode. */
1244 align
= expand_simple_binop (Pmode
, AND
, addr
,
1245 GEN_INT (-GET_MODE_SIZE (SImode
)),
1246 NULL_RTX
, 1, OPTAB_DIRECT
);
1248 ac
->memsi
= gen_rtx_MEM (SImode
, align
);
1249 MEM_VOLATILE_P (ac
->memsi
) = MEM_VOLATILE_P (mem
);
1250 set_mem_alias_set (ac
->memsi
, ALIAS_SET_MEMORY_BARRIER
);
1251 set_mem_align (ac
->memsi
, GET_MODE_BITSIZE (SImode
));
1253 byteoffset
= expand_simple_binop (Pmode
, AND
, addr
,
1254 GEN_INT (GET_MODE_SIZE (SImode
) - 1),
1255 NULL_RTX
, 1, OPTAB_DIRECT
);
1258 /* Calculate shiftcount. */
1259 if (TARGET_BIG_ENDIAN
)
1261 ac
->shift
= GEN_INT (GET_MODE_SIZE (SImode
) - GET_MODE_SIZE (mode
));
1263 ac
->shift
= expand_simple_binop (SImode
, MINUS
, ac
->shift
, byteoffset
,
1264 NULL_RTX
, 1, OPTAB_DIRECT
);
1269 ac
->shift
= NULL_RTX
;
1271 ac
->shift
= byteoffset
;
1274 if (ac
->shift
!= NULL_RTX
)
1276 /* Shift is the byte count, but we need the bitcount. */
1277 ac
->shift
= expand_simple_binop (SImode
, MULT
, ac
->shift
,
1278 GEN_INT (BITS_PER_UNIT
),
1279 NULL_RTX
, 1, OPTAB_DIRECT
);
1280 ac
->modemask
= expand_simple_binop (SImode
, ASHIFT
,
1281 GEN_INT (GET_MODE_MASK (mode
)),
1283 NULL_RTX
, 1, OPTAB_DIRECT
);
1286 ac
->modemask
= GEN_INT (GET_MODE_MASK (mode
));
1288 ac
->modemaski
= expand_simple_unop (SImode
, NOT
, ac
->modemask
, NULL_RTX
, 1);
1292 /* Expand an atomic compare and swap operation for HImode and QImode.
1293 MEM is the memory location, CMP the old value to compare MEM with
1294 and NEW the value to set if CMP == MEM. */
1297 xtensa_expand_compare_and_swap (rtx target
, rtx mem
, rtx cmp
, rtx
new)
1299 enum machine_mode mode
= GET_MODE (mem
);
1300 struct alignment_context ac
;
1301 rtx tmp
, cmpv
, newv
, val
;
1302 rtx oldval
= gen_reg_rtx (SImode
);
1303 rtx res
= gen_reg_rtx (SImode
);
1304 rtx csloop
= gen_label_rtx ();
1305 rtx csend
= gen_label_rtx ();
1307 init_alignment_context (&ac
, mem
);
1309 if (ac
.shift
!= NULL_RTX
)
1311 cmp
= xtensa_expand_mask_and_shift (cmp
, mode
, ac
.shift
);
1312 new = xtensa_expand_mask_and_shift (new, mode
, ac
.shift
);
1315 /* Load the surrounding word into VAL with the MEM value masked out. */
1316 val
= force_reg (SImode
, expand_simple_binop (SImode
, AND
, ac
.memsi
,
1317 ac
.modemaski
, NULL_RTX
, 1,
1319 emit_label (csloop
);
1321 /* Patch CMP and NEW into VAL at correct position. */
1322 cmpv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, cmp
, val
,
1323 NULL_RTX
, 1, OPTAB_DIRECT
));
1324 newv
= force_reg (SImode
, expand_simple_binop (SImode
, IOR
, new, val
,
1325 NULL_RTX
, 1, OPTAB_DIRECT
));
1327 /* Jump to end if we're done. */
1328 emit_insn (gen_sync_compare_and_swapsi (res
, ac
.memsi
, cmpv
, newv
));
1329 emit_cmp_and_jump_insns (res
, cmpv
, EQ
, const0_rtx
, SImode
, true, csend
);
1331 /* Check for changes outside mode. */
1332 emit_move_insn (oldval
, val
);
1333 tmp
= expand_simple_binop (SImode
, AND
, res
, ac
.modemaski
,
1334 val
, 1, OPTAB_DIRECT
);
1336 emit_move_insn (val
, tmp
);
1338 /* Loop internal if so. */
1339 emit_cmp_and_jump_insns (oldval
, val
, NE
, const0_rtx
, SImode
, true, csloop
);
1343 /* Return the correct part of the bitfield. */
1344 convert_move (target
,
1345 (ac
.shift
== NULL_RTX
? res
1346 : expand_simple_binop (SImode
, LSHIFTRT
, res
, ac
.shift
,
1347 NULL_RTX
, 1, OPTAB_DIRECT
)),
1352 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode --
1353 the default expansion works fine for SImode). MEM is the memory location
1354 and VAL the value to play with. If AFTER is true then store the value
1355 MEM holds after the operation, if AFTER is false then store the value MEM
1356 holds before the operation. If TARGET is zero then discard that value, else
1357 store it to TARGET. */
1360 xtensa_expand_atomic (enum rtx_code code
, rtx target
, rtx mem
, rtx val
,
1363 enum machine_mode mode
= GET_MODE (mem
);
1364 struct alignment_context ac
;
1365 rtx csloop
= gen_label_rtx ();
1367 rtx old
= gen_reg_rtx (SImode
);
1368 rtx
new = gen_reg_rtx (SImode
);
1369 rtx orig
= NULL_RTX
;
1371 init_alignment_context (&ac
, mem
);
1373 /* Prepare values before the compare-and-swap loop. */
1374 if (ac
.shift
!= NULL_RTX
)
1375 val
= xtensa_expand_mask_and_shift (val
, mode
, ac
.shift
);
1380 orig
= gen_reg_rtx (SImode
);
1381 convert_move (orig
, val
, 1);
1389 case MULT
: /* NAND */
1391 /* val = "11..1<val>11..1" */
1392 val
= expand_simple_binop (SImode
, XOR
, val
, ac
.modemaski
,
1393 NULL_RTX
, 1, OPTAB_DIRECT
);
1400 /* Load full word. Subsequent loads are performed by S32C1I. */
1401 cmp
= force_reg (SImode
, ac
.memsi
);
1403 emit_label (csloop
);
1404 emit_move_insn (old
, cmp
);
1410 val
= expand_simple_binop (SImode
, code
, old
, orig
,
1411 NULL_RTX
, 1, OPTAB_DIRECT
);
1412 val
= expand_simple_binop (SImode
, AND
, val
, ac
.modemask
,
1413 NULL_RTX
, 1, OPTAB_DIRECT
);
1416 tmp
= expand_simple_binop (SImode
, AND
, old
, ac
.modemaski
,
1417 NULL_RTX
, 1, OPTAB_DIRECT
);
1418 tmp
= expand_simple_binop (SImode
, IOR
, tmp
, val
,
1419 new, 1, OPTAB_DIRECT
);
1425 tmp
= expand_simple_binop (SImode
, code
, old
, val
,
1426 new, 1, OPTAB_DIRECT
);
1429 case MULT
: /* NAND */
1430 tmp
= expand_simple_binop (SImode
, XOR
, old
, ac
.modemask
,
1431 NULL_RTX
, 1, OPTAB_DIRECT
);
1432 tmp
= expand_simple_binop (SImode
, AND
, tmp
, val
,
1433 new, 1, OPTAB_DIRECT
);
1441 emit_move_insn (new, tmp
);
1442 emit_insn (gen_sync_compare_and_swapsi (cmp
, ac
.memsi
, old
, new));
1443 emit_cmp_and_jump_insns (cmp
, old
, NE
, const0_rtx
, SImode
, true, csloop
);
1447 tmp
= (after
? new : cmp
);
1448 convert_move (target
,
1449 (ac
.shift
== NULL_RTX
? tmp
1450 : expand_simple_binop (SImode
, LSHIFTRT
, tmp
, ac
.shift
,
1451 NULL_RTX
, 1, OPTAB_DIRECT
)),
1458 xtensa_setup_frame_addresses (void)
1460 /* Set flag to cause FRAME_POINTER_REQUIRED to be set. */
1461 cfun
->machine
->accesses_prev_frame
= 1;
1464 (gen_rtx_SYMBOL_REF (Pmode
, "__xtensa_libgcc_window_spill"),
1469 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit
1470 a comment showing where the end of the loop is. However, if there is a
1471 label or a branch at the end of the loop then we need to place a nop
1472 there. If the loop ends with a label we need the nop so that branches
1473 targeting that label will target the nop (and thus remain in the loop),
1474 instead of targeting the instruction after the loop (and thus exiting
1475 the loop). If the loop ends with a branch, we need the nop in case the
1476 branch is targeting a location inside the loop. When the branch
1477 executes it will cause the loop count to be decremented even if it is
1478 taken (because it is the last instruction in the loop), so we need to
1479 nop after the branch to prevent the loop count from being decremented
1480 when the branch is taken. */
1483 xtensa_emit_loop_end (rtx insn
, rtx
*operands
)
1487 for (insn
= PREV_INSN (insn
); insn
&& !done
; insn
= PREV_INSN (insn
))
1489 switch (GET_CODE (insn
))
1496 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1502 rtx body
= PATTERN (insn
);
1504 if (GET_CODE (body
) == JUMP_INSN
)
1506 output_asm_insn (TARGET_DENSITY
? "nop.n" : "nop", operands
);
1509 else if ((GET_CODE (body
) != USE
)
1510 && (GET_CODE (body
) != CLOBBER
))
1517 output_asm_insn ("# loop end for %0", operands
);
1522 xtensa_emit_branch (bool inverted
, bool immed
, rtx
*operands
)
1524 static char result
[64];
1528 code
= GET_CODE (operands
[3]);
1531 case EQ
: op
= inverted
? "ne" : "eq"; break;
1532 case NE
: op
= inverted
? "eq" : "ne"; break;
1533 case LT
: op
= inverted
? "ge" : "lt"; break;
1534 case GE
: op
= inverted
? "lt" : "ge"; break;
1535 case LTU
: op
= inverted
? "geu" : "ltu"; break;
1536 case GEU
: op
= inverted
? "ltu" : "geu"; break;
1537 default: gcc_unreachable ();
1542 if (INTVAL (operands
[1]) == 0)
1543 sprintf (result
, "b%sz%s\t%%0, %%2", op
,
1544 (TARGET_DENSITY
&& (code
== EQ
|| code
== NE
)) ? ".n" : "");
1546 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1549 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1556 xtensa_emit_bit_branch (bool inverted
, bool immed
, rtx
*operands
)
1558 static char result
[64];
1561 switch (GET_CODE (operands
[3]))
1563 case EQ
: op
= inverted
? "bs" : "bc"; break;
1564 case NE
: op
= inverted
? "bc" : "bs"; break;
1565 default: gcc_unreachable ();
1570 unsigned bitnum
= INTVAL (operands
[1]) & 0x1f;
1571 operands
[1] = GEN_INT (bitnum
);
1572 sprintf (result
, "b%si\t%%0, %%d1, %%2", op
);
1575 sprintf (result
, "b%s\t%%0, %%1, %%2", op
);
1582 xtensa_emit_movcc (bool inverted
, bool isfp
, bool isbool
, rtx
*operands
)
1584 static char result
[64];
1588 code
= GET_CODE (operands
[4]);
1593 case EQ
: op
= inverted
? "t" : "f"; break;
1594 case NE
: op
= inverted
? "f" : "t"; break;
1595 default: gcc_unreachable ();
1602 case EQ
: op
= inverted
? "nez" : "eqz"; break;
1603 case NE
: op
= inverted
? "eqz" : "nez"; break;
1604 case LT
: op
= inverted
? "gez" : "ltz"; break;
1605 case GE
: op
= inverted
? "ltz" : "gez"; break;
1606 default: gcc_unreachable ();
1610 sprintf (result
, "mov%s%s\t%%0, %%%d, %%1",
1611 op
, isfp
? ".s" : "", inverted
? 3 : 2);
1617 xtensa_emit_call (int callop
, rtx
*operands
)
1619 static char result
[64];
1620 rtx tgt
= operands
[callop
];
1622 if (GET_CODE (tgt
) == CONST_INT
)
1623 sprintf (result
, "call8\t0x%lx", INTVAL (tgt
));
1624 else if (register_operand (tgt
, VOIDmode
))
1625 sprintf (result
, "callx8\t%%%d", callop
);
1627 sprintf (result
, "call8\t%%%d", callop
);
1634 xtensa_legitimate_address_p (enum machine_mode mode
, rtx addr
, bool strict
)
1636 /* Allow constant pool addresses. */
1637 if (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
1638 && ! TARGET_CONST16
&& constantpool_address_p (addr
))
1641 while (GET_CODE (addr
) == SUBREG
)
1642 addr
= SUBREG_REG (addr
);
1644 /* Allow base registers. */
1645 if (GET_CODE (addr
) == REG
&& BASE_REG_P (addr
, strict
))
1648 /* Check for "register + offset" addressing. */
1649 if (GET_CODE (addr
) == PLUS
)
1651 rtx xplus0
= XEXP (addr
, 0);
1652 rtx xplus1
= XEXP (addr
, 1);
1653 enum rtx_code code0
;
1654 enum rtx_code code1
;
1656 while (GET_CODE (xplus0
) == SUBREG
)
1657 xplus0
= SUBREG_REG (xplus0
);
1658 code0
= GET_CODE (xplus0
);
1660 while (GET_CODE (xplus1
) == SUBREG
)
1661 xplus1
= SUBREG_REG (xplus1
);
1662 code1
= GET_CODE (xplus1
);
1664 /* Swap operands if necessary so the register is first. */
1665 if (code0
!= REG
&& code1
== REG
)
1667 xplus0
= XEXP (addr
, 1);
1668 xplus1
= XEXP (addr
, 0);
1669 code0
= GET_CODE (xplus0
);
1670 code1
= GET_CODE (xplus1
);
1673 if (code0
== REG
&& BASE_REG_P (xplus0
, strict
)
1674 && code1
== CONST_INT
1675 && xtensa_mem_offset (INTVAL (xplus1
), mode
))
1684 xtensa_legitimize_address (rtx x
,
1685 rtx oldx ATTRIBUTE_UNUSED
,
1686 enum machine_mode mode
)
1688 if (GET_CODE (x
) == PLUS
)
1690 rtx plus0
= XEXP (x
, 0);
1691 rtx plus1
= XEXP (x
, 1);
1693 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1695 plus0
= XEXP (x
, 1);
1696 plus1
= XEXP (x
, 0);
1699 /* Try to split up the offset to use an ADDMI instruction. */
1700 if (GET_CODE (plus0
) == REG
1701 && GET_CODE (plus1
) == CONST_INT
1702 && !xtensa_mem_offset (INTVAL (plus1
), mode
)
1703 && !xtensa_simm8 (INTVAL (plus1
))
1704 && xtensa_mem_offset (INTVAL (plus1
) & 0xff, mode
)
1705 && xtensa_simm8x256 (INTVAL (plus1
) & ~0xff))
1707 rtx temp
= gen_reg_rtx (Pmode
);
1708 rtx addmi_offset
= GEN_INT (INTVAL (plus1
) & ~0xff);
1709 emit_insn (gen_rtx_SET (Pmode
, temp
,
1710 gen_rtx_PLUS (Pmode
, plus0
, addmi_offset
)));
1711 return gen_rtx_PLUS (Pmode
, temp
, GEN_INT (INTVAL (plus1
) & 0xff));
1719 /* Return the debugger register number to use for 'regno'. */
1722 xtensa_dbx_register_number (int regno
)
1726 if (GP_REG_P (regno
))
1728 regno
-= GP_REG_FIRST
;
1731 else if (BR_REG_P (regno
))
1733 regno
-= BR_REG_FIRST
;
1736 else if (FP_REG_P (regno
))
1738 regno
-= FP_REG_FIRST
;
1741 else if (ACC_REG_P (regno
))
1743 first
= 0x200; /* Start of Xtensa special registers. */
1744 regno
= 16; /* ACCLO is special register 16. */
1747 /* When optimizing, we sometimes get asked about pseudo-registers
1748 that don't represent hard registers. Return 0 for these. */
1752 return first
+ regno
;
1756 /* Argument support functions. */
1758 /* Initialize CUMULATIVE_ARGS for a function. */
1761 init_cumulative_args (CUMULATIVE_ARGS
*cum
, int incoming
)
1764 cum
->incoming
= incoming
;
1768 /* Advance the argument to the next argument position. */
1771 function_arg_advance (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
)
1776 arg_words
= &cum
->arg_words
;
1777 max
= MAX_ARGS_IN_REGISTERS
;
1779 words
= (((mode
!= BLKmode
)
1780 ? (int) GET_MODE_SIZE (mode
)
1781 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1783 if (*arg_words
< max
1784 && (targetm
.calls
.must_pass_in_stack (mode
, type
)
1785 || *arg_words
+ words
> max
))
1788 *arg_words
+= words
;
1792 /* Return an RTL expression containing the register for the given mode,
1793 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero
1794 if this is an incoming argument to the current function. */
1797 function_arg (CUMULATIVE_ARGS
*cum
, enum machine_mode mode
, tree type
,
1800 int regbase
, words
, max
;
1804 arg_words
= &cum
->arg_words
;
1805 regbase
= (incoming_p
? GP_ARG_FIRST
: GP_OUTGOING_ARG_FIRST
);
1806 max
= MAX_ARGS_IN_REGISTERS
;
1808 words
= (((mode
!= BLKmode
)
1809 ? (int) GET_MODE_SIZE (mode
)
1810 : int_size_in_bytes (type
)) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1812 if (type
&& (TYPE_ALIGN (type
) > BITS_PER_WORD
))
1814 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_WORD
;
1815 *arg_words
= (*arg_words
+ align
- 1) & -align
;
1818 if (*arg_words
+ words
> max
)
1821 regno
= regbase
+ *arg_words
;
1823 if (cum
->incoming
&& regno
<= A7_REG
&& regno
+ words
> A7_REG
)
1824 cfun
->machine
->need_a7_copy
= true;
1826 return gen_rtx_REG (mode
, regno
);
1831 function_arg_boundary (enum machine_mode mode
, tree type
)
1833 unsigned int alignment
;
1835 alignment
= type
? TYPE_ALIGN (type
) : GET_MODE_ALIGNMENT (mode
);
1836 if (alignment
< PARM_BOUNDARY
)
1837 alignment
= PARM_BOUNDARY
;
1838 if (alignment
> STACK_BOUNDARY
)
1839 alignment
= STACK_BOUNDARY
;
1845 xtensa_return_in_msb (tree valtype
)
1847 return (TARGET_BIG_ENDIAN
1848 && AGGREGATE_TYPE_P (valtype
)
1849 && int_size_in_bytes (valtype
) >= UNITS_PER_WORD
);
1854 override_options (void)
1857 enum machine_mode mode
;
1859 if (!TARGET_BOOLEANS
&& TARGET_HARD_FLOAT
)
1860 error ("boolean registers required for the floating-point option");
1862 /* Set up array giving whether a given register can hold a given mode. */
1863 for (mode
= VOIDmode
;
1864 mode
!= MAX_MACHINE_MODE
;
1865 mode
= (enum machine_mode
) ((int) mode
+ 1))
1867 int size
= GET_MODE_SIZE (mode
);
1868 enum mode_class
class = GET_MODE_CLASS (mode
);
1870 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1874 if (ACC_REG_P (regno
))
1875 temp
= (TARGET_MAC16
1876 && (class == MODE_INT
) && (size
<= UNITS_PER_WORD
));
1877 else if (GP_REG_P (regno
))
1878 temp
= ((regno
& 1) == 0 || (size
<= UNITS_PER_WORD
));
1879 else if (FP_REG_P (regno
))
1880 temp
= (TARGET_HARD_FLOAT
&& (mode
== SFmode
));
1881 else if (BR_REG_P (regno
))
1882 temp
= (TARGET_BOOLEANS
&& (mode
== CCmode
));
1886 xtensa_hard_regno_mode_ok
[(int) mode
][regno
] = temp
;
1890 init_machine_status
= xtensa_init_machine_status
;
1892 /* Check PIC settings. PIC is only supported when using L32R
1893 instructions, and some targets need to always use PIC. */
1894 if (flag_pic
&& TARGET_CONST16
)
1895 error ("-f%s is not supported with CONST16 instructions",
1896 (flag_pic
> 1 ? "PIC" : "pic"));
1897 else if (XTENSA_ALWAYS_PIC
)
1900 error ("PIC is required but not supported with CONST16 instructions");
1903 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */
1907 /* Hot/cold partitioning does not work on this architecture, because of
1908 constant pools (the load instruction cannot necessarily reach that far).
1909 Therefore disable it on this architecture. */
1910 if (flag_reorder_blocks_and_partition
)
1912 flag_reorder_blocks_and_partition
= 0;
1913 flag_reorder_blocks
= 1;
1918 /* A C compound statement to output to stdio stream STREAM the
1919 assembler syntax for an instruction operand X. X is an RTL
1922 CODE is a value that can be used to specify one of several ways
1923 of printing the operand. It is used when identical operands
1924 must be printed differently depending on the context. CODE
1925 comes from the '%' specification that was used to request
1926 printing of the operand. If the specification was just '%DIGIT'
1927 then CODE is 0; if the specification was '%LTR DIGIT' then CODE
1928 is the ASCII code for LTR.
1930 If X is a register, this macro should print the register's name.
1931 The names can be found in an array 'reg_names' whose type is
1932 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'.
1934 When the machine description has a specification '%PUNCT' (a '%'
1935 followed by a punctuation character), this macro is called with
1936 a null pointer for X and the punctuation character for CODE.
1938 'a', 'c', 'l', and 'n' are reserved.
1940 The Xtensa specific codes are:
1942 'd' CONST_INT, print as signed decimal
1943 'x' CONST_INT, print as signed hexadecimal
1944 'K' CONST_INT, print number of bits in mask for EXTUI
1945 'R' CONST_INT, print (X & 0x1f)
1946 'L' CONST_INT, print ((32 - X) & 0x1f)
1947 'D' REG, print second register of double-word register operand
1948 'N' MEM, print address of next word following a memory operand
1949 'v' MEM, if memory reference is volatile, output a MEMW before it
1950 't' any constant, add "@h" suffix for top 16 bits
1951 'b' any constant, add "@l" suffix for bottom 16 bits
1955 printx (FILE *file
, signed int val
)
1957 /* Print a hexadecimal value in a nice way. */
1958 if ((val
> -0xa) && (val
< 0xa))
1959 fprintf (file
, "%d", val
);
1961 fprintf (file
, "-0x%x", -val
);
1963 fprintf (file
, "0x%x", val
);
1968 print_operand (FILE *file
, rtx x
, int letter
)
1971 error ("PRINT_OPERAND null pointer");
1976 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
1977 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
) + 1]);
1979 output_operand_lossage ("invalid %%D value");
1983 if (GET_CODE (x
) == MEM
)
1985 /* For a volatile memory reference, emit a MEMW before the
1987 if (MEM_VOLATILE_P (x
))
1988 fprintf (file
, "memw\n\t");
1991 output_operand_lossage ("invalid %%v value");
1995 if (GET_CODE (x
) == MEM
1996 && (GET_MODE (x
) == DFmode
|| GET_MODE (x
) == DImode
))
1998 x
= adjust_address (x
, GET_MODE (x
) == DFmode
? SFmode
: SImode
, 4);
1999 output_address (XEXP (x
, 0));
2002 output_operand_lossage ("invalid %%N value");
2006 if (GET_CODE (x
) == CONST_INT
)
2009 unsigned val
= INTVAL (x
);
2015 if ((val
!= 0) || (num_bits
== 0) || (num_bits
> 16))
2016 fatal_insn ("invalid mask", x
);
2018 fprintf (file
, "%d", num_bits
);
2021 output_operand_lossage ("invalid %%K value");
2025 if (GET_CODE (x
) == CONST_INT
)
2026 fprintf (file
, "%ld", (32 - INTVAL (x
)) & 0x1f);
2028 output_operand_lossage ("invalid %%L value");
2032 if (GET_CODE (x
) == CONST_INT
)
2033 fprintf (file
, "%ld", INTVAL (x
) & 0x1f);
2035 output_operand_lossage ("invalid %%R value");
2039 if (GET_CODE (x
) == CONST_INT
)
2040 printx (file
, INTVAL (x
));
2042 output_operand_lossage ("invalid %%x value");
2046 if (GET_CODE (x
) == CONST_INT
)
2047 fprintf (file
, "%ld", INTVAL (x
));
2049 output_operand_lossage ("invalid %%d value");
2054 if (GET_CODE (x
) == CONST_INT
)
2056 printx (file
, INTVAL (x
));
2057 fputs (letter
== 't' ? "@h" : "@l", file
);
2059 else if (GET_CODE (x
) == CONST_DOUBLE
)
2062 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2063 if (GET_MODE (x
) == SFmode
)
2066 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
2067 fprintf (file
, "0x%08lx@%c", l
, letter
== 't' ? 'h' : 'l');
2070 output_operand_lossage ("invalid %%t/%%b value");
2072 else if (GET_CODE (x
) == CONST
)
2074 /* X must be a symbolic constant on ELF. Write an expression
2075 suitable for 'const16' that sets the high or low 16 bits. */
2076 if (GET_CODE (XEXP (x
, 0)) != PLUS
2077 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) != SYMBOL_REF
2078 && GET_CODE (XEXP (XEXP (x
, 0), 0)) != LABEL_REF
)
2079 || GET_CODE (XEXP (XEXP (x
, 0), 1)) != CONST_INT
)
2080 output_operand_lossage ("invalid %%t/%%b value");
2081 print_operand (file
, XEXP (XEXP (x
, 0), 0), 0);
2082 fputs (letter
== 't' ? "@h" : "@l", file
);
2083 /* There must be a non-alphanumeric character between 'h' or 'l'
2084 and the number. The '-' is added by print_operand() already. */
2085 if (INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0)
2087 print_operand (file
, XEXP (XEXP (x
, 0), 1), 0);
2091 output_addr_const (file
, x
);
2092 fputs (letter
== 't' ? "@h" : "@l", file
);
2097 if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
2098 fprintf (file
, "%s", reg_names
[xt_true_regnum (x
)]);
2099 else if (GET_CODE (x
) == MEM
)
2100 output_address (XEXP (x
, 0));
2101 else if (GET_CODE (x
) == CONST_INT
)
2102 fprintf (file
, "%ld", INTVAL (x
));
2104 output_addr_const (file
, x
);
2109 /* A C compound statement to output to stdio stream STREAM the
2110 assembler syntax for an instruction operand that is a memory
2111 reference whose address is ADDR. ADDR is an RTL expression. */
2114 print_operand_address (FILE *file
, rtx addr
)
2117 error ("PRINT_OPERAND_ADDRESS, null pointer");
2119 switch (GET_CODE (addr
))
2122 fatal_insn ("invalid address", addr
);
2126 fprintf (file
, "%s, 0", reg_names
[REGNO (addr
)]);
2132 rtx offset
= (rtx
)0;
2133 rtx arg0
= XEXP (addr
, 0);
2134 rtx arg1
= XEXP (addr
, 1);
2136 if (GET_CODE (arg0
) == REG
)
2141 else if (GET_CODE (arg1
) == REG
)
2147 fatal_insn ("no register in address", addr
);
2149 if (CONSTANT_P (offset
))
2151 fprintf (file
, "%s, ", reg_names
[REGNO (reg
)]);
2152 output_addr_const (file
, offset
);
2155 fatal_insn ("address offset not a constant", addr
);
2163 output_addr_const (file
, addr
);
2170 xtensa_output_addr_const_extra (FILE *fp
, rtx x
)
2172 if (GET_CODE (x
) == UNSPEC
&& XVECLEN (x
, 0) == 1)
2174 switch (XINT (x
, 1))
2179 output_addr_const (fp
, XVECEXP (x
, 0, 0));
2193 xtensa_output_literal (FILE *file
, rtx x
, enum machine_mode mode
, int labelno
)
2200 fprintf (file
, "\t.literal .LC%u, ", (unsigned) labelno
);
2202 switch (GET_MODE_CLASS (mode
))
2205 gcc_assert (GET_CODE (x
) == CONST_DOUBLE
);
2207 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
2211 REAL_VALUE_TO_TARGET_SINGLE (r
, value_long
[0]);
2212 if (HOST_BITS_PER_LONG
> 32)
2213 value_long
[0] &= 0xffffffff;
2214 fprintf (file
, "0x%08lx\n", value_long
[0]);
2218 REAL_VALUE_TO_TARGET_DOUBLE (r
, value_long
);
2219 if (HOST_BITS_PER_LONG
> 32)
2221 value_long
[0] &= 0xffffffff;
2222 value_long
[1] &= 0xffffffff;
2224 fprintf (file
, "0x%08lx, 0x%08lx\n",
2225 value_long
[0], value_long
[1]);
2235 case MODE_PARTIAL_INT
:
2236 size
= GET_MODE_SIZE (mode
);
2240 output_addr_const (file
, x
);
2245 split_double (x
, &first
, &second
);
2246 output_addr_const (file
, first
);
2248 output_addr_const (file
, second
);
2263 /* Return the bytes needed to compute the frame pointer from the current
2266 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT)
2267 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1))
2270 compute_frame_size (int size
)
2272 /* Add space for the incoming static chain value. */
2273 if (cfun
->static_chain_decl
!= NULL
)
2274 size
+= (1 * UNITS_PER_WORD
);
2276 xtensa_current_frame_size
=
2277 XTENSA_STACK_ALIGN (size
2278 + current_function_outgoing_args_size
2279 + (WINDOW_SIZE
* UNITS_PER_WORD
));
2280 return xtensa_current_frame_size
;
2285 xtensa_frame_pointer_required (void)
2287 /* The code to expand builtin_frame_addr and builtin_return_addr
2288 currently uses the hard_frame_pointer instead of frame_pointer.
2289 This seems wrong but maybe it's necessary for other architectures.
2290 This function is derived from the i386 code. */
2292 if (cfun
->machine
->accesses_prev_frame
)
2300 xtensa_expand_prologue (void)
2302 HOST_WIDE_INT total_size
;
2305 total_size
= compute_frame_size (get_frame_size ());
2306 size_rtx
= GEN_INT (total_size
);
2308 if (total_size
< (1 << (12+3)))
2309 emit_insn (gen_entry (size_rtx
, size_rtx
));
2312 /* Use a8 as a temporary since a0-a7 may be live. */
2313 rtx tmp_reg
= gen_rtx_REG (Pmode
, A8_REG
);
2314 emit_insn (gen_entry (size_rtx
, GEN_INT (MIN_FRAME_SIZE
)));
2315 emit_move_insn (tmp_reg
, GEN_INT (total_size
- MIN_FRAME_SIZE
));
2316 emit_insn (gen_subsi3 (tmp_reg
, stack_pointer_rtx
, tmp_reg
));
2317 emit_move_insn (stack_pointer_rtx
, tmp_reg
);
2320 if (frame_pointer_needed
)
2322 if (cfun
->machine
->set_frame_ptr_insn
)
2326 push_topmost_sequence ();
2327 first
= get_insns ();
2328 pop_topmost_sequence ();
2330 /* For all instructions prior to set_frame_ptr_insn, replace
2331 hard_frame_pointer references with stack_pointer. */
2333 insn
!= cfun
->machine
->set_frame_ptr_insn
;
2334 insn
= NEXT_INSN (insn
))
2338 PATTERN (insn
) = replace_rtx (copy_rtx (PATTERN (insn
)),
2339 hard_frame_pointer_rtx
,
2341 df_insn_rescan (insn
);
2346 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
2351 /* Clear variables at function end. */
2354 xtensa_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
2355 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
2357 xtensa_current_frame_size
= 0;
2362 xtensa_return_addr (int count
, rtx frame
)
2364 rtx result
, retaddr
;
2367 retaddr
= gen_rtx_REG (Pmode
, A0_REG
);
2370 rtx addr
= plus_constant (frame
, -4 * UNITS_PER_WORD
);
2371 addr
= memory_address (Pmode
, addr
);
2372 retaddr
= gen_reg_rtx (Pmode
);
2373 emit_move_insn (retaddr
, gen_rtx_MEM (Pmode
, addr
));
2376 /* The 2 most-significant bits of the return address on Xtensa hold
2377 the register window size. To get the real return address, these
2378 bits must be replaced with the high bits from the current PC. */
2380 result
= gen_reg_rtx (Pmode
);
2381 emit_insn (gen_fix_return_addr (result
, retaddr
));
2386 /* Create the va_list data type.
2388 This structure is set up by __builtin_saveregs. The __va_reg field
2389 points to a stack-allocated region holding the contents of the
2390 incoming argument registers. The __va_ndx field is an index
2391 initialized to the position of the first unnamed (variable)
2392 argument. This same index is also used to address the arguments
2393 passed in memory. Thus, the __va_stk field is initialized to point
2394 to the position of the first argument in memory offset to account
2395 for the arguments passed in registers and to account for the size
2396 of the argument registers not being 16-byte aligned. E.G., there
2397 are 6 argument registers of 4 bytes each, but we want the __va_ndx
2398 for the first stack argument to have the maximal alignment of 16
2399 bytes, so we offset the __va_stk address by 32 bytes so that
2400 __va_stk[32] references the first argument on the stack. */
2403 xtensa_build_builtin_va_list (void)
2405 tree f_stk
, f_reg
, f_ndx
, record
, type_decl
;
2407 record
= (*lang_hooks
.types
.make_type
) (RECORD_TYPE
);
2408 type_decl
= build_decl (TYPE_DECL
, get_identifier ("__va_list_tag"), record
);
2410 f_stk
= build_decl (FIELD_DECL
, get_identifier ("__va_stk"),
2412 f_reg
= build_decl (FIELD_DECL
, get_identifier ("__va_reg"),
2414 f_ndx
= build_decl (FIELD_DECL
, get_identifier ("__va_ndx"),
2417 DECL_FIELD_CONTEXT (f_stk
) = record
;
2418 DECL_FIELD_CONTEXT (f_reg
) = record
;
2419 DECL_FIELD_CONTEXT (f_ndx
) = record
;
2421 TREE_CHAIN (record
) = type_decl
;
2422 TYPE_NAME (record
) = type_decl
;
2423 TYPE_FIELDS (record
) = f_stk
;
2424 TREE_CHAIN (f_stk
) = f_reg
;
2425 TREE_CHAIN (f_reg
) = f_ndx
;
2427 layout_type (record
);
2432 /* Save the incoming argument registers on the stack. Returns the
2433 address of the saved registers. */
2436 xtensa_builtin_saveregs (void)
2439 int arg_words
= current_function_args_info
.arg_words
;
2440 int gp_left
= MAX_ARGS_IN_REGISTERS
- arg_words
;
2445 /* Allocate the general-purpose register space. */
2446 gp_regs
= assign_stack_local
2447 (BLKmode
, MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
, -1);
2448 set_mem_alias_set (gp_regs
, get_varargs_alias_set ());
2450 /* Now store the incoming registers. */
2451 cfun
->machine
->need_a7_copy
= true;
2452 cfun
->machine
->vararg_a7
= true;
2453 move_block_from_reg (GP_ARG_FIRST
+ arg_words
,
2454 adjust_address (gp_regs
, BLKmode
,
2455 arg_words
* UNITS_PER_WORD
),
2458 return XEXP (gp_regs
, 0);
2462 /* Implement `va_start' for varargs and stdarg. We look at the
2463 current function to fill in an initial va_list. */
2466 xtensa_va_start (tree valist
, rtx nextarg ATTRIBUTE_UNUSED
)
2474 arg_words
= current_function_args_info
.arg_words
;
2476 f_stk
= TYPE_FIELDS (va_list_type_node
);
2477 f_reg
= TREE_CHAIN (f_stk
);
2478 f_ndx
= TREE_CHAIN (f_reg
);
2480 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
2481 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), valist
, f_reg
, NULL_TREE
);
2482 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), valist
, f_ndx
, NULL_TREE
);
2484 /* Call __builtin_saveregs; save the result in __va_reg */
2485 u
= make_tree (sizetype
, expand_builtin_saveregs ());
2486 u
= fold_convert (ptr_type_node
, u
);
2487 t
= build2 (GIMPLE_MODIFY_STMT
, ptr_type_node
, reg
, u
);
2488 TREE_SIDE_EFFECTS (t
) = 1;
2489 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2491 /* Set the __va_stk member to ($arg_ptr - 32). */
2492 u
= make_tree (ptr_type_node
, virtual_incoming_args_rtx
);
2493 u
= fold_build2 (POINTER_PLUS_EXPR
, ptr_type_node
, u
, size_int (-32));
2494 t
= build2 (GIMPLE_MODIFY_STMT
, ptr_type_node
, stk
, u
);
2495 TREE_SIDE_EFFECTS (t
) = 1;
2496 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2498 /* Set the __va_ndx member. If the first variable argument is on
2499 the stack, adjust __va_ndx by 2 words to account for the extra
2500 alignment offset for __va_stk. */
2501 if (arg_words
>= MAX_ARGS_IN_REGISTERS
)
2503 t
= build2 (GIMPLE_MODIFY_STMT
, integer_type_node
, ndx
,
2504 size_int (arg_words
* UNITS_PER_WORD
));
2505 TREE_SIDE_EFFECTS (t
) = 1;
2506 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2510 /* Implement `va_arg'. */
2513 xtensa_gimplify_va_arg_expr (tree valist
, tree type
, tree
*pre_p
,
2514 tree
*post_p ATTRIBUTE_UNUSED
)
2519 tree type_size
, array
, orig_ndx
, addr
, size
, va_size
, t
;
2520 tree lab_false
, lab_over
, lab_false2
;
2523 indirect
= pass_by_reference (NULL
, TYPE_MODE (type
), type
, false);
2525 type
= build_pointer_type (type
);
2527 /* Handle complex values as separate real and imaginary parts. */
2528 if (TREE_CODE (type
) == COMPLEX_TYPE
)
2530 tree real_part
, imag_part
;
2532 real_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
2534 real_part
= get_initialized_tmp_var (real_part
, pre_p
, NULL
);
2536 imag_part
= xtensa_gimplify_va_arg_expr (valist
, TREE_TYPE (type
),
2538 imag_part
= get_initialized_tmp_var (imag_part
, pre_p
, NULL
);
2540 return build2 (COMPLEX_EXPR
, type
, real_part
, imag_part
);
2543 f_stk
= TYPE_FIELDS (va_list_type_node
);
2544 f_reg
= TREE_CHAIN (f_stk
);
2545 f_ndx
= TREE_CHAIN (f_reg
);
2547 stk
= build3 (COMPONENT_REF
, TREE_TYPE (f_stk
), valist
, f_stk
, NULL_TREE
);
2548 reg
= build3 (COMPONENT_REF
, TREE_TYPE (f_reg
), valist
, f_reg
, NULL_TREE
);
2549 ndx
= build3 (COMPONENT_REF
, TREE_TYPE (f_ndx
), valist
, f_ndx
, NULL_TREE
);
2551 type_size
= size_in_bytes (type
);
2552 va_size
= round_up (type_size
, UNITS_PER_WORD
);
2553 gimplify_expr (&va_size
, pre_p
, NULL
, is_gimple_val
, fb_rvalue
);
2556 /* First align __va_ndx if necessary for this arg:
2558 orig_ndx = (AP).__va_ndx;
2559 if (__alignof__ (TYPE) > 4 )
2560 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1)
2561 & -__alignof__ (TYPE)); */
2563 orig_ndx
= get_initialized_tmp_var (ndx
, pre_p
, NULL
);
2565 if (TYPE_ALIGN (type
) > BITS_PER_WORD
)
2567 int align
= MIN (TYPE_ALIGN (type
), STACK_BOUNDARY
) / BITS_PER_UNIT
;
2569 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
, size_int (align
- 1));
2570 t
= build2 (BIT_AND_EXPR
, integer_type_node
, t
, size_int (-align
));
2571 t
= build2 (GIMPLE_MODIFY_STMT
, integer_type_node
, orig_ndx
, t
);
2572 gimplify_and_add (t
, pre_p
);
2576 /* Increment __va_ndx to point past the argument:
2578 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */
2580 t
= fold_convert (integer_type_node
, va_size
);
2581 t
= build2 (PLUS_EXPR
, integer_type_node
, orig_ndx
, t
);
2582 t
= build2 (GIMPLE_MODIFY_STMT
, integer_type_node
, ndx
, t
);
2583 gimplify_and_add (t
, pre_p
);
2586 /* Check if the argument is in registers:
2588 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4
2589 && !must_pass_in_stack (type))
2590 __array = (AP).__va_reg; */
2592 array
= create_tmp_var (ptr_type_node
, NULL
);
2595 if (!targetm
.calls
.must_pass_in_stack (TYPE_MODE (type
), type
))
2597 lab_false
= create_artificial_label ();
2598 lab_over
= create_artificial_label ();
2600 t
= build2 (GT_EXPR
, boolean_type_node
, ndx
,
2601 size_int (MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2602 t
= build3 (COND_EXPR
, void_type_node
, t
,
2603 build1 (GOTO_EXPR
, void_type_node
, lab_false
),
2605 gimplify_and_add (t
, pre_p
);
2607 t
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, array
, reg
);
2608 gimplify_and_add (t
, pre_p
);
2610 t
= build1 (GOTO_EXPR
, void_type_node
, lab_over
);
2611 gimplify_and_add (t
, pre_p
);
2613 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false
);
2614 gimplify_and_add (t
, pre_p
);
2618 /* ...otherwise, the argument is on the stack (never split between
2619 registers and the stack -- change __va_ndx if necessary):
2623 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4)
2624 (AP).__va_ndx = 32 + __va_size (TYPE);
2625 __array = (AP).__va_stk;
2628 lab_false2
= create_artificial_label ();
2630 t
= build2 (GT_EXPR
, boolean_type_node
, orig_ndx
,
2631 size_int (MAX_ARGS_IN_REGISTERS
* UNITS_PER_WORD
));
2632 t
= build3 (COND_EXPR
, void_type_node
, t
,
2633 build1 (GOTO_EXPR
, void_type_node
, lab_false2
),
2635 gimplify_and_add (t
, pre_p
);
2637 t
= size_binop (PLUS_EXPR
, va_size
, size_int (32));
2638 t
= fold_convert (integer_type_node
, t
);
2639 t
= build2 (GIMPLE_MODIFY_STMT
, integer_type_node
, ndx
, t
);
2640 gimplify_and_add (t
, pre_p
);
2642 t
= build1 (LABEL_EXPR
, void_type_node
, lab_false2
);
2643 gimplify_and_add (t
, pre_p
);
2645 t
= build2 (GIMPLE_MODIFY_STMT
, void_type_node
, array
, stk
);
2646 gimplify_and_add (t
, pre_p
);
2650 t
= build1 (LABEL_EXPR
, void_type_node
, lab_over
);
2651 gimplify_and_add (t
, pre_p
);
2655 /* Given the base array pointer (__array) and index to the subsequent
2656 argument (__va_ndx), find the address:
2658 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4
2662 The results are endian-dependent because values smaller than one word
2663 are aligned differently. */
2666 if (BYTES_BIG_ENDIAN
&& TREE_CODE (type_size
) == INTEGER_CST
)
2668 t
= fold_build2 (GE_EXPR
, boolean_type_node
, type_size
,
2669 size_int (PARM_BOUNDARY
/ BITS_PER_UNIT
));
2670 t
= fold_build3 (COND_EXPR
, sizetype
, t
, va_size
, type_size
);
2676 t
= build2 (MINUS_EXPR
, sizetype
, ndx
, size
);
2677 addr
= build2 (POINTER_PLUS_EXPR
, ptr_type_node
, array
, t
);
2679 addr
= fold_convert (build_pointer_type (type
), addr
);
2681 addr
= build_va_arg_indirect_ref (addr
);
2682 return build_va_arg_indirect_ref (addr
);
2690 XTENSA_BUILTIN_UMULSIDI3
,
2696 xtensa_init_builtins (void)
2700 ftype
= build_function_type_list (unsigned_intDI_type_node
,
2701 unsigned_intSI_type_node
,
2702 unsigned_intSI_type_node
, NULL_TREE
);
2704 add_builtin_function ("__builtin_umulsidi3", ftype
,
2705 XTENSA_BUILTIN_UMULSIDI3
, BUILT_IN_MD
,
2706 "__umulsidi3", NULL_TREE
);
2711 xtensa_fold_builtin (tree fndecl
, tree arglist
, bool ignore ATTRIBUTE_UNUSED
)
2713 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
2716 if (fcode
== XTENSA_BUILTIN_UMULSIDI3
)
2718 arg0
= TREE_VALUE (arglist
);
2719 arg1
= TREE_VALUE (TREE_CHAIN (arglist
));
2720 if ((TREE_CODE (arg0
) == INTEGER_CST
&& TREE_CODE (arg1
) == INTEGER_CST
)
2721 || TARGET_MUL32_HIGH
)
2722 return fold_build2 (MULT_EXPR
, unsigned_intDI_type_node
,
2723 fold_convert (unsigned_intDI_type_node
, arg0
),
2724 fold_convert (unsigned_intDI_type_node
, arg1
));
2729 internal_error ("bad builtin code");
2735 xtensa_expand_builtin (tree exp
, rtx target
,
2736 rtx subtarget ATTRIBUTE_UNUSED
,
2737 enum machine_mode mode ATTRIBUTE_UNUSED
,
2740 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
2741 unsigned int fcode
= DECL_FUNCTION_CODE (fndecl
);
2743 /* The umulsidi3 builtin is just a mechanism to avoid calling the real
2744 __umulsidi3 function when the Xtensa configuration can directly
2745 implement it. If not, just call the function. */
2746 if (fcode
== XTENSA_BUILTIN_UMULSIDI3
)
2747 return expand_call (exp
, target
, ignore
);
2749 internal_error ("bad builtin code");
2755 xtensa_preferred_reload_class (rtx x
, enum reg_class
class, int isoutput
)
2757 if (!isoutput
&& CONSTANT_P (x
) && GET_CODE (x
) == CONST_DOUBLE
)
2760 /* Don't use the stack pointer or hard frame pointer for reloads!
2761 The hard frame pointer would normally be OK except that it may
2762 briefly hold an incoming argument in the prologue, and reload
2763 won't know that it is live because the hard frame pointer is
2764 treated specially. */
2766 if (class == AR_REGS
|| class == GR_REGS
)
2774 xtensa_secondary_reload_class (enum reg_class
class,
2775 enum machine_mode mode ATTRIBUTE_UNUSED
,
2776 rtx x
, int isoutput
)
2780 if (GET_CODE (x
) == SIGN_EXTEND
)
2782 regno
= xt_true_regnum (x
);
2786 if (class == FP_REGS
&& constantpool_mem_p (x
))
2790 if (ACC_REG_P (regno
))
2791 return ((class == GR_REGS
|| class == RL_REGS
) ? NO_REGS
: RL_REGS
);
2792 if (class == ACC_REG
)
2793 return (GP_REG_P (regno
) ? NO_REGS
: RL_REGS
);
2800 order_regs_for_local_alloc (void)
2802 if (!leaf_function_p ())
2804 memcpy (reg_alloc_order
, reg_nonleaf_alloc_order
,
2805 FIRST_PSEUDO_REGISTER
* sizeof (int));
2809 int i
, num_arg_regs
;
2812 /* Use the AR registers in increasing order (skipping a0 and a1)
2813 but save the incoming argument registers for a last resort. */
2814 num_arg_regs
= current_function_args_info
.arg_words
;
2815 if (num_arg_regs
> MAX_ARGS_IN_REGISTERS
)
2816 num_arg_regs
= MAX_ARGS_IN_REGISTERS
;
2817 for (i
= GP_ARG_FIRST
; i
< 16 - num_arg_regs
; i
++)
2818 reg_alloc_order
[nxt
++] = i
+ num_arg_regs
;
2819 for (i
= 0; i
< num_arg_regs
; i
++)
2820 reg_alloc_order
[nxt
++] = GP_ARG_FIRST
+ i
;
2822 /* List the coprocessor registers in order. */
2823 for (i
= 0; i
< BR_REG_NUM
; i
++)
2824 reg_alloc_order
[nxt
++] = BR_REG_FIRST
+ i
;
2826 /* List the FP registers in order for now. */
2827 for (i
= 0; i
< 16; i
++)
2828 reg_alloc_order
[nxt
++] = FP_REG_FIRST
+ i
;
2830 /* GCC requires that we list *all* the registers.... */
2831 reg_alloc_order
[nxt
++] = 0; /* a0 = return address */
2832 reg_alloc_order
[nxt
++] = 1; /* a1 = stack pointer */
2833 reg_alloc_order
[nxt
++] = 16; /* pseudo frame pointer */
2834 reg_alloc_order
[nxt
++] = 17; /* pseudo arg pointer */
2836 reg_alloc_order
[nxt
++] = ACC_REG_FIRST
; /* MAC16 accumulator */
2841 /* Some Xtensa targets support multiple bss sections. If the section
2842 name ends with ".bss", add SECTION_BSS to the flags. */
2845 xtensa_multibss_section_type_flags (tree decl
, const char *name
, int reloc
)
2847 unsigned int flags
= default_section_type_flags (decl
, name
, reloc
);
2850 suffix
= strrchr (name
, '.');
2851 if (suffix
&& strcmp (suffix
, ".bss") == 0)
2853 if (!decl
|| (TREE_CODE (decl
) == VAR_DECL
2854 && DECL_INITIAL (decl
) == NULL_TREE
))
2855 flags
|= SECTION_BSS
; /* @nobits */
2857 warning (0, "only uninitialized variables can be placed in a "
2865 /* The literal pool stays with the function. */
2868 xtensa_select_rtx_section (enum machine_mode mode ATTRIBUTE_UNUSED
,
2869 rtx x ATTRIBUTE_UNUSED
,
2870 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED
)
2872 return function_section (current_function_decl
);
2876 /* Compute a (partial) cost for rtx X. Return true if the complete
2877 cost has been computed, and false if subexpressions should be
2878 scanned. In either case, *TOTAL contains the cost result. */
2881 xtensa_rtx_costs (rtx x
, int code
, int outer_code
, int *total
)
2889 if (xtensa_simm12b (INTVAL (x
)))
2896 if (xtensa_simm8 (INTVAL (x
))
2897 || xtensa_simm8x256 (INTVAL (x
)))
2904 if (xtensa_mask_immediate (INTVAL (x
)))
2911 if ((INTVAL (x
) == 0) || xtensa_b4const (INTVAL (x
)))
2922 /* No way to tell if X is the 2nd operand so be conservative. */
2925 if (xtensa_simm12b (INTVAL (x
)))
2927 else if (TARGET_CONST16
)
2928 *total
= COSTS_N_INSNS (2);
2937 *total
= COSTS_N_INSNS (2);
2944 *total
= COSTS_N_INSNS (4);
2952 (GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
) ? 2 : 1;
2954 if (memory_address_p (GET_MODE (x
), XEXP ((x
), 0)))
2955 *total
= COSTS_N_INSNS (num_words
);
2957 *total
= COSTS_N_INSNS (2*num_words
);
2963 *total
= COSTS_N_INSNS (TARGET_NSA
? 5 : 50);
2967 *total
= COSTS_N_INSNS (TARGET_NSA
? 1 : 50);
2971 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 3 : 2);
2977 if (GET_MODE (x
) == DImode
)
2978 *total
= COSTS_N_INSNS (2);
2980 *total
= COSTS_N_INSNS (1);
2986 if (GET_MODE (x
) == DImode
)
2987 *total
= COSTS_N_INSNS (50);
2989 *total
= COSTS_N_INSNS (1);
2994 enum machine_mode xmode
= GET_MODE (x
);
2995 if (xmode
== SFmode
)
2996 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
2997 else if (xmode
== DFmode
)
2998 *total
= COSTS_N_INSNS (50);
3000 *total
= COSTS_N_INSNS (4);
3007 enum machine_mode xmode
= GET_MODE (x
);
3008 if (xmode
== SFmode
)
3009 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 1 : 50);
3010 else if (xmode
== DFmode
|| xmode
== DImode
)
3011 *total
= COSTS_N_INSNS (50);
3013 *total
= COSTS_N_INSNS (1);
3018 *total
= COSTS_N_INSNS ((GET_MODE (x
) == DImode
) ? 4 : 2);
3023 enum machine_mode xmode
= GET_MODE (x
);
3024 if (xmode
== SFmode
)
3025 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT
? 4 : 50);
3026 else if (xmode
== DFmode
)
3027 *total
= COSTS_N_INSNS (50);
3028 else if (xmode
== DImode
)
3029 *total
= COSTS_N_INSNS (TARGET_MUL32_HIGH
? 10 : 50);
3030 else if (TARGET_MUL32
)
3031 *total
= COSTS_N_INSNS (4);
3032 else if (TARGET_MAC16
)
3033 *total
= COSTS_N_INSNS (16);
3034 else if (TARGET_MUL16
)
3035 *total
= COSTS_N_INSNS (12);
3037 *total
= COSTS_N_INSNS (50);
3044 enum machine_mode xmode
= GET_MODE (x
);
3045 if (xmode
== SFmode
)
3047 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV
? 8 : 50);
3050 else if (xmode
== DFmode
)
3052 *total
= COSTS_N_INSNS (50);
3061 enum machine_mode xmode
= GET_MODE (x
);
3062 if (xmode
== DImode
)
3063 *total
= COSTS_N_INSNS (50);
3064 else if (TARGET_DIV32
)
3065 *total
= COSTS_N_INSNS (32);
3067 *total
= COSTS_N_INSNS (50);
3072 if (GET_MODE (x
) == SFmode
)
3073 *total
= COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT
? 8 : 50);
3075 *total
= COSTS_N_INSNS (50);
3082 *total
= COSTS_N_INSNS (TARGET_MINMAX
? 1 : 50);
3087 *total
= COSTS_N_INSNS (TARGET_SEXT
? 1 : 2);
3092 *total
= COSTS_N_INSNS (1);
3100 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3103 xtensa_return_in_memory (tree type
, tree fntype ATTRIBUTE_UNUSED
)
3105 return ((unsigned HOST_WIDE_INT
) int_size_in_bytes (type
)
3106 > 4 * UNITS_PER_WORD
);
3109 #include "gt-xtensa.h"