1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
3 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
25 /* External variables defined in xtensa.c. */
27 extern unsigned xtensa_current_frame_size
;
29 /* Macros used in the machine description to select various Xtensa
30 configuration options. */
31 #ifndef XCHAL_HAVE_MUL32_HIGH
32 #define XCHAL_HAVE_MUL32_HIGH 0
34 #ifndef XCHAL_HAVE_RELEASE_SYNC
35 #define XCHAL_HAVE_RELEASE_SYNC 0
37 #ifndef XCHAL_HAVE_S32C1I
38 #define XCHAL_HAVE_S32C1I 0
40 #ifndef XCHAL_HAVE_THREADPTR
41 #define XCHAL_HAVE_THREADPTR 0
43 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
44 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
45 #define TARGET_MAC16 XCHAL_HAVE_MAC16
46 #define TARGET_MUL16 XCHAL_HAVE_MUL16
47 #define TARGET_MUL32 XCHAL_HAVE_MUL32
48 #define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH
49 #define TARGET_DIV32 XCHAL_HAVE_DIV32
50 #define TARGET_NSA XCHAL_HAVE_NSA
51 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
52 #define TARGET_SEXT XCHAL_HAVE_SEXT
53 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
54 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
55 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
56 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
57 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
58 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
59 #define TARGET_ABS XCHAL_HAVE_ABS
60 #define TARGET_ADDX XCHAL_HAVE_ADDX
61 #define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC
62 #define TARGET_S32C1I XCHAL_HAVE_S32C1I
63 #define TARGET_ABSOLUTE_LITERALS XSHAL_USE_ABSOLUTE_LITERALS
64 #define TARGET_THREADPTR XCHAL_HAVE_THREADPTR
66 #define TARGET_DEFAULT \
67 ((XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \
68 MASK_SERIALIZE_VOLATILE)
75 /* Target CPU builtins. */
76 #define TARGET_CPU_CPP_BUILTINS() \
78 builtin_assert ("cpu=xtensa"); \
79 builtin_assert ("machine=xtensa"); \
80 builtin_define ("__xtensa__"); \
81 builtin_define ("__XTENSA__"); \
82 builtin_define ("__XTENSA_WINDOWED_ABI__"); \
83 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
84 if (!TARGET_HARD_FLOAT) \
85 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
88 #define CPP_SPEC " %(subtarget_cpp_spec) "
90 #ifndef SUBTARGET_CPP_SPEC
91 #define SUBTARGET_CPP_SPEC ""
95 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
98 #define LIBGCC2_WORDS_BIG_ENDIAN 1
100 #define LIBGCC2_WORDS_BIG_ENDIAN 0
103 /* Show we can debug even without a frame pointer. */
104 #define CAN_DEBUG_WITHOUT_FP
107 /* Target machine storage layout */
109 /* Define this if most significant bit is lowest numbered
110 in instructions that operate on numbered bit-fields. */
111 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
113 /* Define this if most significant byte of a word is the lowest numbered. */
114 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
116 /* Define this if most significant word of a multiword number is the lowest. */
117 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
119 #define MAX_BITS_PER_WORD 32
121 /* Width of a word, in units (bytes). */
122 #define UNITS_PER_WORD 4
123 #define MIN_UNITS_PER_WORD 4
125 /* Width of a floating point register. */
126 #define UNITS_PER_FPREG 4
128 /* Size in bits of various types on the target machine. */
129 #define INT_TYPE_SIZE 32
130 #define SHORT_TYPE_SIZE 16
131 #define LONG_TYPE_SIZE 32
132 #define LONG_LONG_TYPE_SIZE 64
133 #define FLOAT_TYPE_SIZE 32
134 #define DOUBLE_TYPE_SIZE 64
135 #define LONG_DOUBLE_TYPE_SIZE 64
137 /* Allocation boundary (in *bits*) for storing pointers in memory. */
138 #define POINTER_BOUNDARY 32
140 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
141 #define PARM_BOUNDARY 32
143 /* Allocation boundary (in *bits*) for the code of a function. */
144 #define FUNCTION_BOUNDARY 32
146 /* Alignment of field after 'int : 0' in a structure. */
147 #define EMPTY_FIELD_BOUNDARY 32
149 /* Every structure's size must be a multiple of this. */
150 #define STRUCTURE_SIZE_BOUNDARY 8
152 /* There is no point aligning anything to a rounder boundary than this. */
153 #define BIGGEST_ALIGNMENT 128
155 /* Set this nonzero if move instructions will actually fail to work
156 when given unaligned data. */
157 #define STRICT_ALIGNMENT 1
159 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
160 for QImode, because there is no 8-bit load from memory with sign
161 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
162 loads both with and without sign extension. */
163 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
165 if (GET_MODE_CLASS (MODE) == MODE_INT \
166 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
168 if ((MODE) == QImode) \
174 /* Imitate the way many other C compilers handle alignment of
175 bitfields and the structures that contain them. */
176 #define PCC_BITFIELD_TYPE_MATTERS 1
178 /* Disable the use of word-sized or smaller complex modes for structures,
179 and for function arguments in particular, where they cause problems with
180 register a7. The xtensa_copy_incoming_a7 function assumes that there is
181 a single reference to an argument in a7, but with small complex modes the
182 real and imaginary components may be extracted separately, leading to two
183 uses of the register, only one of which would be replaced. */
184 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
185 ((MODE) == CQImode || (MODE) == CHImode)
187 /* Align string constants and constructors to at least a word boundary.
188 The typical use of this macro is to increase alignment for string
189 constants to be word aligned so that 'strcpy' calls that copy
190 constants can be done inline. */
191 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
192 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
193 && (ALIGN) < BITS_PER_WORD \
197 /* Align arrays, unions and records to at least a word boundary.
198 One use of this macro is to increase alignment of medium-size
199 data to make it all fit in fewer cache lines. Another is to
200 cause character arrays to be word-aligned so that 'strcpy' calls
201 that copy constants to character arrays can be done inline. */
202 #undef DATA_ALIGNMENT
203 #define DATA_ALIGNMENT(TYPE, ALIGN) \
204 ((((ALIGN) < BITS_PER_WORD) \
205 && (TREE_CODE (TYPE) == ARRAY_TYPE \
206 || TREE_CODE (TYPE) == UNION_TYPE \
207 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
209 /* Operations between registers always perform the operation
210 on the full register even if a narrower mode is specified. */
211 #define WORD_REGISTER_OPERATIONS
213 /* Xtensa loads are zero-extended by default. */
214 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
216 /* Standard register usage. */
218 /* Number of actual hardware registers.
219 The hardware registers are assigned numbers for the compiler
220 from 0 to just below FIRST_PSEUDO_REGISTER.
221 All registers that the compiler knows about must be given numbers,
222 even those that are not normally considered general registers.
224 The fake frame pointer and argument pointer will never appear in
225 the generated code, since they will always be eliminated and replaced
226 by either the stack pointer or the hard frame pointer.
228 0 - 15 AR[0] - AR[15]
229 16 FRAME_POINTER (fake = initial sp)
230 17 ARG_POINTER (fake = initial sp + framesize)
231 18 BR[0] for floating-point CC
232 19 - 34 FR[0] - FR[15]
233 35 MAC16 accumulator */
235 #define FIRST_PSEUDO_REGISTER 36
237 /* Return the stabs register number to use for REGNO. */
238 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
240 /* 1 for registers that have pervasive standard uses
241 and are not available for the register allocator. */
242 #define FIXED_REGISTERS \
244 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
246 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
250 /* 1 for registers not available across function calls.
251 These must include the FIXED_REGISTERS and also any
252 registers that can be used without being saved.
253 The latter must include the registers where values are returned
254 and the register where structure-value addresses are passed.
255 Aside from that, you can include as many other registers as you like. */
256 #define CALL_USED_REGISTERS \
258 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
260 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
264 /* For non-leaf procedures on Xtensa processors, the allocation order
265 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
266 want to use the lowest numbered registers first to minimize
267 register window overflows. However, local-alloc is not smart
268 enough to consider conflicts with incoming arguments. If an
269 incoming argument in a2 is live throughout the function and
270 local-alloc decides to use a2, then the incoming argument must
271 either be spilled or copied to another register. To get around
272 this, we define ADJUST_REG_ALLOC_ORDER to redefine
273 reg_alloc_order for leaf functions such that lowest numbered
274 registers are used first with the exception that the incoming
275 argument registers are not used until after other register choices
276 have been exhausted. */
278 #define REG_ALLOC_ORDER \
279 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
281 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
286 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
288 /* For Xtensa, the only point of this is to prevent GCC from otherwise
289 giving preference to call-used registers. To minimize window
290 overflows for the AR registers, we want to give preference to the
291 lower-numbered AR registers. For other register files, which are
292 not windowed, we still prefer call-used registers, if there are any. */
293 extern const char xtensa_leaf_regs
[FIRST_PSEUDO_REGISTER
];
294 #define LEAF_REGISTERS xtensa_leaf_regs
296 /* For Xtensa, no remapping is necessary, but this macro must be
297 defined if LEAF_REGISTERS is defined. */
298 #define LEAF_REG_REMAP(REGNO) (REGNO)
300 /* This must be declared if LEAF_REGISTERS is set. */
301 extern int leaf_function
;
303 /* Internal macros to classify a register number. */
305 /* 16 address registers + fake registers */
306 #define GP_REG_FIRST 0
307 #define GP_REG_LAST 17
308 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
310 /* Coprocessor registers */
311 #define BR_REG_FIRST 18
312 #define BR_REG_LAST 18
313 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
315 /* 16 floating-point registers */
316 #define FP_REG_FIRST 19
317 #define FP_REG_LAST 34
318 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
320 /* MAC16 accumulator */
321 #define ACC_REG_FIRST 35
322 #define ACC_REG_LAST 35
323 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
325 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
326 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
327 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
328 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
330 /* Return number of consecutive hard regs needed starting at reg REGNO
331 to hold something of mode MODE. */
332 #define HARD_REGNO_NREGS(REGNO, MODE) \
333 (FP_REG_P (REGNO) ? \
334 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
335 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
337 /* Value is 1 if hard register REGNO can hold a value of machine-mode
339 extern char xtensa_hard_regno_mode_ok
[][FIRST_PSEUDO_REGISTER
];
341 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
342 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
344 /* Value is 1 if it is a good idea to tie two pseudo registers
345 when one has mode MODE1 and one has mode MODE2.
346 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
347 for any hard reg, then this must be 0 for correct output. */
348 #define MODES_TIEABLE_P(MODE1, MODE2) \
349 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
350 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
351 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
352 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
354 /* Register to use for pushing function arguments. */
355 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
357 /* Base register for access to local variables of the function. */
358 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
360 /* The register number of the frame pointer register, which is used to
361 access automatic variables in the stack frame. For Xtensa, this
362 register never appears in the output. It is always eliminated to
363 either the stack pointer or the hard frame pointer. */
364 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
366 /* Base register for access to arguments of the function. */
367 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
369 /* For now we don't try to use the full set of boolean registers. Without
370 software pipelining of FP operations, there's not much to gain and it's
371 a real pain to get them reloaded. */
372 #define FPCC_REGNUM (BR_REG_FIRST + 0)
374 /* It is as good or better to call a constant function address than to
375 call an address kept in a register. */
376 #define NO_FUNCTION_CSE 1
378 /* Xtensa processors have "register windows". GCC does not currently
379 take advantage of the possibility for variable-sized windows; instead,
380 we use a fixed window size of 8. */
382 #define INCOMING_REGNO(OUT) \
383 ((GP_REG_P (OUT) && \
384 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
385 (OUT) - WINDOW_SIZE : (OUT))
387 #define OUTGOING_REGNO(IN) \
389 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
390 (IN) + WINDOW_SIZE : (IN))
393 /* Define the classes of registers for register constraints in the
394 machine description. */
397 NO_REGS
, /* no registers in set */
398 BR_REGS
, /* coprocessor boolean registers */
399 FP_REGS
, /* floating point registers */
400 ACC_REG
, /* MAC16 accumulator */
401 SP_REG
, /* sp register (aka a1) */
402 RL_REGS
, /* preferred reload regs (not sp or fp) */
403 GR_REGS
, /* integer registers except sp */
404 AR_REGS
, /* all integer registers */
405 ALL_REGS
, /* all registers */
406 LIM_REG_CLASSES
/* max value + 1 */
409 #define N_REG_CLASSES (int) LIM_REG_CLASSES
411 #define GENERAL_REGS AR_REGS
413 /* An initializer containing the names of the register classes as C
414 string constants. These names are used in writing some of the
416 #define REG_CLASS_NAMES \
429 /* Contents of the register classes. The Nth integer specifies the
430 contents of class N. The way the integer MASK is interpreted is
431 that register R is in the class if 'MASK & (1 << R)' is 1. */
432 #define REG_CLASS_CONTENTS \
434 { 0x00000000, 0x00000000 }, /* no registers */ \
435 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
436 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
437 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
438 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
439 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
440 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
441 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
442 { 0xffffffff, 0x0000000f } /* all registers */ \
445 #define IRA_COVER_CLASSES \
447 BR_REGS, FP_REGS, ACC_REG, AR_REGS, LIM_REG_CLASSES \
450 /* A C expression whose value is a register class containing hard
451 register REGNO. In general there is more that one such class;
452 choose a class which is "minimal", meaning that no smaller class
453 also contains the register. */
454 extern const enum reg_class xtensa_regno_to_class
[FIRST_PSEUDO_REGISTER
];
456 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
458 /* Use the Xtensa AR register file for base registers.
459 No index registers. */
460 #define BASE_REG_CLASS AR_REGS
461 #define INDEX_REG_CLASS NO_REGS
463 /* The small_register_classes_for_mode_p hook must always return true for
464 Xtrnase, because all of the 16 AR registers may be explicitly used in
465 the RTL, as either incoming or outgoing arguments. */
466 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
468 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
469 xtensa_preferred_reload_class (X, CLASS, 0)
471 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \
472 xtensa_preferred_reload_class (X, CLASS, 1)
474 /* Return the maximum number of consecutive registers
475 needed to represent mode MODE in a register of class CLASS. */
476 #define CLASS_UNITS(mode, size) \
477 ((GET_MODE_SIZE (mode) + (size) - 1) / (size))
479 #define CLASS_MAX_NREGS(CLASS, MODE) \
480 (CLASS_UNITS (MODE, UNITS_PER_WORD))
483 /* Stack layout; function entry, exit and calling. */
485 #define STACK_GROWS_DOWNWARD
487 /* Offset within stack frame to start allocating local variables at. */
488 #define STARTING_FRAME_OFFSET \
489 crtl->outgoing_args_size
491 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
492 they are eliminated to either the stack pointer or hard frame pointer. */
493 #define ELIMINABLE_REGS \
494 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
495 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
496 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
497 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
499 /* Specify the initial difference between the specified pair of registers. */
500 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
502 compute_frame_size (get_frame_size ()); \
505 case FRAME_POINTER_REGNUM: \
508 case ARG_POINTER_REGNUM: \
509 (OFFSET) = xtensa_current_frame_size; \
512 gcc_unreachable (); \
516 /* If defined, the maximum amount of space required for outgoing
517 arguments will be computed and placed into the variable
518 'crtl->outgoing_args_size'. No space will be pushed
519 onto the stack for each call; instead, the function prologue
520 should increase the stack frame size by this amount. */
521 #define ACCUMULATE_OUTGOING_ARGS 1
523 /* Offset from the argument pointer register to the first argument's
524 address. On some machines it may depend on the data type of the
525 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
526 location above the first argument's address. */
527 #define FIRST_PARM_OFFSET(FNDECL) 0
529 /* Align stack frames on 128 bits for Xtensa. This is necessary for
530 128-bit datatypes defined in TIE (e.g., for Vectra). */
531 #define STACK_BOUNDARY 128
533 /* Use a fixed register window size of 8. */
534 #define WINDOW_SIZE 8
536 /* Symbolic macros for the registers used to return integer, floating
537 point, and values of coprocessor and user-defined modes. */
538 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
539 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
541 /* Symbolic macros for the first/last argument registers. */
542 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
543 #define GP_ARG_LAST (GP_REG_FIRST + 7)
544 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
545 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
547 #define MAX_ARGS_IN_REGISTERS 6
549 /* Don't worry about compatibility with PCC. */
550 #define DEFAULT_PCC_STRUCT_RETURN 0
552 /* Define how to find the value returned by a library function
553 assuming the value has mode MODE. Because we have defined
554 TARGET_PROMOTE_FUNCTION_MODE to promote everything, we have to
555 perform the same promotions as PROMOTE_MODE. */
556 #define XTENSA_LIBCALL_VALUE(MODE, OUTGOINGP) \
557 gen_rtx_REG ((GET_MODE_CLASS (MODE) == MODE_INT \
558 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
560 OUTGOINGP ? GP_OUTGOING_RETURN : GP_RETURN)
562 #define LIBCALL_VALUE(MODE) \
563 XTENSA_LIBCALL_VALUE ((MODE), 0)
565 #define LIBCALL_OUTGOING_VALUE(MODE) \
566 XTENSA_LIBCALL_VALUE ((MODE), 1)
568 /* A C expression that is nonzero if REGNO is the number of a hard
569 register in which the values of called function may come back. A
570 register whose use for returning values is limited to serving as
571 the second of a pair (for a value of type 'double', say) need not
572 be recognized by this macro. If the machine has register windows,
573 so that the caller and the called function use different registers
574 for the return value, this macro should recognize only the caller's
576 #define FUNCTION_VALUE_REGNO_P(N) \
579 /* A C expression that is nonzero if REGNO is the number of a hard
580 register in which function arguments are sometimes passed. This
581 does *not* include implicit arguments such as the static chain and
582 the structure-value address. On many machines, no registers can be
583 used for this purpose since all function arguments are pushed on
585 #define FUNCTION_ARG_REGNO_P(N) \
586 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
588 /* Record the number of argument words seen so far, along with a flag to
589 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG
590 is used for both incoming and outgoing args, so a separate flag is
592 typedef struct xtensa_args
598 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
599 init_cumulative_args (&CUM, 0)
601 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
602 init_cumulative_args (&CUM, 1)
604 #define FUNCTION_ARG_BOUNDARY function_arg_boundary
606 /* Profiling Xtensa code is typically done with the built-in profiling
607 feature of Tensilica's instruction set simulator, which does not
608 require any compiler support. Profiling code on a real (i.e.,
609 non-simulated) Xtensa processor is currently only supported by
610 GNU/Linux with glibc. The glibc version of _mcount doesn't require
611 counter variables. The _mcount function needs the current PC and
612 the current return address to identify an arc in the call graph.
613 Pass the current return address as the first argument; the current
614 PC is available as a0 in _mcount's register window. Both of these
615 values contain window size information in the two most significant
616 bits; we assume that _mcount will mask off those bits. The call to
617 _mcount uses a window size of 8 to make sure that it doesn't clobber
618 any incoming argument values. */
620 #define NO_PROFILE_COUNTERS 1
622 #define FUNCTION_PROFILER(FILE, LABELNO) \
624 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
627 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
628 fprintf (FILE, "\tcallx8\ta8\n"); \
631 fprintf (FILE, "\tcall8\t_mcount\n"); \
634 /* Stack pointer value doesn't matter at exit. */
635 #define EXIT_IGNORE_STACK 1
637 /* Size in bytes of the trampoline, as an integer. Make sure this is
638 a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */
639 #define TRAMPOLINE_SIZE (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? 60 : 52)
641 /* Alignment required for trampolines, in bits. */
642 #define TRAMPOLINE_ALIGNMENT 32
644 /* If defined, a C expression that produces the machine-specific code
645 to setup the stack so that arbitrary frames can be accessed.
647 On Xtensa, a stack back-trace must always begin from the stack pointer,
648 so that the register overflow save area can be located. However, the
649 stack-walking code in GCC always begins from the hard_frame_pointer
650 register, not the stack pointer. The frame pointer is usually equal
651 to the stack pointer, but the __builtin_return_address and
652 __builtin_frame_address functions will not work if count > 0 and
653 they are called from a routine that uses alloca. These functions
654 are not guaranteed to work at all if count > 0 so maybe that is OK.
656 A nicer solution would be to allow the architecture-specific files to
657 specify whether to start from the stack pointer or frame pointer. That
658 would also allow us to skip the machine->accesses_prev_frame stuff that
659 we currently need to ensure that there is a frame pointer when these
660 builtin functions are used. */
662 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
664 /* A C expression whose value is RTL representing the address in a
665 stack frame where the pointer to the caller's frame is stored.
666 Assume that FRAMEADDR is an RTL expression for the address of the
669 For Xtensa, there is no easy way to get the frame pointer if it is
670 not equivalent to the stack pointer. Moreover, the result of this
671 macro is used for continuing to walk back up the stack, so it must
672 return the stack pointer address. Thus, there is some inconsistency
673 here in that __builtin_frame_address will return the frame pointer
674 when count == 0 and the stack pointer when count > 0. */
676 #define DYNAMIC_CHAIN_ADDRESS(frame) \
677 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
679 /* Define this if the return address of a particular stack frame is
680 accessed from the frame pointer of the previous stack frame. */
681 #define RETURN_ADDR_IN_PREVIOUS_FRAME
683 /* A C expression whose value is RTL representing the value of the
684 return address for the frame COUNT steps up from the current
685 frame, after the prologue. */
686 #define RETURN_ADDR_RTX xtensa_return_addr
688 /* Addressing modes, and classification of registers for them. */
690 /* C expressions which are nonzero if register number NUM is suitable
691 for use as a base or index register in operand addresses. */
693 #define REGNO_OK_FOR_INDEX_P(NUM) 0
694 #define REGNO_OK_FOR_BASE_P(NUM) \
695 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
697 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
698 valid for use as a base or index register. */
701 #define REG_OK_STRICT_FLAG 1
703 #define REG_OK_STRICT_FLAG 0
706 #define BASE_REG_P(X, STRICT) \
707 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
708 || REGNO_OK_FOR_BASE_P (REGNO (X)))
710 #define REG_OK_FOR_INDEX_P(X) 0
711 #define REG_OK_FOR_BASE_P(X) BASE_REG_P (X, REG_OK_STRICT_FLAG)
713 /* Maximum number of registers that can appear in a valid memory address. */
714 #define MAX_REGS_PER_ADDRESS 1
716 /* A C expression that is 1 if the RTX X is a constant which is a
717 valid address. This is defined to be the same as 'CONSTANT_P (X)',
718 but rejecting CONST_DOUBLE. */
719 #define CONSTANT_ADDRESS_P(X) \
720 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
721 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
722 || (GET_CODE (X) == CONST)))
724 /* Nonzero if the constant value X is a legitimate general operand.
725 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
726 #define LEGITIMATE_CONSTANT_P(X) (! xtensa_tls_referenced_p (X))
728 /* A C expression that is nonzero if X is a legitimate immediate
729 operand on the target machine when generating position independent
731 #define LEGITIMATE_PIC_OPERAND_P(X) \
732 ((GET_CODE (X) != SYMBOL_REF \
733 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
734 && GET_CODE (X) != LABEL_REF \
735 && GET_CODE (X) != CONST)
737 /* Treat constant-pool references as "mode dependent" since they can
738 only be accessed with SImode loads. This works around a bug in the
739 combiner where a constant pool reference is temporarily converted
740 to an HImode load, which is then assumed to zero-extend based on
741 our definition of LOAD_EXTEND_OP. This is wrong because the high
742 bits of a 16-bit value in the constant pool are now sign-extended
745 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
747 if (constantpool_address_p (ADDR)) \
751 /* Specify the machine mode that this machine uses
752 for the index in the tablejump instruction. */
753 #define CASE_VECTOR_MODE (SImode)
755 /* Define this as 1 if 'char' should by default be signed; else as 0. */
756 #define DEFAULT_SIGNED_CHAR 0
758 /* Max number of bytes we can move from memory to memory
759 in one reasonably fast instruction. */
761 #define MAX_MOVE_MAX 4
763 /* Prefer word-sized loads. */
764 #define SLOW_BYTE_ACCESS 1
766 /* Shift instructions ignore all but the low-order few bits. */
767 #define SHIFT_COUNT_TRUNCATED 1
769 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
770 is done just by pretending it is already truncated. */
771 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
773 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
774 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
776 /* Specify the machine mode that pointers have.
777 After generation of rtl, the compiler makes no further distinction
778 between pointers and any other objects of this machine mode. */
781 /* A function address in a call instruction is a word address (for
782 indexing purposes) so give the MEM rtx a words's mode. */
783 #define FUNCTION_MODE SImode
785 /* A C expression for the cost of moving data from a register in
786 class FROM to one in class TO. The classes are expressed using
787 the enumeration values such as 'GENERAL_REGS'. A value of 2 is
788 the default; other values are interpreted relative to that. */
789 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
790 (((FROM) == (TO) && (FROM) != BR_REGS && (TO) != BR_REGS) \
792 : (reg_class_subset_p ((FROM), AR_REGS) \
793 && reg_class_subset_p ((TO), AR_REGS) \
795 : (reg_class_subset_p ((FROM), AR_REGS) \
798 : ((FROM) == ACC_REG \
799 && reg_class_subset_p ((TO), AR_REGS) \
803 #define MEMORY_MOVE_COST(MODE, CLASS, IN) 4
805 #define BRANCH_COST(speed_p, predictable_p) 3
807 /* How to refer to registers in assembler output.
808 This sequence is indexed by compiler's hard-register-number (see above). */
809 #define REGISTER_NAMES \
811 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
812 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
813 "fp", "argp", "b0", \
814 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
815 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
819 /* If defined, a C initializer for an array of structures containing a
820 name and a register number. This macro defines additional names
821 for hard registers, thus allowing the 'asm' option in declarations
822 to refer to registers using alternate names. */
823 #define ADDITIONAL_REGISTER_NAMES \
825 { "a1", 1 + GP_REG_FIRST } \
828 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
829 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
831 /* Recognize machine-specific patterns that may appear within
832 constants. Used for PIC-specific UNSPECs. */
833 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \
835 if (xtensa_output_addr_const_extra (STREAM, X) == FALSE) \
839 /* Globalizing directive for a label. */
840 #define GLOBAL_ASM_OP "\t.global\t"
842 /* Declare an uninitialized external linkage data object. */
843 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
844 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
846 /* This is how to output an element of a case-vector that is absolute. */
847 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
848 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
849 LOCAL_LABEL_PREFIX, VALUE)
851 /* This is how to output an element of a case-vector that is relative.
852 This is used for pc-relative code. */
853 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
855 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
856 LOCAL_LABEL_PREFIX, (VALUE), \
857 LOCAL_LABEL_PREFIX, (REL)); \
860 /* This is how to output an assembler line that says to advance the
861 location counter to a multiple of 2**LOG bytes. */
862 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
865 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
868 /* Indicate that jump tables go in the text section. This is
869 necessary when compiling PIC code. */
870 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
873 /* Define the strings to put out for each section in the object file. */
874 #define TEXT_SECTION_ASM_OP "\t.text"
875 #define DATA_SECTION_ASM_OP "\t.data"
876 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
879 /* Define output to appear before the constant pool. */
880 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
884 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
885 switch_to_section (function_section (FUNDECL)); \
886 fprintf (FILE, "\t.literal_position\n"); \
891 /* A C statement (with or without semicolon) to output a constant in
892 the constant pool, if it needs special treatment. */
893 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
895 xtensa_output_literal (FILE, X, MODE, LABELNO); \
899 /* How to start an assembler comment. */
900 #define ASM_COMMENT_START "#"
902 /* Exception handling. Xtensa uses much of the standard DWARF2 unwinding
903 machinery, but the variable size register window save areas are too
904 complicated to efficiently describe with CFI entries. The CFA must
905 still be specified in DWARF so that DW_AT_frame_base is set correctly
907 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0)
908 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0)
909 #define DWARF_FRAME_REGISTERS 16
910 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM)
911 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
913 ? (((GLOBAL) ? DW_EH_PE_indirect : 0) \
914 | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
917 /* Emit a PC-relative relocation. */
918 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
920 fputs (integer_asm_op (SIZE, FALSE), FILE); \
921 assemble_name (FILE, LABEL); \
922 fputs ("@pcrel", FILE); \
925 /* Xtensa constant pool breaks the devices in crtstuff.c to control
926 section in where code resides. We have to write it as asm code. Use
927 a MOVI and let the assembler relax it -- for the .init and .fini
928 sections, the assembler knows to put the literal in the right
930 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
932 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
934 TEXT_SECTION_ASM_OP);