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1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler.
2 Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
3 2012 Free Software Foundation, Inc.
4 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
11 version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 /* Get Xtensa configuration settings */
23 #include "xtensa-config.h"
24
25 /* External variables defined in xtensa.c. */
26
27 extern unsigned xtensa_current_frame_size;
28
29 /* Macros used in the machine description to select various Xtensa
30 configuration options. */
31 #ifndef XCHAL_HAVE_MUL32_HIGH
32 #define XCHAL_HAVE_MUL32_HIGH 0
33 #endif
34 #ifndef XCHAL_HAVE_RELEASE_SYNC
35 #define XCHAL_HAVE_RELEASE_SYNC 0
36 #endif
37 #ifndef XCHAL_HAVE_S32C1I
38 #define XCHAL_HAVE_S32C1I 0
39 #endif
40 #ifndef XCHAL_HAVE_THREADPTR
41 #define XCHAL_HAVE_THREADPTR 0
42 #endif
43 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE
44 #define TARGET_DENSITY XCHAL_HAVE_DENSITY
45 #define TARGET_MAC16 XCHAL_HAVE_MAC16
46 #define TARGET_MUL16 XCHAL_HAVE_MUL16
47 #define TARGET_MUL32 XCHAL_HAVE_MUL32
48 #define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH
49 #define TARGET_DIV32 XCHAL_HAVE_DIV32
50 #define TARGET_NSA XCHAL_HAVE_NSA
51 #define TARGET_MINMAX XCHAL_HAVE_MINMAX
52 #define TARGET_SEXT XCHAL_HAVE_SEXT
53 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS
54 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
55 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV
56 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP
57 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT
58 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT
59 #define TARGET_ABS XCHAL_HAVE_ABS
60 #define TARGET_ADDX XCHAL_HAVE_ADDX
61 #define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC
62 #define TARGET_S32C1I XCHAL_HAVE_S32C1I
63 #define TARGET_ABSOLUTE_LITERALS XSHAL_USE_ABSOLUTE_LITERALS
64 #define TARGET_THREADPTR XCHAL_HAVE_THREADPTR
65
66 #define TARGET_DEFAULT \
67 ((XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \
68 MASK_SERIALIZE_VOLATILE)
69
70 #ifndef HAVE_AS_TLS
71 #define HAVE_AS_TLS 0
72 #endif
73
74 \f
75 /* Target CPU builtins. */
76 #define TARGET_CPU_CPP_BUILTINS() \
77 do { \
78 builtin_assert ("cpu=xtensa"); \
79 builtin_assert ("machine=xtensa"); \
80 builtin_define ("__xtensa__"); \
81 builtin_define ("__XTENSA__"); \
82 builtin_define ("__XTENSA_WINDOWED_ABI__"); \
83 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \
84 if (!TARGET_HARD_FLOAT) \
85 builtin_define ("__XTENSA_SOFT_FLOAT__"); \
86 } while (0)
87
88 #define CPP_SPEC " %(subtarget_cpp_spec) "
89
90 #ifndef SUBTARGET_CPP_SPEC
91 #define SUBTARGET_CPP_SPEC ""
92 #endif
93
94 #define EXTRA_SPECS \
95 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC },
96
97 /* Target machine storage layout */
98
99 /* Define this if most significant bit is lowest numbered
100 in instructions that operate on numbered bit-fields. */
101 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
102
103 /* Define this if most significant byte of a word is the lowest numbered. */
104 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
105
106 /* Define this if most significant word of a multiword number is the lowest. */
107 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
108
109 #define MAX_BITS_PER_WORD 32
110
111 /* Width of a word, in units (bytes). */
112 #define UNITS_PER_WORD 4
113 #define MIN_UNITS_PER_WORD 4
114
115 /* Width of a floating point register. */
116 #define UNITS_PER_FPREG 4
117
118 /* Size in bits of various types on the target machine. */
119 #define INT_TYPE_SIZE 32
120 #define SHORT_TYPE_SIZE 16
121 #define LONG_TYPE_SIZE 32
122 #define LONG_LONG_TYPE_SIZE 64
123 #define FLOAT_TYPE_SIZE 32
124 #define DOUBLE_TYPE_SIZE 64
125 #define LONG_DOUBLE_TYPE_SIZE 64
126
127 /* Allocation boundary (in *bits*) for storing pointers in memory. */
128 #define POINTER_BOUNDARY 32
129
130 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
131 #define PARM_BOUNDARY 32
132
133 /* Allocation boundary (in *bits*) for the code of a function. */
134 #define FUNCTION_BOUNDARY 32
135
136 /* Alignment of field after 'int : 0' in a structure. */
137 #define EMPTY_FIELD_BOUNDARY 32
138
139 /* Every structure's size must be a multiple of this. */
140 #define STRUCTURE_SIZE_BOUNDARY 8
141
142 /* There is no point aligning anything to a rounder boundary than this. */
143 #define BIGGEST_ALIGNMENT 128
144
145 /* Set this nonzero if move instructions will actually fail to work
146 when given unaligned data. */
147 #define STRICT_ALIGNMENT 1
148
149 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP
150 for QImode, because there is no 8-bit load from memory with sign
151 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit
152 loads both with and without sign extension. */
153 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
154 do { \
155 if (GET_MODE_CLASS (MODE) == MODE_INT \
156 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
157 { \
158 if ((MODE) == QImode) \
159 (UNSIGNEDP) = 1; \
160 (MODE) = SImode; \
161 } \
162 } while (0)
163
164 /* Imitate the way many other C compilers handle alignment of
165 bitfields and the structures that contain them. */
166 #define PCC_BITFIELD_TYPE_MATTERS 1
167
168 /* Align string constants and constructors to at least a word boundary.
169 The typical use of this macro is to increase alignment for string
170 constants to be word aligned so that 'strcpy' calls that copy
171 constants can be done inline. */
172 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
173 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
174 && (ALIGN) < BITS_PER_WORD \
175 ? BITS_PER_WORD \
176 : (ALIGN))
177
178 /* Align arrays, unions and records to at least a word boundary.
179 One use of this macro is to increase alignment of medium-size
180 data to make it all fit in fewer cache lines. Another is to
181 cause character arrays to be word-aligned so that 'strcpy' calls
182 that copy constants to character arrays can be done inline. */
183 #undef DATA_ALIGNMENT
184 #define DATA_ALIGNMENT(TYPE, ALIGN) \
185 ((((ALIGN) < BITS_PER_WORD) \
186 && (TREE_CODE (TYPE) == ARRAY_TYPE \
187 || TREE_CODE (TYPE) == UNION_TYPE \
188 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
189
190 /* Operations between registers always perform the operation
191 on the full register even if a narrower mode is specified. */
192 #define WORD_REGISTER_OPERATIONS
193
194 /* Xtensa loads are zero-extended by default. */
195 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
196
197 /* Standard register usage. */
198
199 /* Number of actual hardware registers.
200 The hardware registers are assigned numbers for the compiler
201 from 0 to just below FIRST_PSEUDO_REGISTER.
202 All registers that the compiler knows about must be given numbers,
203 even those that are not normally considered general registers.
204
205 The fake frame pointer and argument pointer will never appear in
206 the generated code, since they will always be eliminated and replaced
207 by either the stack pointer or the hard frame pointer.
208
209 0 - 15 AR[0] - AR[15]
210 16 FRAME_POINTER (fake = initial sp)
211 17 ARG_POINTER (fake = initial sp + framesize)
212 18 BR[0] for floating-point CC
213 19 - 34 FR[0] - FR[15]
214 35 MAC16 accumulator */
215
216 #define FIRST_PSEUDO_REGISTER 36
217
218 /* Return the stabs register number to use for REGNO. */
219 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO)
220
221 /* 1 for registers that have pervasive standard uses
222 and are not available for the register allocator. */
223 #define FIXED_REGISTERS \
224 { \
225 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
226 1, 1, 0, \
227 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
228 0, \
229 }
230
231 /* 1 for registers not available across function calls.
232 These must include the FIXED_REGISTERS and also any
233 registers that can be used without being saved.
234 The latter must include the registers where values are returned
235 and the register where structure-value addresses are passed.
236 Aside from that, you can include as many other registers as you like. */
237 #define CALL_USED_REGISTERS \
238 { \
239 1, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \
240 1, 1, 1, \
241 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
242 1, \
243 }
244
245 /* For non-leaf procedures on Xtensa processors, the allocation order
246 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we
247 want to use the lowest numbered registers first to minimize
248 register window overflows. However, local-alloc is not smart
249 enough to consider conflicts with incoming arguments. If an
250 incoming argument in a2 is live throughout the function and
251 local-alloc decides to use a2, then the incoming argument must
252 either be spilled or copied to another register. To get around
253 this, we define ADJUST_REG_ALLOC_ORDER to redefine
254 reg_alloc_order for leaf functions such that lowest numbered
255 registers are used first with the exception that the incoming
256 argument registers are not used until after other register choices
257 have been exhausted. */
258
259 #define REG_ALLOC_ORDER \
260 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \
261 18, \
262 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \
263 0, 1, 16, 17, \
264 35, \
265 }
266
267 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc ()
268
269 /* For Xtensa, the only point of this is to prevent GCC from otherwise
270 giving preference to call-used registers. To minimize window
271 overflows for the AR registers, we want to give preference to the
272 lower-numbered AR registers. For other register files, which are
273 not windowed, we still prefer call-used registers, if there are any. */
274 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER];
275 #define LEAF_REGISTERS xtensa_leaf_regs
276
277 /* For Xtensa, no remapping is necessary, but this macro must be
278 defined if LEAF_REGISTERS is defined. */
279 #define LEAF_REG_REMAP(REGNO) (REGNO)
280
281 /* This must be declared if LEAF_REGISTERS is set. */
282 extern int leaf_function;
283
284 /* Internal macros to classify a register number. */
285
286 /* 16 address registers + fake registers */
287 #define GP_REG_FIRST 0
288 #define GP_REG_LAST 17
289 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
290
291 /* Coprocessor registers */
292 #define BR_REG_FIRST 18
293 #define BR_REG_LAST 18
294 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1)
295
296 /* 16 floating-point registers */
297 #define FP_REG_FIRST 19
298 #define FP_REG_LAST 34
299 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
300
301 /* MAC16 accumulator */
302 #define ACC_REG_FIRST 35
303 #define ACC_REG_LAST 35
304 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1)
305
306 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
307 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM)
308 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
309 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM)
310
311 /* Return number of consecutive hard regs needed starting at reg REGNO
312 to hold something of mode MODE. */
313 #define HARD_REGNO_NREGS(REGNO, MODE) \
314 (FP_REG_P (REGNO) ? \
315 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \
316 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
317
318 /* Value is 1 if hard register REGNO can hold a value of machine-mode
319 MODE. */
320 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
321
322 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
323 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)]
324
325 /* Value is 1 if it is a good idea to tie two pseudo registers
326 when one has mode MODE1 and one has mode MODE2.
327 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
328 for any hard reg, then this must be 0 for correct output. */
329 #define MODES_TIEABLE_P(MODE1, MODE2) \
330 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
331 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
332 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
333 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
334
335 /* Register to use for pushing function arguments. */
336 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1)
337
338 /* Base register for access to local variables of the function. */
339 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + 7)
340
341 /* The register number of the frame pointer register, which is used to
342 access automatic variables in the stack frame. For Xtensa, this
343 register never appears in the output. It is always eliminated to
344 either the stack pointer or the hard frame pointer. */
345 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16)
346
347 /* Base register for access to arguments of the function. */
348 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17)
349
350 /* For now we don't try to use the full set of boolean registers. Without
351 software pipelining of FP operations, there's not much to gain and it's
352 a real pain to get them reloaded. */
353 #define FPCC_REGNUM (BR_REG_FIRST + 0)
354
355 /* It is as good or better to call a constant function address than to
356 call an address kept in a register. */
357 #define NO_FUNCTION_CSE 1
358
359 /* Xtensa processors have "register windows". GCC does not currently
360 take advantage of the possibility for variable-sized windows; instead,
361 we use a fixed window size of 8. */
362
363 #define INCOMING_REGNO(OUT) \
364 ((GP_REG_P (OUT) && \
365 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \
366 (OUT) - WINDOW_SIZE : (OUT))
367
368 #define OUTGOING_REGNO(IN) \
369 ((GP_REG_P (IN) && \
370 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \
371 (IN) + WINDOW_SIZE : (IN))
372
373
374 /* Define the classes of registers for register constraints in the
375 machine description. */
376 enum reg_class
377 {
378 NO_REGS, /* no registers in set */
379 BR_REGS, /* coprocessor boolean registers */
380 FP_REGS, /* floating point registers */
381 ACC_REG, /* MAC16 accumulator */
382 SP_REG, /* sp register (aka a1) */
383 RL_REGS, /* preferred reload regs (not sp or fp) */
384 GR_REGS, /* integer registers except sp */
385 AR_REGS, /* all integer registers */
386 ALL_REGS, /* all registers */
387 LIM_REG_CLASSES /* max value + 1 */
388 };
389
390 #define N_REG_CLASSES (int) LIM_REG_CLASSES
391
392 #define GENERAL_REGS AR_REGS
393
394 /* An initializer containing the names of the register classes as C
395 string constants. These names are used in writing some of the
396 debugging dumps. */
397 #define REG_CLASS_NAMES \
398 { \
399 "NO_REGS", \
400 "BR_REGS", \
401 "FP_REGS", \
402 "ACC_REG", \
403 "SP_REG", \
404 "RL_REGS", \
405 "GR_REGS", \
406 "AR_REGS", \
407 "ALL_REGS" \
408 }
409
410 /* Contents of the register classes. The Nth integer specifies the
411 contents of class N. The way the integer MASK is interpreted is
412 that register R is in the class if 'MASK & (1 << R)' is 1. */
413 #define REG_CLASS_CONTENTS \
414 { \
415 { 0x00000000, 0x00000000 }, /* no registers */ \
416 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \
417 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \
418 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \
419 { 0x00000002, 0x00000000 }, /* stack pointer register */ \
420 { 0x0000ff7d, 0x00000000 }, /* preferred reload registers */ \
421 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \
422 { 0x0003ffff, 0x00000000 }, /* integer registers */ \
423 { 0xffffffff, 0x0000000f } /* all registers */ \
424 }
425
426 /* A C expression whose value is a register class containing hard
427 register REGNO. In general there is more that one such class;
428 choose a class which is "minimal", meaning that no smaller class
429 also contains the register. */
430 extern const enum reg_class xtensa_regno_to_class[FIRST_PSEUDO_REGISTER];
431
432 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class[ (REGNO) ]
433
434 /* Use the Xtensa AR register file for base registers.
435 No index registers. */
436 #define BASE_REG_CLASS AR_REGS
437 #define INDEX_REG_CLASS NO_REGS
438
439 /* The small_register_classes_for_mode_p hook must always return true for
440 Xtrnase, because all of the 16 AR registers may be explicitly used in
441 the RTL, as either incoming or outgoing arguments. */
442 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true
443
444 /* Stack layout; function entry, exit and calling. */
445
446 #define STACK_GROWS_DOWNWARD
447
448 /* Offset within stack frame to start allocating local variables at. */
449 #define STARTING_FRAME_OFFSET \
450 crtl->outgoing_args_size
451
452 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so
453 they are eliminated to either the stack pointer or hard frame pointer. */
454 #define ELIMINABLE_REGS \
455 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
456 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
457 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
458 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}}
459
460 /* Specify the initial difference between the specified pair of registers. */
461 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
462 do { \
463 compute_frame_size (get_frame_size ()); \
464 switch (FROM) \
465 { \
466 case FRAME_POINTER_REGNUM: \
467 (OFFSET) = 0; \
468 break; \
469 case ARG_POINTER_REGNUM: \
470 (OFFSET) = xtensa_current_frame_size; \
471 break; \
472 default: \
473 gcc_unreachable (); \
474 } \
475 } while (0)
476
477 /* If defined, the maximum amount of space required for outgoing
478 arguments will be computed and placed into the variable
479 'crtl->outgoing_args_size'. No space will be pushed
480 onto the stack for each call; instead, the function prologue
481 should increase the stack frame size by this amount. */
482 #define ACCUMULATE_OUTGOING_ARGS 1
483
484 /* Offset from the argument pointer register to the first argument's
485 address. On some machines it may depend on the data type of the
486 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the
487 location above the first argument's address. */
488 #define FIRST_PARM_OFFSET(FNDECL) 0
489
490 /* Align stack frames on 128 bits for Xtensa. This is necessary for
491 128-bit datatypes defined in TIE (e.g., for Vectra). */
492 #define STACK_BOUNDARY 128
493
494 /* Use a fixed register window size of 8. */
495 #define WINDOW_SIZE 8
496
497 /* Symbolic macros for the registers used to return integer, floating
498 point, and values of coprocessor and user-defined modes. */
499 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE)
500 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2)
501
502 /* Symbolic macros for the first/last argument registers. */
503 #define GP_ARG_FIRST (GP_REG_FIRST + 2)
504 #define GP_ARG_LAST (GP_REG_FIRST + 7)
505 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE)
506 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE)
507
508 #define MAX_ARGS_IN_REGISTERS 6
509
510 /* Don't worry about compatibility with PCC. */
511 #define DEFAULT_PCC_STRUCT_RETURN 0
512
513 /* A C expression that is nonzero if REGNO is the number of a hard
514 register in which function arguments are sometimes passed. This
515 does *not* include implicit arguments such as the static chain and
516 the structure-value address. On many machines, no registers can be
517 used for this purpose since all function arguments are pushed on
518 the stack. */
519 #define FUNCTION_ARG_REGNO_P(N) \
520 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST)
521
522 /* Record the number of argument words seen so far, along with a flag to
523 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG
524 is used for both incoming and outgoing args, so a separate flag is
525 needed. */
526 typedef struct xtensa_args
527 {
528 int arg_words;
529 int incoming;
530 } CUMULATIVE_ARGS;
531
532 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
533 init_cumulative_args (&CUM, 0)
534
535 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \
536 init_cumulative_args (&CUM, 1)
537
538 /* Profiling Xtensa code is typically done with the built-in profiling
539 feature of Tensilica's instruction set simulator, which does not
540 require any compiler support. Profiling code on a real (i.e.,
541 non-simulated) Xtensa processor is currently only supported by
542 GNU/Linux with glibc. The glibc version of _mcount doesn't require
543 counter variables. The _mcount function needs the current PC and
544 the current return address to identify an arc in the call graph.
545 Pass the current return address as the first argument; the current
546 PC is available as a0 in _mcount's register window. Both of these
547 values contain window size information in the two most significant
548 bits; we assume that _mcount will mask off those bits. The call to
549 _mcount uses a window size of 8 to make sure that it doesn't clobber
550 any incoming argument values. */
551
552 #define NO_PROFILE_COUNTERS 1
553
554 #define FUNCTION_PROFILER(FILE, LABELNO) \
555 do { \
556 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \
557 if (flag_pic) \
558 { \
559 fprintf (FILE, "\tmovi\ta8, _mcount@PLT\n"); \
560 fprintf (FILE, "\tcallx8\ta8\n"); \
561 } \
562 else \
563 fprintf (FILE, "\tcall8\t_mcount\n"); \
564 } while (0)
565
566 /* Stack pointer value doesn't matter at exit. */
567 #define EXIT_IGNORE_STACK 1
568
569 /* Size in bytes of the trampoline, as an integer. Make sure this is
570 a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */
571 #define TRAMPOLINE_SIZE (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? 60 : 52)
572
573 /* Alignment required for trampolines, in bits. */
574 #define TRAMPOLINE_ALIGNMENT 32
575
576 /* If defined, a C expression that produces the machine-specific code
577 to setup the stack so that arbitrary frames can be accessed.
578
579 On Xtensa, a stack back-trace must always begin from the stack pointer,
580 so that the register overflow save area can be located. However, the
581 stack-walking code in GCC always begins from the hard_frame_pointer
582 register, not the stack pointer. The frame pointer is usually equal
583 to the stack pointer, but the __builtin_return_address and
584 __builtin_frame_address functions will not work if count > 0 and
585 they are called from a routine that uses alloca. These functions
586 are not guaranteed to work at all if count > 0 so maybe that is OK.
587
588 A nicer solution would be to allow the architecture-specific files to
589 specify whether to start from the stack pointer or frame pointer. That
590 would also allow us to skip the machine->accesses_prev_frame stuff that
591 we currently need to ensure that there is a frame pointer when these
592 builtin functions are used. */
593
594 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses
595
596 /* A C expression whose value is RTL representing the address in a
597 stack frame where the pointer to the caller's frame is stored.
598 Assume that FRAMEADDR is an RTL expression for the address of the
599 stack frame itself.
600
601 For Xtensa, there is no easy way to get the frame pointer if it is
602 not equivalent to the stack pointer. Moreover, the result of this
603 macro is used for continuing to walk back up the stack, so it must
604 return the stack pointer address. Thus, there is some inconsistency
605 here in that __builtin_frame_address will return the frame pointer
606 when count == 0 and the stack pointer when count > 0. */
607
608 #define DYNAMIC_CHAIN_ADDRESS(frame) \
609 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD))
610
611 /* Define this if the return address of a particular stack frame is
612 accessed from the frame pointer of the previous stack frame. */
613 #define RETURN_ADDR_IN_PREVIOUS_FRAME
614
615 /* A C expression whose value is RTL representing the value of the
616 return address for the frame COUNT steps up from the current
617 frame, after the prologue. */
618 #define RETURN_ADDR_RTX xtensa_return_addr
619
620 /* Addressing modes, and classification of registers for them. */
621
622 /* C expressions which are nonzero if register number NUM is suitable
623 for use as a base or index register in operand addresses. */
624
625 #define REGNO_OK_FOR_INDEX_P(NUM) 0
626 #define REGNO_OK_FOR_BASE_P(NUM) \
627 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM]))
628
629 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is
630 valid for use as a base or index register. */
631
632 #ifdef REG_OK_STRICT
633 #define REG_OK_STRICT_FLAG 1
634 #else
635 #define REG_OK_STRICT_FLAG 0
636 #endif
637
638 #define BASE_REG_P(X, STRICT) \
639 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \
640 || REGNO_OK_FOR_BASE_P (REGNO (X)))
641
642 #define REG_OK_FOR_INDEX_P(X) 0
643 #define REG_OK_FOR_BASE_P(X) BASE_REG_P (X, REG_OK_STRICT_FLAG)
644
645 /* Maximum number of registers that can appear in a valid memory address. */
646 #define MAX_REGS_PER_ADDRESS 1
647
648 /* A C expression that is 1 if the RTX X is a constant which is a
649 valid address. This is defined to be the same as 'CONSTANT_P (X)',
650 but rejecting CONST_DOUBLE. */
651 #define CONSTANT_ADDRESS_P(X) \
652 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
653 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
654 || (GET_CODE (X) == CONST)))
655
656 /* A C expression that is nonzero if X is a legitimate immediate
657 operand on the target machine when generating position independent
658 code. */
659 #define LEGITIMATE_PIC_OPERAND_P(X) \
660 ((GET_CODE (X) != SYMBOL_REF \
661 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
662 && GET_CODE (X) != LABEL_REF \
663 && GET_CODE (X) != CONST)
664
665 /* Specify the machine mode that this machine uses
666 for the index in the tablejump instruction. */
667 #define CASE_VECTOR_MODE (SImode)
668
669 /* Define this as 1 if 'char' should by default be signed; else as 0. */
670 #define DEFAULT_SIGNED_CHAR 0
671
672 /* Max number of bytes we can move from memory to memory
673 in one reasonably fast instruction. */
674 #define MOVE_MAX 4
675 #define MAX_MOVE_MAX 4
676
677 /* Prefer word-sized loads. */
678 #define SLOW_BYTE_ACCESS 1
679
680 /* Shift instructions ignore all but the low-order few bits. */
681 #define SHIFT_COUNT_TRUNCATED 1
682
683 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
684 is done just by pretending it is already truncated. */
685 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
686
687 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
688 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1)
689
690 /* Specify the machine mode that pointers have.
691 After generation of rtl, the compiler makes no further distinction
692 between pointers and any other objects of this machine mode. */
693 #define Pmode SImode
694
695 /* A function address in a call instruction is a word address (for
696 indexing purposes) so give the MEM rtx a words's mode. */
697 #define FUNCTION_MODE SImode
698
699 #define BRANCH_COST(speed_p, predictable_p) 3
700
701 /* How to refer to registers in assembler output.
702 This sequence is indexed by compiler's hard-register-number (see above). */
703 #define REGISTER_NAMES \
704 { \
705 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \
706 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \
707 "fp", "argp", "b0", \
708 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
709 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \
710 "acc" \
711 }
712
713 /* If defined, a C initializer for an array of structures containing a
714 name and a register number. This macro defines additional names
715 for hard registers, thus allowing the 'asm' option in declarations
716 to refer to registers using alternate names. */
717 #define ADDITIONAL_REGISTER_NAMES \
718 { \
719 { "a1", 1 + GP_REG_FIRST } \
720 }
721
722 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
723 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
724
725 /* Globalizing directive for a label. */
726 #define GLOBAL_ASM_OP "\t.global\t"
727
728 /* Declare an uninitialized external linkage data object. */
729 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
730 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN)
731
732 /* This is how to output an element of a case-vector that is absolute. */
733 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
734 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \
735 LOCAL_LABEL_PREFIX, VALUE)
736
737 /* This is how to output an element of a case-vector that is relative.
738 This is used for pc-relative code. */
739 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
740 do { \
741 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \
742 LOCAL_LABEL_PREFIX, (VALUE), \
743 LOCAL_LABEL_PREFIX, (REL)); \
744 } while (0)
745
746 /* This is how to output an assembler line that says to advance the
747 location counter to a multiple of 2**LOG bytes. */
748 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \
749 do { \
750 if ((LOG) != 0) \
751 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \
752 } while (0)
753
754 /* Indicate that jump tables go in the text section. This is
755 necessary when compiling PIC code. */
756 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
757
758
759 /* Define the strings to put out for each section in the object file. */
760 #define TEXT_SECTION_ASM_OP "\t.text"
761 #define DATA_SECTION_ASM_OP "\t.data"
762 #define BSS_SECTION_ASM_OP "\t.section\t.bss"
763
764
765 /* Define output to appear before the constant pool. */
766 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \
767 do { \
768 if ((SIZE) > 0) \
769 { \
770 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \
771 switch_to_section (function_section (FUNDECL)); \
772 fprintf (FILE, "\t.literal_position\n"); \
773 } \
774 } while (0)
775
776
777 /* A C statement (with or without semicolon) to output a constant in
778 the constant pool, if it needs special treatment. */
779 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \
780 do { \
781 xtensa_output_literal (FILE, X, MODE, LABELNO); \
782 goto JUMPTO; \
783 } while (0)
784
785 /* How to start an assembler comment. */
786 #define ASM_COMMENT_START "#"
787
788 /* Exception handling. Xtensa uses much of the standard DWARF2 unwinding
789 machinery, but the variable size register window save areas are too
790 complicated to efficiently describe with CFI entries. The CFA must
791 still be specified in DWARF so that DW_AT_frame_base is set correctly
792 for debugging. */
793 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0)
794 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0)
795 #define DWARF_FRAME_REGISTERS 16
796 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM)
797 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
798 (flag_pic \
799 ? (((GLOBAL) ? DW_EH_PE_indirect : 0) \
800 | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
801 : DW_EH_PE_absptr)
802
803 /* Emit a PC-relative relocation. */
804 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \
805 do { \
806 fputs (integer_asm_op (SIZE, FALSE), FILE); \
807 assemble_name (FILE, LABEL); \
808 fputs ("@pcrel", FILE); \
809 } while (0)
810
811 /* Xtensa constant pool breaks the devices in crtstuff.c to control
812 section in where code resides. We have to write it as asm code. Use
813 a MOVI and let the assembler relax it -- for the .init and .fini
814 sections, the assembler knows to put the literal in the right
815 place. */
816 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
817 asm (SECTION_OP "\n\
818 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\
819 callx8\ta8\n" \
820 TEXT_SECTION_ASM_OP);