gcc/config/xtensa/xtensa.md

   1 ;; GCC machine description for Tensilica's Xtensa architecture.
   2 ;; Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007
   3 ;; Free Software Foundation, Inc.
   4 ;; Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica.
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify it
   9 ;; under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12
  13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  16 ;; License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22
  23 (define_constants [
  24   (A0_REG               0)
  25   (A1_REG               1)
  26   (A7_REG               7)
  27   (A8_REG               8)
  28
  29   (UNSPEC_NOP           2)
  30   (UNSPEC_PLT           3)
  31   (UNSPEC_RET_ADDR      4)
  32
  33   (UNSPECV_SET_FP       1)
  34   (UNSPECV_ENTRY        2)
  35   (UNSPECV_MEMW         3)
  36   (UNSPECV_S32RI        4)
  37   (UNSPECV_S32C1I       5)
  38 ])
  39
  40 ;; This code macro allows signed and unsigned widening multiplications
  41 ;; to use the same template.
  42 (define_code_macro any_extend [sign_extend zero_extend])
  43
  44 ;; <u> expands to an empty string when doing a signed operation and
  45 ;; "u" when doing an unsigned operation.
  46 (define_code_attr u [(sign_extend "") (zero_extend "u")])
  47
  48 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
  49 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
  50
  51 ;; This code macro allows four integer min/max operations to be
  52 ;; generated from one template.
  53 (define_code_macro any_minmax [smin umin smax umax])
  54
  55 ;; <minmax> expands to the opcode name for any_minmax operations.
  56 (define_code_attr minmax [(smin "min") (umin "minu")
  57                           (smax "max") (umax "maxu")])
  58
  59 ;; This code macro allows all branch instructions to be generated from
  60 ;; a single define_expand template.
  61 (define_code_macro any_cond [eq ne gt ge lt le gtu geu ltu leu])
  62
  63 ;; This code macro is for setting a register from a comparison.
  64 (define_code_macro any_scc [eq ne gt ge lt le])
  65
  66 ;; This code macro is for floating-point comparisons.
  67 (define_code_macro any_scc_sf [eq lt le])
  68
  69 ;; These macros allow to combine most atomic operations.
  70 (define_code_macro ATOMIC [and ior xor plus minus mult])
  71 (define_code_attr atomic [(and "and") (ior "ior") (xor "xor")
  72                           (plus "add") (minus "sub") (mult "nand")])
  73
  74 ;; These mode macros allow the HI and QI patterns to be defined from
  75 ;; the same template.
  76 (define_mode_macro HQI [HI QI])
  77
  78 \f
  79 ;; Attributes.
  80
  81 (define_attr "type"
  82   "unknown,jump,call,load,store,move,arith,multi,nop,farith,fmadd,fdiv,fsqrt,fconv,fload,fstore,mul16,mul32,div32,mac16,rsr,wsr"
  83   (const_string "unknown"))
  84
  85 (define_attr "mode"
  86   "unknown,none,QI,HI,SI,DI,SF,DF,BL"
  87   (const_string "unknown"))
  88
  89 (define_attr "length" "" (const_int 1))
  90
  91 ;; Describe a user's asm statement.
  92 (define_asm_attributes
  93   [(set_attr "type" "multi")])
  94
  95 \f
  96 ;; Pipeline model.
  97
  98 ;; The Xtensa basically has simple 5-stage RISC pipeline.
  99 ;; Most instructions complete in 1 cycle, and it is OK to assume that
 100 ;; everything is fully pipelined.  The exceptions have special insn
 101 ;; reservations in the pipeline description below.  The Xtensa can
 102 ;; issue one instruction per cycle, so defining CPU units is unnecessary.
 103
 104 (define_insn_reservation "xtensa_any_insn" 1
 105                          (eq_attr "type" "!load,fload,rsr,mul16,mul32,fmadd,fconv")
 106                          "nothing")
 107
 108 (define_insn_reservation "xtensa_memory" 2
 109                          (eq_attr "type" "load,fload")
 110                          "nothing")
 111
 112 (define_insn_reservation "xtensa_sreg" 2
 113                          (eq_attr "type" "rsr")
 114                          "nothing")
 115
 116 (define_insn_reservation "xtensa_mul16" 2
 117                          (eq_attr "type" "mul16")
 118                          "nothing")
 119
 120 (define_insn_reservation "xtensa_mul32" 2
 121                          (eq_attr "type" "mul32")
 122                          "nothing")
 123
 124 (define_insn_reservation "xtensa_fmadd" 4
 125                          (eq_attr "type" "fmadd")
 126                          "nothing")
 127
 128 (define_insn_reservation "xtensa_fconv" 2
 129                          (eq_attr "type" "fconv")
 130                          "nothing")
 131 \f
 132 ;; Include predicates and constraints.
 133
 134 (include "predicates.md")
 135 (include "constraints.md")
 136
 137 \f
 138 ;; Addition.
 139
 140 (define_insn "addsi3"
 141   [(set (match_operand:SI 0 "register_operand" "=D,D,a,a,a")
 142         (plus:SI (match_operand:SI 1 "register_operand" "%d,d,r,r,r")
 143                  (match_operand:SI 2 "add_operand" "d,O,r,J,N")))]
 144   ""
 145   "@
 146    add.n\t%0, %1, %2
 147    addi.n\t%0, %1, %d2
 148    add\t%0, %1, %2
 149    addi\t%0, %1, %d2
 150    addmi\t%0, %1, %x2"
 151   [(set_attr "type"     "arith,arith,arith,arith,arith")
 152    (set_attr "mode"     "SI")
 153    (set_attr "length"   "2,2,3,3,3")])
 154
 155 (define_insn "*addx"
 156   [(set (match_operand:SI 0 "register_operand" "=a")
 157         (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
 158                           (match_operand:SI 3 "addsubx_operand" "i"))
 159                  (match_operand:SI 2 "register_operand" "r")))]
 160   "TARGET_ADDX"
 161   "addx%3\t%0, %1, %2"
 162   [(set_attr "type"     "arith")
 163    (set_attr "mode"     "SI")
 164    (set_attr "length"   "3")])
 165
 166 (define_insn "addsf3"
 167   [(set (match_operand:SF 0 "register_operand" "=f")
 168         (plus:SF (match_operand:SF 1 "register_operand" "%f")
 169                  (match_operand:SF 2 "register_operand" "f")))]
 170   "TARGET_HARD_FLOAT"
 171   "add.s\t%0, %1, %2"
 172   [(set_attr "type"     "fmadd")
 173    (set_attr "mode"     "SF")
 174    (set_attr "length"   "3")])
 175
 176 \f
 177 ;; Subtraction.
 178
 179 (define_insn "subsi3"
 180   [(set (match_operand:SI 0 "register_operand" "=a")
 181         (minus:SI (match_operand:SI 1 "register_operand" "r")
 182                   (match_operand:SI 2 "register_operand" "r")))]
 183   ""
 184   "sub\t%0, %1, %2"
 185   [(set_attr "type"     "arith")
 186    (set_attr "mode"     "SI")
 187    (set_attr "length"   "3")])
 188
 189 (define_insn "*subx"
 190   [(set (match_operand:SI 0 "register_operand" "=a")
 191         (minus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
 192                            (match_operand:SI 3 "addsubx_operand" "i"))
 193                   (match_operand:SI 2 "register_operand" "r")))]
 194   "TARGET_ADDX"
 195   "subx%3\t%0, %1, %2"
 196   [(set_attr "type"     "arith")
 197    (set_attr "mode"     "SI")
 198    (set_attr "length"   "3")])
 199
 200 (define_insn "subsf3"
 201   [(set (match_operand:SF 0 "register_operand" "=f")
 202         (minus:SF (match_operand:SF 1 "register_operand" "f")
 203                   (match_operand:SF 2 "register_operand" "f")))]
 204   "TARGET_HARD_FLOAT"
 205   "sub.s\t%0, %1, %2"
 206   [(set_attr "type"     "fmadd")
 207    (set_attr "mode"     "SF")
 208    (set_attr "length"   "3")])
 209
 210 \f
 211 ;; Multiplication.
 212
 213 (define_expand "<u>mulsidi3"
 214   [(set (match_operand:DI 0 "register_operand")
 215         (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
 216                  (any_extend:DI (match_operand:SI 2 "register_operand"))))]
 217   "TARGET_MUL32_HIGH"
 218 {
 219   emit_insn (gen_mulsi3 (gen_lowpart (SImode, operands[0]),
 220                          operands[1], operands[2]));
 221   emit_insn (gen_<u>mulsi3_highpart (gen_highpart (SImode, operands[0]),
 222                                      operands[1], operands[2]));
 223   DONE;
 224 })
 225
 226 (define_insn "<u>mulsi3_highpart"
 227   [(set (match_operand:SI 0 "register_operand" "=a")
 228         (truncate:SI
 229          (lshiftrt:DI
 230           (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "%r"))
 231                    (any_extend:DI (match_operand:SI 2 "register_operand" "r")))
 232           (const_int 32))))]
 233   "TARGET_MUL32_HIGH"
 234   "mul<su>h\t%0, %1, %2"
 235   [(set_attr "type"     "mul32")
 236    (set_attr "mode"     "SI")
 237    (set_attr "length"   "3")])
 238
 239 (define_insn "mulsi3"
 240   [(set (match_operand:SI 0 "register_operand" "=a")
 241         (mult:SI (match_operand:SI 1 "register_operand" "%r")
 242                  (match_operand:SI 2 "register_operand" "r")))]
 243   "TARGET_MUL32"
 244   "mull\t%0, %1, %2"
 245   [(set_attr "type"     "mul32")
 246    (set_attr "mode"     "SI")
 247    (set_attr "length"   "3")])
 248
 249 (define_insn "mulhisi3"
 250   [(set (match_operand:SI 0 "register_operand" "=C,A")
 251         (mult:SI (sign_extend:SI
 252                   (match_operand:HI 1 "register_operand" "%r,r"))
 253                  (sign_extend:SI
 254                   (match_operand:HI 2 "register_operand" "r,r"))))]
 255   "TARGET_MUL16 || TARGET_MAC16"
 256   "@
 257    mul16s\t%0, %1, %2
 258    mul.aa.ll\t%1, %2"
 259   [(set_attr "type"     "mul16,mac16")
 260    (set_attr "mode"     "SI")
 261    (set_attr "length"   "3,3")])
 262
 263 (define_insn "umulhisi3"
 264   [(set (match_operand:SI 0 "register_operand" "=C,A")
 265         (mult:SI (zero_extend:SI
 266                   (match_operand:HI 1 "register_operand" "%r,r"))
 267                  (zero_extend:SI
 268                   (match_operand:HI 2 "register_operand" "r,r"))))]
 269   "TARGET_MUL16 || TARGET_MAC16"
 270   "@
 271    mul16u\t%0, %1, %2
 272    umul.aa.ll\t%1, %2"
 273   [(set_attr "type"     "mul16,mac16")
 274    (set_attr "mode"     "SI")
 275    (set_attr "length"   "3,3")])
 276
 277 (define_insn "muladdhisi"
 278   [(set (match_operand:SI 0 "register_operand" "=A")
 279         (plus:SI (mult:SI (sign_extend:SI
 280                            (match_operand:HI 1 "register_operand" "%r"))
 281                           (sign_extend:SI
 282                            (match_operand:HI 2 "register_operand" "r")))
 283                  (match_operand:SI 3 "register_operand" "0")))]
 284   "TARGET_MAC16"
 285   "mula.aa.ll\t%1, %2"
 286   [(set_attr "type"     "mac16")
 287    (set_attr "mode"     "SI")
 288    (set_attr "length"   "3")])
 289
 290 (define_insn "mulsubhisi"
 291   [(set (match_operand:SI 0 "register_operand" "=A")
 292         (minus:SI (match_operand:SI 1 "register_operand" "0")
 293                   (mult:SI (sign_extend:SI
 294                             (match_operand:HI 2 "register_operand" "%r"))
 295                            (sign_extend:SI
 296                             (match_operand:HI 3 "register_operand" "r")))))]
 297   "TARGET_MAC16"
 298   "muls.aa.ll\t%2, %3"
 299   [(set_attr "type"     "mac16")
 300    (set_attr "mode"     "SI")
 301    (set_attr "length"   "3")])
 302
 303 (define_insn "mulsf3"
 304   [(set (match_operand:SF 0 "register_operand" "=f")
 305         (mult:SF (match_operand:SF 1 "register_operand" "%f")
 306                  (match_operand:SF 2 "register_operand" "f")))]
 307   "TARGET_HARD_FLOAT"
 308   "mul.s\t%0, %1, %2"
 309   [(set_attr "type"     "fmadd")
 310    (set_attr "mode"     "SF")
 311    (set_attr "length"   "3")])
 312
 313 (define_insn "muladdsf3"
 314   [(set (match_operand:SF 0 "register_operand" "=f")
 315         (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f")
 316                           (match_operand:SF 2 "register_operand" "f"))
 317                  (match_operand:SF 3 "register_operand" "0")))]
 318   "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
 319   "madd.s\t%0, %1, %2"
 320   [(set_attr "type"     "fmadd")
 321    (set_attr "mode"     "SF")
 322    (set_attr "length"   "3")])
 323
 324 (define_insn "mulsubsf3"
 325   [(set (match_operand:SF 0 "register_operand" "=f")
 326         (minus:SF (match_operand:SF 1 "register_operand" "0")
 327                   (mult:SF (match_operand:SF 2 "register_operand" "%f")
 328                            (match_operand:SF 3 "register_operand" "f"))))]
 329   "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
 330   "msub.s\t%0, %2, %3"
 331   [(set_attr "type"     "fmadd")
 332    (set_attr "mode"     "SF")
 333    (set_attr "length"   "3")])
 334
 335 \f
 336 ;; Division.
 337
 338 (define_insn "divsi3"
 339   [(set (match_operand:SI 0 "register_operand" "=a")
 340         (div:SI (match_operand:SI 1 "register_operand" "r")
 341                 (match_operand:SI 2 "register_operand" "r")))]
 342   "TARGET_DIV32"
 343   "quos\t%0, %1, %2"
 344   [(set_attr "type"     "div32")
 345    (set_attr "mode"     "SI")
 346    (set_attr "length"   "3")])
 347
 348 (define_insn "udivsi3"
 349   [(set (match_operand:SI 0 "register_operand" "=a")
 350         (udiv:SI (match_operand:SI 1 "register_operand" "r")
 351                  (match_operand:SI 2 "register_operand" "r")))]
 352   "TARGET_DIV32"
 353   "quou\t%0, %1, %2"
 354   [(set_attr "type"     "div32")
 355    (set_attr "mode"     "SI")
 356    (set_attr "length"   "3")])
 357
 358 (define_insn "divsf3"
 359   [(set (match_operand:SF 0 "register_operand" "=f")
 360         (div:SF (match_operand:SF 1 "register_operand" "f")
 361                 (match_operand:SF 2 "register_operand" "f")))]
 362   "TARGET_HARD_FLOAT_DIV"
 363   "div.s\t%0, %1, %2"
 364   [(set_attr "type"     "fdiv")
 365    (set_attr "mode"     "SF")
 366    (set_attr "length"   "3")])
 367
 368 (define_insn "*recipsf2"
 369   [(set (match_operand:SF 0 "register_operand" "=f")
 370         (div:SF (match_operand:SF 1 "const_float_1_operand" "")
 371                 (match_operand:SF 2 "register_operand" "f")))]
 372   "TARGET_HARD_FLOAT_RECIP && flag_unsafe_math_optimizations"
 373   "recip.s\t%0, %2"
 374   [(set_attr "type"     "fdiv")
 375    (set_attr "mode"     "SF")
 376    (set_attr "length"   "3")])
 377
 378 \f
 379 ;; Remainders.
 380
 381 (define_insn "modsi3"
 382   [(set (match_operand:SI 0 "register_operand" "=a")
 383         (mod:SI (match_operand:SI 1 "register_operand" "r")
 384                 (match_operand:SI 2 "register_operand" "r")))]
 385   "TARGET_DIV32"
 386   "rems\t%0, %1, %2"
 387   [(set_attr "type"     "div32")
 388    (set_attr "mode"     "SI")
 389    (set_attr "length"   "3")])
 390
 391 (define_insn "umodsi3"
 392   [(set (match_operand:SI 0 "register_operand" "=a")
 393         (umod:SI (match_operand:SI 1 "register_operand" "r")
 394                  (match_operand:SI 2 "register_operand" "r")))]
 395   "TARGET_DIV32"
 396   "remu\t%0, %1, %2"
 397   [(set_attr "type"     "div32")
 398    (set_attr "mode"     "SI")
 399    (set_attr "length"   "3")])
 400
 401 \f
 402 ;; Square roots.
 403
 404 (define_insn "sqrtsf2"
 405   [(set (match_operand:SF 0 "register_operand" "=f")
 406         (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
 407   "TARGET_HARD_FLOAT_SQRT"
 408   "sqrt.s\t%0, %1"
 409   [(set_attr "type"     "fsqrt")
 410    (set_attr "mode"     "SF")
 411    (set_attr "length"   "3")])
 412
 413 (define_insn "*rsqrtsf2"
 414   [(set (match_operand:SF 0 "register_operand" "=f")
 415         (div:SF (match_operand:SF 1 "const_float_1_operand" "")
 416                 (sqrt:SF (match_operand:SF 2 "register_operand" "f"))))]
 417   "TARGET_HARD_FLOAT_RSQRT && flag_unsafe_math_optimizations"
 418   "rsqrt.s\t%0, %2"
 419   [(set_attr "type"     "fsqrt")
 420    (set_attr "mode"     "SF")
 421    (set_attr "length"   "3")])
 422
 423 \f
 424 ;; Absolute value.
 425
 426 (define_insn "abssi2"
 427   [(set (match_operand:SI 0 "register_operand" "=a")
 428         (abs:SI (match_operand:SI 1 "register_operand" "r")))]
 429   "TARGET_ABS"
 430   "abs\t%0, %1"
 431   [(set_attr "type"     "arith")
 432    (set_attr "mode"     "SI")
 433    (set_attr "length"   "3")])
 434
 435 (define_insn "abssf2"
 436   [(set (match_operand:SF 0 "register_operand" "=f")
 437         (abs:SF (match_operand:SF 1 "register_operand" "f")))]
 438   "TARGET_HARD_FLOAT"
 439   "abs.s\t%0, %1"
 440   [(set_attr "type"     "farith")
 441    (set_attr "mode"     "SF")
 442    (set_attr "length"   "3")])
 443
 444 \f
 445 ;; Min and max.
 446
 447 (define_insn "<code>si3"
 448   [(set (match_operand:SI 0 "register_operand" "=a")
 449         (any_minmax:SI (match_operand:SI 1 "register_operand" "%r")
 450                        (match_operand:SI 2 "register_operand" "r")))]
 451   "TARGET_MINMAX"
 452   "<minmax>\t%0, %1, %2"
 453   [(set_attr "type"     "arith")
 454    (set_attr "mode"     "SI")
 455    (set_attr "length"   "3")])
 456
 457 \f
 458 ;; Count leading/trailing zeros and find first bit.
 459
 460 (define_insn "clzsi2"
 461   [(set (match_operand:SI 0 "register_operand" "=a")
 462         (clz:SI (match_operand:SI 1 "register_operand" "r")))]
 463   "TARGET_NSA"
 464   "nsau\t%0, %1"
 465   [(set_attr "type"     "arith")
 466    (set_attr "mode"     "SI")
 467    (set_attr "length"   "3")])
 468
 469 (define_expand "ctzsi2"
 470   [(set (match_operand:SI 0 "register_operand" "")
 471         (ctz:SI (match_operand:SI 1 "register_operand" "")))]
 472   "TARGET_NSA"
 473 {
 474   rtx temp = gen_reg_rtx (SImode);
 475   emit_insn (gen_negsi2 (temp, operands[1]));
 476   emit_insn (gen_andsi3 (temp, temp, operands[1]));
 477   emit_insn (gen_clzsi2 (temp, temp));
 478   emit_insn (gen_negsi2 (temp, temp));
 479   emit_insn (gen_addsi3 (operands[0], temp, GEN_INT (31)));
 480   DONE;
 481 })
 482
 483 (define_expand "ffssi2"
 484   [(set (match_operand:SI 0 "register_operand" "")
 485         (ffs:SI (match_operand:SI 1 "register_operand" "")))]
 486   "TARGET_NSA"
 487 {
 488   rtx temp = gen_reg_rtx (SImode);
 489   emit_insn (gen_negsi2 (temp, operands[1]));
 490   emit_insn (gen_andsi3 (temp, temp, operands[1]));
 491   emit_insn (gen_clzsi2 (temp, temp));
 492   emit_insn (gen_negsi2 (temp, temp));
 493   emit_insn (gen_addsi3 (operands[0], temp, GEN_INT (32)));
 494   DONE;
 495 })
 496
 497 \f
 498 ;; Negation and one's complement.
 499
 500 (define_insn "negsi2"
 501   [(set (match_operand:SI 0 "register_operand" "=a")
 502         (neg:SI (match_operand:SI 1 "register_operand" "r")))]
 503   ""
 504   "neg\t%0, %1"
 505   [(set_attr "type"     "arith")
 506    (set_attr "mode"     "SI")
 507    (set_attr "length"   "3")])
 508
 509 (define_expand "one_cmplsi2"
 510   [(set (match_operand:SI 0 "register_operand" "")
 511         (not:SI (match_operand:SI 1 "register_operand" "")))]
 512   ""
 513 {
 514   rtx temp = gen_reg_rtx (SImode);
 515   emit_insn (gen_movsi (temp, constm1_rtx));
 516   emit_insn (gen_xorsi3 (operands[0], temp, operands[1]));
 517   DONE;
 518 })
 519
 520 (define_insn "negsf2"
 521   [(set (match_operand:SF 0 "register_operand" "=f")
 522         (neg:SF (match_operand:SF 1 "register_operand" "f")))]
 523   "TARGET_HARD_FLOAT"
 524   "neg.s\t%0, %1"
 525   [(set_attr "type"     "farith")
 526    (set_attr "mode"     "SF")
 527    (set_attr "length"   "3")])
 528
 529 \f
 530 ;; Logical instructions.
 531
 532 (define_insn "andsi3"
 533   [(set (match_operand:SI 0 "register_operand" "=a,a")
 534         (and:SI (match_operand:SI 1 "register_operand" "%r,r")
 535                 (match_operand:SI 2 "mask_operand" "P,r")))]
 536   ""
 537   "@
 538    extui\t%0, %1, 0, %K2
 539    and\t%0, %1, %2"
 540   [(set_attr "type"     "arith,arith")
 541    (set_attr "mode"     "SI")
 542    (set_attr "length"   "3,3")])
 543
 544 (define_insn "iorsi3"
 545   [(set (match_operand:SI 0 "register_operand" "=a")
 546         (ior:SI (match_operand:SI 1 "register_operand" "%r")
 547                 (match_operand:SI 2 "register_operand" "r")))]
 548   ""
 549   "or\t%0, %1, %2"
 550   [(set_attr "type"     "arith")
 551    (set_attr "mode"     "SI")
 552    (set_attr "length"   "3")])
 553
 554 (define_insn "xorsi3"
 555   [(set (match_operand:SI 0 "register_operand" "=a")
 556         (xor:SI (match_operand:SI 1 "register_operand" "%r")
 557                 (match_operand:SI 2 "register_operand" "r")))]
 558   ""
 559   "xor\t%0, %1, %2"
 560   [(set_attr "type"     "arith")
 561    (set_attr "mode"     "SI")
 562    (set_attr "length"   "3")])
 563
 564 \f
 565 ;; Zero-extend instructions.
 566
 567 (define_insn "zero_extendhisi2"
 568   [(set (match_operand:SI 0 "register_operand" "=a,a")
 569         (zero_extend:SI (match_operand:HI 1 "nonimmed_operand" "r,U")))]
 570   ""
 571   "@
 572    extui\t%0, %1, 0, 16
 573    l16ui\t%0, %1"
 574   [(set_attr "type"     "arith,load")
 575    (set_attr "mode"     "SI")
 576    (set_attr "length"   "3,3")])
 577
 578 (define_insn "zero_extendqisi2"
 579   [(set (match_operand:SI 0 "register_operand" "=a,a")
 580         (zero_extend:SI (match_operand:QI 1 "nonimmed_operand" "r,U")))]
 581   ""
 582   "@
 583    extui\t%0, %1, 0, 8
 584    l8ui\t%0, %1"
 585   [(set_attr "type"     "arith,load")
 586    (set_attr "mode"     "SI")
 587    (set_attr "length"   "3,3")])
 588
 589 \f
 590 ;; Sign-extend instructions.
 591
 592 (define_expand "extendhisi2"
 593   [(set (match_operand:SI 0 "register_operand" "")
 594         (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
 595   ""
 596 {
 597   if (sext_operand (operands[1], HImode))
 598     emit_insn (gen_extendhisi2_internal (operands[0], operands[1]));
 599   else
 600     xtensa_extend_reg (operands[0], operands[1]);
 601   DONE;
 602 })
 603
 604 (define_insn "extendhisi2_internal"
 605   [(set (match_operand:SI 0 "register_operand" "=B,a")
 606         (sign_extend:SI (match_operand:HI 1 "sext_operand" "r,U")))]
 607   ""
 608   "@
 609    sext\t%0, %1, 15
 610    l16si\t%0, %1"
 611   [(set_attr "type"     "arith,load")
 612    (set_attr "mode"     "SI")
 613    (set_attr "length"   "3,3")])
 614
 615 (define_expand "extendqisi2"
 616   [(set (match_operand:SI 0 "register_operand" "")
 617         (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
 618   ""
 619 {
 620   if (TARGET_SEXT)
 621     emit_insn (gen_extendqisi2_internal (operands[0], operands[1]));
 622   else
 623     xtensa_extend_reg (operands[0], operands[1]);
 624   DONE;
 625 })
 626
 627 (define_insn "extendqisi2_internal"
 628   [(set (match_operand:SI 0 "register_operand" "=B")
 629         (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
 630   "TARGET_SEXT"
 631   "sext\t%0, %1, 7"
 632   [(set_attr "type"     "arith")
 633    (set_attr "mode"     "SI")
 634    (set_attr "length"   "3")])
 635
 636 \f
 637 ;; Field extract instructions.
 638
 639 (define_expand "extv"
 640   [(set (match_operand:SI 0 "register_operand" "")
 641         (sign_extract:SI (match_operand:SI 1 "register_operand" "")
 642                          (match_operand:SI 2 "const_int_operand" "")
 643                          (match_operand:SI 3 "const_int_operand" "")))]
 644   "TARGET_SEXT"
 645 {
 646   if (!sext_fldsz_operand (operands[2], SImode))
 647     FAIL;
 648
 649   /* We could expand to a right shift followed by SEXT but that's
 650      no better than the standard left and right shift sequence.  */
 651   if (!lsbitnum_operand (operands[3], SImode))
 652     FAIL;
 653
 654   emit_insn (gen_extv_internal (operands[0], operands[1],
 655                                 operands[2], operands[3]));
 656   DONE;
 657 })
 658
 659 (define_insn "extv_internal"
 660   [(set (match_operand:SI 0 "register_operand" "=a")
 661         (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
 662                          (match_operand:SI 2 "sext_fldsz_operand" "i")
 663                          (match_operand:SI 3 "lsbitnum_operand" "i")))]
 664   "TARGET_SEXT"
 665 {
 666   int fldsz = INTVAL (operands[2]);
 667   operands[2] = GEN_INT (fldsz - 1);
 668   return "sext\t%0, %1, %2";
 669 }
 670   [(set_attr "type"     "arith")
 671    (set_attr "mode"     "SI")
 672    (set_attr "length"   "3")])
 673
 674 (define_expand "extzv"
 675   [(set (match_operand:SI 0 "register_operand" "")
 676         (zero_extract:SI (match_operand:SI 1 "register_operand" "")
 677                          (match_operand:SI 2 "const_int_operand" "")
 678                          (match_operand:SI 3 "const_int_operand" "")))]
 679   ""
 680 {
 681   if (!extui_fldsz_operand (operands[2], SImode))
 682     FAIL;
 683   emit_insn (gen_extzv_internal (operands[0], operands[1],
 684                                  operands[2], operands[3]));
 685   DONE;
 686 })
 687
 688 (define_insn "extzv_internal"
 689   [(set (match_operand:SI 0 "register_operand" "=a")
 690         (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
 691                          (match_operand:SI 2 "extui_fldsz_operand" "i")
 692                          (match_operand:SI 3 "const_int_operand" "i")))]
 693   ""
 694 {
 695   int shift;
 696   if (BITS_BIG_ENDIAN)
 697     shift = (32 - (INTVAL (operands[2]) + INTVAL (operands[3]))) & 0x1f;
 698   else
 699     shift = INTVAL (operands[3]) & 0x1f;
 700   operands[3] = GEN_INT (shift);
 701   return "extui\t%0, %1, %3, %2";
 702 }
 703   [(set_attr "type"     "arith")
 704    (set_attr "mode"     "SI")
 705    (set_attr "length"   "3")])
 706
 707 \f
 708 ;; Conversions.
 709
 710 (define_insn "fix_truncsfsi2"
 711   [(set (match_operand:SI 0 "register_operand" "=a")
 712         (fix:SI (match_operand:SF 1 "register_operand" "f")))]
 713   "TARGET_HARD_FLOAT"
 714   "trunc.s\t%0, %1, 0"
 715   [(set_attr "type"     "fconv")
 716    (set_attr "mode"     "SF")
 717    (set_attr "length"   "3")])
 718
 719 (define_insn "fixuns_truncsfsi2"
 720   [(set (match_operand:SI 0 "register_operand" "=a")
 721         (unsigned_fix:SI (match_operand:SF 1 "register_operand" "f")))]
 722   "TARGET_HARD_FLOAT"
 723   "utrunc.s\t%0, %1, 0"
 724   [(set_attr "type"     "fconv")
 725    (set_attr "mode"     "SF")
 726    (set_attr "length"   "3")])
 727
 728 (define_insn "floatsisf2"
 729   [(set (match_operand:SF 0 "register_operand" "=f")
 730         (float:SF (match_operand:SI 1 "register_operand" "a")))]
 731   "TARGET_HARD_FLOAT"
 732   "float.s\t%0, %1, 0"
 733   [(set_attr "type"     "fconv")
 734    (set_attr "mode"     "SF")
 735    (set_attr "length"   "3")])
 736
 737 (define_insn "floatunssisf2"
 738   [(set (match_operand:SF 0 "register_operand" "=f")
 739         (unsigned_float:SF (match_operand:SI 1 "register_operand" "a")))]
 740   "TARGET_HARD_FLOAT"
 741   "ufloat.s\t%0, %1, 0"
 742   [(set_attr "type"     "fconv")
 743    (set_attr "mode"     "SF")
 744    (set_attr "length"   "3")])
 745
 746 \f
 747 ;; Data movement instructions.
 748
 749 ;; 64-bit Integer moves
 750
 751 (define_expand "movdi"
 752   [(set (match_operand:DI 0 "nonimmed_operand" "")
 753         (match_operand:DI 1 "general_operand" ""))]
 754   ""
 755 {
 756   if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
 757     operands[1] = force_const_mem (DImode, operands[1]);
 758
 759   if (!register_operand (operands[0], DImode)
 760       && !register_operand (operands[1], DImode))
 761     operands[1] = force_reg (DImode, operands[1]);
 762
 763   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
 764 })
 765
 766 (define_insn_and_split "movdi_internal"
 767   [(set (match_operand:DI 0 "nonimmed_operand" "=a,W,a,a,U")
 768         (match_operand:DI 1 "move_operand" "r,i,T,U,r"))]
 769   "register_operand (operands[0], DImode)
 770    || register_operand (operands[1], DImode)"
 771   "#"
 772   "reload_completed"
 773   [(set (match_dup 0) (match_dup 2))
 774    (set (match_dup 1) (match_dup 3))]
 775 {
 776   xtensa_split_operand_pair (operands, SImode);
 777   if (reg_overlap_mentioned_p (operands[0], operands[3]))
 778     {
 779       rtx tmp;
 780       tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
 781       tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
 782     }
 783 })
 784
 785 ;; 32-bit Integer moves
 786
 787 (define_expand "movsi"
 788   [(set (match_operand:SI 0 "nonimmed_operand" "")
 789         (match_operand:SI 1 "general_operand" ""))]
 790   ""
 791 {
 792   if (xtensa_emit_move_sequence (operands, SImode))
 793     DONE;
 794 })
 795
 796 (define_insn "movsi_internal"
 797   [(set (match_operand:SI 0 "nonimmed_operand" "=D,D,D,D,R,R,a,q,a,W,a,a,U,*a,*A")
 798         (match_operand:SI 1 "move_operand" "M,D,d,R,D,d,r,r,I,i,T,U,r,*A,*r"))]
 799   "xtensa_valid_move (SImode, operands)"
 800   "@
 801    movi.n\t%0, %x1
 802    mov.n\t%0, %1
 803    mov.n\t%0, %1
 804    %v1l32i.n\t%0, %1
 805    %v0s32i.n\t%1, %0
 806    %v0s32i.n\t%1, %0
 807    mov\t%0, %1
 808    movsp\t%0, %1
 809    movi\t%0, %x1
 810    const16\t%0, %t1\;const16\t%0, %b1
 811    %v1l32r\t%0, %1
 812    %v1l32i\t%0, %1
 813    %v0s32i\t%1, %0
 814    rsr\t%0, ACCLO
 815    wsr\t%1, ACCLO"
 816   [(set_attr "type" "move,move,move,load,store,store,move,move,move,move,load,load,store,rsr,wsr")
 817    (set_attr "mode"     "SI")
 818    (set_attr "length"   "2,2,2,2,2,2,3,3,3,6,3,3,3,3,3")])
 819
 820 ;; 16-bit Integer moves
 821
 822 (define_expand "movhi"
 823   [(set (match_operand:HI 0 "nonimmed_operand" "")
 824         (match_operand:HI 1 "general_operand" ""))]
 825   ""
 826 {
 827   if (xtensa_emit_move_sequence (operands, HImode))
 828     DONE;
 829 })
 830
 831 (define_insn "movhi_internal"
 832   [(set (match_operand:HI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
 833         (match_operand:HI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
 834   "xtensa_valid_move (HImode, operands)"
 835   "@
 836    movi.n\t%0, %x1
 837    mov.n\t%0, %1
 838    mov\t%0, %1
 839    movi\t%0, %x1
 840    %v1l16ui\t%0, %1
 841    %v0s16i\t%1, %0
 842    rsr\t%0, ACCLO
 843    wsr\t%1, ACCLO"
 844   [(set_attr "type"     "move,move,move,move,load,store,rsr,wsr")
 845    (set_attr "mode"     "HI")
 846    (set_attr "length"   "2,2,3,3,3,3,3,3")])
 847
 848 ;; 8-bit Integer moves
 849
 850 (define_expand "movqi"
 851   [(set (match_operand:QI 0 "nonimmed_operand" "")
 852         (match_operand:QI 1 "general_operand" ""))]
 853   ""
 854 {
 855   if (xtensa_emit_move_sequence (operands, QImode))
 856     DONE;
 857 })
 858
 859 (define_insn "movqi_internal"
 860   [(set (match_operand:QI 0 "nonimmed_operand" "=D,D,a,a,a,U,*a,*A")
 861         (match_operand:QI 1 "move_operand" "M,d,r,I,U,r,*A,*r"))]
 862   "xtensa_valid_move (QImode, operands)"
 863   "@
 864    movi.n\t%0, %x1
 865    mov.n\t%0, %1
 866    mov\t%0, %1
 867    movi\t%0, %x1
 868    %v1l8ui\t%0, %1
 869    %v0s8i\t%1, %0
 870    rsr\t%0, ACCLO
 871    wsr\t%1, ACCLO"
 872   [(set_attr "type"     "move,move,move,move,load,store,rsr,wsr")
 873    (set_attr "mode"     "QI")
 874    (set_attr "length"   "2,2,3,3,3,3,3,3")])
 875
 876 ;; 32-bit floating point moves
 877
 878 (define_expand "movsf"
 879   [(set (match_operand:SF 0 "nonimmed_operand" "")
 880         (match_operand:SF 1 "general_operand" ""))]
 881   ""
 882 {
 883   if (!TARGET_CONST16 && CONSTANT_P (operands[1]))
 884     operands[1] = force_const_mem (SFmode, operands[1]);
 885
 886   if ((!register_operand (operands[0], SFmode)
 887        && !register_operand (operands[1], SFmode))
 888       || (FP_REG_P (xt_true_regnum (operands[0]))
 889           && !(reload_in_progress | reload_completed)
 890           && (constantpool_mem_p (operands[1])
 891               || CONSTANT_P (operands[1]))))
 892     operands[1] = force_reg (SFmode, operands[1]);
 893
 894   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
 895 })
 896
 897 (define_insn "movsf_internal"
 898   [(set (match_operand:SF 0 "nonimmed_operand" "=f,f,U,D,D,R,a,f,a,W,a,a,U")
 899         (match_operand:SF 1 "move_operand" "f,U,f,d,R,d,r,r,f,iF,T,U,r"))]
 900   "((register_operand (operands[0], SFmode)
 901      || register_operand (operands[1], SFmode))
 902     && !(FP_REG_P (xt_true_regnum (operands[0]))
 903          && (constantpool_mem_p (operands[1]) || CONSTANT_P (operands[1]))))"
 904   "@
 905    mov.s\t%0, %1
 906    %v1lsi\t%0, %1
 907    %v0ssi\t%1, %0
 908    mov.n\t%0, %1
 909    %v1l32i.n\t%0, %1
 910    %v0s32i.n\t%1, %0
 911    mov\t%0, %1
 912    wfr\t%0, %1
 913    rfr\t%0, %1
 914    const16\t%0, %t1\;const16\t%0, %b1
 915    %v1l32r\t%0, %1
 916    %v1l32i\t%0, %1
 917    %v0s32i\t%1, %0"
 918   [(set_attr "type"     "farith,fload,fstore,move,load,store,move,farith,farith,move,load,load,store")
 919    (set_attr "mode"     "SF")
 920    (set_attr "length"   "3,3,3,2,2,2,3,3,3,6,3,3,3")])
 921
 922 (define_insn "*lsiu"
 923   [(set (match_operand:SF 0 "register_operand" "=f")
 924         (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "+a")
 925                          (match_operand:SI 2 "fpmem_offset_operand" "i"))))
 926    (set (match_dup 1)
 927         (plus:SI (match_dup 1) (match_dup 2)))]
 928   "TARGET_HARD_FLOAT"
 929 {
 930   if (volatile_refs_p (PATTERN (insn)))
 931     output_asm_insn ("memw", operands);
 932   return "lsiu\t%0, %1, %2";
 933 }
 934   [(set_attr "type"     "fload")
 935    (set_attr "mode"     "SF")
 936    (set_attr "length"   "3")])
 937
 938 (define_insn "*ssiu"
 939   [(set (mem:SF (plus:SI (match_operand:SI 0 "register_operand" "+a")
 940                          (match_operand:SI 1 "fpmem_offset_operand" "i")))
 941         (match_operand:SF 2 "register_operand" "f"))
 942    (set (match_dup 0)
 943         (plus:SI (match_dup 0) (match_dup 1)))]
 944   "TARGET_HARD_FLOAT"
 945 {
 946   if (volatile_refs_p (PATTERN (insn)))
 947     output_asm_insn ("memw", operands);
 948   return "ssiu\t%2, %0, %1";
 949 }
 950   [(set_attr "type"     "fstore")
 951    (set_attr "mode"     "SF")
 952    (set_attr "length"   "3")])
 953
 954 ;; 64-bit floating point moves
 955
 956 (define_expand "movdf"
 957   [(set (match_operand:DF 0 "nonimmed_operand" "")
 958         (match_operand:DF 1 "general_operand" ""))]
 959   ""
 960 {
 961   if (CONSTANT_P (operands[1]) && !TARGET_CONST16)
 962     operands[1] = force_const_mem (DFmode, operands[1]);
 963
 964   if (!register_operand (operands[0], DFmode)
 965       && !register_operand (operands[1], DFmode))
 966     operands[1] = force_reg (DFmode, operands[1]);
 967
 968   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
 969 })
 970
 971 (define_insn_and_split "movdf_internal"
 972   [(set (match_operand:DF 0 "nonimmed_operand" "=a,W,a,a,U")
 973         (match_operand:DF 1 "move_operand" "r,iF,T,U,r"))]
 974   "register_operand (operands[0], DFmode)
 975    || register_operand (operands[1], DFmode)"
 976   "#"
 977   "reload_completed"
 978   [(set (match_dup 0) (match_dup 2))
 979    (set (match_dup 1) (match_dup 3))]
 980 {
 981   xtensa_split_operand_pair (operands, SFmode);
 982   if (reg_overlap_mentioned_p (operands[0], operands[3]))
 983     {
 984       rtx tmp;
 985       tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
 986       tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
 987     }
 988 })
 989
 990 ;; Block moves
 991
 992 (define_expand "movmemsi"
 993   [(parallel [(set (match_operand:BLK 0 "" "")
 994                    (match_operand:BLK 1 "" ""))
 995               (use (match_operand:SI 2 "arith_operand" ""))
 996               (use (match_operand:SI 3 "const_int_operand" ""))])]
 997   ""
 998 {
 999   if (!xtensa_expand_block_move (operands))
1000     FAIL;
1001   DONE;
1002 })
1003
1004 \f
1005 ;; Shift instructions.
1006
1007 (define_expand "ashlsi3"
1008   [(set (match_operand:SI 0 "register_operand" "")
1009         (ashift:SI (match_operand:SI 1 "register_operand" "")
1010                    (match_operand:SI 2 "arith_operand" "")))]
1011   ""
1012 {
1013   operands[1] = xtensa_copy_incoming_a7 (operands[1]);
1014 })
1015
1016 (define_insn "ashlsi3_internal"
1017   [(set (match_operand:SI 0 "register_operand" "=a,a")
1018         (ashift:SI (match_operand:SI 1 "register_operand" "r,r")
1019                    (match_operand:SI 2 "arith_operand" "J,r")))]
1020   ""
1021   "@
1022    slli\t%0, %1, %R2
1023    ssl\t%2\;sll\t%0, %1"
1024   [(set_attr "type"     "arith,arith")
1025    (set_attr "mode"     "SI")
1026    (set_attr "length"   "3,6")])
1027
1028 (define_insn "ashrsi3"
1029   [(set (match_operand:SI 0 "register_operand" "=a,a")
1030         (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
1031                      (match_operand:SI 2 "arith_operand" "J,r")))]
1032   ""
1033   "@
1034    srai\t%0, %1, %R2
1035    ssr\t%2\;sra\t%0, %1"
1036   [(set_attr "type"     "arith,arith")
1037    (set_attr "mode"     "SI")
1038    (set_attr "length"   "3,6")])
1039
1040 (define_insn "lshrsi3"
1041   [(set (match_operand:SI 0 "register_operand" "=a,a")
1042         (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
1043                      (match_operand:SI 2 "arith_operand" "J,r")))]
1044   ""
1045 {
1046   if (which_alternative == 0)
1047     {
1048       if ((INTVAL (operands[2]) & 0x1f) < 16)
1049         return "srli\t%0, %1, %R2";
1050       else
1051         return "extui\t%0, %1, %R2, %L2";
1052     }
1053   return "ssr\t%2\;srl\t%0, %1";
1054 }
1055   [(set_attr "type"     "arith,arith")
1056    (set_attr "mode"     "SI")
1057    (set_attr "length"   "3,6")])
1058
1059 (define_insn "rotlsi3"
1060   [(set (match_operand:SI 0 "register_operand" "=a,a")
1061         (rotate:SI (match_operand:SI 1 "register_operand" "r,r")
1062                      (match_operand:SI 2 "arith_operand" "J,r")))]
1063   ""
1064   "@
1065    ssai\t%L2\;src\t%0, %1, %1
1066    ssl\t%2\;src\t%0, %1, %1"
1067   [(set_attr "type"     "multi,multi")
1068    (set_attr "mode"     "SI")
1069    (set_attr "length"   "6,6")])
1070
1071 (define_insn "rotrsi3"
1072   [(set (match_operand:SI 0 "register_operand" "=a,a")
1073         (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
1074                      (match_operand:SI 2 "arith_operand" "J,r")))]
1075   ""
1076   "@
1077    ssai\t%R2\;src\t%0, %1, %1
1078    ssr\t%2\;src\t%0, %1, %1"
1079   [(set_attr "type"     "multi,multi")
1080    (set_attr "mode"     "SI")
1081    (set_attr "length"   "6,6")])
1082
1083 \f
1084 ;; Comparisons.
1085
1086 ;; Handle comparisons by stashing away the operands and then using that
1087 ;; information in the subsequent conditional branch.
1088
1089 (define_expand "cmpsi"
1090   [(set (cc0)
1091         (compare:CC (match_operand:SI 0 "register_operand" "")
1092                     (match_operand:SI 1 "nonmemory_operand" "")))]
1093   ""
1094 {
1095   branch_cmp[0] = operands[0];
1096   branch_cmp[1] = operands[1];
1097   branch_type = CMP_SI;
1098   DONE;
1099 })
1100
1101 (define_expand "cmpsf"
1102   [(set (cc0)
1103         (compare:CC (match_operand:SF 0 "register_operand" "")
1104                     (match_operand:SF 1 "register_operand" "")))]
1105   "TARGET_HARD_FLOAT"
1106 {
1107   branch_cmp[0] = operands[0];
1108   branch_cmp[1] = operands[1];
1109   branch_type = CMP_SF;
1110   DONE;
1111 })
1112
1113 \f
1114 ;; Conditional branches.
1115
1116 (define_expand "b<code>"
1117   [(set (pc)
1118         (if_then_else (any_cond (cc0) (const_int 0))
1119                       (label_ref (match_operand 0 "" ""))
1120                       (pc)))]
1121   ""
1122 {
1123   xtensa_expand_conditional_branch (operands, <CODE>);
1124   DONE;
1125 })
1126
1127 ;; Branch patterns for standard integer comparisons
1128
1129 (define_insn "*btrue"
1130   [(set (pc)
1131         (if_then_else (match_operator 3 "branch_operator"
1132                        [(match_operand:SI 0 "register_operand" "r,r")
1133                         (match_operand:SI 1 "branch_operand" "K,r")])
1134                       (label_ref (match_operand 2 "" ""))
1135                       (pc)))]
1136   ""
1137 {
1138   return xtensa_emit_branch (false, which_alternative == 0, operands);
1139 }
1140   [(set_attr "type"     "jump,jump")
1141    (set_attr "mode"     "none")
1142    (set_attr "length"   "3,3")])
1143
1144 (define_insn "*bfalse"
1145   [(set (pc)
1146         (if_then_else (match_operator 3 "branch_operator"
1147                        [(match_operand:SI 0 "register_operand" "r,r")
1148                         (match_operand:SI 1 "branch_operand" "K,r")])
1149                       (pc)
1150                       (label_ref (match_operand 2 "" ""))))]
1151   ""
1152 {
1153   return xtensa_emit_branch (true, which_alternative == 0, operands);
1154 }
1155   [(set_attr "type"     "jump,jump")
1156    (set_attr "mode"     "none")
1157    (set_attr "length"   "3,3")])
1158
1159 (define_insn "*ubtrue"
1160   [(set (pc)
1161         (if_then_else (match_operator 3 "ubranch_operator"
1162                        [(match_operand:SI 0 "register_operand" "r,r")
1163                         (match_operand:SI 1 "ubranch_operand" "L,r")])
1164                       (label_ref (match_operand 2 "" ""))
1165                       (pc)))]
1166   ""
1167 {
1168   return xtensa_emit_branch (false, which_alternative == 0, operands);
1169 }
1170   [(set_attr "type"     "jump,jump")
1171    (set_attr "mode"     "none")
1172    (set_attr "length"   "3,3")])
1173
1174 (define_insn "*ubfalse"
1175   [(set (pc)
1176         (if_then_else (match_operator 3 "ubranch_operator"
1177                          [(match_operand:SI 0 "register_operand" "r,r")
1178                           (match_operand:SI 1 "ubranch_operand" "L,r")])
1179                       (pc)
1180                       (label_ref (match_operand 2 "" ""))))]
1181   ""
1182 {
1183   return xtensa_emit_branch (true, which_alternative == 0, operands);
1184 }
1185   [(set_attr "type"     "jump,jump")
1186    (set_attr "mode"     "none")
1187    (set_attr "length"   "3,3")])
1188
1189 ;; Branch patterns for bit testing
1190
1191 (define_insn "*bittrue"
1192   [(set (pc)
1193         (if_then_else (match_operator 3 "boolean_operator"
1194                         [(zero_extract:SI
1195                             (match_operand:SI 0 "register_operand" "r,r")
1196                             (const_int 1)
1197                             (match_operand:SI 1 "arith_operand" "J,r"))
1198                          (const_int 0)])
1199                       (label_ref (match_operand 2 "" ""))
1200                       (pc)))]
1201   ""
1202 {
1203   return xtensa_emit_bit_branch (false, which_alternative == 0, operands);
1204 }
1205   [(set_attr "type"     "jump")
1206    (set_attr "mode"     "none")
1207    (set_attr "length"   "3")])
1208
1209 (define_insn "*bitfalse"
1210   [(set (pc)
1211         (if_then_else (match_operator 3 "boolean_operator"
1212                         [(zero_extract:SI
1213                             (match_operand:SI 0 "register_operand" "r,r")
1214                             (const_int 1)
1215                             (match_operand:SI 1 "arith_operand" "J,r"))
1216                          (const_int 0)])
1217                       (pc)
1218                       (label_ref (match_operand 2 "" ""))))]
1219   ""
1220 {
1221   return xtensa_emit_bit_branch (true, which_alternative == 0, operands);
1222 }
1223   [(set_attr "type"     "jump")
1224    (set_attr "mode"     "none")
1225    (set_attr "length"   "3")])
1226
1227 (define_insn "*masktrue"
1228   [(set (pc)
1229         (if_then_else (match_operator 3 "boolean_operator"
1230                  [(and:SI (match_operand:SI 0 "register_operand" "r")
1231                           (match_operand:SI 1 "register_operand" "r"))
1232                   (const_int 0)])
1233                       (label_ref (match_operand 2 "" ""))
1234                       (pc)))]
1235   ""
1236 {
1237   switch (GET_CODE (operands[3]))
1238     {
1239     case EQ:            return "bnone\t%0, %1, %2";
1240     case NE:            return "bany\t%0, %1, %2";
1241     default:            gcc_unreachable ();
1242     }
1243 }
1244   [(set_attr "type"     "jump")
1245    (set_attr "mode"     "none")
1246    (set_attr "length"   "3")])
1247
1248 (define_insn "*maskfalse"
1249   [(set (pc)
1250         (if_then_else (match_operator 3 "boolean_operator"
1251                  [(and:SI (match_operand:SI 0 "register_operand" "r")
1252                           (match_operand:SI 1 "register_operand" "r"))
1253                   (const_int 0)])
1254                       (pc)
1255                       (label_ref (match_operand 2 "" ""))))]
1256   ""
1257 {
1258   switch (GET_CODE (operands[3]))
1259     {
1260     case EQ:            return "bany\t%0, %1, %2";
1261     case NE:            return "bnone\t%0, %1, %2";
1262     default:            gcc_unreachable ();
1263     }
1264 }
1265   [(set_attr "type"     "jump")
1266    (set_attr "mode"     "none")
1267    (set_attr "length"   "3")])
1268
1269
1270 ;; Define the loop insns used by bct optimization to represent the
1271 ;; start and end of a zero-overhead loop (in loop.c).  This start
1272 ;; template generates the loop insn; the end template doesn't generate
1273 ;; any instructions since loop end is handled in hardware.
1274
1275 (define_insn "zero_cost_loop_start"
1276   [(set (pc)
1277         (if_then_else (eq (match_operand:SI 0 "register_operand" "a")
1278                           (const_int 0))
1279                       (label_ref (match_operand 1 "" ""))
1280                       (pc)))
1281    (set (reg:SI 19)
1282         (plus:SI (match_dup 0) (const_int -1)))]
1283   ""
1284   "loopnez\t%0, %l1"
1285   [(set_attr "type"     "jump")
1286    (set_attr "mode"     "none")
1287    (set_attr "length"   "3")])
1288
1289 (define_insn "zero_cost_loop_end"
1290   [(set (pc)
1291         (if_then_else (ne (reg:SI 19) (const_int 0))
1292                       (label_ref (match_operand 0 "" ""))
1293                       (pc)))
1294    (set (reg:SI 19)
1295         (plus:SI (reg:SI 19) (const_int -1)))]
1296   ""
1297 {
1298     xtensa_emit_loop_end (insn, operands);
1299     return "";
1300 }
1301   [(set_attr "type"     "jump")
1302    (set_attr "mode"     "none")
1303    (set_attr "length"   "0")])
1304
1305 \f
1306 ;; Setting a register from a comparison.
1307
1308 (define_expand "s<code>"
1309   [(set (match_operand:SI 0 "register_operand" "")
1310         (any_scc:SI (match_dup 1)
1311                     (match_dup 2)))]
1312   ""
1313 {
1314   operands[1] = gen_rtx_<CODE> (SImode, branch_cmp[0], branch_cmp[1]);
1315   if (!xtensa_expand_scc (operands))
1316     FAIL;
1317   DONE;
1318 })
1319
1320 \f
1321 ;; Conditional moves.
1322
1323 (define_expand "movsicc"
1324   [(set (match_operand:SI 0 "register_operand" "")
1325         (if_then_else:SI (match_operand 1 "comparison_operator" "")
1326                          (match_operand:SI 2 "register_operand" "")
1327                          (match_operand:SI 3 "register_operand" "")))]
1328   ""
1329 {
1330   if (!xtensa_expand_conditional_move (operands, 0))
1331     FAIL;
1332   DONE;
1333 })
1334
1335 (define_expand "movsfcc"
1336   [(set (match_operand:SF 0 "register_operand" "")
1337         (if_then_else:SF (match_operand 1 "comparison_operator" "")
1338                          (match_operand:SF 2 "register_operand" "")
1339                          (match_operand:SF 3 "register_operand" "")))]
1340   ""
1341 {
1342   if (!xtensa_expand_conditional_move (operands, 1))
1343     FAIL;
1344   DONE;
1345 })
1346
1347 (define_insn "movsicc_internal0"
1348   [(set (match_operand:SI 0 "register_operand" "=a,a")
1349         (if_then_else:SI (match_operator 4 "branch_operator"
1350                            [(match_operand:SI 1 "register_operand" "r,r")
1351                             (const_int 0)])
1352                          (match_operand:SI 2 "register_operand" "r,0")
1353                          (match_operand:SI 3 "register_operand" "0,r")))]
1354   ""
1355 {
1356   return xtensa_emit_movcc (which_alternative == 1, false, false, operands);
1357 }
1358   [(set_attr "type"     "move,move")
1359    (set_attr "mode"     "SI")
1360    (set_attr "length"   "3,3")])
1361
1362 (define_insn "movsicc_internal1"
1363   [(set (match_operand:SI 0 "register_operand" "=a,a")
1364         (if_then_else:SI (match_operator 4 "boolean_operator"
1365                            [(match_operand:CC 1 "register_operand" "b,b")
1366                             (const_int 0)])
1367                          (match_operand:SI 2 "register_operand" "r,0")
1368                          (match_operand:SI 3 "register_operand" "0,r")))]
1369   "TARGET_BOOLEANS"
1370 {
1371   return xtensa_emit_movcc (which_alternative == 1, false, true, operands);
1372 }
1373   [(set_attr "type"     "move,move")
1374    (set_attr "mode"     "SI")
1375    (set_attr "length"   "3,3")])
1376
1377 (define_insn "movsfcc_internal0"
1378   [(set (match_operand:SF 0 "register_operand" "=a,a,f,f")
1379         (if_then_else:SF (match_operator 4 "branch_operator"
1380                            [(match_operand:SI 1 "register_operand" "r,r,r,r")
1381                             (const_int 0)])
1382                          (match_operand:SF 2 "register_operand" "r,0,f,0")
1383                          (match_operand:SF 3 "register_operand" "0,r,0,f")))]
1384   ""
1385 {
1386   return xtensa_emit_movcc ((which_alternative & 1) == 1,
1387                             which_alternative >= 2, false, operands);
1388 }
1389   [(set_attr "type"     "move,move,move,move")
1390    (set_attr "mode"     "SF")
1391    (set_attr "length"   "3,3,3,3")])
1392
1393 (define_insn "movsfcc_internal1"
1394   [(set (match_operand:SF 0 "register_operand" "=a,a,f,f")
1395         (if_then_else:SF (match_operator 4 "boolean_operator"
1396                            [(match_operand:CC 1 "register_operand" "b,b,b,b")
1397                             (const_int 0)])
1398                          (match_operand:SF 2 "register_operand" "r,0,f,0")
1399                          (match_operand:SF 3 "register_operand" "0,r,0,f")))]
1400   "TARGET_BOOLEANS"
1401 {
1402   return xtensa_emit_movcc ((which_alternative & 1) == 1,
1403                             which_alternative >= 2, true, operands);
1404 }
1405   [(set_attr "type"     "move,move,move,move")
1406    (set_attr "mode"     "SF")
1407    (set_attr "length"   "3,3,3,3")])
1408
1409 \f
1410 ;; Floating-point comparisons.
1411
1412 (define_insn "s<code>_sf"
1413   [(set (match_operand:CC 0 "register_operand" "=b")
1414         (any_scc_sf:CC (match_operand:SF 1 "register_operand" "f")
1415                        (match_operand:SF 2 "register_operand" "f")))]
1416   "TARGET_HARD_FLOAT"
1417   "o<code>.s\t%0, %1, %2"
1418   [(set_attr "type"     "farith")
1419    (set_attr "mode"     "BL")
1420    (set_attr "length"   "3")])
1421
1422 \f
1423 ;; Unconditional branches.
1424
1425 (define_insn "jump"
1426   [(set (pc)
1427         (label_ref (match_operand 0 "" "")))]
1428   ""
1429   "j\t%l0"
1430   [(set_attr "type"     "jump")
1431    (set_attr "mode"     "none")
1432    (set_attr "length"   "3")])
1433
1434 (define_expand "indirect_jump"
1435   [(set (pc)
1436         (match_operand 0 "register_operand" ""))]
1437   ""
1438 {
1439   rtx dest = operands[0];
1440   if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
1441     operands[0] = copy_to_mode_reg (Pmode, dest);
1442
1443   emit_jump_insn (gen_indirect_jump_internal (dest));
1444   DONE;
1445 })
1446
1447 (define_insn "indirect_jump_internal"
1448   [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
1449   ""
1450   "jx\t%0"
1451   [(set_attr "type"     "jump")
1452    (set_attr "mode"     "none")
1453    (set_attr "length"   "3")])
1454
1455
1456 (define_expand "tablejump"
1457   [(use (match_operand:SI 0 "register_operand" ""))
1458    (use (label_ref (match_operand 1 "" "")))]
1459    ""
1460 {
1461   rtx target = operands[0];
1462   if (flag_pic)
1463     {
1464       /* For PIC, the table entry is relative to the start of the table.  */
1465       rtx label = gen_reg_rtx (SImode);
1466       target = gen_reg_rtx (SImode);
1467       emit_move_insn (label, gen_rtx_LABEL_REF (SImode, operands[1]));
1468       emit_insn (gen_addsi3 (target, operands[0], label));
1469     }
1470   emit_jump_insn (gen_tablejump_internal (target, operands[1]));
1471   DONE;
1472 })
1473
1474 (define_insn "tablejump_internal"
1475   [(set (pc)
1476         (match_operand:SI 0 "register_operand" "r"))
1477    (use (label_ref (match_operand 1 "" "")))]
1478   ""
1479   "jx\t%0"
1480   [(set_attr "type"     "jump")
1481    (set_attr "mode"     "none")
1482    (set_attr "length"   "3")])
1483
1484 \f
1485 ;; Function calls.
1486
1487 (define_expand "sym_PLT"
1488   [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PLT))]
1489   ""
1490   "")
1491
1492 (define_expand "call"
1493   [(call (match_operand 0 "memory_operand" "")
1494          (match_operand 1 "" ""))]
1495   ""
1496 {
1497   rtx addr = XEXP (operands[0], 0);
1498   if (flag_pic && GET_CODE (addr) == SYMBOL_REF
1499       && (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
1500     addr = gen_sym_PLT (addr);
1501   if (!call_insn_operand (addr, VOIDmode))
1502     XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
1503 })
1504
1505 (define_insn "call_internal"
1506   [(call (mem (match_operand:SI 0 "call_insn_operand" "nir"))
1507          (match_operand 1 "" "i"))]
1508   ""
1509 {
1510   return xtensa_emit_call (0, operands);
1511 }
1512   [(set_attr "type"     "call")
1513    (set_attr "mode"     "none")
1514    (set_attr "length"   "3")])
1515
1516 (define_expand "call_value"
1517   [(set (match_operand 0 "register_operand" "")
1518         (call (match_operand 1 "memory_operand" "")
1519               (match_operand 2 "" "")))]
1520   ""
1521 {
1522   rtx addr = XEXP (operands[1], 0);
1523   if (flag_pic && GET_CODE (addr) == SYMBOL_REF
1524       && (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
1525     addr = gen_sym_PLT (addr);
1526   if (!call_insn_operand (addr, VOIDmode))
1527     XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
1528 })
1529
1530 (define_insn "call_value_internal"
1531    [(set (match_operand 0 "register_operand" "=a")
1532          (call (mem (match_operand:SI 1 "call_insn_operand" "nir"))
1533                (match_operand 2 "" "i")))]
1534   ""
1535 {
1536   return xtensa_emit_call (1, operands);
1537 }
1538   [(set_attr "type"     "call")
1539    (set_attr "mode"     "none")
1540    (set_attr "length"   "3")])
1541
1542 (define_insn "entry"
1543   [(set (reg:SI A1_REG)
1544         (unspec_volatile:SI [(match_operand:SI 0 "const_int_operand" "i")
1545                              (match_operand:SI 1 "const_int_operand" "i")]
1546                             UNSPECV_ENTRY))]
1547   ""
1548   "entry\tsp, %1"
1549   [(set_attr "type"     "move")
1550    (set_attr "mode"     "SI")
1551    (set_attr "length"   "3")])
1552
1553 (define_insn "return"
1554   [(return)
1555    (use (reg:SI A0_REG))]
1556   "reload_completed"
1557 {
1558   return (TARGET_DENSITY ? "retw.n" : "retw");
1559 }
1560   [(set_attr "type"     "jump")
1561    (set_attr "mode"     "none")
1562    (set_attr "length"   "2")])
1563
1564 \f
1565 ;; Miscellaneous instructions.
1566
1567 (define_expand "prologue"
1568   [(const_int 0)]
1569   ""
1570 {
1571   xtensa_expand_prologue ();
1572   DONE;
1573 })
1574
1575 (define_expand "epilogue"
1576   [(return)]
1577   ""
1578 {
1579   emit_jump_insn (gen_return ());
1580   DONE;
1581 })
1582
1583 (define_insn "nop"
1584   [(const_int 0)]
1585   ""
1586 {
1587   return (TARGET_DENSITY ? "nop.n" : "nop");
1588 }
1589   [(set_attr "type"     "nop")
1590    (set_attr "mode"     "none")
1591    (set_attr "length"   "3")])
1592
1593 (define_expand "nonlocal_goto"
1594   [(match_operand:SI 0 "general_operand" "")
1595    (match_operand:SI 1 "general_operand" "")
1596    (match_operand:SI 2 "general_operand" "")
1597    (match_operand:SI 3 "" "")]
1598   ""
1599 {
1600   xtensa_expand_nonlocal_goto (operands);
1601   DONE;
1602 })
1603
1604 ;; Setting up a frame pointer is tricky for Xtensa because GCC doesn't
1605 ;; know if a frame pointer is required until the reload pass, and
1606 ;; because there may be an incoming argument value in the hard frame
1607 ;; pointer register (a7).  If there is an incoming argument in that
1608 ;; register, the "set_frame_ptr" insn gets inserted immediately after
1609 ;; the insn that copies the incoming argument to a pseudo or to the
1610 ;; stack.  This serves several purposes here: (1) it keeps the
1611 ;; optimizer from copy-propagating or scheduling the use of a7 as an
1612 ;; incoming argument away from the beginning of the function; (2) we
1613 ;; can use a post-reload splitter to expand away the insn if a frame
1614 ;; pointer is not required, so that the post-reload scheduler can do
1615 ;; the right thing; and (3) it makes it easy for the prologue expander
1616 ;; to search for this insn to determine whether it should add a new insn
1617 ;; to set up the frame pointer.
1618
1619 (define_insn "set_frame_ptr"
1620   [(set (reg:SI A7_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_FP))]
1621   ""
1622 {
1623   if (frame_pointer_needed)
1624     return "mov\ta7, sp";
1625   return "";
1626 }
1627   [(set_attr "type"     "move")
1628    (set_attr "mode"     "SI")
1629    (set_attr "length"   "3")])
1630
1631 ;; Post-reload splitter to remove fp assignment when it's not needed.
1632 (define_split
1633   [(set (reg:SI A7_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_FP))]
1634   "reload_completed && !frame_pointer_needed"
1635   [(unspec [(const_int 0)] UNSPEC_NOP)]
1636   "")
1637
1638 ;; The preceding splitter needs something to split the insn into;
1639 ;; things start breaking if the result is just a "use" so instead we
1640 ;; generate the following insn.
1641 (define_insn "*unspec_nop"
1642   [(unspec [(const_int 0)] UNSPEC_NOP)]
1643   ""
1644   ""
1645   [(set_attr "type"     "nop")
1646    (set_attr "mode"     "none")
1647    (set_attr "length"   "0")])
1648
1649 ;; The fix_return_addr pattern sets the high 2 bits of an address in a
1650 ;; register to match the high bits of the current PC.
1651 (define_insn "fix_return_addr"
1652   [(set (match_operand:SI 0 "register_operand" "=a")
1653         (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
1654                    UNSPEC_RET_ADDR))
1655    (clobber (match_scratch:SI 2 "=r"))
1656    (clobber (match_scratch:SI 3 "=r"))]
1657   ""
1658   "mov\t%2, a0\;call0\t0f\;.align\t4\;0:\;mov\t%3, a0\;mov\ta0, %2\;\
1659 srli\t%3, %3, 30\;slli\t%0, %1, 2\;ssai\t2\;src\t%0, %3, %0"
1660   [(set_attr "type"     "multi")
1661    (set_attr "mode"     "SI")
1662    (set_attr "length"   "24")])
1663
1664 \f
1665 ;; Instructions for the Xtensa "boolean" option.
1666
1667 (define_insn "*booltrue"
1668   [(set (pc)
1669         (if_then_else (match_operator 2 "boolean_operator"
1670                          [(match_operand:CC 0 "register_operand" "b")
1671                           (const_int 0)])
1672                       (label_ref (match_operand 1 "" ""))
1673                       (pc)))]
1674   "TARGET_BOOLEANS"
1675 {
1676   if (GET_CODE (operands[2]) == EQ)
1677     return "bf\t%0, %1";
1678   else
1679     return "bt\t%0, %1";
1680 }
1681   [(set_attr "type"     "jump")
1682    (set_attr "mode"     "none")
1683    (set_attr "length"   "3")])
1684
1685 (define_insn "*boolfalse"
1686   [(set (pc)
1687         (if_then_else (match_operator 2 "boolean_operator"
1688                          [(match_operand:CC 0 "register_operand" "b")
1689                           (const_int 0)])
1690                       (pc)
1691                       (label_ref (match_operand 1 "" ""))))]
1692   "TARGET_BOOLEANS"
1693 {
1694   if (GET_CODE (operands[2]) == EQ)
1695     return "bt\t%0, %1";
1696   else
1697     return "bf\t%0, %1";
1698 }
1699   [(set_attr "type"     "jump")
1700    (set_attr "mode"     "none")
1701    (set_attr "length"   "3")])
1702
1703 \f
1704 ;; Atomic operations
1705
1706 (define_expand "memory_barrier"
1707   [(set (mem:BLK (match_dup 0))
1708         (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MEMW))]
1709   ""
1710 {
1711   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (SImode));
1712   MEM_VOLATILE_P (operands[0]) = 1;
1713 })
1714
1715 (define_insn "*memory_barrier"
1716   [(set (match_operand:BLK 0 "" "")
1717         (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MEMW))]
1718   ""
1719   "memw"
1720   [(set_attr "type"     "unknown")
1721    (set_attr "mode"     "none")
1722    (set_attr "length"   "3")])
1723
1724 ;; sync_lock_release is only implemented for SImode.
1725 ;; For other modes, just use the default of a store with a memory_barrier.
1726 (define_insn "sync_lock_releasesi"
1727   [(set (match_operand:SI 0 "mem_operand" "=U")
1728         (unspec_volatile:SI
1729           [(match_operand:SI 1 "register_operand" "r")]
1730           UNSPECV_S32RI))]
1731   "TARGET_RELEASE_SYNC"
1732   "s32ri\t%1, %0"
1733   [(set_attr "type"     "store")
1734    (set_attr "mode"     "SI")
1735    (set_attr "length"   "3")])
1736
1737 (define_insn "sync_compare_and_swapsi"
1738   [(parallel
1739     [(set (match_operand:SI 0 "register_operand" "=a")
1740           (match_operand:SI 1 "mem_operand" "+U"))
1741      (set (match_dup 1)
1742           (unspec_volatile:SI
1743             [(match_dup 1)
1744              (match_operand:SI 2 "register_operand" "r")
1745              (match_operand:SI 3 "register_operand" "0")]
1746             UNSPECV_S32C1I))])]
1747   "TARGET_S32C1I"
1748   "wsr\t%2, SCOMPARE1\;s32c1i\t%3, %1"
1749   [(set_attr "type"     "multi")
1750    (set_attr "mode"     "SI")
1751    (set_attr "length"   "6")])
1752
1753 (define_expand "sync_compare_and_swap<mode>"
1754   [(parallel
1755     [(set (match_operand:HQI 0 "register_operand" "")
1756           (match_operand:HQI 1 "mem_operand" ""))
1757      (set (match_dup 1)
1758           (unspec_volatile:HQI
1759             [(match_dup 1)
1760              (match_operand:HQI 2 "register_operand" "")
1761              (match_operand:HQI 3 "register_operand" "")]
1762             UNSPECV_S32C1I))])]
1763   "TARGET_S32C1I"
1764 {
1765   xtensa_expand_compare_and_swap (operands[0], operands[1],
1766                                   operands[2], operands[3]);
1767   DONE;
1768 })
1769
1770 (define_expand "sync_lock_test_and_set<mode>"
1771   [(match_operand:HQI 0 "register_operand")
1772    (match_operand:HQI 1 "memory_operand")
1773    (match_operand:HQI 2 "register_operand")]
1774   "TARGET_S32C1I"
1775 {
1776   xtensa_expand_atomic (SET, operands[0], operands[1], operands[2], false);
1777   DONE;
1778 })
1779
1780 (define_expand "sync_<atomic><mode>"
1781   [(set (match_operand:HQI 0 "memory_operand")
1782         (ATOMIC:HQI (match_dup 0)
1783                     (match_operand:HQI 1 "register_operand")))]
1784   "TARGET_S32C1I"
1785 {
1786   xtensa_expand_atomic (<CODE>, NULL_RTX, operands[0], operands[1], false);
1787   DONE;
1788 })
1789
1790 (define_expand "sync_old_<atomic><mode>"
1791   [(set (match_operand:HQI 0 "register_operand")
1792         (match_operand:HQI 1 "memory_operand"))
1793    (set (match_dup 1)
1794         (ATOMIC:HQI (match_dup 1)
1795                     (match_operand:HQI 2 "register_operand")))]
1796   "TARGET_S32C1I"
1797 {
1798   xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], false);
1799   DONE;
1800 })
1801
1802 (define_expand "sync_new_<atomic><mode>"
1803   [(set (match_operand:HQI 0 "register_operand")
1804         (ATOMIC:HQI (match_operand:HQI 1 "memory_operand")
1805                     (match_operand:HQI 2 "register_operand")))
1806    (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))]
1807   "TARGET_S32C1I"
1808 {
1809   xtensa_expand_atomic (<CODE>, operands[0], operands[1], operands[2], true);
1810   DONE;
1811 })