gcc/doc/aarch64-acle-intrinsics.texi

   1 @c Copyright (C) 2014 Free Software Foundation, Inc.
   2 @c This is part of the GCC manual.
   3 @c For copying conditions, see the file gcc.texi.
   4
   5 @subsubsection CRC32 intrinsics
   6
   7 These intrinsics are available when the CRC32 architecture extension is
   8 specified, e.g. when the @option{-march=armv8-a+crc} switch is used, or when
   9 the target processor specified with @option{-mcpu} supports it.
  10
  11 @itemize @bullet
  12 @item uint32_t __crc32b (uint32_t, uint8_t)
  13 @*@emph{Form of expected instruction(s):} @code{crc32b @var{w0}, @var{w1}, @var{w2}}
  14 @end itemize
  15
  16
  17 @itemize @bullet
  18 @item uint32_t __crc32h (uint32_t, uint16_t)
  19 @*@emph{Form of expected instruction(s):} @code{crc32h @var{w0}, @var{w1}, @var{w2}}
  20 @end itemize
  21
  22
  23 @itemize @bullet
  24 @item uint32_t __crc32w (uint32_t, uint32_t)
  25 @*@emph{Form of expected instruction(s):} @code{crc32w @var{w0}, @var{w1}, @var{w2}}
  26 @end itemize
  27
  28
  29 @itemize @bullet
  30 @item uint32_t __crc32d (uint32_t, uint64_t)
  31 @*@emph{Form of expected instruction(s):} @code{crc32x @var{w0}, @var{w1}, @var{x2}}
  32 @end itemize
  33
  34 @itemize @bullet
  35 @item uint32_t __crc32cb (uint32_t, uint8_t)
  36 @*@emph{Form of expected instruction(s):} @code{crc32cb @var{w0}, @var{w1}, @var{w2}}
  37 @end itemize
  38
  39
  40 @itemize @bullet
  41 @item uint32_t __crc32ch (uint32_t, uint16_t)
  42 @*@emph{Form of expected instruction(s):} @code{crc32ch @var{w0}, @var{w1}, @var{w2}}
  43 @end itemize
  44
  45
  46 @itemize @bullet
  47 @item uint32_t __crc32cw (uint32_t, uint32_t)
  48 @*@emph{Form of expected instruction(s):} @code{crc32cw @var{w0}, @var{w1}, @var{w2}}
  49 @end itemize
  50
  51
  52 @itemize @bullet
  53 @item uint32_t __crc32cd (uint32_t, uint64_t)
  54 @*@emph{Form of expected instruction(s):} @code{crc32cx @var{w0}, @var{w1}, @var{x2}}
  55 @end itemize