gcc/doc/arm-neon-intrinsics.texi

   1 @c Copyright (C) 2006-2014 Free Software Foundation, Inc.
   2 @c This is part of the GCC manual.
   3 @c For copying conditions, see the file gcc.texi.
   4
   5 @c This file is generated automatically using gcc/config/arm/neon-docgen.ml
   6 @c Please do not edit manually.
   7 @subsubsection Addition
   8
   9 @itemize @bullet
  10 @item uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t)
  11 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
  12 @end itemize
  13
  14
  15 @itemize @bullet
  16 @item uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t)
  17 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
  18 @end itemize
  19
  20
  21 @itemize @bullet
  22 @item uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t)
  23 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
  24 @end itemize
  25
  26
  27 @itemize @bullet
  28 @item int32x2_t vadd_s32 (int32x2_t, int32x2_t)
  29 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
  30 @end itemize
  31
  32
  33 @itemize @bullet
  34 @item int16x4_t vadd_s16 (int16x4_t, int16x4_t)
  35 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
  36 @end itemize
  37
  38
  39 @itemize @bullet
  40 @item int8x8_t vadd_s8 (int8x8_t, int8x8_t)
  41 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
  42 @end itemize
  43
  44
  45 @itemize @bullet
  46 @item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
  47 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
  48 @end itemize
  49
  50
  51 @itemize @bullet
  52 @item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
  53 @end itemize
  54
  55
  56 @itemize @bullet
  57 @item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
  58 @end itemize
  59
  60
  61 @itemize @bullet
  62 @item uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t)
  63 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
  64 @end itemize
  65
  66
  67 @itemize @bullet
  68 @item uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t)
  69 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
  70 @end itemize
  71
  72
  73 @itemize @bullet
  74 @item uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t)
  75 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
  76 @end itemize
  77
  78
  79 @itemize @bullet
  80 @item int32x4_t vaddq_s32 (int32x4_t, int32x4_t)
  81 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
  82 @end itemize
  83
  84
  85 @itemize @bullet
  86 @item int16x8_t vaddq_s16 (int16x8_t, int16x8_t)
  87 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
  88 @end itemize
  89
  90
  91 @itemize @bullet
  92 @item int8x16_t vaddq_s8 (int8x16_t, int8x16_t)
  93 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
  94 @end itemize
  95
  96
  97 @itemize @bullet
  98 @item uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t)
  99 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
 100 @end itemize
 101
 102
 103 @itemize @bullet
 104 @item int64x2_t vaddq_s64 (int64x2_t, int64x2_t)
 105 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
 106 @end itemize
 107
 108
 109 @itemize @bullet
 110 @item float32x4_t vaddq_f32 (float32x4_t, float32x4_t)
 111 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{q0}, @var{q0}, @var{q0}}
 112 @end itemize
 113
 114
 115 @itemize @bullet
 116 @item uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t)
 117 @*@emph{Form of expected instruction(s):} @code{vaddl.u32 @var{q0}, @var{d0}, @var{d0}}
 118 @end itemize
 119
 120
 121 @itemize @bullet
 122 @item uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t)
 123 @*@emph{Form of expected instruction(s):} @code{vaddl.u16 @var{q0}, @var{d0}, @var{d0}}
 124 @end itemize
 125
 126
 127 @itemize @bullet
 128 @item uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t)
 129 @*@emph{Form of expected instruction(s):} @code{vaddl.u8 @var{q0}, @var{d0}, @var{d0}}
 130 @end itemize
 131
 132
 133 @itemize @bullet
 134 @item int64x2_t vaddl_s32 (int32x2_t, int32x2_t)
 135 @*@emph{Form of expected instruction(s):} @code{vaddl.s32 @var{q0}, @var{d0}, @var{d0}}
 136 @end itemize
 137
 138
 139 @itemize @bullet
 140 @item int32x4_t vaddl_s16 (int16x4_t, int16x4_t)
 141 @*@emph{Form of expected instruction(s):} @code{vaddl.s16 @var{q0}, @var{d0}, @var{d0}}
 142 @end itemize
 143
 144
 145 @itemize @bullet
 146 @item int16x8_t vaddl_s8 (int8x8_t, int8x8_t)
 147 @*@emph{Form of expected instruction(s):} @code{vaddl.s8 @var{q0}, @var{d0}, @var{d0}}
 148 @end itemize
 149
 150
 151 @itemize @bullet
 152 @item uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t)
 153 @*@emph{Form of expected instruction(s):} @code{vaddw.u32 @var{q0}, @var{q0}, @var{d0}}
 154 @end itemize
 155
 156
 157 @itemize @bullet
 158 @item uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t)
 159 @*@emph{Form of expected instruction(s):} @code{vaddw.u16 @var{q0}, @var{q0}, @var{d0}}
 160 @end itemize
 161
 162
 163 @itemize @bullet
 164 @item uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t)
 165 @*@emph{Form of expected instruction(s):} @code{vaddw.u8 @var{q0}, @var{q0}, @var{d0}}
 166 @end itemize
 167
 168
 169 @itemize @bullet
 170 @item int64x2_t vaddw_s32 (int64x2_t, int32x2_t)
 171 @*@emph{Form of expected instruction(s):} @code{vaddw.s32 @var{q0}, @var{q0}, @var{d0}}
 172 @end itemize
 173
 174
 175 @itemize @bullet
 176 @item int32x4_t vaddw_s16 (int32x4_t, int16x4_t)
 177 @*@emph{Form of expected instruction(s):} @code{vaddw.s16 @var{q0}, @var{q0}, @var{d0}}
 178 @end itemize
 179
 180
 181 @itemize @bullet
 182 @item int16x8_t vaddw_s8 (int16x8_t, int8x8_t)
 183 @*@emph{Form of expected instruction(s):} @code{vaddw.s8 @var{q0}, @var{q0}, @var{d0}}
 184 @end itemize
 185
 186
 187 @itemize @bullet
 188 @item uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t)
 189 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{d0}, @var{d0}, @var{d0}}
 190 @end itemize
 191
 192
 193 @itemize @bullet
 194 @item uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t)
 195 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{d0}, @var{d0}, @var{d0}}
 196 @end itemize
 197
 198
 199 @itemize @bullet
 200 @item uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t)
 201 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{d0}, @var{d0}, @var{d0}}
 202 @end itemize
 203
 204
 205 @itemize @bullet
 206 @item int32x2_t vhadd_s32 (int32x2_t, int32x2_t)
 207 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{d0}, @var{d0}, @var{d0}}
 208 @end itemize
 209
 210
 211 @itemize @bullet
 212 @item int16x4_t vhadd_s16 (int16x4_t, int16x4_t)
 213 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{d0}, @var{d0}, @var{d0}}
 214 @end itemize
 215
 216
 217 @itemize @bullet
 218 @item int8x8_t vhadd_s8 (int8x8_t, int8x8_t)
 219 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{d0}, @var{d0}, @var{d0}}
 220 @end itemize
 221
 222
 223 @itemize @bullet
 224 @item uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t)
 225 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{q0}, @var{q0}, @var{q0}}
 226 @end itemize
 227
 228
 229 @itemize @bullet
 230 @item uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t)
 231 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{q0}, @var{q0}, @var{q0}}
 232 @end itemize
 233
 234
 235 @itemize @bullet
 236 @item uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t)
 237 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{q0}, @var{q0}, @var{q0}}
 238 @end itemize
 239
 240
 241 @itemize @bullet
 242 @item int32x4_t vhaddq_s32 (int32x4_t, int32x4_t)
 243 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{q0}, @var{q0}, @var{q0}}
 244 @end itemize
 245
 246
 247 @itemize @bullet
 248 @item int16x8_t vhaddq_s16 (int16x8_t, int16x8_t)
 249 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{q0}, @var{q0}, @var{q0}}
 250 @end itemize
 251
 252
 253 @itemize @bullet
 254 @item int8x16_t vhaddq_s8 (int8x16_t, int8x16_t)
 255 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{q0}, @var{q0}, @var{q0}}
 256 @end itemize
 257
 258
 259 @itemize @bullet
 260 @item uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t)
 261 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{d0}, @var{d0}, @var{d0}}
 262 @end itemize
 263
 264
 265 @itemize @bullet
 266 @item uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t)
 267 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{d0}, @var{d0}, @var{d0}}
 268 @end itemize
 269
 270
 271 @itemize @bullet
 272 @item uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t)
 273 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{d0}, @var{d0}, @var{d0}}
 274 @end itemize
 275
 276
 277 @itemize @bullet
 278 @item int32x2_t vrhadd_s32 (int32x2_t, int32x2_t)
 279 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{d0}, @var{d0}, @var{d0}}
 280 @end itemize
 281
 282
 283 @itemize @bullet
 284 @item int16x4_t vrhadd_s16 (int16x4_t, int16x4_t)
 285 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{d0}, @var{d0}, @var{d0}}
 286 @end itemize
 287
 288
 289 @itemize @bullet
 290 @item int8x8_t vrhadd_s8 (int8x8_t, int8x8_t)
 291 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{d0}, @var{d0}, @var{d0}}
 292 @end itemize
 293
 294
 295 @itemize @bullet
 296 @item uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t)
 297 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{q0}, @var{q0}, @var{q0}}
 298 @end itemize
 299
 300
 301 @itemize @bullet
 302 @item uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t)
 303 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{q0}, @var{q0}, @var{q0}}
 304 @end itemize
 305
 306
 307 @itemize @bullet
 308 @item uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t)
 309 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{q0}, @var{q0}, @var{q0}}
 310 @end itemize
 311
 312
 313 @itemize @bullet
 314 @item int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t)
 315 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{q0}, @var{q0}, @var{q0}}
 316 @end itemize
 317
 318
 319 @itemize @bullet
 320 @item int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t)
 321 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{q0}, @var{q0}, @var{q0}}
 322 @end itemize
 323
 324
 325 @itemize @bullet
 326 @item int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t)
 327 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{q0}, @var{q0}, @var{q0}}
 328 @end itemize
 329
 330
 331 @itemize @bullet
 332 @item uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t)
 333 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{d0}, @var{d0}, @var{d0}}
 334 @end itemize
 335
 336
 337 @itemize @bullet
 338 @item uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t)
 339 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{d0}, @var{d0}, @var{d0}}
 340 @end itemize
 341
 342
 343 @itemize @bullet
 344 @item uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t)
 345 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{d0}, @var{d0}, @var{d0}}
 346 @end itemize
 347
 348
 349 @itemize @bullet
 350 @item int32x2_t vqadd_s32 (int32x2_t, int32x2_t)
 351 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{d0}, @var{d0}, @var{d0}}
 352 @end itemize
 353
 354
 355 @itemize @bullet
 356 @item int16x4_t vqadd_s16 (int16x4_t, int16x4_t)
 357 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{d0}, @var{d0}, @var{d0}}
 358 @end itemize
 359
 360
 361 @itemize @bullet
 362 @item int8x8_t vqadd_s8 (int8x8_t, int8x8_t)
 363 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{d0}, @var{d0}, @var{d0}}
 364 @end itemize
 365
 366
 367 @itemize @bullet
 368 @item uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t)
 369 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{d0}, @var{d0}, @var{d0}}
 370 @end itemize
 371
 372
 373 @itemize @bullet
 374 @item int64x1_t vqadd_s64 (int64x1_t, int64x1_t)
 375 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{d0}, @var{d0}, @var{d0}}
 376 @end itemize
 377
 378
 379 @itemize @bullet
 380 @item uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t)
 381 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{q0}, @var{q0}, @var{q0}}
 382 @end itemize
 383
 384
 385 @itemize @bullet
 386 @item uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t)
 387 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{q0}, @var{q0}, @var{q0}}
 388 @end itemize
 389
 390
 391 @itemize @bullet
 392 @item uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t)
 393 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{q0}, @var{q0}, @var{q0}}
 394 @end itemize
 395
 396
 397 @itemize @bullet
 398 @item int32x4_t vqaddq_s32 (int32x4_t, int32x4_t)
 399 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{q0}, @var{q0}, @var{q0}}
 400 @end itemize
 401
 402
 403 @itemize @bullet
 404 @item int16x8_t vqaddq_s16 (int16x8_t, int16x8_t)
 405 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{q0}, @var{q0}, @var{q0}}
 406 @end itemize
 407
 408
 409 @itemize @bullet
 410 @item int8x16_t vqaddq_s8 (int8x16_t, int8x16_t)
 411 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{q0}, @var{q0}, @var{q0}}
 412 @end itemize
 413
 414
 415 @itemize @bullet
 416 @item uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t)
 417 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{q0}, @var{q0}, @var{q0}}
 418 @end itemize
 419
 420
 421 @itemize @bullet
 422 @item int64x2_t vqaddq_s64 (int64x2_t, int64x2_t)
 423 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{q0}, @var{q0}, @var{q0}}
 424 @end itemize
 425
 426
 427 @itemize @bullet
 428 @item uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t)
 429 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 430 @end itemize
 431
 432
 433 @itemize @bullet
 434 @item uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t)
 435 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 436 @end itemize
 437
 438
 439 @itemize @bullet
 440 @item uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t)
 441 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 442 @end itemize
 443
 444
 445 @itemize @bullet
 446 @item int32x2_t vaddhn_s64 (int64x2_t, int64x2_t)
 447 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 448 @end itemize
 449
 450
 451 @itemize @bullet
 452 @item int16x4_t vaddhn_s32 (int32x4_t, int32x4_t)
 453 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 454 @end itemize
 455
 456
 457 @itemize @bullet
 458 @item int8x8_t vaddhn_s16 (int16x8_t, int16x8_t)
 459 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 460 @end itemize
 461
 462
 463 @itemize @bullet
 464 @item uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t)
 465 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 466 @end itemize
 467
 468
 469 @itemize @bullet
 470 @item uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t)
 471 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 472 @end itemize
 473
 474
 475 @itemize @bullet
 476 @item uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t)
 477 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 478 @end itemize
 479
 480
 481 @itemize @bullet
 482 @item int32x2_t vraddhn_s64 (int64x2_t, int64x2_t)
 483 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
 484 @end itemize
 485
 486
 487 @itemize @bullet
 488 @item int16x4_t vraddhn_s32 (int32x4_t, int32x4_t)
 489 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
 490 @end itemize
 491
 492
 493 @itemize @bullet
 494 @item int8x8_t vraddhn_s16 (int16x8_t, int16x8_t)
 495 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
 496 @end itemize
 497
 498
 499
 500
 501 @subsubsection Multiplication
 502
 503 @itemize @bullet
 504 @item uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t)
 505 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
 506 @end itemize
 507
 508
 509 @itemize @bullet
 510 @item uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t)
 511 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
 512 @end itemize
 513
 514
 515 @itemize @bullet
 516 @item uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t)
 517 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
 518 @end itemize
 519
 520
 521 @itemize @bullet
 522 @item int32x2_t vmul_s32 (int32x2_t, int32x2_t)
 523 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
 524 @end itemize
 525
 526
 527 @itemize @bullet
 528 @item int16x4_t vmul_s16 (int16x4_t, int16x4_t)
 529 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
 530 @end itemize
 531
 532
 533 @itemize @bullet
 534 @item int8x8_t vmul_s8 (int8x8_t, int8x8_t)
 535 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
 536 @end itemize
 537
 538
 539 @itemize @bullet
 540 @item float32x2_t vmul_f32 (float32x2_t, float32x2_t)
 541 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}}
 542 @end itemize
 543
 544
 545 @itemize @bullet
 546 @item poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t)
 547 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{d0}, @var{d0}, @var{d0}}
 548 @end itemize
 549
 550
 551 @itemize @bullet
 552 @item uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t)
 553 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
 554 @end itemize
 555
 556
 557 @itemize @bullet
 558 @item uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t)
 559 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
 560 @end itemize
 561
 562
 563 @itemize @bullet
 564 @item uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t)
 565 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
 566 @end itemize
 567
 568
 569 @itemize @bullet
 570 @item int32x4_t vmulq_s32 (int32x4_t, int32x4_t)
 571 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
 572 @end itemize
 573
 574
 575 @itemize @bullet
 576 @item int16x8_t vmulq_s16 (int16x8_t, int16x8_t)
 577 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
 578 @end itemize
 579
 580
 581 @itemize @bullet
 582 @item int8x16_t vmulq_s8 (int8x16_t, int8x16_t)
 583 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
 584 @end itemize
 585
 586
 587 @itemize @bullet
 588 @item float32x4_t vmulq_f32 (float32x4_t, float32x4_t)
 589 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{q0}}
 590 @end itemize
 591
 592
 593 @itemize @bullet
 594 @item poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t)
 595 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{q0}, @var{q0}, @var{q0}}
 596 @end itemize
 597
 598
 599 @itemize @bullet
 600 @item int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t)
 601 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
 602 @end itemize
 603
 604
 605 @itemize @bullet
 606 @item int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t)
 607 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
 608 @end itemize
 609
 610
 611 @itemize @bullet
 612 @item int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t)
 613 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
 614 @end itemize
 615
 616
 617 @itemize @bullet
 618 @item int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t)
 619 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
 620 @end itemize
 621
 622
 623 @itemize @bullet
 624 @item int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t)
 625 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
 626 @end itemize
 627
 628
 629 @itemize @bullet
 630 @item int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t)
 631 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
 632 @end itemize
 633
 634
 635 @itemize @bullet
 636 @item int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t)
 637 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
 638 @end itemize
 639
 640
 641 @itemize @bullet
 642 @item int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t)
 643 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
 644 @end itemize
 645
 646
 647 @itemize @bullet
 648 @item uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t)
 649 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}}
 650 @end itemize
 651
 652
 653 @itemize @bullet
 654 @item uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t)
 655 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}}
 656 @end itemize
 657
 658
 659 @itemize @bullet
 660 @item uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t)
 661 @*@emph{Form of expected instruction(s):} @code{vmull.u8 @var{q0}, @var{d0}, @var{d0}}
 662 @end itemize
 663
 664
 665 @itemize @bullet
 666 @item int64x2_t vmull_s32 (int32x2_t, int32x2_t)
 667 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}}
 668 @end itemize
 669
 670
 671 @itemize @bullet
 672 @item int32x4_t vmull_s16 (int16x4_t, int16x4_t)
 673 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}}
 674 @end itemize
 675
 676
 677 @itemize @bullet
 678 @item int16x8_t vmull_s8 (int8x8_t, int8x8_t)
 679 @*@emph{Form of expected instruction(s):} @code{vmull.s8 @var{q0}, @var{d0}, @var{d0}}
 680 @end itemize
 681
 682
 683 @itemize @bullet
 684 @item poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t)
 685 @*@emph{Form of expected instruction(s):} @code{vmull.p8 @var{q0}, @var{d0}, @var{d0}}
 686 @end itemize
 687
 688
 689 @itemize @bullet
 690 @item int64x2_t vqdmull_s32 (int32x2_t, int32x2_t)
 691 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}}
 692 @end itemize
 693
 694
 695 @itemize @bullet
 696 @item int32x4_t vqdmull_s16 (int16x4_t, int16x4_t)
 697 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}}
 698 @end itemize
 699
 700
 701
 702
 703 @subsubsection Multiply-accumulate
 704
 705 @itemize @bullet
 706 @item uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 707 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
 708 @end itemize
 709
 710
 711 @itemize @bullet
 712 @item uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 713 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
 714 @end itemize
 715
 716
 717 @itemize @bullet
 718 @item uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 719 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
 720 @end itemize
 721
 722
 723 @itemize @bullet
 724 @item int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t)
 725 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
 726 @end itemize
 727
 728
 729 @itemize @bullet
 730 @item int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t)
 731 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
 732 @end itemize
 733
 734
 735 @itemize @bullet
 736 @item int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t)
 737 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
 738 @end itemize
 739
 740
 741 @itemize @bullet
 742 @item float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t)
 743 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}}
 744 @end itemize
 745
 746
 747 @itemize @bullet
 748 @item uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 749 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
 750 @end itemize
 751
 752
 753 @itemize @bullet
 754 @item uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 755 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
 756 @end itemize
 757
 758
 759 @itemize @bullet
 760 @item uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 761 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
 762 @end itemize
 763
 764
 765 @itemize @bullet
 766 @item int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t)
 767 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
 768 @end itemize
 769
 770
 771 @itemize @bullet
 772 @item int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t)
 773 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
 774 @end itemize
 775
 776
 777 @itemize @bullet
 778 @item int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t)
 779 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
 780 @end itemize
 781
 782
 783 @itemize @bullet
 784 @item float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t)
 785 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{q0}}
 786 @end itemize
 787
 788
 789 @itemize @bullet
 790 @item uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
 791 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}}
 792 @end itemize
 793
 794
 795 @itemize @bullet
 796 @item uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
 797 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}}
 798 @end itemize
 799
 800
 801 @itemize @bullet
 802 @item uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
 803 @*@emph{Form of expected instruction(s):} @code{vmlal.u8 @var{q0}, @var{d0}, @var{d0}}
 804 @end itemize
 805
 806
 807 @itemize @bullet
 808 @item int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
 809 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}}
 810 @end itemize
 811
 812
 813 @itemize @bullet
 814 @item int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
 815 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}}
 816 @end itemize
 817
 818
 819 @itemize @bullet
 820 @item int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t)
 821 @*@emph{Form of expected instruction(s):} @code{vmlal.s8 @var{q0}, @var{d0}, @var{d0}}
 822 @end itemize
 823
 824
 825 @itemize @bullet
 826 @item int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
 827 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}}
 828 @end itemize
 829
 830
 831 @itemize @bullet
 832 @item int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
 833 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}}
 834 @end itemize
 835
 836
 837
 838
 839 @subsubsection Multiply-subtract
 840
 841 @itemize @bullet
 842 @item uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
 843 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
 844 @end itemize
 845
 846
 847 @itemize @bullet
 848 @item uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
 849 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
 850 @end itemize
 851
 852
 853 @itemize @bullet
 854 @item uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
 855 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
 856 @end itemize
 857
 858
 859 @itemize @bullet
 860 @item int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t)
 861 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
 862 @end itemize
 863
 864
 865 @itemize @bullet
 866 @item int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t)
 867 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
 868 @end itemize
 869
 870
 871 @itemize @bullet
 872 @item int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t)
 873 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
 874 @end itemize
 875
 876
 877 @itemize @bullet
 878 @item float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t)
 879 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}}
 880 @end itemize
 881
 882
 883 @itemize @bullet
 884 @item uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
 885 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
 886 @end itemize
 887
 888
 889 @itemize @bullet
 890 @item uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
 891 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
 892 @end itemize
 893
 894
 895 @itemize @bullet
 896 @item uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
 897 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
 898 @end itemize
 899
 900
 901 @itemize @bullet
 902 @item int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t)
 903 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
 904 @end itemize
 905
 906
 907 @itemize @bullet
 908 @item int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t)
 909 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
 910 @end itemize
 911
 912
 913 @itemize @bullet
 914 @item int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t)
 915 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
 916 @end itemize
 917
 918
 919 @itemize @bullet
 920 @item float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t)
 921 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{q0}}
 922 @end itemize
 923
 924
 925 @itemize @bullet
 926 @item uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
 927 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}}
 928 @end itemize
 929
 930
 931 @itemize @bullet
 932 @item uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
 933 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}}
 934 @end itemize
 935
 936
 937 @itemize @bullet
 938 @item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
 939 @*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}}
 940 @end itemize
 941
 942
 943 @itemize @bullet
 944 @item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
 945 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
 946 @end itemize
 947
 948
 949 @itemize @bullet
 950 @item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
 951 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
 952 @end itemize
 953
 954
 955 @itemize @bullet
 956 @item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
 957 @*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}}
 958 @end itemize
 959
 960
 961 @itemize @bullet
 962 @item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
 963 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
 964 @end itemize
 965
 966
 967 @itemize @bullet
 968 @item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
 969 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
 970 @end itemize
 971
 972
 973
 974
 975 @subsubsection Fused-multiply-accumulate
 976
 977 @itemize @bullet
 978 @item float32x2_t vfma_f32 (float32x2_t, float32x2_t, float32x2_t)
 979 @*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{d0}, @var{d0}, @var{d0}}
 980 @end itemize
 981
 982
 983 @itemize @bullet
 984 @item float32x4_t vfmaq_f32 (float32x4_t, float32x4_t, float32x4_t)
 985 @*@emph{Form of expected instruction(s):} @code{vfma.f32 @var{q0}, @var{q0}, @var{q0}}
 986 @end itemize
 987
 988
 989
 990
 991 @subsubsection Fused-multiply-subtract
 992
 993 @itemize @bullet
 994 @item float32x2_t vfms_f32 (float32x2_t, float32x2_t, float32x2_t)
 995 @*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{d0}, @var{d0}, @var{d0}}
 996 @end itemize
 997
 998
 999 @itemize @bullet
1000 @item float32x4_t vfmsq_f32 (float32x4_t, float32x4_t, float32x4_t)
1001 @*@emph{Form of expected instruction(s):} @code{vfms.f32 @var{q0}, @var{q0}, @var{q0}}
1002 @end itemize
1003
1004
1005
1006
1007 @subsubsection Round to integral (to nearest, ties to even)
1008
1009 @itemize @bullet
1010 @item float32x2_t vrndn_f32 (float32x2_t)
1011 @*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{d0}, @var{d0}}
1012 @end itemize
1013
1014
1015 @itemize @bullet
1016 @item float32x4_t vrndqn_f32 (float32x4_t)
1017 @*@emph{Form of expected instruction(s):} @code{vrintn.f32 @var{q0}, @var{q0}}
1018 @end itemize
1019
1020
1021
1022
1023 @subsubsection Round to integral (to nearest, ties away from zero)
1024
1025 @itemize @bullet
1026 @item float32x2_t vrnda_f32 (float32x2_t)
1027 @*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{d0}, @var{d0}}
1028 @end itemize
1029
1030
1031 @itemize @bullet
1032 @item float32x4_t vrndqa_f32 (float32x4_t)
1033 @*@emph{Form of expected instruction(s):} @code{vrinta.f32 @var{q0}, @var{q0}}
1034 @end itemize
1035
1036
1037
1038
1039 @subsubsection Round to integral (towards +Inf)
1040
1041 @itemize @bullet
1042 @item float32x2_t vrndp_f32 (float32x2_t)
1043 @*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{d0}, @var{d0}}
1044 @end itemize
1045
1046
1047 @itemize @bullet
1048 @item float32x4_t vrndqp_f32 (float32x4_t)
1049 @*@emph{Form of expected instruction(s):} @code{vrintp.f32 @var{q0}, @var{q0}}
1050 @end itemize
1051
1052
1053
1054
1055 @subsubsection Round to integral (towards -Inf)
1056
1057 @itemize @bullet
1058 @item float32x2_t vrndm_f32 (float32x2_t)
1059 @*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{d0}, @var{d0}}
1060 @end itemize
1061
1062
1063 @itemize @bullet
1064 @item float32x4_t vrndqm_f32 (float32x4_t)
1065 @*@emph{Form of expected instruction(s):} @code{vrintm.f32 @var{q0}, @var{q0}}
1066 @end itemize
1067
1068
1069
1070
1071 @subsubsection Round to integral (towards 0)
1072
1073 @itemize @bullet
1074 @item float32x2_t vrnd_f32 (float32x2_t)
1075 @*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{d0}, @var{d0}}
1076 @end itemize
1077
1078
1079 @itemize @bullet
1080 @item float32x4_t vrndq_f32 (float32x4_t)
1081 @*@emph{Form of expected instruction(s):} @code{vrintz.f32 @var{q0}, @var{q0}}
1082 @end itemize
1083
1084
1085
1086
1087 @subsubsection Subtraction
1088
1089 @itemize @bullet
1090 @item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
1091 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
1092 @end itemize
1093
1094
1095 @itemize @bullet
1096 @item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
1097 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1098 @end itemize
1099
1100
1101 @itemize @bullet
1102 @item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
1103 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1104 @end itemize
1105
1106
1107 @itemize @bullet
1108 @item int32x2_t vsub_s32 (int32x2_t, int32x2_t)
1109 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
1110 @end itemize
1111
1112
1113 @itemize @bullet
1114 @item int16x4_t vsub_s16 (int16x4_t, int16x4_t)
1115 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1116 @end itemize
1117
1118
1119 @itemize @bullet
1120 @item int8x8_t vsub_s8 (int8x8_t, int8x8_t)
1121 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1122 @end itemize
1123
1124
1125 @itemize @bullet
1126 @item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
1127 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
1128 @end itemize
1129
1130
1131 @itemize @bullet
1132 @item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
1133 @end itemize
1134
1135
1136 @itemize @bullet
1137 @item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
1138 @end itemize
1139
1140
1141 @itemize @bullet
1142 @item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
1143 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1144 @end itemize
1145
1146
1147 @itemize @bullet
1148 @item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
1149 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1150 @end itemize
1151
1152
1153 @itemize @bullet
1154 @item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
1155 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1156 @end itemize
1157
1158
1159 @itemize @bullet
1160 @item int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
1161 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1162 @end itemize
1163
1164
1165 @itemize @bullet
1166 @item int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
1167 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1168 @end itemize
1169
1170
1171 @itemize @bullet
1172 @item int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
1173 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1174 @end itemize
1175
1176
1177 @itemize @bullet
1178 @item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
1179 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1180 @end itemize
1181
1182
1183 @itemize @bullet
1184 @item int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
1185 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1186 @end itemize
1187
1188
1189 @itemize @bullet
1190 @item float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
1191 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}}
1192 @end itemize
1193
1194
1195 @itemize @bullet
1196 @item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
1197 @*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}}
1198 @end itemize
1199
1200
1201 @itemize @bullet
1202 @item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
1203 @*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}}
1204 @end itemize
1205
1206
1207 @itemize @bullet
1208 @item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
1209 @*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}}
1210 @end itemize
1211
1212
1213 @itemize @bullet
1214 @item int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
1215 @*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}}
1216 @end itemize
1217
1218
1219 @itemize @bullet
1220 @item int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
1221 @*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}}
1222 @end itemize
1223
1224
1225 @itemize @bullet
1226 @item int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
1227 @*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}}
1228 @end itemize
1229
1230
1231 @itemize @bullet
1232 @item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
1233 @*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}}
1234 @end itemize
1235
1236
1237 @itemize @bullet
1238 @item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
1239 @*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}}
1240 @end itemize
1241
1242
1243 @itemize @bullet
1244 @item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
1245 @*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}}
1246 @end itemize
1247
1248
1249 @itemize @bullet
1250 @item int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
1251 @*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}}
1252 @end itemize
1253
1254
1255 @itemize @bullet
1256 @item int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
1257 @*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}}
1258 @end itemize
1259
1260
1261 @itemize @bullet
1262 @item int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
1263 @*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}}
1264 @end itemize
1265
1266
1267 @itemize @bullet
1268 @item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
1269 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}}
1270 @end itemize
1271
1272
1273 @itemize @bullet
1274 @item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
1275 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}}
1276 @end itemize
1277
1278
1279 @itemize @bullet
1280 @item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
1281 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}}
1282 @end itemize
1283
1284
1285 @itemize @bullet
1286 @item int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
1287 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}}
1288 @end itemize
1289
1290
1291 @itemize @bullet
1292 @item int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
1293 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}}
1294 @end itemize
1295
1296
1297 @itemize @bullet
1298 @item int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
1299 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}}
1300 @end itemize
1301
1302
1303 @itemize @bullet
1304 @item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
1305 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}}
1306 @end itemize
1307
1308
1309 @itemize @bullet
1310 @item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
1311 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}}
1312 @end itemize
1313
1314
1315 @itemize @bullet
1316 @item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
1317 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}}
1318 @end itemize
1319
1320
1321 @itemize @bullet
1322 @item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
1323 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}}
1324 @end itemize
1325
1326
1327 @itemize @bullet
1328 @item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
1329 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}}
1330 @end itemize
1331
1332
1333 @itemize @bullet
1334 @item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
1335 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}}
1336 @end itemize
1337
1338
1339 @itemize @bullet
1340 @item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
1341 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}}
1342 @end itemize
1343
1344
1345 @itemize @bullet
1346 @item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
1347 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}}
1348 @end itemize
1349
1350
1351 @itemize @bullet
1352 @item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
1353 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}}
1354 @end itemize
1355
1356
1357 @itemize @bullet
1358 @item int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
1359 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}}
1360 @end itemize
1361
1362
1363 @itemize @bullet
1364 @item int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
1365 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}}
1366 @end itemize
1367
1368
1369 @itemize @bullet
1370 @item int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
1371 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}}
1372 @end itemize
1373
1374
1375 @itemize @bullet
1376 @item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
1377 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}}
1378 @end itemize
1379
1380
1381 @itemize @bullet
1382 @item int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
1383 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}}
1384 @end itemize
1385
1386
1387 @itemize @bullet
1388 @item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
1389 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}}
1390 @end itemize
1391
1392
1393 @itemize @bullet
1394 @item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
1395 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}}
1396 @end itemize
1397
1398
1399 @itemize @bullet
1400 @item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
1401 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}}
1402 @end itemize
1403
1404
1405 @itemize @bullet
1406 @item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
1407 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}}
1408 @end itemize
1409
1410
1411 @itemize @bullet
1412 @item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
1413 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}}
1414 @end itemize
1415
1416
1417 @itemize @bullet
1418 @item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
1419 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}}
1420 @end itemize
1421
1422
1423 @itemize @bullet
1424 @item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
1425 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}}
1426 @end itemize
1427
1428
1429 @itemize @bullet
1430 @item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
1431 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}}
1432 @end itemize
1433
1434
1435 @itemize @bullet
1436 @item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
1437 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1438 @end itemize
1439
1440
1441 @itemize @bullet
1442 @item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
1443 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1444 @end itemize
1445
1446
1447 @itemize @bullet
1448 @item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
1449 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1450 @end itemize
1451
1452
1453 @itemize @bullet
1454 @item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
1455 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1456 @end itemize
1457
1458
1459 @itemize @bullet
1460 @item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
1461 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1462 @end itemize
1463
1464
1465 @itemize @bullet
1466 @item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
1467 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1468 @end itemize
1469
1470
1471 @itemize @bullet
1472 @item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
1473 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1474 @end itemize
1475
1476
1477 @itemize @bullet
1478 @item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
1479 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1480 @end itemize
1481
1482
1483 @itemize @bullet
1484 @item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
1485 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1486 @end itemize
1487
1488
1489 @itemize @bullet
1490 @item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
1491 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1492 @end itemize
1493
1494
1495 @itemize @bullet
1496 @item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
1497 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1498 @end itemize
1499
1500
1501 @itemize @bullet
1502 @item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
1503 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1504 @end itemize
1505
1506
1507
1508
1509 @subsubsection Comparison (equal-to)
1510
1511 @itemize @bullet
1512 @item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)
1513 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1514 @end itemize
1515
1516
1517 @itemize @bullet
1518 @item uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t)
1519 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1520 @end itemize
1521
1522
1523 @itemize @bullet
1524 @item uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t)
1525 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1526 @end itemize
1527
1528
1529 @itemize @bullet
1530 @item uint32x2_t vceq_s32 (int32x2_t, int32x2_t)
1531 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1532 @end itemize
1533
1534
1535 @itemize @bullet
1536 @item uint16x4_t vceq_s16 (int16x4_t, int16x4_t)
1537 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1538 @end itemize
1539
1540
1541 @itemize @bullet
1542 @item uint8x8_t vceq_s8 (int8x8_t, int8x8_t)
1543 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1544 @end itemize
1545
1546
1547 @itemize @bullet
1548 @item uint32x2_t vceq_f32 (float32x2_t, float32x2_t)
1549 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{d0}, @var{d0}, @var{d0}}
1550 @end itemize
1551
1552
1553 @itemize @bullet
1554 @item uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t)
1555 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1556 @end itemize
1557
1558
1559 @itemize @bullet
1560 @item uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t)
1561 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1562 @end itemize
1563
1564
1565 @itemize @bullet
1566 @item uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t)
1567 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1568 @end itemize
1569
1570
1571 @itemize @bullet
1572 @item uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t)
1573 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1574 @end itemize
1575
1576
1577 @itemize @bullet
1578 @item uint32x4_t vceqq_s32 (int32x4_t, int32x4_t)
1579 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1580 @end itemize
1581
1582
1583 @itemize @bullet
1584 @item uint16x8_t vceqq_s16 (int16x8_t, int16x8_t)
1585 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1586 @end itemize
1587
1588
1589 @itemize @bullet
1590 @item uint8x16_t vceqq_s8 (int8x16_t, int8x16_t)
1591 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1592 @end itemize
1593
1594
1595 @itemize @bullet
1596 @item uint32x4_t vceqq_f32 (float32x4_t, float32x4_t)
1597 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{q0}, @var{q0}, @var{q0}}
1598 @end itemize
1599
1600
1601 @itemize @bullet
1602 @item uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t)
1603 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1604 @end itemize
1605
1606
1607
1608
1609 @subsubsection Comparison (greater-than-or-equal-to)
1610
1611 @itemize @bullet
1612 @item uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
1613 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1614 @end itemize
1615
1616
1617 @itemize @bullet
1618 @item uint16x4_t vcge_s16 (int16x4_t, int16x4_t)
1619 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1620 @end itemize
1621
1622
1623 @itemize @bullet
1624 @item uint8x8_t vcge_s8 (int8x8_t, int8x8_t)
1625 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1626 @end itemize
1627
1628
1629 @itemize @bullet
1630 @item uint32x2_t vcge_f32 (float32x2_t, float32x2_t)
1631 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1632 @end itemize
1633
1634
1635 @itemize @bullet
1636 @item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
1637 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1638 @end itemize
1639
1640
1641 @itemize @bullet
1642 @item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
1643 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1644 @end itemize
1645
1646
1647 @itemize @bullet
1648 @item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
1649 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1650 @end itemize
1651
1652
1653 @itemize @bullet
1654 @item uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t)
1655 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1656 @end itemize
1657
1658
1659 @itemize @bullet
1660 @item uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t)
1661 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1662 @end itemize
1663
1664
1665 @itemize @bullet
1666 @item uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t)
1667 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1668 @end itemize
1669
1670
1671 @itemize @bullet
1672 @item uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t)
1673 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1674 @end itemize
1675
1676
1677 @itemize @bullet
1678 @item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
1679 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1680 @end itemize
1681
1682
1683 @itemize @bullet
1684 @item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
1685 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1686 @end itemize
1687
1688
1689 @itemize @bullet
1690 @item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
1691 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1692 @end itemize
1693
1694
1695
1696
1697 @subsubsection Comparison (less-than-or-equal-to)
1698
1699 @itemize @bullet
1700 @item uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
1701 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1702 @end itemize
1703
1704
1705 @itemize @bullet
1706 @item uint16x4_t vcle_s16 (int16x4_t, int16x4_t)
1707 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1708 @end itemize
1709
1710
1711 @itemize @bullet
1712 @item uint8x8_t vcle_s8 (int8x8_t, int8x8_t)
1713 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1714 @end itemize
1715
1716
1717 @itemize @bullet
1718 @item uint32x2_t vcle_f32 (float32x2_t, float32x2_t)
1719 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1720 @end itemize
1721
1722
1723 @itemize @bullet
1724 @item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
1725 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1726 @end itemize
1727
1728
1729 @itemize @bullet
1730 @item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
1731 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1732 @end itemize
1733
1734
1735 @itemize @bullet
1736 @item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
1737 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1738 @end itemize
1739
1740
1741 @itemize @bullet
1742 @item uint32x4_t vcleq_s32 (int32x4_t, int32x4_t)
1743 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1744 @end itemize
1745
1746
1747 @itemize @bullet
1748 @item uint16x8_t vcleq_s16 (int16x8_t, int16x8_t)
1749 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1750 @end itemize
1751
1752
1753 @itemize @bullet
1754 @item uint8x16_t vcleq_s8 (int8x16_t, int8x16_t)
1755 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1756 @end itemize
1757
1758
1759 @itemize @bullet
1760 @item uint32x4_t vcleq_f32 (float32x4_t, float32x4_t)
1761 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1762 @end itemize
1763
1764
1765 @itemize @bullet
1766 @item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
1767 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1768 @end itemize
1769
1770
1771 @itemize @bullet
1772 @item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
1773 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1774 @end itemize
1775
1776
1777 @itemize @bullet
1778 @item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
1779 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1780 @end itemize
1781
1782
1783
1784
1785 @subsubsection Comparison (greater-than)
1786
1787 @itemize @bullet
1788 @item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
1789 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1790 @end itemize
1791
1792
1793 @itemize @bullet
1794 @item uint16x4_t vcgt_s16 (int16x4_t, int16x4_t)
1795 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1796 @end itemize
1797
1798
1799 @itemize @bullet
1800 @item uint8x8_t vcgt_s8 (int8x8_t, int8x8_t)
1801 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1802 @end itemize
1803
1804
1805 @itemize @bullet
1806 @item uint32x2_t vcgt_f32 (float32x2_t, float32x2_t)
1807 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1808 @end itemize
1809
1810
1811 @itemize @bullet
1812 @item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
1813 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1814 @end itemize
1815
1816
1817 @itemize @bullet
1818 @item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
1819 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1820 @end itemize
1821
1822
1823 @itemize @bullet
1824 @item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
1825 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1826 @end itemize
1827
1828
1829 @itemize @bullet
1830 @item uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t)
1831 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1832 @end itemize
1833
1834
1835 @itemize @bullet
1836 @item uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t)
1837 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1838 @end itemize
1839
1840
1841 @itemize @bullet
1842 @item uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t)
1843 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1844 @end itemize
1845
1846
1847 @itemize @bullet
1848 @item uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t)
1849 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1850 @end itemize
1851
1852
1853 @itemize @bullet
1854 @item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
1855 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1856 @end itemize
1857
1858
1859 @itemize @bullet
1860 @item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
1861 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1862 @end itemize
1863
1864
1865 @itemize @bullet
1866 @item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
1867 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1868 @end itemize
1869
1870
1871
1872
1873 @subsubsection Comparison (less-than)
1874
1875 @itemize @bullet
1876 @item uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
1877 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1878 @end itemize
1879
1880
1881 @itemize @bullet
1882 @item uint16x4_t vclt_s16 (int16x4_t, int16x4_t)
1883 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1884 @end itemize
1885
1886
1887 @itemize @bullet
1888 @item uint8x8_t vclt_s8 (int8x8_t, int8x8_t)
1889 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1890 @end itemize
1891
1892
1893 @itemize @bullet
1894 @item uint32x2_t vclt_f32 (float32x2_t, float32x2_t)
1895 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1896 @end itemize
1897
1898
1899 @itemize @bullet
1900 @item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
1901 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1902 @end itemize
1903
1904
1905 @itemize @bullet
1906 @item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
1907 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1908 @end itemize
1909
1910
1911 @itemize @bullet
1912 @item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
1913 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1914 @end itemize
1915
1916
1917 @itemize @bullet
1918 @item uint32x4_t vcltq_s32 (int32x4_t, int32x4_t)
1919 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1920 @end itemize
1921
1922
1923 @itemize @bullet
1924 @item uint16x8_t vcltq_s16 (int16x8_t, int16x8_t)
1925 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1926 @end itemize
1927
1928
1929 @itemize @bullet
1930 @item uint8x16_t vcltq_s8 (int8x16_t, int8x16_t)
1931 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1932 @end itemize
1933
1934
1935 @itemize @bullet
1936 @item uint32x4_t vcltq_f32 (float32x4_t, float32x4_t)
1937 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1938 @end itemize
1939
1940
1941 @itemize @bullet
1942 @item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
1943 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1944 @end itemize
1945
1946
1947 @itemize @bullet
1948 @item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
1949 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1950 @end itemize
1951
1952
1953 @itemize @bullet
1954 @item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
1955 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1956 @end itemize
1957
1958
1959
1960
1961 @subsubsection Comparison (absolute greater-than-or-equal-to)
1962
1963 @itemize @bullet
1964 @item uint32x2_t vcage_f32 (float32x2_t, float32x2_t)
1965 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1966 @end itemize
1967
1968
1969 @itemize @bullet
1970 @item uint32x4_t vcageq_f32 (float32x4_t, float32x4_t)
1971 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1972 @end itemize
1973
1974
1975
1976
1977 @subsubsection Comparison (absolute less-than-or-equal-to)
1978
1979 @itemize @bullet
1980 @item uint32x2_t vcale_f32 (float32x2_t, float32x2_t)
1981 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1982 @end itemize
1983
1984
1985 @itemize @bullet
1986 @item uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t)
1987 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1988 @end itemize
1989
1990
1991
1992
1993 @subsubsection Comparison (absolute greater-than)
1994
1995 @itemize @bullet
1996 @item uint32x2_t vcagt_f32 (float32x2_t, float32x2_t)
1997 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1998 @end itemize
1999
2000
2001 @itemize @bullet
2002 @item uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t)
2003 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
2004 @end itemize
2005
2006
2007
2008
2009 @subsubsection Comparison (absolute less-than)
2010
2011 @itemize @bullet
2012 @item uint32x2_t vcalt_f32 (float32x2_t, float32x2_t)
2013 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
2014 @end itemize
2015
2016
2017 @itemize @bullet
2018 @item uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t)
2019 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
2020 @end itemize
2021
2022
2023
2024
2025 @subsubsection Test bits
2026
2027 @itemize @bullet
2028 @item uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t)
2029 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
2030 @end itemize
2031
2032
2033 @itemize @bullet
2034 @item uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t)
2035 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
2036 @end itemize
2037
2038
2039 @itemize @bullet
2040 @item uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t)
2041 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
2042 @end itemize
2043
2044
2045 @itemize @bullet
2046 @item uint32x2_t vtst_s32 (int32x2_t, int32x2_t)
2047 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
2048 @end itemize
2049
2050
2051 @itemize @bullet
2052 @item uint16x4_t vtst_s16 (int16x4_t, int16x4_t)
2053 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
2054 @end itemize
2055
2056
2057 @itemize @bullet
2058 @item uint8x8_t vtst_s8 (int8x8_t, int8x8_t)
2059 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
2060 @end itemize
2061
2062
2063 @itemize @bullet
2064 @item uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t)
2065 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
2066 @end itemize
2067
2068
2069 @itemize @bullet
2070 @item uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t)
2071 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
2072 @end itemize
2073
2074
2075 @itemize @bullet
2076 @item uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t)
2077 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
2078 @end itemize
2079
2080
2081 @itemize @bullet
2082 @item uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t)
2083 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2084 @end itemize
2085
2086
2087 @itemize @bullet
2088 @item uint32x4_t vtstq_s32 (int32x4_t, int32x4_t)
2089 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
2090 @end itemize
2091
2092
2093 @itemize @bullet
2094 @item uint16x8_t vtstq_s16 (int16x8_t, int16x8_t)
2095 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
2096 @end itemize
2097
2098
2099 @itemize @bullet
2100 @item uint8x16_t vtstq_s8 (int8x16_t, int8x16_t)
2101 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2102 @end itemize
2103
2104
2105 @itemize @bullet
2106 @item uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t)
2107 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2108 @end itemize
2109
2110
2111
2112
2113 @subsubsection Absolute difference
2114
2115 @itemize @bullet
2116 @item uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t)
2117 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{d0}, @var{d0}, @var{d0}}
2118 @end itemize
2119
2120
2121 @itemize @bullet
2122 @item uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t)
2123 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{d0}, @var{d0}, @var{d0}}
2124 @end itemize
2125
2126
2127 @itemize @bullet
2128 @item uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t)
2129 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{d0}, @var{d0}, @var{d0}}
2130 @end itemize
2131
2132
2133 @itemize @bullet
2134 @item int32x2_t vabd_s32 (int32x2_t, int32x2_t)
2135 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{d0}, @var{d0}, @var{d0}}
2136 @end itemize
2137
2138
2139 @itemize @bullet
2140 @item int16x4_t vabd_s16 (int16x4_t, int16x4_t)
2141 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{d0}, @var{d0}, @var{d0}}
2142 @end itemize
2143
2144
2145 @itemize @bullet
2146 @item int8x8_t vabd_s8 (int8x8_t, int8x8_t)
2147 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{d0}, @var{d0}, @var{d0}}
2148 @end itemize
2149
2150
2151 @itemize @bullet
2152 @item float32x2_t vabd_f32 (float32x2_t, float32x2_t)
2153 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{d0}, @var{d0}, @var{d0}}
2154 @end itemize
2155
2156
2157 @itemize @bullet
2158 @item uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t)
2159 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{q0}, @var{q0}, @var{q0}}
2160 @end itemize
2161
2162
2163 @itemize @bullet
2164 @item uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t)
2165 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{q0}, @var{q0}, @var{q0}}
2166 @end itemize
2167
2168
2169 @itemize @bullet
2170 @item uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t)
2171 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{q0}, @var{q0}, @var{q0}}
2172 @end itemize
2173
2174
2175 @itemize @bullet
2176 @item int32x4_t vabdq_s32 (int32x4_t, int32x4_t)
2177 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{q0}, @var{q0}, @var{q0}}
2178 @end itemize
2179
2180
2181 @itemize @bullet
2182 @item int16x8_t vabdq_s16 (int16x8_t, int16x8_t)
2183 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{q0}, @var{q0}, @var{q0}}
2184 @end itemize
2185
2186
2187 @itemize @bullet
2188 @item int8x16_t vabdq_s8 (int8x16_t, int8x16_t)
2189 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{q0}, @var{q0}, @var{q0}}
2190 @end itemize
2191
2192
2193 @itemize @bullet
2194 @item float32x4_t vabdq_f32 (float32x4_t, float32x4_t)
2195 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{q0}, @var{q0}, @var{q0}}
2196 @end itemize
2197
2198
2199 @itemize @bullet
2200 @item uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t)
2201 @*@emph{Form of expected instruction(s):} @code{vabdl.u32 @var{q0}, @var{d0}, @var{d0}}
2202 @end itemize
2203
2204
2205 @itemize @bullet
2206 @item uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t)
2207 @*@emph{Form of expected instruction(s):} @code{vabdl.u16 @var{q0}, @var{d0}, @var{d0}}
2208 @end itemize
2209
2210
2211 @itemize @bullet
2212 @item uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t)
2213 @*@emph{Form of expected instruction(s):} @code{vabdl.u8 @var{q0}, @var{d0}, @var{d0}}
2214 @end itemize
2215
2216
2217 @itemize @bullet
2218 @item int64x2_t vabdl_s32 (int32x2_t, int32x2_t)
2219 @*@emph{Form of expected instruction(s):} @code{vabdl.s32 @var{q0}, @var{d0}, @var{d0}}
2220 @end itemize
2221
2222
2223 @itemize @bullet
2224 @item int32x4_t vabdl_s16 (int16x4_t, int16x4_t)
2225 @*@emph{Form of expected instruction(s):} @code{vabdl.s16 @var{q0}, @var{d0}, @var{d0}}
2226 @end itemize
2227
2228
2229 @itemize @bullet
2230 @item int16x8_t vabdl_s8 (int8x8_t, int8x8_t)
2231 @*@emph{Form of expected instruction(s):} @code{vabdl.s8 @var{q0}, @var{d0}, @var{d0}}
2232 @end itemize
2233
2234
2235
2236
2237 @subsubsection Absolute difference and accumulate
2238
2239 @itemize @bullet
2240 @item uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
2241 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{d0}, @var{d0}, @var{d0}}
2242 @end itemize
2243
2244
2245 @itemize @bullet
2246 @item uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
2247 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{d0}, @var{d0}, @var{d0}}
2248 @end itemize
2249
2250
2251 @itemize @bullet
2252 @item uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
2253 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{d0}, @var{d0}, @var{d0}}
2254 @end itemize
2255
2256
2257 @itemize @bullet
2258 @item int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t)
2259 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{d0}, @var{d0}, @var{d0}}
2260 @end itemize
2261
2262
2263 @itemize @bullet
2264 @item int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t)
2265 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{d0}, @var{d0}, @var{d0}}
2266 @end itemize
2267
2268
2269 @itemize @bullet
2270 @item int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t)
2271 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{d0}, @var{d0}, @var{d0}}
2272 @end itemize
2273
2274
2275 @itemize @bullet
2276 @item uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2277 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{q0}, @var{q0}, @var{q0}}
2278 @end itemize
2279
2280
2281 @itemize @bullet
2282 @item uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
2283 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{q0}, @var{q0}, @var{q0}}
2284 @end itemize
2285
2286
2287 @itemize @bullet
2288 @item uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
2289 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{q0}, @var{q0}, @var{q0}}
2290 @end itemize
2291
2292
2293 @itemize @bullet
2294 @item int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t)
2295 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{q0}, @var{q0}, @var{q0}}
2296 @end itemize
2297
2298
2299 @itemize @bullet
2300 @item int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t)
2301 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{q0}, @var{q0}, @var{q0}}
2302 @end itemize
2303
2304
2305 @itemize @bullet
2306 @item int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t)
2307 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{q0}, @var{q0}, @var{q0}}
2308 @end itemize
2309
2310
2311 @itemize @bullet
2312 @item uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
2313 @*@emph{Form of expected instruction(s):} @code{vabal.u32 @var{q0}, @var{d0}, @var{d0}}
2314 @end itemize
2315
2316
2317 @itemize @bullet
2318 @item uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
2319 @*@emph{Form of expected instruction(s):} @code{vabal.u16 @var{q0}, @var{d0}, @var{d0}}
2320 @end itemize
2321
2322
2323 @itemize @bullet
2324 @item uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
2325 @*@emph{Form of expected instruction(s):} @code{vabal.u8 @var{q0}, @var{d0}, @var{d0}}
2326 @end itemize
2327
2328
2329 @itemize @bullet
2330 @item int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t)
2331 @*@emph{Form of expected instruction(s):} @code{vabal.s32 @var{q0}, @var{d0}, @var{d0}}
2332 @end itemize
2333
2334
2335 @itemize @bullet
2336 @item int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t)
2337 @*@emph{Form of expected instruction(s):} @code{vabal.s16 @var{q0}, @var{d0}, @var{d0}}
2338 @end itemize
2339
2340
2341 @itemize @bullet
2342 @item int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t)
2343 @*@emph{Form of expected instruction(s):} @code{vabal.s8 @var{q0}, @var{d0}, @var{d0}}
2344 @end itemize
2345
2346
2347
2348
2349 @subsubsection Maximum
2350
2351 @itemize @bullet
2352 @item uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t)
2353 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{d0}, @var{d0}, @var{d0}}
2354 @end itemize
2355
2356
2357 @itemize @bullet
2358 @item uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t)
2359 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{d0}, @var{d0}, @var{d0}}
2360 @end itemize
2361
2362
2363 @itemize @bullet
2364 @item uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t)
2365 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{d0}, @var{d0}, @var{d0}}
2366 @end itemize
2367
2368
2369 @itemize @bullet
2370 @item int32x2_t vmax_s32 (int32x2_t, int32x2_t)
2371 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{d0}, @var{d0}, @var{d0}}
2372 @end itemize
2373
2374
2375 @itemize @bullet
2376 @item int16x4_t vmax_s16 (int16x4_t, int16x4_t)
2377 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{d0}, @var{d0}, @var{d0}}
2378 @end itemize
2379
2380
2381 @itemize @bullet
2382 @item int8x8_t vmax_s8 (int8x8_t, int8x8_t)
2383 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{d0}, @var{d0}, @var{d0}}
2384 @end itemize
2385
2386
2387 @itemize @bullet
2388 @item float32x2_t vmax_f32 (float32x2_t, float32x2_t)
2389 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{d0}, @var{d0}, @var{d0}}
2390 @end itemize
2391
2392
2393 @itemize @bullet
2394 @item uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t)
2395 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{q0}, @var{q0}, @var{q0}}
2396 @end itemize
2397
2398
2399 @itemize @bullet
2400 @item uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t)
2401 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{q0}, @var{q0}, @var{q0}}
2402 @end itemize
2403
2404
2405 @itemize @bullet
2406 @item uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t)
2407 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{q0}, @var{q0}, @var{q0}}
2408 @end itemize
2409
2410
2411 @itemize @bullet
2412 @item int32x4_t vmaxq_s32 (int32x4_t, int32x4_t)
2413 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{q0}, @var{q0}, @var{q0}}
2414 @end itemize
2415
2416
2417 @itemize @bullet
2418 @item int16x8_t vmaxq_s16 (int16x8_t, int16x8_t)
2419 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{q0}, @var{q0}, @var{q0}}
2420 @end itemize
2421
2422
2423 @itemize @bullet
2424 @item int8x16_t vmaxq_s8 (int8x16_t, int8x16_t)
2425 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{q0}, @var{q0}, @var{q0}}
2426 @end itemize
2427
2428
2429 @itemize @bullet
2430 @item float32x4_t vmaxq_f32 (float32x4_t, float32x4_t)
2431 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{q0}, @var{q0}, @var{q0}}
2432 @end itemize
2433
2434
2435
2436
2437 @subsubsection Minimum
2438
2439 @itemize @bullet
2440 @item uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t)
2441 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{d0}, @var{d0}, @var{d0}}
2442 @end itemize
2443
2444
2445 @itemize @bullet
2446 @item uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t)
2447 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{d0}, @var{d0}, @var{d0}}
2448 @end itemize
2449
2450
2451 @itemize @bullet
2452 @item uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t)
2453 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{d0}, @var{d0}, @var{d0}}
2454 @end itemize
2455
2456
2457 @itemize @bullet
2458 @item int32x2_t vmin_s32 (int32x2_t, int32x2_t)
2459 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{d0}, @var{d0}, @var{d0}}
2460 @end itemize
2461
2462
2463 @itemize @bullet
2464 @item int16x4_t vmin_s16 (int16x4_t, int16x4_t)
2465 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{d0}, @var{d0}, @var{d0}}
2466 @end itemize
2467
2468
2469 @itemize @bullet
2470 @item int8x8_t vmin_s8 (int8x8_t, int8x8_t)
2471 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{d0}, @var{d0}, @var{d0}}
2472 @end itemize
2473
2474
2475 @itemize @bullet
2476 @item float32x2_t vmin_f32 (float32x2_t, float32x2_t)
2477 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{d0}, @var{d0}, @var{d0}}
2478 @end itemize
2479
2480
2481 @itemize @bullet
2482 @item uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t)
2483 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{q0}, @var{q0}, @var{q0}}
2484 @end itemize
2485
2486
2487 @itemize @bullet
2488 @item uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t)
2489 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{q0}, @var{q0}, @var{q0}}
2490 @end itemize
2491
2492
2493 @itemize @bullet
2494 @item uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t)
2495 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{q0}, @var{q0}, @var{q0}}
2496 @end itemize
2497
2498
2499 @itemize @bullet
2500 @item int32x4_t vminq_s32 (int32x4_t, int32x4_t)
2501 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{q0}, @var{q0}, @var{q0}}
2502 @end itemize
2503
2504
2505 @itemize @bullet
2506 @item int16x8_t vminq_s16 (int16x8_t, int16x8_t)
2507 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{q0}, @var{q0}, @var{q0}}
2508 @end itemize
2509
2510
2511 @itemize @bullet
2512 @item int8x16_t vminq_s8 (int8x16_t, int8x16_t)
2513 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{q0}, @var{q0}, @var{q0}}
2514 @end itemize
2515
2516
2517 @itemize @bullet
2518 @item float32x4_t vminq_f32 (float32x4_t, float32x4_t)
2519 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{q0}, @var{q0}, @var{q0}}
2520 @end itemize
2521
2522
2523
2524
2525 @subsubsection Pairwise add
2526
2527 @itemize @bullet
2528 @item uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t)
2529 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2530 @end itemize
2531
2532
2533 @itemize @bullet
2534 @item uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t)
2535 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2536 @end itemize
2537
2538
2539 @itemize @bullet
2540 @item uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t)
2541 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2542 @end itemize
2543
2544
2545 @itemize @bullet
2546 @item int32x2_t vpadd_s32 (int32x2_t, int32x2_t)
2547 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2548 @end itemize
2549
2550
2551 @itemize @bullet
2552 @item int16x4_t vpadd_s16 (int16x4_t, int16x4_t)
2553 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2554 @end itemize
2555
2556
2557 @itemize @bullet
2558 @item int8x8_t vpadd_s8 (int8x8_t, int8x8_t)
2559 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2560 @end itemize
2561
2562
2563 @itemize @bullet
2564 @item float32x2_t vpadd_f32 (float32x2_t, float32x2_t)
2565 @*@emph{Form of expected instruction(s):} @code{vpadd.f32 @var{d0}, @var{d0}, @var{d0}}
2566 @end itemize
2567
2568
2569 @itemize @bullet
2570 @item uint64x1_t vpaddl_u32 (uint32x2_t)
2571 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{d0}, @var{d0}}
2572 @end itemize
2573
2574
2575 @itemize @bullet
2576 @item uint32x2_t vpaddl_u16 (uint16x4_t)
2577 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{d0}, @var{d0}}
2578 @end itemize
2579
2580
2581 @itemize @bullet
2582 @item uint16x4_t vpaddl_u8 (uint8x8_t)
2583 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{d0}, @var{d0}}
2584 @end itemize
2585
2586
2587 @itemize @bullet
2588 @item int64x1_t vpaddl_s32 (int32x2_t)
2589 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{d0}, @var{d0}}
2590 @end itemize
2591
2592
2593 @itemize @bullet
2594 @item int32x2_t vpaddl_s16 (int16x4_t)
2595 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{d0}, @var{d0}}
2596 @end itemize
2597
2598
2599 @itemize @bullet
2600 @item int16x4_t vpaddl_s8 (int8x8_t)
2601 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{d0}, @var{d0}}
2602 @end itemize
2603
2604
2605 @itemize @bullet
2606 @item uint64x2_t vpaddlq_u32 (uint32x4_t)
2607 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{q0}, @var{q0}}
2608 @end itemize
2609
2610
2611 @itemize @bullet
2612 @item uint32x4_t vpaddlq_u16 (uint16x8_t)
2613 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{q0}, @var{q0}}
2614 @end itemize
2615
2616
2617 @itemize @bullet
2618 @item uint16x8_t vpaddlq_u8 (uint8x16_t)
2619 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{q0}, @var{q0}}
2620 @end itemize
2621
2622
2623 @itemize @bullet
2624 @item int64x2_t vpaddlq_s32 (int32x4_t)
2625 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{q0}, @var{q0}}
2626 @end itemize
2627
2628
2629 @itemize @bullet
2630 @item int32x4_t vpaddlq_s16 (int16x8_t)
2631 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{q0}, @var{q0}}
2632 @end itemize
2633
2634
2635 @itemize @bullet
2636 @item int16x8_t vpaddlq_s8 (int8x16_t)
2637 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{q0}, @var{q0}}
2638 @end itemize
2639
2640
2641
2642
2643 @subsubsection Pairwise add, single_opcode widen and accumulate
2644
2645 @itemize @bullet
2646 @item uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t)
2647 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{d0}, @var{d0}}
2648 @end itemize
2649
2650
2651 @itemize @bullet
2652 @item uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t)
2653 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{d0}, @var{d0}}
2654 @end itemize
2655
2656
2657 @itemize @bullet
2658 @item uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t)
2659 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{d0}, @var{d0}}
2660 @end itemize
2661
2662
2663 @itemize @bullet
2664 @item int64x1_t vpadal_s32 (int64x1_t, int32x2_t)
2665 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{d0}, @var{d0}}
2666 @end itemize
2667
2668
2669 @itemize @bullet
2670 @item int32x2_t vpadal_s16 (int32x2_t, int16x4_t)
2671 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{d0}, @var{d0}}
2672 @end itemize
2673
2674
2675 @itemize @bullet
2676 @item int16x4_t vpadal_s8 (int16x4_t, int8x8_t)
2677 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{d0}, @var{d0}}
2678 @end itemize
2679
2680
2681 @itemize @bullet
2682 @item uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t)
2683 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{q0}, @var{q0}}
2684 @end itemize
2685
2686
2687 @itemize @bullet
2688 @item uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t)
2689 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{q0}, @var{q0}}
2690 @end itemize
2691
2692
2693 @itemize @bullet
2694 @item uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t)
2695 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{q0}, @var{q0}}
2696 @end itemize
2697
2698
2699 @itemize @bullet
2700 @item int64x2_t vpadalq_s32 (int64x2_t, int32x4_t)
2701 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{q0}, @var{q0}}
2702 @end itemize
2703
2704
2705 @itemize @bullet
2706 @item int32x4_t vpadalq_s16 (int32x4_t, int16x8_t)
2707 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{q0}, @var{q0}}
2708 @end itemize
2709
2710
2711 @itemize @bullet
2712 @item int16x8_t vpadalq_s8 (int16x8_t, int8x16_t)
2713 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{q0}, @var{q0}}
2714 @end itemize
2715
2716
2717
2718
2719 @subsubsection Folding maximum
2720
2721 @itemize @bullet
2722 @item uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t)
2723 @*@emph{Form of expected instruction(s):} @code{vpmax.u32 @var{d0}, @var{d0}, @var{d0}}
2724 @end itemize
2725
2726
2727 @itemize @bullet
2728 @item uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t)
2729 @*@emph{Form of expected instruction(s):} @code{vpmax.u16 @var{d0}, @var{d0}, @var{d0}}
2730 @end itemize
2731
2732
2733 @itemize @bullet
2734 @item uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t)
2735 @*@emph{Form of expected instruction(s):} @code{vpmax.u8 @var{d0}, @var{d0}, @var{d0}}
2736 @end itemize
2737
2738
2739 @itemize @bullet
2740 @item int32x2_t vpmax_s32 (int32x2_t, int32x2_t)
2741 @*@emph{Form of expected instruction(s):} @code{vpmax.s32 @var{d0}, @var{d0}, @var{d0}}
2742 @end itemize
2743
2744
2745 @itemize @bullet
2746 @item int16x4_t vpmax_s16 (int16x4_t, int16x4_t)
2747 @*@emph{Form of expected instruction(s):} @code{vpmax.s16 @var{d0}, @var{d0}, @var{d0}}
2748 @end itemize
2749
2750
2751 @itemize @bullet
2752 @item int8x8_t vpmax_s8 (int8x8_t, int8x8_t)
2753 @*@emph{Form of expected instruction(s):} @code{vpmax.s8 @var{d0}, @var{d0}, @var{d0}}
2754 @end itemize
2755
2756
2757 @itemize @bullet
2758 @item float32x2_t vpmax_f32 (float32x2_t, float32x2_t)
2759 @*@emph{Form of expected instruction(s):} @code{vpmax.f32 @var{d0}, @var{d0}, @var{d0}}
2760 @end itemize
2761
2762
2763
2764
2765 @subsubsection Folding minimum
2766
2767 @itemize @bullet
2768 @item uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t)
2769 @*@emph{Form of expected instruction(s):} @code{vpmin.u32 @var{d0}, @var{d0}, @var{d0}}
2770 @end itemize
2771
2772
2773 @itemize @bullet
2774 @item uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t)
2775 @*@emph{Form of expected instruction(s):} @code{vpmin.u16 @var{d0}, @var{d0}, @var{d0}}
2776 @end itemize
2777
2778
2779 @itemize @bullet
2780 @item uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t)
2781 @*@emph{Form of expected instruction(s):} @code{vpmin.u8 @var{d0}, @var{d0}, @var{d0}}
2782 @end itemize
2783
2784
2785 @itemize @bullet
2786 @item int32x2_t vpmin_s32 (int32x2_t, int32x2_t)
2787 @*@emph{Form of expected instruction(s):} @code{vpmin.s32 @var{d0}, @var{d0}, @var{d0}}
2788 @end itemize
2789
2790
2791 @itemize @bullet
2792 @item int16x4_t vpmin_s16 (int16x4_t, int16x4_t)
2793 @*@emph{Form of expected instruction(s):} @code{vpmin.s16 @var{d0}, @var{d0}, @var{d0}}
2794 @end itemize
2795
2796
2797 @itemize @bullet
2798 @item int8x8_t vpmin_s8 (int8x8_t, int8x8_t)
2799 @*@emph{Form of expected instruction(s):} @code{vpmin.s8 @var{d0}, @var{d0}, @var{d0}}
2800 @end itemize
2801
2802
2803 @itemize @bullet
2804 @item float32x2_t vpmin_f32 (float32x2_t, float32x2_t)
2805 @*@emph{Form of expected instruction(s):} @code{vpmin.f32 @var{d0}, @var{d0}, @var{d0}}
2806 @end itemize
2807
2808
2809
2810
2811 @subsubsection Reciprocal step
2812
2813 @itemize @bullet
2814 @item float32x2_t vrecps_f32 (float32x2_t, float32x2_t)
2815 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{d0}, @var{d0}, @var{d0}}
2816 @end itemize
2817
2818
2819 @itemize @bullet
2820 @item float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t)
2821 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{q0}, @var{q0}, @var{q0}}
2822 @end itemize
2823
2824
2825 @itemize @bullet
2826 @item float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t)
2827 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{d0}, @var{d0}, @var{d0}}
2828 @end itemize
2829
2830
2831 @itemize @bullet
2832 @item float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t)
2833 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{q0}, @var{q0}, @var{q0}}
2834 @end itemize
2835
2836
2837
2838
2839 @subsubsection Vector shift left
2840
2841 @itemize @bullet
2842 @item uint32x2_t vshl_u32 (uint32x2_t, int32x2_t)
2843 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{d0}, @var{d0}, @var{d0}}
2844 @end itemize
2845
2846
2847 @itemize @bullet
2848 @item uint16x4_t vshl_u16 (uint16x4_t, int16x4_t)
2849 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{d0}, @var{d0}, @var{d0}}
2850 @end itemize
2851
2852
2853 @itemize @bullet
2854 @item uint8x8_t vshl_u8 (uint8x8_t, int8x8_t)
2855 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{d0}, @var{d0}, @var{d0}}
2856 @end itemize
2857
2858
2859 @itemize @bullet
2860 @item int32x2_t vshl_s32 (int32x2_t, int32x2_t)
2861 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{d0}, @var{d0}, @var{d0}}
2862 @end itemize
2863
2864
2865 @itemize @bullet
2866 @item int16x4_t vshl_s16 (int16x4_t, int16x4_t)
2867 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{d0}, @var{d0}, @var{d0}}
2868 @end itemize
2869
2870
2871 @itemize @bullet
2872 @item int8x8_t vshl_s8 (int8x8_t, int8x8_t)
2873 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{d0}, @var{d0}, @var{d0}}
2874 @end itemize
2875
2876
2877 @itemize @bullet
2878 @item uint64x1_t vshl_u64 (uint64x1_t, int64x1_t)
2879 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{d0}, @var{d0}, @var{d0}}
2880 @end itemize
2881
2882
2883 @itemize @bullet
2884 @item int64x1_t vshl_s64 (int64x1_t, int64x1_t)
2885 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{d0}, @var{d0}, @var{d0}}
2886 @end itemize
2887
2888
2889 @itemize @bullet
2890 @item uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t)
2891 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{q0}, @var{q0}, @var{q0}}
2892 @end itemize
2893
2894
2895 @itemize @bullet
2896 @item uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t)
2897 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{q0}, @var{q0}, @var{q0}}
2898 @end itemize
2899
2900
2901 @itemize @bullet
2902 @item uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t)
2903 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{q0}, @var{q0}, @var{q0}}
2904 @end itemize
2905
2906
2907 @itemize @bullet
2908 @item int32x4_t vshlq_s32 (int32x4_t, int32x4_t)
2909 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{q0}, @var{q0}, @var{q0}}
2910 @end itemize
2911
2912
2913 @itemize @bullet
2914 @item int16x8_t vshlq_s16 (int16x8_t, int16x8_t)
2915 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{q0}, @var{q0}, @var{q0}}
2916 @end itemize
2917
2918
2919 @itemize @bullet
2920 @item int8x16_t vshlq_s8 (int8x16_t, int8x16_t)
2921 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{q0}, @var{q0}, @var{q0}}
2922 @end itemize
2923
2924
2925 @itemize @bullet
2926 @item uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t)
2927 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{q0}, @var{q0}, @var{q0}}
2928 @end itemize
2929
2930
2931 @itemize @bullet
2932 @item int64x2_t vshlq_s64 (int64x2_t, int64x2_t)
2933 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{q0}, @var{q0}, @var{q0}}
2934 @end itemize
2935
2936
2937 @itemize @bullet
2938 @item uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t)
2939 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{d0}, @var{d0}, @var{d0}}
2940 @end itemize
2941
2942
2943 @itemize @bullet
2944 @item uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t)
2945 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{d0}, @var{d0}, @var{d0}}
2946 @end itemize
2947
2948
2949 @itemize @bullet
2950 @item uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t)
2951 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{d0}, @var{d0}, @var{d0}}
2952 @end itemize
2953
2954
2955 @itemize @bullet
2956 @item int32x2_t vrshl_s32 (int32x2_t, int32x2_t)
2957 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{d0}, @var{d0}, @var{d0}}
2958 @end itemize
2959
2960
2961 @itemize @bullet
2962 @item int16x4_t vrshl_s16 (int16x4_t, int16x4_t)
2963 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{d0}, @var{d0}, @var{d0}}
2964 @end itemize
2965
2966
2967 @itemize @bullet
2968 @item int8x8_t vrshl_s8 (int8x8_t, int8x8_t)
2969 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{d0}, @var{d0}, @var{d0}}
2970 @end itemize
2971
2972
2973 @itemize @bullet
2974 @item uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t)
2975 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{d0}, @var{d0}, @var{d0}}
2976 @end itemize
2977
2978
2979 @itemize @bullet
2980 @item int64x1_t vrshl_s64 (int64x1_t, int64x1_t)
2981 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{d0}, @var{d0}, @var{d0}}
2982 @end itemize
2983
2984
2985 @itemize @bullet
2986 @item uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t)
2987 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{q0}, @var{q0}, @var{q0}}
2988 @end itemize
2989
2990
2991 @itemize @bullet
2992 @item uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t)
2993 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{q0}, @var{q0}, @var{q0}}
2994 @end itemize
2995
2996
2997 @itemize @bullet
2998 @item uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t)
2999 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{q0}, @var{q0}, @var{q0}}
3000 @end itemize
3001
3002
3003 @itemize @bullet
3004 @item int32x4_t vrshlq_s32 (int32x4_t, int32x4_t)
3005 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3006 @end itemize
3007
3008
3009 @itemize @bullet
3010 @item int16x8_t vrshlq_s16 (int16x8_t, int16x8_t)
3011 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3012 @end itemize
3013
3014
3015 @itemize @bullet
3016 @item int8x16_t vrshlq_s8 (int8x16_t, int8x16_t)
3017 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3018 @end itemize
3019
3020
3021 @itemize @bullet
3022 @item uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t)
3023 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3024 @end itemize
3025
3026
3027 @itemize @bullet
3028 @item int64x2_t vrshlq_s64 (int64x2_t, int64x2_t)
3029 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3030 @end itemize
3031
3032
3033 @itemize @bullet
3034 @item uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t)
3035 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, @var{d0}}
3036 @end itemize
3037
3038
3039 @itemize @bullet
3040 @item uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t)
3041 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, @var{d0}}
3042 @end itemize
3043
3044
3045 @itemize @bullet
3046 @item uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t)
3047 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, @var{d0}}
3048 @end itemize
3049
3050
3051 @itemize @bullet
3052 @item int32x2_t vqshl_s32 (int32x2_t, int32x2_t)
3053 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, @var{d0}}
3054 @end itemize
3055
3056
3057 @itemize @bullet
3058 @item int16x4_t vqshl_s16 (int16x4_t, int16x4_t)
3059 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, @var{d0}}
3060 @end itemize
3061
3062
3063 @itemize @bullet
3064 @item int8x8_t vqshl_s8 (int8x8_t, int8x8_t)
3065 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, @var{d0}}
3066 @end itemize
3067
3068
3069 @itemize @bullet
3070 @item uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t)
3071 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, @var{d0}}
3072 @end itemize
3073
3074
3075 @itemize @bullet
3076 @item int64x1_t vqshl_s64 (int64x1_t, int64x1_t)
3077 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, @var{d0}}
3078 @end itemize
3079
3080
3081 @itemize @bullet
3082 @item uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t)
3083 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, @var{q0}}
3084 @end itemize
3085
3086
3087 @itemize @bullet
3088 @item uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t)
3089 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, @var{q0}}
3090 @end itemize
3091
3092
3093 @itemize @bullet
3094 @item uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t)
3095 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, @var{q0}}
3096 @end itemize
3097
3098
3099 @itemize @bullet
3100 @item int32x4_t vqshlq_s32 (int32x4_t, int32x4_t)
3101 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, @var{q0}}
3102 @end itemize
3103
3104
3105 @itemize @bullet
3106 @item int16x8_t vqshlq_s16 (int16x8_t, int16x8_t)
3107 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, @var{q0}}
3108 @end itemize
3109
3110
3111 @itemize @bullet
3112 @item int8x16_t vqshlq_s8 (int8x16_t, int8x16_t)
3113 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, @var{q0}}
3114 @end itemize
3115
3116
3117 @itemize @bullet
3118 @item uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t)
3119 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, @var{q0}}
3120 @end itemize
3121
3122
3123 @itemize @bullet
3124 @item int64x2_t vqshlq_s64 (int64x2_t, int64x2_t)
3125 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, @var{q0}}
3126 @end itemize
3127
3128
3129 @itemize @bullet
3130 @item uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t)
3131 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{d0}, @var{d0}, @var{d0}}
3132 @end itemize
3133
3134
3135 @itemize @bullet
3136 @item uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t)
3137 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{d0}, @var{d0}, @var{d0}}
3138 @end itemize
3139
3140
3141 @itemize @bullet
3142 @item uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t)
3143 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{d0}, @var{d0}, @var{d0}}
3144 @end itemize
3145
3146
3147 @itemize @bullet
3148 @item int32x2_t vqrshl_s32 (int32x2_t, int32x2_t)
3149 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{d0}, @var{d0}, @var{d0}}
3150 @end itemize
3151
3152
3153 @itemize @bullet
3154 @item int16x4_t vqrshl_s16 (int16x4_t, int16x4_t)
3155 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{d0}, @var{d0}, @var{d0}}
3156 @end itemize
3157
3158
3159 @itemize @bullet
3160 @item int8x8_t vqrshl_s8 (int8x8_t, int8x8_t)
3161 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{d0}, @var{d0}, @var{d0}}
3162 @end itemize
3163
3164
3165 @itemize @bullet
3166 @item uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t)
3167 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{d0}, @var{d0}, @var{d0}}
3168 @end itemize
3169
3170
3171 @itemize @bullet
3172 @item int64x1_t vqrshl_s64 (int64x1_t, int64x1_t)
3173 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{d0}, @var{d0}, @var{d0}}
3174 @end itemize
3175
3176
3177 @itemize @bullet
3178 @item uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t)
3179 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{q0}, @var{q0}, @var{q0}}
3180 @end itemize
3181
3182
3183 @itemize @bullet
3184 @item uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t)
3185 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{q0}, @var{q0}, @var{q0}}
3186 @end itemize
3187
3188
3189 @itemize @bullet
3190 @item uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t)
3191 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{q0}, @var{q0}, @var{q0}}
3192 @end itemize
3193
3194
3195 @itemize @bullet
3196 @item int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t)
3197 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3198 @end itemize
3199
3200
3201 @itemize @bullet
3202 @item int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t)
3203 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3204 @end itemize
3205
3206
3207 @itemize @bullet
3208 @item int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t)
3209 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3210 @end itemize
3211
3212
3213 @itemize @bullet
3214 @item uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t)
3215 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3216 @end itemize
3217
3218
3219 @itemize @bullet
3220 @item int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t)
3221 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3222 @end itemize
3223
3224
3225
3226
3227 @subsubsection Vector shift left by constant
3228
3229 @itemize @bullet
3230 @item uint32x2_t vshl_n_u32 (uint32x2_t, const int)
3231 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3232 @end itemize
3233
3234
3235 @itemize @bullet
3236 @item uint16x4_t vshl_n_u16 (uint16x4_t, const int)
3237 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3238 @end itemize
3239
3240
3241 @itemize @bullet
3242 @item uint8x8_t vshl_n_u8 (uint8x8_t, const int)
3243 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3244 @end itemize
3245
3246
3247 @itemize @bullet
3248 @item int32x2_t vshl_n_s32 (int32x2_t, const int)
3249 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3250 @end itemize
3251
3252
3253 @itemize @bullet
3254 @item int16x4_t vshl_n_s16 (int16x4_t, const int)
3255 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3256 @end itemize
3257
3258
3259 @itemize @bullet
3260 @item int8x8_t vshl_n_s8 (int8x8_t, const int)
3261 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3262 @end itemize
3263
3264
3265 @itemize @bullet
3266 @item uint64x1_t vshl_n_u64 (uint64x1_t, const int)
3267 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3268 @end itemize
3269
3270
3271 @itemize @bullet
3272 @item int64x1_t vshl_n_s64 (int64x1_t, const int)
3273 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3274 @end itemize
3275
3276
3277 @itemize @bullet
3278 @item uint32x4_t vshlq_n_u32 (uint32x4_t, const int)
3279 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3280 @end itemize
3281
3282
3283 @itemize @bullet
3284 @item uint16x8_t vshlq_n_u16 (uint16x8_t, const int)
3285 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3286 @end itemize
3287
3288
3289 @itemize @bullet
3290 @item uint8x16_t vshlq_n_u8 (uint8x16_t, const int)
3291 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3292 @end itemize
3293
3294
3295 @itemize @bullet
3296 @item int32x4_t vshlq_n_s32 (int32x4_t, const int)
3297 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3298 @end itemize
3299
3300
3301 @itemize @bullet
3302 @item int16x8_t vshlq_n_s16 (int16x8_t, const int)
3303 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3304 @end itemize
3305
3306
3307 @itemize @bullet
3308 @item int8x16_t vshlq_n_s8 (int8x16_t, const int)
3309 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3310 @end itemize
3311
3312
3313 @itemize @bullet
3314 @item uint64x2_t vshlq_n_u64 (uint64x2_t, const int)
3315 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3316 @end itemize
3317
3318
3319 @itemize @bullet
3320 @item int64x2_t vshlq_n_s64 (int64x2_t, const int)
3321 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3322 @end itemize
3323
3324
3325 @itemize @bullet
3326 @item uint32x2_t vqshl_n_u32 (uint32x2_t, const int)
3327 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, #@var{0}}
3328 @end itemize
3329
3330
3331 @itemize @bullet
3332 @item uint16x4_t vqshl_n_u16 (uint16x4_t, const int)
3333 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, #@var{0}}
3334 @end itemize
3335
3336
3337 @itemize @bullet
3338 @item uint8x8_t vqshl_n_u8 (uint8x8_t, const int)
3339 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, #@var{0}}
3340 @end itemize
3341
3342
3343 @itemize @bullet
3344 @item int32x2_t vqshl_n_s32 (int32x2_t, const int)
3345 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, #@var{0}}
3346 @end itemize
3347
3348
3349 @itemize @bullet
3350 @item int16x4_t vqshl_n_s16 (int16x4_t, const int)
3351 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, #@var{0}}
3352 @end itemize
3353
3354
3355 @itemize @bullet
3356 @item int8x8_t vqshl_n_s8 (int8x8_t, const int)
3357 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, #@var{0}}
3358 @end itemize
3359
3360
3361 @itemize @bullet
3362 @item uint64x1_t vqshl_n_u64 (uint64x1_t, const int)
3363 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, #@var{0}}
3364 @end itemize
3365
3366
3367 @itemize @bullet
3368 @item int64x1_t vqshl_n_s64 (int64x1_t, const int)
3369 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, #@var{0}}
3370 @end itemize
3371
3372
3373 @itemize @bullet
3374 @item uint32x4_t vqshlq_n_u32 (uint32x4_t, const int)
3375 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, #@var{0}}
3376 @end itemize
3377
3378
3379 @itemize @bullet
3380 @item uint16x8_t vqshlq_n_u16 (uint16x8_t, const int)
3381 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, #@var{0}}
3382 @end itemize
3383
3384
3385 @itemize @bullet
3386 @item uint8x16_t vqshlq_n_u8 (uint8x16_t, const int)
3387 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, #@var{0}}
3388 @end itemize
3389
3390
3391 @itemize @bullet
3392 @item int32x4_t vqshlq_n_s32 (int32x4_t, const int)
3393 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, #@var{0}}
3394 @end itemize
3395
3396
3397 @itemize @bullet
3398 @item int16x8_t vqshlq_n_s16 (int16x8_t, const int)
3399 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, #@var{0}}
3400 @end itemize
3401
3402
3403 @itemize @bullet
3404 @item int8x16_t vqshlq_n_s8 (int8x16_t, const int)
3405 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, #@var{0}}
3406 @end itemize
3407
3408
3409 @itemize @bullet
3410 @item uint64x2_t vqshlq_n_u64 (uint64x2_t, const int)
3411 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, #@var{0}}
3412 @end itemize
3413
3414
3415 @itemize @bullet
3416 @item int64x2_t vqshlq_n_s64 (int64x2_t, const int)
3417 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, #@var{0}}
3418 @end itemize
3419
3420
3421 @itemize @bullet
3422 @item uint64x1_t vqshlu_n_s64 (int64x1_t, const int)
3423 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{d0}, @var{d0}, #@var{0}}
3424 @end itemize
3425
3426
3427 @itemize @bullet
3428 @item uint32x2_t vqshlu_n_s32 (int32x2_t, const int)
3429 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{d0}, @var{d0}, #@var{0}}
3430 @end itemize
3431
3432
3433 @itemize @bullet
3434 @item uint16x4_t vqshlu_n_s16 (int16x4_t, const int)
3435 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{d0}, @var{d0}, #@var{0}}
3436 @end itemize
3437
3438
3439 @itemize @bullet
3440 @item uint8x8_t vqshlu_n_s8 (int8x8_t, const int)
3441 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{d0}, @var{d0}, #@var{0}}
3442 @end itemize
3443
3444
3445 @itemize @bullet
3446 @item uint64x2_t vqshluq_n_s64 (int64x2_t, const int)
3447 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{q0}, @var{q0}, #@var{0}}
3448 @end itemize
3449
3450
3451 @itemize @bullet
3452 @item uint32x4_t vqshluq_n_s32 (int32x4_t, const int)
3453 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{q0}, @var{q0}, #@var{0}}
3454 @end itemize
3455
3456
3457 @itemize @bullet
3458 @item uint16x8_t vqshluq_n_s16 (int16x8_t, const int)
3459 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{q0}, @var{q0}, #@var{0}}
3460 @end itemize
3461
3462
3463 @itemize @bullet
3464 @item uint8x16_t vqshluq_n_s8 (int8x16_t, const int)
3465 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{q0}, @var{q0}, #@var{0}}
3466 @end itemize
3467
3468
3469 @itemize @bullet
3470 @item uint64x2_t vshll_n_u32 (uint32x2_t, const int)
3471 @*@emph{Form of expected instruction(s):} @code{vshll.u32 @var{q0}, @var{d0}, #@var{0}}
3472 @end itemize
3473
3474
3475 @itemize @bullet
3476 @item uint32x4_t vshll_n_u16 (uint16x4_t, const int)
3477 @*@emph{Form of expected instruction(s):} @code{vshll.u16 @var{q0}, @var{d0}, #@var{0}}
3478 @end itemize
3479
3480
3481 @itemize @bullet
3482 @item uint16x8_t vshll_n_u8 (uint8x8_t, const int)
3483 @*@emph{Form of expected instruction(s):} @code{vshll.u8 @var{q0}, @var{d0}, #@var{0}}
3484 @end itemize
3485
3486
3487 @itemize @bullet
3488 @item int64x2_t vshll_n_s32 (int32x2_t, const int)
3489 @*@emph{Form of expected instruction(s):} @code{vshll.s32 @var{q0}, @var{d0}, #@var{0}}
3490 @end itemize
3491
3492
3493 @itemize @bullet
3494 @item int32x4_t vshll_n_s16 (int16x4_t, const int)
3495 @*@emph{Form of expected instruction(s):} @code{vshll.s16 @var{q0}, @var{d0}, #@var{0}}
3496 @end itemize
3497
3498
3499 @itemize @bullet
3500 @item int16x8_t vshll_n_s8 (int8x8_t, const int)
3501 @*@emph{Form of expected instruction(s):} @code{vshll.s8 @var{q0}, @var{d0}, #@var{0}}
3502 @end itemize
3503
3504
3505
3506
3507 @subsubsection Vector shift right by constant
3508
3509 @itemize @bullet
3510 @item uint32x2_t vshr_n_u32 (uint32x2_t, const int)
3511 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{d0}, @var{d0}, #@var{0}}
3512 @end itemize
3513
3514
3515 @itemize @bullet
3516 @item uint16x4_t vshr_n_u16 (uint16x4_t, const int)
3517 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{d0}, @var{d0}, #@var{0}}
3518 @end itemize
3519
3520
3521 @itemize @bullet
3522 @item uint8x8_t vshr_n_u8 (uint8x8_t, const int)
3523 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{d0}, @var{d0}, #@var{0}}
3524 @end itemize
3525
3526
3527 @itemize @bullet
3528 @item int32x2_t vshr_n_s32 (int32x2_t, const int)
3529 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{d0}, @var{d0}, #@var{0}}
3530 @end itemize
3531
3532
3533 @itemize @bullet
3534 @item int16x4_t vshr_n_s16 (int16x4_t, const int)
3535 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{d0}, @var{d0}, #@var{0}}
3536 @end itemize
3537
3538
3539 @itemize @bullet
3540 @item int8x8_t vshr_n_s8 (int8x8_t, const int)
3541 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{d0}, @var{d0}, #@var{0}}
3542 @end itemize
3543
3544
3545 @itemize @bullet
3546 @item uint64x1_t vshr_n_u64 (uint64x1_t, const int)
3547 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{d0}, @var{d0}, #@var{0}}
3548 @end itemize
3549
3550
3551 @itemize @bullet
3552 @item int64x1_t vshr_n_s64 (int64x1_t, const int)
3553 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{d0}, @var{d0}, #@var{0}}
3554 @end itemize
3555
3556
3557 @itemize @bullet
3558 @item uint32x4_t vshrq_n_u32 (uint32x4_t, const int)
3559 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{q0}, @var{q0}, #@var{0}}
3560 @end itemize
3561
3562
3563 @itemize @bullet
3564 @item uint16x8_t vshrq_n_u16 (uint16x8_t, const int)
3565 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{q0}, @var{q0}, #@var{0}}
3566 @end itemize
3567
3568
3569 @itemize @bullet
3570 @item uint8x16_t vshrq_n_u8 (uint8x16_t, const int)
3571 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{q0}, @var{q0}, #@var{0}}
3572 @end itemize
3573
3574
3575 @itemize @bullet
3576 @item int32x4_t vshrq_n_s32 (int32x4_t, const int)
3577 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{q0}, @var{q0}, #@var{0}}
3578 @end itemize
3579
3580
3581 @itemize @bullet
3582 @item int16x8_t vshrq_n_s16 (int16x8_t, const int)
3583 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{q0}, @var{q0}, #@var{0}}
3584 @end itemize
3585
3586
3587 @itemize @bullet
3588 @item int8x16_t vshrq_n_s8 (int8x16_t, const int)
3589 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{q0}, @var{q0}, #@var{0}}
3590 @end itemize
3591
3592
3593 @itemize @bullet
3594 @item uint64x2_t vshrq_n_u64 (uint64x2_t, const int)
3595 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{q0}, @var{q0}, #@var{0}}
3596 @end itemize
3597
3598
3599 @itemize @bullet
3600 @item int64x2_t vshrq_n_s64 (int64x2_t, const int)
3601 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{q0}, @var{q0}, #@var{0}}
3602 @end itemize
3603
3604
3605 @itemize @bullet
3606 @item uint32x2_t vrshr_n_u32 (uint32x2_t, const int)
3607 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{d0}, @var{d0}, #@var{0}}
3608 @end itemize
3609
3610
3611 @itemize @bullet
3612 @item uint16x4_t vrshr_n_u16 (uint16x4_t, const int)
3613 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{d0}, @var{d0}, #@var{0}}
3614 @end itemize
3615
3616
3617 @itemize @bullet
3618 @item uint8x8_t vrshr_n_u8 (uint8x8_t, const int)
3619 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{d0}, @var{d0}, #@var{0}}
3620 @end itemize
3621
3622
3623 @itemize @bullet
3624 @item int32x2_t vrshr_n_s32 (int32x2_t, const int)
3625 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{d0}, @var{d0}, #@var{0}}
3626 @end itemize
3627
3628
3629 @itemize @bullet
3630 @item int16x4_t vrshr_n_s16 (int16x4_t, const int)
3631 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{d0}, @var{d0}, #@var{0}}
3632 @end itemize
3633
3634
3635 @itemize @bullet
3636 @item int8x8_t vrshr_n_s8 (int8x8_t, const int)
3637 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{d0}, @var{d0}, #@var{0}}
3638 @end itemize
3639
3640
3641 @itemize @bullet
3642 @item uint64x1_t vrshr_n_u64 (uint64x1_t, const int)
3643 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{d0}, @var{d0}, #@var{0}}
3644 @end itemize
3645
3646
3647 @itemize @bullet
3648 @item int64x1_t vrshr_n_s64 (int64x1_t, const int)
3649 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{d0}, @var{d0}, #@var{0}}
3650 @end itemize
3651
3652
3653 @itemize @bullet
3654 @item uint32x4_t vrshrq_n_u32 (uint32x4_t, const int)
3655 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{q0}, @var{q0}, #@var{0}}
3656 @end itemize
3657
3658
3659 @itemize @bullet
3660 @item uint16x8_t vrshrq_n_u16 (uint16x8_t, const int)
3661 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{q0}, @var{q0}, #@var{0}}
3662 @end itemize
3663
3664
3665 @itemize @bullet
3666 @item uint8x16_t vrshrq_n_u8 (uint8x16_t, const int)
3667 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{q0}, @var{q0}, #@var{0}}
3668 @end itemize
3669
3670
3671 @itemize @bullet
3672 @item int32x4_t vrshrq_n_s32 (int32x4_t, const int)
3673 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{q0}, @var{q0}, #@var{0}}
3674 @end itemize
3675
3676
3677 @itemize @bullet
3678 @item int16x8_t vrshrq_n_s16 (int16x8_t, const int)
3679 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{q0}, @var{q0}, #@var{0}}
3680 @end itemize
3681
3682
3683 @itemize @bullet
3684 @item int8x16_t vrshrq_n_s8 (int8x16_t, const int)
3685 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{q0}, @var{q0}, #@var{0}}
3686 @end itemize
3687
3688
3689 @itemize @bullet
3690 @item uint64x2_t vrshrq_n_u64 (uint64x2_t, const int)
3691 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{q0}, @var{q0}, #@var{0}}
3692 @end itemize
3693
3694
3695 @itemize @bullet
3696 @item int64x2_t vrshrq_n_s64 (int64x2_t, const int)
3697 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{q0}, @var{q0}, #@var{0}}
3698 @end itemize
3699
3700
3701 @itemize @bullet
3702 @item uint32x2_t vshrn_n_u64 (uint64x2_t, const int)
3703 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3704 @end itemize
3705
3706
3707 @itemize @bullet
3708 @item uint16x4_t vshrn_n_u32 (uint32x4_t, const int)
3709 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3710 @end itemize
3711
3712
3713 @itemize @bullet
3714 @item uint8x8_t vshrn_n_u16 (uint16x8_t, const int)
3715 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3716 @end itemize
3717
3718
3719 @itemize @bullet
3720 @item int32x2_t vshrn_n_s64 (int64x2_t, const int)
3721 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3722 @end itemize
3723
3724
3725 @itemize @bullet
3726 @item int16x4_t vshrn_n_s32 (int32x4_t, const int)
3727 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3728 @end itemize
3729
3730
3731 @itemize @bullet
3732 @item int8x8_t vshrn_n_s16 (int16x8_t, const int)
3733 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3734 @end itemize
3735
3736
3737 @itemize @bullet
3738 @item uint32x2_t vrshrn_n_u64 (uint64x2_t, const int)
3739 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3740 @end itemize
3741
3742
3743 @itemize @bullet
3744 @item uint16x4_t vrshrn_n_u32 (uint32x4_t, const int)
3745 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3746 @end itemize
3747
3748
3749 @itemize @bullet
3750 @item uint8x8_t vrshrn_n_u16 (uint16x8_t, const int)
3751 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3752 @end itemize
3753
3754
3755 @itemize @bullet
3756 @item int32x2_t vrshrn_n_s64 (int64x2_t, const int)
3757 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3758 @end itemize
3759
3760
3761 @itemize @bullet
3762 @item int16x4_t vrshrn_n_s32 (int32x4_t, const int)
3763 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3764 @end itemize
3765
3766
3767 @itemize @bullet
3768 @item int8x8_t vrshrn_n_s16 (int16x8_t, const int)
3769 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3770 @end itemize
3771
3772
3773 @itemize @bullet
3774 @item uint32x2_t vqshrn_n_u64 (uint64x2_t, const int)
3775 @*@emph{Form of expected instruction(s):} @code{vqshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3776 @end itemize
3777
3778
3779 @itemize @bullet
3780 @item uint16x4_t vqshrn_n_u32 (uint32x4_t, const int)
3781 @*@emph{Form of expected instruction(s):} @code{vqshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3782 @end itemize
3783
3784
3785 @itemize @bullet
3786 @item uint8x8_t vqshrn_n_u16 (uint16x8_t, const int)
3787 @*@emph{Form of expected instruction(s):} @code{vqshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3788 @end itemize
3789
3790
3791 @itemize @bullet
3792 @item int32x2_t vqshrn_n_s64 (int64x2_t, const int)
3793 @*@emph{Form of expected instruction(s):} @code{vqshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3794 @end itemize
3795
3796
3797 @itemize @bullet
3798 @item int16x4_t vqshrn_n_s32 (int32x4_t, const int)
3799 @*@emph{Form of expected instruction(s):} @code{vqshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3800 @end itemize
3801
3802
3803 @itemize @bullet
3804 @item int8x8_t vqshrn_n_s16 (int16x8_t, const int)
3805 @*@emph{Form of expected instruction(s):} @code{vqshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3806 @end itemize
3807
3808
3809 @itemize @bullet
3810 @item uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int)
3811 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3812 @end itemize
3813
3814
3815 @itemize @bullet
3816 @item uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int)
3817 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3818 @end itemize
3819
3820
3821 @itemize @bullet
3822 @item uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int)
3823 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3824 @end itemize
3825
3826
3827 @itemize @bullet
3828 @item int32x2_t vqrshrn_n_s64 (int64x2_t, const int)
3829 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3830 @end itemize
3831
3832
3833 @itemize @bullet
3834 @item int16x4_t vqrshrn_n_s32 (int32x4_t, const int)
3835 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3836 @end itemize
3837
3838
3839 @itemize @bullet
3840 @item int8x8_t vqrshrn_n_s16 (int16x8_t, const int)
3841 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3842 @end itemize
3843
3844
3845 @itemize @bullet
3846 @item uint32x2_t vqshrun_n_s64 (int64x2_t, const int)
3847 @*@emph{Form of expected instruction(s):} @code{vqshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3848 @end itemize
3849
3850
3851 @itemize @bullet
3852 @item uint16x4_t vqshrun_n_s32 (int32x4_t, const int)
3853 @*@emph{Form of expected instruction(s):} @code{vqshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3854 @end itemize
3855
3856
3857 @itemize @bullet
3858 @item uint8x8_t vqshrun_n_s16 (int16x8_t, const int)
3859 @*@emph{Form of expected instruction(s):} @code{vqshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3860 @end itemize
3861
3862
3863 @itemize @bullet
3864 @item uint32x2_t vqrshrun_n_s64 (int64x2_t, const int)
3865 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3866 @end itemize
3867
3868
3869 @itemize @bullet
3870 @item uint16x4_t vqrshrun_n_s32 (int32x4_t, const int)
3871 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3872 @end itemize
3873
3874
3875 @itemize @bullet
3876 @item uint8x8_t vqrshrun_n_s16 (int16x8_t, const int)
3877 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3878 @end itemize
3879
3880
3881
3882
3883 @subsubsection Vector shift right by constant and accumulate
3884
3885 @itemize @bullet
3886 @item uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3887 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{d0}, @var{d0}, #@var{0}}
3888 @end itemize
3889
3890
3891 @itemize @bullet
3892 @item uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3893 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{d0}, @var{d0}, #@var{0}}
3894 @end itemize
3895
3896
3897 @itemize @bullet
3898 @item uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3899 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{d0}, @var{d0}, #@var{0}}
3900 @end itemize
3901
3902
3903 @itemize @bullet
3904 @item int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int)
3905 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{d0}, @var{d0}, #@var{0}}
3906 @end itemize
3907
3908
3909 @itemize @bullet
3910 @item int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int)
3911 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{d0}, @var{d0}, #@var{0}}
3912 @end itemize
3913
3914
3915 @itemize @bullet
3916 @item int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int)
3917 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{d0}, @var{d0}, #@var{0}}
3918 @end itemize
3919
3920
3921 @itemize @bullet
3922 @item uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3923 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{d0}, @var{d0}, #@var{0}}
3924 @end itemize
3925
3926
3927 @itemize @bullet
3928 @item int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int)
3929 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{d0}, @var{d0}, #@var{0}}
3930 @end itemize
3931
3932
3933 @itemize @bullet
3934 @item uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3935 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{q0}, @var{q0}, #@var{0}}
3936 @end itemize
3937
3938
3939 @itemize @bullet
3940 @item uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3941 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{q0}, @var{q0}, #@var{0}}
3942 @end itemize
3943
3944
3945 @itemize @bullet
3946 @item uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3947 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{q0}, @var{q0}, #@var{0}}
3948 @end itemize
3949
3950
3951 @itemize @bullet
3952 @item int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int)
3953 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{q0}, @var{q0}, #@var{0}}
3954 @end itemize
3955
3956
3957 @itemize @bullet
3958 @item int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int)
3959 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{q0}, @var{q0}, #@var{0}}
3960 @end itemize
3961
3962
3963 @itemize @bullet
3964 @item int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int)
3965 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{q0}, @var{q0}, #@var{0}}
3966 @end itemize
3967
3968
3969 @itemize @bullet
3970 @item uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3971 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{q0}, @var{q0}, #@var{0}}
3972 @end itemize
3973
3974
3975 @itemize @bullet
3976 @item int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int)
3977 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{q0}, @var{q0}, #@var{0}}
3978 @end itemize
3979
3980
3981 @itemize @bullet
3982 @item uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3983 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{d0}, @var{d0}, #@var{0}}
3984 @end itemize
3985
3986
3987 @itemize @bullet
3988 @item uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3989 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{d0}, @var{d0}, #@var{0}}
3990 @end itemize
3991
3992
3993 @itemize @bullet
3994 @item uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3995 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{d0}, @var{d0}, #@var{0}}
3996 @end itemize
3997
3998
3999 @itemize @bullet
4000 @item int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int)
4001 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{d0}, @var{d0}, #@var{0}}
4002 @end itemize
4003
4004
4005 @itemize @bullet
4006 @item int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int)
4007 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{d0}, @var{d0}, #@var{0}}
4008 @end itemize
4009
4010
4011 @itemize @bullet
4012 @item int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int)
4013 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{d0}, @var{d0}, #@var{0}}
4014 @end itemize
4015
4016
4017 @itemize @bullet
4018 @item uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int)
4019 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{d0}, @var{d0}, #@var{0}}
4020 @end itemize
4021
4022
4023 @itemize @bullet
4024 @item int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int)
4025 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{d0}, @var{d0}, #@var{0}}
4026 @end itemize
4027
4028
4029 @itemize @bullet
4030 @item uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
4031 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{q0}, @var{q0}, #@var{0}}
4032 @end itemize
4033
4034
4035 @itemize @bullet
4036 @item uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
4037 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{q0}, @var{q0}, #@var{0}}
4038 @end itemize
4039
4040
4041 @itemize @bullet
4042 @item uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
4043 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{q0}, @var{q0}, #@var{0}}
4044 @end itemize
4045
4046
4047 @itemize @bullet
4048 @item int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int)
4049 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{q0}, @var{q0}, #@var{0}}
4050 @end itemize
4051
4052
4053 @itemize @bullet
4054 @item int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int)
4055 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{q0}, @var{q0}, #@var{0}}
4056 @end itemize
4057
4058
4059 @itemize @bullet
4060 @item int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int)
4061 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{q0}, @var{q0}, #@var{0}}
4062 @end itemize
4063
4064
4065 @itemize @bullet
4066 @item uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
4067 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{q0}, @var{q0}, #@var{0}}
4068 @end itemize
4069
4070
4071 @itemize @bullet
4072 @item int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int)
4073 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{q0}, @var{q0}, #@var{0}}
4074 @end itemize
4075
4076
4077
4078
4079 @subsubsection Vector shift right and insert
4080
4081 @itemize @bullet
4082 @item poly64x1_t vsri_n_p64 (poly64x1_t, poly64x1_t, const int)
4083 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4084 @end itemize
4085
4086
4087 @itemize @bullet
4088 @item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
4089 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
4090 @end itemize
4091
4092
4093 @itemize @bullet
4094 @item uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int)
4095 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4096 @end itemize
4097
4098
4099 @itemize @bullet
4100 @item uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int)
4101 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4102 @end itemize
4103
4104
4105 @itemize @bullet
4106 @item int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int)
4107 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
4108 @end itemize
4109
4110
4111 @itemize @bullet
4112 @item int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int)
4113 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4114 @end itemize
4115
4116
4117 @itemize @bullet
4118 @item int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int)
4119 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4120 @end itemize
4121
4122
4123 @itemize @bullet
4124 @item uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int)
4125 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4126 @end itemize
4127
4128
4129 @itemize @bullet
4130 @item int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int)
4131 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4132 @end itemize
4133
4134
4135 @itemize @bullet
4136 @item poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int)
4137 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4138 @end itemize
4139
4140
4141 @itemize @bullet
4142 @item poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int)
4143 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4144 @end itemize
4145
4146
4147 @itemize @bullet
4148 @item poly64x2_t vsriq_n_p64 (poly64x2_t, poly64x2_t, const int)
4149 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4150 @end itemize
4151
4152
4153 @itemize @bullet
4154 @item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
4155 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4156 @end itemize
4157
4158
4159 @itemize @bullet
4160 @item uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int)
4161 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4162 @end itemize
4163
4164
4165 @itemize @bullet
4166 @item uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int)
4167 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4168 @end itemize
4169
4170
4171 @itemize @bullet
4172 @item int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int)
4173 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4174 @end itemize
4175
4176
4177 @itemize @bullet
4178 @item int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int)
4179 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4180 @end itemize
4181
4182
4183 @itemize @bullet
4184 @item int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int)
4185 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4186 @end itemize
4187
4188
4189 @itemize @bullet
4190 @item uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int)
4191 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4192 @end itemize
4193
4194
4195 @itemize @bullet
4196 @item int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int)
4197 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4198 @end itemize
4199
4200
4201 @itemize @bullet
4202 @item poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int)
4203 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4204 @end itemize
4205
4206
4207 @itemize @bullet
4208 @item poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int)
4209 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4210 @end itemize
4211
4212
4213
4214
4215 @subsubsection Vector shift left and insert
4216
4217 @itemize @bullet
4218 @item poly64x1_t vsli_n_p64 (poly64x1_t, poly64x1_t, const int)
4219 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4220 @end itemize
4221
4222
4223 @itemize @bullet
4224 @item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
4225 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4226 @end itemize
4227
4228
4229 @itemize @bullet
4230 @item uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int)
4231 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4232 @end itemize
4233
4234
4235 @itemize @bullet
4236 @item uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int)
4237 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4238 @end itemize
4239
4240
4241 @itemize @bullet
4242 @item int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int)
4243 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4244 @end itemize
4245
4246
4247 @itemize @bullet
4248 @item int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int)
4249 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4250 @end itemize
4251
4252
4253 @itemize @bullet
4254 @item int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int)
4255 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4256 @end itemize
4257
4258
4259 @itemize @bullet
4260 @item uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int)
4261 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4262 @end itemize
4263
4264
4265 @itemize @bullet
4266 @item int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int)
4267 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4268 @end itemize
4269
4270
4271 @itemize @bullet
4272 @item poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int)
4273 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4274 @end itemize
4275
4276
4277 @itemize @bullet
4278 @item poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int)
4279 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4280 @end itemize
4281
4282
4283 @itemize @bullet
4284 @item poly64x2_t vsliq_n_p64 (poly64x2_t, poly64x2_t, const int)
4285 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4286 @end itemize
4287
4288
4289 @itemize @bullet
4290 @item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
4291 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4292 @end itemize
4293
4294
4295 @itemize @bullet
4296 @item uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int)
4297 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4298 @end itemize
4299
4300
4301 @itemize @bullet
4302 @item uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int)
4303 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4304 @end itemize
4305
4306
4307 @itemize @bullet
4308 @item int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int)
4309 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4310 @end itemize
4311
4312
4313 @itemize @bullet
4314 @item int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int)
4315 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4316 @end itemize
4317
4318
4319 @itemize @bullet
4320 @item int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int)
4321 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4322 @end itemize
4323
4324
4325 @itemize @bullet
4326 @item uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int)
4327 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4328 @end itemize
4329
4330
4331 @itemize @bullet
4332 @item int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int)
4333 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4334 @end itemize
4335
4336
4337 @itemize @bullet
4338 @item poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int)
4339 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4340 @end itemize
4341
4342
4343 @itemize @bullet
4344 @item poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int)
4345 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4346 @end itemize
4347
4348
4349
4350
4351 @subsubsection Absolute value
4352
4353 @itemize @bullet
4354 @item float32x2_t vabs_f32 (float32x2_t)
4355 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{d0}, @var{d0}}
4356 @end itemize
4357
4358
4359 @itemize @bullet
4360 @item int32x2_t vabs_s32 (int32x2_t)
4361 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{d0}, @var{d0}}
4362 @end itemize
4363
4364
4365 @itemize @bullet
4366 @item int16x4_t vabs_s16 (int16x4_t)
4367 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{d0}, @var{d0}}
4368 @end itemize
4369
4370
4371 @itemize @bullet
4372 @item int8x8_t vabs_s8 (int8x8_t)
4373 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{d0}, @var{d0}}
4374 @end itemize
4375
4376
4377 @itemize @bullet
4378 @item float32x4_t vabsq_f32 (float32x4_t)
4379 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{q0}, @var{q0}}
4380 @end itemize
4381
4382
4383 @itemize @bullet
4384 @item int32x4_t vabsq_s32 (int32x4_t)
4385 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{q0}, @var{q0}}
4386 @end itemize
4387
4388
4389 @itemize @bullet
4390 @item int16x8_t vabsq_s16 (int16x8_t)
4391 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{q0}, @var{q0}}
4392 @end itemize
4393
4394
4395 @itemize @bullet
4396 @item int8x16_t vabsq_s8 (int8x16_t)
4397 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{q0}, @var{q0}}
4398 @end itemize
4399
4400
4401 @itemize @bullet
4402 @item int32x2_t vqabs_s32 (int32x2_t)
4403 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{d0}, @var{d0}}
4404 @end itemize
4405
4406
4407 @itemize @bullet
4408 @item int16x4_t vqabs_s16 (int16x4_t)
4409 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{d0}, @var{d0}}
4410 @end itemize
4411
4412
4413 @itemize @bullet
4414 @item int8x8_t vqabs_s8 (int8x8_t)
4415 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{d0}, @var{d0}}
4416 @end itemize
4417
4418
4419 @itemize @bullet
4420 @item int32x4_t vqabsq_s32 (int32x4_t)
4421 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{q0}, @var{q0}}
4422 @end itemize
4423
4424
4425 @itemize @bullet
4426 @item int16x8_t vqabsq_s16 (int16x8_t)
4427 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{q0}, @var{q0}}
4428 @end itemize
4429
4430
4431 @itemize @bullet
4432 @item int8x16_t vqabsq_s8 (int8x16_t)
4433 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{q0}, @var{q0}}
4434 @end itemize
4435
4436
4437
4438
4439 @subsubsection Negation
4440
4441 @itemize @bullet
4442 @item float32x2_t vneg_f32 (float32x2_t)
4443 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{d0}, @var{d0}}
4444 @end itemize
4445
4446
4447 @itemize @bullet
4448 @item int32x2_t vneg_s32 (int32x2_t)
4449 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{d0}, @var{d0}}
4450 @end itemize
4451
4452
4453 @itemize @bullet
4454 @item int16x4_t vneg_s16 (int16x4_t)
4455 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{d0}, @var{d0}}
4456 @end itemize
4457
4458
4459 @itemize @bullet
4460 @item int8x8_t vneg_s8 (int8x8_t)
4461 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{d0}, @var{d0}}
4462 @end itemize
4463
4464
4465 @itemize @bullet
4466 @item float32x4_t vnegq_f32 (float32x4_t)
4467 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{q0}, @var{q0}}
4468 @end itemize
4469
4470
4471 @itemize @bullet
4472 @item int32x4_t vnegq_s32 (int32x4_t)
4473 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{q0}, @var{q0}}
4474 @end itemize
4475
4476
4477 @itemize @bullet
4478 @item int16x8_t vnegq_s16 (int16x8_t)
4479 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{q0}, @var{q0}}
4480 @end itemize
4481
4482
4483 @itemize @bullet
4484 @item int8x16_t vnegq_s8 (int8x16_t)
4485 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{q0}, @var{q0}}
4486 @end itemize
4487
4488
4489 @itemize @bullet
4490 @item int32x2_t vqneg_s32 (int32x2_t)
4491 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}}
4492 @end itemize
4493
4494
4495 @itemize @bullet
4496 @item int16x4_t vqneg_s16 (int16x4_t)
4497 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}}
4498 @end itemize
4499
4500
4501 @itemize @bullet
4502 @item int8x8_t vqneg_s8 (int8x8_t)
4503 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}}
4504 @end itemize
4505
4506
4507 @itemize @bullet
4508 @item int32x4_t vqnegq_s32 (int32x4_t)
4509 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}}
4510 @end itemize
4511
4512
4513 @itemize @bullet
4514 @item int16x8_t vqnegq_s16 (int16x8_t)
4515 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}}
4516 @end itemize
4517
4518
4519 @itemize @bullet
4520 @item int8x16_t vqnegq_s8 (int8x16_t)
4521 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}}
4522 @end itemize
4523
4524
4525
4526
4527 @subsubsection Bitwise not
4528
4529 @itemize @bullet
4530 @item uint32x2_t vmvn_u32 (uint32x2_t)
4531 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4532 @end itemize
4533
4534
4535 @itemize @bullet
4536 @item uint16x4_t vmvn_u16 (uint16x4_t)
4537 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4538 @end itemize
4539
4540
4541 @itemize @bullet
4542 @item uint8x8_t vmvn_u8 (uint8x8_t)
4543 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4544 @end itemize
4545
4546
4547 @itemize @bullet
4548 @item int32x2_t vmvn_s32 (int32x2_t)
4549 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4550 @end itemize
4551
4552
4553 @itemize @bullet
4554 @item int16x4_t vmvn_s16 (int16x4_t)
4555 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4556 @end itemize
4557
4558
4559 @itemize @bullet
4560 @item int8x8_t vmvn_s8 (int8x8_t)
4561 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4562 @end itemize
4563
4564
4565 @itemize @bullet
4566 @item poly8x8_t vmvn_p8 (poly8x8_t)
4567 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4568 @end itemize
4569
4570
4571 @itemize @bullet
4572 @item uint32x4_t vmvnq_u32 (uint32x4_t)
4573 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4574 @end itemize
4575
4576
4577 @itemize @bullet
4578 @item uint16x8_t vmvnq_u16 (uint16x8_t)
4579 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4580 @end itemize
4581
4582
4583 @itemize @bullet
4584 @item uint8x16_t vmvnq_u8 (uint8x16_t)
4585 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4586 @end itemize
4587
4588
4589 @itemize @bullet
4590 @item int32x4_t vmvnq_s32 (int32x4_t)
4591 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4592 @end itemize
4593
4594
4595 @itemize @bullet
4596 @item int16x8_t vmvnq_s16 (int16x8_t)
4597 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4598 @end itemize
4599
4600
4601 @itemize @bullet
4602 @item int8x16_t vmvnq_s8 (int8x16_t)
4603 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4604 @end itemize
4605
4606
4607 @itemize @bullet
4608 @item poly8x16_t vmvnq_p8 (poly8x16_t)
4609 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4610 @end itemize
4611
4612
4613
4614
4615 @subsubsection Count leading sign bits
4616
4617 @itemize @bullet
4618 @item int32x2_t vcls_s32 (int32x2_t)
4619 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{d0}, @var{d0}}
4620 @end itemize
4621
4622
4623 @itemize @bullet
4624 @item int16x4_t vcls_s16 (int16x4_t)
4625 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{d0}, @var{d0}}
4626 @end itemize
4627
4628
4629 @itemize @bullet
4630 @item int8x8_t vcls_s8 (int8x8_t)
4631 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{d0}, @var{d0}}
4632 @end itemize
4633
4634
4635 @itemize @bullet
4636 @item int32x4_t vclsq_s32 (int32x4_t)
4637 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{q0}, @var{q0}}
4638 @end itemize
4639
4640
4641 @itemize @bullet
4642 @item int16x8_t vclsq_s16 (int16x8_t)
4643 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{q0}, @var{q0}}
4644 @end itemize
4645
4646
4647 @itemize @bullet
4648 @item int8x16_t vclsq_s8 (int8x16_t)
4649 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{q0}, @var{q0}}
4650 @end itemize
4651
4652
4653
4654
4655 @subsubsection Count leading zeros
4656
4657 @itemize @bullet
4658 @item uint32x2_t vclz_u32 (uint32x2_t)
4659 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4660 @end itemize
4661
4662
4663 @itemize @bullet
4664 @item uint16x4_t vclz_u16 (uint16x4_t)
4665 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4666 @end itemize
4667
4668
4669 @itemize @bullet
4670 @item uint8x8_t vclz_u8 (uint8x8_t)
4671 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4672 @end itemize
4673
4674
4675 @itemize @bullet
4676 @item int32x2_t vclz_s32 (int32x2_t)
4677 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4678 @end itemize
4679
4680
4681 @itemize @bullet
4682 @item int16x4_t vclz_s16 (int16x4_t)
4683 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4684 @end itemize
4685
4686
4687 @itemize @bullet
4688 @item int8x8_t vclz_s8 (int8x8_t)
4689 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4690 @end itemize
4691
4692
4693 @itemize @bullet
4694 @item uint32x4_t vclzq_u32 (uint32x4_t)
4695 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4696 @end itemize
4697
4698
4699 @itemize @bullet
4700 @item uint16x8_t vclzq_u16 (uint16x8_t)
4701 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4702 @end itemize
4703
4704
4705 @itemize @bullet
4706 @item uint8x16_t vclzq_u8 (uint8x16_t)
4707 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4708 @end itemize
4709
4710
4711 @itemize @bullet
4712 @item int32x4_t vclzq_s32 (int32x4_t)
4713 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4714 @end itemize
4715
4716
4717 @itemize @bullet
4718 @item int16x8_t vclzq_s16 (int16x8_t)
4719 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4720 @end itemize
4721
4722
4723 @itemize @bullet
4724 @item int8x16_t vclzq_s8 (int8x16_t)
4725 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4726 @end itemize
4727
4728
4729
4730
4731 @subsubsection Count number of set bits
4732
4733 @itemize @bullet
4734 @item uint8x8_t vcnt_u8 (uint8x8_t)
4735 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4736 @end itemize
4737
4738
4739 @itemize @bullet
4740 @item int8x8_t vcnt_s8 (int8x8_t)
4741 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4742 @end itemize
4743
4744
4745 @itemize @bullet
4746 @item poly8x8_t vcnt_p8 (poly8x8_t)
4747 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4748 @end itemize
4749
4750
4751 @itemize @bullet
4752 @item uint8x16_t vcntq_u8 (uint8x16_t)
4753 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4754 @end itemize
4755
4756
4757 @itemize @bullet
4758 @item int8x16_t vcntq_s8 (int8x16_t)
4759 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4760 @end itemize
4761
4762
4763 @itemize @bullet
4764 @item poly8x16_t vcntq_p8 (poly8x16_t)
4765 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4766 @end itemize
4767
4768
4769
4770
4771 @subsubsection Reciprocal estimate
4772
4773 @itemize @bullet
4774 @item float32x2_t vrecpe_f32 (float32x2_t)
4775 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{d0}, @var{d0}}
4776 @end itemize
4777
4778
4779 @itemize @bullet
4780 @item uint32x2_t vrecpe_u32 (uint32x2_t)
4781 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{d0}, @var{d0}}
4782 @end itemize
4783
4784
4785 @itemize @bullet
4786 @item float32x4_t vrecpeq_f32 (float32x4_t)
4787 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{q0}, @var{q0}}
4788 @end itemize
4789
4790
4791 @itemize @bullet
4792 @item uint32x4_t vrecpeq_u32 (uint32x4_t)
4793 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{q0}, @var{q0}}
4794 @end itemize
4795
4796
4797
4798
4799 @subsubsection Reciprocal square-root estimate
4800
4801 @itemize @bullet
4802 @item float32x2_t vrsqrte_f32 (float32x2_t)
4803 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{d0}, @var{d0}}
4804 @end itemize
4805
4806
4807 @itemize @bullet
4808 @item uint32x2_t vrsqrte_u32 (uint32x2_t)
4809 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{d0}, @var{d0}}
4810 @end itemize
4811
4812
4813 @itemize @bullet
4814 @item float32x4_t vrsqrteq_f32 (float32x4_t)
4815 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{q0}, @var{q0}}
4816 @end itemize
4817
4818
4819 @itemize @bullet
4820 @item uint32x4_t vrsqrteq_u32 (uint32x4_t)
4821 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{q0}, @var{q0}}
4822 @end itemize
4823
4824
4825
4826
4827 @subsubsection Get lanes from a vector
4828
4829 @itemize @bullet
4830 @item uint32_t vget_lane_u32 (uint32x2_t, const int)
4831 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4832 @end itemize
4833
4834
4835 @itemize @bullet
4836 @item uint16_t vget_lane_u16 (uint16x4_t, const int)
4837 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4838 @end itemize
4839
4840
4841 @itemize @bullet
4842 @item uint8_t vget_lane_u8 (uint8x8_t, const int)
4843 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4844 @end itemize
4845
4846
4847 @itemize @bullet
4848 @item int32_t vget_lane_s32 (int32x2_t, const int)
4849 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4850 @end itemize
4851
4852
4853 @itemize @bullet
4854 @item int16_t vget_lane_s16 (int16x4_t, const int)
4855 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4856 @end itemize
4857
4858
4859 @itemize @bullet
4860 @item int8_t vget_lane_s8 (int8x8_t, const int)
4861 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4862 @end itemize
4863
4864
4865 @itemize @bullet
4866 @item float32_t vget_lane_f32 (float32x2_t, const int)
4867 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4868 @end itemize
4869
4870
4871 @itemize @bullet
4872 @item poly16_t vget_lane_p16 (poly16x4_t, const int)
4873 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4874 @end itemize
4875
4876
4877 @itemize @bullet
4878 @item poly8_t vget_lane_p8 (poly8x8_t, const int)
4879 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4880 @end itemize
4881
4882
4883 @itemize @bullet
4884 @item uint64_t vget_lane_u64 (uint64x1_t, const int)
4885 @end itemize
4886
4887
4888 @itemize @bullet
4889 @item int64_t vget_lane_s64 (int64x1_t, const int)
4890 @end itemize
4891
4892
4893 @itemize @bullet
4894 @item uint32_t vgetq_lane_u32 (uint32x4_t, const int)
4895 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4896 @end itemize
4897
4898
4899 @itemize @bullet
4900 @item uint16_t vgetq_lane_u16 (uint16x8_t, const int)
4901 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4902 @end itemize
4903
4904
4905 @itemize @bullet
4906 @item uint8_t vgetq_lane_u8 (uint8x16_t, const int)
4907 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4908 @end itemize
4909
4910
4911 @itemize @bullet
4912 @item int32_t vgetq_lane_s32 (int32x4_t, const int)
4913 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4914 @end itemize
4915
4916
4917 @itemize @bullet
4918 @item int16_t vgetq_lane_s16 (int16x8_t, const int)
4919 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4920 @end itemize
4921
4922
4923 @itemize @bullet
4924 @item int8_t vgetq_lane_s8 (int8x16_t, const int)
4925 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4926 @end itemize
4927
4928
4929 @itemize @bullet
4930 @item float32_t vgetq_lane_f32 (float32x4_t, const int)
4931 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4932 @end itemize
4933
4934
4935 @itemize @bullet
4936 @item poly16_t vgetq_lane_p16 (poly16x8_t, const int)
4937 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4938 @end itemize
4939
4940
4941 @itemize @bullet
4942 @item poly8_t vgetq_lane_p8 (poly8x16_t, const int)
4943 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4944 @end itemize
4945
4946
4947 @itemize @bullet
4948 @item uint64_t vgetq_lane_u64 (uint64x2_t, const int)
4949 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}}
4950 @end itemize
4951
4952
4953 @itemize @bullet
4954 @item int64_t vgetq_lane_s64 (int64x2_t, const int)
4955 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}} @emph{or} @code{fmrrd @var{r0}, @var{r0}, @var{d0}}
4956 @end itemize
4957
4958
4959
4960
4961 @subsubsection Set lanes in a vector
4962
4963 @itemize @bullet
4964 @item uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int)
4965 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4966 @end itemize
4967
4968
4969 @itemize @bullet
4970 @item uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int)
4971 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4972 @end itemize
4973
4974
4975 @itemize @bullet
4976 @item uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int)
4977 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4978 @end itemize
4979
4980
4981 @itemize @bullet
4982 @item int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int)
4983 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4984 @end itemize
4985
4986
4987 @itemize @bullet
4988 @item int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int)
4989 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4990 @end itemize
4991
4992
4993 @itemize @bullet
4994 @item int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int)
4995 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4996 @end itemize
4997
4998
4999 @itemize @bullet
5000 @item float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int)
5001 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5002 @end itemize
5003
5004
5005 @itemize @bullet
5006 @item poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int)
5007 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5008 @end itemize
5009
5010
5011 @itemize @bullet
5012 @item poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int)
5013 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5014 @end itemize
5015
5016
5017 @itemize @bullet
5018 @item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
5019 @end itemize
5020
5021
5022 @itemize @bullet
5023 @item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
5024 @end itemize
5025
5026
5027 @itemize @bullet
5028 @item uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int)
5029 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5030 @end itemize
5031
5032
5033 @itemize @bullet
5034 @item uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int)
5035 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5036 @end itemize
5037
5038
5039 @itemize @bullet
5040 @item uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int)
5041 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5042 @end itemize
5043
5044
5045 @itemize @bullet
5046 @item int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int)
5047 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5048 @end itemize
5049
5050
5051 @itemize @bullet
5052 @item int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int)
5053 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5054 @end itemize
5055
5056
5057 @itemize @bullet
5058 @item int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int)
5059 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5060 @end itemize
5061
5062
5063 @itemize @bullet
5064 @item float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int)
5065 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
5066 @end itemize
5067
5068
5069 @itemize @bullet
5070 @item poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int)
5071 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
5072 @end itemize
5073
5074
5075 @itemize @bullet
5076 @item poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int)
5077 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
5078 @end itemize
5079
5080
5081 @itemize @bullet
5082 @item uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int)
5083 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5084 @end itemize
5085
5086
5087 @itemize @bullet
5088 @item int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int)
5089 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
5090 @end itemize
5091
5092
5093
5094
5095 @subsubsection Create vector from literal bit pattern
5096
5097 @itemize @bullet
5098 @item poly64x1_t vcreate_p64 (uint64_t)
5099 @end itemize
5100
5101
5102 @itemize @bullet
5103 @item uint32x2_t vcreate_u32 (uint64_t)
5104 @end itemize
5105
5106
5107 @itemize @bullet
5108 @item uint16x4_t vcreate_u16 (uint64_t)
5109 @end itemize
5110
5111
5112 @itemize @bullet
5113 @item uint8x8_t vcreate_u8 (uint64_t)
5114 @end itemize
5115
5116
5117 @itemize @bullet
5118 @item int32x2_t vcreate_s32 (uint64_t)
5119 @end itemize
5120
5121
5122 @itemize @bullet
5123 @item int16x4_t vcreate_s16 (uint64_t)
5124 @end itemize
5125
5126
5127 @itemize @bullet
5128 @item int8x8_t vcreate_s8 (uint64_t)
5129 @end itemize
5130
5131
5132 @itemize @bullet
5133 @item uint64x1_t vcreate_u64 (uint64_t)
5134 @end itemize
5135
5136
5137 @itemize @bullet
5138 @item int64x1_t vcreate_s64 (uint64_t)
5139 @end itemize
5140
5141
5142 @itemize @bullet
5143 @item float32x2_t vcreate_f32 (uint64_t)
5144 @end itemize
5145
5146
5147 @itemize @bullet
5148 @item poly16x4_t vcreate_p16 (uint64_t)
5149 @end itemize
5150
5151
5152 @itemize @bullet
5153 @item poly8x8_t vcreate_p8 (uint64_t)
5154 @end itemize
5155
5156
5157
5158
5159 @subsubsection Set all lanes to the same value
5160
5161 @itemize @bullet
5162 @item uint32x2_t vdup_n_u32 (uint32_t)
5163 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5164 @end itemize
5165
5166
5167 @itemize @bullet
5168 @item uint16x4_t vdup_n_u16 (uint16_t)
5169 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5170 @end itemize
5171
5172
5173 @itemize @bullet
5174 @item uint8x8_t vdup_n_u8 (uint8_t)
5175 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5176 @end itemize
5177
5178
5179 @itemize @bullet
5180 @item int32x2_t vdup_n_s32 (int32_t)
5181 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5182 @end itemize
5183
5184
5185 @itemize @bullet
5186 @item int16x4_t vdup_n_s16 (int16_t)
5187 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5188 @end itemize
5189
5190
5191 @itemize @bullet
5192 @item int8x8_t vdup_n_s8 (int8_t)
5193 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5194 @end itemize
5195
5196
5197 @itemize @bullet
5198 @item float32x2_t vdup_n_f32 (float32_t)
5199 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5200 @end itemize
5201
5202
5203 @itemize @bullet
5204 @item poly16x4_t vdup_n_p16 (poly16_t)
5205 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5206 @end itemize
5207
5208
5209 @itemize @bullet
5210 @item poly8x8_t vdup_n_p8 (poly8_t)
5211 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5212 @end itemize
5213
5214
5215 @itemize @bullet
5216 @item poly64x1_t vdup_n_p64 (poly64_t)
5217 @end itemize
5218
5219
5220 @itemize @bullet
5221 @item uint64x1_t vdup_n_u64 (uint64_t)
5222 @end itemize
5223
5224
5225 @itemize @bullet
5226 @item int64x1_t vdup_n_s64 (int64_t)
5227 @end itemize
5228
5229
5230 @itemize @bullet
5231 @item poly64x2_t vdupq_n_p64 (poly64_t)
5232 @end itemize
5233
5234
5235 @itemize @bullet
5236 @item uint32x4_t vdupq_n_u32 (uint32_t)
5237 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5238 @end itemize
5239
5240
5241 @itemize @bullet
5242 @item uint16x8_t vdupq_n_u16 (uint16_t)
5243 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5244 @end itemize
5245
5246
5247 @itemize @bullet
5248 @item uint8x16_t vdupq_n_u8 (uint8_t)
5249 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5250 @end itemize
5251
5252
5253 @itemize @bullet
5254 @item int32x4_t vdupq_n_s32 (int32_t)
5255 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5256 @end itemize
5257
5258
5259 @itemize @bullet
5260 @item int16x8_t vdupq_n_s16 (int16_t)
5261 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5262 @end itemize
5263
5264
5265 @itemize @bullet
5266 @item int8x16_t vdupq_n_s8 (int8_t)
5267 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5268 @end itemize
5269
5270
5271 @itemize @bullet
5272 @item float32x4_t vdupq_n_f32 (float32_t)
5273 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5274 @end itemize
5275
5276
5277 @itemize @bullet
5278 @item poly16x8_t vdupq_n_p16 (poly16_t)
5279 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5280 @end itemize
5281
5282
5283 @itemize @bullet
5284 @item poly8x16_t vdupq_n_p8 (poly8_t)
5285 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5286 @end itemize
5287
5288
5289 @itemize @bullet
5290 @item uint64x2_t vdupq_n_u64 (uint64_t)
5291 @end itemize
5292
5293
5294 @itemize @bullet
5295 @item int64x2_t vdupq_n_s64 (int64_t)
5296 @end itemize
5297
5298
5299 @itemize @bullet
5300 @item uint32x2_t vmov_n_u32 (uint32_t)
5301 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5302 @end itemize
5303
5304
5305 @itemize @bullet
5306 @item uint16x4_t vmov_n_u16 (uint16_t)
5307 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5308 @end itemize
5309
5310
5311 @itemize @bullet
5312 @item uint8x8_t vmov_n_u8 (uint8_t)
5313 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5314 @end itemize
5315
5316
5317 @itemize @bullet
5318 @item int32x2_t vmov_n_s32 (int32_t)
5319 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5320 @end itemize
5321
5322
5323 @itemize @bullet
5324 @item int16x4_t vmov_n_s16 (int16_t)
5325 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5326 @end itemize
5327
5328
5329 @itemize @bullet
5330 @item int8x8_t vmov_n_s8 (int8_t)
5331 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5332 @end itemize
5333
5334
5335 @itemize @bullet
5336 @item float32x2_t vmov_n_f32 (float32_t)
5337 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5338 @end itemize
5339
5340
5341 @itemize @bullet
5342 @item poly16x4_t vmov_n_p16 (poly16_t)
5343 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5344 @end itemize
5345
5346
5347 @itemize @bullet
5348 @item poly8x8_t vmov_n_p8 (poly8_t)
5349 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5350 @end itemize
5351
5352
5353 @itemize @bullet
5354 @item uint64x1_t vmov_n_u64 (uint64_t)
5355 @end itemize
5356
5357
5358 @itemize @bullet
5359 @item int64x1_t vmov_n_s64 (int64_t)
5360 @end itemize
5361
5362
5363 @itemize @bullet
5364 @item uint32x4_t vmovq_n_u32 (uint32_t)
5365 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5366 @end itemize
5367
5368
5369 @itemize @bullet
5370 @item uint16x8_t vmovq_n_u16 (uint16_t)
5371 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5372 @end itemize
5373
5374
5375 @itemize @bullet
5376 @item uint8x16_t vmovq_n_u8 (uint8_t)
5377 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5378 @end itemize
5379
5380
5381 @itemize @bullet
5382 @item int32x4_t vmovq_n_s32 (int32_t)
5383 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5384 @end itemize
5385
5386
5387 @itemize @bullet
5388 @item int16x8_t vmovq_n_s16 (int16_t)
5389 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5390 @end itemize
5391
5392
5393 @itemize @bullet
5394 @item int8x16_t vmovq_n_s8 (int8_t)
5395 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5396 @end itemize
5397
5398
5399 @itemize @bullet
5400 @item float32x4_t vmovq_n_f32 (float32_t)
5401 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5402 @end itemize
5403
5404
5405 @itemize @bullet
5406 @item poly16x8_t vmovq_n_p16 (poly16_t)
5407 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5408 @end itemize
5409
5410
5411 @itemize @bullet
5412 @item poly8x16_t vmovq_n_p8 (poly8_t)
5413 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5414 @end itemize
5415
5416
5417 @itemize @bullet
5418 @item uint64x2_t vmovq_n_u64 (uint64_t)
5419 @end itemize
5420
5421
5422 @itemize @bullet
5423 @item int64x2_t vmovq_n_s64 (int64_t)
5424 @end itemize
5425
5426
5427 @itemize @bullet
5428 @item uint32x2_t vdup_lane_u32 (uint32x2_t, const int)
5429 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5430 @end itemize
5431
5432
5433 @itemize @bullet
5434 @item uint16x4_t vdup_lane_u16 (uint16x4_t, const int)
5435 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5436 @end itemize
5437
5438
5439 @itemize @bullet
5440 @item uint8x8_t vdup_lane_u8 (uint8x8_t, const int)
5441 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5442 @end itemize
5443
5444
5445 @itemize @bullet
5446 @item int32x2_t vdup_lane_s32 (int32x2_t, const int)
5447 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5448 @end itemize
5449
5450
5451 @itemize @bullet
5452 @item int16x4_t vdup_lane_s16 (int16x4_t, const int)
5453 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5454 @end itemize
5455
5456
5457 @itemize @bullet
5458 @item int8x8_t vdup_lane_s8 (int8x8_t, const int)
5459 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5460 @end itemize
5461
5462
5463 @itemize @bullet
5464 @item float32x2_t vdup_lane_f32 (float32x2_t, const int)
5465 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5466 @end itemize
5467
5468
5469 @itemize @bullet
5470 @item poly16x4_t vdup_lane_p16 (poly16x4_t, const int)
5471 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5472 @end itemize
5473
5474
5475 @itemize @bullet
5476 @item poly8x8_t vdup_lane_p8 (poly8x8_t, const int)
5477 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5478 @end itemize
5479
5480
5481 @itemize @bullet
5482 @item poly64x1_t vdup_lane_p64 (poly64x1_t, const int)
5483 @end itemize
5484
5485
5486 @itemize @bullet
5487 @item uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
5488 @end itemize
5489
5490
5491 @itemize @bullet
5492 @item int64x1_t vdup_lane_s64 (int64x1_t, const int)
5493 @end itemize
5494
5495
5496 @itemize @bullet
5497 @item uint32x4_t vdupq_lane_u32 (uint32x2_t, const int)
5498 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5499 @end itemize
5500
5501
5502 @itemize @bullet
5503 @item uint16x8_t vdupq_lane_u16 (uint16x4_t, const int)
5504 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5505 @end itemize
5506
5507
5508 @itemize @bullet
5509 @item uint8x16_t vdupq_lane_u8 (uint8x8_t, const int)
5510 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5511 @end itemize
5512
5513
5514 @itemize @bullet
5515 @item int32x4_t vdupq_lane_s32 (int32x2_t, const int)
5516 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5517 @end itemize
5518
5519
5520 @itemize @bullet
5521 @item int16x8_t vdupq_lane_s16 (int16x4_t, const int)
5522 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5523 @end itemize
5524
5525
5526 @itemize @bullet
5527 @item int8x16_t vdupq_lane_s8 (int8x8_t, const int)
5528 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5529 @end itemize
5530
5531
5532 @itemize @bullet
5533 @item float32x4_t vdupq_lane_f32 (float32x2_t, const int)
5534 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5535 @end itemize
5536
5537
5538 @itemize @bullet
5539 @item poly16x8_t vdupq_lane_p16 (poly16x4_t, const int)
5540 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5541 @end itemize
5542
5543
5544 @itemize @bullet
5545 @item poly8x16_t vdupq_lane_p8 (poly8x8_t, const int)
5546 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5547 @end itemize
5548
5549
5550 @itemize @bullet
5551 @item poly64x2_t vdupq_lane_p64 (poly64x1_t, const int)
5552 @end itemize
5553
5554
5555 @itemize @bullet
5556 @item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
5557 @end itemize
5558
5559
5560 @itemize @bullet
5561 @item int64x2_t vdupq_lane_s64 (int64x1_t, const int)
5562 @end itemize
5563
5564
5565
5566
5567 @subsubsection Combining vectors
5568
5569 @itemize @bullet
5570 @item poly64x2_t vcombine_p64 (poly64x1_t, poly64x1_t)
5571 @end itemize
5572
5573
5574 @itemize @bullet
5575 @item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
5576 @end itemize
5577
5578
5579 @itemize @bullet
5580 @item uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t)
5581 @end itemize
5582
5583
5584 @itemize @bullet
5585 @item uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t)
5586 @end itemize
5587
5588
5589 @itemize @bullet
5590 @item int32x4_t vcombine_s32 (int32x2_t, int32x2_t)
5591 @end itemize
5592
5593
5594 @itemize @bullet
5595 @item int16x8_t vcombine_s16 (int16x4_t, int16x4_t)
5596 @end itemize
5597
5598
5599 @itemize @bullet
5600 @item int8x16_t vcombine_s8 (int8x8_t, int8x8_t)
5601 @end itemize
5602
5603
5604 @itemize @bullet
5605 @item uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t)
5606 @end itemize
5607
5608
5609 @itemize @bullet
5610 @item int64x2_t vcombine_s64 (int64x1_t, int64x1_t)
5611 @end itemize
5612
5613
5614 @itemize @bullet
5615 @item float32x4_t vcombine_f32 (float32x2_t, float32x2_t)
5616 @end itemize
5617
5618
5619 @itemize @bullet
5620 @item poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t)
5621 @end itemize
5622
5623
5624 @itemize @bullet
5625 @item poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t)
5626 @end itemize
5627
5628
5629
5630
5631 @subsubsection Splitting vectors
5632
5633 @itemize @bullet
5634 @item poly64x1_t vget_high_p64 (poly64x2_t)
5635 @end itemize
5636
5637
5638 @itemize @bullet
5639 @item uint32x2_t vget_high_u32 (uint32x4_t)
5640 @end itemize
5641
5642
5643 @itemize @bullet
5644 @item uint16x4_t vget_high_u16 (uint16x8_t)
5645 @end itemize
5646
5647
5648 @itemize @bullet
5649 @item uint8x8_t vget_high_u8 (uint8x16_t)
5650 @end itemize
5651
5652
5653 @itemize @bullet
5654 @item int32x2_t vget_high_s32 (int32x4_t)
5655 @end itemize
5656
5657
5658 @itemize @bullet
5659 @item int16x4_t vget_high_s16 (int16x8_t)
5660 @end itemize
5661
5662
5663 @itemize @bullet
5664 @item int8x8_t vget_high_s8 (int8x16_t)
5665 @end itemize
5666
5667
5668 @itemize @bullet
5669 @item uint64x1_t vget_high_u64 (uint64x2_t)
5670 @end itemize
5671
5672
5673 @itemize @bullet
5674 @item int64x1_t vget_high_s64 (int64x2_t)
5675 @end itemize
5676
5677
5678 @itemize @bullet
5679 @item float32x2_t vget_high_f32 (float32x4_t)
5680 @end itemize
5681
5682
5683 @itemize @bullet
5684 @item poly16x4_t vget_high_p16 (poly16x8_t)
5685 @end itemize
5686
5687
5688 @itemize @bullet
5689 @item poly8x8_t vget_high_p8 (poly8x16_t)
5690 @end itemize
5691
5692
5693 @itemize @bullet
5694 @item uint32x2_t vget_low_u32 (uint32x4_t)
5695 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5696 @end itemize
5697
5698
5699 @itemize @bullet
5700 @item uint16x4_t vget_low_u16 (uint16x8_t)
5701 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5702 @end itemize
5703
5704
5705 @itemize @bullet
5706 @item uint8x8_t vget_low_u8 (uint8x16_t)
5707 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5708 @end itemize
5709
5710
5711 @itemize @bullet
5712 @item int32x2_t vget_low_s32 (int32x4_t)
5713 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5714 @end itemize
5715
5716
5717 @itemize @bullet
5718 @item int16x4_t vget_low_s16 (int16x8_t)
5719 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5720 @end itemize
5721
5722
5723 @itemize @bullet
5724 @item int8x8_t vget_low_s8 (int8x16_t)
5725 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5726 @end itemize
5727
5728
5729 @itemize @bullet
5730 @item float32x2_t vget_low_f32 (float32x4_t)
5731 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5732 @end itemize
5733
5734
5735 @itemize @bullet
5736 @item poly16x4_t vget_low_p16 (poly16x8_t)
5737 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5738 @end itemize
5739
5740
5741 @itemize @bullet
5742 @item poly8x8_t vget_low_p8 (poly8x16_t)
5743 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5744 @end itemize
5745
5746
5747 @itemize @bullet
5748 @item poly64x1_t vget_low_p64 (poly64x2_t)
5749 @end itemize
5750
5751
5752 @itemize @bullet
5753 @item uint64x1_t vget_low_u64 (uint64x2_t)
5754 @end itemize
5755
5756
5757 @itemize @bullet
5758 @item int64x1_t vget_low_s64 (int64x2_t)
5759 @end itemize
5760
5761
5762
5763
5764 @subsubsection Conversions
5765
5766 @itemize @bullet
5767 @item float32x2_t vcvt_f32_u32 (uint32x2_t)
5768 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}}
5769 @end itemize
5770
5771
5772 @itemize @bullet
5773 @item float32x2_t vcvt_f32_s32 (int32x2_t)
5774 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}}
5775 @end itemize
5776
5777
5778 @itemize @bullet
5779 @item uint32x2_t vcvt_u32_f32 (float32x2_t)
5780 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}}
5781 @end itemize
5782
5783
5784 @itemize @bullet
5785 @item int32x2_t vcvt_s32_f32 (float32x2_t)
5786 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}}
5787 @end itemize
5788
5789
5790 @itemize @bullet
5791 @item float32x4_t vcvtq_f32_u32 (uint32x4_t)
5792 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}}
5793 @end itemize
5794
5795
5796 @itemize @bullet
5797 @item float32x4_t vcvtq_f32_s32 (int32x4_t)
5798 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}}
5799 @end itemize
5800
5801
5802 @itemize @bullet
5803 @item uint32x4_t vcvtq_u32_f32 (float32x4_t)
5804 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}}
5805 @end itemize
5806
5807
5808 @itemize @bullet
5809 @item int32x4_t vcvtq_s32_f32 (float32x4_t)
5810 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}}
5811 @end itemize
5812
5813
5814 @itemize @bullet
5815 @item float16x4_t vcvt_f16_f32 (float32x4_t)
5816 @*@emph{Form of expected instruction(s):} @code{vcvt.f16.f32 @var{d0}, @var{q0}}
5817 @end itemize
5818
5819
5820 @itemize @bullet
5821 @item float32x4_t vcvt_f32_f16 (float16x4_t)
5822 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.f16 @var{q0}, @var{d0}}
5823 @end itemize
5824
5825
5826 @itemize @bullet
5827 @item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
5828 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
5829 @end itemize
5830
5831
5832 @itemize @bullet
5833 @item float32x2_t vcvt_n_f32_s32 (int32x2_t, const int)
5834 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}, #@var{0}}
5835 @end itemize
5836
5837
5838 @itemize @bullet
5839 @item uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int)
5840 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}, #@var{0}}
5841 @end itemize
5842
5843
5844 @itemize @bullet
5845 @item int32x2_t vcvt_n_s32_f32 (float32x2_t, const int)
5846 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}, #@var{0}}
5847 @end itemize
5848
5849
5850 @itemize @bullet
5851 @item float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int)
5852 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}, #@var{0}}
5853 @end itemize
5854
5855
5856 @itemize @bullet
5857 @item float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int)
5858 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}, #@var{0}}
5859 @end itemize
5860
5861
5862 @itemize @bullet
5863 @item uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int)
5864 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}, #@var{0}}
5865 @end itemize
5866
5867
5868 @itemize @bullet
5869 @item int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int)
5870 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}, #@var{0}}
5871 @end itemize
5872
5873
5874
5875
5876 @subsubsection Move, single_opcode narrowing
5877
5878 @itemize @bullet
5879 @item uint32x2_t vmovn_u64 (uint64x2_t)
5880 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5881 @end itemize
5882
5883
5884 @itemize @bullet
5885 @item uint16x4_t vmovn_u32 (uint32x4_t)
5886 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5887 @end itemize
5888
5889
5890 @itemize @bullet
5891 @item uint8x8_t vmovn_u16 (uint16x8_t)
5892 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5893 @end itemize
5894
5895
5896 @itemize @bullet
5897 @item int32x2_t vmovn_s64 (int64x2_t)
5898 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5899 @end itemize
5900
5901
5902 @itemize @bullet
5903 @item int16x4_t vmovn_s32 (int32x4_t)
5904 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5905 @end itemize
5906
5907
5908 @itemize @bullet
5909 @item int8x8_t vmovn_s16 (int16x8_t)
5910 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5911 @end itemize
5912
5913
5914 @itemize @bullet
5915 @item uint32x2_t vqmovn_u64 (uint64x2_t)
5916 @*@emph{Form of expected instruction(s):} @code{vqmovn.u64 @var{d0}, @var{q0}}
5917 @end itemize
5918
5919
5920 @itemize @bullet
5921 @item uint16x4_t vqmovn_u32 (uint32x4_t)
5922 @*@emph{Form of expected instruction(s):} @code{vqmovn.u32 @var{d0}, @var{q0}}
5923 @end itemize
5924
5925
5926 @itemize @bullet
5927 @item uint8x8_t vqmovn_u16 (uint16x8_t)
5928 @*@emph{Form of expected instruction(s):} @code{vqmovn.u16 @var{d0}, @var{q0}}
5929 @end itemize
5930
5931
5932 @itemize @bullet
5933 @item int32x2_t vqmovn_s64 (int64x2_t)
5934 @*@emph{Form of expected instruction(s):} @code{vqmovn.s64 @var{d0}, @var{q0}}
5935 @end itemize
5936
5937
5938 @itemize @bullet
5939 @item int16x4_t vqmovn_s32 (int32x4_t)
5940 @*@emph{Form of expected instruction(s):} @code{vqmovn.s32 @var{d0}, @var{q0}}
5941 @end itemize
5942
5943
5944 @itemize @bullet
5945 @item int8x8_t vqmovn_s16 (int16x8_t)
5946 @*@emph{Form of expected instruction(s):} @code{vqmovn.s16 @var{d0}, @var{q0}}
5947 @end itemize
5948
5949
5950 @itemize @bullet
5951 @item uint32x2_t vqmovun_s64 (int64x2_t)
5952 @*@emph{Form of expected instruction(s):} @code{vqmovun.s64 @var{d0}, @var{q0}}
5953 @end itemize
5954
5955
5956 @itemize @bullet
5957 @item uint16x4_t vqmovun_s32 (int32x4_t)
5958 @*@emph{Form of expected instruction(s):} @code{vqmovun.s32 @var{d0}, @var{q0}}
5959 @end itemize
5960
5961
5962 @itemize @bullet
5963 @item uint8x8_t vqmovun_s16 (int16x8_t)
5964 @*@emph{Form of expected instruction(s):} @code{vqmovun.s16 @var{d0}, @var{q0}}
5965 @end itemize
5966
5967
5968
5969
5970 @subsubsection Move, single_opcode long
5971
5972 @itemize @bullet
5973 @item uint64x2_t vmovl_u32 (uint32x2_t)
5974 @*@emph{Form of expected instruction(s):} @code{vmovl.u32 @var{q0}, @var{d0}}
5975 @end itemize
5976
5977
5978 @itemize @bullet
5979 @item uint32x4_t vmovl_u16 (uint16x4_t)
5980 @*@emph{Form of expected instruction(s):} @code{vmovl.u16 @var{q0}, @var{d0}}
5981 @end itemize
5982
5983
5984 @itemize @bullet
5985 @item uint16x8_t vmovl_u8 (uint8x8_t)
5986 @*@emph{Form of expected instruction(s):} @code{vmovl.u8 @var{q0}, @var{d0}}
5987 @end itemize
5988
5989
5990 @itemize @bullet
5991 @item int64x2_t vmovl_s32 (int32x2_t)
5992 @*@emph{Form of expected instruction(s):} @code{vmovl.s32 @var{q0}, @var{d0}}
5993 @end itemize
5994
5995
5996 @itemize @bullet
5997 @item int32x4_t vmovl_s16 (int16x4_t)
5998 @*@emph{Form of expected instruction(s):} @code{vmovl.s16 @var{q0}, @var{d0}}
5999 @end itemize
6000
6001
6002 @itemize @bullet
6003 @item int16x8_t vmovl_s8 (int8x8_t)
6004 @*@emph{Form of expected instruction(s):} @code{vmovl.s8 @var{q0}, @var{d0}}
6005 @end itemize
6006
6007
6008
6009
6010 @subsubsection Table lookup
6011
6012 @itemize @bullet
6013 @item poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t)
6014 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6015 @end itemize
6016
6017
6018 @itemize @bullet
6019 @item int8x8_t vtbl1_s8 (int8x8_t, int8x8_t)
6020 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6021 @end itemize
6022
6023
6024 @itemize @bullet
6025 @item uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t)
6026 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6027 @end itemize
6028
6029
6030 @itemize @bullet
6031 @item poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t)
6032 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6033 @end itemize
6034
6035
6036 @itemize @bullet
6037 @item int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t)
6038 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6039 @end itemize
6040
6041
6042 @itemize @bullet
6043 @item uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t)
6044 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6045 @end itemize
6046
6047
6048 @itemize @bullet
6049 @item poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t)
6050 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6051 @end itemize
6052
6053
6054 @itemize @bullet
6055 @item int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t)
6056 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6057 @end itemize
6058
6059
6060 @itemize @bullet
6061 @item uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t)
6062 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6063 @end itemize
6064
6065
6066 @itemize @bullet
6067 @item poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t)
6068 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6069 @end itemize
6070
6071
6072 @itemize @bullet
6073 @item int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t)
6074 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6075 @end itemize
6076
6077
6078 @itemize @bullet
6079 @item uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t)
6080 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6081 @end itemize
6082
6083
6084
6085
6086 @subsubsection Extended table lookup
6087
6088 @itemize @bullet
6089 @item poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t)
6090 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6091 @end itemize
6092
6093
6094 @itemize @bullet
6095 @item int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t)
6096 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6097 @end itemize
6098
6099
6100 @itemize @bullet
6101 @item uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
6102 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
6103 @end itemize
6104
6105
6106 @itemize @bullet
6107 @item poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t)
6108 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6109 @end itemize
6110
6111
6112 @itemize @bullet
6113 @item int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t)
6114 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6115 @end itemize
6116
6117
6118 @itemize @bullet
6119 @item uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t)
6120 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
6121 @end itemize
6122
6123
6124 @itemize @bullet
6125 @item poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t)
6126 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6127 @end itemize
6128
6129
6130 @itemize @bullet
6131 @item int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t)
6132 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6133 @end itemize
6134
6135
6136 @itemize @bullet
6137 @item uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t)
6138 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
6139 @end itemize
6140
6141
6142 @itemize @bullet
6143 @item poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t)
6144 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6145 @end itemize
6146
6147
6148 @itemize @bullet
6149 @item int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t)
6150 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6151 @end itemize
6152
6153
6154 @itemize @bullet
6155 @item uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t)
6156 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
6157 @end itemize
6158
6159
6160
6161
6162 @subsubsection Multiply, lane
6163
6164 @itemize @bullet
6165 @item float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int)
6166 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6167 @end itemize
6168
6169
6170 @itemize @bullet
6171 @item uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int)
6172 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6173 @end itemize
6174
6175
6176 @itemize @bullet
6177 @item uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int)
6178 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6179 @end itemize
6180
6181
6182 @itemize @bullet
6183 @item int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int)
6184 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6185 @end itemize
6186
6187
6188 @itemize @bullet
6189 @item int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int)
6190 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6191 @end itemize
6192
6193
6194 @itemize @bullet
6195 @item float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int)
6196 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6197 @end itemize
6198
6199
6200 @itemize @bullet
6201 @item uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int)
6202 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6203 @end itemize
6204
6205
6206 @itemize @bullet
6207 @item uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int)
6208 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6209 @end itemize
6210
6211
6212 @itemize @bullet
6213 @item int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int)
6214 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6215 @end itemize
6216
6217
6218 @itemize @bullet
6219 @item int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int)
6220 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6221 @end itemize
6222
6223
6224
6225
6226 @subsubsection Long multiply, lane
6227
6228 @itemize @bullet
6229 @item uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int)
6230 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6231 @end itemize
6232
6233
6234 @itemize @bullet
6235 @item uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int)
6236 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6237 @end itemize
6238
6239
6240 @itemize @bullet
6241 @item int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int)
6242 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6243 @end itemize
6244
6245
6246 @itemize @bullet
6247 @item int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int)
6248 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6249 @end itemize
6250
6251
6252
6253
6254 @subsubsection Saturating doubling long multiply, lane
6255
6256 @itemize @bullet
6257 @item int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int)
6258 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6259 @end itemize
6260
6261
6262 @itemize @bullet
6263 @item int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int)
6264 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6265 @end itemize
6266
6267
6268
6269
6270 @subsubsection Saturating doubling multiply high, lane
6271
6272 @itemize @bullet
6273 @item int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6274 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6275 @end itemize
6276
6277
6278 @itemize @bullet
6279 @item int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6280 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6281 @end itemize
6282
6283
6284 @itemize @bullet
6285 @item int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6286 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6287 @end itemize
6288
6289
6290 @itemize @bullet
6291 @item int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6292 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6293 @end itemize
6294
6295
6296 @itemize @bullet
6297 @item int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6298 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6299 @end itemize
6300
6301
6302 @itemize @bullet
6303 @item int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6304 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6305 @end itemize
6306
6307
6308 @itemize @bullet
6309 @item int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6310 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6311 @end itemize
6312
6313
6314 @itemize @bullet
6315 @item int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6316 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6317 @end itemize
6318
6319
6320
6321
6322 @subsubsection Multiply-accumulate, lane
6323
6324 @itemize @bullet
6325 @item float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6326 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6327 @end itemize
6328
6329
6330 @itemize @bullet
6331 @item uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6332 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6333 @end itemize
6334
6335
6336 @itemize @bullet
6337 @item uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6338 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6339 @end itemize
6340
6341
6342 @itemize @bullet
6343 @item int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6344 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6345 @end itemize
6346
6347
6348 @itemize @bullet
6349 @item int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6350 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6351 @end itemize
6352
6353
6354 @itemize @bullet
6355 @item float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6356 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6357 @end itemize
6358
6359
6360 @itemize @bullet
6361 @item uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6362 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6363 @end itemize
6364
6365
6366 @itemize @bullet
6367 @item uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6368 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6369 @end itemize
6370
6371
6372 @itemize @bullet
6373 @item int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6374 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6375 @end itemize
6376
6377
6378 @itemize @bullet
6379 @item int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6380 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6381 @end itemize
6382
6383
6384 @itemize @bullet
6385 @item uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6386 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6387 @end itemize
6388
6389
6390 @itemize @bullet
6391 @item uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6392 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6393 @end itemize
6394
6395
6396 @itemize @bullet
6397 @item int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6398 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6399 @end itemize
6400
6401
6402 @itemize @bullet
6403 @item int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6404 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6405 @end itemize
6406
6407
6408 @itemize @bullet
6409 @item int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6410 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6411 @end itemize
6412
6413
6414 @itemize @bullet
6415 @item int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6416 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6417 @end itemize
6418
6419
6420
6421
6422 @subsubsection Multiply-subtract, lane
6423
6424 @itemize @bullet
6425 @item float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6426 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6427 @end itemize
6428
6429
6430 @itemize @bullet
6431 @item uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6432 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6433 @end itemize
6434
6435
6436 @itemize @bullet
6437 @item uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6438 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6439 @end itemize
6440
6441
6442 @itemize @bullet
6443 @item int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6444 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6445 @end itemize
6446
6447
6448 @itemize @bullet
6449 @item int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6450 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6451 @end itemize
6452
6453
6454 @itemize @bullet
6455 @item float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6456 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6457 @end itemize
6458
6459
6460 @itemize @bullet
6461 @item uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6462 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6463 @end itemize
6464
6465
6466 @itemize @bullet
6467 @item uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6468 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6469 @end itemize
6470
6471
6472 @itemize @bullet
6473 @item int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6474 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6475 @end itemize
6476
6477
6478 @itemize @bullet
6479 @item int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6480 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6481 @end itemize
6482
6483
6484 @itemize @bullet
6485 @item uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6486 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6487 @end itemize
6488
6489
6490 @itemize @bullet
6491 @item uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6492 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6493 @end itemize
6494
6495
6496 @itemize @bullet
6497 @item int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6498 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6499 @end itemize
6500
6501
6502 @itemize @bullet
6503 @item int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6504 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6505 @end itemize
6506
6507
6508 @itemize @bullet
6509 @item int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6510 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6511 @end itemize
6512
6513
6514 @itemize @bullet
6515 @item int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6516 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6517 @end itemize
6518
6519
6520
6521
6522 @subsubsection Vector multiply by scalar
6523
6524 @itemize @bullet
6525 @item float32x2_t vmul_n_f32 (float32x2_t, float32_t)
6526 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6527 @end itemize
6528
6529
6530 @itemize @bullet
6531 @item uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t)
6532 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6533 @end itemize
6534
6535
6536 @itemize @bullet
6537 @item uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t)
6538 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6539 @end itemize
6540
6541
6542 @itemize @bullet
6543 @item int32x2_t vmul_n_s32 (int32x2_t, int32_t)
6544 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6545 @end itemize
6546
6547
6548 @itemize @bullet
6549 @item int16x4_t vmul_n_s16 (int16x4_t, int16_t)
6550 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6551 @end itemize
6552
6553
6554 @itemize @bullet
6555 @item float32x4_t vmulq_n_f32 (float32x4_t, float32_t)
6556 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6557 @end itemize
6558
6559
6560 @itemize @bullet
6561 @item uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t)
6562 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6563 @end itemize
6564
6565
6566 @itemize @bullet
6567 @item uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t)
6568 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6569 @end itemize
6570
6571
6572 @itemize @bullet
6573 @item int32x4_t vmulq_n_s32 (int32x4_t, int32_t)
6574 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6575 @end itemize
6576
6577
6578 @itemize @bullet
6579 @item int16x8_t vmulq_n_s16 (int16x8_t, int16_t)
6580 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6581 @end itemize
6582
6583
6584
6585
6586 @subsubsection Vector long multiply by scalar
6587
6588 @itemize @bullet
6589 @item uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t)
6590 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6591 @end itemize
6592
6593
6594 @itemize @bullet
6595 @item uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t)
6596 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6597 @end itemize
6598
6599
6600 @itemize @bullet
6601 @item int64x2_t vmull_n_s32 (int32x2_t, int32_t)
6602 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6603 @end itemize
6604
6605
6606 @itemize @bullet
6607 @item int32x4_t vmull_n_s16 (int16x4_t, int16_t)
6608 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6609 @end itemize
6610
6611
6612
6613
6614 @subsubsection Vector saturating doubling long multiply by scalar
6615
6616 @itemize @bullet
6617 @item int64x2_t vqdmull_n_s32 (int32x2_t, int32_t)
6618 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6619 @end itemize
6620
6621
6622 @itemize @bullet
6623 @item int32x4_t vqdmull_n_s16 (int16x4_t, int16_t)
6624 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6625 @end itemize
6626
6627
6628
6629
6630 @subsubsection Vector saturating doubling multiply high by scalar
6631
6632 @itemize @bullet
6633 @item int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t)
6634 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6635 @end itemize
6636
6637
6638 @itemize @bullet
6639 @item int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t)
6640 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6641 @end itemize
6642
6643
6644 @itemize @bullet
6645 @item int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t)
6646 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6647 @end itemize
6648
6649
6650 @itemize @bullet
6651 @item int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t)
6652 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6653 @end itemize
6654
6655
6656 @itemize @bullet
6657 @item int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t)
6658 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6659 @end itemize
6660
6661
6662 @itemize @bullet
6663 @item int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t)
6664 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6665 @end itemize
6666
6667
6668 @itemize @bullet
6669 @item int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t)
6670 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6671 @end itemize
6672
6673
6674 @itemize @bullet
6675 @item int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t)
6676 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6677 @end itemize
6678
6679
6680
6681
6682 @subsubsection Vector multiply-accumulate by scalar
6683
6684 @itemize @bullet
6685 @item float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t)
6686 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6687 @end itemize
6688
6689
6690 @itemize @bullet
6691 @item uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6692 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6693 @end itemize
6694
6695
6696 @itemize @bullet
6697 @item uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6698 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6699 @end itemize
6700
6701
6702 @itemize @bullet
6703 @item int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t)
6704 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6705 @end itemize
6706
6707
6708 @itemize @bullet
6709 @item int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t)
6710 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6711 @end itemize
6712
6713
6714 @itemize @bullet
6715 @item float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t)
6716 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6717 @end itemize
6718
6719
6720 @itemize @bullet
6721 @item uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6722 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6723 @end itemize
6724
6725
6726 @itemize @bullet
6727 @item uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6728 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6729 @end itemize
6730
6731
6732 @itemize @bullet
6733 @item int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t)
6734 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6735 @end itemize
6736
6737
6738 @itemize @bullet
6739 @item int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t)
6740 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6741 @end itemize
6742
6743
6744 @itemize @bullet
6745 @item uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6746 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6747 @end itemize
6748
6749
6750 @itemize @bullet
6751 @item uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6752 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6753 @end itemize
6754
6755
6756 @itemize @bullet
6757 @item int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6758 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6759 @end itemize
6760
6761
6762 @itemize @bullet
6763 @item int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6764 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6765 @end itemize
6766
6767
6768 @itemize @bullet
6769 @item int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6770 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6771 @end itemize
6772
6773
6774 @itemize @bullet
6775 @item int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6776 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6777 @end itemize
6778
6779
6780
6781
6782 @subsubsection Vector multiply-subtract by scalar
6783
6784 @itemize @bullet
6785 @item float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t)
6786 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6787 @end itemize
6788
6789
6790 @itemize @bullet
6791 @item uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6792 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6793 @end itemize
6794
6795
6796 @itemize @bullet
6797 @item uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6798 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6799 @end itemize
6800
6801
6802 @itemize @bullet
6803 @item int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t)
6804 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6805 @end itemize
6806
6807
6808 @itemize @bullet
6809 @item int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t)
6810 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6811 @end itemize
6812
6813
6814 @itemize @bullet
6815 @item float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t)
6816 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6817 @end itemize
6818
6819
6820 @itemize @bullet
6821 @item uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6822 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6823 @end itemize
6824
6825
6826 @itemize @bullet
6827 @item uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6828 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6829 @end itemize
6830
6831
6832 @itemize @bullet
6833 @item int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t)
6834 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6835 @end itemize
6836
6837
6838 @itemize @bullet
6839 @item int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t)
6840 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6841 @end itemize
6842
6843
6844 @itemize @bullet
6845 @item uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6846 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6847 @end itemize
6848
6849
6850 @itemize @bullet
6851 @item uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6852 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6853 @end itemize
6854
6855
6856 @itemize @bullet
6857 @item int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6858 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6859 @end itemize
6860
6861
6862 @itemize @bullet
6863 @item int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6864 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6865 @end itemize
6866
6867
6868 @itemize @bullet
6869 @item int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6870 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6871 @end itemize
6872
6873
6874 @itemize @bullet
6875 @item int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6876 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6877 @end itemize
6878
6879
6880
6881
6882 @subsubsection Vector extract
6883
6884 @itemize @bullet
6885 @item poly64x1_t vext_p64 (poly64x1_t, poly64x1_t, const int)
6886 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6887 @end itemize
6888
6889
6890 @itemize @bullet
6891 @item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
6892 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6893 @end itemize
6894
6895
6896 @itemize @bullet
6897 @item uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int)
6898 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6899 @end itemize
6900
6901
6902 @itemize @bullet
6903 @item uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int)
6904 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6905 @end itemize
6906
6907
6908 @itemize @bullet
6909 @item int32x2_t vext_s32 (int32x2_t, int32x2_t, const int)
6910 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6911 @end itemize
6912
6913
6914 @itemize @bullet
6915 @item int16x4_t vext_s16 (int16x4_t, int16x4_t, const int)
6916 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6917 @end itemize
6918
6919
6920 @itemize @bullet
6921 @item int8x8_t vext_s8 (int8x8_t, int8x8_t, const int)
6922 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6923 @end itemize
6924
6925
6926 @itemize @bullet
6927 @item uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int)
6928 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6929 @end itemize
6930
6931
6932 @itemize @bullet
6933 @item int64x1_t vext_s64 (int64x1_t, int64x1_t, const int)
6934 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6935 @end itemize
6936
6937
6938 @itemize @bullet
6939 @item float32x2_t vext_f32 (float32x2_t, float32x2_t, const int)
6940 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6941 @end itemize
6942
6943
6944 @itemize @bullet
6945 @item poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int)
6946 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6947 @end itemize
6948
6949
6950 @itemize @bullet
6951 @item poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int)
6952 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6953 @end itemize
6954
6955
6956 @itemize @bullet
6957 @item poly64x2_t vextq_p64 (poly64x2_t, poly64x2_t, const int)
6958 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6959 @end itemize
6960
6961
6962 @itemize @bullet
6963 @item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
6964 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6965 @end itemize
6966
6967
6968 @itemize @bullet
6969 @item uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int)
6970 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6971 @end itemize
6972
6973
6974 @itemize @bullet
6975 @item uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int)
6976 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6977 @end itemize
6978
6979
6980 @itemize @bullet
6981 @item int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int)
6982 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6983 @end itemize
6984
6985
6986 @itemize @bullet
6987 @item int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int)
6988 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6989 @end itemize
6990
6991
6992 @itemize @bullet
6993 @item int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int)
6994 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6995 @end itemize
6996
6997
6998 @itemize @bullet
6999 @item uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int)
7000 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
7001 @end itemize
7002
7003
7004 @itemize @bullet
7005 @item int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int)
7006 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
7007 @end itemize
7008
7009
7010 @itemize @bullet
7011 @item float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int)
7012 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
7013 @end itemize
7014
7015
7016 @itemize @bullet
7017 @item poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int)
7018 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
7019 @end itemize
7020
7021
7022 @itemize @bullet
7023 @item poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int)
7024 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
7025 @end itemize
7026
7027
7028
7029
7030 @subsubsection Reverse elements
7031
7032 @itemize @bullet
7033 @item uint32x2_t vrev64_u32 (uint32x2_t)
7034 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
7035 @end itemize
7036
7037
7038 @itemize @bullet
7039 @item uint16x4_t vrev64_u16 (uint16x4_t)
7040 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
7041 @end itemize
7042
7043
7044 @itemize @bullet
7045 @item uint8x8_t vrev64_u8 (uint8x8_t)
7046 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
7047 @end itemize
7048
7049
7050 @itemize @bullet
7051 @item int32x2_t vrev64_s32 (int32x2_t)
7052 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
7053 @end itemize
7054
7055
7056 @itemize @bullet
7057 @item int16x4_t vrev64_s16 (int16x4_t)
7058 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
7059 @end itemize
7060
7061
7062 @itemize @bullet
7063 @item int8x8_t vrev64_s8 (int8x8_t)
7064 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
7065 @end itemize
7066
7067
7068 @itemize @bullet
7069 @item float32x2_t vrev64_f32 (float32x2_t)
7070 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
7071 @end itemize
7072
7073
7074 @itemize @bullet
7075 @item poly16x4_t vrev64_p16 (poly16x4_t)
7076 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
7077 @end itemize
7078
7079
7080 @itemize @bullet
7081 @item poly8x8_t vrev64_p8 (poly8x8_t)
7082 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
7083 @end itemize
7084
7085
7086 @itemize @bullet
7087 @item uint32x4_t vrev64q_u32 (uint32x4_t)
7088 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
7089 @end itemize
7090
7091
7092 @itemize @bullet
7093 @item uint16x8_t vrev64q_u16 (uint16x8_t)
7094 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
7095 @end itemize
7096
7097
7098 @itemize @bullet
7099 @item uint8x16_t vrev64q_u8 (uint8x16_t)
7100 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
7101 @end itemize
7102
7103
7104 @itemize @bullet
7105 @item int32x4_t vrev64q_s32 (int32x4_t)
7106 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
7107 @end itemize
7108
7109
7110 @itemize @bullet
7111 @item int16x8_t vrev64q_s16 (int16x8_t)
7112 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
7113 @end itemize
7114
7115
7116 @itemize @bullet
7117 @item int8x16_t vrev64q_s8 (int8x16_t)
7118 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
7119 @end itemize
7120
7121
7122 @itemize @bullet
7123 @item float32x4_t vrev64q_f32 (float32x4_t)
7124 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
7125 @end itemize
7126
7127
7128 @itemize @bullet
7129 @item poly16x8_t vrev64q_p16 (poly16x8_t)
7130 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
7131 @end itemize
7132
7133
7134 @itemize @bullet
7135 @item poly8x16_t vrev64q_p8 (poly8x16_t)
7136 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
7137 @end itemize
7138
7139
7140 @itemize @bullet
7141 @item uint16x4_t vrev32_u16 (uint16x4_t)
7142 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
7143 @end itemize
7144
7145
7146 @itemize @bullet
7147 @item int16x4_t vrev32_s16 (int16x4_t)
7148 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
7149 @end itemize
7150
7151
7152 @itemize @bullet
7153 @item uint8x8_t vrev32_u8 (uint8x8_t)
7154 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
7155 @end itemize
7156
7157
7158 @itemize @bullet
7159 @item int8x8_t vrev32_s8 (int8x8_t)
7160 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
7161 @end itemize
7162
7163
7164 @itemize @bullet
7165 @item poly16x4_t vrev32_p16 (poly16x4_t)
7166 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
7167 @end itemize
7168
7169
7170 @itemize @bullet
7171 @item poly8x8_t vrev32_p8 (poly8x8_t)
7172 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
7173 @end itemize
7174
7175
7176 @itemize @bullet
7177 @item uint16x8_t vrev32q_u16 (uint16x8_t)
7178 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7179 @end itemize
7180
7181
7182 @itemize @bullet
7183 @item int16x8_t vrev32q_s16 (int16x8_t)
7184 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7185 @end itemize
7186
7187
7188 @itemize @bullet
7189 @item uint8x16_t vrev32q_u8 (uint8x16_t)
7190 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7191 @end itemize
7192
7193
7194 @itemize @bullet
7195 @item int8x16_t vrev32q_s8 (int8x16_t)
7196 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7197 @end itemize
7198
7199
7200 @itemize @bullet
7201 @item poly16x8_t vrev32q_p16 (poly16x8_t)
7202 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7203 @end itemize
7204
7205
7206 @itemize @bullet
7207 @item poly8x16_t vrev32q_p8 (poly8x16_t)
7208 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7209 @end itemize
7210
7211
7212 @itemize @bullet
7213 @item uint8x8_t vrev16_u8 (uint8x8_t)
7214 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7215 @end itemize
7216
7217
7218 @itemize @bullet
7219 @item int8x8_t vrev16_s8 (int8x8_t)
7220 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7221 @end itemize
7222
7223
7224 @itemize @bullet
7225 @item poly8x8_t vrev16_p8 (poly8x8_t)
7226 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7227 @end itemize
7228
7229
7230 @itemize @bullet
7231 @item uint8x16_t vrev16q_u8 (uint8x16_t)
7232 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7233 @end itemize
7234
7235
7236 @itemize @bullet
7237 @item int8x16_t vrev16q_s8 (int8x16_t)
7238 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7239 @end itemize
7240
7241
7242 @itemize @bullet
7243 @item poly8x16_t vrev16q_p8 (poly8x16_t)
7244 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7245 @end itemize
7246
7247
7248
7249
7250 @subsubsection Bit selection
7251
7252 @itemize @bullet
7253 @item poly64x1_t vbsl_p64 (uint64x1_t, poly64x1_t, poly64x1_t)
7254 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7255 @end itemize
7256
7257
7258 @itemize @bullet
7259 @item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
7260 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7261 @end itemize
7262
7263
7264 @itemize @bullet
7265 @item uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
7266 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7267 @end itemize
7268
7269
7270 @itemize @bullet
7271 @item uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
7272 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7273 @end itemize
7274
7275
7276 @itemize @bullet
7277 @item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
7278 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7279 @end itemize
7280
7281
7282 @itemize @bullet
7283 @item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
7284 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7285 @end itemize
7286
7287
7288 @itemize @bullet
7289 @item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
7290 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7291 @end itemize
7292
7293
7294 @itemize @bullet
7295 @item uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t)
7296 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7297 @end itemize
7298
7299
7300 @itemize @bullet
7301 @item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
7302 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7303 @end itemize
7304
7305
7306 @itemize @bullet
7307 @item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
7308 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7309 @end itemize
7310
7311
7312 @itemize @bullet
7313 @item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
7314 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7315 @end itemize
7316
7317
7318 @itemize @bullet
7319 @item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
7320 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7321 @end itemize
7322
7323
7324 @itemize @bullet
7325 @item poly64x2_t vbslq_p64 (uint64x2_t, poly64x2_t, poly64x2_t)
7326 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7327 @end itemize
7328
7329
7330 @itemize @bullet
7331 @item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
7332 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7333 @end itemize
7334
7335
7336 @itemize @bullet
7337 @item uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
7338 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7339 @end itemize
7340
7341
7342 @itemize @bullet
7343 @item uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
7344 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7345 @end itemize
7346
7347
7348 @itemize @bullet
7349 @item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
7350 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7351 @end itemize
7352
7353
7354 @itemize @bullet
7355 @item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
7356 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7357 @end itemize
7358
7359
7360 @itemize @bullet
7361 @item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
7362 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7363 @end itemize
7364
7365
7366 @itemize @bullet
7367 @item uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t)
7368 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7369 @end itemize
7370
7371
7372 @itemize @bullet
7373 @item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
7374 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7375 @end itemize
7376
7377
7378 @itemize @bullet
7379 @item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
7380 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7381 @end itemize
7382
7383
7384 @itemize @bullet
7385 @item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
7386 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7387 @end itemize
7388
7389
7390 @itemize @bullet
7391 @item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
7392 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7393 @end itemize
7394
7395
7396
7397
7398 @subsubsection Transpose elements
7399
7400 @itemize @bullet
7401 @item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
7402 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7403 @end itemize
7404
7405
7406 @itemize @bullet
7407 @item uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t)
7408 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7409 @end itemize
7410
7411
7412 @itemize @bullet
7413 @item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
7414 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7415 @end itemize
7416
7417
7418 @itemize @bullet
7419 @item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
7420 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7421 @end itemize
7422
7423
7424 @itemize @bullet
7425 @item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
7426 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7427 @end itemize
7428
7429
7430 @itemize @bullet
7431 @item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
7432 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7433 @end itemize
7434
7435
7436 @itemize @bullet
7437 @item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
7438 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7439 @end itemize
7440
7441
7442 @itemize @bullet
7443 @item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
7444 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7445 @end itemize
7446
7447
7448 @itemize @bullet
7449 @item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
7450 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7451 @end itemize
7452
7453
7454 @itemize @bullet
7455 @item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
7456 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7457 @end itemize
7458
7459
7460 @itemize @bullet
7461 @item uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t)
7462 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7463 @end itemize
7464
7465
7466 @itemize @bullet
7467 @item uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t)
7468 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7469 @end itemize
7470
7471
7472 @itemize @bullet
7473 @item int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t)
7474 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7475 @end itemize
7476
7477
7478 @itemize @bullet
7479 @item int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t)
7480 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7481 @end itemize
7482
7483
7484 @itemize @bullet
7485 @item int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t)
7486 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7487 @end itemize
7488
7489
7490 @itemize @bullet
7491 @item float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t)
7492 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7493 @end itemize
7494
7495
7496 @itemize @bullet
7497 @item poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t)
7498 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7499 @end itemize
7500
7501
7502 @itemize @bullet
7503 @item poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t)
7504 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7505 @end itemize
7506
7507
7508
7509
7510 @subsubsection Zip elements
7511
7512 @itemize @bullet
7513 @item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
7514 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7515 @end itemize
7516
7517
7518 @itemize @bullet
7519 @item uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t)
7520 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7521 @end itemize
7522
7523
7524 @itemize @bullet
7525 @item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
7526 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7527 @end itemize
7528
7529
7530 @itemize @bullet
7531 @item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
7532 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7533 @end itemize
7534
7535
7536 @itemize @bullet
7537 @item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
7538 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7539 @end itemize
7540
7541
7542 @itemize @bullet
7543 @item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
7544 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7545 @end itemize
7546
7547
7548 @itemize @bullet
7549 @item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
7550 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7551 @end itemize
7552
7553
7554 @itemize @bullet
7555 @item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
7556 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7557 @end itemize
7558
7559
7560 @itemize @bullet
7561 @item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
7562 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7563 @end itemize
7564
7565
7566 @itemize @bullet
7567 @item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
7568 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7569 @end itemize
7570
7571
7572 @itemize @bullet
7573 @item uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t)
7574 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7575 @end itemize
7576
7577
7578 @itemize @bullet
7579 @item uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t)
7580 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7581 @end itemize
7582
7583
7584 @itemize @bullet
7585 @item int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t)
7586 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7587 @end itemize
7588
7589
7590 @itemize @bullet
7591 @item int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t)
7592 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7593 @end itemize
7594
7595
7596 @itemize @bullet
7597 @item int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t)
7598 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7599 @end itemize
7600
7601
7602 @itemize @bullet
7603 @item float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t)
7604 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7605 @end itemize
7606
7607
7608 @itemize @bullet
7609 @item poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t)
7610 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7611 @end itemize
7612
7613
7614 @itemize @bullet
7615 @item poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t)
7616 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7617 @end itemize
7618
7619
7620
7621
7622 @subsubsection Unzip elements
7623
7624 @itemize @bullet
7625 @item uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t)
7626 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7627 @end itemize
7628
7629
7630 @itemize @bullet
7631 @item uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t)
7632 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7633 @end itemize
7634
7635
7636 @itemize @bullet
7637 @item uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t)
7638 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7639 @end itemize
7640
7641
7642 @itemize @bullet
7643 @item int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t)
7644 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7645 @end itemize
7646
7647
7648 @itemize @bullet
7649 @item int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t)
7650 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7651 @end itemize
7652
7653
7654 @itemize @bullet
7655 @item int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t)
7656 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7657 @end itemize
7658
7659
7660 @itemize @bullet
7661 @item float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t)
7662 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7663 @end itemize
7664
7665
7666 @itemize @bullet
7667 @item poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t)
7668 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7669 @end itemize
7670
7671
7672 @itemize @bullet
7673 @item poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t)
7674 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7675 @end itemize
7676
7677
7678 @itemize @bullet
7679 @item uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t)
7680 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7681 @end itemize
7682
7683
7684 @itemize @bullet
7685 @item uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t)
7686 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7687 @end itemize
7688
7689
7690 @itemize @bullet
7691 @item uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t)
7692 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7693 @end itemize
7694
7695
7696 @itemize @bullet
7697 @item int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t)
7698 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7699 @end itemize
7700
7701
7702 @itemize @bullet
7703 @item int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t)
7704 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7705 @end itemize
7706
7707
7708 @itemize @bullet
7709 @item int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t)
7710 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7711 @end itemize
7712
7713
7714 @itemize @bullet
7715 @item float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t)
7716 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7717 @end itemize
7718
7719
7720 @itemize @bullet
7721 @item poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t)
7722 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7723 @end itemize
7724
7725
7726 @itemize @bullet
7727 @item poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t)
7728 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7729 @end itemize
7730
7731
7732
7733
7734 @subsubsection Element/structure loads, VLD1 variants
7735
7736 @itemize @bullet
7737 @item poly64x1_t vld1_p64 (const poly64_t *)
7738 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7739 @end itemize
7740
7741
7742 @itemize @bullet
7743 @item uint32x2_t vld1_u32 (const uint32_t *)
7744 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7745 @end itemize
7746
7747
7748 @itemize @bullet
7749 @item uint16x4_t vld1_u16 (const uint16_t *)
7750 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7751 @end itemize
7752
7753
7754 @itemize @bullet
7755 @item uint8x8_t vld1_u8 (const uint8_t *)
7756 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7757 @end itemize
7758
7759
7760 @itemize @bullet
7761 @item int32x2_t vld1_s32 (const int32_t *)
7762 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7763 @end itemize
7764
7765
7766 @itemize @bullet
7767 @item int16x4_t vld1_s16 (const int16_t *)
7768 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7769 @end itemize
7770
7771
7772 @itemize @bullet
7773 @item int8x8_t vld1_s8 (const int8_t *)
7774 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7775 @end itemize
7776
7777
7778 @itemize @bullet
7779 @item uint64x1_t vld1_u64 (const uint64_t *)
7780 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7781 @end itemize
7782
7783
7784 @itemize @bullet
7785 @item int64x1_t vld1_s64 (const int64_t *)
7786 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7787 @end itemize
7788
7789
7790 @itemize @bullet
7791 @item float32x2_t vld1_f32 (const float32_t *)
7792 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7793 @end itemize
7794
7795
7796 @itemize @bullet
7797 @item poly16x4_t vld1_p16 (const poly16_t *)
7798 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7799 @end itemize
7800
7801
7802 @itemize @bullet
7803 @item poly8x8_t vld1_p8 (const poly8_t *)
7804 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7805 @end itemize
7806
7807
7808 @itemize @bullet
7809 @item poly64x2_t vld1q_p64 (const poly64_t *)
7810 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7811 @end itemize
7812
7813
7814 @itemize @bullet
7815 @item uint32x4_t vld1q_u32 (const uint32_t *)
7816 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7817 @end itemize
7818
7819
7820 @itemize @bullet
7821 @item uint16x8_t vld1q_u16 (const uint16_t *)
7822 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7823 @end itemize
7824
7825
7826 @itemize @bullet
7827 @item uint8x16_t vld1q_u8 (const uint8_t *)
7828 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7829 @end itemize
7830
7831
7832 @itemize @bullet
7833 @item int32x4_t vld1q_s32 (const int32_t *)
7834 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7835 @end itemize
7836
7837
7838 @itemize @bullet
7839 @item int16x8_t vld1q_s16 (const int16_t *)
7840 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7841 @end itemize
7842
7843
7844 @itemize @bullet
7845 @item int8x16_t vld1q_s8 (const int8_t *)
7846 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7847 @end itemize
7848
7849
7850 @itemize @bullet
7851 @item uint64x2_t vld1q_u64 (const uint64_t *)
7852 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7853 @end itemize
7854
7855
7856 @itemize @bullet
7857 @item int64x2_t vld1q_s64 (const int64_t *)
7858 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7859 @end itemize
7860
7861
7862 @itemize @bullet
7863 @item float32x4_t vld1q_f32 (const float32_t *)
7864 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7865 @end itemize
7866
7867
7868 @itemize @bullet
7869 @item poly16x8_t vld1q_p16 (const poly16_t *)
7870 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7871 @end itemize
7872
7873
7874 @itemize @bullet
7875 @item poly8x16_t vld1q_p8 (const poly8_t *)
7876 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7877 @end itemize
7878
7879
7880 @itemize @bullet
7881 @item uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int)
7882 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7883 @end itemize
7884
7885
7886 @itemize @bullet
7887 @item uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int)
7888 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7889 @end itemize
7890
7891
7892 @itemize @bullet
7893 @item uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int)
7894 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7895 @end itemize
7896
7897
7898 @itemize @bullet
7899 @item int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int)
7900 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7901 @end itemize
7902
7903
7904 @itemize @bullet
7905 @item int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int)
7906 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7907 @end itemize
7908
7909
7910 @itemize @bullet
7911 @item int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int)
7912 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7913 @end itemize
7914
7915
7916 @itemize @bullet
7917 @item float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int)
7918 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7919 @end itemize
7920
7921
7922 @itemize @bullet
7923 @item poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int)
7924 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7925 @end itemize
7926
7927
7928 @itemize @bullet
7929 @item poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int)
7930 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7931 @end itemize
7932
7933
7934 @itemize @bullet
7935 @item poly64x1_t vld1_lane_p64 (const poly64_t *, poly64x1_t, const int)
7936 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7937 @end itemize
7938
7939
7940 @itemize @bullet
7941 @item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
7942 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7943 @end itemize
7944
7945
7946 @itemize @bullet
7947 @item int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int)
7948 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7949 @end itemize
7950
7951
7952 @itemize @bullet
7953 @item uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int)
7954 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7955 @end itemize
7956
7957
7958 @itemize @bullet
7959 @item uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int)
7960 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7961 @end itemize
7962
7963
7964 @itemize @bullet
7965 @item uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int)
7966 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7967 @end itemize
7968
7969
7970 @itemize @bullet
7971 @item int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int)
7972 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7973 @end itemize
7974
7975
7976 @itemize @bullet
7977 @item int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int)
7978 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7979 @end itemize
7980
7981
7982 @itemize @bullet
7983 @item int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int)
7984 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7985 @end itemize
7986
7987
7988 @itemize @bullet
7989 @item float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int)
7990 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7991 @end itemize
7992
7993
7994 @itemize @bullet
7995 @item poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int)
7996 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7997 @end itemize
7998
7999
8000 @itemize @bullet
8001 @item poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int)
8002 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8003 @end itemize
8004
8005
8006 @itemize @bullet
8007 @item poly64x2_t vld1q_lane_p64 (const poly64_t *, poly64x2_t, const int)
8008 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8009 @end itemize
8010
8011
8012 @itemize @bullet
8013 @item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
8014 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8015 @end itemize
8016
8017
8018 @itemize @bullet
8019 @item int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int)
8020 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8021 @end itemize
8022
8023
8024 @itemize @bullet
8025 @item uint32x2_t vld1_dup_u32 (const uint32_t *)
8026 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
8027 @end itemize
8028
8029
8030 @itemize @bullet
8031 @item uint16x4_t vld1_dup_u16 (const uint16_t *)
8032 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
8033 @end itemize
8034
8035
8036 @itemize @bullet
8037 @item uint8x8_t vld1_dup_u8 (const uint8_t *)
8038 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
8039 @end itemize
8040
8041
8042 @itemize @bullet
8043 @item int32x2_t vld1_dup_s32 (const int32_t *)
8044 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
8045 @end itemize
8046
8047
8048 @itemize @bullet
8049 @item int16x4_t vld1_dup_s16 (const int16_t *)
8050 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
8051 @end itemize
8052
8053
8054 @itemize @bullet
8055 @item int8x8_t vld1_dup_s8 (const int8_t *)
8056 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
8057 @end itemize
8058
8059
8060 @itemize @bullet
8061 @item float32x2_t vld1_dup_f32 (const float32_t *)
8062 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
8063 @end itemize
8064
8065
8066 @itemize @bullet
8067 @item poly16x4_t vld1_dup_p16 (const poly16_t *)
8068 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
8069 @end itemize
8070
8071
8072 @itemize @bullet
8073 @item poly8x8_t vld1_dup_p8 (const poly8_t *)
8074 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
8075 @end itemize
8076
8077
8078 @itemize @bullet
8079 @item poly64x1_t vld1_dup_p64 (const poly64_t *)
8080 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8081 @end itemize
8082
8083
8084 @itemize @bullet
8085 @item uint64x1_t vld1_dup_u64 (const uint64_t *)
8086 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8087 @end itemize
8088
8089
8090 @itemize @bullet
8091 @item int64x1_t vld1_dup_s64 (const int64_t *)
8092 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8093 @end itemize
8094
8095
8096 @itemize @bullet
8097 @item uint32x4_t vld1q_dup_u32 (const uint32_t *)
8098 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8099 @end itemize
8100
8101
8102 @itemize @bullet
8103 @item uint16x8_t vld1q_dup_u16 (const uint16_t *)
8104 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8105 @end itemize
8106
8107
8108 @itemize @bullet
8109 @item uint8x16_t vld1q_dup_u8 (const uint8_t *)
8110 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8111 @end itemize
8112
8113
8114 @itemize @bullet
8115 @item int32x4_t vld1q_dup_s32 (const int32_t *)
8116 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8117 @end itemize
8118
8119
8120 @itemize @bullet
8121 @item int16x8_t vld1q_dup_s16 (const int16_t *)
8122 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8123 @end itemize
8124
8125
8126 @itemize @bullet
8127 @item int8x16_t vld1q_dup_s8 (const int8_t *)
8128 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8129 @end itemize
8130
8131
8132 @itemize @bullet
8133 @item float32x4_t vld1q_dup_f32 (const float32_t *)
8134 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8135 @end itemize
8136
8137
8138 @itemize @bullet
8139 @item poly16x8_t vld1q_dup_p16 (const poly16_t *)
8140 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8141 @end itemize
8142
8143
8144 @itemize @bullet
8145 @item poly8x16_t vld1q_dup_p8 (const poly8_t *)
8146 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8147 @end itemize
8148
8149
8150 @itemize @bullet
8151 @item poly64x2_t vld1q_dup_p64 (const poly64_t *)
8152 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8153 @end itemize
8154
8155
8156 @itemize @bullet
8157 @item uint64x2_t vld1q_dup_u64 (const uint64_t *)
8158 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8159 @end itemize
8160
8161
8162 @itemize @bullet
8163 @item int64x2_t vld1q_dup_s64 (const int64_t *)
8164 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
8165 @end itemize
8166
8167
8168
8169
8170 @subsubsection Element/structure stores, VST1 variants
8171
8172 @itemize @bullet
8173 @item void vst1_p64 (poly64_t *, poly64x1_t)
8174 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8175 @end itemize
8176
8177
8178 @itemize @bullet
8179 @item void vst1_u32 (uint32_t *, uint32x2_t)
8180 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
8181 @end itemize
8182
8183
8184 @itemize @bullet
8185 @item void vst1_u16 (uint16_t *, uint16x4_t)
8186 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8187 @end itemize
8188
8189
8190 @itemize @bullet
8191 @item void vst1_u8 (uint8_t *, uint8x8_t)
8192 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8193 @end itemize
8194
8195
8196 @itemize @bullet
8197 @item void vst1_s32 (int32_t *, int32x2_t)
8198 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
8199 @end itemize
8200
8201
8202 @itemize @bullet
8203 @item void vst1_s16 (int16_t *, int16x4_t)
8204 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8205 @end itemize
8206
8207
8208 @itemize @bullet
8209 @item void vst1_s8 (int8_t *, int8x8_t)
8210 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8211 @end itemize
8212
8213
8214 @itemize @bullet
8215 @item void vst1_u64 (uint64_t *, uint64x1_t)
8216 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8217 @end itemize
8218
8219
8220 @itemize @bullet
8221 @item void vst1_s64 (int64_t *, int64x1_t)
8222 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8223 @end itemize
8224
8225
8226 @itemize @bullet
8227 @item void vst1_f32 (float32_t *, float32x2_t)
8228 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
8229 @end itemize
8230
8231
8232 @itemize @bullet
8233 @item void vst1_p16 (poly16_t *, poly16x4_t)
8234 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
8235 @end itemize
8236
8237
8238 @itemize @bullet
8239 @item void vst1_p8 (poly8_t *, poly8x8_t)
8240 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
8241 @end itemize
8242
8243
8244 @itemize @bullet
8245 @item void vst1q_p64 (poly64_t *, poly64x2_t)
8246 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8247 @end itemize
8248
8249
8250 @itemize @bullet
8251 @item void vst1q_u32 (uint32_t *, uint32x4_t)
8252 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8253 @end itemize
8254
8255
8256 @itemize @bullet
8257 @item void vst1q_u16 (uint16_t *, uint16x8_t)
8258 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8259 @end itemize
8260
8261
8262 @itemize @bullet
8263 @item void vst1q_u8 (uint8_t *, uint8x16_t)
8264 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8265 @end itemize
8266
8267
8268 @itemize @bullet
8269 @item void vst1q_s32 (int32_t *, int32x4_t)
8270 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8271 @end itemize
8272
8273
8274 @itemize @bullet
8275 @item void vst1q_s16 (int16_t *, int16x8_t)
8276 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8277 @end itemize
8278
8279
8280 @itemize @bullet
8281 @item void vst1q_s8 (int8_t *, int8x16_t)
8282 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8283 @end itemize
8284
8285
8286 @itemize @bullet
8287 @item void vst1q_u64 (uint64_t *, uint64x2_t)
8288 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8289 @end itemize
8290
8291
8292 @itemize @bullet
8293 @item void vst1q_s64 (int64_t *, int64x2_t)
8294 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8295 @end itemize
8296
8297
8298 @itemize @bullet
8299 @item void vst1q_f32 (float32_t *, float32x4_t)
8300 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8301 @end itemize
8302
8303
8304 @itemize @bullet
8305 @item void vst1q_p16 (poly16_t *, poly16x8_t)
8306 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8307 @end itemize
8308
8309
8310 @itemize @bullet
8311 @item void vst1q_p8 (poly8_t *, poly8x16_t)
8312 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8313 @end itemize
8314
8315
8316 @itemize @bullet
8317 @item void vst1_lane_u32 (uint32_t *, uint32x2_t, const int)
8318 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8319 @end itemize
8320
8321
8322 @itemize @bullet
8323 @item void vst1_lane_u16 (uint16_t *, uint16x4_t, const int)
8324 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8325 @end itemize
8326
8327
8328 @itemize @bullet
8329 @item void vst1_lane_u8 (uint8_t *, uint8x8_t, const int)
8330 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8331 @end itemize
8332
8333
8334 @itemize @bullet
8335 @item void vst1_lane_s32 (int32_t *, int32x2_t, const int)
8336 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8337 @end itemize
8338
8339
8340 @itemize @bullet
8341 @item void vst1_lane_s16 (int16_t *, int16x4_t, const int)
8342 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8343 @end itemize
8344
8345
8346 @itemize @bullet
8347 @item void vst1_lane_s8 (int8_t *, int8x8_t, const int)
8348 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8349 @end itemize
8350
8351
8352 @itemize @bullet
8353 @item void vst1_lane_f32 (float32_t *, float32x2_t, const int)
8354 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8355 @end itemize
8356
8357
8358 @itemize @bullet
8359 @item void vst1_lane_p16 (poly16_t *, poly16x4_t, const int)
8360 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8361 @end itemize
8362
8363
8364 @itemize @bullet
8365 @item void vst1_lane_p8 (poly8_t *, poly8x8_t, const int)
8366 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8367 @end itemize
8368
8369
8370 @itemize @bullet
8371 @item void vst1_lane_p64 (poly64_t *, poly64x1_t, const int)
8372 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8373 @end itemize
8374
8375
8376 @itemize @bullet
8377 @item void vst1_lane_s64 (int64_t *, int64x1_t, const int)
8378 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8379 @end itemize
8380
8381
8382 @itemize @bullet
8383 @item void vst1_lane_u64 (uint64_t *, uint64x1_t, const int)
8384 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8385 @end itemize
8386
8387
8388 @itemize @bullet
8389 @item void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int)
8390 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8391 @end itemize
8392
8393
8394 @itemize @bullet
8395 @item void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int)
8396 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8397 @end itemize
8398
8399
8400 @itemize @bullet
8401 @item void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int)
8402 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8403 @end itemize
8404
8405
8406 @itemize @bullet
8407 @item void vst1q_lane_s32 (int32_t *, int32x4_t, const int)
8408 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8409 @end itemize
8410
8411
8412 @itemize @bullet
8413 @item void vst1q_lane_s16 (int16_t *, int16x8_t, const int)
8414 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8415 @end itemize
8416
8417
8418 @itemize @bullet
8419 @item void vst1q_lane_s8 (int8_t *, int8x16_t, const int)
8420 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8421 @end itemize
8422
8423
8424 @itemize @bullet
8425 @item void vst1q_lane_f32 (float32_t *, float32x4_t, const int)
8426 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8427 @end itemize
8428
8429
8430 @itemize @bullet
8431 @item void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int)
8432 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8433 @end itemize
8434
8435
8436 @itemize @bullet
8437 @item void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int)
8438 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8439 @end itemize
8440
8441
8442 @itemize @bullet
8443 @item void vst1q_lane_p64 (poly64_t *, poly64x2_t, const int)
8444 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8445 @end itemize
8446
8447
8448 @itemize @bullet
8449 @item void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
8450 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8451 @end itemize
8452
8453
8454 @itemize @bullet
8455 @item void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int)
8456 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8457 @end itemize
8458
8459
8460
8461
8462 @subsubsection Element/structure loads, VLD2 variants
8463
8464 @itemize @bullet
8465 @item uint32x2x2_t vld2_u32 (const uint32_t *)
8466 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8467 @end itemize
8468
8469
8470 @itemize @bullet
8471 @item uint16x4x2_t vld2_u16 (const uint16_t *)
8472 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8473 @end itemize
8474
8475
8476 @itemize @bullet
8477 @item uint8x8x2_t vld2_u8 (const uint8_t *)
8478 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8479 @end itemize
8480
8481
8482 @itemize @bullet
8483 @item int32x2x2_t vld2_s32 (const int32_t *)
8484 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8485 @end itemize
8486
8487
8488 @itemize @bullet
8489 @item int16x4x2_t vld2_s16 (const int16_t *)
8490 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8491 @end itemize
8492
8493
8494 @itemize @bullet
8495 @item int8x8x2_t vld2_s8 (const int8_t *)
8496 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8497 @end itemize
8498
8499
8500 @itemize @bullet
8501 @item float32x2x2_t vld2_f32 (const float32_t *)
8502 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8503 @end itemize
8504
8505
8506 @itemize @bullet
8507 @item poly16x4x2_t vld2_p16 (const poly16_t *)
8508 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8509 @end itemize
8510
8511
8512 @itemize @bullet
8513 @item poly8x8x2_t vld2_p8 (const poly8_t *)
8514 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8515 @end itemize
8516
8517
8518 @itemize @bullet
8519 @item poly64x1x2_t vld2_p64 (const poly64_t *)
8520 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8521 @end itemize
8522
8523
8524 @itemize @bullet
8525 @item uint64x1x2_t vld2_u64 (const uint64_t *)
8526 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8527 @end itemize
8528
8529
8530 @itemize @bullet
8531 @item int64x1x2_t vld2_s64 (const int64_t *)
8532 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8533 @end itemize
8534
8535
8536 @itemize @bullet
8537 @item uint32x4x2_t vld2q_u32 (const uint32_t *)
8538 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8539 @end itemize
8540
8541
8542 @itemize @bullet
8543 @item uint16x8x2_t vld2q_u16 (const uint16_t *)
8544 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8545 @end itemize
8546
8547
8548 @itemize @bullet
8549 @item uint8x16x2_t vld2q_u8 (const uint8_t *)
8550 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8551 @end itemize
8552
8553
8554 @itemize @bullet
8555 @item int32x4x2_t vld2q_s32 (const int32_t *)
8556 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8557 @end itemize
8558
8559
8560 @itemize @bullet
8561 @item int16x8x2_t vld2q_s16 (const int16_t *)
8562 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8563 @end itemize
8564
8565
8566 @itemize @bullet
8567 @item int8x16x2_t vld2q_s8 (const int8_t *)
8568 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8569 @end itemize
8570
8571
8572 @itemize @bullet
8573 @item float32x4x2_t vld2q_f32 (const float32_t *)
8574 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8575 @end itemize
8576
8577
8578 @itemize @bullet
8579 @item poly16x8x2_t vld2q_p16 (const poly16_t *)
8580 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8581 @end itemize
8582
8583
8584 @itemize @bullet
8585 @item poly8x16x2_t vld2q_p8 (const poly8_t *)
8586 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8587 @end itemize
8588
8589
8590 @itemize @bullet
8591 @item uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int)
8592 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8593 @end itemize
8594
8595
8596 @itemize @bullet
8597 @item uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int)
8598 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8599 @end itemize
8600
8601
8602 @itemize @bullet
8603 @item uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int)
8604 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8605 @end itemize
8606
8607
8608 @itemize @bullet
8609 @item int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int)
8610 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8611 @end itemize
8612
8613
8614 @itemize @bullet
8615 @item int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int)
8616 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8617 @end itemize
8618
8619
8620 @itemize @bullet
8621 @item int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int)
8622 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8623 @end itemize
8624
8625
8626 @itemize @bullet
8627 @item float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int)
8628 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8629 @end itemize
8630
8631
8632 @itemize @bullet
8633 @item poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int)
8634 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8635 @end itemize
8636
8637
8638 @itemize @bullet
8639 @item poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int)
8640 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8641 @end itemize
8642
8643
8644 @itemize @bullet
8645 @item int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int)
8646 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8647 @end itemize
8648
8649
8650 @itemize @bullet
8651 @item int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int)
8652 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8653 @end itemize
8654
8655
8656 @itemize @bullet
8657 @item uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int)
8658 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8659 @end itemize
8660
8661
8662 @itemize @bullet
8663 @item uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int)
8664 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8665 @end itemize
8666
8667
8668 @itemize @bullet
8669 @item float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int)
8670 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8671 @end itemize
8672
8673
8674 @itemize @bullet
8675 @item poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int)
8676 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8677 @end itemize
8678
8679
8680 @itemize @bullet
8681 @item uint32x2x2_t vld2_dup_u32 (const uint32_t *)
8682 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8683 @end itemize
8684
8685
8686 @itemize @bullet
8687 @item uint16x4x2_t vld2_dup_u16 (const uint16_t *)
8688 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8689 @end itemize
8690
8691
8692 @itemize @bullet
8693 @item uint8x8x2_t vld2_dup_u8 (const uint8_t *)
8694 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8695 @end itemize
8696
8697
8698 @itemize @bullet
8699 @item int32x2x2_t vld2_dup_s32 (const int32_t *)
8700 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8701 @end itemize
8702
8703
8704 @itemize @bullet
8705 @item int16x4x2_t vld2_dup_s16 (const int16_t *)
8706 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8707 @end itemize
8708
8709
8710 @itemize @bullet
8711 @item int8x8x2_t vld2_dup_s8 (const int8_t *)
8712 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8713 @end itemize
8714
8715
8716 @itemize @bullet
8717 @item float32x2x2_t vld2_dup_f32 (const float32_t *)
8718 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8719 @end itemize
8720
8721
8722 @itemize @bullet
8723 @item poly16x4x2_t vld2_dup_p16 (const poly16_t *)
8724 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8725 @end itemize
8726
8727
8728 @itemize @bullet
8729 @item poly8x8x2_t vld2_dup_p8 (const poly8_t *)
8730 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8731 @end itemize
8732
8733
8734 @itemize @bullet
8735 @item poly64x1x2_t vld2_dup_p64 (const poly64_t *)
8736 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8737 @end itemize
8738
8739
8740 @itemize @bullet
8741 @item uint64x1x2_t vld2_dup_u64 (const uint64_t *)
8742 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8743 @end itemize
8744
8745
8746 @itemize @bullet
8747 @item int64x1x2_t vld2_dup_s64 (const int64_t *)
8748 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8749 @end itemize
8750
8751
8752
8753
8754 @subsubsection Element/structure stores, VST2 variants
8755
8756 @itemize @bullet
8757 @item void vst2_u32 (uint32_t *, uint32x2x2_t)
8758 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8759 @end itemize
8760
8761
8762 @itemize @bullet
8763 @item void vst2_u16 (uint16_t *, uint16x4x2_t)
8764 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8765 @end itemize
8766
8767
8768 @itemize @bullet
8769 @item void vst2_u8 (uint8_t *, uint8x8x2_t)
8770 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8771 @end itemize
8772
8773
8774 @itemize @bullet
8775 @item void vst2_s32 (int32_t *, int32x2x2_t)
8776 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8777 @end itemize
8778
8779
8780 @itemize @bullet
8781 @item void vst2_s16 (int16_t *, int16x4x2_t)
8782 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8783 @end itemize
8784
8785
8786 @itemize @bullet
8787 @item void vst2_s8 (int8_t *, int8x8x2_t)
8788 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8789 @end itemize
8790
8791
8792 @itemize @bullet
8793 @item void vst2_f32 (float32_t *, float32x2x2_t)
8794 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8795 @end itemize
8796
8797
8798 @itemize @bullet
8799 @item void vst2_p16 (poly16_t *, poly16x4x2_t)
8800 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8801 @end itemize
8802
8803
8804 @itemize @bullet
8805 @item void vst2_p8 (poly8_t *, poly8x8x2_t)
8806 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8807 @end itemize
8808
8809
8810 @itemize @bullet
8811 @item void vst2_p64 (poly64_t *, poly64x1x2_t)
8812 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8813 @end itemize
8814
8815
8816 @itemize @bullet
8817 @item void vst2_u64 (uint64_t *, uint64x1x2_t)
8818 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8819 @end itemize
8820
8821
8822 @itemize @bullet
8823 @item void vst2_s64 (int64_t *, int64x1x2_t)
8824 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8825 @end itemize
8826
8827
8828 @itemize @bullet
8829 @item void vst2q_u32 (uint32_t *, uint32x4x2_t)
8830 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8831 @end itemize
8832
8833
8834 @itemize @bullet
8835 @item void vst2q_u16 (uint16_t *, uint16x8x2_t)
8836 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8837 @end itemize
8838
8839
8840 @itemize @bullet
8841 @item void vst2q_u8 (uint8_t *, uint8x16x2_t)
8842 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8843 @end itemize
8844
8845
8846 @itemize @bullet
8847 @item void vst2q_s32 (int32_t *, int32x4x2_t)
8848 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8849 @end itemize
8850
8851
8852 @itemize @bullet
8853 @item void vst2q_s16 (int16_t *, int16x8x2_t)
8854 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8855 @end itemize
8856
8857
8858 @itemize @bullet
8859 @item void vst2q_s8 (int8_t *, int8x16x2_t)
8860 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8861 @end itemize
8862
8863
8864 @itemize @bullet
8865 @item void vst2q_f32 (float32_t *, float32x4x2_t)
8866 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8867 @end itemize
8868
8869
8870 @itemize @bullet
8871 @item void vst2q_p16 (poly16_t *, poly16x8x2_t)
8872 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8873 @end itemize
8874
8875
8876 @itemize @bullet
8877 @item void vst2q_p8 (poly8_t *, poly8x16x2_t)
8878 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8879 @end itemize
8880
8881
8882 @itemize @bullet
8883 @item void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int)
8884 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8885 @end itemize
8886
8887
8888 @itemize @bullet
8889 @item void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int)
8890 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8891 @end itemize
8892
8893
8894 @itemize @bullet
8895 @item void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int)
8896 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8897 @end itemize
8898
8899
8900 @itemize @bullet
8901 @item void vst2_lane_s32 (int32_t *, int32x2x2_t, const int)
8902 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8903 @end itemize
8904
8905
8906 @itemize @bullet
8907 @item void vst2_lane_s16 (int16_t *, int16x4x2_t, const int)
8908 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8909 @end itemize
8910
8911
8912 @itemize @bullet
8913 @item void vst2_lane_s8 (int8_t *, int8x8x2_t, const int)
8914 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8915 @end itemize
8916
8917
8918 @itemize @bullet
8919 @item void vst2_lane_f32 (float32_t *, float32x2x2_t, const int)
8920 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8921 @end itemize
8922
8923
8924 @itemize @bullet
8925 @item void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int)
8926 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8927 @end itemize
8928
8929
8930 @itemize @bullet
8931 @item void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int)
8932 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8933 @end itemize
8934
8935
8936 @itemize @bullet
8937 @item void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int)
8938 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8939 @end itemize
8940
8941
8942 @itemize @bullet
8943 @item void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int)
8944 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8945 @end itemize
8946
8947
8948 @itemize @bullet
8949 @item void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int)
8950 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8951 @end itemize
8952
8953
8954 @itemize @bullet
8955 @item void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int)
8956 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8957 @end itemize
8958
8959
8960 @itemize @bullet
8961 @item void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int)
8962 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8963 @end itemize
8964
8965
8966 @itemize @bullet
8967 @item void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int)
8968 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8969 @end itemize
8970
8971
8972
8973
8974 @subsubsection Element/structure loads, VLD3 variants
8975
8976 @itemize @bullet
8977 @item uint32x2x3_t vld3_u32 (const uint32_t *)
8978 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8979 @end itemize
8980
8981
8982 @itemize @bullet
8983 @item uint16x4x3_t vld3_u16 (const uint16_t *)
8984 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8985 @end itemize
8986
8987
8988 @itemize @bullet
8989 @item uint8x8x3_t vld3_u8 (const uint8_t *)
8990 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8991 @end itemize
8992
8993
8994 @itemize @bullet
8995 @item int32x2x3_t vld3_s32 (const int32_t *)
8996 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8997 @end itemize
8998
8999
9000 @itemize @bullet
9001 @item int16x4x3_t vld3_s16 (const int16_t *)
9002 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9003 @end itemize
9004
9005
9006 @itemize @bullet
9007 @item int8x8x3_t vld3_s8 (const int8_t *)
9008 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9009 @end itemize
9010
9011
9012 @itemize @bullet
9013 @item float32x2x3_t vld3_f32 (const float32_t *)
9014 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9015 @end itemize
9016
9017
9018 @itemize @bullet
9019 @item poly16x4x3_t vld3_p16 (const poly16_t *)
9020 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9021 @end itemize
9022
9023
9024 @itemize @bullet
9025 @item poly8x8x3_t vld3_p8 (const poly8_t *)
9026 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9027 @end itemize
9028
9029
9030 @itemize @bullet
9031 @item poly64x1x3_t vld3_p64 (const poly64_t *)
9032 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9033 @end itemize
9034
9035
9036 @itemize @bullet
9037 @item uint64x1x3_t vld3_u64 (const uint64_t *)
9038 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9039 @end itemize
9040
9041
9042 @itemize @bullet
9043 @item int64x1x3_t vld3_s64 (const int64_t *)
9044 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9045 @end itemize
9046
9047
9048 @itemize @bullet
9049 @item uint32x4x3_t vld3q_u32 (const uint32_t *)
9050 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9051 @end itemize
9052
9053
9054 @itemize @bullet
9055 @item uint16x8x3_t vld3q_u16 (const uint16_t *)
9056 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9057 @end itemize
9058
9059
9060 @itemize @bullet
9061 @item uint8x16x3_t vld3q_u8 (const uint8_t *)
9062 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9063 @end itemize
9064
9065
9066 @itemize @bullet
9067 @item int32x4x3_t vld3q_s32 (const int32_t *)
9068 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9069 @end itemize
9070
9071
9072 @itemize @bullet
9073 @item int16x8x3_t vld3q_s16 (const int16_t *)
9074 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9075 @end itemize
9076
9077
9078 @itemize @bullet
9079 @item int8x16x3_t vld3q_s8 (const int8_t *)
9080 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9081 @end itemize
9082
9083
9084 @itemize @bullet
9085 @item float32x4x3_t vld3q_f32 (const float32_t *)
9086 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9087 @end itemize
9088
9089
9090 @itemize @bullet
9091 @item poly16x8x3_t vld3q_p16 (const poly16_t *)
9092 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9093 @end itemize
9094
9095
9096 @itemize @bullet
9097 @item poly8x16x3_t vld3q_p8 (const poly8_t *)
9098 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9099 @end itemize
9100
9101
9102 @itemize @bullet
9103 @item uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int)
9104 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9105 @end itemize
9106
9107
9108 @itemize @bullet
9109 @item uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int)
9110 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9111 @end itemize
9112
9113
9114 @itemize @bullet
9115 @item uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int)
9116 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9117 @end itemize
9118
9119
9120 @itemize @bullet
9121 @item int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int)
9122 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9123 @end itemize
9124
9125
9126 @itemize @bullet
9127 @item int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int)
9128 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9129 @end itemize
9130
9131
9132 @itemize @bullet
9133 @item int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int)
9134 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9135 @end itemize
9136
9137
9138 @itemize @bullet
9139 @item float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int)
9140 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9141 @end itemize
9142
9143
9144 @itemize @bullet
9145 @item poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int)
9146 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9147 @end itemize
9148
9149
9150 @itemize @bullet
9151 @item poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int)
9152 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9153 @end itemize
9154
9155
9156 @itemize @bullet
9157 @item int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int)
9158 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9159 @end itemize
9160
9161
9162 @itemize @bullet
9163 @item int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int)
9164 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9165 @end itemize
9166
9167
9168 @itemize @bullet
9169 @item uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int)
9170 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9171 @end itemize
9172
9173
9174 @itemize @bullet
9175 @item uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int)
9176 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9177 @end itemize
9178
9179
9180 @itemize @bullet
9181 @item float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int)
9182 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9183 @end itemize
9184
9185
9186 @itemize @bullet
9187 @item poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int)
9188 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9189 @end itemize
9190
9191
9192 @itemize @bullet
9193 @item uint32x2x3_t vld3_dup_u32 (const uint32_t *)
9194 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9195 @end itemize
9196
9197
9198 @itemize @bullet
9199 @item uint16x4x3_t vld3_dup_u16 (const uint16_t *)
9200 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9201 @end itemize
9202
9203
9204 @itemize @bullet
9205 @item uint8x8x3_t vld3_dup_u8 (const uint8_t *)
9206 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9207 @end itemize
9208
9209
9210 @itemize @bullet
9211 @item int32x2x3_t vld3_dup_s32 (const int32_t *)
9212 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9213 @end itemize
9214
9215
9216 @itemize @bullet
9217 @item int16x4x3_t vld3_dup_s16 (const int16_t *)
9218 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9219 @end itemize
9220
9221
9222 @itemize @bullet
9223 @item int8x8x3_t vld3_dup_s8 (const int8_t *)
9224 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9225 @end itemize
9226
9227
9228 @itemize @bullet
9229 @item float32x2x3_t vld3_dup_f32 (const float32_t *)
9230 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9231 @end itemize
9232
9233
9234 @itemize @bullet
9235 @item poly16x4x3_t vld3_dup_p16 (const poly16_t *)
9236 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9237 @end itemize
9238
9239
9240 @itemize @bullet
9241 @item poly8x8x3_t vld3_dup_p8 (const poly8_t *)
9242 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
9243 @end itemize
9244
9245
9246 @itemize @bullet
9247 @item poly64x1x3_t vld3_dup_p64 (const poly64_t *)
9248 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9249 @end itemize
9250
9251
9252 @itemize @bullet
9253 @item uint64x1x3_t vld3_dup_u64 (const uint64_t *)
9254 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9255 @end itemize
9256
9257
9258 @itemize @bullet
9259 @item int64x1x3_t vld3_dup_s64 (const int64_t *)
9260 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9261 @end itemize
9262
9263
9264
9265
9266 @subsubsection Element/structure stores, VST3 variants
9267
9268 @itemize @bullet
9269 @item void vst3_u32 (uint32_t *, uint32x2x3_t)
9270 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9271 @end itemize
9272
9273
9274 @itemize @bullet
9275 @item void vst3_u16 (uint16_t *, uint16x4x3_t)
9276 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9277 @end itemize
9278
9279
9280 @itemize @bullet
9281 @item void vst3_u8 (uint8_t *, uint8x8x3_t)
9282 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9283 @end itemize
9284
9285
9286 @itemize @bullet
9287 @item void vst3_s32 (int32_t *, int32x2x3_t)
9288 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9289 @end itemize
9290
9291
9292 @itemize @bullet
9293 @item void vst3_s16 (int16_t *, int16x4x3_t)
9294 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9295 @end itemize
9296
9297
9298 @itemize @bullet
9299 @item void vst3_s8 (int8_t *, int8x8x3_t)
9300 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9301 @end itemize
9302
9303
9304 @itemize @bullet
9305 @item void vst3_f32 (float32_t *, float32x2x3_t)
9306 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9307 @end itemize
9308
9309
9310 @itemize @bullet
9311 @item void vst3_p16 (poly16_t *, poly16x4x3_t)
9312 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9313 @end itemize
9314
9315
9316 @itemize @bullet
9317 @item void vst3_p8 (poly8_t *, poly8x8x3_t)
9318 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9319 @end itemize
9320
9321
9322 @itemize @bullet
9323 @item void vst3_p64 (poly64_t *, poly64x1x3_t)
9324 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9325 @end itemize
9326
9327
9328 @itemize @bullet
9329 @item void vst3_u64 (uint64_t *, uint64x1x3_t)
9330 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9331 @end itemize
9332
9333
9334 @itemize @bullet
9335 @item void vst3_s64 (int64_t *, int64x1x3_t)
9336 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9337 @end itemize
9338
9339
9340 @itemize @bullet
9341 @item void vst3q_u32 (uint32_t *, uint32x4x3_t)
9342 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9343 @end itemize
9344
9345
9346 @itemize @bullet
9347 @item void vst3q_u16 (uint16_t *, uint16x8x3_t)
9348 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9349 @end itemize
9350
9351
9352 @itemize @bullet
9353 @item void vst3q_u8 (uint8_t *, uint8x16x3_t)
9354 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9355 @end itemize
9356
9357
9358 @itemize @bullet
9359 @item void vst3q_s32 (int32_t *, int32x4x3_t)
9360 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9361 @end itemize
9362
9363
9364 @itemize @bullet
9365 @item void vst3q_s16 (int16_t *, int16x8x3_t)
9366 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9367 @end itemize
9368
9369
9370 @itemize @bullet
9371 @item void vst3q_s8 (int8_t *, int8x16x3_t)
9372 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9373 @end itemize
9374
9375
9376 @itemize @bullet
9377 @item void vst3q_f32 (float32_t *, float32x4x3_t)
9378 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9379 @end itemize
9380
9381
9382 @itemize @bullet
9383 @item void vst3q_p16 (poly16_t *, poly16x8x3_t)
9384 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9385 @end itemize
9386
9387
9388 @itemize @bullet
9389 @item void vst3q_p8 (poly8_t *, poly8x16x3_t)
9390 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9391 @end itemize
9392
9393
9394 @itemize @bullet
9395 @item void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int)
9396 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9397 @end itemize
9398
9399
9400 @itemize @bullet
9401 @item void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int)
9402 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9403 @end itemize
9404
9405
9406 @itemize @bullet
9407 @item void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int)
9408 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9409 @end itemize
9410
9411
9412 @itemize @bullet
9413 @item void vst3_lane_s32 (int32_t *, int32x2x3_t, const int)
9414 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9415 @end itemize
9416
9417
9418 @itemize @bullet
9419 @item void vst3_lane_s16 (int16_t *, int16x4x3_t, const int)
9420 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9421 @end itemize
9422
9423
9424 @itemize @bullet
9425 @item void vst3_lane_s8 (int8_t *, int8x8x3_t, const int)
9426 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9427 @end itemize
9428
9429
9430 @itemize @bullet
9431 @item void vst3_lane_f32 (float32_t *, float32x2x3_t, const int)
9432 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9433 @end itemize
9434
9435
9436 @itemize @bullet
9437 @item void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int)
9438 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9439 @end itemize
9440
9441
9442 @itemize @bullet
9443 @item void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int)
9444 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9445 @end itemize
9446
9447
9448 @itemize @bullet
9449 @item void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int)
9450 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9451 @end itemize
9452
9453
9454 @itemize @bullet
9455 @item void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int)
9456 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9457 @end itemize
9458
9459
9460 @itemize @bullet
9461 @item void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int)
9462 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9463 @end itemize
9464
9465
9466 @itemize @bullet
9467 @item void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int)
9468 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9469 @end itemize
9470
9471
9472 @itemize @bullet
9473 @item void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int)
9474 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9475 @end itemize
9476
9477
9478 @itemize @bullet
9479 @item void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int)
9480 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9481 @end itemize
9482
9483
9484
9485
9486 @subsubsection Element/structure loads, VLD4 variants
9487
9488 @itemize @bullet
9489 @item uint32x2x4_t vld4_u32 (const uint32_t *)
9490 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9491 @end itemize
9492
9493
9494 @itemize @bullet
9495 @item uint16x4x4_t vld4_u16 (const uint16_t *)
9496 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9497 @end itemize
9498
9499
9500 @itemize @bullet
9501 @item uint8x8x4_t vld4_u8 (const uint8_t *)
9502 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9503 @end itemize
9504
9505
9506 @itemize @bullet
9507 @item int32x2x4_t vld4_s32 (const int32_t *)
9508 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9509 @end itemize
9510
9511
9512 @itemize @bullet
9513 @item int16x4x4_t vld4_s16 (const int16_t *)
9514 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9515 @end itemize
9516
9517
9518 @itemize @bullet
9519 @item int8x8x4_t vld4_s8 (const int8_t *)
9520 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9521 @end itemize
9522
9523
9524 @itemize @bullet
9525 @item float32x2x4_t vld4_f32 (const float32_t *)
9526 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9527 @end itemize
9528
9529
9530 @itemize @bullet
9531 @item poly16x4x4_t vld4_p16 (const poly16_t *)
9532 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9533 @end itemize
9534
9535
9536 @itemize @bullet
9537 @item poly8x8x4_t vld4_p8 (const poly8_t *)
9538 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9539 @end itemize
9540
9541
9542 @itemize @bullet
9543 @item poly64x1x4_t vld4_p64 (const poly64_t *)
9544 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9545 @end itemize
9546
9547
9548 @itemize @bullet
9549 @item uint64x1x4_t vld4_u64 (const uint64_t *)
9550 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9551 @end itemize
9552
9553
9554 @itemize @bullet
9555 @item int64x1x4_t vld4_s64 (const int64_t *)
9556 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9557 @end itemize
9558
9559
9560 @itemize @bullet
9561 @item uint32x4x4_t vld4q_u32 (const uint32_t *)
9562 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9563 @end itemize
9564
9565
9566 @itemize @bullet
9567 @item uint16x8x4_t vld4q_u16 (const uint16_t *)
9568 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9569 @end itemize
9570
9571
9572 @itemize @bullet
9573 @item uint8x16x4_t vld4q_u8 (const uint8_t *)
9574 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9575 @end itemize
9576
9577
9578 @itemize @bullet
9579 @item int32x4x4_t vld4q_s32 (const int32_t *)
9580 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9581 @end itemize
9582
9583
9584 @itemize @bullet
9585 @item int16x8x4_t vld4q_s16 (const int16_t *)
9586 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9587 @end itemize
9588
9589
9590 @itemize @bullet
9591 @item int8x16x4_t vld4q_s8 (const int8_t *)
9592 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9593 @end itemize
9594
9595
9596 @itemize @bullet
9597 @item float32x4x4_t vld4q_f32 (const float32_t *)
9598 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9599 @end itemize
9600
9601
9602 @itemize @bullet
9603 @item poly16x8x4_t vld4q_p16 (const poly16_t *)
9604 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9605 @end itemize
9606
9607
9608 @itemize @bullet
9609 @item poly8x16x4_t vld4q_p8 (const poly8_t *)
9610 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9611 @end itemize
9612
9613
9614 @itemize @bullet
9615 @item uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int)
9616 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9617 @end itemize
9618
9619
9620 @itemize @bullet
9621 @item uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int)
9622 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9623 @end itemize
9624
9625
9626 @itemize @bullet
9627 @item uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int)
9628 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9629 @end itemize
9630
9631
9632 @itemize @bullet
9633 @item int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int)
9634 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9635 @end itemize
9636
9637
9638 @itemize @bullet
9639 @item int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int)
9640 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9641 @end itemize
9642
9643
9644 @itemize @bullet
9645 @item int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int)
9646 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9647 @end itemize
9648
9649
9650 @itemize @bullet
9651 @item float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int)
9652 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9653 @end itemize
9654
9655
9656 @itemize @bullet
9657 @item poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int)
9658 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9659 @end itemize
9660
9661
9662 @itemize @bullet
9663 @item poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int)
9664 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9665 @end itemize
9666
9667
9668 @itemize @bullet
9669 @item int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int)
9670 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9671 @end itemize
9672
9673
9674 @itemize @bullet
9675 @item int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int)
9676 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9677 @end itemize
9678
9679
9680 @itemize @bullet
9681 @item uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int)
9682 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9683 @end itemize
9684
9685
9686 @itemize @bullet
9687 @item uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int)
9688 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9689 @end itemize
9690
9691
9692 @itemize @bullet
9693 @item float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int)
9694 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9695 @end itemize
9696
9697
9698 @itemize @bullet
9699 @item poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int)
9700 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9701 @end itemize
9702
9703
9704 @itemize @bullet
9705 @item uint32x2x4_t vld4_dup_u32 (const uint32_t *)
9706 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9707 @end itemize
9708
9709
9710 @itemize @bullet
9711 @item uint16x4x4_t vld4_dup_u16 (const uint16_t *)
9712 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9713 @end itemize
9714
9715
9716 @itemize @bullet
9717 @item uint8x8x4_t vld4_dup_u8 (const uint8_t *)
9718 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9719 @end itemize
9720
9721
9722 @itemize @bullet
9723 @item int32x2x4_t vld4_dup_s32 (const int32_t *)
9724 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9725 @end itemize
9726
9727
9728 @itemize @bullet
9729 @item int16x4x4_t vld4_dup_s16 (const int16_t *)
9730 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9731 @end itemize
9732
9733
9734 @itemize @bullet
9735 @item int8x8x4_t vld4_dup_s8 (const int8_t *)
9736 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9737 @end itemize
9738
9739
9740 @itemize @bullet
9741 @item float32x2x4_t vld4_dup_f32 (const float32_t *)
9742 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9743 @end itemize
9744
9745
9746 @itemize @bullet
9747 @item poly16x4x4_t vld4_dup_p16 (const poly16_t *)
9748 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9749 @end itemize
9750
9751
9752 @itemize @bullet
9753 @item poly8x8x4_t vld4_dup_p8 (const poly8_t *)
9754 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9755 @end itemize
9756
9757
9758 @itemize @bullet
9759 @item poly64x1x4_t vld4_dup_p64 (const poly64_t *)
9760 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9761 @end itemize
9762
9763
9764 @itemize @bullet
9765 @item uint64x1x4_t vld4_dup_u64 (const uint64_t *)
9766 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9767 @end itemize
9768
9769
9770 @itemize @bullet
9771 @item int64x1x4_t vld4_dup_s64 (const int64_t *)
9772 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9773 @end itemize
9774
9775
9776
9777
9778 @subsubsection Element/structure stores, VST4 variants
9779
9780 @itemize @bullet
9781 @item void vst4_u32 (uint32_t *, uint32x2x4_t)
9782 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9783 @end itemize
9784
9785
9786 @itemize @bullet
9787 @item void vst4_u16 (uint16_t *, uint16x4x4_t)
9788 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9789 @end itemize
9790
9791
9792 @itemize @bullet
9793 @item void vst4_u8 (uint8_t *, uint8x8x4_t)
9794 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9795 @end itemize
9796
9797
9798 @itemize @bullet
9799 @item void vst4_s32 (int32_t *, int32x2x4_t)
9800 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9801 @end itemize
9802
9803
9804 @itemize @bullet
9805 @item void vst4_s16 (int16_t *, int16x4x4_t)
9806 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9807 @end itemize
9808
9809
9810 @itemize @bullet
9811 @item void vst4_s8 (int8_t *, int8x8x4_t)
9812 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9813 @end itemize
9814
9815
9816 @itemize @bullet
9817 @item void vst4_f32 (float32_t *, float32x2x4_t)
9818 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9819 @end itemize
9820
9821
9822 @itemize @bullet
9823 @item void vst4_p16 (poly16_t *, poly16x4x4_t)
9824 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9825 @end itemize
9826
9827
9828 @itemize @bullet
9829 @item void vst4_p8 (poly8_t *, poly8x8x4_t)
9830 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9831 @end itemize
9832
9833
9834 @itemize @bullet
9835 @item void vst4_p64 (poly64_t *, poly64x1x4_t)
9836 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9837 @end itemize
9838
9839
9840 @itemize @bullet
9841 @item void vst4_u64 (uint64_t *, uint64x1x4_t)
9842 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9843 @end itemize
9844
9845
9846 @itemize @bullet
9847 @item void vst4_s64 (int64_t *, int64x1x4_t)
9848 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9849 @end itemize
9850
9851
9852 @itemize @bullet
9853 @item void vst4q_u32 (uint32_t *, uint32x4x4_t)
9854 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9855 @end itemize
9856
9857
9858 @itemize @bullet
9859 @item void vst4q_u16 (uint16_t *, uint16x8x4_t)
9860 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9861 @end itemize
9862
9863
9864 @itemize @bullet
9865 @item void vst4q_u8 (uint8_t *, uint8x16x4_t)
9866 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9867 @end itemize
9868
9869
9870 @itemize @bullet
9871 @item void vst4q_s32 (int32_t *, int32x4x4_t)
9872 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9873 @end itemize
9874
9875
9876 @itemize @bullet
9877 @item void vst4q_s16 (int16_t *, int16x8x4_t)
9878 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9879 @end itemize
9880
9881
9882 @itemize @bullet
9883 @item void vst4q_s8 (int8_t *, int8x16x4_t)
9884 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9885 @end itemize
9886
9887
9888 @itemize @bullet
9889 @item void vst4q_f32 (float32_t *, float32x4x4_t)
9890 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9891 @end itemize
9892
9893
9894 @itemize @bullet
9895 @item void vst4q_p16 (poly16_t *, poly16x8x4_t)
9896 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9897 @end itemize
9898
9899
9900 @itemize @bullet
9901 @item void vst4q_p8 (poly8_t *, poly8x16x4_t)
9902 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9903 @end itemize
9904
9905
9906 @itemize @bullet
9907 @item void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int)
9908 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9909 @end itemize
9910
9911
9912 @itemize @bullet
9913 @item void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int)
9914 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9915 @end itemize
9916
9917
9918 @itemize @bullet
9919 @item void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int)
9920 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9921 @end itemize
9922
9923
9924 @itemize @bullet
9925 @item void vst4_lane_s32 (int32_t *, int32x2x4_t, const int)
9926 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9927 @end itemize
9928
9929
9930 @itemize @bullet
9931 @item void vst4_lane_s16 (int16_t *, int16x4x4_t, const int)
9932 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9933 @end itemize
9934
9935
9936 @itemize @bullet
9937 @item void vst4_lane_s8 (int8_t *, int8x8x4_t, const int)
9938 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9939 @end itemize
9940
9941
9942 @itemize @bullet
9943 @item void vst4_lane_f32 (float32_t *, float32x2x4_t, const int)
9944 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9945 @end itemize
9946
9947
9948 @itemize @bullet
9949 @item void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int)
9950 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9951 @end itemize
9952
9953
9954 @itemize @bullet
9955 @item void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int)
9956 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9957 @end itemize
9958
9959
9960 @itemize @bullet
9961 @item void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int)
9962 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9963 @end itemize
9964
9965
9966 @itemize @bullet
9967 @item void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int)
9968 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9969 @end itemize
9970
9971
9972 @itemize @bullet
9973 @item void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int)
9974 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9975 @end itemize
9976
9977
9978 @itemize @bullet
9979 @item void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int)
9980 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9981 @end itemize
9982
9983
9984 @itemize @bullet
9985 @item void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int)
9986 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9987 @end itemize
9988
9989
9990 @itemize @bullet
9991 @item void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int)
9992 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9993 @end itemize
9994
9995
9996
9997
9998 @subsubsection Logical operations (AND)
9999
10000 @itemize @bullet
10001 @item uint32x2_t vand_u32 (uint32x2_t, uint32x2_t)
10002 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10003 @end itemize
10004
10005
10006 @itemize @bullet
10007 @item uint16x4_t vand_u16 (uint16x4_t, uint16x4_t)
10008 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10009 @end itemize
10010
10011
10012 @itemize @bullet
10013 @item uint8x8_t vand_u8 (uint8x8_t, uint8x8_t)
10014 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10015 @end itemize
10016
10017
10018 @itemize @bullet
10019 @item int32x2_t vand_s32 (int32x2_t, int32x2_t)
10020 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10021 @end itemize
10022
10023
10024 @itemize @bullet
10025 @item int16x4_t vand_s16 (int16x4_t, int16x4_t)
10026 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10027 @end itemize
10028
10029
10030 @itemize @bullet
10031 @item int8x8_t vand_s8 (int8x8_t, int8x8_t)
10032 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
10033 @end itemize
10034
10035
10036 @itemize @bullet
10037 @item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
10038 @end itemize
10039
10040
10041 @itemize @bullet
10042 @item int64x1_t vand_s64 (int64x1_t, int64x1_t)
10043 @end itemize
10044
10045
10046 @itemize @bullet
10047 @item uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t)
10048 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10049 @end itemize
10050
10051
10052 @itemize @bullet
10053 @item uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t)
10054 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10055 @end itemize
10056
10057
10058 @itemize @bullet
10059 @item uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t)
10060 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10061 @end itemize
10062
10063
10064 @itemize @bullet
10065 @item int32x4_t vandq_s32 (int32x4_t, int32x4_t)
10066 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10067 @end itemize
10068
10069
10070 @itemize @bullet
10071 @item int16x8_t vandq_s16 (int16x8_t, int16x8_t)
10072 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10073 @end itemize
10074
10075
10076 @itemize @bullet
10077 @item int8x16_t vandq_s8 (int8x16_t, int8x16_t)
10078 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10079 @end itemize
10080
10081
10082 @itemize @bullet
10083 @item uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t)
10084 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10085 @end itemize
10086
10087
10088 @itemize @bullet
10089 @item int64x2_t vandq_s64 (int64x2_t, int64x2_t)
10090 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
10091 @end itemize
10092
10093
10094
10095
10096 @subsubsection Logical operations (OR)
10097
10098 @itemize @bullet
10099 @item uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t)
10100 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10101 @end itemize
10102
10103
10104 @itemize @bullet
10105 @item uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t)
10106 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10107 @end itemize
10108
10109
10110 @itemize @bullet
10111 @item uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t)
10112 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10113 @end itemize
10114
10115
10116 @itemize @bullet
10117 @item int32x2_t vorr_s32 (int32x2_t, int32x2_t)
10118 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10119 @end itemize
10120
10121
10122 @itemize @bullet
10123 @item int16x4_t vorr_s16 (int16x4_t, int16x4_t)
10124 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10125 @end itemize
10126
10127
10128 @itemize @bullet
10129 @item int8x8_t vorr_s8 (int8x8_t, int8x8_t)
10130 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
10131 @end itemize
10132
10133
10134 @itemize @bullet
10135 @item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
10136 @end itemize
10137
10138
10139 @itemize @bullet
10140 @item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
10141 @end itemize
10142
10143
10144 @itemize @bullet
10145 @item uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t)
10146 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10147 @end itemize
10148
10149
10150 @itemize @bullet
10151 @item uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t)
10152 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10153 @end itemize
10154
10155
10156 @itemize @bullet
10157 @item uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t)
10158 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10159 @end itemize
10160
10161
10162 @itemize @bullet
10163 @item int32x4_t vorrq_s32 (int32x4_t, int32x4_t)
10164 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10165 @end itemize
10166
10167
10168 @itemize @bullet
10169 @item int16x8_t vorrq_s16 (int16x8_t, int16x8_t)
10170 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10171 @end itemize
10172
10173
10174 @itemize @bullet
10175 @item int8x16_t vorrq_s8 (int8x16_t, int8x16_t)
10176 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10177 @end itemize
10178
10179
10180 @itemize @bullet
10181 @item uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t)
10182 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10183 @end itemize
10184
10185
10186 @itemize @bullet
10187 @item int64x2_t vorrq_s64 (int64x2_t, int64x2_t)
10188 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
10189 @end itemize
10190
10191
10192
10193
10194 @subsubsection Logical operations (exclusive OR)
10195
10196 @itemize @bullet
10197 @item uint32x2_t veor_u32 (uint32x2_t, uint32x2_t)
10198 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10199 @end itemize
10200
10201
10202 @itemize @bullet
10203 @item uint16x4_t veor_u16 (uint16x4_t, uint16x4_t)
10204 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10205 @end itemize
10206
10207
10208 @itemize @bullet
10209 @item uint8x8_t veor_u8 (uint8x8_t, uint8x8_t)
10210 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10211 @end itemize
10212
10213
10214 @itemize @bullet
10215 @item int32x2_t veor_s32 (int32x2_t, int32x2_t)
10216 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10217 @end itemize
10218
10219
10220 @itemize @bullet
10221 @item int16x4_t veor_s16 (int16x4_t, int16x4_t)
10222 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10223 @end itemize
10224
10225
10226 @itemize @bullet
10227 @item int8x8_t veor_s8 (int8x8_t, int8x8_t)
10228 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
10229 @end itemize
10230
10231
10232 @itemize @bullet
10233 @item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
10234 @end itemize
10235
10236
10237 @itemize @bullet
10238 @item int64x1_t veor_s64 (int64x1_t, int64x1_t)
10239 @end itemize
10240
10241
10242 @itemize @bullet
10243 @item uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t)
10244 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10245 @end itemize
10246
10247
10248 @itemize @bullet
10249 @item uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t)
10250 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10251 @end itemize
10252
10253
10254 @itemize @bullet
10255 @item uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t)
10256 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10257 @end itemize
10258
10259
10260 @itemize @bullet
10261 @item int32x4_t veorq_s32 (int32x4_t, int32x4_t)
10262 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10263 @end itemize
10264
10265
10266 @itemize @bullet
10267 @item int16x8_t veorq_s16 (int16x8_t, int16x8_t)
10268 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10269 @end itemize
10270
10271
10272 @itemize @bullet
10273 @item int8x16_t veorq_s8 (int8x16_t, int8x16_t)
10274 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10275 @end itemize
10276
10277
10278 @itemize @bullet
10279 @item uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t)
10280 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10281 @end itemize
10282
10283
10284 @itemize @bullet
10285 @item int64x2_t veorq_s64 (int64x2_t, int64x2_t)
10286 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
10287 @end itemize
10288
10289
10290
10291
10292 @subsubsection Logical operations (AND-NOT)
10293
10294 @itemize @bullet
10295 @item uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t)
10296 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10297 @end itemize
10298
10299
10300 @itemize @bullet
10301 @item uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t)
10302 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10303 @end itemize
10304
10305
10306 @itemize @bullet
10307 @item uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t)
10308 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10309 @end itemize
10310
10311
10312 @itemize @bullet
10313 @item int32x2_t vbic_s32 (int32x2_t, int32x2_t)
10314 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10315 @end itemize
10316
10317
10318 @itemize @bullet
10319 @item int16x4_t vbic_s16 (int16x4_t, int16x4_t)
10320 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10321 @end itemize
10322
10323
10324 @itemize @bullet
10325 @item int8x8_t vbic_s8 (int8x8_t, int8x8_t)
10326 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10327 @end itemize
10328
10329
10330 @itemize @bullet
10331 @item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
10332 @end itemize
10333
10334
10335 @itemize @bullet
10336 @item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
10337 @end itemize
10338
10339
10340 @itemize @bullet
10341 @item uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t)
10342 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10343 @end itemize
10344
10345
10346 @itemize @bullet
10347 @item uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t)
10348 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10349 @end itemize
10350
10351
10352 @itemize @bullet
10353 @item uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t)
10354 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10355 @end itemize
10356
10357
10358 @itemize @bullet
10359 @item int32x4_t vbicq_s32 (int32x4_t, int32x4_t)
10360 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10361 @end itemize
10362
10363
10364 @itemize @bullet
10365 @item int16x8_t vbicq_s16 (int16x8_t, int16x8_t)
10366 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10367 @end itemize
10368
10369
10370 @itemize @bullet
10371 @item int8x16_t vbicq_s8 (int8x16_t, int8x16_t)
10372 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10373 @end itemize
10374
10375
10376 @itemize @bullet
10377 @item uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t)
10378 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10379 @end itemize
10380
10381
10382 @itemize @bullet
10383 @item int64x2_t vbicq_s64 (int64x2_t, int64x2_t)
10384 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10385 @end itemize
10386
10387
10388
10389
10390 @subsubsection Logical operations (OR-NOT)
10391
10392 @itemize @bullet
10393 @item uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t)
10394 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10395 @end itemize
10396
10397
10398 @itemize @bullet
10399 @item uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t)
10400 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10401 @end itemize
10402
10403
10404 @itemize @bullet
10405 @item uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t)
10406 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10407 @end itemize
10408
10409
10410 @itemize @bullet
10411 @item int32x2_t vorn_s32 (int32x2_t, int32x2_t)
10412 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10413 @end itemize
10414
10415
10416 @itemize @bullet
10417 @item int16x4_t vorn_s16 (int16x4_t, int16x4_t)
10418 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10419 @end itemize
10420
10421
10422 @itemize @bullet
10423 @item int8x8_t vorn_s8 (int8x8_t, int8x8_t)
10424 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10425 @end itemize
10426
10427
10428 @itemize @bullet
10429 @item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
10430 @end itemize
10431
10432
10433 @itemize @bullet
10434 @item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
10435 @end itemize
10436
10437
10438 @itemize @bullet
10439 @item uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t)
10440 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10441 @end itemize
10442
10443
10444 @itemize @bullet
10445 @item uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t)
10446 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10447 @end itemize
10448
10449
10450 @itemize @bullet
10451 @item uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t)
10452 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10453 @end itemize
10454
10455
10456 @itemize @bullet
10457 @item int32x4_t vornq_s32 (int32x4_t, int32x4_t)
10458 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10459 @end itemize
10460
10461
10462 @itemize @bullet
10463 @item int16x8_t vornq_s16 (int16x8_t, int16x8_t)
10464 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10465 @end itemize
10466
10467
10468 @itemize @bullet
10469 @item int8x16_t vornq_s8 (int8x16_t, int8x16_t)
10470 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10471 @end itemize
10472
10473
10474 @itemize @bullet
10475 @item uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t)
10476 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10477 @end itemize
10478
10479
10480 @itemize @bullet
10481 @item int64x2_t vornq_s64 (int64x2_t, int64x2_t)
10482 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10483 @end itemize
10484
10485
10486
10487
10488 @subsubsection Reinterpret casts
10489
10490 @itemize @bullet
10491 @item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
10492 @end itemize
10493
10494
10495 @itemize @bullet
10496 @item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
10497 @end itemize
10498
10499
10500 @itemize @bullet
10501 @item poly8x8_t vreinterpret_p8_p64 (poly64x1_t)
10502 @end itemize
10503
10504
10505 @itemize @bullet
10506 @item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
10507 @end itemize
10508
10509
10510 @itemize @bullet
10511 @item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
10512 @end itemize
10513
10514
10515 @itemize @bullet
10516 @item poly8x8_t vreinterpret_p8_s8 (int8x8_t)
10517 @end itemize
10518
10519
10520 @itemize @bullet
10521 @item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
10522 @end itemize
10523
10524
10525 @itemize @bullet
10526 @item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
10527 @end itemize
10528
10529
10530 @itemize @bullet
10531 @item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
10532 @end itemize
10533
10534
10535 @itemize @bullet
10536 @item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
10537 @end itemize
10538
10539
10540 @itemize @bullet
10541 @item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
10542 @end itemize
10543
10544
10545 @itemize @bullet
10546 @item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
10547 @end itemize
10548
10549
10550 @itemize @bullet
10551 @item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
10552 @end itemize
10553
10554
10555 @itemize @bullet
10556 @item poly16x4_t vreinterpret_p16_p64 (poly64x1_t)
10557 @end itemize
10558
10559
10560 @itemize @bullet
10561 @item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
10562 @end itemize
10563
10564
10565 @itemize @bullet
10566 @item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
10567 @end itemize
10568
10569
10570 @itemize @bullet
10571 @item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
10572 @end itemize
10573
10574
10575 @itemize @bullet
10576 @item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
10577 @end itemize
10578
10579
10580 @itemize @bullet
10581 @item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
10582 @end itemize
10583
10584
10585 @itemize @bullet
10586 @item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
10587 @end itemize
10588
10589
10590 @itemize @bullet
10591 @item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
10592 @end itemize
10593
10594
10595 @itemize @bullet
10596 @item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
10597 @end itemize
10598
10599
10600 @itemize @bullet
10601 @item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
10602 @end itemize
10603
10604
10605 @itemize @bullet
10606 @item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
10607 @end itemize
10608
10609
10610 @itemize @bullet
10611 @item float32x2_t vreinterpret_f32_p64 (poly64x1_t)
10612 @end itemize
10613
10614
10615 @itemize @bullet
10616 @item float32x2_t vreinterpret_f32_s64 (int64x1_t)
10617 @end itemize
10618
10619
10620 @itemize @bullet
10621 @item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
10622 @end itemize
10623
10624
10625 @itemize @bullet
10626 @item float32x2_t vreinterpret_f32_s8 (int8x8_t)
10627 @end itemize
10628
10629
10630 @itemize @bullet
10631 @item float32x2_t vreinterpret_f32_s16 (int16x4_t)
10632 @end itemize
10633
10634
10635 @itemize @bullet
10636 @item float32x2_t vreinterpret_f32_s32 (int32x2_t)
10637 @end itemize
10638
10639
10640 @itemize @bullet
10641 @item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
10642 @end itemize
10643
10644
10645 @itemize @bullet
10646 @item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
10647 @end itemize
10648
10649
10650 @itemize @bullet
10651 @item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
10652 @end itemize
10653
10654
10655 @itemize @bullet
10656 @item poly64x1_t vreinterpret_p64_p8 (poly8x8_t)
10657 @end itemize
10658
10659
10660 @itemize @bullet
10661 @item poly64x1_t vreinterpret_p64_p16 (poly16x4_t)
10662 @end itemize
10663
10664
10665 @itemize @bullet
10666 @item poly64x1_t vreinterpret_p64_f32 (float32x2_t)
10667 @end itemize
10668
10669
10670 @itemize @bullet
10671 @item poly64x1_t vreinterpret_p64_s64 (int64x1_t)
10672 @end itemize
10673
10674
10675 @itemize @bullet
10676 @item poly64x1_t vreinterpret_p64_u64 (uint64x1_t)
10677 @end itemize
10678
10679
10680 @itemize @bullet
10681 @item poly64x1_t vreinterpret_p64_s8 (int8x8_t)
10682 @end itemize
10683
10684
10685 @itemize @bullet
10686 @item poly64x1_t vreinterpret_p64_s16 (int16x4_t)
10687 @end itemize
10688
10689
10690 @itemize @bullet
10691 @item poly64x1_t vreinterpret_p64_s32 (int32x2_t)
10692 @end itemize
10693
10694
10695 @itemize @bullet
10696 @item poly64x1_t vreinterpret_p64_u8 (uint8x8_t)
10697 @end itemize
10698
10699
10700 @itemize @bullet
10701 @item poly64x1_t vreinterpret_p64_u16 (uint16x4_t)
10702 @end itemize
10703
10704
10705 @itemize @bullet
10706 @item poly64x1_t vreinterpret_p64_u32 (uint32x2_t)
10707 @end itemize
10708
10709
10710 @itemize @bullet
10711 @item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
10712 @end itemize
10713
10714
10715 @itemize @bullet
10716 @item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
10717 @end itemize
10718
10719
10720 @itemize @bullet
10721 @item int64x1_t vreinterpret_s64_f32 (float32x2_t)
10722 @end itemize
10723
10724
10725 @itemize @bullet
10726 @item int64x1_t vreinterpret_s64_p64 (poly64x1_t)
10727 @end itemize
10728
10729
10730 @itemize @bullet
10731 @item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
10732 @end itemize
10733
10734
10735 @itemize @bullet
10736 @item int64x1_t vreinterpret_s64_s8 (int8x8_t)
10737 @end itemize
10738
10739
10740 @itemize @bullet
10741 @item int64x1_t vreinterpret_s64_s16 (int16x4_t)
10742 @end itemize
10743
10744
10745 @itemize @bullet
10746 @item int64x1_t vreinterpret_s64_s32 (int32x2_t)
10747 @end itemize
10748
10749
10750 @itemize @bullet
10751 @item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
10752 @end itemize
10753
10754
10755 @itemize @bullet
10756 @item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
10757 @end itemize
10758
10759
10760 @itemize @bullet
10761 @item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
10762 @end itemize
10763
10764
10765 @itemize @bullet
10766 @item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
10767 @end itemize
10768
10769
10770 @itemize @bullet
10771 @item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
10772 @end itemize
10773
10774
10775 @itemize @bullet
10776 @item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
10777 @end itemize
10778
10779
10780 @itemize @bullet
10781 @item uint64x1_t vreinterpret_u64_p64 (poly64x1_t)
10782 @end itemize
10783
10784
10785 @itemize @bullet
10786 @item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
10787 @end itemize
10788
10789
10790 @itemize @bullet
10791 @item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
10792 @end itemize
10793
10794
10795 @itemize @bullet
10796 @item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
10797 @end itemize
10798
10799
10800 @itemize @bullet
10801 @item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
10802 @end itemize
10803
10804
10805 @itemize @bullet
10806 @item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
10807 @end itemize
10808
10809
10810 @itemize @bullet
10811 @item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
10812 @end itemize
10813
10814
10815 @itemize @bullet
10816 @item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
10817 @end itemize
10818
10819
10820 @itemize @bullet
10821 @item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
10822 @end itemize
10823
10824
10825 @itemize @bullet
10826 @item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
10827 @end itemize
10828
10829
10830 @itemize @bullet
10831 @item int8x8_t vreinterpret_s8_f32 (float32x2_t)
10832 @end itemize
10833
10834
10835 @itemize @bullet
10836 @item int8x8_t vreinterpret_s8_p64 (poly64x1_t)
10837 @end itemize
10838
10839
10840 @itemize @bullet
10841 @item int8x8_t vreinterpret_s8_s64 (int64x1_t)
10842 @end itemize
10843
10844
10845 @itemize @bullet
10846 @item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
10847 @end itemize
10848
10849
10850 @itemize @bullet
10851 @item int8x8_t vreinterpret_s8_s16 (int16x4_t)
10852 @end itemize
10853
10854
10855 @itemize @bullet
10856 @item int8x8_t vreinterpret_s8_s32 (int32x2_t)
10857 @end itemize
10858
10859
10860 @itemize @bullet
10861 @item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
10862 @end itemize
10863
10864
10865 @itemize @bullet
10866 @item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
10867 @end itemize
10868
10869
10870 @itemize @bullet
10871 @item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
10872 @end itemize
10873
10874
10875 @itemize @bullet
10876 @item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
10877 @end itemize
10878
10879
10880 @itemize @bullet
10881 @item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
10882 @end itemize
10883
10884
10885 @itemize @bullet
10886 @item int16x4_t vreinterpret_s16_f32 (float32x2_t)
10887 @end itemize
10888
10889
10890 @itemize @bullet
10891 @item int16x4_t vreinterpret_s16_p64 (poly64x1_t)
10892 @end itemize
10893
10894
10895 @itemize @bullet
10896 @item int16x4_t vreinterpret_s16_s64 (int64x1_t)
10897 @end itemize
10898
10899
10900 @itemize @bullet
10901 @item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
10902 @end itemize
10903
10904
10905 @itemize @bullet
10906 @item int16x4_t vreinterpret_s16_s8 (int8x8_t)
10907 @end itemize
10908
10909
10910 @itemize @bullet
10911 @item int16x4_t vreinterpret_s16_s32 (int32x2_t)
10912 @end itemize
10913
10914
10915 @itemize @bullet
10916 @item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
10917 @end itemize
10918
10919
10920 @itemize @bullet
10921 @item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
10922 @end itemize
10923
10924
10925 @itemize @bullet
10926 @item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
10927 @end itemize
10928
10929
10930 @itemize @bullet
10931 @item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
10932 @end itemize
10933
10934
10935 @itemize @bullet
10936 @item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
10937 @end itemize
10938
10939
10940 @itemize @bullet
10941 @item int32x2_t vreinterpret_s32_f32 (float32x2_t)
10942 @end itemize
10943
10944
10945 @itemize @bullet
10946 @item int32x2_t vreinterpret_s32_p64 (poly64x1_t)
10947 @end itemize
10948
10949
10950 @itemize @bullet
10951 @item int32x2_t vreinterpret_s32_s64 (int64x1_t)
10952 @end itemize
10953
10954
10955 @itemize @bullet
10956 @item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
10957 @end itemize
10958
10959
10960 @itemize @bullet
10961 @item int32x2_t vreinterpret_s32_s8 (int8x8_t)
10962 @end itemize
10963
10964
10965 @itemize @bullet
10966 @item int32x2_t vreinterpret_s32_s16 (int16x4_t)
10967 @end itemize
10968
10969
10970 @itemize @bullet
10971 @item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
10972 @end itemize
10973
10974
10975 @itemize @bullet
10976 @item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
10977 @end itemize
10978
10979
10980 @itemize @bullet
10981 @item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
10982 @end itemize
10983
10984
10985 @itemize @bullet
10986 @item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
10987 @end itemize
10988
10989
10990 @itemize @bullet
10991 @item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
10992 @end itemize
10993
10994
10995 @itemize @bullet
10996 @item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
10997 @end itemize
10998
10999
11000 @itemize @bullet
11001 @item uint8x8_t vreinterpret_u8_p64 (poly64x1_t)
11002 @end itemize
11003
11004
11005 @itemize @bullet
11006 @item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
11007 @end itemize
11008
11009
11010 @itemize @bullet
11011 @item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
11012 @end itemize
11013
11014
11015 @itemize @bullet
11016 @item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
11017 @end itemize
11018
11019
11020 @itemize @bullet
11021 @item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
11022 @end itemize
11023
11024
11025 @itemize @bullet
11026 @item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
11027 @end itemize
11028
11029
11030 @itemize @bullet
11031 @item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
11032 @end itemize
11033
11034
11035 @itemize @bullet
11036 @item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
11037 @end itemize
11038
11039
11040 @itemize @bullet
11041 @item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
11042 @end itemize
11043
11044
11045 @itemize @bullet
11046 @item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
11047 @end itemize
11048
11049
11050 @itemize @bullet
11051 @item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
11052 @end itemize
11053
11054
11055 @itemize @bullet
11056 @item uint16x4_t vreinterpret_u16_p64 (poly64x1_t)
11057 @end itemize
11058
11059
11060 @itemize @bullet
11061 @item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
11062 @end itemize
11063
11064
11065 @itemize @bullet
11066 @item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
11067 @end itemize
11068
11069
11070 @itemize @bullet
11071 @item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
11072 @end itemize
11073
11074
11075 @itemize @bullet
11076 @item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
11077 @end itemize
11078
11079
11080 @itemize @bullet
11081 @item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
11082 @end itemize
11083
11084
11085 @itemize @bullet
11086 @item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
11087 @end itemize
11088
11089
11090 @itemize @bullet
11091 @item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
11092 @end itemize
11093
11094
11095 @itemize @bullet
11096 @item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
11097 @end itemize
11098
11099
11100 @itemize @bullet
11101 @item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
11102 @end itemize
11103
11104
11105 @itemize @bullet
11106 @item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
11107 @end itemize
11108
11109
11110 @itemize @bullet
11111 @item uint32x2_t vreinterpret_u32_p64 (poly64x1_t)
11112 @end itemize
11113
11114
11115 @itemize @bullet
11116 @item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
11117 @end itemize
11118
11119
11120 @itemize @bullet
11121 @item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
11122 @end itemize
11123
11124
11125 @itemize @bullet
11126 @item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
11127 @end itemize
11128
11129
11130 @itemize @bullet
11131 @item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
11132 @end itemize
11133
11134
11135 @itemize @bullet
11136 @item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
11137 @end itemize
11138
11139
11140 @itemize @bullet
11141 @item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
11142 @end itemize
11143
11144
11145 @itemize @bullet
11146 @item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
11147 @end itemize
11148
11149
11150 @itemize @bullet
11151 @item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
11152 @end itemize
11153
11154
11155 @itemize @bullet
11156 @item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
11157 @end itemize
11158
11159
11160 @itemize @bullet
11161 @item poly8x16_t vreinterpretq_p8_p64 (poly64x2_t)
11162 @end itemize
11163
11164
11165 @itemize @bullet
11166 @item poly8x16_t vreinterpretq_p8_p128 (poly128_t)
11167 @end itemize
11168
11169
11170 @itemize @bullet
11171 @item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
11172 @end itemize
11173
11174
11175 @itemize @bullet
11176 @item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
11177 @end itemize
11178
11179
11180 @itemize @bullet
11181 @item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
11182 @end itemize
11183
11184
11185 @itemize @bullet
11186 @item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
11187 @end itemize
11188
11189
11190 @itemize @bullet
11191 @item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
11192 @end itemize
11193
11194
11195 @itemize @bullet
11196 @item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
11197 @end itemize
11198
11199
11200 @itemize @bullet
11201 @item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
11202 @end itemize
11203
11204
11205 @itemize @bullet
11206 @item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
11207 @end itemize
11208
11209
11210 @itemize @bullet
11211 @item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
11212 @end itemize
11213
11214
11215 @itemize @bullet
11216 @item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
11217 @end itemize
11218
11219
11220 @itemize @bullet
11221 @item poly16x8_t vreinterpretq_p16_p64 (poly64x2_t)
11222 @end itemize
11223
11224
11225 @itemize @bullet
11226 @item poly16x8_t vreinterpretq_p16_p128 (poly128_t)
11227 @end itemize
11228
11229
11230 @itemize @bullet
11231 @item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
11232 @end itemize
11233
11234
11235 @itemize @bullet
11236 @item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
11237 @end itemize
11238
11239
11240 @itemize @bullet
11241 @item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
11242 @end itemize
11243
11244
11245 @itemize @bullet
11246 @item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
11247 @end itemize
11248
11249
11250 @itemize @bullet
11251 @item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
11252 @end itemize
11253
11254
11255 @itemize @bullet
11256 @item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
11257 @end itemize
11258
11259
11260 @itemize @bullet
11261 @item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
11262 @end itemize
11263
11264
11265 @itemize @bullet
11266 @item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
11267 @end itemize
11268
11269
11270 @itemize @bullet
11271 @item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
11272 @end itemize
11273
11274
11275 @itemize @bullet
11276 @item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
11277 @end itemize
11278
11279
11280 @itemize @bullet
11281 @item float32x4_t vreinterpretq_f32_p64 (poly64x2_t)
11282 @end itemize
11283
11284
11285 @itemize @bullet
11286 @item float32x4_t vreinterpretq_f32_p128 (poly128_t)
11287 @end itemize
11288
11289
11290 @itemize @bullet
11291 @item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
11292 @end itemize
11293
11294
11295 @itemize @bullet
11296 @item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
11297 @end itemize
11298
11299
11300 @itemize @bullet
11301 @item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
11302 @end itemize
11303
11304
11305 @itemize @bullet
11306 @item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
11307 @end itemize
11308
11309
11310 @itemize @bullet
11311 @item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
11312 @end itemize
11313
11314
11315 @itemize @bullet
11316 @item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
11317 @end itemize
11318
11319
11320 @itemize @bullet
11321 @item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
11322 @end itemize
11323
11324
11325 @itemize @bullet
11326 @item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
11327 @end itemize
11328
11329
11330 @itemize @bullet
11331 @item poly64x2_t vreinterpretq_p64_p8 (poly8x16_t)
11332 @end itemize
11333
11334
11335 @itemize @bullet
11336 @item poly64x2_t vreinterpretq_p64_p16 (poly16x8_t)
11337 @end itemize
11338
11339
11340 @itemize @bullet
11341 @item poly64x2_t vreinterpretq_p64_f32 (float32x4_t)
11342 @end itemize
11343
11344
11345 @itemize @bullet
11346 @item poly64x2_t vreinterpretq_p64_p128 (poly128_t)
11347 @end itemize
11348
11349
11350 @itemize @bullet
11351 @item poly64x2_t vreinterpretq_p64_s64 (int64x2_t)
11352 @end itemize
11353
11354
11355 @itemize @bullet
11356 @item poly64x2_t vreinterpretq_p64_u64 (uint64x2_t)
11357 @end itemize
11358
11359
11360 @itemize @bullet
11361 @item poly64x2_t vreinterpretq_p64_s8 (int8x16_t)
11362 @end itemize
11363
11364
11365 @itemize @bullet
11366 @item poly64x2_t vreinterpretq_p64_s16 (int16x8_t)
11367 @end itemize
11368
11369
11370 @itemize @bullet
11371 @item poly64x2_t vreinterpretq_p64_s32 (int32x4_t)
11372 @end itemize
11373
11374
11375 @itemize @bullet
11376 @item poly64x2_t vreinterpretq_p64_u8 (uint8x16_t)
11377 @end itemize
11378
11379
11380 @itemize @bullet
11381 @item poly64x2_t vreinterpretq_p64_u16 (uint16x8_t)
11382 @end itemize
11383
11384
11385 @itemize @bullet
11386 @item poly64x2_t vreinterpretq_p64_u32 (uint32x4_t)
11387 @end itemize
11388
11389
11390 @itemize @bullet
11391 @item poly128_t vreinterpretq_p128_p8 (poly8x16_t)
11392 @end itemize
11393
11394
11395 @itemize @bullet
11396 @item poly128_t vreinterpretq_p128_p16 (poly16x8_t)
11397 @end itemize
11398
11399
11400 @itemize @bullet
11401 @item poly128_t vreinterpretq_p128_f32 (float32x4_t)
11402 @end itemize
11403
11404
11405 @itemize @bullet
11406 @item poly128_t vreinterpretq_p128_p64 (poly64x2_t)
11407 @end itemize
11408
11409
11410 @itemize @bullet
11411 @item poly128_t vreinterpretq_p128_s64 (int64x2_t)
11412 @end itemize
11413
11414
11415 @itemize @bullet
11416 @item poly128_t vreinterpretq_p128_u64 (uint64x2_t)
11417 @end itemize
11418
11419
11420 @itemize @bullet
11421 @item poly128_t vreinterpretq_p128_s8 (int8x16_t)
11422 @end itemize
11423
11424
11425 @itemize @bullet
11426 @item poly128_t vreinterpretq_p128_s16 (int16x8_t)
11427 @end itemize
11428
11429
11430 @itemize @bullet
11431 @item poly128_t vreinterpretq_p128_s32 (int32x4_t)
11432 @end itemize
11433
11434
11435 @itemize @bullet
11436 @item poly128_t vreinterpretq_p128_u8 (uint8x16_t)
11437 @end itemize
11438
11439
11440 @itemize @bullet
11441 @item poly128_t vreinterpretq_p128_u16 (uint16x8_t)
11442 @end itemize
11443
11444
11445 @itemize @bullet
11446 @item poly128_t vreinterpretq_p128_u32 (uint32x4_t)
11447 @end itemize
11448
11449
11450 @itemize @bullet
11451 @item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
11452 @end itemize
11453
11454
11455 @itemize @bullet
11456 @item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
11457 @end itemize
11458
11459
11460 @itemize @bullet
11461 @item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
11462 @end itemize
11463
11464
11465 @itemize @bullet
11466 @item int64x2_t vreinterpretq_s64_p64 (poly64x2_t)
11467 @end itemize
11468
11469
11470 @itemize @bullet
11471 @item int64x2_t vreinterpretq_s64_p128 (poly128_t)
11472 @end itemize
11473
11474
11475 @itemize @bullet
11476 @item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
11477 @end itemize
11478
11479
11480 @itemize @bullet
11481 @item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
11482 @end itemize
11483
11484
11485 @itemize @bullet
11486 @item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
11487 @end itemize
11488
11489
11490 @itemize @bullet
11491 @item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
11492 @end itemize
11493
11494
11495 @itemize @bullet
11496 @item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
11497 @end itemize
11498
11499
11500 @itemize @bullet
11501 @item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
11502 @end itemize
11503
11504
11505 @itemize @bullet
11506 @item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
11507 @end itemize
11508
11509
11510 @itemize @bullet
11511 @item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
11512 @end itemize
11513
11514
11515 @itemize @bullet
11516 @item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
11517 @end itemize
11518
11519
11520 @itemize @bullet
11521 @item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
11522 @end itemize
11523
11524
11525 @itemize @bullet
11526 @item uint64x2_t vreinterpretq_u64_p64 (poly64x2_t)
11527 @end itemize
11528
11529
11530 @itemize @bullet
11531 @item uint64x2_t vreinterpretq_u64_p128 (poly128_t)
11532 @end itemize
11533
11534
11535 @itemize @bullet
11536 @item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
11537 @end itemize
11538
11539
11540 @itemize @bullet
11541 @item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
11542 @end itemize
11543
11544
11545 @itemize @bullet
11546 @item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
11547 @end itemize
11548
11549
11550 @itemize @bullet
11551 @item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
11552 @end itemize
11553
11554
11555 @itemize @bullet
11556 @item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
11557 @end itemize
11558
11559
11560 @itemize @bullet
11561 @item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
11562 @end itemize
11563
11564
11565 @itemize @bullet
11566 @item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
11567 @end itemize
11568
11569
11570 @itemize @bullet
11571 @item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
11572 @end itemize
11573
11574
11575 @itemize @bullet
11576 @item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
11577 @end itemize
11578
11579
11580 @itemize @bullet
11581 @item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
11582 @end itemize
11583
11584
11585 @itemize @bullet
11586 @item int8x16_t vreinterpretq_s8_p64 (poly64x2_t)
11587 @end itemize
11588
11589
11590 @itemize @bullet
11591 @item int8x16_t vreinterpretq_s8_p128 (poly128_t)
11592 @end itemize
11593
11594
11595 @itemize @bullet
11596 @item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
11597 @end itemize
11598
11599
11600 @itemize @bullet
11601 @item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
11602 @end itemize
11603
11604
11605 @itemize @bullet
11606 @item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
11607 @end itemize
11608
11609
11610 @itemize @bullet
11611 @item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
11612 @end itemize
11613
11614
11615 @itemize @bullet
11616 @item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
11617 @end itemize
11618
11619
11620 @itemize @bullet
11621 @item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
11622 @end itemize
11623
11624
11625 @itemize @bullet
11626 @item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
11627 @end itemize
11628
11629
11630 @itemize @bullet
11631 @item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
11632 @end itemize
11633
11634
11635 @itemize @bullet
11636 @item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
11637 @end itemize
11638
11639
11640 @itemize @bullet
11641 @item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
11642 @end itemize
11643
11644
11645 @itemize @bullet
11646 @item int16x8_t vreinterpretq_s16_p64 (poly64x2_t)
11647 @end itemize
11648
11649
11650 @itemize @bullet
11651 @item int16x8_t vreinterpretq_s16_p128 (poly128_t)
11652 @end itemize
11653
11654
11655 @itemize @bullet
11656 @item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
11657 @end itemize
11658
11659
11660 @itemize @bullet
11661 @item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
11662 @end itemize
11663
11664
11665 @itemize @bullet
11666 @item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
11667 @end itemize
11668
11669
11670 @itemize @bullet
11671 @item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
11672 @end itemize
11673
11674
11675 @itemize @bullet
11676 @item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
11677 @end itemize
11678
11679
11680 @itemize @bullet
11681 @item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
11682 @end itemize
11683
11684
11685 @itemize @bullet
11686 @item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
11687 @end itemize
11688
11689
11690 @itemize @bullet
11691 @item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
11692 @end itemize
11693
11694
11695 @itemize @bullet
11696 @item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
11697 @end itemize
11698
11699
11700 @itemize @bullet
11701 @item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
11702 @end itemize
11703
11704
11705 @itemize @bullet
11706 @item int32x4_t vreinterpretq_s32_p64 (poly64x2_t)
11707 @end itemize
11708
11709
11710 @itemize @bullet
11711 @item int32x4_t vreinterpretq_s32_p128 (poly128_t)
11712 @end itemize
11713
11714
11715 @itemize @bullet
11716 @item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
11717 @end itemize
11718
11719
11720 @itemize @bullet
11721 @item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
11722 @end itemize
11723
11724
11725 @itemize @bullet
11726 @item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
11727 @end itemize
11728
11729
11730 @itemize @bullet
11731 @item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
11732 @end itemize
11733
11734
11735 @itemize @bullet
11736 @item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
11737 @end itemize
11738
11739
11740 @itemize @bullet
11741 @item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
11742 @end itemize
11743
11744
11745 @itemize @bullet
11746 @item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
11747 @end itemize
11748
11749
11750 @itemize @bullet
11751 @item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
11752 @end itemize
11753
11754
11755 @itemize @bullet
11756 @item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
11757 @end itemize
11758
11759
11760 @itemize @bullet
11761 @item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
11762 @end itemize
11763
11764
11765 @itemize @bullet
11766 @item uint8x16_t vreinterpretq_u8_p64 (poly64x2_t)
11767 @end itemize
11768
11769
11770 @itemize @bullet
11771 @item uint8x16_t vreinterpretq_u8_p128 (poly128_t)
11772 @end itemize
11773
11774
11775 @itemize @bullet
11776 @item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
11777 @end itemize
11778
11779
11780 @itemize @bullet
11781 @item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
11782 @end itemize
11783
11784
11785 @itemize @bullet
11786 @item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
11787 @end itemize
11788
11789
11790 @itemize @bullet
11791 @item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
11792 @end itemize
11793
11794
11795 @itemize @bullet
11796 @item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
11797 @end itemize
11798
11799
11800 @itemize @bullet
11801 @item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
11802 @end itemize
11803
11804
11805 @itemize @bullet
11806 @item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
11807 @end itemize
11808
11809
11810 @itemize @bullet
11811 @item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t)
11812 @end itemize
11813
11814
11815 @itemize @bullet
11816 @item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
11817 @end itemize
11818
11819
11820 @itemize @bullet
11821 @item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
11822 @end itemize
11823
11824
11825 @itemize @bullet
11826 @item uint16x8_t vreinterpretq_u16_p64 (poly64x2_t)
11827 @end itemize
11828
11829
11830 @itemize @bullet
11831 @item uint16x8_t vreinterpretq_u16_p128 (poly128_t)
11832 @end itemize
11833
11834
11835 @itemize @bullet
11836 @item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
11837 @end itemize
11838
11839
11840 @itemize @bullet
11841 @item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
11842 @end itemize
11843
11844
11845 @itemize @bullet
11846 @item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
11847 @end itemize
11848
11849
11850 @itemize @bullet
11851 @item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
11852 @end itemize
11853
11854
11855 @itemize @bullet
11856 @item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
11857 @end itemize
11858
11859
11860 @itemize @bullet
11861 @item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
11862 @end itemize
11863
11864
11865 @itemize @bullet
11866 @item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
11867 @end itemize
11868
11869
11870 @itemize @bullet
11871 @item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)
11872 @end itemize
11873
11874
11875 @itemize @bullet
11876 @item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
11877 @end itemize
11878
11879
11880 @itemize @bullet
11881 @item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
11882 @end itemize
11883
11884
11885 @itemize @bullet
11886 @item uint32x4_t vreinterpretq_u32_p64 (poly64x2_t)
11887 @end itemize
11888
11889
11890 @itemize @bullet
11891 @item uint32x4_t vreinterpretq_u32_p128 (poly128_t)
11892 @end itemize
11893
11894
11895 @itemize @bullet
11896 @item uint32x4_t vreinterpretq_u32_s64 (int64x2_t)
11897 @end itemize
11898
11899
11900 @itemize @bullet
11901 @item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
11902 @end itemize
11903
11904
11905 @itemize @bullet
11906 @item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
11907 @end itemize
11908
11909
11910 @itemize @bullet
11911 @item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
11912 @end itemize
11913
11914
11915 @itemize @bullet
11916 @item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
11917 @end itemize
11918
11919
11920 @itemize @bullet
11921 @item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
11922 @end itemize
11923
11924
11925 @itemize @bullet
11926 @item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
11927 @end itemize
11928
11929
11930
11931
11932
11933 @itemize @bullet
11934 @item poly128_t vldrq_p128(poly128_t const *)
11935 @end itemize
11936
11937 @itemize @bullet
11938 @item void vstrq_p128(poly128_t *, poly128_t)
11939 @end itemize
11940
11941 @itemize @bullet
11942 @item uint64x1_t vceq_p64 (poly64x1_t, poly64x1_t)
11943 @end itemize
11944
11945 @itemize @bullet
11946 @item uint64x1_t vtst_p64 (poly64x1_t, poly64x1_t)
11947 @end itemize
11948
11949 @itemize @bullet
11950 @item uint32_t vsha1h_u32 (uint32_t)
11951 @*@emph{Form of expected instruction(s):} @code{sha1h.32 @var{q0}, @var{q1}}
11952 @end itemize
11953
11954 @itemize @bullet
11955 @item uint32x4_t vsha1cq_u32 (uint32x4_t, uint32_t, uint32x4_t)
11956 @*@emph{Form of expected instruction(s):} @code{sha1c.32 @var{q0}, @var{q1}, @var{q2}}
11957 @end itemize
11958
11959 @itemize @bullet
11960 @item uint32x4_t vsha1pq_u32 (uint32x4_t, uint32_t, uint32x4_t)
11961 @*@emph{Form of expected instruction(s):} @code{sha1p.32 @var{q0}, @var{q1}, @var{q2}}
11962 @end itemize
11963
11964 @itemize @bullet
11965 @item uint32x4_t vsha1mq_u32 (uint32x4_t, uint32_t, uint32x4_t)
11966 @*@emph{Form of expected instruction(s):} @code{sha1m.32 @var{q0}, @var{q1}, @var{q2}}
11967 @end itemize
11968
11969 @itemize @bullet
11970 @item uint32x4_t vsha1su0q_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
11971 @*@emph{Form of expected instruction(s):} @code{sha1su0.32 @var{q0}, @var{q1}, @var{q2}}
11972 @end itemize
11973
11974 @itemize @bullet
11975 @item uint32x4_t vsha1su1q_u32 (uint32x4_t, uint32x4_t)
11976 @*@emph{Form of expected instruction(s):} @code{sha1su1.32 @var{q0}, @var{q1}, @var{q2}}
11977 @end itemize
11978
11979 @itemize @bullet
11980 @item uint32x4_t vsha256hq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
11981 @*@emph{Form of expected instruction(s):} @code{sha256h.32 @var{q0}, @var{q1}, @var{q2}}
11982 @end itemize
11983
11984 @itemize @bullet
11985 @item uint32x4_t vsha256h2q_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
11986 @*@emph{Form of expected instruction(s):} @code{sha256h2.32 @var{q0}, @var{q1}, @var{q2}}
11987 @end itemize
11988
11989 @itemize @bullet
11990 @item uint32x4_t vsha256su0q_u32 (uint32x4_t, uint32x4_t)
11991 @*@emph{Form of expected instruction(s):} @code{sha256su0.32 @var{q0}, @var{q1}}
11992 @end itemize
11993
11994 @itemize @bullet
11995 @item uint32x4_t vsha256su1q_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
11996 @*@emph{Form of expected instruction(s):} @code{sha256su1.32 @var{q0}, @var{q1}, @var{q2}}
11997 @end itemize
11998
11999 @itemize @bullet
12000 @item poly128_t vmull_p64 (poly64_t a, poly64_t b)
12001 @*@emph{Form of expected instruction(s):} @code{vmull.p64 @var{q0}, @var{d1}, @var{d2}}
12002 @end itemize
12003
12004 @itemize @bullet
12005 @item poly128_t vmull_high_p64 (poly64x2_t a, poly64x2_t b)
12006 @*@emph{Form of expected instruction(s):} @code{vmull.p64 @var{q0}, @var{d1}, @var{d2}}
12007 @end itemize
12008