1 @c Copyright (C) 1988, 1989, 1992, 1993, 1994, 1996, 1998, 1999, 2000, 2001,
2 @c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
3 @c Free Software Foundation, Inc.
4 @c This is part of the GCC manual.
5 @c For copying conditions, see the file gcc.texi.
9 @chapter Machine Descriptions
10 @cindex machine descriptions
12 A machine description has two parts: a file of instruction patterns
13 (@file{.md} file) and a C header file of macro definitions.
15 The @file{.md} file for a target machine contains a pattern for each
16 instruction that the target machine supports (or at least each instruction
17 that is worth telling the compiler about). It may also contain comments.
18 A semicolon causes the rest of the line to be a comment, unless the semicolon
19 is inside a quoted string.
21 See the next chapter for information on the C header file.
24 * Overview:: How the machine description is used.
25 * Patterns:: How to write instruction patterns.
26 * Example:: An explained example of a @code{define_insn} pattern.
27 * RTL Template:: The RTL template defines what insns match a pattern.
28 * Output Template:: The output template says how to make assembler code
30 * Output Statement:: For more generality, write C code to output
32 * Predicates:: Controlling what kinds of operands can be used
34 * Constraints:: Fine-tuning operand selection.
35 * Standard Names:: Names mark patterns to use for code generation.
36 * Pattern Ordering:: When the order of patterns makes a difference.
37 * Dependent Patterns:: Having one pattern may make you need another.
38 * Jump Patterns:: Special considerations for patterns for jump insns.
39 * Looping Patterns:: How to define patterns for special looping insns.
40 * Insn Canonicalizations::Canonicalization of Instructions
41 * Expander Definitions::Generating a sequence of several RTL insns
42 for a standard operation.
43 * Insn Splitting:: Splitting Instructions into Multiple Instructions.
44 * Including Patterns:: Including Patterns in Machine Descriptions.
45 * Peephole Definitions::Defining machine-specific peephole optimizations.
46 * Insn Attributes:: Specifying the value of attributes for generated insns.
47 * Conditional Execution::Generating @code{define_insn} patterns for
49 * Constant Definitions::Defining symbolic constants that can be used in the
51 * Iterators:: Using iterators to generate patterns from a template.
55 @section Overview of How the Machine Description is Used
57 There are three main conversions that happen in the compiler:
62 The front end reads the source code and builds a parse tree.
65 The parse tree is used to generate an RTL insn list based on named
69 The insn list is matched against the RTL templates to produce assembler
74 For the generate pass, only the names of the insns matter, from either a
75 named @code{define_insn} or a @code{define_expand}. The compiler will
76 choose the pattern with the right name and apply the operands according
77 to the documentation later in this chapter, without regard for the RTL
78 template or operand constraints. Note that the names the compiler looks
79 for are hard-coded in the compiler---it will ignore unnamed patterns and
80 patterns with names it doesn't know about, but if you don't provide a
81 named pattern it needs, it will abort.
83 If a @code{define_insn} is used, the template given is inserted into the
84 insn list. If a @code{define_expand} is used, one of three things
85 happens, based on the condition logic. The condition logic may manually
86 create new insns for the insn list, say via @code{emit_insn()}, and
87 invoke @code{DONE}. For certain named patterns, it may invoke @code{FAIL} to tell the
88 compiler to use an alternate way of performing that task. If it invokes
89 neither @code{DONE} nor @code{FAIL}, the template given in the pattern
90 is inserted, as if the @code{define_expand} were a @code{define_insn}.
92 Once the insn list is generated, various optimization passes convert,
93 replace, and rearrange the insns in the insn list. This is where the
94 @code{define_split} and @code{define_peephole} patterns get used, for
97 Finally, the insn list's RTL is matched up with the RTL templates in the
98 @code{define_insn} patterns, and those patterns are used to emit the
99 final assembly code. For this purpose, each named @code{define_insn}
100 acts like it's unnamed, since the names are ignored.
103 @section Everything about Instruction Patterns
105 @cindex instruction patterns
108 Each instruction pattern contains an incomplete RTL expression, with pieces
109 to be filled in later, operand constraints that restrict how the pieces can
110 be filled in, and an output pattern or C code to generate the assembler
111 output, all wrapped up in a @code{define_insn} expression.
113 A @code{define_insn} is an RTL expression containing four or five operands:
117 An optional name. The presence of a name indicate that this instruction
118 pattern can perform a certain standard job for the RTL-generation
119 pass of the compiler. This pass knows certain names and will use
120 the instruction patterns with those names, if the names are defined
121 in the machine description.
123 The absence of a name is indicated by writing an empty string
124 where the name should go. Nameless instruction patterns are never
125 used for generating RTL code, but they may permit several simpler insns
126 to be combined later on.
128 Names that are not thus known and used in RTL-generation have no
129 effect; they are equivalent to no name at all.
131 For the purpose of debugging the compiler, you may also specify a
132 name beginning with the @samp{*} character. Such a name is used only
133 for identifying the instruction in RTL dumps; it is entirely equivalent
134 to having a nameless pattern for all other purposes.
137 The @dfn{RTL template} (@pxref{RTL Template}) is a vector of incomplete
138 RTL expressions which show what the instruction should look like. It is
139 incomplete because it may contain @code{match_operand},
140 @code{match_operator}, and @code{match_dup} expressions that stand for
141 operands of the instruction.
143 If the vector has only one element, that element is the template for the
144 instruction pattern. If the vector has multiple elements, then the
145 instruction pattern is a @code{parallel} expression containing the
149 @cindex pattern conditions
150 @cindex conditions, in patterns
151 A condition. This is a string which contains a C expression that is
152 the final test to decide whether an insn body matches this pattern.
154 @cindex named patterns and conditions
155 For a named pattern, the condition (if present) may not depend on
156 the data in the insn being matched, but only the target-machine-type
157 flags. The compiler needs to test these conditions during
158 initialization in order to learn exactly which named instructions are
159 available in a particular run.
162 For nameless patterns, the condition is applied only when matching an
163 individual insn, and only after the insn has matched the pattern's
164 recognition template. The insn's operands may be found in the vector
165 @code{operands}. For an insn where the condition has once matched, it
166 can't be used to control register allocation, for example by excluding
167 certain hard registers or hard register combinations.
170 The @dfn{output template}: a string that says how to output matching
171 insns as assembler code. @samp{%} in this string specifies where
172 to substitute the value of an operand. @xref{Output Template}.
174 When simple substitution isn't general enough, you can specify a piece
175 of C code to compute the output. @xref{Output Statement}.
178 Optionally, a vector containing the values of attributes for insns matching
179 this pattern. @xref{Insn Attributes}.
183 @section Example of @code{define_insn}
184 @cindex @code{define_insn} example
186 Here is an actual example of an instruction pattern, for the 68000/68020.
191 (match_operand:SI 0 "general_operand" "rm"))]
195 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
197 return \"cmpl #0,%0\";
202 This can also be written using braced strings:
207 (match_operand:SI 0 "general_operand" "rm"))]
210 if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
216 This is an instruction that sets the condition codes based on the value of
217 a general operand. It has no condition, so any insn whose RTL description
218 has the form shown may be handled according to this pattern. The name
219 @samp{tstsi} means ``test a @code{SImode} value'' and tells the RTL generation
220 pass that, when it is necessary to test such a value, an insn to do so
221 can be constructed using this pattern.
223 The output control string is a piece of C code which chooses which
224 output template to return based on the kind of operand and the specific
225 type of CPU for which code is being generated.
227 @samp{"rm"} is an operand constraint. Its meaning is explained below.
230 @section RTL Template
231 @cindex RTL insn template
232 @cindex generating insns
233 @cindex insns, generating
234 @cindex recognizing insns
235 @cindex insns, recognizing
237 The RTL template is used to define which insns match the particular pattern
238 and how to find their operands. For named patterns, the RTL template also
239 says how to construct an insn from specified operands.
241 Construction involves substituting specified operands into a copy of the
242 template. Matching involves determining the values that serve as the
243 operands in the insn being matched. Both of these activities are
244 controlled by special expression types that direct matching and
245 substitution of the operands.
248 @findex match_operand
249 @item (match_operand:@var{m} @var{n} @var{predicate} @var{constraint})
250 This expression is a placeholder for operand number @var{n} of
251 the insn. When constructing an insn, operand number @var{n}
252 will be substituted at this point. When matching an insn, whatever
253 appears at this position in the insn will be taken as operand
254 number @var{n}; but it must satisfy @var{predicate} or this instruction
255 pattern will not match at all.
257 Operand numbers must be chosen consecutively counting from zero in
258 each instruction pattern. There may be only one @code{match_operand}
259 expression in the pattern for each operand number. Usually operands
260 are numbered in the order of appearance in @code{match_operand}
261 expressions. In the case of a @code{define_expand}, any operand numbers
262 used only in @code{match_dup} expressions have higher values than all
263 other operand numbers.
265 @var{predicate} is a string that is the name of a function that
266 accepts two arguments, an expression and a machine mode.
267 @xref{Predicates}. During matching, the function will be called with
268 the putative operand as the expression and @var{m} as the mode
269 argument (if @var{m} is not specified, @code{VOIDmode} will be used,
270 which normally causes @var{predicate} to accept any mode). If it
271 returns zero, this instruction pattern fails to match.
272 @var{predicate} may be an empty string; then it means no test is to be
273 done on the operand, so anything which occurs in this position is
276 Most of the time, @var{predicate} will reject modes other than @var{m}---but
277 not always. For example, the predicate @code{address_operand} uses
278 @var{m} as the mode of memory ref that the address should be valid for.
279 Many predicates accept @code{const_int} nodes even though their mode is
282 @var{constraint} controls reloading and the choice of the best register
283 class to use for a value, as explained later (@pxref{Constraints}).
284 If the constraint would be an empty string, it can be omitted.
286 People are often unclear on the difference between the constraint and the
287 predicate. The predicate helps decide whether a given insn matches the
288 pattern. The constraint plays no role in this decision; instead, it
289 controls various decisions in the case of an insn which does match.
291 @findex match_scratch
292 @item (match_scratch:@var{m} @var{n} @var{constraint})
293 This expression is also a placeholder for operand number @var{n}
294 and indicates that operand must be a @code{scratch} or @code{reg}
297 When matching patterns, this is equivalent to
300 (match_operand:@var{m} @var{n} "scratch_operand" @var{pred})
303 but, when generating RTL, it produces a (@code{scratch}:@var{m})
306 If the last few expressions in a @code{parallel} are @code{clobber}
307 expressions whose operands are either a hard register or
308 @code{match_scratch}, the combiner can add or delete them when
309 necessary. @xref{Side Effects}.
312 @item (match_dup @var{n})
313 This expression is also a placeholder for operand number @var{n}.
314 It is used when the operand needs to appear more than once in the
317 In construction, @code{match_dup} acts just like @code{match_operand}:
318 the operand is substituted into the insn being constructed. But in
319 matching, @code{match_dup} behaves differently. It assumes that operand
320 number @var{n} has already been determined by a @code{match_operand}
321 appearing earlier in the recognition template, and it matches only an
322 identical-looking expression.
324 Note that @code{match_dup} should not be used to tell the compiler that
325 a particular register is being used for two operands (example:
326 @code{add} that adds one register to another; the second register is
327 both an input operand and the output operand). Use a matching
328 constraint (@pxref{Simple Constraints}) for those. @code{match_dup} is for the cases where one
329 operand is used in two places in the template, such as an instruction
330 that computes both a quotient and a remainder, where the opcode takes
331 two input operands but the RTL template has to refer to each of those
332 twice; once for the quotient pattern and once for the remainder pattern.
334 @findex match_operator
335 @item (match_operator:@var{m} @var{n} @var{predicate} [@var{operands}@dots{}])
336 This pattern is a kind of placeholder for a variable RTL expression
339 When constructing an insn, it stands for an RTL expression whose
340 expression code is taken from that of operand @var{n}, and whose
341 operands are constructed from the patterns @var{operands}.
343 When matching an expression, it matches an expression if the function
344 @var{predicate} returns nonzero on that expression @emph{and} the
345 patterns @var{operands} match the operands of the expression.
347 Suppose that the function @code{commutative_operator} is defined as
348 follows, to match any expression whose operator is one of the
349 commutative arithmetic operators of RTL and whose mode is @var{mode}:
353 commutative_integer_operator (x, mode)
355 enum machine_mode mode;
357 enum rtx_code code = GET_CODE (x);
358 if (GET_MODE (x) != mode)
360 return (GET_RTX_CLASS (code) == RTX_COMM_ARITH
361 || code == EQ || code == NE);
365 Then the following pattern will match any RTL expression consisting
366 of a commutative operator applied to two general operands:
369 (match_operator:SI 3 "commutative_operator"
370 [(match_operand:SI 1 "general_operand" "g")
371 (match_operand:SI 2 "general_operand" "g")])
374 Here the vector @code{[@var{operands}@dots{}]} contains two patterns
375 because the expressions to be matched all contain two operands.
377 When this pattern does match, the two operands of the commutative
378 operator are recorded as operands 1 and 2 of the insn. (This is done
379 by the two instances of @code{match_operand}.) Operand 3 of the insn
380 will be the entire commutative expression: use @code{GET_CODE
381 (operands[3])} to see which commutative operator was used.
383 The machine mode @var{m} of @code{match_operator} works like that of
384 @code{match_operand}: it is passed as the second argument to the
385 predicate function, and that function is solely responsible for
386 deciding whether the expression to be matched ``has'' that mode.
388 When constructing an insn, argument 3 of the gen-function will specify
389 the operation (i.e.@: the expression code) for the expression to be
390 made. It should be an RTL expression, whose expression code is copied
391 into a new expression whose operands are arguments 1 and 2 of the
392 gen-function. The subexpressions of argument 3 are not used;
393 only its expression code matters.
395 When @code{match_operator} is used in a pattern for matching an insn,
396 it usually best if the operand number of the @code{match_operator}
397 is higher than that of the actual operands of the insn. This improves
398 register allocation because the register allocator often looks at
399 operands 1 and 2 of insns to see if it can do register tying.
401 There is no way to specify constraints in @code{match_operator}. The
402 operand of the insn which corresponds to the @code{match_operator}
403 never has any constraints because it is never reloaded as a whole.
404 However, if parts of its @var{operands} are matched by
405 @code{match_operand} patterns, those parts may have constraints of
409 @item (match_op_dup:@var{m} @var{n}[@var{operands}@dots{}])
410 Like @code{match_dup}, except that it applies to operators instead of
411 operands. When constructing an insn, operand number @var{n} will be
412 substituted at this point. But in matching, @code{match_op_dup} behaves
413 differently. It assumes that operand number @var{n} has already been
414 determined by a @code{match_operator} appearing earlier in the
415 recognition template, and it matches only an identical-looking
418 @findex match_parallel
419 @item (match_parallel @var{n} @var{predicate} [@var{subpat}@dots{}])
420 This pattern is a placeholder for an insn that consists of a
421 @code{parallel} expression with a variable number of elements. This
422 expression should only appear at the top level of an insn pattern.
424 When constructing an insn, operand number @var{n} will be substituted at
425 this point. When matching an insn, it matches if the body of the insn
426 is a @code{parallel} expression with at least as many elements as the
427 vector of @var{subpat} expressions in the @code{match_parallel}, if each
428 @var{subpat} matches the corresponding element of the @code{parallel},
429 @emph{and} the function @var{predicate} returns nonzero on the
430 @code{parallel} that is the body of the insn. It is the responsibility
431 of the predicate to validate elements of the @code{parallel} beyond
432 those listed in the @code{match_parallel}.
434 A typical use of @code{match_parallel} is to match load and store
435 multiple expressions, which can contain a variable number of elements
436 in a @code{parallel}. For example,
440 [(match_parallel 0 "load_multiple_operation"
441 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
442 (match_operand:SI 2 "memory_operand" "m"))
444 (clobber (reg:SI 179))])]
449 This example comes from @file{a29k.md}. The function
450 @code{load_multiple_operation} is defined in @file{a29k.c} and checks
451 that subsequent elements in the @code{parallel} are the same as the
452 @code{set} in the pattern, except that they are referencing subsequent
453 registers and memory locations.
455 An insn that matches this pattern might look like:
459 [(set (reg:SI 20) (mem:SI (reg:SI 100)))
461 (clobber (reg:SI 179))
463 (mem:SI (plus:SI (reg:SI 100)
466 (mem:SI (plus:SI (reg:SI 100)
470 @findex match_par_dup
471 @item (match_par_dup @var{n} [@var{subpat}@dots{}])
472 Like @code{match_op_dup}, but for @code{match_parallel} instead of
473 @code{match_operator}.
477 @node Output Template
478 @section Output Templates and Operand Substitution
479 @cindex output templates
480 @cindex operand substitution
482 @cindex @samp{%} in template
484 The @dfn{output template} is a string which specifies how to output the
485 assembler code for an instruction pattern. Most of the template is a
486 fixed string which is output literally. The character @samp{%} is used
487 to specify where to substitute an operand; it can also be used to
488 identify places where different variants of the assembler require
491 In the simplest case, a @samp{%} followed by a digit @var{n} says to output
492 operand @var{n} at that point in the string.
494 @samp{%} followed by a letter and a digit says to output an operand in an
495 alternate fashion. Four letters have standard, built-in meanings described
496 below. The machine description macro @code{PRINT_OPERAND} can define
497 additional letters with nonstandard meanings.
499 @samp{%c@var{digit}} can be used to substitute an operand that is a
500 constant value without the syntax that normally indicates an immediate
503 @samp{%n@var{digit}} is like @samp{%c@var{digit}} except that the value of
504 the constant is negated before printing.
506 @samp{%a@var{digit}} can be used to substitute an operand as if it were a
507 memory reference, with the actual operand treated as the address. This may
508 be useful when outputting a ``load address'' instruction, because often the
509 assembler syntax for such an instruction requires you to write the operand
510 as if it were a memory reference.
512 @samp{%l@var{digit}} is used to substitute a @code{label_ref} into a jump
515 @samp{%=} outputs a number which is unique to each instruction in the
516 entire compilation. This is useful for making local labels to be
517 referred to more than once in a single template that generates multiple
518 assembler instructions.
520 @samp{%} followed by a punctuation character specifies a substitution that
521 does not use an operand. Only one case is standard: @samp{%%} outputs a
522 @samp{%} into the assembler code. Other nonstandard cases can be
523 defined in the @code{PRINT_OPERAND} macro. You must also define
524 which punctuation characters are valid with the
525 @code{PRINT_OPERAND_PUNCT_VALID_P} macro.
529 The template may generate multiple assembler instructions. Write the text
530 for the instructions, with @samp{\;} between them.
532 @cindex matching operands
533 When the RTL contains two operands which are required by constraint to match
534 each other, the output template must refer only to the lower-numbered operand.
535 Matching operands are not always identical, and the rest of the compiler
536 arranges to put the proper RTL expression for printing into the lower-numbered
539 One use of nonstandard letters or punctuation following @samp{%} is to
540 distinguish between different assembler languages for the same machine; for
541 example, Motorola syntax versus MIT syntax for the 68000. Motorola syntax
542 requires periods in most opcode names, while MIT syntax does not. For
543 example, the opcode @samp{movel} in MIT syntax is @samp{move.l} in Motorola
544 syntax. The same file of patterns is used for both kinds of output syntax,
545 but the character sequence @samp{%.} is used in each place where Motorola
546 syntax wants a period. The @code{PRINT_OPERAND} macro for Motorola syntax
547 defines the sequence to output a period; the macro for MIT syntax defines
550 @cindex @code{#} in template
551 As a special case, a template consisting of the single character @code{#}
552 instructs the compiler to first split the insn, and then output the
553 resulting instructions separately. This helps eliminate redundancy in the
554 output templates. If you have a @code{define_insn} that needs to emit
555 multiple assembler instructions, and there is a matching @code{define_split}
556 already defined, then you can simply use @code{#} as the output template
557 instead of writing an output template that emits the multiple assembler
560 If the macro @code{ASSEMBLER_DIALECT} is defined, you can use construct
561 of the form @samp{@{option0|option1|option2@}} in the templates. These
562 describe multiple variants of assembler language syntax.
563 @xref{Instruction Output}.
565 @node Output Statement
566 @section C Statements for Assembler Output
567 @cindex output statements
568 @cindex C statements for assembler output
569 @cindex generating assembler output
571 Often a single fixed template string cannot produce correct and efficient
572 assembler code for all the cases that are recognized by a single
573 instruction pattern. For example, the opcodes may depend on the kinds of
574 operands; or some unfortunate combinations of operands may require extra
575 machine instructions.
577 If the output control string starts with a @samp{@@}, then it is actually
578 a series of templates, each on a separate line. (Blank lines and
579 leading spaces and tabs are ignored.) The templates correspond to the
580 pattern's constraint alternatives (@pxref{Multi-Alternative}). For example,
581 if a target machine has a two-address add instruction @samp{addr} to add
582 into a register and another @samp{addm} to add a register to memory, you
583 might write this pattern:
586 (define_insn "addsi3"
587 [(set (match_operand:SI 0 "general_operand" "=r,m")
588 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
589 (match_operand:SI 2 "general_operand" "g,r")))]
596 @cindex @code{*} in template
597 @cindex asterisk in template
598 If the output control string starts with a @samp{*}, then it is not an
599 output template but rather a piece of C program that should compute a
600 template. It should execute a @code{return} statement to return the
601 template-string you want. Most such templates use C string literals, which
602 require doublequote characters to delimit them. To include these
603 doublequote characters in the string, prefix each one with @samp{\}.
605 If the output control string is written as a brace block instead of a
606 double-quoted string, it is automatically assumed to be C code. In that
607 case, it is not necessary to put in a leading asterisk, or to escape the
608 doublequotes surrounding C string literals.
610 The operands may be found in the array @code{operands}, whose C data type
613 It is very common to select different ways of generating assembler code
614 based on whether an immediate operand is within a certain range. Be
615 careful when doing this, because the result of @code{INTVAL} is an
616 integer on the host machine. If the host machine has more bits in an
617 @code{int} than the target machine has in the mode in which the constant
618 will be used, then some of the bits you get from @code{INTVAL} will be
619 superfluous. For proper results, you must carefully disregard the
620 values of those bits.
622 @findex output_asm_insn
623 It is possible to output an assembler instruction and then go on to output
624 or compute more of them, using the subroutine @code{output_asm_insn}. This
625 receives two arguments: a template-string and a vector of operands. The
626 vector may be @code{operands}, or it may be another array of @code{rtx}
627 that you declare locally and initialize yourself.
629 @findex which_alternative
630 When an insn pattern has multiple alternatives in its constraints, often
631 the appearance of the assembler code is determined mostly by which alternative
632 was matched. When this is so, the C code can test the variable
633 @code{which_alternative}, which is the ordinal number of the alternative
634 that was actually satisfied (0 for the first, 1 for the second alternative,
637 For example, suppose there are two opcodes for storing zero, @samp{clrreg}
638 for registers and @samp{clrmem} for memory locations. Here is how
639 a pattern could use @code{which_alternative} to choose between them:
643 [(set (match_operand:SI 0 "general_operand" "=r,m")
647 return (which_alternative == 0
648 ? "clrreg %0" : "clrmem %0");
652 The example above, where the assembler code to generate was
653 @emph{solely} determined by the alternative, could also have been specified
654 as follows, having the output control string start with a @samp{@@}:
659 [(set (match_operand:SI 0 "general_operand" "=r,m")
671 @cindex operand predicates
672 @cindex operator predicates
674 A predicate determines whether a @code{match_operand} or
675 @code{match_operator} expression matches, and therefore whether the
676 surrounding instruction pattern will be used for that combination of
677 operands. GCC has a number of machine-independent predicates, and you
678 can define machine-specific predicates as needed. By convention,
679 predicates used with @code{match_operand} have names that end in
680 @samp{_operand}, and those used with @code{match_operator} have names
681 that end in @samp{_operator}.
683 All predicates are Boolean functions (in the mathematical sense) of
684 two arguments: the RTL expression that is being considered at that
685 position in the instruction pattern, and the machine mode that the
686 @code{match_operand} or @code{match_operator} specifies. In this
687 section, the first argument is called @var{op} and the second argument
688 @var{mode}. Predicates can be called from C as ordinary two-argument
689 functions; this can be useful in output templates or other
690 machine-specific code.
692 Operand predicates can allow operands that are not actually acceptable
693 to the hardware, as long as the constraints give reload the ability to
694 fix them up (@pxref{Constraints}). However, GCC will usually generate
695 better code if the predicates specify the requirements of the machine
696 instructions as closely as possible. Reload cannot fix up operands
697 that must be constants (``immediate operands''); you must use a
698 predicate that allows only constants, or else enforce the requirement
699 in the extra condition.
701 @cindex predicates and machine modes
702 @cindex normal predicates
703 @cindex special predicates
704 Most predicates handle their @var{mode} argument in a uniform manner.
705 If @var{mode} is @code{VOIDmode} (unspecified), then @var{op} can have
706 any mode. If @var{mode} is anything else, then @var{op} must have the
707 same mode, unless @var{op} is a @code{CONST_INT} or integer
708 @code{CONST_DOUBLE}. These RTL expressions always have
709 @code{VOIDmode}, so it would be counterproductive to check that their
710 mode matches. Instead, predicates that accept @code{CONST_INT} and/or
711 integer @code{CONST_DOUBLE} check that the value stored in the
712 constant will fit in the requested mode.
714 Predicates with this behavior are called @dfn{normal}.
715 @command{genrecog} can optimize the instruction recognizer based on
716 knowledge of how normal predicates treat modes. It can also diagnose
717 certain kinds of common errors in the use of normal predicates; for
718 instance, it is almost always an error to use a normal predicate
719 without specifying a mode.
721 Predicates that do something different with their @var{mode} argument
722 are called @dfn{special}. The generic predicates
723 @code{address_operand} and @code{pmode_register_operand} are special
724 predicates. @command{genrecog} does not do any optimizations or
725 diagnosis when special predicates are used.
728 * Machine-Independent Predicates:: Predicates available to all back ends.
729 * Defining Predicates:: How to write machine-specific predicate
733 @node Machine-Independent Predicates
734 @subsection Machine-Independent Predicates
735 @cindex machine-independent predicates
736 @cindex generic predicates
738 These are the generic predicates available to all back ends. They are
739 defined in @file{recog.c}. The first category of predicates allow
740 only constant, or @dfn{immediate}, operands.
742 @defun immediate_operand
743 This predicate allows any sort of constant that fits in @var{mode}.
744 It is an appropriate choice for instructions that take operands that
748 @defun const_int_operand
749 This predicate allows any @code{CONST_INT} expression that fits in
750 @var{mode}. It is an appropriate choice for an immediate operand that
751 does not allow a symbol or label.
754 @defun const_double_operand
755 This predicate accepts any @code{CONST_DOUBLE} expression that has
756 exactly @var{mode}. If @var{mode} is @code{VOIDmode}, it will also
757 accept @code{CONST_INT}. It is intended for immediate floating point
762 The second category of predicates allow only some kind of machine
765 @defun register_operand
766 This predicate allows any @code{REG} or @code{SUBREG} expression that
767 is valid for @var{mode}. It is often suitable for arithmetic
768 instruction operands on a RISC machine.
771 @defun pmode_register_operand
772 This is a slight variant on @code{register_operand} which works around
773 a limitation in the machine-description reader.
776 (match_operand @var{n} "pmode_register_operand" @var{constraint})
783 (match_operand:P @var{n} "register_operand" @var{constraint})
787 would mean, if the machine-description reader accepted @samp{:P}
788 mode suffixes. Unfortunately, it cannot, because @code{Pmode} is an
789 alias for some other mode, and might vary with machine-specific
790 options. @xref{Misc}.
793 @defun scratch_operand
794 This predicate allows hard registers and @code{SCRATCH} expressions,
795 but not pseudo-registers. It is used internally by @code{match_scratch};
796 it should not be used directly.
800 The third category of predicates allow only some kind of memory reference.
802 @defun memory_operand
803 This predicate allows any valid reference to a quantity of mode
804 @var{mode} in memory, as determined by the weak form of
805 @code{GO_IF_LEGITIMATE_ADDRESS} (@pxref{Addressing Modes}).
808 @defun address_operand
809 This predicate is a little unusual; it allows any operand that is a
810 valid expression for the @emph{address} of a quantity of mode
811 @var{mode}, again determined by the weak form of
812 @code{GO_IF_LEGITIMATE_ADDRESS}. To first order, if
813 @samp{@w{(mem:@var{mode} (@var{exp}))}} is acceptable to
814 @code{memory_operand}, then @var{exp} is acceptable to
815 @code{address_operand}. Note that @var{exp} does not necessarily have
819 @defun indirect_operand
820 This is a stricter form of @code{memory_operand} which allows only
821 memory references with a @code{general_operand} as the address
822 expression. New uses of this predicate are discouraged, because
823 @code{general_operand} is very permissive, so it's hard to tell what
824 an @code{indirect_operand} does or does not allow. If a target has
825 different requirements for memory operands for different instructions,
826 it is better to define target-specific predicates which enforce the
827 hardware's requirements explicitly.
831 This predicate allows a memory reference suitable for pushing a value
832 onto the stack. This will be a @code{MEM} which refers to
833 @code{stack_pointer_rtx}, with a side-effect in its address expression
834 (@pxref{Incdec}); which one is determined by the
835 @code{STACK_PUSH_CODE} macro (@pxref{Frame Layout}).
839 This predicate allows a memory reference suitable for popping a value
840 off the stack. Again, this will be a @code{MEM} referring to
841 @code{stack_pointer_rtx}, with a side-effect in its address
842 expression. However, this time @code{STACK_POP_CODE} is expected.
846 The fourth category of predicates allow some combination of the above
849 @defun nonmemory_operand
850 This predicate allows any immediate or register operand valid for @var{mode}.
853 @defun nonimmediate_operand
854 This predicate allows any register or memory operand valid for @var{mode}.
857 @defun general_operand
858 This predicate allows any immediate, register, or memory operand
859 valid for @var{mode}.
863 Finally, there are two generic operator predicates.
865 @defun comparison_operator
866 This predicate matches any expression which performs an arithmetic
867 comparison in @var{mode}; that is, @code{COMPARISON_P} is true for the
871 @defun ordered_comparison_operator
872 This predicate matches any expression which performs an arithmetic
873 comparison in @var{mode} and whose expression code is valid for integer
874 modes; that is, the expression code will be one of @code{eq}, @code{ne},
875 @code{lt}, @code{ltu}, @code{le}, @code{leu}, @code{gt}, @code{gtu},
876 @code{ge}, @code{geu}.
879 @node Defining Predicates
880 @subsection Defining Machine-Specific Predicates
881 @cindex defining predicates
882 @findex define_predicate
883 @findex define_special_predicate
885 Many machines have requirements for their operands that cannot be
886 expressed precisely using the generic predicates. You can define
887 additional predicates using @code{define_predicate} and
888 @code{define_special_predicate} expressions. These expressions have
893 The name of the predicate, as it will be referred to in
894 @code{match_operand} or @code{match_operator} expressions.
897 An RTL expression which evaluates to true if the predicate allows the
898 operand @var{op}, false if it does not. This expression can only use
899 the following RTL codes:
903 When written inside a predicate expression, a @code{MATCH_OPERAND}
904 expression evaluates to true if the predicate it names would allow
905 @var{op}. The operand number and constraint are ignored. Due to
906 limitations in @command{genrecog}, you can only refer to generic
907 predicates and predicates that have already been defined.
910 This expression evaluates to true if @var{op} or a specified
911 subexpression of @var{op} has one of a given list of RTX codes.
913 The first operand of this expression is a string constant containing a
914 comma-separated list of RTX code names (in lower case). These are the
915 codes for which the @code{MATCH_CODE} will be true.
917 The second operand is a string constant which indicates what
918 subexpression of @var{op} to examine. If it is absent or the empty
919 string, @var{op} itself is examined. Otherwise, the string constant
920 must be a sequence of digits and/or lowercase letters. Each character
921 indicates a subexpression to extract from the current expression; for
922 the first character this is @var{op}, for the second and subsequent
923 characters it is the result of the previous character. A digit
924 @var{n} extracts @samp{@w{XEXP (@var{e}, @var{n})}}; a letter @var{l}
925 extracts @samp{@w{XVECEXP (@var{e}, 0, @var{n})}} where @var{n} is the
926 alphabetic ordinal of @var{l} (0 for `a', 1 for 'b', and so on). The
927 @code{MATCH_CODE} then examines the RTX code of the subexpression
928 extracted by the complete string. It is not possible to extract
929 components of an @code{rtvec} that is not at position 0 within its RTX
933 This expression has one operand, a string constant containing a C
934 expression. The predicate's arguments, @var{op} and @var{mode}, are
935 available with those names in the C expression. The @code{MATCH_TEST}
936 evaluates to true if the C expression evaluates to a nonzero value.
937 @code{MATCH_TEST} expressions must not have side effects.
943 The basic @samp{MATCH_} expressions can be combined using these
944 logical operators, which have the semantics of the C operators
945 @samp{&&}, @samp{||}, @samp{!}, and @samp{@w{? :}} respectively. As
946 in Common Lisp, you may give an @code{AND} or @code{IOR} expression an
947 arbitrary number of arguments; this has exactly the same effect as
948 writing a chain of two-argument @code{AND} or @code{IOR} expressions.
952 An optional block of C code, which should execute
953 @samp{@w{return true}} if the predicate is found to match and
954 @samp{@w{return false}} if it does not. It must not have any side
955 effects. The predicate arguments, @var{op} and @var{mode}, are
956 available with those names.
958 If a code block is present in a predicate definition, then the RTL
959 expression must evaluate to true @emph{and} the code block must
960 execute @samp{@w{return true}} for the predicate to allow the operand.
961 The RTL expression is evaluated first; do not re-check anything in the
962 code block that was checked in the RTL expression.
965 The program @command{genrecog} scans @code{define_predicate} and
966 @code{define_special_predicate} expressions to determine which RTX
967 codes are possibly allowed. You should always make this explicit in
968 the RTL predicate expression, using @code{MATCH_OPERAND} and
971 Here is an example of a simple predicate definition, from the IA64
976 ;; @r{True if @var{op} is a @code{SYMBOL_REF} which refers to the sdata section.}
977 (define_predicate "small_addr_symbolic_operand"
978 (and (match_code "symbol_ref")
979 (match_test "SYMBOL_REF_SMALL_ADDR_P (op)")))
984 And here is another, showing the use of the C block.
988 ;; @r{True if @var{op} is a register operand that is (or could be) a GR reg.}
989 (define_predicate "gr_register_operand"
990 (match_operand 0 "register_operand")
993 if (GET_CODE (op) == SUBREG)
994 op = SUBREG_REG (op);
997 return (regno >= FIRST_PSEUDO_REGISTER || GENERAL_REGNO_P (regno));
1002 Predicates written with @code{define_predicate} automatically include
1003 a test that @var{mode} is @code{VOIDmode}, or @var{op} has the same
1004 mode as @var{mode}, or @var{op} is a @code{CONST_INT} or
1005 @code{CONST_DOUBLE}. They do @emph{not} check specifically for
1006 integer @code{CONST_DOUBLE}, nor do they test that the value of either
1007 kind of constant fits in the requested mode. This is because
1008 target-specific predicates that take constants usually have to do more
1009 stringent value checks anyway. If you need the exact same treatment
1010 of @code{CONST_INT} or @code{CONST_DOUBLE} that the generic predicates
1011 provide, use a @code{MATCH_OPERAND} subexpression to call
1012 @code{const_int_operand}, @code{const_double_operand}, or
1013 @code{immediate_operand}.
1015 Predicates written with @code{define_special_predicate} do not get any
1016 automatic mode checks, and are treated as having special mode handling
1017 by @command{genrecog}.
1019 The program @command{genpreds} is responsible for generating code to
1020 test predicates. It also writes a header file containing function
1021 declarations for all machine-specific predicates. It is not necessary
1022 to declare these predicates in @file{@var{cpu}-protos.h}.
1025 @c Most of this node appears by itself (in a different place) even
1026 @c when the INTERNALS flag is clear. Passages that require the internals
1027 @c manual's context are conditionalized to appear only in the internals manual.
1030 @section Operand Constraints
1031 @cindex operand constraints
1034 Each @code{match_operand} in an instruction pattern can specify
1035 constraints for the operands allowed. The constraints allow you to
1036 fine-tune matching within the set of operands allowed by the
1042 @section Constraints for @code{asm} Operands
1043 @cindex operand constraints, @code{asm}
1044 @cindex constraints, @code{asm}
1045 @cindex @code{asm} constraints
1047 Here are specific details on what constraint letters you can use with
1048 @code{asm} operands.
1050 Constraints can say whether
1051 an operand may be in a register, and which kinds of register; whether the
1052 operand can be a memory reference, and which kinds of address; whether the
1053 operand may be an immediate constant, and which possible values it may
1054 have. Constraints can also require two operands to match.
1055 Side-effects aren't allowed in operands of inline @code{asm}, unless
1056 @samp{<} or @samp{>} constraints are used, because there is no guarantee
1057 that the side-effects will happen exactly once in an instruction that can update
1058 the addressing register.
1062 * Simple Constraints:: Basic use of constraints.
1063 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1064 * Class Preferences:: Constraints guide which hard register to put things in.
1065 * Modifiers:: More precise control over effects of constraints.
1066 * Disable Insn Alternatives:: Disable insn alternatives using the @code{enabled} attribute.
1067 * Machine Constraints:: Existing constraints for some particular machines.
1068 * Define Constraints:: How to define machine-specific constraints.
1069 * C Constraint Interface:: How to test constraints from C code.
1075 * Simple Constraints:: Basic use of constraints.
1076 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
1077 * Modifiers:: More precise control over effects of constraints.
1078 * Machine Constraints:: Special constraints for some particular machines.
1082 @node Simple Constraints
1083 @subsection Simple Constraints
1084 @cindex simple constraints
1086 The simplest kind of constraint is a string full of letters, each of
1087 which describes one kind of operand that is permitted. Here are
1088 the letters that are allowed:
1092 Whitespace characters are ignored and can be inserted at any position
1093 except the first. This enables each alternative for different operands to
1094 be visually aligned in the machine description even if they have different
1095 number of constraints and modifiers.
1097 @cindex @samp{m} in constraint
1098 @cindex memory references in constraints
1100 A memory operand is allowed, with any kind of address that the machine
1101 supports in general.
1102 Note that the letter used for the general memory constraint can be
1103 re-defined by a back end using the @code{TARGET_MEM_CONSTRAINT} macro.
1105 @cindex offsettable address
1106 @cindex @samp{o} in constraint
1108 A memory operand is allowed, but only if the address is
1109 @dfn{offsettable}. This means that adding a small integer (actually,
1110 the width in bytes of the operand, as determined by its machine mode)
1111 may be added to the address and the result is also a valid memory
1114 @cindex autoincrement/decrement addressing
1115 For example, an address which is constant is offsettable; so is an
1116 address that is the sum of a register and a constant (as long as a
1117 slightly larger constant is also within the range of address-offsets
1118 supported by the machine); but an autoincrement or autodecrement
1119 address is not offsettable. More complicated indirect/indexed
1120 addresses may or may not be offsettable depending on the other
1121 addressing modes that the machine supports.
1123 Note that in an output operand which can be matched by another
1124 operand, the constraint letter @samp{o} is valid only when accompanied
1125 by both @samp{<} (if the target machine has predecrement addressing)
1126 and @samp{>} (if the target machine has preincrement addressing).
1128 @cindex @samp{V} in constraint
1130 A memory operand that is not offsettable. In other words, anything that
1131 would fit the @samp{m} constraint but not the @samp{o} constraint.
1133 @cindex @samp{<} in constraint
1135 A memory operand with autodecrement addressing (either predecrement or
1136 postdecrement) is allowed. In inline @code{asm} this constraint is only
1137 allowed if the operand is used exactly once in an instruction that can
1138 handle the side-effects. Not using an operand with @samp{<} in constraint
1139 string in the inline @code{asm} pattern at all or using it in multiple
1140 instructions isn't valid, because the side-effects wouldn't be performed
1141 or would be performed more than once. Furthermore, on some targets
1142 the operand with @samp{<} in constraint string must be accompanied by
1143 special instruction suffixes like @code{%U0} instruction suffix on PowerPC
1144 or @code{%P0} on IA-64.
1146 @cindex @samp{>} in constraint
1148 A memory operand with autoincrement addressing (either preincrement or
1149 postincrement) is allowed. In inline @code{asm} the same restrictions
1150 as for @samp{<} apply.
1152 @cindex @samp{r} in constraint
1153 @cindex registers in constraints
1155 A register operand is allowed provided that it is in a general
1158 @cindex constants in constraints
1159 @cindex @samp{i} in constraint
1161 An immediate integer operand (one with constant value) is allowed.
1162 This includes symbolic constants whose values will be known only at
1163 assembly time or later.
1165 @cindex @samp{n} in constraint
1167 An immediate integer operand with a known numeric value is allowed.
1168 Many systems cannot support assembly-time constants for operands less
1169 than a word wide. Constraints for these operands should use @samp{n}
1170 rather than @samp{i}.
1172 @cindex @samp{I} in constraint
1173 @item @samp{I}, @samp{J}, @samp{K}, @dots{} @samp{P}
1174 Other letters in the range @samp{I} through @samp{P} may be defined in
1175 a machine-dependent fashion to permit immediate integer operands with
1176 explicit integer values in specified ranges. For example, on the
1177 68000, @samp{I} is defined to stand for the range of values 1 to 8.
1178 This is the range permitted as a shift count in the shift
1181 @cindex @samp{E} in constraint
1183 An immediate floating operand (expression code @code{const_double}) is
1184 allowed, but only if the target floating point format is the same as
1185 that of the host machine (on which the compiler is running).
1187 @cindex @samp{F} in constraint
1189 An immediate floating operand (expression code @code{const_double} or
1190 @code{const_vector}) is allowed.
1192 @cindex @samp{G} in constraint
1193 @cindex @samp{H} in constraint
1194 @item @samp{G}, @samp{H}
1195 @samp{G} and @samp{H} may be defined in a machine-dependent fashion to
1196 permit immediate floating operands in particular ranges of values.
1198 @cindex @samp{s} in constraint
1200 An immediate integer operand whose value is not an explicit integer is
1203 This might appear strange; if an insn allows a constant operand with a
1204 value not known at compile time, it certainly must allow any known
1205 value. So why use @samp{s} instead of @samp{i}? Sometimes it allows
1206 better code to be generated.
1208 For example, on the 68000 in a fullword instruction it is possible to
1209 use an immediate operand; but if the immediate value is between @minus{}128
1210 and 127, better code results from loading the value into a register and
1211 using the register. This is because the load into the register can be
1212 done with a @samp{moveq} instruction. We arrange for this to happen
1213 by defining the letter @samp{K} to mean ``any integer outside the
1214 range @minus{}128 to 127'', and then specifying @samp{Ks} in the operand
1217 @cindex @samp{g} in constraint
1219 Any register, memory or immediate integer operand is allowed, except for
1220 registers that are not general registers.
1222 @cindex @samp{X} in constraint
1225 Any operand whatsoever is allowed, even if it does not satisfy
1226 @code{general_operand}. This is normally used in the constraint of
1227 a @code{match_scratch} when certain alternatives will not actually
1228 require a scratch register.
1231 Any operand whatsoever is allowed.
1234 @cindex @samp{0} in constraint
1235 @cindex digits in constraint
1236 @item @samp{0}, @samp{1}, @samp{2}, @dots{} @samp{9}
1237 An operand that matches the specified operand number is allowed. If a
1238 digit is used together with letters within the same alternative, the
1239 digit should come last.
1241 This number is allowed to be more than a single digit. If multiple
1242 digits are encountered consecutively, they are interpreted as a single
1243 decimal integer. There is scant chance for ambiguity, since to-date
1244 it has never been desirable that @samp{10} be interpreted as matching
1245 either operand 1 @emph{or} operand 0. Should this be desired, one
1246 can use multiple alternatives instead.
1248 @cindex matching constraint
1249 @cindex constraint, matching
1250 This is called a @dfn{matching constraint} and what it really means is
1251 that the assembler has only a single operand that fills two roles
1253 considered separate in the RTL insn. For example, an add insn has two
1254 input operands and one output operand in the RTL, but on most CISC
1257 which @code{asm} distinguishes. For example, an add instruction uses
1258 two input operands and an output operand, but on most CISC
1260 machines an add instruction really has only two operands, one of them an
1261 input-output operand:
1267 Matching constraints are used in these circumstances.
1268 More precisely, the two operands that match must include one input-only
1269 operand and one output-only operand. Moreover, the digit must be a
1270 smaller number than the number of the operand that uses it in the
1274 For operands to match in a particular case usually means that they
1275 are identical-looking RTL expressions. But in a few special cases
1276 specific kinds of dissimilarity are allowed. For example, @code{*x}
1277 as an input operand will match @code{*x++} as an output operand.
1278 For proper results in such cases, the output template should always
1279 use the output-operand's number when printing the operand.
1282 @cindex load address instruction
1283 @cindex push address instruction
1284 @cindex address constraints
1285 @cindex @samp{p} in constraint
1287 An operand that is a valid memory address is allowed. This is
1288 for ``load address'' and ``push address'' instructions.
1290 @findex address_operand
1291 @samp{p} in the constraint must be accompanied by @code{address_operand}
1292 as the predicate in the @code{match_operand}. This predicate interprets
1293 the mode specified in the @code{match_operand} as the mode of the memory
1294 reference for which the address would be valid.
1296 @cindex other register constraints
1297 @cindex extensible constraints
1298 @item @var{other-letters}
1299 Other letters can be defined in machine-dependent fashion to stand for
1300 particular classes of registers or other arbitrary operand types.
1301 @samp{d}, @samp{a} and @samp{f} are defined on the 68000/68020 to stand
1302 for data, address and floating point registers.
1306 In order to have valid assembler code, each operand must satisfy
1307 its constraint. But a failure to do so does not prevent the pattern
1308 from applying to an insn. Instead, it directs the compiler to modify
1309 the code so that the constraint will be satisfied. Usually this is
1310 done by copying an operand into a register.
1312 Contrast, therefore, the two instruction patterns that follow:
1316 [(set (match_operand:SI 0 "general_operand" "=r")
1317 (plus:SI (match_dup 0)
1318 (match_operand:SI 1 "general_operand" "r")))]
1324 which has two operands, one of which must appear in two places, and
1328 [(set (match_operand:SI 0 "general_operand" "=r")
1329 (plus:SI (match_operand:SI 1 "general_operand" "0")
1330 (match_operand:SI 2 "general_operand" "r")))]
1336 which has three operands, two of which are required by a constraint to be
1337 identical. If we are considering an insn of the form
1340 (insn @var{n} @var{prev} @var{next}
1342 (plus:SI (reg:SI 6) (reg:SI 109)))
1347 the first pattern would not apply at all, because this insn does not
1348 contain two identical subexpressions in the right place. The pattern would
1349 say, ``That does not look like an add instruction; try other patterns''.
1350 The second pattern would say, ``Yes, that's an add instruction, but there
1351 is something wrong with it''. It would direct the reload pass of the
1352 compiler to generate additional insns to make the constraint true. The
1353 results might look like this:
1356 (insn @var{n2} @var{prev} @var{n}
1357 (set (reg:SI 3) (reg:SI 6))
1360 (insn @var{n} @var{n2} @var{next}
1362 (plus:SI (reg:SI 3) (reg:SI 109)))
1366 It is up to you to make sure that each operand, in each pattern, has
1367 constraints that can handle any RTL expression that could be present for
1368 that operand. (When multiple alternatives are in use, each pattern must,
1369 for each possible combination of operand expressions, have at least one
1370 alternative which can handle that combination of operands.) The
1371 constraints don't need to @emph{allow} any possible operand---when this is
1372 the case, they do not constrain---but they must at least point the way to
1373 reloading any possible operand so that it will fit.
1377 If the constraint accepts whatever operands the predicate permits,
1378 there is no problem: reloading is never necessary for this operand.
1380 For example, an operand whose constraints permit everything except
1381 registers is safe provided its predicate rejects registers.
1383 An operand whose predicate accepts only constant values is safe
1384 provided its constraints include the letter @samp{i}. If any possible
1385 constant value is accepted, then nothing less than @samp{i} will do;
1386 if the predicate is more selective, then the constraints may also be
1390 Any operand expression can be reloaded by copying it into a register.
1391 So if an operand's constraints allow some kind of register, it is
1392 certain to be safe. It need not permit all classes of registers; the
1393 compiler knows how to copy a register into another register of the
1394 proper class in order to make an instruction valid.
1396 @cindex nonoffsettable memory reference
1397 @cindex memory reference, nonoffsettable
1399 A nonoffsettable memory reference can be reloaded by copying the
1400 address into a register. So if the constraint uses the letter
1401 @samp{o}, all memory references are taken care of.
1404 A constant operand can be reloaded by allocating space in memory to
1405 hold it as preinitialized data. Then the memory reference can be used
1406 in place of the constant. So if the constraint uses the letters
1407 @samp{o} or @samp{m}, constant operands are not a problem.
1410 If the constraint permits a constant and a pseudo register used in an insn
1411 was not allocated to a hard register and is equivalent to a constant,
1412 the register will be replaced with the constant. If the predicate does
1413 not permit a constant and the insn is re-recognized for some reason, the
1414 compiler will crash. Thus the predicate must always recognize any
1415 objects allowed by the constraint.
1418 If the operand's predicate can recognize registers, but the constraint does
1419 not permit them, it can make the compiler crash. When this operand happens
1420 to be a register, the reload pass will be stymied, because it does not know
1421 how to copy a register temporarily into memory.
1423 If the predicate accepts a unary operator, the constraint applies to the
1424 operand. For example, the MIPS processor at ISA level 3 supports an
1425 instruction which adds two registers in @code{SImode} to produce a
1426 @code{DImode} result, but only if the registers are correctly sign
1427 extended. This predicate for the input operands accepts a
1428 @code{sign_extend} of an @code{SImode} register. Write the constraint
1429 to indicate the type of register that is required for the operand of the
1433 @node Multi-Alternative
1434 @subsection Multiple Alternative Constraints
1435 @cindex multiple alternative constraints
1437 Sometimes a single instruction has multiple alternative sets of possible
1438 operands. For example, on the 68000, a logical-or instruction can combine
1439 register or an immediate value into memory, or it can combine any kind of
1440 operand into a register; but it cannot combine one memory location into
1443 These constraints are represented as multiple alternatives. An alternative
1444 can be described by a series of letters for each operand. The overall
1445 constraint for an operand is made from the letters for this operand
1446 from the first alternative, a comma, the letters for this operand from
1447 the second alternative, a comma, and so on until the last alternative.
1449 Here is how it is done for fullword logical-or on the 68000:
1452 (define_insn "iorsi3"
1453 [(set (match_operand:SI 0 "general_operand" "=m,d")
1454 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1455 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
1459 The first alternative has @samp{m} (memory) for operand 0, @samp{0} for
1460 operand 1 (meaning it must match operand 0), and @samp{dKs} for operand
1461 2. The second alternative has @samp{d} (data register) for operand 0,
1462 @samp{0} for operand 1, and @samp{dmKs} for operand 2. The @samp{=} and
1463 @samp{%} in the constraints apply to all the alternatives; their
1464 meaning is explained in the next section (@pxref{Class Preferences}).
1467 @c FIXME Is this ? and ! stuff of use in asm()? If not, hide unless INTERNAL
1468 If all the operands fit any one alternative, the instruction is valid.
1469 Otherwise, for each alternative, the compiler counts how many instructions
1470 must be added to copy the operands so that that alternative applies.
1471 The alternative requiring the least copying is chosen. If two alternatives
1472 need the same amount of copying, the one that comes first is chosen.
1473 These choices can be altered with the @samp{?} and @samp{!} characters:
1476 @cindex @samp{?} in constraint
1477 @cindex question mark
1479 Disparage slightly the alternative that the @samp{?} appears in,
1480 as a choice when no alternative applies exactly. The compiler regards
1481 this alternative as one unit more costly for each @samp{?} that appears
1484 @cindex @samp{!} in constraint
1485 @cindex exclamation point
1487 Disparage severely the alternative that the @samp{!} appears in.
1488 This alternative can still be used if it fits without reloading,
1489 but if reloading is needed, some other alternative will be used.
1493 When an insn pattern has multiple alternatives in its constraints, often
1494 the appearance of the assembler code is determined mostly by which
1495 alternative was matched. When this is so, the C code for writing the
1496 assembler code can use the variable @code{which_alternative}, which is
1497 the ordinal number of the alternative that was actually satisfied (0 for
1498 the first, 1 for the second alternative, etc.). @xref{Output Statement}.
1502 @node Class Preferences
1503 @subsection Register Class Preferences
1504 @cindex class preference constraints
1505 @cindex register class preference constraints
1507 @cindex voting between constraint alternatives
1508 The operand constraints have another function: they enable the compiler
1509 to decide which kind of hardware register a pseudo register is best
1510 allocated to. The compiler examines the constraints that apply to the
1511 insns that use the pseudo register, looking for the machine-dependent
1512 letters such as @samp{d} and @samp{a} that specify classes of registers.
1513 The pseudo register is put in whichever class gets the most ``votes''.
1514 The constraint letters @samp{g} and @samp{r} also vote: they vote in
1515 favor of a general register. The machine description says which registers
1516 are considered general.
1518 Of course, on some machines all registers are equivalent, and no register
1519 classes are defined. Then none of this complexity is relevant.
1523 @subsection Constraint Modifier Characters
1524 @cindex modifiers in constraints
1525 @cindex constraint modifier characters
1527 @c prevent bad page break with this line
1528 Here are constraint modifier characters.
1531 @cindex @samp{=} in constraint
1533 Means that this operand is write-only for this instruction: the previous
1534 value is discarded and replaced by output data.
1536 @cindex @samp{+} in constraint
1538 Means that this operand is both read and written by the instruction.
1540 When the compiler fixes up the operands to satisfy the constraints,
1541 it needs to know which operands are inputs to the instruction and
1542 which are outputs from it. @samp{=} identifies an output; @samp{+}
1543 identifies an operand that is both input and output; all other operands
1544 are assumed to be input only.
1546 If you specify @samp{=} or @samp{+} in a constraint, you put it in the
1547 first character of the constraint string.
1549 @cindex @samp{&} in constraint
1550 @cindex earlyclobber operand
1552 Means (in a particular alternative) that this operand is an
1553 @dfn{earlyclobber} operand, which is modified before the instruction is
1554 finished using the input operands. Therefore, this operand may not lie
1555 in a register that is used as an input operand or as part of any memory
1558 @samp{&} applies only to the alternative in which it is written. In
1559 constraints with multiple alternatives, sometimes one alternative
1560 requires @samp{&} while others do not. See, for example, the
1561 @samp{movdf} insn of the 68000.
1563 An input operand can be tied to an earlyclobber operand if its only
1564 use as an input occurs before the early result is written. Adding
1565 alternatives of this form often allows GCC to produce better code
1566 when only some of the inputs can be affected by the earlyclobber.
1567 See, for example, the @samp{mulsi3} insn of the ARM@.
1569 @samp{&} does not obviate the need to write @samp{=}.
1571 @cindex @samp{%} in constraint
1573 Declares the instruction to be commutative for this operand and the
1574 following operand. This means that the compiler may interchange the
1575 two operands if that is the cheapest way to make all operands fit the
1578 This is often used in patterns for addition instructions
1579 that really have only two operands: the result must go in one of the
1580 arguments. Here for example, is how the 68000 halfword-add
1581 instruction is defined:
1584 (define_insn "addhi3"
1585 [(set (match_operand:HI 0 "general_operand" "=m,r")
1586 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1587 (match_operand:HI 2 "general_operand" "di,g")))]
1591 GCC can only handle one commutative pair in an asm; if you use more,
1592 the compiler may fail. Note that you need not use the modifier if
1593 the two alternatives are strictly identical; this would only waste
1594 time in the reload pass. The modifier is not operational after
1595 register allocation, so the result of @code{define_peephole2}
1596 and @code{define_split}s performed after reload cannot rely on
1597 @samp{%} to make the intended insn match.
1599 @cindex @samp{#} in constraint
1601 Says that all following characters, up to the next comma, are to be
1602 ignored as a constraint. They are significant only for choosing
1603 register preferences.
1605 @cindex @samp{*} in constraint
1607 Says that the following character should be ignored when choosing
1608 register preferences. @samp{*} has no effect on the meaning of the
1609 constraint as a constraint, and no effect on reloading.
1612 Here is an example: the 68000 has an instruction to sign-extend a
1613 halfword in a data register, and can also sign-extend a value by
1614 copying it into an address register. While either kind of register is
1615 acceptable, the constraints on an address-register destination are
1616 less strict, so it is best if register allocation makes an address
1617 register its goal. Therefore, @samp{*} is used so that the @samp{d}
1618 constraint letter (for data register) is ignored when computing
1619 register preferences.
1622 (define_insn "extendhisi2"
1623 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1625 (match_operand:HI 1 "general_operand" "0,g")))]
1631 @node Machine Constraints
1632 @subsection Constraints for Particular Machines
1633 @cindex machine specific constraints
1634 @cindex constraints, machine specific
1636 Whenever possible, you should use the general-purpose constraint letters
1637 in @code{asm} arguments, since they will convey meaning more readily to
1638 people reading your code. Failing that, use the constraint letters
1639 that usually have very similar meanings across architectures. The most
1640 commonly used constraints are @samp{m} and @samp{r} (for memory and
1641 general-purpose registers respectively; @pxref{Simple Constraints}), and
1642 @samp{I}, usually the letter indicating the most common
1643 immediate-constant format.
1645 Each architecture defines additional constraints. These constraints
1646 are used by the compiler itself for instruction generation, as well as
1647 for @code{asm} statements; therefore, some of the constraints are not
1648 particularly useful for @code{asm}. Here is a summary of some of the
1649 machine-dependent constraints available on some particular machines;
1650 it includes both constraints that are useful for @code{asm} and
1651 constraints that aren't. The compiler source file mentioned in the
1652 table heading for each architecture is the definitive reference for
1653 the meanings of that architecture's constraints.
1656 @item ARM family---@file{config/arm/arm.h}
1659 Floating-point register
1662 VFP floating-point register
1665 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0, 4.0, 5.0
1669 Floating-point constant that would satisfy the constraint @samp{F} if it
1673 Integer that is valid as an immediate operand in a data processing
1674 instruction. That is, an integer in the range 0 to 255 rotated by a
1678 Integer in the range @minus{}4095 to 4095
1681 Integer that satisfies constraint @samp{I} when inverted (ones complement)
1684 Integer that satisfies constraint @samp{I} when negated (twos complement)
1687 Integer in the range 0 to 32
1690 A memory reference where the exact address is in a single register
1691 (`@samp{m}' is preferable for @code{asm} statements)
1694 An item in the constant pool
1697 A symbol in the text segment of the current file
1700 A memory reference suitable for VFP load/store insns (reg+constant offset)
1703 A memory reference suitable for iWMMXt load/store instructions.
1706 A memory reference suitable for the ARMv4 ldrsb instruction.
1709 @item AVR family---@file{config/avr/constraints.md}
1712 Registers from r0 to r15
1715 Registers from r16 to r23
1718 Registers from r16 to r31
1721 Registers from r24 to r31. These registers can be used in @samp{adiw} command
1724 Pointer register (r26--r31)
1727 Base pointer register (r28--r31)
1730 Stack pointer register (SPH:SPL)
1733 Temporary register r0
1736 Register pair X (r27:r26)
1739 Register pair Y (r29:r28)
1742 Register pair Z (r31:r30)
1745 Constant greater than @minus{}1, less than 64
1748 Constant greater than @minus{}64, less than 1
1757 Constant that fits in 8 bits
1760 Constant integer @minus{}1
1763 Constant integer 8, 16, or 24
1769 A floating point constant 0.0
1772 A memory address based on Y or Z pointer with displacement.
1775 @item Epiphany---@file{config/epiphany/constraints.md}
1778 An unsigned 16-bit constant.
1781 An unsigned 5-bit constant.
1784 A signed 11-bit constant.
1787 A signed 11-bit constant added to @minus{}1.
1788 Can only match when the @option{-m1reg-@var{reg}} option is active.
1791 Left-shift of @minus{}1, i.e., a bit mask with a block of leading ones, the rest
1792 being a block of trailing zeroes.
1793 Can only match when the @option{-m1reg-@var{reg}} option is active.
1796 Right-shift of @minus{}1, i.e., a bit mask with a trailing block of ones, the
1797 rest being zeroes. Or to put it another way, one less than a power of two.
1798 Can only match when the @option{-m1reg-@var{reg}} option is active.
1801 Constant for arithmetic/logical operations.
1802 This is like @code{i}, except that for position independent code,
1803 no symbols / expressions needing relocations are allowed.
1806 Symbolic constant for call/jump instruction.
1809 The register class usable in short insns. This is a register class
1810 constraint, and can thus drive register allocation.
1811 This constraint won't match unless @option{-mprefer-short-insn-regs} is
1815 The the register class of registers that can be used to hold a
1816 sibcall call address. I.e., a caller-saved register.
1819 Core control register class.
1822 The register group usable in short insns.
1823 This constraint does not use a register class, so that it only
1824 passively matches suitable registers, and doesn't drive register allocation.
1828 Constant suitable for the addsi3_r pattern. This is a valid offset
1829 For byte, halfword, or word addressing.
1833 Matches the return address if it can be replaced with the link register.
1836 Matches the integer condition code register.
1839 Matches the return address if it is in a stack slot.
1842 Matches control register values to switch fp mode, which are encapsulated in
1843 @code{UNSPEC_FP_MODE}.
1846 @item CR16 Architecture---@file{config/cr16/cr16.h}
1850 Registers from r0 to r14 (registers without stack pointer)
1853 Register from r0 to r11 (all 16-bit registers)
1856 Register from r12 to r15 (all 32-bit registers)
1859 Signed constant that fits in 4 bits
1862 Signed constant that fits in 5 bits
1865 Signed constant that fits in 6 bits
1868 Unsigned constant that fits in 4 bits
1871 Signed constant that fits in 32 bits
1874 Check for 64 bits wide constants for add/sub instructions
1877 Floating point constant that is legal for store immediate
1880 @item Hewlett-Packard PA-RISC---@file{config/pa/pa.h}
1886 Floating point register
1889 Shift amount register
1892 Floating point register (deprecated)
1895 Upper floating point register (32-bit), floating point register (64-bit)
1901 Signed 11-bit integer constant
1904 Signed 14-bit integer constant
1907 Integer constant that can be deposited with a @code{zdepi} instruction
1910 Signed 5-bit integer constant
1916 Integer constant that can be loaded with a @code{ldil} instruction
1919 Integer constant whose value plus one is a power of 2
1922 Integer constant that can be used for @code{and} operations in @code{depi}
1923 and @code{extru} instructions
1932 Floating-point constant 0.0
1935 A @code{lo_sum} data-linkage-table memory operand
1938 A memory operand that can be used as the destination operand of an
1939 integer store instruction
1942 A scaled or unscaled indexed memory operand
1945 A memory operand for floating-point loads and stores
1948 A register indirect memory operand
1951 @item picoChip family---@file{picochip.h}
1957 Pointer register. A register which can be used to access memory without
1958 supplying an offset. Any other register can be used to access memory,
1959 but will need a constant offset. In the case of the offset being zero,
1960 it is more efficient to use a pointer register, since this reduces code
1964 A twin register. A register which may be paired with an adjacent
1965 register to create a 32-bit register.
1968 Any absolute memory address (e.g., symbolic constant, symbolic
1972 4-bit signed integer.
1975 4-bit unsigned integer.
1978 8-bit signed integer.
1981 Any constant whose absolute value is no greater than 4-bits.
1984 10-bit signed integer
1987 16-bit signed integer.
1991 @item PowerPC and IBM RS6000---@file{config/rs6000/rs6000.h}
1994 Address base register
1997 Floating point register (containing 64-bit value)
2000 Floating point register (containing 32-bit value)
2003 Altivec vector register
2006 VSX vector register to hold vector double data
2009 VSX vector register to hold vector float data
2012 VSX vector register to hold scalar float data
2018 @samp{MQ}, @samp{CTR}, or @samp{LINK} register
2027 @samp{LINK} register
2030 @samp{CR} register (condition register) number 0
2033 @samp{CR} register (condition register)
2036 @samp{XER[CA]} carry bit (part of the XER register)
2039 Signed 16-bit constant
2042 Unsigned 16-bit constant shifted left 16 bits (use @samp{L} instead for
2043 @code{SImode} constants)
2046 Unsigned 16-bit constant
2049 Signed 16-bit constant shifted left 16 bits
2052 Constant larger than 31
2061 Constant whose negation is a signed 16-bit constant
2064 Floating point constant that can be loaded into a register with one
2065 instruction per word
2068 Integer/Floating point constant that can be loaded into a register using
2073 Normally, @code{m} does not allow addresses that update the base register.
2074 If @samp{<} or @samp{>} constraint is also used, they are allowed and
2075 therefore on PowerPC targets in that case it is only safe
2076 to use @samp{m<>} in an @code{asm} statement if that @code{asm} statement
2077 accesses the operand exactly once. The @code{asm} statement must also
2078 use @samp{%U@var{<opno>}} as a placeholder for the ``update'' flag in the
2079 corresponding load or store instruction. For example:
2082 asm ("st%U0 %1,%0" : "=m<>" (mem) : "r" (val));
2088 asm ("st %1,%0" : "=m<>" (mem) : "r" (val));
2094 A ``stable'' memory operand; that is, one which does not include any
2095 automodification of the base register. This used to be useful when
2096 @samp{m} allowed automodification of the base register, but as those are now only
2097 allowed when @samp{<} or @samp{>} is used, @samp{es} is basically the same
2098 as @samp{m} without @samp{<} and @samp{>}.
2101 Memory operand that is an offset from a register (it is usually better
2102 to use @samp{m} or @samp{es} in @code{asm} statements)
2105 Memory operand that is an indexed or indirect from a register (it is
2106 usually better to use @samp{m} or @samp{es} in @code{asm} statements)
2112 Address operand that is an indexed or indirect from a register (@samp{p} is
2113 preferable for @code{asm} statements)
2116 Constant suitable as a 64-bit mask operand
2119 Constant suitable as a 32-bit mask operand
2122 System V Release 4 small data area reference
2125 AND masks that can be performed by two rldic@{l, r@} instructions
2128 Vector constant that does not require memory
2131 Vector constant that is all zeros.
2135 @item Intel 386---@file{config/i386/constraints.md}
2138 Legacy register---the eight integer registers available on all
2139 i386 processors (@code{a}, @code{b}, @code{c}, @code{d},
2140 @code{si}, @code{di}, @code{bp}, @code{sp}).
2143 Any register accessible as @code{@var{r}l}. In 32-bit mode, @code{a},
2144 @code{b}, @code{c}, and @code{d}; in 64-bit mode, any integer register.
2147 Any register accessible as @code{@var{r}h}: @code{a}, @code{b},
2148 @code{c}, and @code{d}.
2152 Any register that can be used as the index in a base+index memory
2153 access: that is, any general register except the stack pointer.
2157 The @code{a} register.
2160 The @code{b} register.
2163 The @code{c} register.
2166 The @code{d} register.
2169 The @code{si} register.
2172 The @code{di} register.
2175 The @code{a} and @code{d} registers. This class is used for instructions
2176 that return double word results in the @code{ax:dx} register pair. Single
2177 word values will be allocated either in @code{ax} or @code{dx}.
2178 For example on i386 the following implements @code{rdtsc}:
2181 unsigned long long rdtsc (void)
2183 unsigned long long tick;
2184 __asm__ __volatile__("rdtsc":"=A"(tick));
2189 This is not correct on x86_64 as it would allocate tick in either @code{ax}
2190 or @code{dx}. You have to use the following variant instead:
2193 unsigned long long rdtsc (void)
2195 unsigned int tickl, tickh;
2196 __asm__ __volatile__("rdtsc":"=a"(tickl),"=d"(tickh));
2197 return ((unsigned long long)tickh << 32)|tickl;
2203 Any 80387 floating-point (stack) register.
2206 Top of 80387 floating-point stack (@code{%st(0)}).
2209 Second from top of 80387 floating-point stack (@code{%st(1)}).
2218 First SSE register (@code{%xmm0}).
2222 Any SSE register, when SSE2 is enabled.
2225 Any SSE register, when SSE2 and inter-unit moves are enabled.
2228 Any MMX register, when inter-unit moves are enabled.
2232 Integer constant in the range 0 @dots{} 31, for 32-bit shifts.
2235 Integer constant in the range 0 @dots{} 63, for 64-bit shifts.
2238 Signed 8-bit integer constant.
2241 @code{0xFF} or @code{0xFFFF}, for andsi as a zero-extending move.
2244 0, 1, 2, or 3 (shifts for the @code{lea} instruction).
2247 Unsigned 8-bit integer constant (for @code{in} and @code{out}
2252 Integer constant in the range 0 @dots{} 127, for 128-bit shifts.
2256 Standard 80387 floating point constant.
2259 Standard SSE floating point constant.
2262 32-bit signed integer constant, or a symbolic reference known
2263 to fit that range (for immediate operands in sign-extending x86-64
2267 32-bit unsigned integer constant, or a symbolic reference known
2268 to fit that range (for immediate operands in zero-extending x86-64
2273 @item Intel IA-64---@file{config/ia64/ia64.h}
2276 General register @code{r0} to @code{r3} for @code{addl} instruction
2282 Predicate register (@samp{c} as in ``conditional'')
2285 Application register residing in M-unit
2288 Application register residing in I-unit
2291 Floating-point register
2294 Memory operand. If used together with @samp{<} or @samp{>},
2295 the operand can have postincrement and postdecrement which
2296 require printing with @samp{%Pn} on IA-64.
2299 Floating-point constant 0.0 or 1.0
2302 14-bit signed integer constant
2305 22-bit signed integer constant
2308 8-bit signed integer constant for logical instructions
2311 8-bit adjusted signed integer constant for compare pseudo-ops
2314 6-bit unsigned integer constant for shift counts
2317 9-bit signed integer constant for load and store postincrements
2323 0 or @minus{}1 for @code{dep} instruction
2326 Non-volatile memory for floating-point loads and stores
2329 Integer constant in the range 1 to 4 for @code{shladd} instruction
2332 Memory operand except postincrement and postdecrement. This is
2333 now roughly the same as @samp{m} when not used together with @samp{<}
2337 @item FRV---@file{config/frv/frv.h}
2340 Register in the class @code{ACC_REGS} (@code{acc0} to @code{acc7}).
2343 Register in the class @code{EVEN_ACC_REGS} (@code{acc0} to @code{acc7}).
2346 Register in the class @code{CC_REGS} (@code{fcc0} to @code{fcc3} and
2347 @code{icc0} to @code{icc3}).
2350 Register in the class @code{GPR_REGS} (@code{gr0} to @code{gr63}).
2353 Register in the class @code{EVEN_REGS} (@code{gr0} to @code{gr63}).
2354 Odd registers are excluded not in the class but through the use of a machine
2355 mode larger than 4 bytes.
2358 Register in the class @code{FPR_REGS} (@code{fr0} to @code{fr63}).
2361 Register in the class @code{FEVEN_REGS} (@code{fr0} to @code{fr63}).
2362 Odd registers are excluded not in the class but through the use of a machine
2363 mode larger than 4 bytes.
2366 Register in the class @code{LR_REG} (the @code{lr} register).
2369 Register in the class @code{QUAD_REGS} (@code{gr2} to @code{gr63}).
2370 Register numbers not divisible by 4 are excluded not in the class but through
2371 the use of a machine mode larger than 8 bytes.
2374 Register in the class @code{ICC_REGS} (@code{icc0} to @code{icc3}).
2377 Register in the class @code{FCC_REGS} (@code{fcc0} to @code{fcc3}).
2380 Register in the class @code{ICR_REGS} (@code{cc4} to @code{cc7}).
2383 Register in the class @code{FCR_REGS} (@code{cc0} to @code{cc3}).
2386 Register in the class @code{QUAD_FPR_REGS} (@code{fr0} to @code{fr63}).
2387 Register numbers not divisible by 4 are excluded not in the class but through
2388 the use of a machine mode larger than 8 bytes.
2391 Register in the class @code{SPR_REGS} (@code{lcr} and @code{lr}).
2394 Register in the class @code{QUAD_ACC_REGS} (@code{acc0} to @code{acc7}).
2397 Register in the class @code{ACCG_REGS} (@code{accg0} to @code{accg7}).
2400 Register in the class @code{CR_REGS} (@code{cc0} to @code{cc7}).
2403 Floating point constant zero
2406 6-bit signed integer constant
2409 10-bit signed integer constant
2412 16-bit signed integer constant
2415 16-bit unsigned integer constant
2418 12-bit signed integer constant that is negative---i.e.@: in the
2419 range of @minus{}2048 to @minus{}1
2425 12-bit signed integer constant that is greater than zero---i.e.@: in the
2430 @item Blackfin family---@file{config/bfin/constraints.md}
2439 A call clobbered P register.
2442 A single register. If @var{n} is in the range 0 to 7, the corresponding D
2443 register. If it is @code{A}, then the register P0.
2446 Even-numbered D register
2449 Odd-numbered D register
2452 Accumulator register.
2455 Even-numbered accumulator register.
2458 Odd-numbered accumulator register.
2470 Registers used for circular buffering, i.e. I, B, or L registers.
2485 Any D, P, B, M, I or L register.
2488 Additional registers typically used only in prologues and epilogues: RETS,
2489 RETN, RETI, RETX, RETE, ASTAT, SEQSTAT and USP.
2492 Any register except accumulators or CC.
2495 Signed 16 bit integer (in the range @minus{}32768 to 32767)
2498 Unsigned 16 bit integer (in the range 0 to 65535)
2501 Signed 7 bit integer (in the range @minus{}64 to 63)
2504 Unsigned 7 bit integer (in the range 0 to 127)
2507 Unsigned 5 bit integer (in the range 0 to 31)
2510 Signed 4 bit integer (in the range @minus{}8 to 7)
2513 Signed 3 bit integer (in the range @minus{}3 to 4)
2516 Unsigned 3 bit integer (in the range 0 to 7)
2519 Constant @var{n}, where @var{n} is a single-digit constant in the range 0 to 4.
2522 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2523 use with either accumulator.
2526 An integer equal to one of the MACFLAG_XXX constants that is suitable for
2527 use only with accumulator A1.
2536 An integer constant with exactly a single bit set.
2539 An integer constant with all bits set except exactly one.
2547 @item M32C---@file{config/m32c/m32c.c}
2552 @samp{$sp}, @samp{$fb}, @samp{$sb}.
2555 Any control register, when they're 16 bits wide (nothing if control
2556 registers are 24 bits wide)
2559 Any control register, when they're 24 bits wide.
2568 $r0 or $r2, or $r2r0 for 32 bit values.
2571 $r1 or $r3, or $r3r1 for 32 bit values.
2574 A register that can hold a 64 bit value.
2577 $r0 or $r1 (registers with addressable high/low bytes)
2586 Address registers when they're 16 bits wide.
2589 Address registers when they're 24 bits wide.
2592 Registers that can hold QI values.
2595 Registers that can be used with displacements ($a0, $a1, $sb).
2598 Registers that can hold 32 bit values.
2601 Registers that can hold 16 bit values.
2604 Registers chat can hold 16 bit values, including all control
2608 $r0 through R1, plus $a0 and $a1.
2614 The memory-based pseudo-registers $mem0 through $mem15.
2617 Registers that can hold pointers (16 bit registers for r8c, m16c; 24
2618 bit registers for m32cm, m32c).
2621 Matches multiple registers in a PARALLEL to form a larger register.
2622 Used to match function return values.
2628 @minus{}128 @dots{} 127
2631 @minus{}32768 @dots{} 32767
2637 @minus{}8 @dots{} @minus{}1 or 1 @dots{} 8
2640 @minus{}16 @dots{} @minus{}1 or 1 @dots{} 16
2643 @minus{}32 @dots{} @minus{}1 or 1 @dots{} 32
2646 @minus{}65536 @dots{} @minus{}1
2649 An 8 bit value with exactly one bit set.
2652 A 16 bit value with exactly one bit set.
2655 The common src/dest memory addressing modes.
2658 Memory addressed using $a0 or $a1.
2661 Memory addressed with immediate addresses.
2664 Memory addressed using the stack pointer ($sp).
2667 Memory addressed using the frame base register ($fb).
2670 Memory addressed using the small base register ($sb).
2676 @item MeP---@file{config/mep/constraints.md}
2686 Any control register.
2689 Either the $hi or the $lo register.
2692 Coprocessor registers that can be directly loaded ($c0-$c15).
2695 Coprocessor registers that can be moved to each other.
2698 Coprocessor registers that can be moved to core registers.
2710 Registers which can be used in $tp-relative addressing.
2716 The coprocessor registers.
2719 The coprocessor control registers.
2725 User-defined register set A.
2728 User-defined register set B.
2731 User-defined register set C.
2734 User-defined register set D.
2737 Offsets for $gp-rel addressing.
2740 Constants that can be used directly with boolean insns.
2743 Constants that can be moved directly to registers.
2746 Small constants that can be added to registers.
2752 Small constants that can be compared to registers.
2755 Constants that can be loaded into the top half of registers.
2758 Signed 8-bit immediates.
2761 Symbols encoded for $tp-rel or $gp-rel addressing.
2764 Non-constant addresses for loading/saving coprocessor registers.
2767 The top half of a symbol's value.
2770 A register indirect address without offset.
2773 Symbolic references to the control bus.
2777 @item MicroBlaze---@file{config/microblaze/constraints.md}
2780 A general register (@code{r0} to @code{r31}).
2783 A status register (@code{rmsr}, @code{$fcc1} to @code{$fcc7}).
2787 @item MIPS---@file{config/mips/constraints.md}
2790 An address register. This is equivalent to @code{r} unless
2791 generating MIPS16 code.
2794 A floating-point register (if available).
2797 Formerly the @code{hi} register. This constraint is no longer supported.
2800 The @code{lo} register. Use this register to store values that are
2801 no bigger than a word.
2804 The concatenated @code{hi} and @code{lo} registers. Use this register
2805 to store doubleword values.
2808 A register suitable for use in an indirect jump. This will always be
2809 @code{$25} for @option{-mabicalls}.
2812 Register @code{$3}. Do not use this constraint in new code;
2813 it is retained only for compatibility with glibc.
2816 Equivalent to @code{r}; retained for backwards compatibility.
2819 A floating-point condition code register.
2822 A signed 16-bit constant (for arithmetic instructions).
2828 An unsigned 16-bit constant (for logic instructions).
2831 A signed 32-bit constant in which the lower 16 bits are zero.
2832 Such constants can be loaded using @code{lui}.
2835 A constant that cannot be loaded using @code{lui}, @code{addiu}
2839 A constant in the range @minus{}65535 to @minus{}1 (inclusive).
2842 A signed 15-bit constant.
2845 A constant in the range 1 to 65535 (inclusive).
2848 Floating-point zero.
2851 An address that can be used in a non-macro load or store.
2854 @item Motorola 680x0---@file{config/m68k/constraints.md}
2863 68881 floating-point register, if available
2866 Integer in the range 1 to 8
2869 16-bit signed number
2872 Signed number whose magnitude is greater than 0x80
2875 Integer in the range @minus{}8 to @minus{}1
2878 Signed number whose magnitude is greater than 0x100
2881 Range 24 to 31, rotatert:SI 8 to 1 expressed as rotate
2884 16 (for rotate using swap)
2887 Range 8 to 15, rotatert:HI 8 to 1 expressed as rotate
2890 Numbers that mov3q can handle
2893 Floating point constant that is not a 68881 constant
2896 Operands that satisfy 'm' when -mpcrel is in effect
2899 Operands that satisfy 's' when -mpcrel is not in effect
2902 Address register indirect addressing mode
2905 Register offset addressing
2920 Range of signed numbers that don't fit in 16 bits
2923 Integers valid for mvq
2926 Integers valid for a moveq followed by a swap
2929 Integers valid for mvz
2932 Integers valid for mvs
2938 Non-register operands allowed in clr
2942 @item Moxie---@file{config/moxie/constraints.md}
2951 A register indirect memory operand
2954 A constant in the range of 0 to 255.
2957 A constant in the range of 0 to @minus{}255.
2961 @item PDP-11---@file{config/pdp11/constraints.md}
2964 Floating point registers AC0 through AC3. These can be loaded from/to
2965 memory with a single instruction.
2968 Odd numbered general registers (R1, R3, R5). These are used for
2969 16-bit multiply operations.
2972 Any of the floating point registers (AC0 through AC5).
2975 Floating point constant 0.
2978 An integer constant that fits in 16 bits.
2981 An integer constant whose low order 16 bits are zero.
2984 An integer constant that does not meet the constraints for codes
2985 @samp{I} or @samp{J}.
2988 The integer constant 1.
2991 The integer constant @minus{}1.
2994 The integer constant 0.
2997 Integer constants @minus{}4 through @minus{}1 and 1 through 4; shifts by these
2998 amounts are handled as multiple single-bit shifts rather than a single
2999 variable-length shift.
3002 A memory reference which requires an additional word (address or
3003 offset) after the opcode.
3006 A memory reference that is encoded within the opcode.
3010 @item RL78---@file{config/rl78/constraints.md}
3014 An integer constant in the range 1 @dots{} 7.
3016 An integer constant in the range 0 @dots{} 255.
3018 An integer constant in the range @minus{}255 @dots{} 0
3020 The integer constant 1.
3022 The integer constant -1.
3024 The integer constant 0.
3026 The integer constant 2.
3028 The integer constant -2.
3030 An integer constant in the range 1 @dots{} 15.
3032 The built-in compare types--eq, ne, gtu, ltu, geu, and leu.
3034 The synthetic compare types--gt, lt, ge, and le.
3036 A memory reference with an absolute address.
3038 A memory reference using @code{BC} as a base register, with an optional offset.
3040 A memory reference using @code{AX}, @code{BC}, @code{DE}, or @code{HL} for the address, for calls.
3042 A memory reference using any 16-bit register pair for the address, for calls.
3044 A memory reference using @code{DE} as a base register, with an optional offset.
3046 A memory reference using @code{DE} as a base register, without any offset.
3048 Any memory reference to an address in the far address space.
3050 A memory reference using @code{HL} as a base register, with an optional one-byte offset.
3052 A memory reference using @code{HL} as a base register, with @code{B} or @code{C} as the index register.
3054 A memory reference using @code{HL} as a base register, without any offset.
3056 A memory reference using @code{SP} as a base register, with an optional one-byte offset.
3058 Any memory reference to an address in the near address space.
3060 The @code{AX} register.
3062 The @code{BC} register.
3064 The @code{DE} register.
3066 @code{A} through @code{L} registers.
3068 The @code{SP} register.
3070 The @code{HL} register.
3072 The 16-bit @code{R8} register.
3074 The 16-bit @code{R10} register.
3076 The registers reserved for interrupts (@code{R24} to @code{R31}).
3078 The @code{A} register.
3080 The @code{B} register.
3082 The @code{C} register.
3084 The @code{D} register.
3086 The @code{E} register.
3088 The @code{H} register.
3090 The @code{L} register.
3092 The virtual registers.
3094 The @code{PSW} register.
3096 The @code{X} register.
3100 @item RX---@file{config/rx/constraints.md}
3103 An address which does not involve register indirect addressing or
3104 pre/post increment/decrement addressing.
3110 A constant in the range @minus{}256 to 255, inclusive.
3113 A constant in the range @minus{}128 to 127, inclusive.
3116 A constant in the range @minus{}32768 to 32767, inclusive.
3119 A constant in the range @minus{}8388608 to 8388607, inclusive.
3122 A constant in the range 0 to 15, inclusive.
3127 @item SPARC---@file{config/sparc/sparc.h}
3130 Floating-point register on the SPARC-V8 architecture and
3131 lower floating-point register on the SPARC-V9 architecture.
3134 Floating-point register. It is equivalent to @samp{f} on the
3135 SPARC-V8 architecture and contains both lower and upper
3136 floating-point registers on the SPARC-V9 architecture.
3139 Floating-point condition code register.
3142 Lower floating-point register. It is only valid on the SPARC-V9
3143 architecture when the Visual Instruction Set is available.
3146 Floating-point register. It is only valid on the SPARC-V9 architecture
3147 when the Visual Instruction Set is available.
3150 64-bit global or out register for the SPARC-V8+ architecture.
3156 Signed 13-bit constant
3162 32-bit constant with the low 12 bits clear (a constant that can be
3163 loaded with the @code{sethi} instruction)
3166 A constant in the range supported by @code{movcc} instructions
3169 A constant in the range supported by @code{movrcc} instructions
3172 Same as @samp{K}, except that it verifies that bits that are not in the
3173 lower 32-bit range are all zero. Must be used instead of @samp{K} for
3174 modes wider than @code{SImode}
3183 Signed 13-bit constant, sign-extended to 32 or 64 bits
3186 Floating-point constant whose integral representation can
3187 be moved into an integer register using a single sethi
3191 Floating-point constant whose integral representation can
3192 be moved into an integer register using a single mov
3196 Floating-point constant whose integral representation can
3197 be moved into an integer register using a high/lo_sum
3198 instruction sequence
3201 Memory address aligned to an 8-byte boundary
3207 Memory address for @samp{e} constraint registers
3214 @item SPU---@file{config/spu/spu.h}
3217 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 64 bit value.
3220 An immediate for and/xor/or instructions. const_int is treated as a 64 bit value.
3223 An immediate for the @code{iohl} instruction. const_int is treated as a 64 bit value.
3226 An immediate which can be loaded with @code{fsmbi}.
3229 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is treated as a 32 bit value.
3232 An immediate for most arithmetic instructions. const_int is treated as a 32 bit value.
3235 An immediate for and/xor/or instructions. const_int is treated as a 32 bit value.
3238 An immediate for the @code{iohl} instruction. const_int is treated as a 32 bit value.
3241 A constant in the range [@minus{}64, 63] for shift/rotate instructions.
3244 An unsigned 7-bit constant for conversion/nop/channel instructions.
3247 A signed 10-bit constant for most arithmetic instructions.
3250 A signed 16 bit immediate for @code{stop}.
3253 An unsigned 16-bit constant for @code{iohl} and @code{fsmbi}.
3256 An unsigned 7-bit constant whose 3 least significant bits are 0.
3259 An unsigned 3-bit constant for 16-byte rotates and shifts
3262 Call operand, reg, for indirect calls
3265 Call operand, symbol, for relative calls.
3268 Call operand, const_int, for absolute calls.
3271 An immediate which can be loaded with the il/ila/ilh/ilhu instructions. const_int is sign extended to 128 bit.
3274 An immediate for shift and rotate instructions. const_int is treated as a 32 bit value.
3277 An immediate for and/xor/or instructions. const_int is sign extended as a 128 bit.
3280 An immediate for the @code{iohl} instruction. const_int is sign extended to 128 bit.
3284 @item S/390 and zSeries---@file{config/s390/s390.h}
3287 Address register (general purpose register except r0)
3290 Condition code register
3293 Data register (arbitrary general purpose register)
3296 Floating-point register
3299 Unsigned 8-bit constant (0--255)
3302 Unsigned 12-bit constant (0--4095)
3305 Signed 16-bit constant (@minus{}32768--32767)
3308 Value appropriate as displacement.
3311 for short displacement
3312 @item (@minus{}524288..524287)
3313 for long displacement
3317 Constant integer with a value of 0x7fffffff.
3320 Multiple letter constraint followed by 4 parameter letters.
3323 number of the part counting from most to least significant
3327 mode of the containing operand
3329 value of the other parts (F---all bits set)
3331 The constraint matches if the specified part of a constant
3332 has a value different from its other parts.
3335 Memory reference without index register and with short displacement.
3338 Memory reference with index register and short displacement.
3341 Memory reference without index register but with long displacement.
3344 Memory reference with index register and long displacement.
3347 Pointer with short displacement.
3350 Pointer with long displacement.
3353 Shift count operand.
3357 @item Score family---@file{config/score/score.h}
3360 Registers from r0 to r32.
3363 Registers from r0 to r16.
3366 r8---r11 or r22---r27 registers.
3387 cnt + lcb + scb register.
3390 cr0---cr15 register.
3402 cp1 + cp2 + cp3 registers.
3405 High 16-bit constant (32-bit constant with 16 LSBs zero).
3408 Unsigned 5 bit integer (in the range 0 to 31).
3411 Unsigned 16 bit integer (in the range 0 to 65535).
3414 Signed 16 bit integer (in the range @minus{}32768 to 32767).
3417 Unsigned 14 bit integer (in the range 0 to 16383).
3420 Signed 14 bit integer (in the range @minus{}8192 to 8191).
3426 @item Xstormy16---@file{config/stormy16/stormy16.h}
3441 Registers r0 through r7.
3444 Registers r0 and r1.
3450 Registers r8 and r9.
3453 A constant between 0 and 3 inclusive.
3456 A constant that has exactly one bit set.
3459 A constant that has exactly one bit clear.
3462 A constant between 0 and 255 inclusive.
3465 A constant between @minus{}255 and 0 inclusive.
3468 A constant between @minus{}3 and 0 inclusive.
3471 A constant between 1 and 4 inclusive.
3474 A constant between @minus{}4 and @minus{}1 inclusive.
3477 A memory reference that is a stack push.
3480 A memory reference that is a stack pop.
3483 A memory reference that refers to a constant address of known value.
3486 The register indicated by Rx (not implemented yet).
3489 A constant that is not between 2 and 15 inclusive.
3496 @item TI C6X family---@file{config/c6x/constraints.md}
3499 Register file A (A0--A31).
3502 Register file B (B0--B31).
3505 Predicate registers in register file A (A0--A2 on C64X and
3506 higher, A1 and A2 otherwise).
3509 Predicate registers in register file B (B0--B2).
3512 A call-used register in register file B (B0--B9, B16--B31).
3515 Register file A, excluding predicate registers (A3--A31,
3516 plus A0 if not C64X or higher).
3519 Register file B, excluding predicate registers (B3--B31).
3522 Integer constant in the range 0 @dots{} 15.
3525 Integer constant in the range 0 @dots{} 31.
3528 Integer constant in the range @minus{}31 @dots{} 0.
3531 Integer constant in the range @minus{}16 @dots{} 15.
3534 Integer constant that can be the operand of an ADDA or a SUBA insn.
3537 Integer constant in the range 0 @dots{} 65535.
3540 Integer constant in the range @minus{}32768 @dots{} 32767.
3543 Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
3546 Integer constant that is a valid mask for the clr instruction.
3549 Integer constant that is a valid mask for the set instruction.
3552 Memory location with A base register.
3555 Memory location with B base register.
3559 On C64x+ targets, a GP-relative small data reference.
3562 Any kind of @code{SYMBOL_REF}, for use in a call address.
3565 Any kind of immediate operand, unless it matches the S0 constraint.
3568 Memory location with B base register, but not using a long offset.
3571 A memory operand with an address that can't be used in an unaligned access.
3575 Register B14 (aka DP).
3579 @item TILE-Gx---@file{config/tilegx/constraints.md}
3592 Each of these represents a register constraint for an individual
3593 register, from r0 to r10.
3596 Signed 8-bit integer constant.
3599 Signed 16-bit integer constant.
3602 Unsigned 16-bit integer constant.
3605 Integer constant that fits in one signed byte when incremented by one
3606 (@minus{}129 @dots{} 126).
3609 Memory operand. If used together with @samp{<} or @samp{>}, the
3610 operand can have postincrement which requires printing with @samp{%In}
3611 and @samp{%in} on TILE-Gx. For example:
3614 asm ("st_add %I0,%1,%i0" : "=m<>" (*mem) : "r" (val));
3618 A bit mask suitable for the BFINS instruction.
3621 Integer constant that is a byte tiled out eight times.
3624 The integer zero constant.
3627 Integer constant that is a sign-extended byte tiled out as four shorts.
3630 Integer constant that fits in one signed byte when incremented
3631 (@minus{}129 @dots{} 126), but excluding -1.
3634 Integer constant that has all 1 bits consecutive and starting at bit 0.
3637 A 16-bit fragment of a got, tls, or pc-relative reference.
3640 Memory operand except postincrement. This is roughly the same as
3641 @samp{m} when not used together with @samp{<} or @samp{>}.
3644 An 8-element vector constant with identical elements.
3647 A 4-element vector constant with identical elements.
3650 The integer constant 0xffffffff.
3653 The integer constant 0xffffffff00000000.
3657 @item TILEPro---@file{config/tilepro/constraints.md}
3670 Each of these represents a register constraint for an individual
3671 register, from r0 to r10.
3674 Signed 8-bit integer constant.
3677 Signed 16-bit integer constant.
3680 Nonzero integer constant with low 16 bits zero.
3683 Integer constant that fits in one signed byte when incremented by one
3684 (@minus{}129 @dots{} 126).
3687 Memory operand. If used together with @samp{<} or @samp{>}, the
3688 operand can have postincrement which requires printing with @samp{%In}
3689 and @samp{%in} on TILEPro. For example:
3692 asm ("swadd %I0,%1,%i0" : "=m<>" (mem) : "r" (val));
3696 A bit mask suitable for the MM instruction.
3699 Integer constant that is a byte tiled out four times.
3702 The integer zero constant.
3705 Integer constant that is a sign-extended byte tiled out as two shorts.
3708 Integer constant that fits in one signed byte when incremented
3709 (@minus{}129 @dots{} 126), but excluding -1.
3712 A symbolic operand, or a 16-bit fragment of a got, tls, or pc-relative
3716 Memory operand except postincrement. This is roughly the same as
3717 @samp{m} when not used together with @samp{<} or @samp{>}.
3720 A 4-element vector constant with identical elements.
3723 A 2-element vector constant with identical elements.
3727 @item Xtensa---@file{config/xtensa/constraints.md}
3730 General-purpose 32-bit register
3733 One-bit boolean register
3736 MAC16 40-bit accumulator register
3739 Signed 12-bit integer constant, for use in MOVI instructions
3742 Signed 8-bit integer constant, for use in ADDI instructions
3745 Integer constant valid for BccI instructions
3748 Unsigned constant valid for BccUI instructions
3755 @node Disable Insn Alternatives
3756 @subsection Disable insn alternatives using the @code{enabled} attribute
3759 The @code{enabled} insn attribute may be used to disable certain insn
3760 alternatives for machine-specific reasons. This is useful when adding
3761 new instructions to an existing pattern which are only available for
3762 certain cpu architecture levels as specified with the @code{-march=}
3765 If an insn alternative is disabled, then it will never be used. The
3766 compiler treats the constraints for the disabled alternative as
3769 In order to make use of the @code{enabled} attribute a back end has to add
3770 in the machine description files:
3774 A definition of the @code{enabled} insn attribute. The attribute is
3775 defined as usual using the @code{define_attr} command. This
3776 definition should be based on other insn attributes and/or target flags.
3777 The @code{enabled} attribute is a numeric attribute and should evaluate to
3778 @code{(const_int 1)} for an enabled alternative and to
3779 @code{(const_int 0)} otherwise.
3781 A definition of another insn attribute used to describe for what
3782 reason an insn alternative might be available or
3783 not. E.g. @code{cpu_facility} as in the example below.
3785 An assignment for the second attribute to each insn definition
3786 combining instructions which are not all available under the same
3787 circumstances. (Note: It obviously only makes sense for definitions
3788 with more than one alternative. Otherwise the insn pattern should be
3789 disabled or enabled using the insn condition.)
3792 E.g. the following two patterns could easily be merged using the @code{enabled}
3797 (define_insn "*movdi_old"
3798 [(set (match_operand:DI 0 "register_operand" "=d")
3799 (match_operand:DI 1 "register_operand" " d"))]
3803 (define_insn "*movdi_new"
3804 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3805 (match_operand:DI 1 "register_operand" " d,d,f"))]
3818 (define_insn "*movdi_combined"
3819 [(set (match_operand:DI 0 "register_operand" "=d,f,d")
3820 (match_operand:DI 1 "register_operand" " d,d,f"))]
3826 [(set_attr "cpu_facility" "*,new,new")])
3830 with the @code{enabled} attribute defined like this:
3834 (define_attr "cpu_facility" "standard,new" (const_string "standard"))
3836 (define_attr "enabled" ""
3837 (cond [(eq_attr "cpu_facility" "standard") (const_int 1)
3838 (and (eq_attr "cpu_facility" "new")
3839 (ne (symbol_ref "TARGET_NEW") (const_int 0)))
3848 @node Define Constraints
3849 @subsection Defining Machine-Specific Constraints
3850 @cindex defining constraints
3851 @cindex constraints, defining
3853 Machine-specific constraints fall into two categories: register and
3854 non-register constraints. Within the latter category, constraints
3855 which allow subsets of all possible memory or address operands should
3856 be specially marked, to give @code{reload} more information.
3858 Machine-specific constraints can be given names of arbitrary length,
3859 but they must be entirely composed of letters, digits, underscores
3860 (@samp{_}), and angle brackets (@samp{< >}). Like C identifiers, they
3861 must begin with a letter or underscore.
3863 In order to avoid ambiguity in operand constraint strings, no
3864 constraint can have a name that begins with any other constraint's
3865 name. For example, if @code{x} is defined as a constraint name,
3866 @code{xy} may not be, and vice versa. As a consequence of this rule,
3867 no constraint may begin with one of the generic constraint letters:
3868 @samp{E F V X g i m n o p r s}.
3870 Register constraints correspond directly to register classes.
3871 @xref{Register Classes}. There is thus not much flexibility in their
3874 @deffn {MD Expression} define_register_constraint name regclass docstring
3875 All three arguments are string constants.
3876 @var{name} is the name of the constraint, as it will appear in
3877 @code{match_operand} expressions. If @var{name} is a multi-letter
3878 constraint its length shall be the same for all constraints starting
3879 with the same letter. @var{regclass} can be either the
3880 name of the corresponding register class (@pxref{Register Classes}),
3881 or a C expression which evaluates to the appropriate register class.
3882 If it is an expression, it must have no side effects, and it cannot
3883 look at the operand. The usual use of expressions is to map some
3884 register constraints to @code{NO_REGS} when the register class
3885 is not available on a given subarchitecture.
3887 @var{docstring} is a sentence documenting the meaning of the
3888 constraint. Docstrings are explained further below.
3891 Non-register constraints are more like predicates: the constraint
3892 definition gives a Boolean expression which indicates whether the
3895 @deffn {MD Expression} define_constraint name docstring exp
3896 The @var{name} and @var{docstring} arguments are the same as for
3897 @code{define_register_constraint}, but note that the docstring comes
3898 immediately after the name for these expressions. @var{exp} is an RTL
3899 expression, obeying the same rules as the RTL expressions in predicate
3900 definitions. @xref{Defining Predicates}, for details. If it
3901 evaluates true, the constraint matches; if it evaluates false, it
3902 doesn't. Constraint expressions should indicate which RTL codes they
3903 might match, just like predicate expressions.
3905 @code{match_test} C expressions have access to the
3906 following variables:
3910 The RTL object defining the operand.
3912 The machine mode of @var{op}.
3914 @samp{INTVAL (@var{op})}, if @var{op} is a @code{const_int}.
3916 @samp{CONST_DOUBLE_HIGH (@var{op})}, if @var{op} is an integer
3917 @code{const_double}.
3919 @samp{CONST_DOUBLE_LOW (@var{op})}, if @var{op} is an integer
3920 @code{const_double}.
3922 @samp{CONST_DOUBLE_REAL_VALUE (@var{op})}, if @var{op} is a floating-point
3923 @code{const_double}.
3926 The @var{*val} variables should only be used once another piece of the
3927 expression has verified that @var{op} is the appropriate kind of RTL
3931 Most non-register constraints should be defined with
3932 @code{define_constraint}. The remaining two definition expressions
3933 are only appropriate for constraints that should be handled specially
3934 by @code{reload} if they fail to match.
3936 @deffn {MD Expression} define_memory_constraint name docstring exp
3937 Use this expression for constraints that match a subset of all memory
3938 operands: that is, @code{reload} can make them match by converting the
3939 operand to the form @samp{@w{(mem (reg @var{X}))}}, where @var{X} is a
3940 base register (from the register class specified by
3941 @code{BASE_REG_CLASS}, @pxref{Register Classes}).
3943 For example, on the S/390, some instructions do not accept arbitrary
3944 memory references, but only those that do not make use of an index
3945 register. The constraint letter @samp{Q} is defined to represent a
3946 memory address of this type. If @samp{Q} is defined with
3947 @code{define_memory_constraint}, a @samp{Q} constraint can handle any
3948 memory operand, because @code{reload} knows it can simply copy the
3949 memory address into a base register if required. This is analogous to
3950 the way an @samp{o} constraint can handle any memory operand.
3952 The syntax and semantics are otherwise identical to
3953 @code{define_constraint}.
3956 @deffn {MD Expression} define_address_constraint name docstring exp
3957 Use this expression for constraints that match a subset of all address
3958 operands: that is, @code{reload} can make the constraint match by
3959 converting the operand to the form @samp{@w{(reg @var{X})}}, again
3960 with @var{X} a base register.
3962 Constraints defined with @code{define_address_constraint} can only be
3963 used with the @code{address_operand} predicate, or machine-specific
3964 predicates that work the same way. They are treated analogously to
3965 the generic @samp{p} constraint.
3967 The syntax and semantics are otherwise identical to
3968 @code{define_constraint}.
3971 For historical reasons, names beginning with the letters @samp{G H}
3972 are reserved for constraints that match only @code{const_double}s, and
3973 names beginning with the letters @samp{I J K L M N O P} are reserved
3974 for constraints that match only @code{const_int}s. This may change in
3975 the future. For the time being, constraints with these names must be
3976 written in a stylized form, so that @code{genpreds} can tell you did
3981 (define_constraint "[@var{GHIJKLMNOP}]@dots{}"
3983 (and (match_code "const_int") ; @r{@code{const_double} for G/H}
3984 @var{condition}@dots{})) ; @r{usually a @code{match_test}}
3987 @c the semicolons line up in the formatted manual
3989 It is fine to use names beginning with other letters for constraints
3990 that match @code{const_double}s or @code{const_int}s.
3992 Each docstring in a constraint definition should be one or more complete
3993 sentences, marked up in Texinfo format. @emph{They are currently unused.}
3994 In the future they will be copied into the GCC manual, in @ref{Machine
3995 Constraints}, replacing the hand-maintained tables currently found in
3996 that section. Also, in the future the compiler may use this to give
3997 more helpful diagnostics when poor choice of @code{asm} constraints
3998 causes a reload failure.
4000 If you put the pseudo-Texinfo directive @samp{@@internal} at the
4001 beginning of a docstring, then (in the future) it will appear only in
4002 the internals manual's version of the machine-specific constraint tables.
4003 Use this for constraints that should not appear in @code{asm} statements.
4005 @node C Constraint Interface
4006 @subsection Testing constraints from C
4007 @cindex testing constraints
4008 @cindex constraints, testing
4010 It is occasionally useful to test a constraint from C code rather than
4011 implicitly via the constraint string in a @code{match_operand}. The
4012 generated file @file{tm_p.h} declares a few interfaces for working
4013 with machine-specific constraints. None of these interfaces work with
4014 the generic constraints described in @ref{Simple Constraints}. This
4015 may change in the future.
4017 @strong{Warning:} @file{tm_p.h} may declare other functions that
4018 operate on constraints, besides the ones documented here. Do not use
4019 those functions from machine-dependent code. They exist to implement
4020 the old constraint interface that machine-independent components of
4021 the compiler still expect. They will change or disappear in the
4024 Some valid constraint names are not valid C identifiers, so there is a
4025 mangling scheme for referring to them from C@. Constraint names that
4026 do not contain angle brackets or underscores are left unchanged.
4027 Underscores are doubled, each @samp{<} is replaced with @samp{_l}, and
4028 each @samp{>} with @samp{_g}. Here are some examples:
4030 @c the @c's prevent double blank lines in the printed manual.
4032 @multitable {Original} {Mangled}
4033 @item @strong{Original} @tab @strong{Mangled} @c
4034 @item @code{x} @tab @code{x} @c
4035 @item @code{P42x} @tab @code{P42x} @c
4036 @item @code{P4_x} @tab @code{P4__x} @c
4037 @item @code{P4>x} @tab @code{P4_gx} @c
4038 @item @code{P4>>} @tab @code{P4_g_g} @c
4039 @item @code{P4_g>} @tab @code{P4__g_g} @c
4043 Throughout this section, the variable @var{c} is either a constraint
4044 in the abstract sense, or a constant from @code{enum constraint_num};
4045 the variable @var{m} is a mangled constraint name (usually as part of
4046 a larger identifier).
4048 @deftp Enum constraint_num
4049 For each machine-specific constraint, there is a corresponding
4050 enumeration constant: @samp{CONSTRAINT_} plus the mangled name of the
4051 constraint. Functions that take an @code{enum constraint_num} as an
4052 argument expect one of these constants.
4054 Machine-independent constraints do not have associated constants.
4055 This may change in the future.
4058 @deftypefun {inline bool} satisfies_constraint_@var{m} (rtx @var{exp})
4059 For each machine-specific, non-register constraint @var{m}, there is
4060 one of these functions; it returns @code{true} if @var{exp} satisfies the
4061 constraint. These functions are only visible if @file{rtl.h} was included
4062 before @file{tm_p.h}.
4065 @deftypefun bool constraint_satisfied_p (rtx @var{exp}, enum constraint_num @var{c})
4066 Like the @code{satisfies_constraint_@var{m}} functions, but the
4067 constraint to test is given as an argument, @var{c}. If @var{c}
4068 specifies a register constraint, this function will always return
4072 @deftypefun {enum reg_class} regclass_for_constraint (enum constraint_num @var{c})
4073 Returns the register class associated with @var{c}. If @var{c} is not
4074 a register constraint, or those registers are not available for the
4075 currently selected subtarget, returns @code{NO_REGS}.
4078 Here is an example use of @code{satisfies_constraint_@var{m}}. In
4079 peephole optimizations (@pxref{Peephole Definitions}), operand
4080 constraint strings are ignored, so if there are relevant constraints,
4081 they must be tested in the C condition. In the example, the
4082 optimization is applied if operand 2 does @emph{not} satisfy the
4083 @samp{K} constraint. (This is a simplified version of a peephole
4084 definition from the i386 machine description.)
4088 [(match_scratch:SI 3 "r")
4089 (set (match_operand:SI 0 "register_operand" "")
4090 (mult:SI (match_operand:SI 1 "memory_operand" "")
4091 (match_operand:SI 2 "immediate_operand" "")))]
4093 "!satisfies_constraint_K (operands[2])"
4095 [(set (match_dup 3) (match_dup 1))
4096 (set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))]
4101 @node Standard Names
4102 @section Standard Pattern Names For Generation
4103 @cindex standard pattern names
4104 @cindex pattern names
4105 @cindex names, pattern
4107 Here is a table of the instruction names that are meaningful in the RTL
4108 generation pass of the compiler. Giving one of these names to an
4109 instruction pattern tells the RTL generation pass that it can use the
4110 pattern to accomplish a certain task.
4113 @cindex @code{mov@var{m}} instruction pattern
4114 @item @samp{mov@var{m}}
4115 Here @var{m} stands for a two-letter machine mode name, in lowercase.
4116 This instruction pattern moves data with that machine mode from operand
4117 1 to operand 0. For example, @samp{movsi} moves full-word data.
4119 If operand 0 is a @code{subreg} with mode @var{m} of a register whose
4120 own mode is wider than @var{m}, the effect of this instruction is
4121 to store the specified value in the part of the register that corresponds
4122 to mode @var{m}. Bits outside of @var{m}, but which are within the
4123 same target word as the @code{subreg} are undefined. Bits which are
4124 outside the target word are left unchanged.
4126 This class of patterns is special in several ways. First of all, each
4127 of these names up to and including full word size @emph{must} be defined,
4128 because there is no other way to copy a datum from one place to another.
4129 If there are patterns accepting operands in larger modes,
4130 @samp{mov@var{m}} must be defined for integer modes of those sizes.
4132 Second, these patterns are not used solely in the RTL generation pass.
4133 Even the reload pass can generate move insns to copy values from stack
4134 slots into temporary registers. When it does so, one of the operands is
4135 a hard register and the other is an operand that can need to be reloaded
4139 Therefore, when given such a pair of operands, the pattern must generate
4140 RTL which needs no reloading and needs no temporary registers---no
4141 registers other than the operands. For example, if you support the
4142 pattern with a @code{define_expand}, then in such a case the
4143 @code{define_expand} mustn't call @code{force_reg} or any other such
4144 function which might generate new pseudo registers.
4146 This requirement exists even for subword modes on a RISC machine where
4147 fetching those modes from memory normally requires several insns and
4148 some temporary registers.
4150 @findex change_address
4151 During reload a memory reference with an invalid address may be passed
4152 as an operand. Such an address will be replaced with a valid address
4153 later in the reload pass. In this case, nothing may be done with the
4154 address except to use it as it stands. If it is copied, it will not be
4155 replaced with a valid address. No attempt should be made to make such
4156 an address into a valid address and no routine (such as
4157 @code{change_address}) that will do so may be called. Note that
4158 @code{general_operand} will fail when applied to such an address.
4160 @findex reload_in_progress
4161 The global variable @code{reload_in_progress} (which must be explicitly
4162 declared if required) can be used to determine whether such special
4163 handling is required.
4165 The variety of operands that have reloads depends on the rest of the
4166 machine description, but typically on a RISC machine these can only be
4167 pseudo registers that did not get hard registers, while on other
4168 machines explicit memory references will get optional reloads.
4170 If a scratch register is required to move an object to or from memory,
4171 it can be allocated using @code{gen_reg_rtx} prior to life analysis.
4173 If there are cases which need scratch registers during or after reload,
4174 you must provide an appropriate secondary_reload target hook.
4176 @findex can_create_pseudo_p
4177 The macro @code{can_create_pseudo_p} can be used to determine if it
4178 is unsafe to create new pseudo registers. If this variable is nonzero, then
4179 it is unsafe to call @code{gen_reg_rtx} to allocate a new pseudo.
4181 The constraints on a @samp{mov@var{m}} must permit moving any hard
4182 register to any other hard register provided that
4183 @code{HARD_REGNO_MODE_OK} permits mode @var{m} in both registers and
4184 @code{TARGET_REGISTER_MOVE_COST} applied to their classes returns a value
4187 It is obligatory to support floating point @samp{mov@var{m}}
4188 instructions into and out of any registers that can hold fixed point
4189 values, because unions and structures (which have modes @code{SImode} or
4190 @code{DImode}) can be in those registers and they may have floating
4193 There may also be a need to support fixed point @samp{mov@var{m}}
4194 instructions in and out of floating point registers. Unfortunately, I
4195 have forgotten why this was so, and I don't know whether it is still
4196 true. If @code{HARD_REGNO_MODE_OK} rejects fixed point values in
4197 floating point registers, then the constraints of the fixed point
4198 @samp{mov@var{m}} instructions must be designed to avoid ever trying to
4199 reload into a floating point register.
4201 @cindex @code{reload_in} instruction pattern
4202 @cindex @code{reload_out} instruction pattern
4203 @item @samp{reload_in@var{m}}
4204 @itemx @samp{reload_out@var{m}}
4205 These named patterns have been obsoleted by the target hook
4206 @code{secondary_reload}.
4208 Like @samp{mov@var{m}}, but used when a scratch register is required to
4209 move between operand 0 and operand 1. Operand 2 describes the scratch
4210 register. See the discussion of the @code{SECONDARY_RELOAD_CLASS}
4211 macro in @pxref{Register Classes}.
4213 There are special restrictions on the form of the @code{match_operand}s
4214 used in these patterns. First, only the predicate for the reload
4215 operand is examined, i.e., @code{reload_in} examines operand 1, but not
4216 the predicates for operand 0 or 2. Second, there may be only one
4217 alternative in the constraints. Third, only a single register class
4218 letter may be used for the constraint; subsequent constraint letters
4219 are ignored. As a special exception, an empty constraint string
4220 matches the @code{ALL_REGS} register class. This may relieve ports
4221 of the burden of defining an @code{ALL_REGS} constraint letter just
4224 @cindex @code{movstrict@var{m}} instruction pattern
4225 @item @samp{movstrict@var{m}}
4226 Like @samp{mov@var{m}} except that if operand 0 is a @code{subreg}
4227 with mode @var{m} of a register whose natural mode is wider,
4228 the @samp{movstrict@var{m}} instruction is guaranteed not to alter
4229 any of the register except the part which belongs to mode @var{m}.
4231 @cindex @code{movmisalign@var{m}} instruction pattern
4232 @item @samp{movmisalign@var{m}}
4233 This variant of a move pattern is designed to load or store a value
4234 from a memory address that is not naturally aligned for its mode.
4235 For a store, the memory will be in operand 0; for a load, the memory
4236 will be in operand 1. The other operand is guaranteed not to be a
4237 memory, so that it's easy to tell whether this is a load or store.
4239 This pattern is used by the autovectorizer, and when expanding a
4240 @code{MISALIGNED_INDIRECT_REF} expression.
4242 @cindex @code{load_multiple} instruction pattern
4243 @item @samp{load_multiple}
4244 Load several consecutive memory locations into consecutive registers.
4245 Operand 0 is the first of the consecutive registers, operand 1
4246 is the first memory location, and operand 2 is a constant: the
4247 number of consecutive registers.
4249 Define this only if the target machine really has such an instruction;
4250 do not define this if the most efficient way of loading consecutive
4251 registers from memory is to do them one at a time.
4253 On some machines, there are restrictions as to which consecutive
4254 registers can be stored into memory, such as particular starting or
4255 ending register numbers or only a range of valid counts. For those
4256 machines, use a @code{define_expand} (@pxref{Expander Definitions})
4257 and make the pattern fail if the restrictions are not met.
4259 Write the generated insn as a @code{parallel} with elements being a
4260 @code{set} of one register from the appropriate memory location (you may
4261 also need @code{use} or @code{clobber} elements). Use a
4262 @code{match_parallel} (@pxref{RTL Template}) to recognize the insn. See
4263 @file{rs6000.md} for examples of the use of this insn pattern.
4265 @cindex @samp{store_multiple} instruction pattern
4266 @item @samp{store_multiple}
4267 Similar to @samp{load_multiple}, but store several consecutive registers
4268 into consecutive memory locations. Operand 0 is the first of the
4269 consecutive memory locations, operand 1 is the first register, and
4270 operand 2 is a constant: the number of consecutive registers.
4272 @cindex @code{vec_load_lanes@var{m}@var{n}} instruction pattern
4273 @item @samp{vec_load_lanes@var{m}@var{n}}
4274 Perform an interleaved load of several vectors from memory operand 1
4275 into register operand 0. Both operands have mode @var{m}. The register
4276 operand is viewed as holding consecutive vectors of mode @var{n},
4277 while the memory operand is a flat array that contains the same number
4278 of elements. The operation is equivalent to:
4281 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4282 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4283 for (i = 0; i < c; i++)
4284 operand0[i][j] = operand1[j * c + i];
4287 For example, @samp{vec_load_lanestiv4hi} loads 8 16-bit values
4288 from memory into a register of mode @samp{TI}@. The register
4289 contains two consecutive vectors of mode @samp{V4HI}@.
4291 This pattern can only be used if:
4293 TARGET_ARRAY_MODE_SUPPORTED_P (@var{n}, @var{c})
4295 is true. GCC assumes that, if a target supports this kind of
4296 instruction for some mode @var{n}, it also supports unaligned
4297 loads for vectors of mode @var{n}.
4299 @cindex @code{vec_store_lanes@var{m}@var{n}} instruction pattern
4300 @item @samp{vec_store_lanes@var{m}@var{n}}
4301 Equivalent to @samp{vec_load_lanes@var{m}@var{n}}, with the memory
4302 and register operands reversed. That is, the instruction is
4306 int c = GET_MODE_SIZE (@var{m}) / GET_MODE_SIZE (@var{n});
4307 for (j = 0; j < GET_MODE_NUNITS (@var{n}); j++)
4308 for (i = 0; i < c; i++)
4309 operand0[j * c + i] = operand1[i][j];
4312 for a memory operand 0 and register operand 1.
4314 @cindex @code{vec_set@var{m}} instruction pattern
4315 @item @samp{vec_set@var{m}}
4316 Set given field in the vector value. Operand 0 is the vector to modify,
4317 operand 1 is new value of field and operand 2 specify the field index.
4319 @cindex @code{vec_extract@var{m}} instruction pattern
4320 @item @samp{vec_extract@var{m}}
4321 Extract given field from the vector value. Operand 1 is the vector, operand 2
4322 specify field index and operand 0 place to store value into.
4324 @cindex @code{vec_init@var{m}} instruction pattern
4325 @item @samp{vec_init@var{m}}
4326 Initialize the vector to given values. Operand 0 is the vector to initialize
4327 and operand 1 is parallel containing values for individual fields.
4329 @cindex @code{vcond@var{m}@var{n}} instruction pattern
4330 @item @samp{vcond@var{m}@var{n}}
4331 Output a conditional vector move. Operand 0 is the destination to
4332 receive a combination of operand 1 and operand 2, which are of mode @var{m},
4333 dependent on the outcome of the predicate in operand 3 which is a
4334 vector comparison with operands of mode @var{n} in operands 4 and 5. The
4335 modes @var{m} and @var{n} should have the same size. Operand 0
4336 will be set to the value @var{op1} & @var{msk} | @var{op2} & ~@var{msk}
4337 where @var{msk} is computed by element-wise evaluation of the vector
4338 comparison with a truth value of all-ones and a false value of all-zeros.
4340 @cindex @code{vec_perm@var{m}} instruction pattern
4341 @item @samp{vec_perm@var{m}}
4342 Output a (variable) vector permutation. Operand 0 is the destination
4343 to receive elements from operand 1 and operand 2, which are of mode
4344 @var{m}. Operand 3 is the @dfn{selector}. It is an integral mode
4345 vector of the same width and number of elements as mode @var{m}.
4347 The input elements are numbered from 0 in operand 1 through
4348 @math{2*@var{N}-1} in operand 2. The elements of the selector must
4349 be computed modulo @math{2*@var{N}}. Note that if
4350 @code{rtx_equal_p(operand1, operand2)}, this can be implemented
4351 with just operand 1 and selector elements modulo @var{N}.
4353 In order to make things easy for a number of targets, if there is no
4354 @samp{vec_perm} pattern for mode @var{m}, but there is for mode @var{q}
4355 where @var{q} is a vector of @code{QImode} of the same width as @var{m},
4356 the middle-end will lower the mode @var{m} @code{VEC_PERM_EXPR} to
4359 @cindex @code{vec_perm_const@var{m}} instruction pattern
4360 @item @samp{vec_perm_const@var{m}}
4361 Like @samp{vec_perm} except that the permutation is a compile-time
4362 constant. That is, operand 3, the @dfn{selector}, is a @code{CONST_VECTOR}.
4364 Some targets cannot perform a permutation with a variable selector,
4365 but can efficiently perform a constant permutation. Further, the
4366 target hook @code{vec_perm_ok} is queried to determine if the
4367 specific constant permutation is available efficiently; the named
4368 pattern is never expanded without @code{vec_perm_ok} returning true.
4370 There is no need for a target to supply both @samp{vec_perm@var{m}}
4371 and @samp{vec_perm_const@var{m}} if the former can trivially implement
4372 the operation with, say, the vector constant loaded into a register.
4374 @cindex @code{push@var{m}1} instruction pattern
4375 @item @samp{push@var{m}1}
4376 Output a push instruction. Operand 0 is value to push. Used only when
4377 @code{PUSH_ROUNDING} is defined. For historical reason, this pattern may be
4378 missing and in such case an @code{mov} expander is used instead, with a
4379 @code{MEM} expression forming the push operation. The @code{mov} expander
4380 method is deprecated.
4382 @cindex @code{add@var{m}3} instruction pattern
4383 @item @samp{add@var{m}3}
4384 Add operand 2 and operand 1, storing the result in operand 0. All operands
4385 must have mode @var{m}. This can be used even on two-address machines, by
4386 means of constraints requiring operands 1 and 0 to be the same location.
4388 @cindex @code{ssadd@var{m}3} instruction pattern
4389 @cindex @code{usadd@var{m}3} instruction pattern
4390 @cindex @code{sub@var{m}3} instruction pattern
4391 @cindex @code{sssub@var{m}3} instruction pattern
4392 @cindex @code{ussub@var{m}3} instruction pattern
4393 @cindex @code{mul@var{m}3} instruction pattern
4394 @cindex @code{ssmul@var{m}3} instruction pattern
4395 @cindex @code{usmul@var{m}3} instruction pattern
4396 @cindex @code{div@var{m}3} instruction pattern
4397 @cindex @code{ssdiv@var{m}3} instruction pattern
4398 @cindex @code{udiv@var{m}3} instruction pattern
4399 @cindex @code{usdiv@var{m}3} instruction pattern
4400 @cindex @code{mod@var{m}3} instruction pattern
4401 @cindex @code{umod@var{m}3} instruction pattern
4402 @cindex @code{umin@var{m}3} instruction pattern
4403 @cindex @code{umax@var{m}3} instruction pattern
4404 @cindex @code{and@var{m}3} instruction pattern
4405 @cindex @code{ior@var{m}3} instruction pattern
4406 @cindex @code{xor@var{m}3} instruction pattern
4407 @item @samp{ssadd@var{m}3}, @samp{usadd@var{m}3}
4408 @item @samp{sub@var{m}3}, @samp{sssub@var{m}3}, @samp{ussub@var{m}3}
4409 @item @samp{mul@var{m}3}, @samp{ssmul@var{m}3}, @samp{usmul@var{m}3}
4410 @itemx @samp{div@var{m}3}, @samp{ssdiv@var{m}3}
4411 @itemx @samp{udiv@var{m}3}, @samp{usdiv@var{m}3}
4412 @itemx @samp{mod@var{m}3}, @samp{umod@var{m}3}
4413 @itemx @samp{umin@var{m}3}, @samp{umax@var{m}3}
4414 @itemx @samp{and@var{m}3}, @samp{ior@var{m}3}, @samp{xor@var{m}3}
4415 Similar, for other arithmetic operations.
4417 @cindex @code{fma@var{m}4} instruction pattern
4418 @item @samp{fma@var{m}4}
4419 Multiply operand 2 and operand 1, then add operand 3, storing the
4420 result in operand 0. All operands must have mode @var{m}. This
4421 pattern is used to implement the @code{fma}, @code{fmaf}, and
4422 @code{fmal} builtin functions from the ISO C99 standard. The
4423 @code{fma} operation may produce different results than doing the
4424 multiply followed by the add if the machine does not perform a
4425 rounding step between the operations.
4427 @cindex @code{fms@var{m}4} instruction pattern
4428 @item @samp{fms@var{m}4}
4429 Like @code{fma@var{m}4}, except operand 3 subtracted from the
4430 product instead of added to the product. This is represented
4434 (fma:@var{m} @var{op1} @var{op2} (neg:@var{m} @var{op3}))
4437 @cindex @code{fnma@var{m}4} instruction pattern
4438 @item @samp{fnma@var{m}4}
4439 Like @code{fma@var{m}4} except that the intermediate product
4440 is negated before being added to operand 3. This is represented
4444 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} @var{op3})
4447 @cindex @code{fnms@var{m}4} instruction pattern
4448 @item @samp{fnms@var{m}4}
4449 Like @code{fms@var{m}4} except that the intermediate product
4450 is negated before subtracting operand 3. This is represented
4454 (fma:@var{m} (neg:@var{m} @var{op1}) @var{op2} (neg:@var{m} @var{op3}))
4457 @cindex @code{min@var{m}3} instruction pattern
4458 @cindex @code{max@var{m}3} instruction pattern
4459 @item @samp{smin@var{m}3}, @samp{smax@var{m}3}
4460 Signed minimum and maximum operations. When used with floating point,
4461 if both operands are zeros, or if either operand is @code{NaN}, then
4462 it is unspecified which of the two operands is returned as the result.
4464 @cindex @code{reduc_smin_@var{m}} instruction pattern
4465 @cindex @code{reduc_smax_@var{m}} instruction pattern
4466 @item @samp{reduc_smin_@var{m}}, @samp{reduc_smax_@var{m}}
4467 Find the signed minimum/maximum of the elements of a vector. The vector is
4468 operand 1, and the scalar result is stored in the least significant bits of
4469 operand 0 (also a vector). The output and input vector should have the same
4472 @cindex @code{reduc_umin_@var{m}} instruction pattern
4473 @cindex @code{reduc_umax_@var{m}} instruction pattern
4474 @item @samp{reduc_umin_@var{m}}, @samp{reduc_umax_@var{m}}
4475 Find the unsigned minimum/maximum of the elements of a vector. The vector is
4476 operand 1, and the scalar result is stored in the least significant bits of
4477 operand 0 (also a vector). The output and input vector should have the same
4480 @cindex @code{reduc_splus_@var{m}} instruction pattern
4481 @item @samp{reduc_splus_@var{m}}
4482 Compute the sum of the signed elements of a vector. The vector is operand 1,
4483 and the scalar result is stored in the least significant bits of operand 0
4484 (also a vector). The output and input vector should have the same modes.
4486 @cindex @code{reduc_uplus_@var{m}} instruction pattern
4487 @item @samp{reduc_uplus_@var{m}}
4488 Compute the sum of the unsigned elements of a vector. The vector is operand 1,
4489 and the scalar result is stored in the least significant bits of operand 0
4490 (also a vector). The output and input vector should have the same modes.
4492 @cindex @code{sdot_prod@var{m}} instruction pattern
4493 @item @samp{sdot_prod@var{m}}
4494 @cindex @code{udot_prod@var{m}} instruction pattern
4495 @item @samp{udot_prod@var{m}}
4496 Compute the sum of the products of two signed/unsigned elements.
4497 Operand 1 and operand 2 are of the same mode. Their product, which is of a
4498 wider mode, is computed and added to operand 3. Operand 3 is of a mode equal or
4499 wider than the mode of the product. The result is placed in operand 0, which
4500 is of the same mode as operand 3.
4502 @cindex @code{ssum_widen@var{m3}} instruction pattern
4503 @item @samp{ssum_widen@var{m3}}
4504 @cindex @code{usum_widen@var{m3}} instruction pattern
4505 @item @samp{usum_widen@var{m3}}
4506 Operands 0 and 2 are of the same mode, which is wider than the mode of
4507 operand 1. Add operand 1 to operand 2 and place the widened result in
4508 operand 0. (This is used express accumulation of elements into an accumulator
4511 @cindex @code{vec_shl_@var{m}} instruction pattern
4512 @cindex @code{vec_shr_@var{m}} instruction pattern
4513 @item @samp{vec_shl_@var{m}}, @samp{vec_shr_@var{m}}
4514 Whole vector left/right shift in bits.
4515 Operand 1 is a vector to be shifted.
4516 Operand 2 is an integer shift amount in bits.
4517 Operand 0 is where the resulting shifted vector is stored.
4518 The output and input vectors should have the same modes.
4520 @cindex @code{vec_pack_trunc_@var{m}} instruction pattern
4521 @item @samp{vec_pack_trunc_@var{m}}
4522 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4523 are vectors of the same mode having N integral or floating point elements
4524 of size S@. Operand 0 is the resulting vector in which 2*N elements of
4525 size N/2 are concatenated after narrowing them down using truncation.
4527 @cindex @code{vec_pack_ssat_@var{m}} instruction pattern
4528 @cindex @code{vec_pack_usat_@var{m}} instruction pattern
4529 @item @samp{vec_pack_ssat_@var{m}}, @samp{vec_pack_usat_@var{m}}
4530 Narrow (demote) and merge the elements of two vectors. Operands 1 and 2
4531 are vectors of the same mode having N integral elements of size S.
4532 Operand 0 is the resulting vector in which the elements of the two input
4533 vectors are concatenated after narrowing them down using signed/unsigned
4534 saturating arithmetic.
4536 @cindex @code{vec_pack_sfix_trunc_@var{m}} instruction pattern
4537 @cindex @code{vec_pack_ufix_trunc_@var{m}} instruction pattern
4538 @item @samp{vec_pack_sfix_trunc_@var{m}}, @samp{vec_pack_ufix_trunc_@var{m}}
4539 Narrow, convert to signed/unsigned integral type and merge the elements
4540 of two vectors. Operands 1 and 2 are vectors of the same mode having N
4541 floating point elements of size S@. Operand 0 is the resulting vector
4542 in which 2*N elements of size N/2 are concatenated.
4544 @cindex @code{vec_unpacks_hi_@var{m}} instruction pattern
4545 @cindex @code{vec_unpacks_lo_@var{m}} instruction pattern
4546 @item @samp{vec_unpacks_hi_@var{m}}, @samp{vec_unpacks_lo_@var{m}}
4547 Extract and widen (promote) the high/low part of a vector of signed
4548 integral or floating point elements. The input vector (operand 1) has N
4549 elements of size S@. Widen (promote) the high/low elements of the vector
4550 using signed or floating point extension and place the resulting N/2
4551 values of size 2*S in the output vector (operand 0).
4553 @cindex @code{vec_unpacku_hi_@var{m}} instruction pattern
4554 @cindex @code{vec_unpacku_lo_@var{m}} instruction pattern
4555 @item @samp{vec_unpacku_hi_@var{m}}, @samp{vec_unpacku_lo_@var{m}}
4556 Extract and widen (promote) the high/low part of a vector of unsigned
4557 integral elements. The input vector (operand 1) has N elements of size S.
4558 Widen (promote) the high/low elements of the vector using zero extension and
4559 place the resulting N/2 values of size 2*S in the output vector (operand 0).
4561 @cindex @code{vec_unpacks_float_hi_@var{m}} instruction pattern
4562 @cindex @code{vec_unpacks_float_lo_@var{m}} instruction pattern
4563 @cindex @code{vec_unpacku_float_hi_@var{m}} instruction pattern
4564 @cindex @code{vec_unpacku_float_lo_@var{m}} instruction pattern
4565 @item @samp{vec_unpacks_float_hi_@var{m}}, @samp{vec_unpacks_float_lo_@var{m}}
4566 @itemx @samp{vec_unpacku_float_hi_@var{m}}, @samp{vec_unpacku_float_lo_@var{m}}
4567 Extract, convert to floating point type and widen the high/low part of a
4568 vector of signed/unsigned integral elements. The input vector (operand 1)
4569 has N elements of size S@. Convert the high/low elements of the vector using
4570 floating point conversion and place the resulting N/2 values of size 2*S in
4571 the output vector (operand 0).
4573 @cindex @code{vec_widen_umult_hi_@var{m}} instruction pattern
4574 @cindex @code{vec_widen_umult_lo__@var{m}} instruction pattern
4575 @cindex @code{vec_widen_smult_hi_@var{m}} instruction pattern
4576 @cindex @code{vec_widen_smult_lo_@var{m}} instruction pattern
4577 @item @samp{vec_widen_umult_hi_@var{m}}, @samp{vec_widen_umult_lo_@var{m}}
4578 @itemx @samp{vec_widen_smult_hi_@var{m}}, @samp{vec_widen_smult_lo_@var{m}}
4579 Signed/Unsigned widening multiplication. The two inputs (operands 1 and 2)
4580 are vectors with N signed/unsigned elements of size S@. Multiply the high/low
4581 elements of the two vectors, and put the N/2 products of size 2*S in the
4582 output vector (operand 0).
4584 @cindex @code{vec_widen_ushiftl_hi_@var{m}} instruction pattern
4585 @cindex @code{vec_widen_ushiftl_lo_@var{m}} instruction pattern
4586 @cindex @code{vec_widen_sshiftl_hi_@var{m}} instruction pattern
4587 @cindex @code{vec_widen_sshiftl_lo_@var{m}} instruction pattern
4588 @item @samp{vec_widen_ushiftl_hi_@var{m}}, @samp{vec_widen_ushiftl_lo_@var{m}}
4589 @itemx @samp{vec_widen_sshiftl_hi_@var{m}}, @samp{vec_widen_sshiftl_lo_@var{m}}
4590 Signed/Unsigned widening shift left. The first input (operand 1) is a vector
4591 with N signed/unsigned elements of size S@. Operand 2 is a constant. Shift
4592 the high/low elements of operand 1, and put the N/2 results of size 2*S in the
4593 output vector (operand 0).
4595 @cindex @code{mulhisi3} instruction pattern
4596 @item @samp{mulhisi3}
4597 Multiply operands 1 and 2, which have mode @code{HImode}, and store
4598 a @code{SImode} product in operand 0.
4600 @cindex @code{mulqihi3} instruction pattern
4601 @cindex @code{mulsidi3} instruction pattern
4602 @item @samp{mulqihi3}, @samp{mulsidi3}
4603 Similar widening-multiplication instructions of other widths.
4605 @cindex @code{umulqihi3} instruction pattern
4606 @cindex @code{umulhisi3} instruction pattern
4607 @cindex @code{umulsidi3} instruction pattern
4608 @item @samp{umulqihi3}, @samp{umulhisi3}, @samp{umulsidi3}
4609 Similar widening-multiplication instructions that do unsigned
4612 @cindex @code{usmulqihi3} instruction pattern
4613 @cindex @code{usmulhisi3} instruction pattern
4614 @cindex @code{usmulsidi3} instruction pattern
4615 @item @samp{usmulqihi3}, @samp{usmulhisi3}, @samp{usmulsidi3}
4616 Similar widening-multiplication instructions that interpret the first
4617 operand as unsigned and the second operand as signed, then do a signed
4620 @cindex @code{smul@var{m}3_highpart} instruction pattern
4621 @item @samp{smul@var{m}3_highpart}
4622 Perform a signed multiplication of operands 1 and 2, which have mode
4623 @var{m}, and store the most significant half of the product in operand 0.
4624 The least significant half of the product is discarded.
4626 @cindex @code{umul@var{m}3_highpart} instruction pattern
4627 @item @samp{umul@var{m}3_highpart}
4628 Similar, but the multiplication is unsigned.
4630 @cindex @code{madd@var{m}@var{n}4} instruction pattern
4631 @item @samp{madd@var{m}@var{n}4}
4632 Multiply operands 1 and 2, sign-extend them to mode @var{n}, add
4633 operand 3, and store the result in operand 0. Operands 1 and 2
4634 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4635 Both modes must be integer or fixed-point modes and @var{n} must be twice
4636 the size of @var{m}.
4638 In other words, @code{madd@var{m}@var{n}4} is like
4639 @code{mul@var{m}@var{n}3} except that it also adds operand 3.
4641 These instructions are not allowed to @code{FAIL}.
4643 @cindex @code{umadd@var{m}@var{n}4} instruction pattern
4644 @item @samp{umadd@var{m}@var{n}4}
4645 Like @code{madd@var{m}@var{n}4}, but zero-extend the multiplication
4646 operands instead of sign-extending them.
4648 @cindex @code{ssmadd@var{m}@var{n}4} instruction pattern
4649 @item @samp{ssmadd@var{m}@var{n}4}
4650 Like @code{madd@var{m}@var{n}4}, but all involved operations must be
4653 @cindex @code{usmadd@var{m}@var{n}4} instruction pattern
4654 @item @samp{usmadd@var{m}@var{n}4}
4655 Like @code{umadd@var{m}@var{n}4}, but all involved operations must be
4656 unsigned-saturating.
4658 @cindex @code{msub@var{m}@var{n}4} instruction pattern
4659 @item @samp{msub@var{m}@var{n}4}
4660 Multiply operands 1 and 2, sign-extend them to mode @var{n}, subtract the
4661 result from operand 3, and store the result in operand 0. Operands 1 and 2
4662 have mode @var{m} and operands 0 and 3 have mode @var{n}.
4663 Both modes must be integer or fixed-point modes and @var{n} must be twice
4664 the size of @var{m}.
4666 In other words, @code{msub@var{m}@var{n}4} is like
4667 @code{mul@var{m}@var{n}3} except that it also subtracts the result
4670 These instructions are not allowed to @code{FAIL}.
4672 @cindex @code{umsub@var{m}@var{n}4} instruction pattern
4673 @item @samp{umsub@var{m}@var{n}4}
4674 Like @code{msub@var{m}@var{n}4}, but zero-extend the multiplication
4675 operands instead of sign-extending them.
4677 @cindex @code{ssmsub@var{m}@var{n}4} instruction pattern
4678 @item @samp{ssmsub@var{m}@var{n}4}
4679 Like @code{msub@var{m}@var{n}4}, but all involved operations must be
4682 @cindex @code{usmsub@var{m}@var{n}4} instruction pattern
4683 @item @samp{usmsub@var{m}@var{n}4}
4684 Like @code{umsub@var{m}@var{n}4}, but all involved operations must be
4685 unsigned-saturating.
4687 @cindex @code{divmod@var{m}4} instruction pattern
4688 @item @samp{divmod@var{m}4}
4689 Signed division that produces both a quotient and a remainder.
4690 Operand 1 is divided by operand 2 to produce a quotient stored
4691 in operand 0 and a remainder stored in operand 3.
4693 For machines with an instruction that produces both a quotient and a
4694 remainder, provide a pattern for @samp{divmod@var{m}4} but do not
4695 provide patterns for @samp{div@var{m}3} and @samp{mod@var{m}3}. This
4696 allows optimization in the relatively common case when both the quotient
4697 and remainder are computed.
4699 If an instruction that just produces a quotient or just a remainder
4700 exists and is more efficient than the instruction that produces both,
4701 write the output routine of @samp{divmod@var{m}4} to call
4702 @code{find_reg_note} and look for a @code{REG_UNUSED} note on the
4703 quotient or remainder and generate the appropriate instruction.
4705 @cindex @code{udivmod@var{m}4} instruction pattern
4706 @item @samp{udivmod@var{m}4}
4707 Similar, but does unsigned division.
4709 @anchor{shift patterns}
4710 @cindex @code{ashl@var{m}3} instruction pattern
4711 @cindex @code{ssashl@var{m}3} instruction pattern
4712 @cindex @code{usashl@var{m}3} instruction pattern
4713 @item @samp{ashl@var{m}3}, @samp{ssashl@var{m}3}, @samp{usashl@var{m}3}
4714 Arithmetic-shift operand 1 left by a number of bits specified by operand
4715 2, and store the result in operand 0. Here @var{m} is the mode of
4716 operand 0 and operand 1; operand 2's mode is specified by the
4717 instruction pattern, and the compiler will convert the operand to that
4718 mode before generating the instruction. The meaning of out-of-range shift
4719 counts can optionally be specified by @code{TARGET_SHIFT_TRUNCATION_MASK}.
4720 @xref{TARGET_SHIFT_TRUNCATION_MASK}. Operand 2 is always a scalar type.
4722 @cindex @code{ashr@var{m}3} instruction pattern
4723 @cindex @code{lshr@var{m}3} instruction pattern
4724 @cindex @code{rotl@var{m}3} instruction pattern
4725 @cindex @code{rotr@var{m}3} instruction pattern
4726 @item @samp{ashr@var{m}3}, @samp{lshr@var{m}3}, @samp{rotl@var{m}3}, @samp{rotr@var{m}3}
4727 Other shift and rotate instructions, analogous to the
4728 @code{ashl@var{m}3} instructions. Operand 2 is always a scalar type.
4730 @cindex @code{vashl@var{m}3} instruction pattern
4731 @cindex @code{vashr@var{m}3} instruction pattern
4732 @cindex @code{vlshr@var{m}3} instruction pattern
4733 @cindex @code{vrotl@var{m}3} instruction pattern
4734 @cindex @code{vrotr@var{m}3} instruction pattern
4735 @item @samp{vashl@var{m}3}, @samp{vashr@var{m}3}, @samp{vlshr@var{m}3}, @samp{vrotl@var{m}3}, @samp{vrotr@var{m}3}
4736 Vector shift and rotate instructions that take vectors as operand 2
4737 instead of a scalar type.
4739 @cindex @code{neg@var{m}2} instruction pattern
4740 @cindex @code{ssneg@var{m}2} instruction pattern
4741 @cindex @code{usneg@var{m}2} instruction pattern
4742 @item @samp{neg@var{m}2}, @samp{ssneg@var{m}2}, @samp{usneg@var{m}2}
4743 Negate operand 1 and store the result in operand 0.
4745 @cindex @code{abs@var{m}2} instruction pattern
4746 @item @samp{abs@var{m}2}
4747 Store the absolute value of operand 1 into operand 0.
4749 @cindex @code{sqrt@var{m}2} instruction pattern
4750 @item @samp{sqrt@var{m}2}
4751 Store the square root of operand 1 into operand 0.
4753 The @code{sqrt} built-in function of C always uses the mode which
4754 corresponds to the C data type @code{double} and the @code{sqrtf}
4755 built-in function uses the mode which corresponds to the C data
4758 @cindex @code{fmod@var{m}3} instruction pattern
4759 @item @samp{fmod@var{m}3}
4760 Store the remainder of dividing operand 1 by operand 2 into
4761 operand 0, rounded towards zero to an integer.
4763 The @code{fmod} built-in function of C always uses the mode which
4764 corresponds to the C data type @code{double} and the @code{fmodf}
4765 built-in function uses the mode which corresponds to the C data
4768 @cindex @code{remainder@var{m}3} instruction pattern
4769 @item @samp{remainder@var{m}3}
4770 Store the remainder of dividing operand 1 by operand 2 into
4771 operand 0, rounded to the nearest integer.
4773 The @code{remainder} built-in function of C always uses the mode
4774 which corresponds to the C data type @code{double} and the
4775 @code{remainderf} built-in function uses the mode which corresponds
4776 to the C data type @code{float}.
4778 @cindex @code{cos@var{m}2} instruction pattern
4779 @item @samp{cos@var{m}2}
4780 Store the cosine of operand 1 into operand 0.
4782 The @code{cos} built-in function of C always uses the mode which
4783 corresponds to the C data type @code{double} and the @code{cosf}
4784 built-in function uses the mode which corresponds to the C data
4787 @cindex @code{sin@var{m}2} instruction pattern
4788 @item @samp{sin@var{m}2}
4789 Store the sine of operand 1 into operand 0.
4791 The @code{sin} built-in function of C always uses the mode which
4792 corresponds to the C data type @code{double} and the @code{sinf}
4793 built-in function uses the mode which corresponds to the C data
4796 @cindex @code{exp@var{m}2} instruction pattern
4797 @item @samp{exp@var{m}2}
4798 Store the exponential of operand 1 into operand 0.
4800 The @code{exp} built-in function of C always uses the mode which
4801 corresponds to the C data type @code{double} and the @code{expf}
4802 built-in function uses the mode which corresponds to the C data
4805 @cindex @code{log@var{m}2} instruction pattern
4806 @item @samp{log@var{m}2}
4807 Store the natural logarithm of operand 1 into operand 0.
4809 The @code{log} built-in function of C always uses the mode which
4810 corresponds to the C data type @code{double} and the @code{logf}
4811 built-in function uses the mode which corresponds to the C data
4814 @cindex @code{pow@var{m}3} instruction pattern
4815 @item @samp{pow@var{m}3}
4816 Store the value of operand 1 raised to the exponent operand 2
4819 The @code{pow} built-in function of C always uses the mode which
4820 corresponds to the C data type @code{double} and the @code{powf}
4821 built-in function uses the mode which corresponds to the C data
4824 @cindex @code{atan2@var{m}3} instruction pattern
4825 @item @samp{atan2@var{m}3}
4826 Store the arc tangent (inverse tangent) of operand 1 divided by
4827 operand 2 into operand 0, using the signs of both arguments to
4828 determine the quadrant of the result.
4830 The @code{atan2} built-in function of C always uses the mode which
4831 corresponds to the C data type @code{double} and the @code{atan2f}
4832 built-in function uses the mode which corresponds to the C data
4835 @cindex @code{floor@var{m}2} instruction pattern
4836 @item @samp{floor@var{m}2}
4837 Store the largest integral value not greater than argument.
4839 The @code{floor} built-in function of C always uses the mode which
4840 corresponds to the C data type @code{double} and the @code{floorf}
4841 built-in function uses the mode which corresponds to the C data
4844 @cindex @code{btrunc@var{m}2} instruction pattern
4845 @item @samp{btrunc@var{m}2}
4846 Store the argument rounded to integer towards zero.
4848 The @code{trunc} built-in function of C always uses the mode which
4849 corresponds to the C data type @code{double} and the @code{truncf}
4850 built-in function uses the mode which corresponds to the C data
4853 @cindex @code{round@var{m}2} instruction pattern
4854 @item @samp{round@var{m}2}
4855 Store the argument rounded to integer away from zero.
4857 The @code{round} built-in function of C always uses the mode which
4858 corresponds to the C data type @code{double} and the @code{roundf}
4859 built-in function uses the mode which corresponds to the C data
4862 @cindex @code{ceil@var{m}2} instruction pattern
4863 @item @samp{ceil@var{m}2}
4864 Store the argument rounded to integer away from zero.
4866 The @code{ceil} built-in function of C always uses the mode which
4867 corresponds to the C data type @code{double} and the @code{ceilf}
4868 built-in function uses the mode which corresponds to the C data
4871 @cindex @code{nearbyint@var{m}2} instruction pattern
4872 @item @samp{nearbyint@var{m}2}
4873 Store the argument rounded according to the default rounding mode
4875 The @code{nearbyint} built-in function of C always uses the mode which
4876 corresponds to the C data type @code{double} and the @code{nearbyintf}
4877 built-in function uses the mode which corresponds to the C data
4880 @cindex @code{rint@var{m}2} instruction pattern
4881 @item @samp{rint@var{m}2}
4882 Store the argument rounded according to the default rounding mode and
4883 raise the inexact exception when the result differs in value from
4886 The @code{rint} built-in function of C always uses the mode which
4887 corresponds to the C data type @code{double} and the @code{rintf}
4888 built-in function uses the mode which corresponds to the C data
4891 @cindex @code{lrint@var{m}@var{n}2}
4892 @item @samp{lrint@var{m}@var{n}2}
4893 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4894 point mode @var{n} as a signed number according to the current
4895 rounding mode and store in operand 0 (which has mode @var{n}).
4897 @cindex @code{lround@var{m}@var{n}2}
4898 @item @samp{lround@var{m}@var{n}2}
4899 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4900 point mode @var{n} as a signed number rounding to nearest and away
4901 from zero and store in operand 0 (which has mode @var{n}).
4903 @cindex @code{lfloor@var{m}@var{n}2}
4904 @item @samp{lfloor@var{m}@var{n}2}
4905 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4906 point mode @var{n} as a signed number rounding down and store in
4907 operand 0 (which has mode @var{n}).
4909 @cindex @code{lceil@var{m}@var{n}2}
4910 @item @samp{lceil@var{m}@var{n}2}
4911 Convert operand 1 (valid for floating point mode @var{m}) to fixed
4912 point mode @var{n} as a signed number rounding up and store in
4913 operand 0 (which has mode @var{n}).
4915 @cindex @code{copysign@var{m}3} instruction pattern
4916 @item @samp{copysign@var{m}3}
4917 Store a value with the magnitude of operand 1 and the sign of operand
4920 The @code{copysign} built-in function of C always uses the mode which
4921 corresponds to the C data type @code{double} and the @code{copysignf}
4922 built-in function uses the mode which corresponds to the C data
4925 @cindex @code{ffs@var{m}2} instruction pattern
4926 @item @samp{ffs@var{m}2}
4927 Store into operand 0 one plus the index of the least significant 1-bit
4928 of operand 1. If operand 1 is zero, store zero. @var{m} is the mode
4929 of operand 0; operand 1's mode is specified by the instruction
4930 pattern, and the compiler will convert the operand to that mode before
4931 generating the instruction.
4933 The @code{ffs} built-in function of C always uses the mode which
4934 corresponds to the C data type @code{int}.
4936 @cindex @code{clz@var{m}2} instruction pattern
4937 @item @samp{clz@var{m}2}
4938 Store into operand 0 the number of leading 0-bits in @var{x}, starting
4939 at the most significant bit position. If @var{x} is 0, the
4940 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4941 the result is undefined or has a useful value.
4942 @var{m} is the mode of operand 0; operand 1's mode is
4943 specified by the instruction pattern, and the compiler will convert the
4944 operand to that mode before generating the instruction.
4946 @cindex @code{ctz@var{m}2} instruction pattern
4947 @item @samp{ctz@var{m}2}
4948 Store into operand 0 the number of trailing 0-bits in @var{x}, starting
4949 at the least significant bit position. If @var{x} is 0, the
4950 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}) macro defines if
4951 the result is undefined or has a useful value.
4952 @var{m} is the mode of operand 0; operand 1's mode is
4953 specified by the instruction pattern, and the compiler will convert the
4954 operand to that mode before generating the instruction.
4956 @cindex @code{popcount@var{m}2} instruction pattern
4957 @item @samp{popcount@var{m}2}
4958 Store into operand 0 the number of 1-bits in @var{x}. @var{m} is the
4959 mode of operand 0; operand 1's mode is specified by the instruction
4960 pattern, and the compiler will convert the operand to that mode before
4961 generating the instruction.
4963 @cindex @code{parity@var{m}2} instruction pattern
4964 @item @samp{parity@var{m}2}
4965 Store into operand 0 the parity of @var{x}, i.e.@: the number of 1-bits
4966 in @var{x} modulo 2. @var{m} is the mode of operand 0; operand 1's mode
4967 is specified by the instruction pattern, and the compiler will convert
4968 the operand to that mode before generating the instruction.
4970 @cindex @code{one_cmpl@var{m}2} instruction pattern
4971 @item @samp{one_cmpl@var{m}2}
4972 Store the bitwise-complement of operand 1 into operand 0.
4974 @cindex @code{movmem@var{m}} instruction pattern
4975 @item @samp{movmem@var{m}}
4976 Block move instruction. The destination and source blocks of memory
4977 are the first two operands, and both are @code{mem:BLK}s with an
4978 address in mode @code{Pmode}.
4980 The number of bytes to move is the third operand, in mode @var{m}.
4981 Usually, you specify @code{word_mode} for @var{m}. However, if you can
4982 generate better code knowing the range of valid lengths is smaller than
4983 those representable in a full word, you should provide a pattern with a
4984 mode corresponding to the range of values you can handle efficiently
4985 (e.g., @code{QImode} for values in the range 0--127; note we avoid numbers
4986 that appear negative) and also a pattern with @code{word_mode}.
4988 The fourth operand is the known shared alignment of the source and
4989 destination, in the form of a @code{const_int} rtx. Thus, if the
4990 compiler knows that both source and destination are word-aligned,
4991 it may provide the value 4 for this operand.
4993 Optional operands 5 and 6 specify expected alignment and size of block
4994 respectively. The expected alignment differs from alignment in operand 4
4995 in a way that the blocks are not required to be aligned according to it in
4996 all cases. This expected alignment is also in bytes, just like operand 4.
4997 Expected size, when unknown, is set to @code{(const_int -1)}.
4999 Descriptions of multiple @code{movmem@var{m}} patterns can only be
5000 beneficial if the patterns for smaller modes have fewer restrictions
5001 on their first, second and fourth operands. Note that the mode @var{m}
5002 in @code{movmem@var{m}} does not impose any restriction on the mode of
5003 individually moved data units in the block.
5005 These patterns need not give special consideration to the possibility
5006 that the source and destination strings might overlap.
5008 @cindex @code{movstr} instruction pattern
5010 String copy instruction, with @code{stpcpy} semantics. Operand 0 is
5011 an output operand in mode @code{Pmode}. The addresses of the
5012 destination and source strings are operands 1 and 2, and both are
5013 @code{mem:BLK}s with addresses in mode @code{Pmode}. The execution of
5014 the expansion of this pattern should store in operand 0 the address in
5015 which the @code{NUL} terminator was stored in the destination string.
5017 @cindex @code{setmem@var{m}} instruction pattern
5018 @item @samp{setmem@var{m}}
5019 Block set instruction. The destination string is the first operand,
5020 given as a @code{mem:BLK} whose address is in mode @code{Pmode}. The
5021 number of bytes to set is the second operand, in mode @var{m}. The value to
5022 initialize the memory with is the third operand. Targets that only support the
5023 clearing of memory should reject any value that is not the constant 0. See
5024 @samp{movmem@var{m}} for a discussion of the choice of mode.
5026 The fourth operand is the known alignment of the destination, in the form
5027 of a @code{const_int} rtx. Thus, if the compiler knows that the
5028 destination is word-aligned, it may provide the value 4 for this
5031 Optional operands 5 and 6 specify expected alignment and size of block
5032 respectively. The expected alignment differs from alignment in operand 4
5033 in a way that the blocks are not required to be aligned according to it in
5034 all cases. This expected alignment is also in bytes, just like operand 4.
5035 Expected size, when unknown, is set to @code{(const_int -1)}.
5037 The use for multiple @code{setmem@var{m}} is as for @code{movmem@var{m}}.
5039 @cindex @code{cmpstrn@var{m}} instruction pattern
5040 @item @samp{cmpstrn@var{m}}
5041 String compare instruction, with five operands. Operand 0 is the output;
5042 it has mode @var{m}. The remaining four operands are like the operands
5043 of @samp{movmem@var{m}}. The two memory blocks specified are compared
5044 byte by byte in lexicographic order starting at the beginning of each
5045 string. The instruction is not allowed to prefetch more than one byte
5046 at a time since either string may end in the first byte and reading past
5047 that may access an invalid page or segment and cause a fault. The
5048 comparison terminates early if the fetched bytes are different or if
5049 they are equal to zero. The effect of the instruction is to store a
5050 value in operand 0 whose sign indicates the result of the comparison.
5052 @cindex @code{cmpstr@var{m}} instruction pattern
5053 @item @samp{cmpstr@var{m}}
5054 String compare instruction, without known maximum length. Operand 0 is the
5055 output; it has mode @var{m}. The second and third operand are the blocks of
5056 memory to be compared; both are @code{mem:BLK} with an address in mode
5059 The fourth operand is the known shared alignment of the source and
5060 destination, in the form of a @code{const_int} rtx. Thus, if the
5061 compiler knows that both source and destination are word-aligned,
5062 it may provide the value 4 for this operand.
5064 The two memory blocks specified are compared byte by byte in lexicographic
5065 order starting at the beginning of each string. The instruction is not allowed
5066 to prefetch more than one byte at a time since either string may end in the
5067 first byte and reading past that may access an invalid page or segment and
5068 cause a fault. The comparison will terminate when the fetched bytes
5069 are different or if they are equal to zero. The effect of the
5070 instruction is to store a value in operand 0 whose sign indicates the
5071 result of the comparison.
5073 @cindex @code{cmpmem@var{m}} instruction pattern
5074 @item @samp{cmpmem@var{m}}
5075 Block compare instruction, with five operands like the operands
5076 of @samp{cmpstr@var{m}}. The two memory blocks specified are compared
5077 byte by byte in lexicographic order starting at the beginning of each
5078 block. Unlike @samp{cmpstr@var{m}} the instruction can prefetch
5079 any bytes in the two memory blocks. Also unlike @samp{cmpstr@var{m}}
5080 the comparison will not stop if both bytes are zero. The effect of
5081 the instruction is to store a value in operand 0 whose sign indicates
5082 the result of the comparison.
5084 @cindex @code{strlen@var{m}} instruction pattern
5085 @item @samp{strlen@var{m}}
5086 Compute the length of a string, with three operands.
5087 Operand 0 is the result (of mode @var{m}), operand 1 is
5088 a @code{mem} referring to the first character of the string,
5089 operand 2 is the character to search for (normally zero),
5090 and operand 3 is a constant describing the known alignment
5091 of the beginning of the string.
5093 @cindex @code{float@var{m}@var{n}2} instruction pattern
5094 @item @samp{float@var{m}@var{n}2}
5095 Convert signed integer operand 1 (valid for fixed point mode @var{m}) to
5096 floating point mode @var{n} and store in operand 0 (which has mode
5099 @cindex @code{floatuns@var{m}@var{n}2} instruction pattern
5100 @item @samp{floatuns@var{m}@var{n}2}
5101 Convert unsigned integer operand 1 (valid for fixed point mode @var{m})
5102 to floating point mode @var{n} and store in operand 0 (which has mode
5105 @cindex @code{fix@var{m}@var{n}2} instruction pattern
5106 @item @samp{fix@var{m}@var{n}2}
5107 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5108 point mode @var{n} as a signed number and store in operand 0 (which
5109 has mode @var{n}). This instruction's result is defined only when
5110 the value of operand 1 is an integer.
5112 If the machine description defines this pattern, it also needs to
5113 define the @code{ftrunc} pattern.
5115 @cindex @code{fixuns@var{m}@var{n}2} instruction pattern
5116 @item @samp{fixuns@var{m}@var{n}2}
5117 Convert operand 1 (valid for floating point mode @var{m}) to fixed
5118 point mode @var{n} as an unsigned number and store in operand 0 (which
5119 has mode @var{n}). This instruction's result is defined only when the
5120 value of operand 1 is an integer.
5122 @cindex @code{ftrunc@var{m}2} instruction pattern
5123 @item @samp{ftrunc@var{m}2}
5124 Convert operand 1 (valid for floating point mode @var{m}) to an
5125 integer value, still represented in floating point mode @var{m}, and
5126 store it in operand 0 (valid for floating point mode @var{m}).
5128 @cindex @code{fix_trunc@var{m}@var{n}2} instruction pattern
5129 @item @samp{fix_trunc@var{m}@var{n}2}
5130 Like @samp{fix@var{m}@var{n}2} but works for any floating point value
5131 of mode @var{m} by converting the value to an integer.
5133 @cindex @code{fixuns_trunc@var{m}@var{n}2} instruction pattern
5134 @item @samp{fixuns_trunc@var{m}@var{n}2}
5135 Like @samp{fixuns@var{m}@var{n}2} but works for any floating point
5136 value of mode @var{m} by converting the value to an integer.
5138 @cindex @code{trunc@var{m}@var{n}2} instruction pattern
5139 @item @samp{trunc@var{m}@var{n}2}
5140 Truncate operand 1 (valid for mode @var{m}) to mode @var{n} and
5141 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5142 point or both floating point.
5144 @cindex @code{extend@var{m}@var{n}2} instruction pattern
5145 @item @samp{extend@var{m}@var{n}2}
5146 Sign-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5147 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5148 point or both floating point.
5150 @cindex @code{zero_extend@var{m}@var{n}2} instruction pattern
5151 @item @samp{zero_extend@var{m}@var{n}2}
5152 Zero-extend operand 1 (valid for mode @var{m}) to mode @var{n} and
5153 store in operand 0 (which has mode @var{n}). Both modes must be fixed
5156 @cindex @code{fract@var{m}@var{n}2} instruction pattern
5157 @item @samp{fract@var{m}@var{n}2}
5158 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5159 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5160 could be fixed-point to fixed-point, signed integer to fixed-point,
5161 fixed-point to signed integer, floating-point to fixed-point,
5162 or fixed-point to floating-point.
5163 When overflows or underflows happen, the results are undefined.
5165 @cindex @code{satfract@var{m}@var{n}2} instruction pattern
5166 @item @samp{satfract@var{m}@var{n}2}
5167 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5168 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5169 could be fixed-point to fixed-point, signed integer to fixed-point,
5170 or floating-point to fixed-point.
5171 When overflows or underflows happen, the instruction saturates the
5172 results to the maximum or the minimum.
5174 @cindex @code{fractuns@var{m}@var{n}2} instruction pattern
5175 @item @samp{fractuns@var{m}@var{n}2}
5176 Convert operand 1 of mode @var{m} to mode @var{n} and store in
5177 operand 0 (which has mode @var{n}). Mode @var{m} and mode @var{n}
5178 could be unsigned integer to fixed-point, or
5179 fixed-point to unsigned integer.
5180 When overflows or underflows happen, the results are undefined.
5182 @cindex @code{satfractuns@var{m}@var{n}2} instruction pattern
5183 @item @samp{satfractuns@var{m}@var{n}2}
5184 Convert unsigned integer operand 1 of mode @var{m} to fixed-point mode
5185 @var{n} and store in operand 0 (which has mode @var{n}).
5186 When overflows or underflows happen, the instruction saturates the
5187 results to the maximum or the minimum.
5189 @cindex @code{extv} instruction pattern
5191 Extract a bit-field from operand 1 (a register or memory operand), where
5192 operand 2 specifies the width in bits and operand 3 the starting bit,
5193 and store it in operand 0. Operand 0 must have mode @code{word_mode}.
5194 Operand 1 may have mode @code{byte_mode} or @code{word_mode}; often
5195 @code{word_mode} is allowed only for registers. Operands 2 and 3 must
5196 be valid for @code{word_mode}.
5198 The RTL generation pass generates this instruction only with constants
5199 for operands 2 and 3 and the constant is never zero for operand 2.
5201 The bit-field value is sign-extended to a full word integer
5202 before it is stored in operand 0.
5204 @cindex @code{extzv} instruction pattern
5206 Like @samp{extv} except that the bit-field value is zero-extended.
5208 @cindex @code{insv} instruction pattern
5210 Store operand 3 (which must be valid for @code{word_mode}) into a
5211 bit-field in operand 0, where operand 1 specifies the width in bits and
5212 operand 2 the starting bit. Operand 0 may have mode @code{byte_mode} or
5213 @code{word_mode}; often @code{word_mode} is allowed only for registers.
5214 Operands 1 and 2 must be valid for @code{word_mode}.
5216 The RTL generation pass generates this instruction only with constants
5217 for operands 1 and 2 and the constant is never zero for operand 1.
5219 @cindex @code{mov@var{mode}cc} instruction pattern
5220 @item @samp{mov@var{mode}cc}
5221 Conditionally move operand 2 or operand 3 into operand 0 according to the
5222 comparison in operand 1. If the comparison is true, operand 2 is moved
5223 into operand 0, otherwise operand 3 is moved.
5225 The mode of the operands being compared need not be the same as the operands
5226 being moved. Some machines, sparc64 for example, have instructions that
5227 conditionally move an integer value based on the floating point condition
5228 codes and vice versa.
5230 If the machine does not have conditional move instructions, do not
5231 define these patterns.
5233 @cindex @code{add@var{mode}cc} instruction pattern
5234 @item @samp{add@var{mode}cc}
5235 Similar to @samp{mov@var{mode}cc} but for conditional addition. Conditionally
5236 move operand 2 or (operands 2 + operand 3) into operand 0 according to the
5237 comparison in operand 1. If the comparison is true, operand 2 is moved into
5238 operand 0, otherwise (operand 2 + operand 3) is moved.
5240 @cindex @code{cstore@var{mode}4} instruction pattern
5241 @item @samp{cstore@var{mode}4}
5242 Store zero or nonzero in operand 0 according to whether a comparison
5243 is true. Operand 1 is a comparison operator. Operand 2 and operand 3
5244 are the first and second operand of the comparison, respectively.
5245 You specify the mode that operand 0 must have when you write the
5246 @code{match_operand} expression. The compiler automatically sees which
5247 mode you have used and supplies an operand of that mode.
5249 The value stored for a true condition must have 1 as its low bit, or
5250 else must be negative. Otherwise the instruction is not suitable and
5251 you should omit it from the machine description. You describe to the
5252 compiler exactly which value is stored by defining the macro
5253 @code{STORE_FLAG_VALUE} (@pxref{Misc}). If a description cannot be
5254 found that can be used for all the possible comparison operators, you
5255 should pick one and use a @code{define_expand} to map all results
5256 onto the one you chose.
5258 These operations may @code{FAIL}, but should do so only in relatively
5259 uncommon cases; if they would @code{FAIL} for common cases involving
5260 integer comparisons, it is best to restrict the predicates to not
5261 allow these operands. Likewise if a given comparison operator will
5262 always fail, independent of the operands (for floating-point modes, the
5263 @code{ordered_comparison_operator} predicate is often useful in this case).
5265 If this pattern is omitted, the compiler will generate a conditional
5266 branch---for example, it may copy a constant one to the target and branching
5267 around an assignment of zero to the target---or a libcall. If the predicate
5268 for operand 1 only rejects some operators, it will also try reordering the
5269 operands and/or inverting the result value (e.g.@: by an exclusive OR).
5270 These possibilities could be cheaper or equivalent to the instructions
5271 used for the @samp{cstore@var{mode}4} pattern followed by those required
5272 to convert a positive result from @code{STORE_FLAG_VALUE} to 1; in this
5273 case, you can and should make operand 1's predicate reject some operators
5274 in the @samp{cstore@var{mode}4} pattern, or remove the pattern altogether
5275 from the machine description.
5277 @cindex @code{cbranch@var{mode}4} instruction pattern
5278 @item @samp{cbranch@var{mode}4}
5279 Conditional branch instruction combined with a compare instruction.
5280 Operand 0 is a comparison operator. Operand 1 and operand 2 are the
5281 first and second operands of the comparison, respectively. Operand 3
5282 is a @code{label_ref} that refers to the label to jump to.
5284 @cindex @code{jump} instruction pattern
5286 A jump inside a function; an unconditional branch. Operand 0 is the
5287 @code{label_ref} of the label to jump to. This pattern name is mandatory
5290 @cindex @code{call} instruction pattern
5292 Subroutine call instruction returning no value. Operand 0 is the
5293 function to call; operand 1 is the number of bytes of arguments pushed
5294 as a @code{const_int}; operand 2 is the number of registers used as
5297 On most machines, operand 2 is not actually stored into the RTL
5298 pattern. It is supplied for the sake of some RISC machines which need
5299 to put this information into the assembler code; they can put it in
5300 the RTL instead of operand 1.
5302 Operand 0 should be a @code{mem} RTX whose address is the address of the
5303 function. Note, however, that this address can be a @code{symbol_ref}
5304 expression even if it would not be a legitimate memory address on the
5305 target machine. If it is also not a valid argument for a call
5306 instruction, the pattern for this operation should be a
5307 @code{define_expand} (@pxref{Expander Definitions}) that places the
5308 address into a register and uses that register in the call instruction.
5310 @cindex @code{call_value} instruction pattern
5311 @item @samp{call_value}
5312 Subroutine call instruction returning a value. Operand 0 is the hard
5313 register in which the value is returned. There are three more
5314 operands, the same as the three operands of the @samp{call}
5315 instruction (but with numbers increased by one).
5317 Subroutines that return @code{BLKmode} objects use the @samp{call}
5320 @cindex @code{call_pop} instruction pattern
5321 @cindex @code{call_value_pop} instruction pattern
5322 @item @samp{call_pop}, @samp{call_value_pop}
5323 Similar to @samp{call} and @samp{call_value}, except used if defined and
5324 if @code{RETURN_POPS_ARGS} is nonzero. They should emit a @code{parallel}
5325 that contains both the function call and a @code{set} to indicate the
5326 adjustment made to the frame pointer.
5328 For machines where @code{RETURN_POPS_ARGS} can be nonzero, the use of these
5329 patterns increases the number of functions for which the frame pointer
5330 can be eliminated, if desired.
5332 @cindex @code{untyped_call} instruction pattern
5333 @item @samp{untyped_call}
5334 Subroutine call instruction returning a value of any type. Operand 0 is
5335 the function to call; operand 1 is a memory location where the result of
5336 calling the function is to be stored; operand 2 is a @code{parallel}
5337 expression where each element is a @code{set} expression that indicates
5338 the saving of a function return value into the result block.
5340 This instruction pattern should be defined to support
5341 @code{__builtin_apply} on machines where special instructions are needed
5342 to call a subroutine with arbitrary arguments or to save the value
5343 returned. This instruction pattern is required on machines that have
5344 multiple registers that can hold a return value
5345 (i.e.@: @code{FUNCTION_VALUE_REGNO_P} is true for more than one register).
5347 @cindex @code{return} instruction pattern
5349 Subroutine return instruction. This instruction pattern name should be
5350 defined only if a single instruction can do all the work of returning
5353 Like the @samp{mov@var{m}} patterns, this pattern is also used after the
5354 RTL generation phase. In this case it is to support machines where
5355 multiple instructions are usually needed to return from a function, but
5356 some class of functions only requires one instruction to implement a
5357 return. Normally, the applicable functions are those which do not need
5358 to save any registers or allocate stack space.
5360 It is valid for this pattern to expand to an instruction using
5361 @code{simple_return} if no epilogue is required.
5363 @cindex @code{simple_return} instruction pattern
5364 @item @samp{simple_return}
5365 Subroutine return instruction. This instruction pattern name should be
5366 defined only if a single instruction can do all the work of returning
5367 from a function on a path where no epilogue is required. This pattern
5368 is very similar to the @code{return} instruction pattern, but it is emitted
5369 only by the shrink-wrapping optimization on paths where the function
5370 prologue has not been executed, and a function return should occur without
5371 any of the effects of the epilogue. Additional uses may be introduced on
5372 paths where both the prologue and the epilogue have executed.
5374 @findex reload_completed
5375 @findex leaf_function_p
5376 For such machines, the condition specified in this pattern should only
5377 be true when @code{reload_completed} is nonzero and the function's
5378 epilogue would only be a single instruction. For machines with register
5379 windows, the routine @code{leaf_function_p} may be used to determine if
5380 a register window push is required.
5382 Machines that have conditional return instructions should define patterns
5388 (if_then_else (match_operator
5389 0 "comparison_operator"
5390 [(cc0) (const_int 0)])
5397 where @var{condition} would normally be the same condition specified on the
5398 named @samp{return} pattern.
5400 @cindex @code{untyped_return} instruction pattern
5401 @item @samp{untyped_return}
5402 Untyped subroutine return instruction. This instruction pattern should
5403 be defined to support @code{__builtin_return} on machines where special
5404 instructions are needed to return a value of any type.
5406 Operand 0 is a memory location where the result of calling a function
5407 with @code{__builtin_apply} is stored; operand 1 is a @code{parallel}
5408 expression where each element is a @code{set} expression that indicates
5409 the restoring of a function return value from the result block.
5411 @cindex @code{nop} instruction pattern
5413 No-op instruction. This instruction pattern name should always be defined
5414 to output a no-op in assembler code. @code{(const_int 0)} will do as an
5417 @cindex @code{indirect_jump} instruction pattern
5418 @item @samp{indirect_jump}
5419 An instruction to jump to an address which is operand zero.
5420 This pattern name is mandatory on all machines.
5422 @cindex @code{casesi} instruction pattern
5424 Instruction to jump through a dispatch table, including bounds checking.
5425 This instruction takes five operands:
5429 The index to dispatch on, which has mode @code{SImode}.
5432 The lower bound for indices in the table, an integer constant.
5435 The total range of indices in the table---the largest index
5436 minus the smallest one (both inclusive).
5439 A label that precedes the table itself.
5442 A label to jump to if the index has a value outside the bounds.
5445 The table is an @code{addr_vec} or @code{addr_diff_vec} inside of a
5446 @code{jump_insn}. The number of elements in the table is one plus the
5447 difference between the upper bound and the lower bound.
5449 @cindex @code{tablejump} instruction pattern
5450 @item @samp{tablejump}
5451 Instruction to jump to a variable address. This is a low-level
5452 capability which can be used to implement a dispatch table when there
5453 is no @samp{casesi} pattern.
5455 This pattern requires two operands: the address or offset, and a label
5456 which should immediately precede the jump table. If the macro
5457 @code{CASE_VECTOR_PC_RELATIVE} evaluates to a nonzero value then the first
5458 operand is an offset which counts from the address of the table; otherwise,
5459 it is an absolute address to jump to. In either case, the first operand has
5462 The @samp{tablejump} insn is always the last insn before the jump
5463 table it uses. Its assembler code normally has no need to use the
5464 second operand, but you should incorporate it in the RTL pattern so
5465 that the jump optimizer will not delete the table as unreachable code.
5468 @cindex @code{decrement_and_branch_until_zero} instruction pattern
5469 @item @samp{decrement_and_branch_until_zero}
5470 Conditional branch instruction that decrements a register and
5471 jumps if the register is nonzero. Operand 0 is the register to
5472 decrement and test; operand 1 is the label to jump to if the
5473 register is nonzero. @xref{Looping Patterns}.
5475 This optional instruction pattern is only used by the combiner,
5476 typically for loops reversed by the loop optimizer when strength
5477 reduction is enabled.
5479 @cindex @code{doloop_end} instruction pattern
5480 @item @samp{doloop_end}
5481 Conditional branch instruction that decrements a register and jumps if
5482 the register is nonzero. This instruction takes five operands: Operand
5483 0 is the register to decrement and test; operand 1 is the number of loop
5484 iterations as a @code{const_int} or @code{const0_rtx} if this cannot be
5485 determined until run-time; operand 2 is the actual or estimated maximum
5486 number of iterations as a @code{const_int}; operand 3 is the number of
5487 enclosed loops as a @code{const_int} (an innermost loop has a value of
5488 1); operand 4 is the label to jump to if the register is nonzero.
5489 @xref{Looping Patterns}.
5491 This optional instruction pattern should be defined for machines with
5492 low-overhead looping instructions as the loop optimizer will try to
5493 modify suitable loops to utilize it. If nested low-overhead looping is
5494 not supported, use a @code{define_expand} (@pxref{Expander Definitions})
5495 and make the pattern fail if operand 3 is not @code{const1_rtx}.
5496 Similarly, if the actual or estimated maximum number of iterations is
5497 too large for this instruction, make it fail.
5499 @cindex @code{doloop_begin} instruction pattern
5500 @item @samp{doloop_begin}
5501 Companion instruction to @code{doloop_end} required for machines that
5502 need to perform some initialization, such as loading special registers
5503 used by a low-overhead looping instruction. If initialization insns do
5504 not always need to be emitted, use a @code{define_expand}
5505 (@pxref{Expander Definitions}) and make it fail.
5508 @cindex @code{canonicalize_funcptr_for_compare} instruction pattern
5509 @item @samp{canonicalize_funcptr_for_compare}
5510 Canonicalize the function pointer in operand 1 and store the result
5513 Operand 0 is always a @code{reg} and has mode @code{Pmode}; operand 1
5514 may be a @code{reg}, @code{mem}, @code{symbol_ref}, @code{const_int}, etc
5515 and also has mode @code{Pmode}.
5517 Canonicalization of a function pointer usually involves computing
5518 the address of the function which would be called if the function
5519 pointer were used in an indirect call.
5521 Only define this pattern if function pointers on the target machine
5522 can have different values but still call the same function when
5523 used in an indirect call.
5525 @cindex @code{save_stack_block} instruction pattern
5526 @cindex @code{save_stack_function} instruction pattern
5527 @cindex @code{save_stack_nonlocal} instruction pattern
5528 @cindex @code{restore_stack_block} instruction pattern
5529 @cindex @code{restore_stack_function} instruction pattern
5530 @cindex @code{restore_stack_nonlocal} instruction pattern
5531 @item @samp{save_stack_block}
5532 @itemx @samp{save_stack_function}
5533 @itemx @samp{save_stack_nonlocal}
5534 @itemx @samp{restore_stack_block}
5535 @itemx @samp{restore_stack_function}
5536 @itemx @samp{restore_stack_nonlocal}
5537 Most machines save and restore the stack pointer by copying it to or
5538 from an object of mode @code{Pmode}. Do not define these patterns on
5541 Some machines require special handling for stack pointer saves and
5542 restores. On those machines, define the patterns corresponding to the
5543 non-standard cases by using a @code{define_expand} (@pxref{Expander
5544 Definitions}) that produces the required insns. The three types of
5545 saves and restores are:
5549 @samp{save_stack_block} saves the stack pointer at the start of a block
5550 that allocates a variable-sized object, and @samp{restore_stack_block}
5551 restores the stack pointer when the block is exited.
5554 @samp{save_stack_function} and @samp{restore_stack_function} do a
5555 similar job for the outermost block of a function and are used when the
5556 function allocates variable-sized objects or calls @code{alloca}. Only
5557 the epilogue uses the restored stack pointer, allowing a simpler save or
5558 restore sequence on some machines.
5561 @samp{save_stack_nonlocal} is used in functions that contain labels
5562 branched to by nested functions. It saves the stack pointer in such a
5563 way that the inner function can use @samp{restore_stack_nonlocal} to
5564 restore the stack pointer. The compiler generates code to restore the
5565 frame and argument pointer registers, but some machines require saving
5566 and restoring additional data such as register window information or
5567 stack backchains. Place insns in these patterns to save and restore any
5571 When saving the stack pointer, operand 0 is the save area and operand 1
5572 is the stack pointer. The mode used to allocate the save area defaults
5573 to @code{Pmode} but you can override that choice by defining the
5574 @code{STACK_SAVEAREA_MODE} macro (@pxref{Storage Layout}). You must
5575 specify an integral mode, or @code{VOIDmode} if no save area is needed
5576 for a particular type of save (either because no save is needed or
5577 because a machine-specific save area can be used). Operand 0 is the
5578 stack pointer and operand 1 is the save area for restore operations. If
5579 @samp{save_stack_block} is defined, operand 0 must not be
5580 @code{VOIDmode} since these saves can be arbitrarily nested.
5582 A save area is a @code{mem} that is at a constant offset from
5583 @code{virtual_stack_vars_rtx} when the stack pointer is saved for use by
5584 nonlocal gotos and a @code{reg} in the other two cases.
5586 @cindex @code{allocate_stack} instruction pattern
5587 @item @samp{allocate_stack}
5588 Subtract (or add if @code{STACK_GROWS_DOWNWARD} is undefined) operand 1 from
5589 the stack pointer to create space for dynamically allocated data.
5591 Store the resultant pointer to this space into operand 0. If you
5592 are allocating space from the main stack, do this by emitting a
5593 move insn to copy @code{virtual_stack_dynamic_rtx} to operand 0.
5594 If you are allocating the space elsewhere, generate code to copy the
5595 location of the space to operand 0. In the latter case, you must
5596 ensure this space gets freed when the corresponding space on the main
5599 Do not define this pattern if all that must be done is the subtraction.
5600 Some machines require other operations such as stack probes or
5601 maintaining the back chain. Define this pattern to emit those
5602 operations in addition to updating the stack pointer.
5604 @cindex @code{check_stack} instruction pattern
5605 @item @samp{check_stack}
5606 If stack checking (@pxref{Stack Checking}) cannot be done on your system by
5607 probing the stack, define this pattern to perform the needed check and signal
5608 an error if the stack has overflowed. The single operand is the address in
5609 the stack farthest from the current stack pointer that you need to validate.
5610 Normally, on platforms where this pattern is needed, you would obtain the
5611 stack limit from a global or thread-specific variable or register.
5613 @cindex @code{probe_stack} instruction pattern
5614 @item @samp{probe_stack}
5615 If stack checking (@pxref{Stack Checking}) can be done on your system by
5616 probing the stack but doing it with a ``store zero'' instruction is not valid
5617 or optimal, define this pattern to do the probing differently and signal an
5618 error if the stack has overflowed. The single operand is the memory reference
5619 in the stack that needs to be probed.
5621 @cindex @code{nonlocal_goto} instruction pattern
5622 @item @samp{nonlocal_goto}
5623 Emit code to generate a non-local goto, e.g., a jump from one function
5624 to a label in an outer function. This pattern has four arguments,
5625 each representing a value to be used in the jump. The first
5626 argument is to be loaded into the frame pointer, the second is
5627 the address to branch to (code to dispatch to the actual label),
5628 the third is the address of a location where the stack is saved,
5629 and the last is the address of the label, to be placed in the
5630 location for the incoming static chain.
5632 On most machines you need not define this pattern, since GCC will
5633 already generate the correct code, which is to load the frame pointer
5634 and static chain, restore the stack (using the
5635 @samp{restore_stack_nonlocal} pattern, if defined), and jump indirectly
5636 to the dispatcher. You need only define this pattern if this code will
5637 not work on your machine.
5639 @cindex @code{nonlocal_goto_receiver} instruction pattern
5640 @item @samp{nonlocal_goto_receiver}
5641 This pattern, if defined, contains code needed at the target of a
5642 nonlocal goto after the code already generated by GCC@. You will not
5643 normally need to define this pattern. A typical reason why you might
5644 need this pattern is if some value, such as a pointer to a global table,
5645 must be restored when the frame pointer is restored. Note that a nonlocal
5646 goto only occurs within a unit-of-translation, so a global table pointer
5647 that is shared by all functions of a given module need not be restored.
5648 There are no arguments.
5650 @cindex @code{exception_receiver} instruction pattern
5651 @item @samp{exception_receiver}
5652 This pattern, if defined, contains code needed at the site of an
5653 exception handler that isn't needed at the site of a nonlocal goto. You
5654 will not normally need to define this pattern. A typical reason why you
5655 might need this pattern is if some value, such as a pointer to a global
5656 table, must be restored after control flow is branched to the handler of
5657 an exception. There are no arguments.
5659 @cindex @code{builtin_setjmp_setup} instruction pattern
5660 @item @samp{builtin_setjmp_setup}
5661 This pattern, if defined, contains additional code needed to initialize
5662 the @code{jmp_buf}. You will not normally need to define this pattern.
5663 A typical reason why you might need this pattern is if some value, such
5664 as a pointer to a global table, must be restored. Though it is
5665 preferred that the pointer value be recalculated if possible (given the
5666 address of a label for instance). The single argument is a pointer to
5667 the @code{jmp_buf}. Note that the buffer is five words long and that
5668 the first three are normally used by the generic mechanism.
5670 @cindex @code{builtin_setjmp_receiver} instruction pattern
5671 @item @samp{builtin_setjmp_receiver}
5672 This pattern, if defined, contains code needed at the site of a
5673 built-in setjmp that isn't needed at the site of a nonlocal goto. You
5674 will not normally need to define this pattern. A typical reason why you
5675 might need this pattern is if some value, such as a pointer to a global
5676 table, must be restored. It takes one argument, which is the label
5677 to which builtin_longjmp transfered control; this pattern may be emitted
5678 at a small offset from that label.
5680 @cindex @code{builtin_longjmp} instruction pattern
5681 @item @samp{builtin_longjmp}
5682 This pattern, if defined, performs the entire action of the longjmp.
5683 You will not normally need to define this pattern unless you also define
5684 @code{builtin_setjmp_setup}. The single argument is a pointer to the
5687 @cindex @code{eh_return} instruction pattern
5688 @item @samp{eh_return}
5689 This pattern, if defined, affects the way @code{__builtin_eh_return},
5690 and thence the call frame exception handling library routines, are
5691 built. It is intended to handle non-trivial actions needed along
5692 the abnormal return path.
5694 The address of the exception handler to which the function should return
5695 is passed as operand to this pattern. It will normally need to copied by
5696 the pattern to some special register or memory location.
5697 If the pattern needs to determine the location of the target call
5698 frame in order to do so, it may use @code{EH_RETURN_STACKADJ_RTX},
5699 if defined; it will have already been assigned.
5701 If this pattern is not defined, the default action will be to simply
5702 copy the return address to @code{EH_RETURN_HANDLER_RTX}. Either
5703 that macro or this pattern needs to be defined if call frame exception
5704 handling is to be used.
5706 @cindex @code{prologue} instruction pattern
5707 @anchor{prologue instruction pattern}
5708 @item @samp{prologue}
5709 This pattern, if defined, emits RTL for entry to a function. The function
5710 entry is responsible for setting up the stack frame, initializing the frame
5711 pointer register, saving callee saved registers, etc.
5713 Using a prologue pattern is generally preferred over defining
5714 @code{TARGET_ASM_FUNCTION_PROLOGUE} to emit assembly code for the prologue.
5716 The @code{prologue} pattern is particularly useful for targets which perform
5717 instruction scheduling.
5719 @cindex @code{window_save} instruction pattern
5720 @anchor{window_save instruction pattern}
5721 @item @samp{window_save}
5722 This pattern, if defined, emits RTL for a register window save. It should
5723 be defined if the target machine has register windows but the window events
5724 are decoupled from calls to subroutines. The canonical example is the SPARC
5727 @cindex @code{epilogue} instruction pattern
5728 @anchor{epilogue instruction pattern}
5729 @item @samp{epilogue}
5730 This pattern emits RTL for exit from a function. The function
5731 exit is responsible for deallocating the stack frame, restoring callee saved
5732 registers and emitting the return instruction.
5734 Using an epilogue pattern is generally preferred over defining
5735 @code{TARGET_ASM_FUNCTION_EPILOGUE} to emit assembly code for the epilogue.
5737 The @code{epilogue} pattern is particularly useful for targets which perform
5738 instruction scheduling or which have delay slots for their return instruction.
5740 @cindex @code{sibcall_epilogue} instruction pattern
5741 @item @samp{sibcall_epilogue}
5742 This pattern, if defined, emits RTL for exit from a function without the final
5743 branch back to the calling function. This pattern will be emitted before any
5744 sibling call (aka tail call) sites.
5746 The @code{sibcall_epilogue} pattern must not clobber any arguments used for
5747 parameter passing or any stack slots for arguments passed to the current
5750 @cindex @code{trap} instruction pattern
5752 This pattern, if defined, signals an error, typically by causing some
5753 kind of signal to be raised. Among other places, it is used by the Java
5754 front end to signal `invalid array index' exceptions.
5756 @cindex @code{ctrap@var{MM}4} instruction pattern
5757 @item @samp{ctrap@var{MM}4}
5758 Conditional trap instruction. Operand 0 is a piece of RTL which
5759 performs a comparison, and operands 1 and 2 are the arms of the
5760 comparison. Operand 3 is the trap code, an integer.
5762 A typical @code{ctrap} pattern looks like
5765 (define_insn "ctrapsi4"
5766 [(trap_if (match_operator 0 "trap_operator"
5767 [(match_operand 1 "register_operand")
5768 (match_operand 2 "immediate_operand")])
5769 (match_operand 3 "const_int_operand" "i"))]
5774 @cindex @code{prefetch} instruction pattern
5775 @item @samp{prefetch}
5777 This pattern, if defined, emits code for a non-faulting data prefetch
5778 instruction. Operand 0 is the address of the memory to prefetch. Operand 1
5779 is a constant 1 if the prefetch is preparing for a write to the memory
5780 address, or a constant 0 otherwise. Operand 2 is the expected degree of
5781 temporal locality of the data and is a value between 0 and 3, inclusive; 0
5782 means that the data has no temporal locality, so it need not be left in the
5783 cache after the access; 3 means that the data has a high degree of temporal
5784 locality and should be left in all levels of cache possible; 1 and 2 mean,
5785 respectively, a low or moderate degree of temporal locality.
5787 Targets that do not support write prefetches or locality hints can ignore
5788 the values of operands 1 and 2.
5790 @cindex @code{blockage} instruction pattern
5791 @item @samp{blockage}
5793 This pattern defines a pseudo insn that prevents the instruction
5794 scheduler from moving instructions across the boundary defined by the
5795 blockage insn. Normally an UNSPEC_VOLATILE pattern.
5797 @cindex @code{memory_barrier} instruction pattern
5798 @item @samp{memory_barrier}
5800 If the target memory model is not fully synchronous, then this pattern
5801 should be defined to an instruction that orders both loads and stores
5802 before the instruction with respect to loads and stores after the instruction.
5803 This pattern has no operands.
5805 @cindex @code{sync_compare_and_swap@var{mode}} instruction pattern
5806 @item @samp{sync_compare_and_swap@var{mode}}
5808 This pattern, if defined, emits code for an atomic compare-and-swap
5809 operation. Operand 1 is the memory on which the atomic operation is
5810 performed. Operand 2 is the ``old'' value to be compared against the
5811 current contents of the memory location. Operand 3 is the ``new'' value
5812 to store in the memory if the compare succeeds. Operand 0 is the result
5813 of the operation; it should contain the contents of the memory
5814 before the operation. If the compare succeeds, this should obviously be
5815 a copy of operand 2.
5817 This pattern must show that both operand 0 and operand 1 are modified.
5819 This pattern must issue any memory barrier instructions such that all
5820 memory operations before the atomic operation occur before the atomic
5821 operation and all memory operations after the atomic operation occur
5822 after the atomic operation.
5824 For targets where the success or failure of the compare-and-swap
5825 operation is available via the status flags, it is possible to
5826 avoid a separate compare operation and issue the subsequent
5827 branch or store-flag operation immediately after the compare-and-swap.
5828 To this end, GCC will look for a @code{MODE_CC} set in the
5829 output of @code{sync_compare_and_swap@var{mode}}; if the machine
5830 description includes such a set, the target should also define special
5831 @code{cbranchcc4} and/or @code{cstorecc4} instructions. GCC will then
5832 be able to take the destination of the @code{MODE_CC} set and pass it
5833 to the @code{cbranchcc4} or @code{cstorecc4} pattern as the first
5834 operand of the comparison (the second will be @code{(const_int 0)}).
5836 For targets where the operating system may provide support for this
5837 operation via library calls, the @code{sync_compare_and_swap_optab}
5838 may be initialized to a function with the same interface as the
5839 @code{__sync_val_compare_and_swap_@var{n}} built-in. If the entire
5840 set of @var{__sync} builtins are supported via library calls, the
5841 target can initialize all of the optabs at once with
5842 @code{init_sync_libfuncs}.
5843 For the purposes of C++11 @code{std::atomic::is_lock_free}, it is
5844 assumed that these library calls do @emph{not} use any kind of
5845 interruptable locking.
5847 @cindex @code{sync_add@var{mode}} instruction pattern
5848 @cindex @code{sync_sub@var{mode}} instruction pattern
5849 @cindex @code{sync_ior@var{mode}} instruction pattern
5850 @cindex @code{sync_and@var{mode}} instruction pattern
5851 @cindex @code{sync_xor@var{mode}} instruction pattern
5852 @cindex @code{sync_nand@var{mode}} instruction pattern
5853 @item @samp{sync_add@var{mode}}, @samp{sync_sub@var{mode}}
5854 @itemx @samp{sync_ior@var{mode}}, @samp{sync_and@var{mode}}
5855 @itemx @samp{sync_xor@var{mode}}, @samp{sync_nand@var{mode}}
5857 These patterns emit code for an atomic operation on memory.
5858 Operand 0 is the memory on which the atomic operation is performed.
5859 Operand 1 is the second operand to the binary operator.
5861 This pattern must issue any memory barrier instructions such that all
5862 memory operations before the atomic operation occur before the atomic
5863 operation and all memory operations after the atomic operation occur
5864 after the atomic operation.
5866 If these patterns are not defined, the operation will be constructed
5867 from a compare-and-swap operation, if defined.
5869 @cindex @code{sync_old_add@var{mode}} instruction pattern
5870 @cindex @code{sync_old_sub@var{mode}} instruction pattern
5871 @cindex @code{sync_old_ior@var{mode}} instruction pattern
5872 @cindex @code{sync_old_and@var{mode}} instruction pattern
5873 @cindex @code{sync_old_xor@var{mode}} instruction pattern
5874 @cindex @code{sync_old_nand@var{mode}} instruction pattern
5875 @item @samp{sync_old_add@var{mode}}, @samp{sync_old_sub@var{mode}}
5876 @itemx @samp{sync_old_ior@var{mode}}, @samp{sync_old_and@var{mode}}
5877 @itemx @samp{sync_old_xor@var{mode}}, @samp{sync_old_nand@var{mode}}
5879 These patterns are emit code for an atomic operation on memory,
5880 and return the value that the memory contained before the operation.
5881 Operand 0 is the result value, operand 1 is the memory on which the
5882 atomic operation is performed, and operand 2 is the second operand
5883 to the binary operator.
5885 This pattern must issue any memory barrier instructions such that all
5886 memory operations before the atomic operation occur before the atomic
5887 operation and all memory operations after the atomic operation occur
5888 after the atomic operation.
5890 If these patterns are not defined, the operation will be constructed
5891 from a compare-and-swap operation, if defined.
5893 @cindex @code{sync_new_add@var{mode}} instruction pattern
5894 @cindex @code{sync_new_sub@var{mode}} instruction pattern
5895 @cindex @code{sync_new_ior@var{mode}} instruction pattern
5896 @cindex @code{sync_new_and@var{mode}} instruction pattern
5897 @cindex @code{sync_new_xor@var{mode}} instruction pattern
5898 @cindex @code{sync_new_nand@var{mode}} instruction pattern
5899 @item @samp{sync_new_add@var{mode}}, @samp{sync_new_sub@var{mode}}
5900 @itemx @samp{sync_new_ior@var{mode}}, @samp{sync_new_and@var{mode}}
5901 @itemx @samp{sync_new_xor@var{mode}}, @samp{sync_new_nand@var{mode}}
5903 These patterns are like their @code{sync_old_@var{op}} counterparts,
5904 except that they return the value that exists in the memory location
5905 after the operation, rather than before the operation.
5907 @cindex @code{sync_lock_test_and_set@var{mode}} instruction pattern
5908 @item @samp{sync_lock_test_and_set@var{mode}}
5910 This pattern takes two forms, based on the capabilities of the target.
5911 In either case, operand 0 is the result of the operand, operand 1 is
5912 the memory on which the atomic operation is performed, and operand 2
5913 is the value to set in the lock.
5915 In the ideal case, this operation is an atomic exchange operation, in
5916 which the previous value in memory operand is copied into the result
5917 operand, and the value operand is stored in the memory operand.
5919 For less capable targets, any value operand that is not the constant 1
5920 should be rejected with @code{FAIL}. In this case the target may use
5921 an atomic test-and-set bit operation. The result operand should contain
5922 1 if the bit was previously set and 0 if the bit was previously clear.
5923 The true contents of the memory operand are implementation defined.
5925 This pattern must issue any memory barrier instructions such that the
5926 pattern as a whole acts as an acquire barrier, that is all memory
5927 operations after the pattern do not occur until the lock is acquired.
5929 If this pattern is not defined, the operation will be constructed from
5930 a compare-and-swap operation, if defined.
5932 @cindex @code{sync_lock_release@var{mode}} instruction pattern
5933 @item @samp{sync_lock_release@var{mode}}
5935 This pattern, if defined, releases a lock set by
5936 @code{sync_lock_test_and_set@var{mode}}. Operand 0 is the memory
5937 that contains the lock; operand 1 is the value to store in the lock.
5939 If the target doesn't implement full semantics for
5940 @code{sync_lock_test_and_set@var{mode}}, any value operand which is not
5941 the constant 0 should be rejected with @code{FAIL}, and the true contents
5942 of the memory operand are implementation defined.
5944 This pattern must issue any memory barrier instructions such that the
5945 pattern as a whole acts as a release barrier, that is the lock is
5946 released only after all previous memory operations have completed.
5948 If this pattern is not defined, then a @code{memory_barrier} pattern
5949 will be emitted, followed by a store of the value to the memory operand.
5951 @cindex @code{atomic_compare_and_swap@var{mode}} instruction pattern
5952 @item @samp{atomic_compare_and_swap@var{mode}}
5953 This pattern, if defined, emits code for an atomic compare-and-swap
5954 operation with memory model semantics. Operand 2 is the memory on which
5955 the atomic operation is performed. Operand 0 is an output operand which
5956 is set to true or false based on whether the operation succeeded. Operand
5957 1 is an output operand which is set to the contents of the memory before
5958 the operation was attempted. Operand 3 is the value that is expected to
5959 be in memory. Operand 4 is the value to put in memory if the expected
5960 value is found there. Operand 5 is set to 1 if this compare and swap is to
5961 be treated as a weak operation. Operand 6 is the memory model to be used
5962 if the operation is a success. Operand 7 is the memory model to be used
5963 if the operation fails.
5965 If memory referred to in operand 2 contains the value in operand 3, then
5966 operand 4 is stored in memory pointed to by operand 2 and fencing based on
5967 the memory model in operand 6 is issued.
5969 If memory referred to in operand 2 does not contain the value in operand 3,
5970 then fencing based on the memory model in operand 7 is issued.
5972 If a target does not support weak compare-and-swap operations, or the port
5973 elects not to implement weak operations, the argument in operand 5 can be
5974 ignored. Note a strong implementation must be provided.
5976 If this pattern is not provided, the @code{__atomic_compare_exchange}
5977 built-in functions will utilize the legacy @code{sync_compare_and_swap}
5978 pattern with an @code{__ATOMIC_SEQ_CST} memory model.
5980 @cindex @code{atomic_load@var{mode}} instruction pattern
5981 @item @samp{atomic_load@var{mode}}
5982 This pattern implements an atomic load operation with memory model
5983 semantics. Operand 1 is the memory address being loaded from. Operand 0
5984 is the result of the load. Operand 2 is the memory model to be used for
5987 If not present, the @code{__atomic_load} built-in function will either
5988 resort to a normal load with memory barriers, or a compare-and-swap
5989 operation if a normal load would not be atomic.
5991 @cindex @code{atomic_store@var{mode}} instruction pattern
5992 @item @samp{atomic_store@var{mode}}
5993 This pattern implements an atomic store operation with memory model
5994 semantics. Operand 0 is the memory address being stored to. Operand 1
5995 is the value to be written. Operand 2 is the memory model to be used for
5998 If not present, the @code{__atomic_store} built-in function will attempt to
5999 perform a normal store and surround it with any required memory fences. If
6000 the store would not be atomic, then an @code{__atomic_exchange} is
6001 attempted with the result being ignored.
6003 @cindex @code{atomic_exchange@var{mode}} instruction pattern
6004 @item @samp{atomic_exchange@var{mode}}
6005 This pattern implements an atomic exchange operation with memory model
6006 semantics. Operand 1 is the memory location the operation is performed on.
6007 Operand 0 is an output operand which is set to the original value contained
6008 in the memory pointed to by operand 1. Operand 2 is the value to be
6009 stored. Operand 3 is the memory model to be used.
6011 If this pattern is not present, the built-in function
6012 @code{__atomic_exchange} will attempt to preform the operation with a
6013 compare and swap loop.
6015 @cindex @code{atomic_add@var{mode}} instruction pattern
6016 @cindex @code{atomic_sub@var{mode}} instruction pattern
6017 @cindex @code{atomic_or@var{mode}} instruction pattern
6018 @cindex @code{atomic_and@var{mode}} instruction pattern
6019 @cindex @code{atomic_xor@var{mode}} instruction pattern
6020 @cindex @code{atomic_nand@var{mode}} instruction pattern
6021 @item @samp{atomic_add@var{mode}}, @samp{atomic_sub@var{mode}}
6022 @itemx @samp{atomic_or@var{mode}}, @samp{atomic_and@var{mode}}
6023 @itemx @samp{atomic_xor@var{mode}}, @samp{atomic_nand@var{mode}}
6025 These patterns emit code for an atomic operation on memory with memory
6026 model semantics. Operand 0 is the memory on which the atomic operation is
6027 performed. Operand 1 is the second operand to the binary operator.
6028 Operand 2 is the memory model to be used by the operation.
6030 If these patterns are not defined, attempts will be made to use legacy
6031 @code{sync} patterns, or equivilent patterns which return a result. If
6032 none of these are available a compare-and-swap loop will be used.
6034 @cindex @code{atomic_fetch_add@var{mode}} instruction pattern
6035 @cindex @code{atomic_fetch_sub@var{mode}} instruction pattern
6036 @cindex @code{atomic_fetch_or@var{mode}} instruction pattern
6037 @cindex @code{atomic_fetch_and@var{mode}} instruction pattern
6038 @cindex @code{atomic_fetch_xor@var{mode}} instruction pattern
6039 @cindex @code{atomic_fetch_nand@var{mode}} instruction pattern
6040 @item @samp{atomic_fetch_add@var{mode}}, @samp{atomic_fetch_sub@var{mode}}
6041 @itemx @samp{atomic_fetch_or@var{mode}}, @samp{atomic_fetch_and@var{mode}}
6042 @itemx @samp{atomic_fetch_xor@var{mode}}, @samp{atomic_fetch_nand@var{mode}}
6044 These patterns emit code for an atomic operation on memory with memory
6045 model semantics, and return the original value. Operand 0 is an output
6046 operand which contains the value of the memory location before the
6047 operation was performed. Operand 1 is the memory on which the atomic
6048 operation is performed. Operand 2 is the second operand to the binary
6049 operator. Operand 3 is the memory model to be used by the operation.
6051 If these patterns are not defined, attempts will be made to use legacy
6052 @code{sync} patterns. If none of these are available a compare-and-swap
6055 @cindex @code{atomic_add_fetch@var{mode}} instruction pattern
6056 @cindex @code{atomic_sub_fetch@var{mode}} instruction pattern
6057 @cindex @code{atomic_or_fetch@var{mode}} instruction pattern
6058 @cindex @code{atomic_and_fetch@var{mode}} instruction pattern
6059 @cindex @code{atomic_xor_fetch@var{mode}} instruction pattern
6060 @cindex @code{atomic_nand_fetch@var{mode}} instruction pattern
6061 @item @samp{atomic_add_fetch@var{mode}}, @samp{atomic_sub_fetch@var{mode}}
6062 @itemx @samp{atomic_or_fetch@var{mode}}, @samp{atomic_and_fetch@var{mode}}
6063 @itemx @samp{atomic_xor_fetch@var{mode}}, @samp{atomic_nand_fetch@var{mode}}
6065 These patterns emit code for an atomic operation on memory with memory
6066 model semantics and return the result after the operation is performed.
6067 Operand 0 is an output operand which contains the value after the
6068 operation. Operand 1 is the memory on which the atomic operation is
6069 performed. Operand 2 is the second operand to the binary operator.
6070 Operand 3 is the memory model to be used by the operation.
6072 If these patterns are not defined, attempts will be made to use legacy
6073 @code{sync} patterns, or equivilent patterns which return the result before
6074 the operation followed by the arithmetic operation required to produce the
6075 result. If none of these are available a compare-and-swap loop will be
6078 @cindex @code{atomic_test_and_set} instruction pattern
6079 @item @samp{atomic_test_and_set}
6081 This pattern emits code for @code{__builtin_atomic_test_and_set}.
6082 Operand 0 is an output operand which is set to true if the previous
6083 previous contents of the byte was "set", and false otherwise. Operand 1
6084 is the @code{QImode} memory to be modified. Operand 2 is the memory
6087 The specific value that defines "set" is implementation defined, and
6088 is normally based on what is performed by the native atomic test and set
6091 @cindex @code{mem_thread_fence@var{mode}} instruction pattern
6092 @item @samp{mem_thread_fence@var{mode}}
6093 This pattern emits code required to implement a thread fence with
6094 memory model semantics. Operand 0 is the memory model to be used.
6096 If this pattern is not specified, all memory models except
6097 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6100 @cindex @code{mem_signal_fence@var{mode}} instruction pattern
6101 @item @samp{mem_signal_fence@var{mode}}
6102 This pattern emits code required to implement a signal fence with
6103 memory model semantics. Operand 0 is the memory model to be used.
6105 This pattern should impact the compiler optimizers the same way that
6106 mem_signal_fence does, but it does not need to issue any barrier
6109 If this pattern is not specified, all memory models except
6110 @code{__ATOMIC_RELAXED} will result in issuing a @code{sync_synchronize}
6113 @cindex @code{stack_protect_set} instruction pattern
6114 @item @samp{stack_protect_set}
6116 This pattern, if defined, moves a @code{ptr_mode} value from the memory
6117 in operand 1 to the memory in operand 0 without leaving the value in
6118 a register afterward. This is to avoid leaking the value some place
6119 that an attacker might use to rewrite the stack guard slot after
6120 having clobbered it.
6122 If this pattern is not defined, then a plain move pattern is generated.
6124 @cindex @code{stack_protect_test} instruction pattern
6125 @item @samp{stack_protect_test}
6127 This pattern, if defined, compares a @code{ptr_mode} value from the
6128 memory in operand 1 with the memory in operand 0 without leaving the
6129 value in a register afterward and branches to operand 2 if the values
6132 If this pattern is not defined, then a plain compare pattern and
6133 conditional branch pattern is used.
6135 @cindex @code{clear_cache} instruction pattern
6136 @item @samp{clear_cache}
6138 This pattern, if defined, flushes the instruction cache for a region of
6139 memory. The region is bounded to by the Pmode pointers in operand 0
6140 inclusive and operand 1 exclusive.
6142 If this pattern is not defined, a call to the library function
6143 @code{__clear_cache} is used.
6148 @c Each of the following nodes are wrapped in separate
6149 @c "@ifset INTERNALS" to work around memory limits for the default
6150 @c configuration in older tetex distributions. Known to not work:
6151 @c tetex-1.0.7, known to work: tetex-2.0.2.
6153 @node Pattern Ordering
6154 @section When the Order of Patterns Matters
6155 @cindex Pattern Ordering
6156 @cindex Ordering of Patterns
6158 Sometimes an insn can match more than one instruction pattern. Then the
6159 pattern that appears first in the machine description is the one used.
6160 Therefore, more specific patterns (patterns that will match fewer things)
6161 and faster instructions (those that will produce better code when they
6162 do match) should usually go first in the description.
6164 In some cases the effect of ordering the patterns can be used to hide
6165 a pattern when it is not valid. For example, the 68000 has an
6166 instruction for converting a fullword to floating point and another
6167 for converting a byte to floating point. An instruction converting
6168 an integer to floating point could match either one. We put the
6169 pattern to convert the fullword first to make sure that one will
6170 be used rather than the other. (Otherwise a large integer might
6171 be generated as a single-byte immediate quantity, which would not work.)
6172 Instead of using this pattern ordering it would be possible to make the
6173 pattern for convert-a-byte smart enough to deal properly with any
6178 @node Dependent Patterns
6179 @section Interdependence of Patterns
6180 @cindex Dependent Patterns
6181 @cindex Interdependence of Patterns
6183 In some cases machines support instructions identical except for the
6184 machine mode of one or more operands. For example, there may be
6185 ``sign-extend halfword'' and ``sign-extend byte'' instructions whose
6189 (set (match_operand:SI 0 @dots{})
6190 (extend:SI (match_operand:HI 1 @dots{})))
6192 (set (match_operand:SI 0 @dots{})
6193 (extend:SI (match_operand:QI 1 @dots{})))
6197 Constant integers do not specify a machine mode, so an instruction to
6198 extend a constant value could match either pattern. The pattern it
6199 actually will match is the one that appears first in the file. For correct
6200 results, this must be the one for the widest possible mode (@code{HImode},
6201 here). If the pattern matches the @code{QImode} instruction, the results
6202 will be incorrect if the constant value does not actually fit that mode.
6204 Such instructions to extend constants are rarely generated because they are
6205 optimized away, but they do occasionally happen in nonoptimized
6208 If a constraint in a pattern allows a constant, the reload pass may
6209 replace a register with a constant permitted by the constraint in some
6210 cases. Similarly for memory references. Because of this substitution,
6211 you should not provide separate patterns for increment and decrement
6212 instructions. Instead, they should be generated from the same pattern
6213 that supports register-register add insns by examining the operands and
6214 generating the appropriate machine instruction.
6219 @section Defining Jump Instruction Patterns
6220 @cindex jump instruction patterns
6221 @cindex defining jump instruction patterns
6223 GCC does not assume anything about how the machine realizes jumps.
6224 The machine description should define a single pattern, usually
6225 a @code{define_expand}, which expands to all the required insns.
6227 Usually, this would be a comparison insn to set the condition code
6228 and a separate branch insn testing the condition code and branching
6229 or not according to its value. For many machines, however,
6230 separating compares and branches is limiting, which is why the
6231 more flexible approach with one @code{define_expand} is used in GCC.
6232 The machine description becomes clearer for architectures that
6233 have compare-and-branch instructions but no condition code. It also
6234 works better when different sets of comparison operators are supported
6235 by different kinds of conditional branches (e.g. integer vs. floating-point),
6236 or by conditional branches with respect to conditional stores.
6238 Two separate insns are always used if the machine description represents
6239 a condition code register using the legacy RTL expression @code{(cc0)},
6240 and on most machines that use a separate condition code register
6241 (@pxref{Condition Code}). For machines that use @code{(cc0)}, in
6242 fact, the set and use of the condition code must be separate and
6243 adjacent@footnote{@code{note} insns can separate them, though.}, thus
6244 allowing flags in @code{cc_status} to be used (@pxref{Condition Code}) and
6245 so that the comparison and branch insns could be located from each other
6246 by using the functions @code{prev_cc0_setter} and @code{next_cc0_user}.
6248 Even in this case having a single entry point for conditional branches
6249 is advantageous, because it handles equally well the case where a single
6250 comparison instruction records the results of both signed and unsigned
6251 comparison of the given operands (with the branch insns coming in distinct
6252 signed and unsigned flavors) as in the x86 or SPARC, and the case where
6253 there are distinct signed and unsigned compare instructions and only
6254 one set of conditional branch instructions as in the PowerPC.
6258 @node Looping Patterns
6259 @section Defining Looping Instruction Patterns
6260 @cindex looping instruction patterns
6261 @cindex defining looping instruction patterns
6263 Some machines have special jump instructions that can be utilized to
6264 make loops more efficient. A common example is the 68000 @samp{dbra}
6265 instruction which performs a decrement of a register and a branch if the
6266 result was greater than zero. Other machines, in particular digital
6267 signal processors (DSPs), have special block repeat instructions to
6268 provide low-overhead loop support. For example, the TI TMS320C3x/C4x
6269 DSPs have a block repeat instruction that loads special registers to
6270 mark the top and end of a loop and to count the number of loop
6271 iterations. This avoids the need for fetching and executing a
6272 @samp{dbra}-like instruction and avoids pipeline stalls associated with
6275 GCC has three special named patterns to support low overhead looping.
6276 They are @samp{decrement_and_branch_until_zero}, @samp{doloop_begin},
6277 and @samp{doloop_end}. The first pattern,
6278 @samp{decrement_and_branch_until_zero}, is not emitted during RTL
6279 generation but may be emitted during the instruction combination phase.
6280 This requires the assistance of the loop optimizer, using information
6281 collected during strength reduction, to reverse a loop to count down to
6282 zero. Some targets also require the loop optimizer to add a
6283 @code{REG_NONNEG} note to indicate that the iteration count is always
6284 positive. This is needed if the target performs a signed loop
6285 termination test. For example, the 68000 uses a pattern similar to the
6286 following for its @code{dbra} instruction:
6290 (define_insn "decrement_and_branch_until_zero"
6293 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6296 (label_ref (match_operand 1 "" ""))
6299 (plus:SI (match_dup 0)
6301 "find_reg_note (insn, REG_NONNEG, 0)"
6306 Note that since the insn is both a jump insn and has an output, it must
6307 deal with its own reloads, hence the `m' constraints. Also note that
6308 since this insn is generated by the instruction combination phase
6309 combining two sequential insns together into an implicit parallel insn,
6310 the iteration counter needs to be biased by the same amount as the
6311 decrement operation, in this case @minus{}1. Note that the following similar
6312 pattern will not be matched by the combiner.
6316 (define_insn "decrement_and_branch_until_zero"
6319 (ge (match_operand:SI 0 "general_operand" "+d*am")
6321 (label_ref (match_operand 1 "" ""))
6324 (plus:SI (match_dup 0)
6326 "find_reg_note (insn, REG_NONNEG, 0)"
6331 The other two special looping patterns, @samp{doloop_begin} and
6332 @samp{doloop_end}, are emitted by the loop optimizer for certain
6333 well-behaved loops with a finite number of loop iterations using
6334 information collected during strength reduction.
6336 The @samp{doloop_end} pattern describes the actual looping instruction
6337 (or the implicit looping operation) and the @samp{doloop_begin} pattern
6338 is an optional companion pattern that can be used for initialization
6339 needed for some low-overhead looping instructions.
6341 Note that some machines require the actual looping instruction to be
6342 emitted at the top of the loop (e.g., the TMS320C3x/C4x DSPs). Emitting
6343 the true RTL for a looping instruction at the top of the loop can cause
6344 problems with flow analysis. So instead, a dummy @code{doloop} insn is
6345 emitted at the end of the loop. The machine dependent reorg pass checks
6346 for the presence of this @code{doloop} insn and then searches back to
6347 the top of the loop, where it inserts the true looping insn (provided
6348 there are no instructions in the loop which would cause problems). Any
6349 additional labels can be emitted at this point. In addition, if the
6350 desired special iteration counter register was not allocated, this
6351 machine dependent reorg pass could emit a traditional compare and jump
6354 The essential difference between the
6355 @samp{decrement_and_branch_until_zero} and the @samp{doloop_end}
6356 patterns is that the loop optimizer allocates an additional pseudo
6357 register for the latter as an iteration counter. This pseudo register
6358 cannot be used within the loop (i.e., general induction variables cannot
6359 be derived from it), however, in many cases the loop induction variable
6360 may become redundant and removed by the flow pass.
6365 @node Insn Canonicalizations
6366 @section Canonicalization of Instructions
6367 @cindex canonicalization of instructions
6368 @cindex insn canonicalization
6370 There are often cases where multiple RTL expressions could represent an
6371 operation performed by a single machine instruction. This situation is
6372 most commonly encountered with logical, branch, and multiply-accumulate
6373 instructions. In such cases, the compiler attempts to convert these
6374 multiple RTL expressions into a single canonical form to reduce the
6375 number of insn patterns required.
6377 In addition to algebraic simplifications, following canonicalizations
6382 For commutative and comparison operators, a constant is always made the
6383 second operand. If a machine only supports a constant as the second
6384 operand, only patterns that match a constant in the second operand need
6388 For associative operators, a sequence of operators will always chain
6389 to the left; for instance, only the left operand of an integer @code{plus}
6390 can itself be a @code{plus}. @code{and}, @code{ior}, @code{xor},
6391 @code{plus}, @code{mult}, @code{smin}, @code{smax}, @code{umin}, and
6392 @code{umax} are associative when applied to integers, and sometimes to
6396 @cindex @code{neg}, canonicalization of
6397 @cindex @code{not}, canonicalization of
6398 @cindex @code{mult}, canonicalization of
6399 @cindex @code{plus}, canonicalization of
6400 @cindex @code{minus}, canonicalization of
6401 For these operators, if only one operand is a @code{neg}, @code{not},
6402 @code{mult}, @code{plus}, or @code{minus} expression, it will be the
6406 In combinations of @code{neg}, @code{mult}, @code{plus}, and
6407 @code{minus}, the @code{neg} operations (if any) will be moved inside
6408 the operations as far as possible. For instance,
6409 @code{(neg (mult A B))} is canonicalized as @code{(mult (neg A) B)}, but
6410 @code{(plus (mult (neg B) C) A)} is canonicalized as
6411 @code{(minus A (mult B C))}.
6413 @cindex @code{compare}, canonicalization of
6415 For the @code{compare} operator, a constant is always the second operand
6416 if the first argument is a condition code register or @code{(cc0)}.
6419 An operand of @code{neg}, @code{not}, @code{mult}, @code{plus}, or
6420 @code{minus} is made the first operand under the same conditions as
6424 @code{(ltu (plus @var{a} @var{b}) @var{b})} is converted to
6425 @code{(ltu (plus @var{a} @var{b}) @var{a})}. Likewise with @code{geu} instead
6429 @code{(minus @var{x} (const_int @var{n}))} is converted to
6430 @code{(plus @var{x} (const_int @var{-n}))}.
6433 Within address computations (i.e., inside @code{mem}), a left shift is
6434 converted into the appropriate multiplication by a power of two.
6436 @cindex @code{ior}, canonicalization of
6437 @cindex @code{and}, canonicalization of
6438 @cindex De Morgan's law
6440 De Morgan's Law is used to move bitwise negation inside a bitwise
6441 logical-and or logical-or operation. If this results in only one
6442 operand being a @code{not} expression, it will be the first one.
6444 A machine that has an instruction that performs a bitwise logical-and of one
6445 operand with the bitwise negation of the other should specify the pattern
6446 for that instruction as
6450 [(set (match_operand:@var{m} 0 @dots{})
6451 (and:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6452 (match_operand:@var{m} 2 @dots{})))]
6458 Similarly, a pattern for a ``NAND'' instruction should be written
6462 [(set (match_operand:@var{m} 0 @dots{})
6463 (ior:@var{m} (not:@var{m} (match_operand:@var{m} 1 @dots{}))
6464 (not:@var{m} (match_operand:@var{m} 2 @dots{}))))]
6469 In both cases, it is not necessary to include patterns for the many
6470 logically equivalent RTL expressions.
6472 @cindex @code{xor}, canonicalization of
6474 The only possible RTL expressions involving both bitwise exclusive-or
6475 and bitwise negation are @code{(xor:@var{m} @var{x} @var{y})}
6476 and @code{(not:@var{m} (xor:@var{m} @var{x} @var{y}))}.
6479 The sum of three items, one of which is a constant, will only appear in
6483 (plus:@var{m} (plus:@var{m} @var{x} @var{y}) @var{constant})
6486 @cindex @code{zero_extract}, canonicalization of
6487 @cindex @code{sign_extract}, canonicalization of
6489 Equality comparisons of a group of bits (usually a single bit) with zero
6490 will be written using @code{zero_extract} rather than the equivalent
6491 @code{and} or @code{sign_extract} operations.
6493 @cindex @code{mult}, canonicalization of
6495 @code{(sign_extend:@var{m1} (mult:@var{m2} (sign_extend:@var{m2} @var{x})
6496 (sign_extend:@var{m2} @var{y})))} is converted to @code{(mult:@var{m1}
6497 (sign_extend:@var{m1} @var{x}) (sign_extend:@var{m1} @var{y}))}, and likewise
6498 for @code{zero_extend}.
6501 @code{(sign_extend:@var{m1} (mult:@var{m2} (ashiftrt:@var{m2}
6502 @var{x} @var{s}) (sign_extend:@var{m2} @var{y})))} is converted
6503 to @code{(mult:@var{m1} (sign_extend:@var{m1} (ashiftrt:@var{m2}
6504 @var{x} @var{s})) (sign_extend:@var{m1} @var{y}))}, and likewise for
6505 patterns using @code{zero_extend} and @code{lshiftrt}. If the second
6506 operand of @code{mult} is also a shift, then that is extended also.
6507 This transformation is only applied when it can be proven that the
6508 original operation had sufficient precision to prevent overflow.
6512 Further canonicalization rules are defined in the function
6513 @code{commutative_operand_precedence} in @file{gcc/rtlanal.c}.
6517 @node Expander Definitions
6518 @section Defining RTL Sequences for Code Generation
6519 @cindex expander definitions
6520 @cindex code generation RTL sequences
6521 @cindex defining RTL sequences for code generation
6523 On some target machines, some standard pattern names for RTL generation
6524 cannot be handled with single insn, but a sequence of RTL insns can
6525 represent them. For these target machines, you can write a
6526 @code{define_expand} to specify how to generate the sequence of RTL@.
6528 @findex define_expand
6529 A @code{define_expand} is an RTL expression that looks almost like a
6530 @code{define_insn}; but, unlike the latter, a @code{define_expand} is used
6531 only for RTL generation and it can produce more than one RTL insn.
6533 A @code{define_expand} RTX has four operands:
6537 The name. Each @code{define_expand} must have a name, since the only
6538 use for it is to refer to it by name.
6541 The RTL template. This is a vector of RTL expressions representing
6542 a sequence of separate instructions. Unlike @code{define_insn}, there
6543 is no implicit surrounding @code{PARALLEL}.
6546 The condition, a string containing a C expression. This expression is
6547 used to express how the availability of this pattern depends on
6548 subclasses of target machine, selected by command-line options when GCC
6549 is run. This is just like the condition of a @code{define_insn} that
6550 has a standard name. Therefore, the condition (if present) may not
6551 depend on the data in the insn being matched, but only the
6552 target-machine-type flags. The compiler needs to test these conditions
6553 during initialization in order to learn exactly which named instructions
6554 are available in a particular run.
6557 The preparation statements, a string containing zero or more C
6558 statements which are to be executed before RTL code is generated from
6561 Usually these statements prepare temporary registers for use as
6562 internal operands in the RTL template, but they can also generate RTL
6563 insns directly by calling routines such as @code{emit_insn}, etc.
6564 Any such insns precede the ones that come from the RTL template.
6567 Every RTL insn emitted by a @code{define_expand} must match some
6568 @code{define_insn} in the machine description. Otherwise, the compiler
6569 will crash when trying to generate code for the insn or trying to optimize
6572 The RTL template, in addition to controlling generation of RTL insns,
6573 also describes the operands that need to be specified when this pattern
6574 is used. In particular, it gives a predicate for each operand.
6576 A true operand, which needs to be specified in order to generate RTL from
6577 the pattern, should be described with a @code{match_operand} in its first
6578 occurrence in the RTL template. This enters information on the operand's
6579 predicate into the tables that record such things. GCC uses the
6580 information to preload the operand into a register if that is required for
6581 valid RTL code. If the operand is referred to more than once, subsequent
6582 references should use @code{match_dup}.
6584 The RTL template may also refer to internal ``operands'' which are
6585 temporary registers or labels used only within the sequence made by the
6586 @code{define_expand}. Internal operands are substituted into the RTL
6587 template with @code{match_dup}, never with @code{match_operand}. The
6588 values of the internal operands are not passed in as arguments by the
6589 compiler when it requests use of this pattern. Instead, they are computed
6590 within the pattern, in the preparation statements. These statements
6591 compute the values and store them into the appropriate elements of
6592 @code{operands} so that @code{match_dup} can find them.
6594 There are two special macros defined for use in the preparation statements:
6595 @code{DONE} and @code{FAIL}. Use them with a following semicolon,
6602 Use the @code{DONE} macro to end RTL generation for the pattern. The
6603 only RTL insns resulting from the pattern on this occasion will be
6604 those already emitted by explicit calls to @code{emit_insn} within the
6605 preparation statements; the RTL template will not be generated.
6609 Make the pattern fail on this occasion. When a pattern fails, it means
6610 that the pattern was not truly available. The calling routines in the
6611 compiler will try other strategies for code generation using other patterns.
6613 Failure is currently supported only for binary (addition, multiplication,
6614 shifting, etc.) and bit-field (@code{extv}, @code{extzv}, and @code{insv})
6618 If the preparation falls through (invokes neither @code{DONE} nor
6619 @code{FAIL}), then the @code{define_expand} acts like a
6620 @code{define_insn} in that the RTL template is used to generate the
6623 The RTL template is not used for matching, only for generating the
6624 initial insn list. If the preparation statement always invokes
6625 @code{DONE} or @code{FAIL}, the RTL template may be reduced to a simple
6626 list of operands, such as this example:
6630 (define_expand "addsi3"
6631 [(match_operand:SI 0 "register_operand" "")
6632 (match_operand:SI 1 "register_operand" "")
6633 (match_operand:SI 2 "register_operand" "")]
6639 handle_add (operands[0], operands[1], operands[2]);
6645 Here is an example, the definition of left-shift for the SPUR chip:
6649 (define_expand "ashlsi3"
6650 [(set (match_operand:SI 0 "register_operand" "")
6654 (match_operand:SI 1 "register_operand" "")
6655 (match_operand:SI 2 "nonmemory_operand" "")))]
6664 if (GET_CODE (operands[2]) != CONST_INT
6665 || (unsigned) INTVAL (operands[2]) > 3)
6672 This example uses @code{define_expand} so that it can generate an RTL insn
6673 for shifting when the shift-count is in the supported range of 0 to 3 but
6674 fail in other cases where machine insns aren't available. When it fails,
6675 the compiler tries another strategy using different patterns (such as, a
6678 If the compiler were able to handle nontrivial condition-strings in
6679 patterns with names, then it would be possible to use a
6680 @code{define_insn} in that case. Here is another case (zero-extension
6681 on the 68000) which makes more use of the power of @code{define_expand}:
6684 (define_expand "zero_extendhisi2"
6685 [(set (match_operand:SI 0 "general_operand" "")
6687 (set (strict_low_part
6691 (match_operand:HI 1 "general_operand" ""))]
6693 "operands[1] = make_safe_from (operands[1], operands[0]);")
6697 @findex make_safe_from
6698 Here two RTL insns are generated, one to clear the entire output operand
6699 and the other to copy the input operand into its low half. This sequence
6700 is incorrect if the input operand refers to [the old value of] the output
6701 operand, so the preparation statement makes sure this isn't so. The
6702 function @code{make_safe_from} copies the @code{operands[1]} into a
6703 temporary register if it refers to @code{operands[0]}. It does this
6704 by emitting another RTL insn.
6706 Finally, a third example shows the use of an internal operand.
6707 Zero-extension on the SPUR chip is done by @code{and}-ing the result
6708 against a halfword mask. But this mask cannot be represented by a
6709 @code{const_int} because the constant value is too large to be legitimate
6710 on this machine. So it must be copied into a register with
6711 @code{force_reg} and then the register used in the @code{and}.
6714 (define_expand "zero_extendhisi2"
6715 [(set (match_operand:SI 0 "register_operand" "")
6717 (match_operand:HI 1 "register_operand" "")
6722 = force_reg (SImode, GEN_INT (65535)); ")
6725 @emph{Note:} If the @code{define_expand} is used to serve a
6726 standard binary or unary arithmetic operation or a bit-field operation,
6727 then the last insn it generates must not be a @code{code_label},
6728 @code{barrier} or @code{note}. It must be an @code{insn},
6729 @code{jump_insn} or @code{call_insn}. If you don't need a real insn
6730 at the end, emit an insn to copy the result of the operation into
6731 itself. Such an insn will generate no code, but it can avoid problems
6736 @node Insn Splitting
6737 @section Defining How to Split Instructions
6738 @cindex insn splitting
6739 @cindex instruction splitting
6740 @cindex splitting instructions
6742 There are two cases where you should specify how to split a pattern
6743 into multiple insns. On machines that have instructions requiring
6744 delay slots (@pxref{Delay Slots}) or that have instructions whose
6745 output is not available for multiple cycles (@pxref{Processor pipeline
6746 description}), the compiler phases that optimize these cases need to
6747 be able to move insns into one-instruction delay slots. However, some
6748 insns may generate more than one machine instruction. These insns
6749 cannot be placed into a delay slot.
6751 Often you can rewrite the single insn as a list of individual insns,
6752 each corresponding to one machine instruction. The disadvantage of
6753 doing so is that it will cause the compilation to be slower and require
6754 more space. If the resulting insns are too complex, it may also
6755 suppress some optimizations. The compiler splits the insn if there is a
6756 reason to believe that it might improve instruction or delay slot
6759 The insn combiner phase also splits putative insns. If three insns are
6760 merged into one insn with a complex expression that cannot be matched by
6761 some @code{define_insn} pattern, the combiner phase attempts to split
6762 the complex pattern into two insns that are recognized. Usually it can
6763 break the complex pattern into two patterns by splitting out some
6764 subexpression. However, in some other cases, such as performing an
6765 addition of a large constant in two insns on a RISC machine, the way to
6766 split the addition into two insns is machine-dependent.
6768 @findex define_split
6769 The @code{define_split} definition tells the compiler how to split a
6770 complex insn into several simpler insns. It looks like this:
6774 [@var{insn-pattern}]
6776 [@var{new-insn-pattern-1}
6777 @var{new-insn-pattern-2}
6779 "@var{preparation-statements}")
6782 @var{insn-pattern} is a pattern that needs to be split and
6783 @var{condition} is the final condition to be tested, as in a
6784 @code{define_insn}. When an insn matching @var{insn-pattern} and
6785 satisfying @var{condition} is found, it is replaced in the insn list
6786 with the insns given by @var{new-insn-pattern-1},
6787 @var{new-insn-pattern-2}, etc.
6789 The @var{preparation-statements} are similar to those statements that
6790 are specified for @code{define_expand} (@pxref{Expander Definitions})
6791 and are executed before the new RTL is generated to prepare for the
6792 generated code or emit some insns whose pattern is not fixed. Unlike
6793 those in @code{define_expand}, however, these statements must not
6794 generate any new pseudo-registers. Once reload has completed, they also
6795 must not allocate any space in the stack frame.
6797 Patterns are matched against @var{insn-pattern} in two different
6798 circumstances. If an insn needs to be split for delay slot scheduling
6799 or insn scheduling, the insn is already known to be valid, which means
6800 that it must have been matched by some @code{define_insn} and, if
6801 @code{reload_completed} is nonzero, is known to satisfy the constraints
6802 of that @code{define_insn}. In that case, the new insn patterns must
6803 also be insns that are matched by some @code{define_insn} and, if
6804 @code{reload_completed} is nonzero, must also satisfy the constraints
6805 of those definitions.
6807 As an example of this usage of @code{define_split}, consider the following
6808 example from @file{a29k.md}, which splits a @code{sign_extend} from
6809 @code{HImode} to @code{SImode} into a pair of shift insns:
6813 [(set (match_operand:SI 0 "gen_reg_operand" "")
6814 (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
6817 (ashift:SI (match_dup 1)
6820 (ashiftrt:SI (match_dup 0)
6823 @{ operands[1] = gen_lowpart (SImode, operands[1]); @}")
6826 When the combiner phase tries to split an insn pattern, it is always the
6827 case that the pattern is @emph{not} matched by any @code{define_insn}.
6828 The combiner pass first tries to split a single @code{set} expression
6829 and then the same @code{set} expression inside a @code{parallel}, but
6830 followed by a @code{clobber} of a pseudo-reg to use as a scratch
6831 register. In these cases, the combiner expects exactly two new insn
6832 patterns to be generated. It will verify that these patterns match some
6833 @code{define_insn} definitions, so you need not do this test in the
6834 @code{define_split} (of course, there is no point in writing a
6835 @code{define_split} that will never produce insns that match).
6837 Here is an example of this use of @code{define_split}, taken from
6842 [(set (match_operand:SI 0 "gen_reg_operand" "")
6843 (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
6844 (match_operand:SI 2 "non_add_cint_operand" "")))]
6846 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
6847 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
6850 int low = INTVAL (operands[2]) & 0xffff;
6851 int high = (unsigned) INTVAL (operands[2]) >> 16;
6854 high++, low |= 0xffff0000;
6856 operands[3] = GEN_INT (high << 16);
6857 operands[4] = GEN_INT (low);
6861 Here the predicate @code{non_add_cint_operand} matches any
6862 @code{const_int} that is @emph{not} a valid operand of a single add
6863 insn. The add with the smaller displacement is written so that it
6864 can be substituted into the address of a subsequent operation.
6866 An example that uses a scratch register, from the same file, generates
6867 an equality comparison of a register and a large constant:
6871 [(set (match_operand:CC 0 "cc_reg_operand" "")
6872 (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
6873 (match_operand:SI 2 "non_short_cint_operand" "")))
6874 (clobber (match_operand:SI 3 "gen_reg_operand" ""))]
6875 "find_single_use (operands[0], insn, 0)
6876 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
6877 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
6878 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
6879 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
6882 /* @r{Get the constant we are comparing against, C, and see what it
6883 looks like sign-extended to 16 bits. Then see what constant
6884 could be XOR'ed with C to get the sign-extended value.} */
6886 int c = INTVAL (operands[2]);
6887 int sextc = (c << 16) >> 16;
6888 int xorv = c ^ sextc;
6890 operands[4] = GEN_INT (xorv);
6891 operands[5] = GEN_INT (sextc);
6895 To avoid confusion, don't write a single @code{define_split} that
6896 accepts some insns that match some @code{define_insn} as well as some
6897 insns that don't. Instead, write two separate @code{define_split}
6898 definitions, one for the insns that are valid and one for the insns that
6901 The splitter is allowed to split jump instructions into sequence of
6902 jumps or create new jumps in while splitting non-jump instructions. As
6903 the central flowgraph and branch prediction information needs to be updated,
6904 several restriction apply.
6906 Splitting of jump instruction into sequence that over by another jump
6907 instruction is always valid, as compiler expect identical behavior of new
6908 jump. When new sequence contains multiple jump instructions or new labels,
6909 more assistance is needed. Splitter is required to create only unconditional
6910 jumps, or simple conditional jump instructions. Additionally it must attach a
6911 @code{REG_BR_PROB} note to each conditional jump. A global variable
6912 @code{split_branch_probability} holds the probability of the original branch in case
6913 it was a simple conditional jump, @minus{}1 otherwise. To simplify
6914 recomputing of edge frequencies, the new sequence is required to have only
6915 forward jumps to the newly created labels.
6917 @findex define_insn_and_split
6918 For the common case where the pattern of a define_split exactly matches the
6919 pattern of a define_insn, use @code{define_insn_and_split}. It looks like
6923 (define_insn_and_split
6924 [@var{insn-pattern}]
6926 "@var{output-template}"
6927 "@var{split-condition}"
6928 [@var{new-insn-pattern-1}
6929 @var{new-insn-pattern-2}
6931 "@var{preparation-statements}"
6932 [@var{insn-attributes}])
6936 @var{insn-pattern}, @var{condition}, @var{output-template}, and
6937 @var{insn-attributes} are used as in @code{define_insn}. The
6938 @var{new-insn-pattern} vector and the @var{preparation-statements} are used as
6939 in a @code{define_split}. The @var{split-condition} is also used as in
6940 @code{define_split}, with the additional behavior that if the condition starts
6941 with @samp{&&}, the condition used for the split will be the constructed as a
6942 logical ``and'' of the split condition with the insn condition. For example,
6946 (define_insn_and_split "zero_extendhisi2_and"
6947 [(set (match_operand:SI 0 "register_operand" "=r")
6948 (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
6949 (clobber (reg:CC 17))]
6950 "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
6952 "&& reload_completed"
6953 [(parallel [(set (match_dup 0)
6954 (and:SI (match_dup 0) (const_int 65535)))
6955 (clobber (reg:CC 17))])]
6957 [(set_attr "type" "alu1")])
6961 In this case, the actual split condition will be
6962 @samp{TARGET_ZERO_EXTEND_WITH_AND && !optimize_size && reload_completed}.
6964 The @code{define_insn_and_split} construction provides exactly the same
6965 functionality as two separate @code{define_insn} and @code{define_split}
6966 patterns. It exists for compactness, and as a maintenance tool to prevent
6967 having to ensure the two patterns' templates match.
6971 @node Including Patterns
6972 @section Including Patterns in Machine Descriptions.
6973 @cindex insn includes
6976 The @code{include} pattern tells the compiler tools where to
6977 look for patterns that are in files other than in the file
6978 @file{.md}. This is used only at build time and there is no preprocessing allowed.
6992 (include "filestuff")
6996 Where @var{pathname} is a string that specifies the location of the file,
6997 specifies the include file to be in @file{gcc/config/target/filestuff}. The
6998 directory @file{gcc/config/target} is regarded as the default directory.
7001 Machine descriptions may be split up into smaller more manageable subsections
7002 and placed into subdirectories.
7008 (include "BOGUS/filestuff")
7012 the include file is specified to be in @file{gcc/config/@var{target}/BOGUS/filestuff}.
7014 Specifying an absolute path for the include file such as;
7017 (include "/u2/BOGUS/filestuff")
7020 is permitted but is not encouraged.
7022 @subsection RTL Generation Tool Options for Directory Search
7023 @cindex directory options .md
7024 @cindex options, directory search
7025 @cindex search options
7027 The @option{-I@var{dir}} option specifies directories to search for machine descriptions.
7032 genrecog -I/p1/abc/proc1 -I/p2/abcd/pro2 target.md
7037 Add the directory @var{dir} to the head of the list of directories to be
7038 searched for header files. This can be used to override a system machine definition
7039 file, substituting your own version, since these directories are
7040 searched before the default machine description file directories. If you use more than
7041 one @option{-I} option, the directories are scanned in left-to-right
7042 order; the standard default directory come after.
7047 @node Peephole Definitions
7048 @section Machine-Specific Peephole Optimizers
7049 @cindex peephole optimizer definitions
7050 @cindex defining peephole optimizers
7052 In addition to instruction patterns the @file{md} file may contain
7053 definitions of machine-specific peephole optimizations.
7055 The combiner does not notice certain peephole optimizations when the data
7056 flow in the program does not suggest that it should try them. For example,
7057 sometimes two consecutive insns related in purpose can be combined even
7058 though the second one does not appear to use a register computed in the
7059 first one. A machine-specific peephole optimizer can detect such
7062 There are two forms of peephole definitions that may be used. The
7063 original @code{define_peephole} is run at assembly output time to
7064 match insns and substitute assembly text. Use of @code{define_peephole}
7067 A newer @code{define_peephole2} matches insns and substitutes new
7068 insns. The @code{peephole2} pass is run after register allocation
7069 but before scheduling, which may result in much better code for
7070 targets that do scheduling.
7073 * define_peephole:: RTL to Text Peephole Optimizers
7074 * define_peephole2:: RTL to RTL Peephole Optimizers
7079 @node define_peephole
7080 @subsection RTL to Text Peephole Optimizers
7081 @findex define_peephole
7084 A definition looks like this:
7088 [@var{insn-pattern-1}
7089 @var{insn-pattern-2}
7093 "@var{optional-insn-attributes}")
7097 The last string operand may be omitted if you are not using any
7098 machine-specific information in this machine description. If present,
7099 it must obey the same rules as in a @code{define_insn}.
7101 In this skeleton, @var{insn-pattern-1} and so on are patterns to match
7102 consecutive insns. The optimization applies to a sequence of insns when
7103 @var{insn-pattern-1} matches the first one, @var{insn-pattern-2} matches
7104 the next, and so on.
7106 Each of the insns matched by a peephole must also match a
7107 @code{define_insn}. Peepholes are checked only at the last stage just
7108 before code generation, and only optionally. Therefore, any insn which
7109 would match a peephole but no @code{define_insn} will cause a crash in code
7110 generation in an unoptimized compilation, or at various optimization
7113 The operands of the insns are matched with @code{match_operands},
7114 @code{match_operator}, and @code{match_dup}, as usual. What is not
7115 usual is that the operand numbers apply to all the insn patterns in the
7116 definition. So, you can check for identical operands in two insns by
7117 using @code{match_operand} in one insn and @code{match_dup} in the
7120 The operand constraints used in @code{match_operand} patterns do not have
7121 any direct effect on the applicability of the peephole, but they will
7122 be validated afterward, so make sure your constraints are general enough
7123 to apply whenever the peephole matches. If the peephole matches
7124 but the constraints are not satisfied, the compiler will crash.
7126 It is safe to omit constraints in all the operands of the peephole; or
7127 you can write constraints which serve as a double-check on the criteria
7130 Once a sequence of insns matches the patterns, the @var{condition} is
7131 checked. This is a C expression which makes the final decision whether to
7132 perform the optimization (we do so if the expression is nonzero). If
7133 @var{condition} is omitted (in other words, the string is empty) then the
7134 optimization is applied to every sequence of insns that matches the
7137 The defined peephole optimizations are applied after register allocation
7138 is complete. Therefore, the peephole definition can check which
7139 operands have ended up in which kinds of registers, just by looking at
7142 @findex prev_active_insn
7143 The way to refer to the operands in @var{condition} is to write
7144 @code{operands[@var{i}]} for operand number @var{i} (as matched by
7145 @code{(match_operand @var{i} @dots{})}). Use the variable @code{insn}
7146 to refer to the last of the insns being matched; use
7147 @code{prev_active_insn} to find the preceding insns.
7149 @findex dead_or_set_p
7150 When optimizing computations with intermediate results, you can use
7151 @var{condition} to match only when the intermediate results are not used
7152 elsewhere. Use the C expression @code{dead_or_set_p (@var{insn},
7153 @var{op})}, where @var{insn} is the insn in which you expect the value
7154 to be used for the last time (from the value of @code{insn}, together
7155 with use of @code{prev_nonnote_insn}), and @var{op} is the intermediate
7156 value (from @code{operands[@var{i}]}).
7158 Applying the optimization means replacing the sequence of insns with one
7159 new insn. The @var{template} controls ultimate output of assembler code
7160 for this combined insn. It works exactly like the template of a
7161 @code{define_insn}. Operand numbers in this template are the same ones
7162 used in matching the original sequence of insns.
7164 The result of a defined peephole optimizer does not need to match any of
7165 the insn patterns in the machine description; it does not even have an
7166 opportunity to match them. The peephole optimizer definition itself serves
7167 as the insn pattern to control how the insn is output.
7169 Defined peephole optimizers are run as assembler code is being output,
7170 so the insns they produce are never combined or rearranged in any way.
7172 Here is an example, taken from the 68000 machine description:
7176 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7177 (set (match_operand:DF 0 "register_operand" "=f")
7178 (match_operand:DF 1 "register_operand" "ad"))]
7179 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7182 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7184 output_asm_insn ("move.l %1,(sp)", xoperands);
7185 output_asm_insn ("move.l %1,-(sp)", operands);
7186 return "fmove.d (sp)+,%0";
7188 output_asm_insn ("movel %1,sp@@", xoperands);
7189 output_asm_insn ("movel %1,sp@@-", operands);
7190 return "fmoved sp@@+,%0";
7196 The effect of this optimization is to change
7222 If a peephole matches a sequence including one or more jump insns, you must
7223 take account of the flags such as @code{CC_REVERSED} which specify that the
7224 condition codes are represented in an unusual manner. The compiler
7225 automatically alters any ordinary conditional jumps which occur in such
7226 situations, but the compiler cannot alter jumps which have been replaced by
7227 peephole optimizations. So it is up to you to alter the assembler code
7228 that the peephole produces. Supply C code to write the assembler output,
7229 and in this C code check the condition code status flags and change the
7230 assembler code as appropriate.
7233 @var{insn-pattern-1} and so on look @emph{almost} like the second
7234 operand of @code{define_insn}. There is one important difference: the
7235 second operand of @code{define_insn} consists of one or more RTX's
7236 enclosed in square brackets. Usually, there is only one: then the same
7237 action can be written as an element of a @code{define_peephole}. But
7238 when there are multiple actions in a @code{define_insn}, they are
7239 implicitly enclosed in a @code{parallel}. Then you must explicitly
7240 write the @code{parallel}, and the square brackets within it, in the
7241 @code{define_peephole}. Thus, if an insn pattern looks like this,
7244 (define_insn "divmodsi4"
7245 [(set (match_operand:SI 0 "general_operand" "=d")
7246 (div:SI (match_operand:SI 1 "general_operand" "0")
7247 (match_operand:SI 2 "general_operand" "dmsK")))
7248 (set (match_operand:SI 3 "general_operand" "=d")
7249 (mod:SI (match_dup 1) (match_dup 2)))]
7251 "divsl%.l %2,%3:%0")
7255 then the way to mention this insn in a peephole is as follows:
7261 [(set (match_operand:SI 0 "general_operand" "=d")
7262 (div:SI (match_operand:SI 1 "general_operand" "0")
7263 (match_operand:SI 2 "general_operand" "dmsK")))
7264 (set (match_operand:SI 3 "general_operand" "=d")
7265 (mod:SI (match_dup 1) (match_dup 2)))])
7272 @node define_peephole2
7273 @subsection RTL to RTL Peephole Optimizers
7274 @findex define_peephole2
7276 The @code{define_peephole2} definition tells the compiler how to
7277 substitute one sequence of instructions for another sequence,
7278 what additional scratch registers may be needed and what their
7283 [@var{insn-pattern-1}
7284 @var{insn-pattern-2}
7287 [@var{new-insn-pattern-1}
7288 @var{new-insn-pattern-2}
7290 "@var{preparation-statements}")
7293 The definition is almost identical to @code{define_split}
7294 (@pxref{Insn Splitting}) except that the pattern to match is not a
7295 single instruction, but a sequence of instructions.
7297 It is possible to request additional scratch registers for use in the
7298 output template. If appropriate registers are not free, the pattern
7299 will simply not match.
7301 @findex match_scratch
7303 Scratch registers are requested with a @code{match_scratch} pattern at
7304 the top level of the input pattern. The allocated register (initially) will
7305 be dead at the point requested within the original sequence. If the scratch
7306 is used at more than a single point, a @code{match_dup} pattern at the
7307 top level of the input pattern marks the last position in the input sequence
7308 at which the register must be available.
7310 Here is an example from the IA-32 machine description:
7314 [(match_scratch:SI 2 "r")
7315 (parallel [(set (match_operand:SI 0 "register_operand" "")
7316 (match_operator:SI 3 "arith_or_logical_operator"
7318 (match_operand:SI 1 "memory_operand" "")]))
7319 (clobber (reg:CC 17))])]
7320 "! optimize_size && ! TARGET_READ_MODIFY"
7321 [(set (match_dup 2) (match_dup 1))
7322 (parallel [(set (match_dup 0)
7323 (match_op_dup 3 [(match_dup 0) (match_dup 2)]))
7324 (clobber (reg:CC 17))])]
7329 This pattern tries to split a load from its use in the hopes that we'll be
7330 able to schedule around the memory load latency. It allocates a single
7331 @code{SImode} register of class @code{GENERAL_REGS} (@code{"r"}) that needs
7332 to be live only at the point just before the arithmetic.
7334 A real example requiring extended scratch lifetimes is harder to come by,
7335 so here's a silly made-up example:
7339 [(match_scratch:SI 4 "r")
7340 (set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
7341 (set (match_operand:SI 2 "" "") (match_dup 1))
7343 (set (match_operand:SI 3 "" "") (match_dup 1))]
7344 "/* @r{determine 1 does not overlap 0 and 2} */"
7345 [(set (match_dup 4) (match_dup 1))
7346 (set (match_dup 0) (match_dup 4))
7347 (set (match_dup 2) (match_dup 4))]
7348 (set (match_dup 3) (match_dup 4))]
7353 If we had not added the @code{(match_dup 4)} in the middle of the input
7354 sequence, it might have been the case that the register we chose at the
7355 beginning of the sequence is killed by the first or second @code{set}.
7359 @node Insn Attributes
7360 @section Instruction Attributes
7361 @cindex insn attributes
7362 @cindex instruction attributes
7364 In addition to describing the instruction supported by the target machine,
7365 the @file{md} file also defines a group of @dfn{attributes} and a set of
7366 values for each. Every generated insn is assigned a value for each attribute.
7367 One possible attribute would be the effect that the insn has on the machine's
7368 condition code. This attribute can then be used by @code{NOTICE_UPDATE_CC}
7369 to track the condition codes.
7372 * Defining Attributes:: Specifying attributes and their values.
7373 * Expressions:: Valid expressions for attribute values.
7374 * Tagging Insns:: Assigning attribute values to insns.
7375 * Attr Example:: An example of assigning attributes.
7376 * Insn Lengths:: Computing the length of insns.
7377 * Constant Attributes:: Defining attributes that are constant.
7378 * Delay Slots:: Defining delay slots required for a machine.
7379 * Processor pipeline description:: Specifying information for insn scheduling.
7384 @node Defining Attributes
7385 @subsection Defining Attributes and their Values
7386 @cindex defining attributes and their values
7387 @cindex attributes, defining
7390 The @code{define_attr} expression is used to define each attribute required
7391 by the target machine. It looks like:
7394 (define_attr @var{name} @var{list-of-values} @var{default})
7397 @var{name} is a string specifying the name of the attribute being defined.
7398 Some attributes are used in a special way by the rest of the compiler. The
7399 @code{enabled} attribute can be used to conditionally enable or disable
7400 insn alternatives (@pxref{Disable Insn Alternatives}). The @code{predicable}
7401 attribute, together with a suitable @code{define_cond_exec}
7402 (@pxref{Conditional Execution}), can be used to automatically generate
7403 conditional variants of instruction patterns. The compiler internally uses
7404 the names @code{ce_enabled} and @code{nonce_enabled}, so they should not be
7405 used elsewhere as alternative names.
7407 @var{list-of-values} is either a string that specifies a comma-separated
7408 list of values that can be assigned to the attribute, or a null string to
7409 indicate that the attribute takes numeric values.
7411 @var{default} is an attribute expression that gives the value of this
7412 attribute for insns that match patterns whose definition does not include
7413 an explicit value for this attribute. @xref{Attr Example}, for more
7414 information on the handling of defaults. @xref{Constant Attributes},
7415 for information on attributes that do not depend on any particular insn.
7418 For each defined attribute, a number of definitions are written to the
7419 @file{insn-attr.h} file. For cases where an explicit set of values is
7420 specified for an attribute, the following are defined:
7424 A @samp{#define} is written for the symbol @samp{HAVE_ATTR_@var{name}}.
7427 An enumerated class is defined for @samp{attr_@var{name}} with
7428 elements of the form @samp{@var{upper-name}_@var{upper-value}} where
7429 the attribute name and value are first converted to uppercase.
7432 A function @samp{get_attr_@var{name}} is defined that is passed an insn and
7433 returns the attribute value for that insn.
7436 For example, if the following is present in the @file{md} file:
7439 (define_attr "type" "branch,fp,load,store,arith" @dots{})
7443 the following lines will be written to the file @file{insn-attr.h}.
7446 #define HAVE_ATTR_type
7447 enum attr_type @{TYPE_BRANCH, TYPE_FP, TYPE_LOAD,
7448 TYPE_STORE, TYPE_ARITH@};
7449 extern enum attr_type get_attr_type ();
7452 If the attribute takes numeric values, no @code{enum} type will be
7453 defined and the function to obtain the attribute's value will return
7456 There are attributes which are tied to a specific meaning. These
7457 attributes are not free to use for other purposes:
7461 The @code{length} attribute is used to calculate the length of emitted
7462 code chunks. This is especially important when verifying branch
7463 distances. @xref{Insn Lengths}.
7466 The @code{enabled} attribute can be defined to prevent certain
7467 alternatives of an insn definition from being used during code
7468 generation. @xref{Disable Insn Alternatives}.
7471 @findex define_enum_attr
7472 @anchor{define_enum_attr}
7473 Another way of defining an attribute is to use:
7476 (define_enum_attr "@var{attr}" "@var{enum}" @var{default})
7479 This works in just the same way as @code{define_attr}, except that
7480 the list of values is taken from a separate enumeration called
7481 @var{enum} (@pxref{define_enum}). This form allows you to use
7482 the same list of values for several attributes without having to
7483 repeat the list each time. For example:
7486 (define_enum "processor" [
7491 (define_enum_attr "arch" "processor"
7492 (const (symbol_ref "target_arch")))
7493 (define_enum_attr "tune" "processor"
7494 (const (symbol_ref "target_tune")))
7497 defines the same attributes as:
7500 (define_attr "arch" "model_a,model_b,@dots{}"
7501 (const (symbol_ref "target_arch")))
7502 (define_attr "tune" "model_a,model_b,@dots{}"
7503 (const (symbol_ref "target_tune")))
7506 but without duplicating the processor list. The second example defines two
7507 separate C enums (@code{attr_arch} and @code{attr_tune}) whereas the first
7508 defines a single C enum (@code{processor}).
7512 @subsection Attribute Expressions
7513 @cindex attribute expressions
7515 RTL expressions used to define attributes use the codes described above
7516 plus a few specific to attribute definitions, to be discussed below.
7517 Attribute value expressions must have one of the following forms:
7520 @cindex @code{const_int} and attributes
7521 @item (const_int @var{i})
7522 The integer @var{i} specifies the value of a numeric attribute. @var{i}
7523 must be non-negative.
7525 The value of a numeric attribute can be specified either with a
7526 @code{const_int}, or as an integer represented as a string in
7527 @code{const_string}, @code{eq_attr} (see below), @code{attr},
7528 @code{symbol_ref}, simple arithmetic expressions, and @code{set_attr}
7529 overrides on specific instructions (@pxref{Tagging Insns}).
7531 @cindex @code{const_string} and attributes
7532 @item (const_string @var{value})
7533 The string @var{value} specifies a constant attribute value.
7534 If @var{value} is specified as @samp{"*"}, it means that the default value of
7535 the attribute is to be used for the insn containing this expression.
7536 @samp{"*"} obviously cannot be used in the @var{default} expression
7537 of a @code{define_attr}.
7539 If the attribute whose value is being specified is numeric, @var{value}
7540 must be a string containing a non-negative integer (normally
7541 @code{const_int} would be used in this case). Otherwise, it must
7542 contain one of the valid values for the attribute.
7544 @cindex @code{if_then_else} and attributes
7545 @item (if_then_else @var{test} @var{true-value} @var{false-value})
7546 @var{test} specifies an attribute test, whose format is defined below.
7547 The value of this expression is @var{true-value} if @var{test} is true,
7548 otherwise it is @var{false-value}.
7550 @cindex @code{cond} and attributes
7551 @item (cond [@var{test1} @var{value1} @dots{}] @var{default})
7552 The first operand of this expression is a vector containing an even
7553 number of expressions and consisting of pairs of @var{test} and @var{value}
7554 expressions. The value of the @code{cond} expression is that of the
7555 @var{value} corresponding to the first true @var{test} expression. If
7556 none of the @var{test} expressions are true, the value of the @code{cond}
7557 expression is that of the @var{default} expression.
7560 @var{test} expressions can have one of the following forms:
7563 @cindex @code{const_int} and attribute tests
7564 @item (const_int @var{i})
7565 This test is true if @var{i} is nonzero and false otherwise.
7567 @cindex @code{not} and attributes
7568 @cindex @code{ior} and attributes
7569 @cindex @code{and} and attributes
7570 @item (not @var{test})
7571 @itemx (ior @var{test1} @var{test2})
7572 @itemx (and @var{test1} @var{test2})
7573 These tests are true if the indicated logical function is true.
7575 @cindex @code{match_operand} and attributes
7576 @item (match_operand:@var{m} @var{n} @var{pred} @var{constraints})
7577 This test is true if operand @var{n} of the insn whose attribute value
7578 is being determined has mode @var{m} (this part of the test is ignored
7579 if @var{m} is @code{VOIDmode}) and the function specified by the string
7580 @var{pred} returns a nonzero value when passed operand @var{n} and mode
7581 @var{m} (this part of the test is ignored if @var{pred} is the null
7584 The @var{constraints} operand is ignored and should be the null string.
7586 @cindex @code{match_test} and attributes
7587 @item (match_test @var{c-expr})
7588 The test is true if C expression @var{c-expr} is true. In non-constant
7589 attributes, @var{c-expr} has access to the following variables:
7593 The rtl instruction under test.
7594 @item which_alternative
7595 The @code{define_insn} alternative that @var{insn} matches.
7596 @xref{Output Statement}.
7598 An array of @var{insn}'s rtl operands.
7601 @var{c-expr} behaves like the condition in a C @code{if} statement,
7602 so there is no need to explicitly convert the expression into a boolean
7603 0 or 1 value. For example, the following two tests are equivalent:
7606 (match_test "x & 2")
7607 (match_test "(x & 2) != 0")
7610 @cindex @code{le} and attributes
7611 @cindex @code{leu} and attributes
7612 @cindex @code{lt} and attributes
7613 @cindex @code{gt} and attributes
7614 @cindex @code{gtu} and attributes
7615 @cindex @code{ge} and attributes
7616 @cindex @code{geu} and attributes
7617 @cindex @code{ne} and attributes
7618 @cindex @code{eq} and attributes
7619 @cindex @code{plus} and attributes
7620 @cindex @code{minus} and attributes
7621 @cindex @code{mult} and attributes
7622 @cindex @code{div} and attributes
7623 @cindex @code{mod} and attributes
7624 @cindex @code{abs} and attributes
7625 @cindex @code{neg} and attributes
7626 @cindex @code{ashift} and attributes
7627 @cindex @code{lshiftrt} and attributes
7628 @cindex @code{ashiftrt} and attributes
7629 @item (le @var{arith1} @var{arith2})
7630 @itemx (leu @var{arith1} @var{arith2})
7631 @itemx (lt @var{arith1} @var{arith2})
7632 @itemx (ltu @var{arith1} @var{arith2})
7633 @itemx (gt @var{arith1} @var{arith2})
7634 @itemx (gtu @var{arith1} @var{arith2})
7635 @itemx (ge @var{arith1} @var{arith2})
7636 @itemx (geu @var{arith1} @var{arith2})
7637 @itemx (ne @var{arith1} @var{arith2})
7638 @itemx (eq @var{arith1} @var{arith2})
7639 These tests are true if the indicated comparison of the two arithmetic
7640 expressions is true. Arithmetic expressions are formed with
7641 @code{plus}, @code{minus}, @code{mult}, @code{div}, @code{mod},
7642 @code{abs}, @code{neg}, @code{and}, @code{ior}, @code{xor}, @code{not},
7643 @code{ashift}, @code{lshiftrt}, and @code{ashiftrt} expressions.
7646 @code{const_int} and @code{symbol_ref} are always valid terms (@pxref{Insn
7647 Lengths},for additional forms). @code{symbol_ref} is a string
7648 denoting a C expression that yields an @code{int} when evaluated by the
7649 @samp{get_attr_@dots{}} routine. It should normally be a global
7653 @item (eq_attr @var{name} @var{value})
7654 @var{name} is a string specifying the name of an attribute.
7656 @var{value} is a string that is either a valid value for attribute
7657 @var{name}, a comma-separated list of values, or @samp{!} followed by a
7658 value or list. If @var{value} does not begin with a @samp{!}, this
7659 test is true if the value of the @var{name} attribute of the current
7660 insn is in the list specified by @var{value}. If @var{value} begins
7661 with a @samp{!}, this test is true if the attribute's value is
7662 @emph{not} in the specified list.
7667 (eq_attr "type" "load,store")
7674 (ior (eq_attr "type" "load") (eq_attr "type" "store"))
7677 If @var{name} specifies an attribute of @samp{alternative}, it refers to the
7678 value of the compiler variable @code{which_alternative}
7679 (@pxref{Output Statement}) and the values must be small integers. For
7683 (eq_attr "alternative" "2,3")
7690 (ior (eq (symbol_ref "which_alternative") (const_int 2))
7691 (eq (symbol_ref "which_alternative") (const_int 3)))
7694 Note that, for most attributes, an @code{eq_attr} test is simplified in cases
7695 where the value of the attribute being tested is known for all insns matching
7696 a particular pattern. This is by far the most common case.
7699 @item (attr_flag @var{name})
7700 The value of an @code{attr_flag} expression is true if the flag
7701 specified by @var{name} is true for the @code{insn} currently being
7704 @var{name} is a string specifying one of a fixed set of flags to test.
7705 Test the flags @code{forward} and @code{backward} to determine the
7706 direction of a conditional branch. Test the flags @code{very_likely},
7707 @code{likely}, @code{very_unlikely}, and @code{unlikely} to determine
7708 if a conditional branch is expected to be taken.
7710 If the @code{very_likely} flag is true, then the @code{likely} flag is also
7711 true. Likewise for the @code{very_unlikely} and @code{unlikely} flags.
7713 This example describes a conditional branch delay slot which
7714 can be nullified for forward branches that are taken (annul-true) or
7715 for backward branches which are not taken (annul-false).
7718 (define_delay (eq_attr "type" "cbranch")
7719 [(eq_attr "in_branch_delay" "true")
7720 (and (eq_attr "in_branch_delay" "true")
7721 (attr_flag "forward"))
7722 (and (eq_attr "in_branch_delay" "true")
7723 (attr_flag "backward"))])
7726 The @code{forward} and @code{backward} flags are false if the current
7727 @code{insn} being scheduled is not a conditional branch.
7729 The @code{very_likely} and @code{likely} flags are true if the
7730 @code{insn} being scheduled is not a conditional branch.
7731 The @code{very_unlikely} and @code{unlikely} flags are false if the
7732 @code{insn} being scheduled is not a conditional branch.
7734 @code{attr_flag} is only used during delay slot scheduling and has no
7735 meaning to other passes of the compiler.
7738 @item (attr @var{name})
7739 The value of another attribute is returned. This is most useful
7740 for numeric attributes, as @code{eq_attr} and @code{attr_flag}
7741 produce more efficient code for non-numeric attributes.
7747 @subsection Assigning Attribute Values to Insns
7748 @cindex tagging insns
7749 @cindex assigning attribute values to insns
7751 The value assigned to an attribute of an insn is primarily determined by
7752 which pattern is matched by that insn (or which @code{define_peephole}
7753 generated it). Every @code{define_insn} and @code{define_peephole} can
7754 have an optional last argument to specify the values of attributes for
7755 matching insns. The value of any attribute not specified in a particular
7756 insn is set to the default value for that attribute, as specified in its
7757 @code{define_attr}. Extensive use of default values for attributes
7758 permits the specification of the values for only one or two attributes
7759 in the definition of most insn patterns, as seen in the example in the
7762 The optional last argument of @code{define_insn} and
7763 @code{define_peephole} is a vector of expressions, each of which defines
7764 the value for a single attribute. The most general way of assigning an
7765 attribute's value is to use a @code{set} expression whose first operand is an
7766 @code{attr} expression giving the name of the attribute being set. The
7767 second operand of the @code{set} is an attribute expression
7768 (@pxref{Expressions}) giving the value of the attribute.
7770 When the attribute value depends on the @samp{alternative} attribute
7771 (i.e., which is the applicable alternative in the constraint of the
7772 insn), the @code{set_attr_alternative} expression can be used. It
7773 allows the specification of a vector of attribute expressions, one for
7777 When the generality of arbitrary attribute expressions is not required,
7778 the simpler @code{set_attr} expression can be used, which allows
7779 specifying a string giving either a single attribute value or a list
7780 of attribute values, one for each alternative.
7782 The form of each of the above specifications is shown below. In each case,
7783 @var{name} is a string specifying the attribute to be set.
7786 @item (set_attr @var{name} @var{value-string})
7787 @var{value-string} is either a string giving the desired attribute value,
7788 or a string containing a comma-separated list giving the values for
7789 succeeding alternatives. The number of elements must match the number
7790 of alternatives in the constraint of the insn pattern.
7792 Note that it may be useful to specify @samp{*} for some alternative, in
7793 which case the attribute will assume its default value for insns matching
7796 @findex set_attr_alternative
7797 @item (set_attr_alternative @var{name} [@var{value1} @var{value2} @dots{}])
7798 Depending on the alternative of the insn, the value will be one of the
7799 specified values. This is a shorthand for using a @code{cond} with
7800 tests on the @samp{alternative} attribute.
7803 @item (set (attr @var{name}) @var{value})
7804 The first operand of this @code{set} must be the special RTL expression
7805 @code{attr}, whose sole operand is a string giving the name of the
7806 attribute being set. @var{value} is the value of the attribute.
7809 The following shows three different ways of representing the same
7810 attribute value specification:
7813 (set_attr "type" "load,store,arith")
7815 (set_attr_alternative "type"
7816 [(const_string "load") (const_string "store")
7817 (const_string "arith")])
7820 (cond [(eq_attr "alternative" "1") (const_string "load")
7821 (eq_attr "alternative" "2") (const_string "store")]
7822 (const_string "arith")))
7826 @findex define_asm_attributes
7827 The @code{define_asm_attributes} expression provides a mechanism to
7828 specify the attributes assigned to insns produced from an @code{asm}
7829 statement. It has the form:
7832 (define_asm_attributes [@var{attr-sets}])
7836 where @var{attr-sets} is specified the same as for both the
7837 @code{define_insn} and the @code{define_peephole} expressions.
7839 These values will typically be the ``worst case'' attribute values. For
7840 example, they might indicate that the condition code will be clobbered.
7842 A specification for a @code{length} attribute is handled specially. The
7843 way to compute the length of an @code{asm} insn is to multiply the
7844 length specified in the expression @code{define_asm_attributes} by the
7845 number of machine instructions specified in the @code{asm} statement,
7846 determined by counting the number of semicolons and newlines in the
7847 string. Therefore, the value of the @code{length} attribute specified
7848 in a @code{define_asm_attributes} should be the maximum possible length
7849 of a single machine instruction.
7854 @subsection Example of Attribute Specifications
7855 @cindex attribute specifications example
7856 @cindex attribute specifications
7858 The judicious use of defaulting is important in the efficient use of
7859 insn attributes. Typically, insns are divided into @dfn{types} and an
7860 attribute, customarily called @code{type}, is used to represent this
7861 value. This attribute is normally used only to define the default value
7862 for other attributes. An example will clarify this usage.
7864 Assume we have a RISC machine with a condition code and in which only
7865 full-word operations are performed in registers. Let us assume that we
7866 can divide all insns into loads, stores, (integer) arithmetic
7867 operations, floating point operations, and branches.
7869 Here we will concern ourselves with determining the effect of an insn on
7870 the condition code and will limit ourselves to the following possible
7871 effects: The condition code can be set unpredictably (clobbered), not
7872 be changed, be set to agree with the results of the operation, or only
7873 changed if the item previously set into the condition code has been
7876 Here is part of a sample @file{md} file for such a machine:
7879 (define_attr "type" "load,store,arith,fp,branch" (const_string "arith"))
7881 (define_attr "cc" "clobber,unchanged,set,change0"
7882 (cond [(eq_attr "type" "load")
7883 (const_string "change0")
7884 (eq_attr "type" "store,branch")
7885 (const_string "unchanged")
7886 (eq_attr "type" "arith")
7887 (if_then_else (match_operand:SI 0 "" "")
7888 (const_string "set")
7889 (const_string "clobber"))]
7890 (const_string "clobber")))
7893 [(set (match_operand:SI 0 "general_operand" "=r,r,m")
7894 (match_operand:SI 1 "general_operand" "r,m,r"))]
7900 [(set_attr "type" "arith,load,store")])
7903 Note that we assume in the above example that arithmetic operations
7904 performed on quantities smaller than a machine word clobber the condition
7905 code since they will set the condition code to a value corresponding to the
7911 @subsection Computing the Length of an Insn
7912 @cindex insn lengths, computing
7913 @cindex computing the length of an insn
7915 For many machines, multiple types of branch instructions are provided, each
7916 for different length branch displacements. In most cases, the assembler
7917 will choose the correct instruction to use. However, when the assembler
7918 cannot do so, GCC can when a special attribute, the @code{length}
7919 attribute, is defined. This attribute must be defined to have numeric
7920 values by specifying a null string in its @code{define_attr}.
7922 In the case of the @code{length} attribute, two additional forms of
7923 arithmetic terms are allowed in test expressions:
7926 @cindex @code{match_dup} and attributes
7927 @item (match_dup @var{n})
7928 This refers to the address of operand @var{n} of the current insn, which
7929 must be a @code{label_ref}.
7931 @cindex @code{pc} and attributes
7933 This refers to the address of the @emph{current} insn. It might have
7934 been more consistent with other usage to make this the address of the
7935 @emph{next} insn but this would be confusing because the length of the
7936 current insn is to be computed.
7939 @cindex @code{addr_vec}, length of
7940 @cindex @code{addr_diff_vec}, length of
7941 For normal insns, the length will be determined by value of the
7942 @code{length} attribute. In the case of @code{addr_vec} and
7943 @code{addr_diff_vec} insn patterns, the length is computed as
7944 the number of vectors multiplied by the size of each vector.
7946 Lengths are measured in addressable storage units (bytes).
7948 The following macros can be used to refine the length computation:
7951 @findex ADJUST_INSN_LENGTH
7952 @item ADJUST_INSN_LENGTH (@var{insn}, @var{length})
7953 If defined, modifies the length assigned to instruction @var{insn} as a
7954 function of the context in which it is used. @var{length} is an lvalue
7955 that contains the initially computed length of the insn and should be
7956 updated with the correct length of the insn.
7958 This macro will normally not be required. A case in which it is
7959 required is the ROMP@. On this machine, the size of an @code{addr_vec}
7960 insn must be increased by two to compensate for the fact that alignment
7964 @findex get_attr_length
7965 The routine that returns @code{get_attr_length} (the value of the
7966 @code{length} attribute) can be used by the output routine to
7967 determine the form of the branch instruction to be written, as the
7968 example below illustrates.
7970 As an example of the specification of variable-length branches, consider
7971 the IBM 360. If we adopt the convention that a register will be set to
7972 the starting address of a function, we can jump to labels within 4k of
7973 the start using a four-byte instruction. Otherwise, we need a six-byte
7974 sequence to load the address from memory and then branch to it.
7976 On such a machine, a pattern for a branch instruction might be specified
7982 (label_ref (match_operand 0 "" "")))]
7985 return (get_attr_length (insn) == 4
7986 ? "b %l0" : "l r15,=a(%l0); br r15");
7988 [(set (attr "length")
7989 (if_then_else (lt (match_dup 0) (const_int 4096))
7996 @node Constant Attributes
7997 @subsection Constant Attributes
7998 @cindex constant attributes
8000 A special form of @code{define_attr}, where the expression for the
8001 default value is a @code{const} expression, indicates an attribute that
8002 is constant for a given run of the compiler. Constant attributes may be
8003 used to specify which variety of processor is used. For example,
8006 (define_attr "cpu" "m88100,m88110,m88000"
8008 (cond [(symbol_ref "TARGET_88100") (const_string "m88100")
8009 (symbol_ref "TARGET_88110") (const_string "m88110")]
8010 (const_string "m88000"))))
8012 (define_attr "memory" "fast,slow"
8014 (if_then_else (symbol_ref "TARGET_FAST_MEM")
8015 (const_string "fast")
8016 (const_string "slow"))))
8019 The routine generated for constant attributes has no parameters as it
8020 does not depend on any particular insn. RTL expressions used to define
8021 the value of a constant attribute may use the @code{symbol_ref} form,
8022 but may not use either the @code{match_operand} form or @code{eq_attr}
8023 forms involving insn attributes.
8028 @subsection Delay Slot Scheduling
8029 @cindex delay slots, defining
8031 The insn attribute mechanism can be used to specify the requirements for
8032 delay slots, if any, on a target machine. An instruction is said to
8033 require a @dfn{delay slot} if some instructions that are physically
8034 after the instruction are executed as if they were located before it.
8035 Classic examples are branch and call instructions, which often execute
8036 the following instruction before the branch or call is performed.
8038 On some machines, conditional branch instructions can optionally
8039 @dfn{annul} instructions in the delay slot. This means that the
8040 instruction will not be executed for certain branch outcomes. Both
8041 instructions that annul if the branch is true and instructions that
8042 annul if the branch is false are supported.
8044 Delay slot scheduling differs from instruction scheduling in that
8045 determining whether an instruction needs a delay slot is dependent only
8046 on the type of instruction being generated, not on data flow between the
8047 instructions. See the next section for a discussion of data-dependent
8048 instruction scheduling.
8050 @findex define_delay
8051 The requirement of an insn needing one or more delay slots is indicated
8052 via the @code{define_delay} expression. It has the following form:
8055 (define_delay @var{test}
8056 [@var{delay-1} @var{annul-true-1} @var{annul-false-1}
8057 @var{delay-2} @var{annul-true-2} @var{annul-false-2}
8061 @var{test} is an attribute test that indicates whether this
8062 @code{define_delay} applies to a particular insn. If so, the number of
8063 required delay slots is determined by the length of the vector specified
8064 as the second argument. An insn placed in delay slot @var{n} must
8065 satisfy attribute test @var{delay-n}. @var{annul-true-n} is an
8066 attribute test that specifies which insns may be annulled if the branch
8067 is true. Similarly, @var{annul-false-n} specifies which insns in the
8068 delay slot may be annulled if the branch is false. If annulling is not
8069 supported for that delay slot, @code{(nil)} should be coded.
8071 For example, in the common case where branch and call insns require
8072 a single delay slot, which may contain any insn other than a branch or
8073 call, the following would be placed in the @file{md} file:
8076 (define_delay (eq_attr "type" "branch,call")
8077 [(eq_attr "type" "!branch,call") (nil) (nil)])
8080 Multiple @code{define_delay} expressions may be specified. In this
8081 case, each such expression specifies different delay slot requirements
8082 and there must be no insn for which tests in two @code{define_delay}
8083 expressions are both true.
8085 For example, if we have a machine that requires one delay slot for branches
8086 but two for calls, no delay slot can contain a branch or call insn,
8087 and any valid insn in the delay slot for the branch can be annulled if the
8088 branch is true, we might represent this as follows:
8091 (define_delay (eq_attr "type" "branch")
8092 [(eq_attr "type" "!branch,call")
8093 (eq_attr "type" "!branch,call")
8096 (define_delay (eq_attr "type" "call")
8097 [(eq_attr "type" "!branch,call") (nil) (nil)
8098 (eq_attr "type" "!branch,call") (nil) (nil)])
8100 @c the above is *still* too long. --mew 4feb93
8104 @node Processor pipeline description
8105 @subsection Specifying processor pipeline description
8106 @cindex processor pipeline description
8107 @cindex processor functional units
8108 @cindex instruction latency time
8109 @cindex interlock delays
8110 @cindex data dependence delays
8111 @cindex reservation delays
8112 @cindex pipeline hazard recognizer
8113 @cindex automaton based pipeline description
8114 @cindex regular expressions
8115 @cindex deterministic finite state automaton
8116 @cindex automaton based scheduler
8120 To achieve better performance, most modern processors
8121 (super-pipelined, superscalar @acronym{RISC}, and @acronym{VLIW}
8122 processors) have many @dfn{functional units} on which several
8123 instructions can be executed simultaneously. An instruction starts
8124 execution if its issue conditions are satisfied. If not, the
8125 instruction is stalled until its conditions are satisfied. Such
8126 @dfn{interlock (pipeline) delay} causes interruption of the fetching
8127 of successor instructions (or demands nop instructions, e.g.@: for some
8130 There are two major kinds of interlock delays in modern processors.
8131 The first one is a data dependence delay determining @dfn{instruction
8132 latency time}. The instruction execution is not started until all
8133 source data have been evaluated by prior instructions (there are more
8134 complex cases when the instruction execution starts even when the data
8135 are not available but will be ready in given time after the
8136 instruction execution start). Taking the data dependence delays into
8137 account is simple. The data dependence (true, output, and
8138 anti-dependence) delay between two instructions is given by a
8139 constant. In most cases this approach is adequate. The second kind
8140 of interlock delays is a reservation delay. The reservation delay
8141 means that two instructions under execution will be in need of shared
8142 processors resources, i.e.@: buses, internal registers, and/or
8143 functional units, which are reserved for some time. Taking this kind
8144 of delay into account is complex especially for modern @acronym{RISC}
8147 The task of exploiting more processor parallelism is solved by an
8148 instruction scheduler. For a better solution to this problem, the
8149 instruction scheduler has to have an adequate description of the
8150 processor parallelism (or @dfn{pipeline description}). GCC
8151 machine descriptions describe processor parallelism and functional
8152 unit reservations for groups of instructions with the aid of
8153 @dfn{regular expressions}.
8155 The GCC instruction scheduler uses a @dfn{pipeline hazard recognizer} to
8156 figure out the possibility of the instruction issue by the processor
8157 on a given simulated processor cycle. The pipeline hazard recognizer is
8158 automatically generated from the processor pipeline description. The
8159 pipeline hazard recognizer generated from the machine description
8160 is based on a deterministic finite state automaton (@acronym{DFA}):
8161 the instruction issue is possible if there is a transition from one
8162 automaton state to another one. This algorithm is very fast, and
8163 furthermore, its speed is not dependent on processor
8164 complexity@footnote{However, the size of the automaton depends on
8165 processor complexity. To limit this effect, machine descriptions
8166 can split orthogonal parts of the machine description among several
8167 automata: but then, since each of these must be stepped independently,
8168 this does cause a small decrease in the algorithm's performance.}.
8170 @cindex automaton based pipeline description
8171 The rest of this section describes the directives that constitute
8172 an automaton-based processor pipeline description. The order of
8173 these constructions within the machine description file is not
8176 @findex define_automaton
8177 @cindex pipeline hazard recognizer
8178 The following optional construction describes names of automata
8179 generated and used for the pipeline hazards recognition. Sometimes
8180 the generated finite state automaton used by the pipeline hazard
8181 recognizer is large. If we use more than one automaton and bind functional
8182 units to the automata, the total size of the automata is usually
8183 less than the size of the single automaton. If there is no one such
8184 construction, only one finite state automaton is generated.
8187 (define_automaton @var{automata-names})
8190 @var{automata-names} is a string giving names of the automata. The
8191 names are separated by commas. All the automata should have unique names.
8192 The automaton name is used in the constructions @code{define_cpu_unit} and
8193 @code{define_query_cpu_unit}.
8195 @findex define_cpu_unit
8196 @cindex processor functional units
8197 Each processor functional unit used in the description of instruction
8198 reservations should be described by the following construction.
8201 (define_cpu_unit @var{unit-names} [@var{automaton-name}])
8204 @var{unit-names} is a string giving the names of the functional units
8205 separated by commas. Don't use name @samp{nothing}, it is reserved
8208 @var{automaton-name} is a string giving the name of the automaton with
8209 which the unit is bound. The automaton should be described in
8210 construction @code{define_automaton}. You should give
8211 @dfn{automaton-name}, if there is a defined automaton.
8213 The assignment of units to automata are constrained by the uses of the
8214 units in insn reservations. The most important constraint is: if a
8215 unit reservation is present on a particular cycle of an alternative
8216 for an insn reservation, then some unit from the same automaton must
8217 be present on the same cycle for the other alternatives of the insn
8218 reservation. The rest of the constraints are mentioned in the
8219 description of the subsequent constructions.
8221 @findex define_query_cpu_unit
8222 @cindex querying function unit reservations
8223 The following construction describes CPU functional units analogously
8224 to @code{define_cpu_unit}. The reservation of such units can be
8225 queried for an automaton state. The instruction scheduler never
8226 queries reservation of functional units for given automaton state. So
8227 as a rule, you don't need this construction. This construction could
8228 be used for future code generation goals (e.g.@: to generate
8229 @acronym{VLIW} insn templates).
8232 (define_query_cpu_unit @var{unit-names} [@var{automaton-name}])
8235 @var{unit-names} is a string giving names of the functional units
8236 separated by commas.
8238 @var{automaton-name} is a string giving the name of the automaton with
8239 which the unit is bound.
8241 @findex define_insn_reservation
8242 @cindex instruction latency time
8243 @cindex regular expressions
8245 The following construction is the major one to describe pipeline
8246 characteristics of an instruction.
8249 (define_insn_reservation @var{insn-name} @var{default_latency}
8250 @var{condition} @var{regexp})
8253 @var{default_latency} is a number giving latency time of the
8254 instruction. There is an important difference between the old
8255 description and the automaton based pipeline description. The latency
8256 time is used for all dependencies when we use the old description. In
8257 the automaton based pipeline description, the given latency time is only
8258 used for true dependencies. The cost of anti-dependencies is always
8259 zero and the cost of output dependencies is the difference between
8260 latency times of the producing and consuming insns (if the difference
8261 is negative, the cost is considered to be zero). You can always
8262 change the default costs for any description by using the target hook
8263 @code{TARGET_SCHED_ADJUST_COST} (@pxref{Scheduling}).
8265 @var{insn-name} is a string giving the internal name of the insn. The
8266 internal names are used in constructions @code{define_bypass} and in
8267 the automaton description file generated for debugging. The internal
8268 name has nothing in common with the names in @code{define_insn}. It is a
8269 good practice to use insn classes described in the processor manual.
8271 @var{condition} defines what RTL insns are described by this
8272 construction. You should remember that you will be in trouble if
8273 @var{condition} for two or more different
8274 @code{define_insn_reservation} constructions is TRUE for an insn. In
8275 this case what reservation will be used for the insn is not defined.
8276 Such cases are not checked during generation of the pipeline hazards
8277 recognizer because in general recognizing that two conditions may have
8278 the same value is quite difficult (especially if the conditions
8279 contain @code{symbol_ref}). It is also not checked during the
8280 pipeline hazard recognizer work because it would slow down the
8281 recognizer considerably.
8283 @var{regexp} is a string describing the reservation of the cpu's functional
8284 units by the instruction. The reservations are described by a regular
8285 expression according to the following syntax:
8288 regexp = regexp "," oneof
8291 oneof = oneof "|" allof
8294 allof = allof "+" repeat
8297 repeat = element "*" number
8300 element = cpu_function_unit_name
8309 @samp{,} is used for describing the start of the next cycle in
8313 @samp{|} is used for describing a reservation described by the first
8314 regular expression @strong{or} a reservation described by the second
8315 regular expression @strong{or} etc.
8318 @samp{+} is used for describing a reservation described by the first
8319 regular expression @strong{and} a reservation described by the
8320 second regular expression @strong{and} etc.
8323 @samp{*} is used for convenience and simply means a sequence in which
8324 the regular expression are repeated @var{number} times with cycle
8325 advancing (see @samp{,}).
8328 @samp{cpu_function_unit_name} denotes reservation of the named
8332 @samp{reservation_name} --- see description of construction
8333 @samp{define_reservation}.
8336 @samp{nothing} denotes no unit reservations.
8339 @findex define_reservation
8340 Sometimes unit reservations for different insns contain common parts.
8341 In such case, you can simplify the pipeline description by describing
8342 the common part by the following construction
8345 (define_reservation @var{reservation-name} @var{regexp})
8348 @var{reservation-name} is a string giving name of @var{regexp}.
8349 Functional unit names and reservation names are in the same name
8350 space. So the reservation names should be different from the
8351 functional unit names and can not be the reserved name @samp{nothing}.
8353 @findex define_bypass
8354 @cindex instruction latency time
8356 The following construction is used to describe exceptions in the
8357 latency time for given instruction pair. This is so called bypasses.
8360 (define_bypass @var{number} @var{out_insn_names} @var{in_insn_names}
8364 @var{number} defines when the result generated by the instructions
8365 given in string @var{out_insn_names} will be ready for the
8366 instructions given in string @var{in_insn_names}. Each of these
8367 strings is a comma-separated list of filename-style globs and
8368 they refer to the names of @code{define_insn_reservation}s.
8371 (define_bypass 1 "cpu1_load_*, cpu1_store_*" "cpu1_load_*")
8373 defines a bypass between instructions that start with
8374 @samp{cpu1_load_} or @samp{cpu1_store_} and those that start with
8377 @var{guard} is an optional string giving the name of a C function which
8378 defines an additional guard for the bypass. The function will get the
8379 two insns as parameters. If the function returns zero the bypass will
8380 be ignored for this case. The additional guard is necessary to
8381 recognize complicated bypasses, e.g.@: when the consumer is only an address
8382 of insn @samp{store} (not a stored value).
8384 If there are more one bypass with the same output and input insns, the
8385 chosen bypass is the first bypass with a guard in description whose
8386 guard function returns nonzero. If there is no such bypass, then
8387 bypass without the guard function is chosen.
8389 @findex exclusion_set
8390 @findex presence_set
8391 @findex final_presence_set
8393 @findex final_absence_set
8396 The following five constructions are usually used to describe
8397 @acronym{VLIW} processors, or more precisely, to describe a placement
8398 of small instructions into @acronym{VLIW} instruction slots. They
8399 can be used for @acronym{RISC} processors, too.
8402 (exclusion_set @var{unit-names} @var{unit-names})
8403 (presence_set @var{unit-names} @var{patterns})
8404 (final_presence_set @var{unit-names} @var{patterns})
8405 (absence_set @var{unit-names} @var{patterns})
8406 (final_absence_set @var{unit-names} @var{patterns})
8409 @var{unit-names} is a string giving names of functional units
8410 separated by commas.
8412 @var{patterns} is a string giving patterns of functional units
8413 separated by comma. Currently pattern is one unit or units
8414 separated by white-spaces.
8416 The first construction (@samp{exclusion_set}) means that each
8417 functional unit in the first string can not be reserved simultaneously
8418 with a unit whose name is in the second string and vice versa. For
8419 example, the construction is useful for describing processors
8420 (e.g.@: some SPARC processors) with a fully pipelined floating point
8421 functional unit which can execute simultaneously only single floating
8422 point insns or only double floating point insns.
8424 The second construction (@samp{presence_set}) means that each
8425 functional unit in the first string can not be reserved unless at
8426 least one of pattern of units whose names are in the second string is
8427 reserved. This is an asymmetric relation. For example, it is useful
8428 for description that @acronym{VLIW} @samp{slot1} is reserved after
8429 @samp{slot0} reservation. We could describe it by the following
8433 (presence_set "slot1" "slot0")
8436 Or @samp{slot1} is reserved only after @samp{slot0} and unit @samp{b0}
8437 reservation. In this case we could write
8440 (presence_set "slot1" "slot0 b0")
8443 The third construction (@samp{final_presence_set}) is analogous to
8444 @samp{presence_set}. The difference between them is when checking is
8445 done. When an instruction is issued in given automaton state
8446 reflecting all current and planned unit reservations, the automaton
8447 state is changed. The first state is a source state, the second one
8448 is a result state. Checking for @samp{presence_set} is done on the
8449 source state reservation, checking for @samp{final_presence_set} is
8450 done on the result reservation. This construction is useful to
8451 describe a reservation which is actually two subsequent reservations.
8452 For example, if we use
8455 (presence_set "slot1" "slot0")
8458 the following insn will be never issued (because @samp{slot1} requires
8459 @samp{slot0} which is absent in the source state).
8462 (define_reservation "insn_and_nop" "slot0 + slot1")
8465 but it can be issued if we use analogous @samp{final_presence_set}.
8467 The forth construction (@samp{absence_set}) means that each functional
8468 unit in the first string can be reserved only if each pattern of units
8469 whose names are in the second string is not reserved. This is an
8470 asymmetric relation (actually @samp{exclusion_set} is analogous to
8471 this one but it is symmetric). For example it might be useful in a
8472 @acronym{VLIW} description to say that @samp{slot0} cannot be reserved
8473 after either @samp{slot1} or @samp{slot2} have been reserved. This
8474 can be described as:
8477 (absence_set "slot0" "slot1, slot2")
8480 Or @samp{slot2} can not be reserved if @samp{slot0} and unit @samp{b0}
8481 are reserved or @samp{slot1} and unit @samp{b1} are reserved. In
8482 this case we could write
8485 (absence_set "slot2" "slot0 b0, slot1 b1")
8488 All functional units mentioned in a set should belong to the same
8491 The last construction (@samp{final_absence_set}) is analogous to
8492 @samp{absence_set} but checking is done on the result (state)
8493 reservation. See comments for @samp{final_presence_set}.
8495 @findex automata_option
8496 @cindex deterministic finite state automaton
8497 @cindex nondeterministic finite state automaton
8498 @cindex finite state automaton minimization
8499 You can control the generator of the pipeline hazard recognizer with
8500 the following construction.
8503 (automata_option @var{options})
8506 @var{options} is a string giving options which affect the generated
8507 code. Currently there are the following options:
8511 @dfn{no-minimization} makes no minimization of the automaton. This is
8512 only worth to do when we are debugging the description and need to
8513 look more accurately at reservations of states.
8516 @dfn{time} means printing time statistics about the generation of
8520 @dfn{stats} means printing statistics about the generated automata
8521 such as the number of DFA states, NDFA states and arcs.
8524 @dfn{v} means a generation of the file describing the result automata.
8525 The file has suffix @samp{.dfa} and can be used for the description
8526 verification and debugging.
8529 @dfn{w} means a generation of warning instead of error for
8530 non-critical errors.
8533 @dfn{no-comb-vect} prevents the automaton generator from generating
8534 two data structures and comparing them for space efficiency. Using
8535 a comb vector to represent transitions may be better, but it can be
8536 very expensive to construct. This option is useful if the build
8537 process spends an unacceptably long time in genautomata.
8540 @dfn{ndfa} makes nondeterministic finite state automata. This affects
8541 the treatment of operator @samp{|} in the regular expressions. The
8542 usual treatment of the operator is to try the first alternative and,
8543 if the reservation is not possible, the second alternative. The
8544 nondeterministic treatment means trying all alternatives, some of them
8545 may be rejected by reservations in the subsequent insns.
8548 @dfn{collapse-ndfa} modifies the behaviour of the generator when
8549 producing an automaton. An additional state transition to collapse a
8550 nondeterministic @acronym{NDFA} state to a deterministic @acronym{DFA}
8551 state is generated. It can be triggered by passing @code{const0_rtx} to
8552 state_transition. In such an automaton, cycle advance transitions are
8553 available only for these collapsed states. This option is useful for
8554 ports that want to use the @code{ndfa} option, but also want to use
8555 @code{define_query_cpu_unit} to assign units to insns issued in a cycle.
8558 @dfn{progress} means output of a progress bar showing how many states
8559 were generated so far for automaton being processed. This is useful
8560 during debugging a @acronym{DFA} description. If you see too many
8561 generated states, you could interrupt the generator of the pipeline
8562 hazard recognizer and try to figure out a reason for generation of the
8566 As an example, consider a superscalar @acronym{RISC} machine which can
8567 issue three insns (two integer insns and one floating point insn) on
8568 the cycle but can finish only two insns. To describe this, we define
8569 the following functional units.
8572 (define_cpu_unit "i0_pipeline, i1_pipeline, f_pipeline")
8573 (define_cpu_unit "port0, port1")
8576 All simple integer insns can be executed in any integer pipeline and
8577 their result is ready in two cycles. The simple integer insns are
8578 issued into the first pipeline unless it is reserved, otherwise they
8579 are issued into the second pipeline. Integer division and
8580 multiplication insns can be executed only in the second integer
8581 pipeline and their results are ready correspondingly in 8 and 4
8582 cycles. The integer division is not pipelined, i.e.@: the subsequent
8583 integer division insn can not be issued until the current division
8584 insn finished. Floating point insns are fully pipelined and their
8585 results are ready in 3 cycles. Where the result of a floating point
8586 insn is used by an integer insn, an additional delay of one cycle is
8587 incurred. To describe all of this we could specify
8590 (define_cpu_unit "div")
8592 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
8593 "(i0_pipeline | i1_pipeline), (port0 | port1)")
8595 (define_insn_reservation "mult" 4 (eq_attr "type" "mult")
8596 "i1_pipeline, nothing*2, (port0 | port1)")
8598 (define_insn_reservation "div" 8 (eq_attr "type" "div")
8599 "i1_pipeline, div*7, div + (port0 | port1)")
8601 (define_insn_reservation "float" 3 (eq_attr "type" "float")
8602 "f_pipeline, nothing, (port0 | port1))
8604 (define_bypass 4 "float" "simple,mult,div")
8607 To simplify the description we could describe the following reservation
8610 (define_reservation "finish" "port0|port1")
8613 and use it in all @code{define_insn_reservation} as in the following
8617 (define_insn_reservation "simple" 2 (eq_attr "type" "int")
8618 "(i0_pipeline | i1_pipeline), finish")
8624 @node Conditional Execution
8625 @section Conditional Execution
8626 @cindex conditional execution
8629 A number of architectures provide for some form of conditional
8630 execution, or predication. The hallmark of this feature is the
8631 ability to nullify most of the instructions in the instruction set.
8632 When the instruction set is large and not entirely symmetric, it
8633 can be quite tedious to describe these forms directly in the
8634 @file{.md} file. An alternative is the @code{define_cond_exec} template.
8636 @findex define_cond_exec
8639 [@var{predicate-pattern}]
8641 "@var{output-template}")
8644 @var{predicate-pattern} is the condition that must be true for the
8645 insn to be executed at runtime and should match a relational operator.
8646 One can use @code{match_operator} to match several relational operators
8647 at once. Any @code{match_operand} operands must have no more than one
8650 @var{condition} is a C expression that must be true for the generated
8653 @findex current_insn_predicate
8654 @var{output-template} is a string similar to the @code{define_insn}
8655 output template (@pxref{Output Template}), except that the @samp{*}
8656 and @samp{@@} special cases do not apply. This is only useful if the
8657 assembly text for the predicate is a simple prefix to the main insn.
8658 In order to handle the general case, there is a global variable
8659 @code{current_insn_predicate} that will contain the entire predicate
8660 if the current insn is predicated, and will otherwise be @code{NULL}.
8662 When @code{define_cond_exec} is used, an implicit reference to
8663 the @code{predicable} instruction attribute is made.
8664 @xref{Insn Attributes}. This attribute must be a boolean (i.e.@: have
8665 exactly two elements in its @var{list-of-values}), with the possible
8666 values being @code{no} and @code{yes}. The default and all uses in
8667 the insns must be a simple constant, not a complex expressions. It
8668 may, however, depend on the alternative, by using a comma-separated
8669 list of values. If that is the case, the port should also define an
8670 @code{enabled} attribute (@pxref{Disable Insn Alternatives}), which
8671 should also allow only @code{no} and @code{yes} as its values.
8673 For each @code{define_insn} for which the @code{predicable}
8674 attribute is true, a new @code{define_insn} pattern will be
8675 generated that matches a predicated version of the instruction.
8679 (define_insn "addsi"
8680 [(set (match_operand:SI 0 "register_operand" "r")
8681 (plus:SI (match_operand:SI 1 "register_operand" "r")
8682 (match_operand:SI 2 "register_operand" "r")))]
8687 [(ne (match_operand:CC 0 "register_operand" "c")
8694 generates a new pattern
8699 (ne (match_operand:CC 3 "register_operand" "c") (const_int 0))
8700 (set (match_operand:SI 0 "register_operand" "r")
8701 (plus:SI (match_operand:SI 1 "register_operand" "r")
8702 (match_operand:SI 2 "register_operand" "r"))))]
8703 "(@var{test2}) && (@var{test1})"
8704 "(%3) add %2,%1,%0")
8709 @node Constant Definitions
8710 @section Constant Definitions
8711 @cindex constant definitions
8712 @findex define_constants
8714 Using literal constants inside instruction patterns reduces legibility and
8715 can be a maintenance problem.
8717 To overcome this problem, you may use the @code{define_constants}
8718 expression. It contains a vector of name-value pairs. From that
8719 point on, wherever any of the names appears in the MD file, it is as
8720 if the corresponding value had been written instead. You may use
8721 @code{define_constants} multiple times; each appearance adds more
8722 constants to the table. It is an error to redefine a constant with
8725 To come back to the a29k load multiple example, instead of
8729 [(match_parallel 0 "load_multiple_operation"
8730 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8731 (match_operand:SI 2 "memory_operand" "m"))
8733 (clobber (reg:SI 179))])]
8749 [(match_parallel 0 "load_multiple_operation"
8750 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
8751 (match_operand:SI 2 "memory_operand" "m"))
8753 (clobber (reg:SI R_CR))])]
8758 The constants that are defined with a define_constant are also output
8759 in the insn-codes.h header file as #defines.
8761 @cindex enumerations
8762 @findex define_c_enum
8763 You can also use the machine description file to define enumerations.
8764 Like the constants defined by @code{define_constant}, these enumerations
8765 are visible to both the machine description file and the main C code.
8767 The syntax is as follows:
8770 (define_c_enum "@var{name}" [
8778 This definition causes the equivalent of the following C code to appear
8779 in @file{insn-constants.h}:
8786 @var{valuen} = @var{n}
8788 #define NUM_@var{cname}_VALUES (@var{n} + 1)
8791 where @var{cname} is the capitalized form of @var{name}.
8792 It also makes each @var{valuei} available in the machine description
8793 file, just as if it had been declared with:
8796 (define_constants [(@var{valuei} @var{i})])
8799 Each @var{valuei} is usually an upper-case identifier and usually
8800 begins with @var{cname}.
8802 You can split the enumeration definition into as many statements as
8803 you like. The above example is directly equivalent to:
8806 (define_c_enum "@var{name}" [@var{value0}])
8807 (define_c_enum "@var{name}" [@var{value1}])
8809 (define_c_enum "@var{name}" [@var{valuen}])
8812 Splitting the enumeration helps to improve the modularity of each
8813 individual @code{.md} file. For example, if a port defines its
8814 synchronization instructions in a separate @file{sync.md} file,
8815 it is convenient to define all synchronization-specific enumeration
8816 values in @file{sync.md} rather than in the main @file{.md} file.
8818 Some enumeration names have special significance to GCC:
8822 @findex unspec_volatile
8823 If an enumeration called @code{unspecv} is defined, GCC will use it
8824 when printing out @code{unspec_volatile} expressions. For example:
8827 (define_c_enum "unspecv" [
8832 causes GCC to print @samp{(unspec_volatile @dots{} 0)} as:
8835 (unspec_volatile ... UNSPECV_BLOCKAGE)
8840 If an enumeration called @code{unspec} is defined, GCC will use
8841 it when printing out @code{unspec} expressions. GCC will also use
8842 it when printing out @code{unspec_volatile} expressions unless an
8843 @code{unspecv} enumeration is also defined. You can therefore
8844 decide whether to keep separate enumerations for volatile and
8845 non-volatile expressions or whether to use the same enumeration
8850 @anchor{define_enum}
8851 Another way of defining an enumeration is to use @code{define_enum}:
8854 (define_enum "@var{name}" [
8862 This directive implies:
8865 (define_c_enum "@var{name}" [
8866 @var{cname}_@var{cvalue0}
8867 @var{cname}_@var{cvalue1}
8869 @var{cname}_@var{cvaluen}
8873 @findex define_enum_attr
8874 where @var{cvaluei} is the capitalized form of @var{valuei}.
8875 However, unlike @code{define_c_enum}, the enumerations defined
8876 by @code{define_enum} can be used in attribute specifications
8877 (@pxref{define_enum_attr}).
8882 @cindex iterators in @file{.md} files
8884 Ports often need to define similar patterns for more than one machine
8885 mode or for more than one rtx code. GCC provides some simple iterator
8886 facilities to make this process easier.
8889 * Mode Iterators:: Generating variations of patterns for different modes.
8890 * Code Iterators:: Doing the same for codes.
8893 @node Mode Iterators
8894 @subsection Mode Iterators
8895 @cindex mode iterators in @file{.md} files
8897 Ports often need to define similar patterns for two or more different modes.
8902 If a processor has hardware support for both single and double
8903 floating-point arithmetic, the @code{SFmode} patterns tend to be
8904 very similar to the @code{DFmode} ones.
8907 If a port uses @code{SImode} pointers in one configuration and
8908 @code{DImode} pointers in another, it will usually have very similar
8909 @code{SImode} and @code{DImode} patterns for manipulating pointers.
8912 Mode iterators allow several patterns to be instantiated from one
8913 @file{.md} file template. They can be used with any type of
8914 rtx-based construct, such as a @code{define_insn},
8915 @code{define_split}, or @code{define_peephole2}.
8918 * Defining Mode Iterators:: Defining a new mode iterator.
8919 * Substitutions:: Combining mode iterators with substitutions
8920 * Examples:: Examples
8923 @node Defining Mode Iterators
8924 @subsubsection Defining Mode Iterators
8925 @findex define_mode_iterator
8927 The syntax for defining a mode iterator is:
8930 (define_mode_iterator @var{name} [(@var{mode1} "@var{cond1}") @dots{} (@var{moden} "@var{condn}")])
8933 This allows subsequent @file{.md} file constructs to use the mode suffix
8934 @code{:@var{name}}. Every construct that does so will be expanded
8935 @var{n} times, once with every use of @code{:@var{name}} replaced by
8936 @code{:@var{mode1}}, once with every use replaced by @code{:@var{mode2}},
8937 and so on. In the expansion for a particular @var{modei}, every
8938 C condition will also require that @var{condi} be true.
8943 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
8946 defines a new mode suffix @code{:P}. Every construct that uses
8947 @code{:P} will be expanded twice, once with every @code{:P} replaced
8948 by @code{:SI} and once with every @code{:P} replaced by @code{:DI}.
8949 The @code{:SI} version will only apply if @code{Pmode == SImode} and
8950 the @code{:DI} version will only apply if @code{Pmode == DImode}.
8952 As with other @file{.md} conditions, an empty string is treated
8953 as ``always true''. @code{(@var{mode} "")} can also be abbreviated
8954 to @code{@var{mode}}. For example:
8957 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
8960 means that the @code{:DI} expansion only applies if @code{TARGET_64BIT}
8961 but that the @code{:SI} expansion has no such constraint.
8963 Iterators are applied in the order they are defined. This can be
8964 significant if two iterators are used in a construct that requires
8965 substitutions. @xref{Substitutions}.
8968 @subsubsection Substitution in Mode Iterators
8969 @findex define_mode_attr
8971 If an @file{.md} file construct uses mode iterators, each version of the
8972 construct will often need slightly different strings or modes. For
8977 When a @code{define_expand} defines several @code{add@var{m}3} patterns
8978 (@pxref{Standard Names}), each expander will need to use the
8979 appropriate mode name for @var{m}.
8982 When a @code{define_insn} defines several instruction patterns,
8983 each instruction will often use a different assembler mnemonic.
8986 When a @code{define_insn} requires operands with different modes,
8987 using an iterator for one of the operand modes usually requires a specific
8988 mode for the other operand(s).
8991 GCC supports such variations through a system of ``mode attributes''.
8992 There are two standard attributes: @code{mode}, which is the name of
8993 the mode in lower case, and @code{MODE}, which is the same thing in
8994 upper case. You can define other attributes using:
8997 (define_mode_attr @var{name} [(@var{mode1} "@var{value1}") @dots{} (@var{moden} "@var{valuen}")])
9000 where @var{name} is the name of the attribute and @var{valuei}
9001 is the value associated with @var{modei}.
9003 When GCC replaces some @var{:iterator} with @var{:mode}, it will scan
9004 each string and mode in the pattern for sequences of the form
9005 @code{<@var{iterator}:@var{attr}>}, where @var{attr} is the name of a
9006 mode attribute. If the attribute is defined for @var{mode}, the whole
9007 @code{<@dots{}>} sequence will be replaced by the appropriate attribute
9010 For example, suppose an @file{.md} file has:
9013 (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
9014 (define_mode_attr load [(SI "lw") (DI "ld")])
9017 If one of the patterns that uses @code{:P} contains the string
9018 @code{"<P:load>\t%0,%1"}, the @code{SI} version of that pattern
9019 will use @code{"lw\t%0,%1"} and the @code{DI} version will use
9022 Here is an example of using an attribute for a mode:
9025 (define_mode_iterator LONG [SI DI])
9026 (define_mode_attr SHORT [(SI "HI") (DI "SI")])
9027 (define_insn @dots{}
9028 (sign_extend:LONG (match_operand:<LONG:SHORT> @dots{})) @dots{})
9031 The @code{@var{iterator}:} prefix may be omitted, in which case the
9032 substitution will be attempted for every iterator expansion.
9035 @subsubsection Mode Iterator Examples
9037 Here is an example from the MIPS port. It defines the following
9038 modes and attributes (among others):
9041 (define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
9042 (define_mode_attr d [(SI "") (DI "d")])
9045 and uses the following template to define both @code{subsi3}
9049 (define_insn "sub<mode>3"
9050 [(set (match_operand:GPR 0 "register_operand" "=d")
9051 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
9052 (match_operand:GPR 2 "register_operand" "d")))]
9055 [(set_attr "type" "arith")
9056 (set_attr "mode" "<MODE>")])
9059 This is exactly equivalent to:
9062 (define_insn "subsi3"
9063 [(set (match_operand:SI 0 "register_operand" "=d")
9064 (minus:SI (match_operand:SI 1 "register_operand" "d")
9065 (match_operand:SI 2 "register_operand" "d")))]
9068 [(set_attr "type" "arith")
9069 (set_attr "mode" "SI")])
9071 (define_insn "subdi3"
9072 [(set (match_operand:DI 0 "register_operand" "=d")
9073 (minus:DI (match_operand:DI 1 "register_operand" "d")
9074 (match_operand:DI 2 "register_operand" "d")))]
9077 [(set_attr "type" "arith")
9078 (set_attr "mode" "DI")])
9081 @node Code Iterators
9082 @subsection Code Iterators
9083 @cindex code iterators in @file{.md} files
9084 @findex define_code_iterator
9085 @findex define_code_attr
9087 Code iterators operate in a similar way to mode iterators. @xref{Mode Iterators}.
9092 (define_code_iterator @var{name} [(@var{code1} "@var{cond1}") @dots{} (@var{coden} "@var{condn}")])
9095 defines a pseudo rtx code @var{name} that can be instantiated as
9096 @var{codei} if condition @var{condi} is true. Each @var{codei}
9097 must have the same rtx format. @xref{RTL Classes}.
9099 As with mode iterators, each pattern that uses @var{name} will be
9100 expanded @var{n} times, once with all uses of @var{name} replaced by
9101 @var{code1}, once with all uses replaced by @var{code2}, and so on.
9102 @xref{Defining Mode Iterators}.
9104 It is possible to define attributes for codes as well as for modes.
9105 There are two standard code attributes: @code{code}, the name of the
9106 code in lower case, and @code{CODE}, the name of the code in upper case.
9107 Other attributes are defined using:
9110 (define_code_attr @var{name} [(@var{code1} "@var{value1}") @dots{} (@var{coden} "@var{valuen}")])
9113 Here's an example of code iterators in action, taken from the MIPS port:
9116 (define_code_iterator any_cond [unordered ordered unlt unge uneq ltgt unle ungt
9117 eq ne gt ge lt le gtu geu ltu leu])
9119 (define_expand "b<code>"
9121 (if_then_else (any_cond:CC (cc0)
9123 (label_ref (match_operand 0 ""))
9127 gen_conditional_branch (operands, <CODE>);
9132 This is equivalent to:
9135 (define_expand "bunordered"
9137 (if_then_else (unordered:CC (cc0)
9139 (label_ref (match_operand 0 ""))
9143 gen_conditional_branch (operands, UNORDERED);
9147 (define_expand "bordered"
9149 (if_then_else (ordered:CC (cc0)
9151 (label_ref (match_operand 0 ""))
9155 gen_conditional_branch (operands, ORDERED);