1 @c Copyright (C) 1988-2020 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
6 @chapter RTL Representation
7 @cindex RTL representation
8 @cindex representation of RTL
9 @cindex Register Transfer Language (RTL)
11 The last part of the compiler work is done on a low-level intermediate
12 representation called Register Transfer Language. In this language, the
13 instructions to be output are described, pretty much one by one, in an
14 algebraic form that describes what the instruction does.
16 RTL is inspired by Lisp lists. It has both an internal form, made up of
17 structures that point at other structures, and a textual form that is used
18 in the machine description and in printed debugging dumps. The textual
19 form uses nested parentheses to indicate the pointers in the internal form.
22 * RTL Objects:: Expressions vs vectors vs strings vs integers.
23 * RTL Classes:: Categories of RTL expression objects, and their structure.
24 * Accessors:: Macros to access expression operands or vector elts.
25 * Special Accessors:: Macros to access specific annotations on RTL.
26 * Flags:: Other flags in an RTL expression.
27 * Machine Modes:: Describing the size and format of a datum.
28 * Constants:: Expressions with constant values.
29 * Regs and Memory:: Expressions representing register contents or memory.
30 * Arithmetic:: Expressions representing arithmetic on other expressions.
31 * Comparisons:: Expressions representing comparison of expressions.
32 * Bit-Fields:: Expressions representing bit-fields in memory or reg.
33 * Vector Operations:: Expressions involving vector datatypes.
34 * Conversions:: Extending, truncating, floating or fixing.
35 * RTL Declarations:: Declaring volatility, constancy, etc.
36 * Side Effects:: Expressions for storing in registers, etc.
37 * Incdec:: Embedded side-effects for autoincrement addressing.
38 * Assembler:: Representing @code{asm} with operands.
39 * Debug Information:: Expressions representing debugging information.
40 * Insns:: Expression types for entire insns.
41 * Calls:: RTL representation of function call insns.
42 * Sharing:: Some expressions are unique; others *must* be copied.
43 * Reading RTL:: Reading textual RTL from a file.
47 @section RTL Object Types
48 @cindex RTL object types
53 @cindex RTL expression
55 RTL uses five kinds of objects: expressions, integers, wide integers,
56 strings and vectors. Expressions are the most important ones. An RTL
57 expression (``RTX'', for short) is a C structure, but it is usually
58 referred to with a pointer; a type that is given the typedef name
61 An integer is simply an @code{int}; their written form uses decimal
62 digits. A wide integer is an integral object whose type is
63 @code{HOST_WIDE_INT}; their written form uses decimal digits.
65 A string is a sequence of characters. In core it is represented as a
66 @code{char *} in usual C fashion, and it is written in C syntax as well.
67 However, strings in RTL may never be null. If you write an empty string in
68 a machine description, it is represented in core as a null pointer rather
69 than as a pointer to a null character. In certain contexts, these null
70 pointers instead of strings are valid. Within RTL code, strings are most
71 commonly found inside @code{symbol_ref} expressions, but they appear in
72 other contexts in the RTL expressions that make up machine descriptions.
74 In a machine description, strings are normally written with double
75 quotes, as you would in C@. However, strings in machine descriptions may
76 extend over many lines, which is invalid C, and adjacent string
77 constants are not concatenated as they are in C@. Any string constant
78 may be surrounded with a single set of parentheses. Sometimes this
79 makes the machine description easier to read.
81 There is also a special syntax for strings, which can be useful when C
82 code is embedded in a machine description. Wherever a string can
83 appear, it is also valid to write a C-style brace block. The entire
84 brace block, including the outermost pair of braces, is considered to be
85 the string constant. Double quote characters inside the braces are not
86 special. Therefore, if you write string constants in the C code, you
87 need not escape each quote character with a backslash.
89 A vector contains an arbitrary number of pointers to expressions. The
90 number of elements in the vector is explicitly present in the vector.
91 The written form of a vector consists of square brackets
92 (@samp{[@dots{}]}) surrounding the elements, in sequence and with
93 whitespace separating them. Vectors of length zero are not created;
94 null pointers are used instead.
96 @cindex expression codes
97 @cindex codes, RTL expression
100 Expressions are classified by @dfn{expression codes} (also called RTX
101 codes). The expression code is a name defined in @file{rtl.def}, which is
102 also (in uppercase) a C enumeration constant. The possible expression
103 codes and their meanings are machine-independent. The code of an RTX can
104 be extracted with the macro @code{GET_CODE (@var{x})} and altered with
105 @code{PUT_CODE (@var{x}, @var{newcode})}.
107 The expression code determines how many operands the expression contains,
108 and what kinds of objects they are. In RTL, unlike Lisp, you cannot tell
109 by looking at an operand what kind of object it is. Instead, you must know
110 from its context---from the expression code of the containing expression.
111 For example, in an expression of code @code{subreg}, the first operand is
112 to be regarded as an expression and the second operand as a polynomial
113 integer. In an expression of code @code{plus}, there are two operands,
114 both of which are to be regarded as expressions. In a @code{symbol_ref}
115 expression, there is one operand, which is to be regarded as a string.
117 Expressions are written as parentheses containing the name of the
118 expression type, its flags and machine mode if any, and then the operands
119 of the expression (separated by spaces).
121 Expression code names in the @samp{md} file are written in lowercase,
122 but when they appear in C code they are written in uppercase. In this
123 manual, they are shown as follows: @code{const_int}.
127 In a few contexts a null pointer is valid where an expression is normally
128 wanted. The written form of this is @code{(nil)}.
131 @section RTL Classes and Formats
133 @cindex classes of RTX codes
134 @cindex RTX codes, classes of
135 @findex GET_RTX_CLASS
137 The various expression codes are divided into several @dfn{classes},
138 which are represented by single characters. You can determine the class
139 of an RTX code with the macro @code{GET_RTX_CLASS (@var{code})}.
140 Currently, @file{rtl.def} defines these classes:
144 An RTX code that represents an actual object, such as a register
145 (@code{REG}) or a memory location (@code{MEM}, @code{SYMBOL_REF}).
146 @code{LO_SUM}) is also included; instead, @code{SUBREG} and
147 @code{STRICT_LOW_PART} are not in this class, but in class
151 An RTX code that represents a constant object. @code{HIGH} is also
152 included in this class.
155 An RTX code for a non-symmetric comparison, such as @code{GEU} or
158 @item RTX_COMM_COMPARE
159 An RTX code for a symmetric (commutative) comparison, such as @code{EQ}
163 An RTX code for a unary arithmetic operation, such as @code{NEG},
164 @code{NOT}, or @code{ABS}. This category also includes value extension
165 (sign or zero) and conversions between integer and floating point.
168 An RTX code for a commutative binary operation, such as @code{PLUS} or
169 @code{AND}. @code{NE} and @code{EQ} are comparisons, so they have class
170 @code{RTX_COMM_COMPARE}.
173 An RTX code for a non-commutative binary operation, such as @code{MINUS},
174 @code{DIV}, or @code{ASHIFTRT}.
176 @item RTX_BITFIELD_OPS
177 An RTX code for a bit-field operation. Currently only
178 @code{ZERO_EXTRACT} and @code{SIGN_EXTRACT}. These have three inputs
179 and are lvalues (so they can be used for insertion as well).
183 An RTX code for other three input operations. Currently only
184 @code{IF_THEN_ELSE}, @code{VEC_MERGE}, @code{SIGN_EXTRACT},
185 @code{ZERO_EXTRACT}, and @code{FMA}.
188 An RTX code for an entire instruction: @code{INSN}, @code{JUMP_INSN}, and
189 @code{CALL_INSN}. @xref{Insns}.
192 An RTX code for something that matches in insns, such as
193 @code{MATCH_DUP}. These only occur in machine descriptions.
196 An RTX code for an auto-increment addressing mode, such as
197 @code{POST_INC}. @samp{XEXP (@var{x}, 0)} gives the auto-modified
201 All other RTX codes. This category includes the remaining codes used
202 only in machine descriptions (@code{DEFINE_*}, etc.). It also includes
203 all the codes describing side effects (@code{SET}, @code{USE},
204 @code{CLOBBER}, etc.) and the non-insns that may appear on an insn
205 chain, such as @code{NOTE}, @code{BARRIER}, and @code{CODE_LABEL}.
206 @code{SUBREG} is also part of this class.
210 For each expression code, @file{rtl.def} specifies the number of
211 contained objects and their kinds using a sequence of characters
212 called the @dfn{format} of the expression code. For example,
213 the format of @code{subreg} is @samp{ep}.
215 @cindex RTL format characters
216 These are the most commonly used format characters:
220 An expression (actually a pointer to an expression).
232 A vector of expressions.
235 A few other format characters are used occasionally:
239 @samp{u} is equivalent to @samp{e} except that it is printed differently
240 in debugging dumps. It is used for pointers to insns.
243 @samp{n} is equivalent to @samp{i} except that it is printed differently
244 in debugging dumps. It is used for the line number or code number of a
248 @samp{S} indicates a string which is optional. In the RTL objects in
249 core, @samp{S} is equivalent to @samp{s}, but when the object is read,
250 from an @samp{md} file, the string value of this operand may be omitted.
251 An omitted string is taken to be the null string.
254 @samp{V} indicates a vector which is optional. In the RTL objects in
255 core, @samp{V} is equivalent to @samp{E}, but when the object is read
256 from an @samp{md} file, the vector value of this operand may be omitted.
257 An omitted vector is effectively the same as a vector of no elements.
260 @samp{B} indicates a pointer to basic block structure.
263 A polynomial integer. At present this is used only for @code{SUBREG_BYTE}.
266 @samp{0} means a slot whose contents do not fit any normal category.
267 @samp{0} slots are not printed at all in dumps, and are often used in
268 special ways by small parts of the compiler.
271 There are macros to get the number of operands and the format
272 of an expression code:
275 @findex GET_RTX_LENGTH
276 @item GET_RTX_LENGTH (@var{code})
277 Number of operands of an RTX of code @var{code}.
279 @findex GET_RTX_FORMAT
280 @item GET_RTX_FORMAT (@var{code})
281 The format of an RTX of code @var{code}, as a C string.
284 Some classes of RTX codes always have the same format. For example, it
285 is safe to assume that all comparison operations have format @code{ee}.
289 All codes of this class have format @code{e}.
292 @itemx RTX_COMM_ARITH
293 @itemx RTX_COMM_COMPARE
295 All codes of these classes have format @code{ee}.
297 @item RTX_BITFIELD_OPS
299 All codes of these classes have format @code{eee}.
302 All codes of this class have formats that begin with @code{iuueiee}.
303 @xref{Insns}. Note that not all RTL objects linked onto an insn chain
304 are of class @code{RTX_INSN}.
310 You can make no assumptions about the format of these codes.
314 @section Access to Operands
316 @cindex access to operands
317 @cindex operand access
323 Operands of expressions are accessed using the macros @code{XEXP},
324 @code{XINT}, @code{XWINT} and @code{XSTR}. Each of these macros takes
325 two arguments: an expression-pointer (RTX) and an operand number
326 (counting from zero). Thus,
333 accesses operand 2 of expression @var{x}, as an expression.
340 accesses the same operand as an integer. @code{XSTR}, used in the same
341 fashion, would access it as a string.
343 Any operand can be accessed as an integer, as an expression or as a string.
344 You must choose the correct method of access for the kind of value actually
345 stored in the operand. You would do this based on the expression code of
346 the containing expression. That is also how you would know how many
349 For example, if @var{x} is an @code{int_list} expression, you know that it has
350 two operands which can be correctly accessed as @code{XINT (@var{x}, 0)}
351 and @code{XEXP (@var{x}, 1)}. Incorrect accesses like
352 @code{XEXP (@var{x}, 0)} and @code{XINT (@var{x}, 1)} would compile,
353 but would trigger an internal compiler error when rtl checking is enabled.
354 Nothing stops you from writing @code{XEXP (@var{x}, 28)} either, but
355 this will access memory past the end of the expression with
356 unpredictable results.
358 Access to operands which are vectors is more complicated. You can use the
359 macro @code{XVEC} to get the vector-pointer itself, or the macros
360 @code{XVECEXP} and @code{XVECLEN} to access the elements and length of a
365 @item XVEC (@var{exp}, @var{idx})
366 Access the vector-pointer which is operand number @var{idx} in @var{exp}.
369 @item XVECLEN (@var{exp}, @var{idx})
370 Access the length (number of elements) in the vector which is
371 in operand number @var{idx} in @var{exp}. This value is an @code{int}.
374 @item XVECEXP (@var{exp}, @var{idx}, @var{eltnum})
375 Access element number @var{eltnum} in the vector which is
376 in operand number @var{idx} in @var{exp}. This value is an RTX@.
378 It is up to you to make sure that @var{eltnum} is not negative
379 and is less than @code{XVECLEN (@var{exp}, @var{idx})}.
382 All the macros defined in this section expand into lvalues and therefore
383 can be used to assign the operands, lengths and vector elements as well as
386 @node Special Accessors
387 @section Access to Special Operands
388 @cindex access to special operands
390 Some RTL nodes have special annotations associated with them.
395 @findex MEM_ALIAS_SET
396 @item MEM_ALIAS_SET (@var{x})
397 If 0, @var{x} is not in any alias set, and may alias anything. Otherwise,
398 @var{x} can only alias @code{MEM}s in a conflicting alias set. This value
399 is set in a language-dependent manner in the front-end, and should not be
400 altered in the back-end. In some front-ends, these numbers may correspond
401 in some way to types, or other language-level entities, but they need not,
402 and the back-end makes no such assumptions.
403 These set numbers are tested with @code{alias_sets_conflict_p}.
406 @item MEM_EXPR (@var{x})
407 If this register is known to hold the value of some user-level
408 declaration, this is that tree node. It may also be a
409 @code{COMPONENT_REF}, in which case this is some field reference,
410 and @code{TREE_OPERAND (@var{x}, 0)} contains the declaration,
411 or another @code{COMPONENT_REF}, or null if there is no compile-time
412 object associated with the reference.
414 @findex MEM_OFFSET_KNOWN_P
415 @item MEM_OFFSET_KNOWN_P (@var{x})
416 True if the offset of the memory reference from @code{MEM_EXPR} is known.
417 @samp{MEM_OFFSET (@var{x})} provides the offset if so.
420 @item MEM_OFFSET (@var{x})
421 The offset from the start of @code{MEM_EXPR}. The value is only valid if
422 @samp{MEM_OFFSET_KNOWN_P (@var{x})} is true.
424 @findex MEM_SIZE_KNOWN_P
425 @item MEM_SIZE_KNOWN_P (@var{x})
426 True if the size of the memory reference is known.
427 @samp{MEM_SIZE (@var{x})} provides its size if so.
430 @item MEM_SIZE (@var{x})
431 The size in bytes of the memory reference.
432 This is mostly relevant for @code{BLKmode} references as otherwise
433 the size is implied by the mode. The value is only valid if
434 @samp{MEM_SIZE_KNOWN_P (@var{x})} is true.
437 @item MEM_ALIGN (@var{x})
438 The known alignment in bits of the memory reference.
440 @findex MEM_ADDR_SPACE
441 @item MEM_ADDR_SPACE (@var{x})
442 The address space of the memory reference. This will commonly be zero
443 for the generic address space.
448 @findex ORIGINAL_REGNO
449 @item ORIGINAL_REGNO (@var{x})
450 This field holds the number the register ``originally'' had; for a
451 pseudo register turned into a hard reg this will hold the old pseudo
455 @item REG_EXPR (@var{x})
456 If this register is known to hold the value of some user-level
457 declaration, this is that tree node.
460 @item REG_OFFSET (@var{x})
461 If this register is known to hold the value of some user-level
462 declaration, this is the offset into that logical storage.
467 @findex SYMBOL_REF_DECL
468 @item SYMBOL_REF_DECL (@var{x})
469 If the @code{symbol_ref} @var{x} was created for a @code{VAR_DECL} or
470 a @code{FUNCTION_DECL}, that tree is recorded here. If this value is
471 null, then @var{x} was created by back end code generation routines,
472 and there is no associated front end symbol table entry.
474 @code{SYMBOL_REF_DECL} may also point to a tree of class @code{'c'},
475 that is, some sort of constant. In this case, the @code{symbol_ref}
476 is an entry in the per-file constant pool; again, there is no associated
477 front end symbol table entry.
479 @findex SYMBOL_REF_CONSTANT
480 @item SYMBOL_REF_CONSTANT (@var{x})
481 If @samp{CONSTANT_POOL_ADDRESS_P (@var{x})} is true, this is the constant
482 pool entry for @var{x}. It is null otherwise.
484 @findex SYMBOL_REF_DATA
485 @item SYMBOL_REF_DATA (@var{x})
486 A field of opaque type used to store @code{SYMBOL_REF_DECL} or
487 @code{SYMBOL_REF_CONSTANT}.
489 @findex SYMBOL_REF_FLAGS
490 @item SYMBOL_REF_FLAGS (@var{x})
491 In a @code{symbol_ref}, this is used to communicate various predicates
492 about the symbol. Some of these are common enough to be computed by
493 common code, some are specific to the target. The common bits are:
496 @findex SYMBOL_REF_FUNCTION_P
497 @findex SYMBOL_FLAG_FUNCTION
498 @item SYMBOL_FLAG_FUNCTION
499 Set if the symbol refers to a function.
501 @findex SYMBOL_REF_LOCAL_P
502 @findex SYMBOL_FLAG_LOCAL
503 @item SYMBOL_FLAG_LOCAL
504 Set if the symbol is local to this ``module''.
505 See @code{TARGET_BINDS_LOCAL_P}.
507 @findex SYMBOL_REF_EXTERNAL_P
508 @findex SYMBOL_FLAG_EXTERNAL
509 @item SYMBOL_FLAG_EXTERNAL
510 Set if this symbol is not defined in this translation unit.
511 Note that this is not the inverse of @code{SYMBOL_FLAG_LOCAL}.
513 @findex SYMBOL_REF_SMALL_P
514 @findex SYMBOL_FLAG_SMALL
515 @item SYMBOL_FLAG_SMALL
516 Set if the symbol is located in the small data section.
517 See @code{TARGET_IN_SMALL_DATA_P}.
519 @findex SYMBOL_FLAG_TLS_SHIFT
520 @findex SYMBOL_REF_TLS_MODEL
521 @item SYMBOL_REF_TLS_MODEL (@var{x})
522 This is a multi-bit field accessor that returns the @code{tls_model}
523 to be used for a thread-local storage symbol. It returns zero for
524 non-thread-local symbols.
526 @findex SYMBOL_REF_HAS_BLOCK_INFO_P
527 @findex SYMBOL_FLAG_HAS_BLOCK_INFO
528 @item SYMBOL_FLAG_HAS_BLOCK_INFO
529 Set if the symbol has @code{SYMBOL_REF_BLOCK} and
530 @code{SYMBOL_REF_BLOCK_OFFSET} fields.
532 @findex SYMBOL_REF_ANCHOR_P
533 @findex SYMBOL_FLAG_ANCHOR
534 @cindex @option{-fsection-anchors}
535 @item SYMBOL_FLAG_ANCHOR
536 Set if the symbol is used as a section anchor. ``Section anchors''
537 are symbols that have a known position within an @code{object_block}
538 and that can be used to access nearby members of that block.
539 They are used to implement @option{-fsection-anchors}.
541 If this flag is set, then @code{SYMBOL_FLAG_HAS_BLOCK_INFO} will be too.
544 Bits beginning with @code{SYMBOL_FLAG_MACH_DEP} are available for
548 @findex SYMBOL_REF_BLOCK
549 @item SYMBOL_REF_BLOCK (@var{x})
550 If @samp{SYMBOL_REF_HAS_BLOCK_INFO_P (@var{x})}, this is the
551 @samp{object_block} structure to which the symbol belongs,
552 or @code{NULL} if it has not been assigned a block.
554 @findex SYMBOL_REF_BLOCK_OFFSET
555 @item SYMBOL_REF_BLOCK_OFFSET (@var{x})
556 If @samp{SYMBOL_REF_HAS_BLOCK_INFO_P (@var{x})}, this is the offset of @var{x}
557 from the first object in @samp{SYMBOL_REF_BLOCK (@var{x})}. The value is
558 negative if @var{x} has not yet been assigned to a block, or it has not
559 been given an offset within that block.
563 @section Flags in an RTL Expression
564 @cindex flags in RTL expression
566 RTL expressions contain several flags (one-bit bit-fields)
567 that are used in certain types of expression. Most often they
568 are accessed with the following macros, which expand into lvalues.
571 @findex CROSSING_JUMP_P
572 @cindex @code{jump_insn} and @samp{/j}
573 @item CROSSING_JUMP_P (@var{x})
574 Nonzero in a @code{jump_insn} if it crosses between hot and cold sections,
575 which could potentially be very far apart in the executable. The presence
576 of this flag indicates to other optimizations that this branching instruction
577 should not be ``collapsed'' into a simpler branching construct. It is used
578 when the optimization to partition basic blocks into hot and cold sections
581 @findex CONSTANT_POOL_ADDRESS_P
582 @cindex @code{symbol_ref} and @samp{/u}
583 @cindex @code{unchanging}, in @code{symbol_ref}
584 @item CONSTANT_POOL_ADDRESS_P (@var{x})
585 Nonzero in a @code{symbol_ref} if it refers to part of the current
586 function's constant pool. For most targets these addresses are in a
587 @code{.rodata} section entirely separate from the function, but for
588 some targets the addresses are close to the beginning of the function.
589 In either case GCC assumes these addresses can be addressed directly,
590 perhaps with the help of base registers.
591 Stored in the @code{unchanging} field and printed as @samp{/u}.
593 @findex INSN_ANNULLED_BRANCH_P
594 @cindex @code{jump_insn} and @samp{/u}
595 @cindex @code{call_insn} and @samp{/u}
596 @cindex @code{insn} and @samp{/u}
597 @cindex @code{unchanging}, in @code{jump_insn}, @code{call_insn} and @code{insn}
598 @item INSN_ANNULLED_BRANCH_P (@var{x})
599 In a @code{jump_insn}, @code{call_insn}, or @code{insn} indicates
600 that the branch is an annulling one. See the discussion under
601 @code{sequence} below. Stored in the @code{unchanging} field and
602 printed as @samp{/u}.
604 @findex INSN_DELETED_P
605 @cindex @code{insn} and @samp{/v}
606 @cindex @code{call_insn} and @samp{/v}
607 @cindex @code{jump_insn} and @samp{/v}
608 @cindex @code{code_label} and @samp{/v}
609 @cindex @code{jump_table_data} and @samp{/v}
610 @cindex @code{barrier} and @samp{/v}
611 @cindex @code{note} and @samp{/v}
612 @cindex @code{volatil}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{code_label}, @code{jump_table_data}, @code{barrier}, and @code{note}
613 @item INSN_DELETED_P (@var{x})
614 In an @code{insn}, @code{call_insn}, @code{jump_insn}, @code{code_label},
615 @code{jump_table_data}, @code{barrier}, or @code{note},
616 nonzero if the insn has been deleted. Stored in the
617 @code{volatil} field and printed as @samp{/v}.
619 @findex INSN_FROM_TARGET_P
620 @cindex @code{insn} and @samp{/s}
621 @cindex @code{jump_insn} and @samp{/s}
622 @cindex @code{call_insn} and @samp{/s}
623 @cindex @code{in_struct}, in @code{insn} and @code{jump_insn} and @code{call_insn}
624 @item INSN_FROM_TARGET_P (@var{x})
625 In an @code{insn} or @code{jump_insn} or @code{call_insn} in a delay
626 slot of a branch, indicates that the insn
627 is from the target of the branch. If the branch insn has
628 @code{INSN_ANNULLED_BRANCH_P} set, this insn will only be executed if
629 the branch is taken. For annulled branches with
630 @code{INSN_FROM_TARGET_P} clear, the insn will be executed only if the
631 branch is not taken. When @code{INSN_ANNULLED_BRANCH_P} is not set,
632 this insn will always be executed. Stored in the @code{in_struct}
633 field and printed as @samp{/s}.
635 @findex LABEL_PRESERVE_P
636 @cindex @code{code_label} and @samp{/i}
637 @cindex @code{note} and @samp{/i}
638 @cindex @code{in_struct}, in @code{code_label} and @code{note}
639 @item LABEL_PRESERVE_P (@var{x})
640 In a @code{code_label} or @code{note}, indicates that the label is referenced by
641 code or data not visible to the RTL of a given function.
642 Labels referenced by a non-local goto will have this bit set. Stored
643 in the @code{in_struct} field and printed as @samp{/s}.
645 @findex LABEL_REF_NONLOCAL_P
646 @cindex @code{label_ref} and @samp{/v}
647 @cindex @code{reg_label} and @samp{/v}
648 @cindex @code{volatil}, in @code{label_ref} and @code{reg_label}
649 @item LABEL_REF_NONLOCAL_P (@var{x})
650 In @code{label_ref} and @code{reg_label} expressions, nonzero if this is
651 a reference to a non-local label.
652 Stored in the @code{volatil} field and printed as @samp{/v}.
654 @findex MEM_KEEP_ALIAS_SET_P
655 @cindex @code{mem} and @samp{/j}
656 @cindex @code{jump}, in @code{mem}
657 @item MEM_KEEP_ALIAS_SET_P (@var{x})
658 In @code{mem} expressions, 1 if we should keep the alias set for this
659 mem unchanged when we access a component. Set to 1, for example, when we
660 are already in a non-addressable component of an aggregate.
661 Stored in the @code{jump} field and printed as @samp{/j}.
663 @findex MEM_VOLATILE_P
664 @cindex @code{mem} and @samp{/v}
665 @cindex @code{asm_input} and @samp{/v}
666 @cindex @code{asm_operands} and @samp{/v}
667 @cindex @code{volatil}, in @code{mem}, @code{asm_operands}, and @code{asm_input}
668 @item MEM_VOLATILE_P (@var{x})
669 In @code{mem}, @code{asm_operands}, and @code{asm_input} expressions,
670 nonzero for volatile memory references.
671 Stored in the @code{volatil} field and printed as @samp{/v}.
674 @cindex @code{mem} and @samp{/c}
675 @cindex @code{call}, in @code{mem}
676 @item MEM_NOTRAP_P (@var{x})
677 In @code{mem}, nonzero for memory references that will not trap.
678 Stored in the @code{call} field and printed as @samp{/c}.
681 @cindex @code{mem} and @samp{/f}
682 @cindex @code{frame_related}, in @code{mem}
683 @item MEM_POINTER (@var{x})
684 Nonzero in a @code{mem} if the memory reference holds a pointer.
685 Stored in the @code{frame_related} field and printed as @samp{/f}.
687 @findex MEM_READONLY_P
688 @cindex @code{mem} and @samp{/u}
689 @cindex @code{unchanging}, in @code{mem}
690 @item MEM_READONLY_P (@var{x})
691 Nonzero in a @code{mem}, if the memory is statically allocated and read-only.
693 Read-only in this context means never modified during the lifetime of the
694 program, not necessarily in ROM or in write-disabled pages. A common
695 example of the later is a shared library's global offset table. This
696 table is initialized by the runtime loader, so the memory is technically
697 writable, but after control is transferred from the runtime loader to the
698 application, this memory will never be subsequently modified.
700 Stored in the @code{unchanging} field and printed as @samp{/u}.
702 @findex PREFETCH_SCHEDULE_BARRIER_P
703 @cindex @code{prefetch} and @samp{/v}
704 @cindex @code{volatile}, in @code{prefetch}
705 @item PREFETCH_SCHEDULE_BARRIER_P (@var{x})
706 In a @code{prefetch}, indicates that the prefetch is a scheduling barrier.
707 No other INSNs will be moved over it.
708 Stored in the @code{volatil} field and printed as @samp{/v}.
710 @findex REG_FUNCTION_VALUE_P
711 @cindex @code{reg} and @samp{/i}
712 @cindex @code{return_val}, in @code{reg}
713 @item REG_FUNCTION_VALUE_P (@var{x})
714 Nonzero in a @code{reg} if it is the place in which this function's
715 value is going to be returned. (This happens only in a hard
716 register.) Stored in the @code{return_val} field and printed as
720 @cindex @code{reg} and @samp{/f}
721 @cindex @code{frame_related}, in @code{reg}
722 @item REG_POINTER (@var{x})
723 Nonzero in a @code{reg} if the register holds a pointer. Stored in the
724 @code{frame_related} field and printed as @samp{/f}.
726 @findex REG_USERVAR_P
727 @cindex @code{reg} and @samp{/v}
728 @cindex @code{volatil}, in @code{reg}
729 @item REG_USERVAR_P (@var{x})
730 In a @code{reg}, nonzero if it corresponds to a variable present in
731 the user's source code. Zero for temporaries generated internally by
732 the compiler. Stored in the @code{volatil} field and printed as
735 The same hard register may be used also for collecting the values of
736 functions called by this one, but @code{REG_FUNCTION_VALUE_P} is zero
739 @findex RTL_CONST_CALL_P
740 @cindex @code{call_insn} and @samp{/u}
741 @cindex @code{unchanging}, in @code{call_insn}
742 @item RTL_CONST_CALL_P (@var{x})
743 In a @code{call_insn} indicates that the insn represents a call to a
744 const function. Stored in the @code{unchanging} field and printed as
747 @findex RTL_PURE_CALL_P
748 @cindex @code{call_insn} and @samp{/i}
749 @cindex @code{return_val}, in @code{call_insn}
750 @item RTL_PURE_CALL_P (@var{x})
751 In a @code{call_insn} indicates that the insn represents a call to a
752 pure function. Stored in the @code{return_val} field and printed as
755 @findex RTL_CONST_OR_PURE_CALL_P
756 @cindex @code{call_insn} and @samp{/u} or @samp{/i}
757 @item RTL_CONST_OR_PURE_CALL_P (@var{x})
758 In a @code{call_insn}, true if @code{RTL_CONST_CALL_P} or
759 @code{RTL_PURE_CALL_P} is true.
761 @findex RTL_LOOPING_CONST_OR_PURE_CALL_P
762 @cindex @code{call_insn} and @samp{/c}
763 @cindex @code{call}, in @code{call_insn}
764 @item RTL_LOOPING_CONST_OR_PURE_CALL_P (@var{x})
765 In a @code{call_insn} indicates that the insn represents a possibly
766 infinite looping call to a const or pure function. Stored in the
767 @code{call} field and printed as @samp{/c}. Only true if one of
768 @code{RTL_CONST_CALL_P} or @code{RTL_PURE_CALL_P} is true.
770 @findex RTX_FRAME_RELATED_P
771 @cindex @code{insn} and @samp{/f}
772 @cindex @code{call_insn} and @samp{/f}
773 @cindex @code{jump_insn} and @samp{/f}
774 @cindex @code{barrier} and @samp{/f}
775 @cindex @code{set} and @samp{/f}
776 @cindex @code{frame_related}, in @code{insn}, @code{call_insn}, @code{jump_insn}, @code{barrier}, and @code{set}
777 @item RTX_FRAME_RELATED_P (@var{x})
778 Nonzero in an @code{insn}, @code{call_insn}, @code{jump_insn},
779 @code{barrier}, or @code{set} which is part of a function prologue
780 and sets the stack pointer, sets the frame pointer, or saves a register.
781 This flag should also be set on an instruction that sets up a temporary
782 register to use in place of the frame pointer.
783 Stored in the @code{frame_related} field and printed as @samp{/f}.
785 In particular, on RISC targets where there are limits on the sizes of
786 immediate constants, it is sometimes impossible to reach the register
787 save area directly from the stack pointer. In that case, a temporary
788 register is used that is near enough to the register save area, and the
789 Canonical Frame Address, i.e., DWARF2's logical frame pointer, register
790 must (temporarily) be changed to be this temporary register. So, the
791 instruction that sets this temporary register must be marked as
792 @code{RTX_FRAME_RELATED_P}.
794 If the marked instruction is overly complex (defined in terms of what
795 @code{dwarf2out_frame_debug_expr} can handle), you will also have to
796 create a @code{REG_FRAME_RELATED_EXPR} note and attach it to the
797 instruction. This note should contain a simple expression of the
798 computation performed by this instruction, i.e., one that
799 @code{dwarf2out_frame_debug_expr} can handle.
801 This flag is required for exception handling support on targets with RTL
804 @findex SCHED_GROUP_P
805 @cindex @code{insn} and @samp{/s}
806 @cindex @code{call_insn} and @samp{/s}
807 @cindex @code{jump_insn} and @samp{/s}
808 @cindex @code{jump_table_data} and @samp{/s}
809 @cindex @code{in_struct}, in @code{insn}, @code{call_insn}, @code{jump_insn} and @code{jump_table_data}
810 @item SCHED_GROUP_P (@var{x})
811 During instruction scheduling, in an @code{insn}, @code{call_insn},
812 @code{jump_insn} or @code{jump_table_data}, indicates that the
813 previous insn must be scheduled together with this insn. This is used to
814 ensure that certain groups of instructions will not be split up by the
815 instruction scheduling pass, for example, @code{use} insns before
816 a @code{call_insn} may not be separated from the @code{call_insn}.
817 Stored in the @code{in_struct} field and printed as @samp{/s}.
819 @findex SET_IS_RETURN_P
820 @cindex @code{insn} and @samp{/j}
821 @cindex @code{jump}, in @code{insn}
822 @item SET_IS_RETURN_P (@var{x})
823 For a @code{set}, nonzero if it is for a return.
824 Stored in the @code{jump} field and printed as @samp{/j}.
826 @findex SIBLING_CALL_P
827 @cindex @code{call_insn} and @samp{/j}
828 @cindex @code{jump}, in @code{call_insn}
829 @item SIBLING_CALL_P (@var{x})
830 For a @code{call_insn}, nonzero if the insn is a sibling call.
831 Stored in the @code{jump} field and printed as @samp{/j}.
833 @findex STRING_POOL_ADDRESS_P
834 @cindex @code{symbol_ref} and @samp{/f}
835 @cindex @code{frame_related}, in @code{symbol_ref}
836 @item STRING_POOL_ADDRESS_P (@var{x})
837 For a @code{symbol_ref} expression, nonzero if it addresses this function's
838 string constant pool.
839 Stored in the @code{frame_related} field and printed as @samp{/f}.
841 @findex SUBREG_PROMOTED_UNSIGNED_P
842 @cindex @code{subreg} and @samp{/u} and @samp{/v}
843 @cindex @code{unchanging}, in @code{subreg}
844 @cindex @code{volatil}, in @code{subreg}
845 @item SUBREG_PROMOTED_UNSIGNED_P (@var{x})
846 Returns a value greater then zero for a @code{subreg} that has
847 @code{SUBREG_PROMOTED_VAR_P} nonzero if the object being referenced is kept
848 zero-extended, zero if it is kept sign-extended, and less then zero if it is
849 extended some other way via the @code{ptr_extend} instruction.
850 Stored in the @code{unchanging}
851 field and @code{volatil} field, printed as @samp{/u} and @samp{/v}.
852 This macro may only be used to get the value it may not be used to change
853 the value. Use @code{SUBREG_PROMOTED_UNSIGNED_SET} to change the value.
855 @findex SUBREG_PROMOTED_UNSIGNED_SET
856 @cindex @code{subreg} and @samp{/u}
857 @cindex @code{unchanging}, in @code{subreg}
858 @cindex @code{volatil}, in @code{subreg}
859 @item SUBREG_PROMOTED_UNSIGNED_SET (@var{x})
860 Set the @code{unchanging} and @code{volatil} fields in a @code{subreg}
861 to reflect zero, sign, or other extension. If @code{volatil} is
862 zero, then @code{unchanging} as nonzero means zero extension and as
863 zero means sign extension. If @code{volatil} is nonzero then some
864 other type of extension was done via the @code{ptr_extend} instruction.
866 @findex SUBREG_PROMOTED_VAR_P
867 @cindex @code{subreg} and @samp{/s}
868 @cindex @code{in_struct}, in @code{subreg}
869 @item SUBREG_PROMOTED_VAR_P (@var{x})
870 Nonzero in a @code{subreg} if it was made when accessing an object that
871 was promoted to a wider mode in accord with the @code{PROMOTED_MODE} machine
872 description macro (@pxref{Storage Layout}). In this case, the mode of
873 the @code{subreg} is the declared mode of the object and the mode of
874 @code{SUBREG_REG} is the mode of the register that holds the object.
875 Promoted variables are always either sign- or zero-extended to the wider
876 mode on every assignment. Stored in the @code{in_struct} field and
877 printed as @samp{/s}.
879 @findex SYMBOL_REF_USED
880 @cindex @code{used}, in @code{symbol_ref}
881 @item SYMBOL_REF_USED (@var{x})
882 In a @code{symbol_ref}, indicates that @var{x} has been used. This is
883 normally only used to ensure that @var{x} is only declared external
884 once. Stored in the @code{used} field.
886 @findex SYMBOL_REF_WEAK
887 @cindex @code{symbol_ref} and @samp{/i}
888 @cindex @code{return_val}, in @code{symbol_ref}
889 @item SYMBOL_REF_WEAK (@var{x})
890 In a @code{symbol_ref}, indicates that @var{x} has been declared weak.
891 Stored in the @code{return_val} field and printed as @samp{/i}.
893 @findex SYMBOL_REF_FLAG
894 @cindex @code{symbol_ref} and @samp{/v}
895 @cindex @code{volatil}, in @code{symbol_ref}
896 @item SYMBOL_REF_FLAG (@var{x})
897 In a @code{symbol_ref}, this is used as a flag for machine-specific purposes.
898 Stored in the @code{volatil} field and printed as @samp{/v}.
900 Most uses of @code{SYMBOL_REF_FLAG} are historic and may be subsumed
901 by @code{SYMBOL_REF_FLAGS}. Certainly use of @code{SYMBOL_REF_FLAGS}
902 is mandatory if the target requires more than one bit of storage.
905 These are the fields to which the above macros refer:
909 @cindex @samp{/c} in RTL dump
911 In a @code{mem}, 1 means that the memory reference will not trap.
913 In a @code{call}, 1 means that this pure or const call may possibly
916 In an RTL dump, this flag is represented as @samp{/c}.
918 @findex frame_related
919 @cindex @samp{/f} in RTL dump
921 In an @code{insn} or @code{set} expression, 1 means that it is part of
922 a function prologue and sets the stack pointer, sets the frame pointer,
923 saves a register, or sets up a temporary register to use in place of the
926 In @code{reg} expressions, 1 means that the register holds a pointer.
928 In @code{mem} expressions, 1 means that the memory reference holds a pointer.
930 In @code{symbol_ref} expressions, 1 means that the reference addresses
931 this function's string constant pool.
933 In an RTL dump, this flag is represented as @samp{/f}.
936 @cindex @samp{/s} in RTL dump
938 In @code{reg} expressions, it is 1 if the register has its entire life
939 contained within the test expression of some loop.
941 In @code{subreg} expressions, 1 means that the @code{subreg} is accessing
942 an object that has had its mode promoted from a wider mode.
944 In @code{label_ref} expressions, 1 means that the referenced label is
945 outside the innermost loop containing the insn in which the @code{label_ref}
948 In @code{code_label} expressions, it is 1 if the label may never be deleted.
949 This is used for labels which are the target of non-local gotos. Such a
950 label that would have been deleted is replaced with a @code{note} of type
951 @code{NOTE_INSN_DELETED_LABEL}.
953 In an @code{insn} during dead-code elimination, 1 means that the insn is
956 In an @code{insn} or @code{jump_insn} during reorg for an insn in the
957 delay slot of a branch,
958 1 means that this insn is from the target of the branch.
960 In an @code{insn} during instruction scheduling, 1 means that this insn
961 must be scheduled as part of a group together with the previous insn.
963 In an RTL dump, this flag is represented as @samp{/s}.
966 @cindex @samp{/i} in RTL dump
968 In @code{reg} expressions, 1 means the register contains
969 the value to be returned by the current function. On
970 machines that pass parameters in registers, the same register number
971 may be used for parameters as well, but this flag is not set on such
974 In @code{symbol_ref} expressions, 1 means the referenced symbol is weak.
976 In @code{call} expressions, 1 means the call is pure.
978 In an RTL dump, this flag is represented as @samp{/i}.
981 @cindex @samp{/j} in RTL dump
983 In a @code{mem} expression, 1 means we should keep the alias set for this
984 mem unchanged when we access a component.
986 In a @code{set}, 1 means it is for a return.
988 In a @code{call_insn}, 1 means it is a sibling call.
990 In a @code{jump_insn}, 1 means it is a crossing jump.
992 In an RTL dump, this flag is represented as @samp{/j}.
995 @cindex @samp{/u} in RTL dump
997 In @code{reg} and @code{mem} expressions, 1 means
998 that the value of the expression never changes.
1000 In @code{subreg} expressions, it is 1 if the @code{subreg} references an
1001 unsigned object whose mode has been promoted to a wider mode.
1003 In an @code{insn} or @code{jump_insn} in the delay slot of a branch
1004 instruction, 1 means an annulling branch should be used.
1006 In a @code{symbol_ref} expression, 1 means that this symbol addresses
1007 something in the per-function constant pool.
1009 In a @code{call_insn} 1 means that this instruction is a call to a const
1012 In an RTL dump, this flag is represented as @samp{/u}.
1016 This flag is used directly (without an access macro) at the end of RTL
1017 generation for a function, to count the number of times an expression
1018 appears in insns. Expressions that appear more than once are copied,
1019 according to the rules for shared structure (@pxref{Sharing}).
1021 For a @code{reg}, it is used directly (without an access macro) by the
1022 leaf register renumbering code to ensure that each register is only
1025 In a @code{symbol_ref}, it indicates that an external declaration for
1026 the symbol has already been written.
1029 @cindex @samp{/v} in RTL dump
1031 @cindex volatile memory references
1032 In a @code{mem}, @code{asm_operands}, or @code{asm_input}
1033 expression, it is 1 if the memory
1034 reference is volatile. Volatile memory references may not be deleted,
1035 reordered or combined.
1037 In a @code{symbol_ref} expression, it is used for machine-specific
1040 In a @code{reg} expression, it is 1 if the value is a user-level variable.
1041 0 indicates an internal compiler temporary.
1043 In an @code{insn}, 1 means the insn has been deleted.
1045 In @code{label_ref} and @code{reg_label} expressions, 1 means a reference
1046 to a non-local label.
1048 In @code{prefetch} expressions, 1 means that the containing insn is a
1051 In an RTL dump, this flag is represented as @samp{/v}.
1055 @section Machine Modes
1056 @cindex machine modes
1058 @findex machine_mode
1059 A machine mode describes a size of data object and the representation used
1060 for it. In the C code, machine modes are represented by an enumeration
1061 type, @code{machine_mode}, defined in @file{machmode.def}. Each RTL
1062 expression has room for a machine mode and so do certain kinds of tree
1063 expressions (declarations and types, to be precise).
1065 In debugging dumps and machine descriptions, the machine mode of an RTL
1066 expression is written after the expression code with a colon to separate
1067 them. The letters @samp{mode} which appear at the end of each machine mode
1068 name are omitted. For example, @code{(reg:SI 38)} is a @code{reg}
1069 expression with machine mode @code{SImode}. If the mode is
1070 @code{VOIDmode}, it is not written at all.
1072 Here is a table of machine modes. The term ``byte'' below refers to an
1073 object of @code{BITS_PER_UNIT} bits (@pxref{Storage Layout}).
1078 ``Bit'' mode represents a single bit, for predicate registers.
1082 ``Quarter-Integer'' mode represents a single byte treated as an integer.
1086 ``Half-Integer'' mode represents a two-byte integer.
1090 ``Partial Single Integer'' mode represents an integer which occupies
1091 four bytes but which doesn't really use all four. On some machines,
1092 this is the right mode to use for pointers.
1096 ``Single Integer'' mode represents a four-byte integer.
1100 ``Partial Double Integer'' mode represents an integer which occupies
1101 eight bytes but which doesn't really use all eight. On some machines,
1102 this is the right mode to use for certain pointers.
1106 ``Double Integer'' mode represents an eight-byte integer.
1110 ``Tetra Integer'' (?) mode represents a sixteen-byte integer.
1114 ``Octa Integer'' (?) mode represents a thirty-two-byte integer.
1118 ``Hexadeca Integer'' (?) mode represents a sixty-four-byte integer.
1122 ``Quarter-Floating'' mode represents a quarter-precision (single byte)
1123 floating point number.
1127 ``Half-Floating'' mode represents a half-precision (two byte) floating
1132 ``Three-Quarter-Floating'' (?) mode represents a three-quarter-precision
1133 (three byte) floating point number.
1137 ``Single Floating'' mode represents a four byte floating point number.
1138 In the common case, of a processor with IEEE arithmetic and 8-bit bytes,
1139 this is a single-precision IEEE floating point number; it can also be
1140 used for double-precision (on processors with 16-bit bytes) and
1141 single-precision VAX and IBM types.
1145 ``Double Floating'' mode represents an eight byte floating point number.
1146 In the common case, of a processor with IEEE arithmetic and 8-bit bytes,
1147 this is a double-precision IEEE floating point number.
1151 ``Extended Floating'' mode represents an IEEE extended floating point
1152 number. This mode only has 80 meaningful bits (ten bytes). Some
1153 processors require such numbers to be padded to twelve bytes, others
1154 to sixteen; this mode is used for either.
1158 ``Single Decimal Floating'' mode represents a four byte decimal
1159 floating point number (as distinct from conventional binary floating
1164 ``Double Decimal Floating'' mode represents an eight byte decimal
1165 floating point number.
1169 ``Tetra Decimal Floating'' mode represents a sixteen byte decimal
1170 floating point number all 128 of whose bits are meaningful.
1174 ``Tetra Floating'' mode represents a sixteen byte floating point number
1175 all 128 of whose bits are meaningful. One common use is the
1176 IEEE quad-precision format.
1180 ``Quarter-Fractional'' mode represents a single byte treated as a signed
1181 fractional number. The default format is ``s.7''.
1185 ``Half-Fractional'' mode represents a two-byte signed fractional number.
1186 The default format is ``s.15''.
1190 ``Single Fractional'' mode represents a four-byte signed fractional number.
1191 The default format is ``s.31''.
1195 ``Double Fractional'' mode represents an eight-byte signed fractional number.
1196 The default format is ``s.63''.
1200 ``Tetra Fractional'' mode represents a sixteen-byte signed fractional number.
1201 The default format is ``s.127''.
1205 ``Unsigned Quarter-Fractional'' mode represents a single byte treated as an
1206 unsigned fractional number. The default format is ``.8''.
1210 ``Unsigned Half-Fractional'' mode represents a two-byte unsigned fractional
1211 number. The default format is ``.16''.
1215 ``Unsigned Single Fractional'' mode represents a four-byte unsigned fractional
1216 number. The default format is ``.32''.
1220 ``Unsigned Double Fractional'' mode represents an eight-byte unsigned
1221 fractional number. The default format is ``.64''.
1225 ``Unsigned Tetra Fractional'' mode represents a sixteen-byte unsigned
1226 fractional number. The default format is ``.128''.
1230 ``Half-Accumulator'' mode represents a two-byte signed accumulator.
1231 The default format is ``s8.7''.
1235 ``Single Accumulator'' mode represents a four-byte signed accumulator.
1236 The default format is ``s16.15''.
1240 ``Double Accumulator'' mode represents an eight-byte signed accumulator.
1241 The default format is ``s32.31''.
1245 ``Tetra Accumulator'' mode represents a sixteen-byte signed accumulator.
1246 The default format is ``s64.63''.
1250 ``Unsigned Half-Accumulator'' mode represents a two-byte unsigned accumulator.
1251 The default format is ``8.8''.
1255 ``Unsigned Single Accumulator'' mode represents a four-byte unsigned
1256 accumulator. The default format is ``16.16''.
1260 ``Unsigned Double Accumulator'' mode represents an eight-byte unsigned
1261 accumulator. The default format is ``32.32''.
1265 ``Unsigned Tetra Accumulator'' mode represents a sixteen-byte unsigned
1266 accumulator. The default format is ``64.64''.
1270 ``Condition Code'' mode represents the value of a condition code, which
1271 is a machine-specific set of bits used to represent the result of a
1272 comparison operation. Other machine-specific modes may also be used for
1273 the condition code. These modes are not used on machines that use
1274 @code{cc0} (@pxref{Condition Code}).
1278 ``Block'' mode represents values that are aggregates to which none of
1279 the other modes apply. In RTL, only memory references can have this mode,
1280 and only if they appear in string-move or vector instructions. On machines
1281 which have no such instructions, @code{BLKmode} will not appear in RTL@.
1285 Void mode means the absence of a mode or an unspecified mode.
1286 For example, RTL expressions of code @code{const_int} have mode
1287 @code{VOIDmode} because they can be taken to have whatever mode the context
1288 requires. In debugging dumps of RTL, @code{VOIDmode} is expressed by
1289 the absence of any mode.
1297 @item QCmode, HCmode, SCmode, DCmode, XCmode, TCmode
1298 These modes stand for a complex number represented as a pair of floating
1299 point values. The floating point values are in @code{QFmode},
1300 @code{HFmode}, @code{SFmode}, @code{DFmode}, @code{XFmode}, and
1301 @code{TFmode}, respectively.
1310 @item CQImode, CHImode, CSImode, CDImode, CTImode, COImode, CPSImode
1311 These modes stand for a complex number represented as a pair of integer
1312 values. The integer values are in @code{QImode}, @code{HImode},
1313 @code{SImode}, @code{DImode}, @code{TImode}, @code{OImode}, and @code{PSImode},
1318 @item BND32mode BND64mode
1319 These modes stand for bounds for pointer of 32 and 64 bit size respectively.
1320 Mode size is double pointer mode size.
1323 The machine description defines @code{Pmode} as a C macro which expands
1324 into the machine mode used for addresses. Normally this is the mode
1325 whose size is @code{BITS_PER_WORD}, @code{SImode} on 32-bit machines.
1327 The only modes which a machine description @i{must} support are
1328 @code{QImode}, and the modes corresponding to @code{BITS_PER_WORD},
1329 @code{FLOAT_TYPE_SIZE} and @code{DOUBLE_TYPE_SIZE}.
1330 The compiler will attempt to use @code{DImode} for 8-byte structures and
1331 unions, but this can be prevented by overriding the definition of
1332 @code{MAX_FIXED_MODE_SIZE}. Alternatively, you can have the compiler
1333 use @code{TImode} for 16-byte structures and unions. Likewise, you can
1334 arrange for the C type @code{short int} to avoid using @code{HImode}.
1336 @cindex mode classes
1337 Very few explicit references to machine modes remain in the compiler and
1338 these few references will soon be removed. Instead, the machine modes
1339 are divided into mode classes. These are represented by the enumeration
1340 type @code{enum mode_class} defined in @file{machmode.h}. The possible
1346 Integer modes. By default these are @code{BImode}, @code{QImode},
1347 @code{HImode}, @code{SImode}, @code{DImode}, @code{TImode}, and
1350 @findex MODE_PARTIAL_INT
1351 @item MODE_PARTIAL_INT
1352 The ``partial integer'' modes, @code{PQImode}, @code{PHImode},
1353 @code{PSImode} and @code{PDImode}.
1357 Floating point modes. By default these are @code{QFmode},
1358 @code{HFmode}, @code{TQFmode}, @code{SFmode}, @code{DFmode},
1359 @code{XFmode} and @code{TFmode}.
1361 @findex MODE_DECIMAL_FLOAT
1362 @item MODE_DECIMAL_FLOAT
1363 Decimal floating point modes. By default these are @code{SDmode},
1364 @code{DDmode} and @code{TDmode}.
1368 Signed fractional modes. By default these are @code{QQmode}, @code{HQmode},
1369 @code{SQmode}, @code{DQmode} and @code{TQmode}.
1373 Unsigned fractional modes. By default these are @code{UQQmode}, @code{UHQmode},
1374 @code{USQmode}, @code{UDQmode} and @code{UTQmode}.
1378 Signed accumulator modes. By default these are @code{HAmode},
1379 @code{SAmode}, @code{DAmode} and @code{TAmode}.
1383 Unsigned accumulator modes. By default these are @code{UHAmode},
1384 @code{USAmode}, @code{UDAmode} and @code{UTAmode}.
1386 @findex MODE_COMPLEX_INT
1387 @item MODE_COMPLEX_INT
1388 Complex integer modes. (These are not currently implemented).
1390 @findex MODE_COMPLEX_FLOAT
1391 @item MODE_COMPLEX_FLOAT
1392 Complex floating point modes. By default these are @code{QCmode},
1393 @code{HCmode}, @code{SCmode}, @code{DCmode}, @code{XCmode}, and
1398 Modes representing condition code values. These are @code{CCmode} plus
1399 any @code{CC_MODE} modes listed in the @file{@var{machine}-modes.def}.
1400 @xref{Jump Patterns},
1401 also see @ref{Condition Code}.
1403 @findex MODE_POINTER_BOUNDS
1404 @item MODE_POINTER_BOUNDS
1405 Pointer bounds modes. Used to represent values of pointer bounds type.
1406 Operations in these modes may be executed as NOPs depending on hardware
1407 features and environment setup.
1411 This is a catchall mode class for modes which don't fit into the above
1412 classes. Currently @code{VOIDmode} and @code{BLKmode} are in
1416 @cindex machine mode wrapper classes
1417 @code{machmode.h} also defines various wrapper classes that combine a
1418 @code{machine_mode} with a static assertion that a particular
1419 condition holds. The classes are:
1422 @findex scalar_int_mode
1423 @item scalar_int_mode
1424 A mode that has class @code{MODE_INT} or @code{MODE_PARTIAL_INT}.
1426 @findex scalar_float_mode
1427 @item scalar_float_mode
1428 A mode that has class @code{MODE_FLOAT} or @code{MODE_DECIMAL_FLOAT}.
1432 A mode that holds a single numerical value. In practice this means
1433 that the mode is a @code{scalar_int_mode}, is a @code{scalar_float_mode},
1434 or has class @code{MODE_FRACT}, @code{MODE_UFRACT}, @code{MODE_ACCUM},
1435 @code{MODE_UACCUM} or @code{MODE_POINTER_BOUNDS}.
1437 @findex complex_mode
1439 A mode that has class @code{MODE_COMPLEX_INT} or @code{MODE_COMPLEX_FLOAT}.
1441 @findex fixed_size_mode
1442 @item fixed_size_mode
1443 A mode whose size is known at compile time.
1446 Named modes use the most constrained of the available wrapper classes,
1447 if one exists, otherwise they use @code{machine_mode}. For example,
1448 @code{QImode} is a @code{scalar_int_mode}, @code{SFmode} is a
1449 @code{scalar_float_mode} and @code{BLKmode} is a plain
1450 @code{machine_mode}. It is possible to refer to any mode as a raw
1451 @code{machine_mode} by adding the @code{E_} prefix, where @code{E}
1452 stands for ``enumeration''. For example, the raw @code{machine_mode}
1453 names of the modes just mentioned are @code{E_QImode}, @code{E_SFmode}
1454 and @code{E_BLKmode} respectively.
1456 The wrapper classes implicitly convert to @code{machine_mode} and to any
1457 wrapper class that represents a more general condition; for example
1458 @code{scalar_int_mode} and @code{scalar_float_mode} both convert
1459 to @code{scalar_mode} and all three convert to @code{fixed_size_mode}.
1460 The classes act like @code{machine_mode}s that accept only certain
1464 @file{machmode.h} also defines a template class @code{opt_mode<@var{T}>}
1465 that holds a @code{T} or nothing, where @code{T} can be either
1466 @code{machine_mode} or one of the wrapper classes above. The main
1467 operations on an @code{opt_mode<@var{T}>} @var{x} are as follows:
1470 @item @var{x}.exists ()
1471 Return true if @var{x} holds a mode rather than nothing.
1473 @item @var{x}.exists (&@var{y})
1474 Return true if @var{x} holds a mode rather than nothing, storing the
1475 mode in @var{y} if so. @var{y} must be assignment-compatible with @var{T}.
1477 @item @var{x}.require ()
1478 Assert that @var{x} holds a mode rather than nothing and return that mode.
1480 @item @var{x} = @var{y}
1481 Set @var{x} to @var{y}, where @var{y} is a @var{T} or implicitly converts
1485 The default constructor sets an @code{opt_mode<@var{T}>} to nothing.
1486 There is also a constructor that takes an initial value of type @var{T}.
1488 It is possible to use the @file{is-a.h} accessors on a @code{machine_mode}
1489 or machine mode wrapper @var{x}:
1493 @item is_a <@var{T}> (@var{x})
1494 Return true if @var{x} meets the conditions for wrapper class @var{T}.
1496 @item is_a <@var{T}> (@var{x}, &@var{y})
1497 Return true if @var{x} meets the conditions for wrapper class @var{T},
1498 storing it in @var{y} if so. @var{y} must be assignment-compatible with
1501 @item as_a <@var{T}> (@var{x})
1502 Assert that @var{x} meets the conditions for wrapper class @var{T}
1503 and return it as a @var{T}.
1505 @item dyn_cast <@var{T}> (@var{x})
1506 Return an @code{opt_mode<@var{T}>} that holds @var{x} if @var{x} meets
1507 the conditions for wrapper class @var{T} and that holds nothing otherwise.
1510 The purpose of these wrapper classes is to give stronger static type
1511 checking. For example, if a function takes a @code{scalar_int_mode},
1512 a caller that has a general @code{machine_mode} must either check or
1513 assert that the code is indeed a scalar integer first, using one of
1514 the functions above.
1516 The wrapper classes are normal C++ classes, with user-defined
1517 constructors. Sometimes it is useful to have a POD version of
1518 the same type, particularly if the type appears in a @code{union}.
1519 The template class @code{pod_mode<@var{T}>} provides a POD version
1520 of wrapper class @var{T}. It is assignment-compatible with @var{T}
1521 and implicitly converts to both @code{machine_mode} and @var{T}.
1523 Here are some C macros that relate to machine modes:
1527 @item GET_MODE (@var{x})
1528 Returns the machine mode of the RTX @var{x}.
1531 @item PUT_MODE (@var{x}, @var{newmode})
1532 Alters the machine mode of the RTX @var{x} to be @var{newmode}.
1534 @findex NUM_MACHINE_MODES
1535 @item NUM_MACHINE_MODES
1536 Stands for the number of machine modes available on the target
1537 machine. This is one greater than the largest numeric value of any
1540 @findex GET_MODE_NAME
1541 @item GET_MODE_NAME (@var{m})
1542 Returns the name of mode @var{m} as a string.
1544 @findex GET_MODE_CLASS
1545 @item GET_MODE_CLASS (@var{m})
1546 Returns the mode class of mode @var{m}.
1548 @findex GET_MODE_WIDER_MODE
1549 @item GET_MODE_WIDER_MODE (@var{m})
1550 Returns the next wider natural mode. For example, the expression
1551 @code{GET_MODE_WIDER_MODE (QImode)} returns @code{HImode}.
1553 @findex GET_MODE_SIZE
1554 @item GET_MODE_SIZE (@var{m})
1555 Returns the size in bytes of a datum of mode @var{m}.
1557 @findex GET_MODE_BITSIZE
1558 @item GET_MODE_BITSIZE (@var{m})
1559 Returns the size in bits of a datum of mode @var{m}.
1561 @findex GET_MODE_IBIT
1562 @item GET_MODE_IBIT (@var{m})
1563 Returns the number of integral bits of a datum of fixed-point mode @var{m}.
1565 @findex GET_MODE_FBIT
1566 @item GET_MODE_FBIT (@var{m})
1567 Returns the number of fractional bits of a datum of fixed-point mode @var{m}.
1569 @findex GET_MODE_MASK
1570 @item GET_MODE_MASK (@var{m})
1571 Returns a bitmask containing 1 for all bits in a word that fit within
1572 mode @var{m}. This macro can only be used for modes whose bitsize is
1573 less than or equal to @code{HOST_BITS_PER_INT}.
1575 @findex GET_MODE_ALIGNMENT
1576 @item GET_MODE_ALIGNMENT (@var{m})
1577 Return the required alignment, in bits, for an object of mode @var{m}.
1579 @findex GET_MODE_UNIT_SIZE
1580 @item GET_MODE_UNIT_SIZE (@var{m})
1581 Returns the size in bytes of the subunits of a datum of mode @var{m}.
1582 This is the same as @code{GET_MODE_SIZE} except in the case of complex
1583 modes. For them, the unit size is the size of the real or imaginary
1586 @findex GET_MODE_NUNITS
1587 @item GET_MODE_NUNITS (@var{m})
1588 Returns the number of units contained in a mode, i.e.,
1589 @code{GET_MODE_SIZE} divided by @code{GET_MODE_UNIT_SIZE}.
1591 @findex GET_CLASS_NARROWEST_MODE
1592 @item GET_CLASS_NARROWEST_MODE (@var{c})
1593 Returns the narrowest mode in mode class @var{c}.
1596 The following 3 variables are defined on every target. They can be
1597 used to allocate buffers that are guaranteed to be large enough to
1598 hold any value that can be represented on the target. The first two
1599 can be overridden by defining them in the target's mode.def file,
1600 however, the value must be a constant that can determined very early
1601 in the compilation process. The third symbol cannot be overridden.
1604 @findex BITS_PER_UNIT
1606 The number of bits in an addressable storage unit (byte). If you do
1607 not define this, the default is 8.
1609 @findex MAX_BITSIZE_MODE_ANY_INT
1610 @item MAX_BITSIZE_MODE_ANY_INT
1611 The maximum bitsize of any mode that is used in integer math. This
1612 should be overridden by the target if it uses large integers as
1613 containers for larger vectors but otherwise never uses the contents to
1614 compute integer values.
1616 @findex MAX_BITSIZE_MODE_ANY_MODE
1617 @item MAX_BITSIZE_MODE_ANY_MODE
1618 The bitsize of the largest mode on the target. The default value is
1619 the largest mode size given in the mode definition file, which is
1620 always correct for targets whose modes have a fixed size. Targets
1621 that might increase the size of a mode beyond this default should define
1622 @code{MAX_BITSIZE_MODE_ANY_MODE} to the actual upper limit in
1623 @file{@var{machine}-modes.def}.
1628 The global variables @code{byte_mode} and @code{word_mode} contain modes
1629 whose classes are @code{MODE_INT} and whose bitsizes are either
1630 @code{BITS_PER_UNIT} or @code{BITS_PER_WORD}, respectively. On 32-bit
1631 machines, these are @code{QImode} and @code{SImode}, respectively.
1634 @section Constant Expression Types
1635 @cindex RTL constants
1636 @cindex RTL constant expression types
1638 The simplest RTL expressions are those that represent constant values.
1642 @item (const_int @var{i})
1643 This type of expression represents the integer value @var{i}. @var{i}
1644 is customarily accessed with the macro @code{INTVAL} as in
1645 @code{INTVAL (@var{exp})}, which is equivalent to @code{XWINT (@var{exp}, 0)}.
1647 Constants generated for modes with fewer bits than in
1648 @code{HOST_WIDE_INT} must be sign extended to full width (e.g., with
1649 @code{gen_int_mode}). For constants for modes with more bits than in
1650 @code{HOST_WIDE_INT} the implied high order bits of that constant are
1651 copies of the top bit. Note however that values are neither
1652 inherently signed nor inherently unsigned; where necessary, signedness
1653 is determined by the rtl operation instead.
1659 There is only one expression object for the integer value zero; it is
1660 the value of the variable @code{const0_rtx}. Likewise, the only
1661 expression for integer value one is found in @code{const1_rtx}, the only
1662 expression for integer value two is found in @code{const2_rtx}, and the
1663 only expression for integer value negative one is found in
1664 @code{constm1_rtx}. Any attempt to create an expression of code
1665 @code{const_int} and value zero, one, two or negative one will return
1666 @code{const0_rtx}, @code{const1_rtx}, @code{const2_rtx} or
1667 @code{constm1_rtx} as appropriate.
1669 @findex const_true_rtx
1670 Similarly, there is only one object for the integer whose value is
1671 @code{STORE_FLAG_VALUE}. It is found in @code{const_true_rtx}. If
1672 @code{STORE_FLAG_VALUE} is one, @code{const_true_rtx} and
1673 @code{const1_rtx} will point to the same object. If
1674 @code{STORE_FLAG_VALUE} is @minus{}1, @code{const_true_rtx} and
1675 @code{constm1_rtx} will point to the same object.
1677 @findex const_double
1678 @item (const_double:@var{m} @var{i0} @var{i1} @dots{})
1679 This represents either a floating-point constant of mode @var{m} or
1680 (on older ports that do not define
1681 @code{TARGET_SUPPORTS_WIDE_INT}) an integer constant too large to fit
1682 into @code{HOST_BITS_PER_WIDE_INT} bits but small enough to fit within
1683 twice that number of bits. In the latter case, @var{m} will be
1684 @code{VOIDmode}. For integral values constants for modes with more
1685 bits than twice the number in @code{HOST_WIDE_INT} the implied high
1686 order bits of that constant are copies of the top bit of
1687 @code{CONST_DOUBLE_HIGH}. Note however that integral values are
1688 neither inherently signed nor inherently unsigned; where necessary,
1689 signedness is determined by the rtl operation instead.
1691 On more modern ports, @code{CONST_DOUBLE} only represents floating
1692 point values. New ports define @code{TARGET_SUPPORTS_WIDE_INT} to
1693 make this designation.
1695 @findex CONST_DOUBLE_LOW
1696 If @var{m} is @code{VOIDmode}, the bits of the value are stored in
1697 @var{i0} and @var{i1}. @var{i0} is customarily accessed with the macro
1698 @code{CONST_DOUBLE_LOW} and @var{i1} with @code{CONST_DOUBLE_HIGH}.
1700 If the constant is floating point (regardless of its precision), then
1701 the number of integers used to store the value depends on the size of
1702 @code{REAL_VALUE_TYPE} (@pxref{Floating Point}). The integers
1703 represent a floating point number, but not precisely in the target
1704 machine's or host machine's floating point format. To convert them to
1705 the precise bit pattern used by the target machine, use the macro
1706 @code{REAL_VALUE_TO_TARGET_DOUBLE} and friends (@pxref{Data Output}).
1708 @findex CONST_WIDE_INT
1709 @item (const_wide_int:@var{m} @var{nunits} @var{elt0} @dots{})
1710 This contains an array of @code{HOST_WIDE_INT}s that is large enough
1711 to hold any constant that can be represented on the target. This form
1712 of rtl is only used on targets that define
1713 @code{TARGET_SUPPORTS_WIDE_INT} to be nonzero and then
1714 @code{CONST_DOUBLE}s are only used to hold floating-point values. If
1715 the target leaves @code{TARGET_SUPPORTS_WIDE_INT} defined as 0,
1716 @code{CONST_WIDE_INT}s are not used and @code{CONST_DOUBLE}s are as
1719 The values are stored in a compressed format. The higher-order
1720 0s or -1s are not represented if they are just the logical sign
1721 extension of the number that is represented.
1723 @findex CONST_WIDE_INT_VEC
1724 @item CONST_WIDE_INT_VEC (@var{code})
1725 Returns the entire array of @code{HOST_WIDE_INT}s that are used to
1726 store the value. This macro should be rarely used.
1728 @findex CONST_WIDE_INT_NUNITS
1729 @item CONST_WIDE_INT_NUNITS (@var{code})
1730 The number of @code{HOST_WIDE_INT}s used to represent the number.
1731 Note that this generally is smaller than the number of
1732 @code{HOST_WIDE_INT}s implied by the mode size.
1734 @findex CONST_WIDE_INT_ELT
1735 @item CONST_WIDE_INT_ELT (@var{code},@var{i})
1736 Returns the @code{i}th element of the array. Element 0 is contains
1737 the low order bits of the constant.
1740 @item (const_fixed:@var{m} @dots{})
1741 Represents a fixed-point constant of mode @var{m}.
1742 The operand is a data structure of type @code{struct fixed_value} and
1743 is accessed with the macro @code{CONST_FIXED_VALUE}. The high part of
1744 data is accessed with @code{CONST_FIXED_VALUE_HIGH}; the low part is
1745 accessed with @code{CONST_FIXED_VALUE_LOW}.
1747 @findex const_poly_int
1748 @item (const_poly_int:@var{m} [@var{c0} @var{c1} @dots{}])
1749 Represents a @code{poly_int}-style polynomial integer with coefficients
1750 @var{c0}, @var{c1}, @dots{}. The coefficients are @code{wide_int}-based
1751 integers rather than rtxes. @code{CONST_POLY_INT_COEFFS} gives the
1752 values of individual coefficients (which is mostly only useful in
1753 low-level routines) and @code{const_poly_int_value} gives the full
1754 @code{poly_int} value.
1756 @findex const_vector
1757 @item (const_vector:@var{m} [@var{x0} @var{x1} @dots{}])
1758 Represents a vector constant. The values in square brackets are
1759 elements of the vector, which are always @code{const_int},
1760 @code{const_wide_int}, @code{const_double} or @code{const_fixed}
1763 Each vector constant @var{v} is treated as a specific instance of an
1764 arbitrary-length sequence that itself contains
1765 @samp{CONST_VECTOR_NPATTERNS (@var{v})} interleaved patterns. Each
1766 pattern has the form:
1769 @{ @var{base0}, @var{base1}, @var{base1} + @var{step}, @var{base1} + @var{step} * 2, @dots{} @}
1772 The first three elements in each pattern are enough to determine the
1773 values of the other elements. However, if all @var{step}s are zero,
1774 only the first two elements are needed. If in addition each @var{base1}
1775 is equal to the corresponding @var{base0}, only the first element in
1776 each pattern is needed. The number of determining elements per pattern
1777 is given by @samp{CONST_VECTOR_NELTS_PER_PATTERN (@var{v})}.
1779 For example, the constant:
1782 @{ 0, 1, 2, 6, 3, 8, 4, 10, 5, 12, 6, 14, 7, 16, 8, 18 @}
1785 is interpreted as an interleaving of the sequences:
1788 @{ 0, 2, 3, 4, 5, 6, 7, 8 @}
1789 @{ 1, 6, 8, 10, 12, 14, 16, 18 @}
1792 where the sequences are represented by the following patterns:
1795 @var{base0} == 0, @var{base1} == 2, @var{step} == 1
1796 @var{base0} == 1, @var{base1} == 6, @var{step} == 2
1802 CONST_VECTOR_NPATTERNS (@var{v}) == 2
1803 CONST_VECTOR_NELTS_PER_PATTERN (@var{v}) == 3
1806 Thus the first 6 elements (@samp{@{ 0, 1, 2, 6, 3, 8 @}}) are enough
1807 to determine the whole sequence; we refer to them as the ``encoded''
1808 elements. They are the only elements present in the square brackets
1809 for variable-length @code{const_vector}s (i.e.@: for
1810 @code{const_vector}s whose mode @var{m} has a variable number of
1811 elements). However, as a convenience to code that needs to handle
1812 both @code{const_vector}s and @code{parallel}s, all elements are
1813 present in the square brackets for fixed-length @code{const_vector}s;
1814 the encoding scheme simply reduces the amount of work involved in
1815 processing constants that follow a regular pattern.
1817 Sometimes this scheme can create two possible encodings of the same
1818 vector. For example @{ 0, 1 @} could be seen as two patterns with
1819 one element each or one pattern with two elements (@var{base0} and
1820 @var{base1}). The canonical encoding is always the one with the
1821 fewest patterns or (if both encodings have the same number of
1822 petterns) the one with the fewest encoded elements.
1824 @samp{const_vector_encoding_nelts (@var{v})} gives the total number of
1825 encoded elements in @var{v}, which is 6 in the example above.
1826 @code{CONST_VECTOR_ENCODED_ELT (@var{v}, @var{i})} accesses the value
1827 of encoded element @var{i}.
1829 @samp{CONST_VECTOR_DUPLICATE_P (@var{v})} is true if @var{v} simply contains
1830 repeated instances of @samp{CONST_VECTOR_NPATTERNS (@var{v})} values. This is
1831 a shorthand for testing @samp{CONST_VECTOR_NELTS_PER_PATTERN (@var{v}) == 1}.
1833 @samp{CONST_VECTOR_STEPPED_P (@var{v})} is true if at least one
1834 pattern in @var{v} has a nonzero step. This is a shorthand for
1835 testing @samp{CONST_VECTOR_NELTS_PER_PATTERN (@var{v}) == 3}.
1837 @code{CONST_VECTOR_NUNITS (@var{v})} gives the total number of elements
1838 in @var{v}; it is a shorthand for getting the number of units in
1839 @samp{GET_MODE (@var{v})}.
1841 The utility function @code{const_vector_elt} gives the value of an
1842 arbitrary element as an @code{rtx}. @code{const_vector_int_elt} gives
1843 the same value as a @code{wide_int}.
1845 @findex const_string
1846 @item (const_string @var{str})
1847 Represents a constant string with value @var{str}. Currently this is
1848 used only for insn attributes (@pxref{Insn Attributes}) since constant
1849 strings in C are placed in memory.
1852 @item (symbol_ref:@var{mode} @var{symbol})
1853 Represents the value of an assembler label for data. @var{symbol} is
1854 a string that describes the name of the assembler label. If it starts
1855 with a @samp{*}, the label is the rest of @var{symbol} not including
1856 the @samp{*}. Otherwise, the label is @var{symbol}, usually prefixed
1859 The @code{symbol_ref} contains a mode, which is usually @code{Pmode}.
1860 Usually that is the only mode for which a symbol is directly valid.
1863 @item (label_ref:@var{mode} @var{label})
1864 Represents the value of an assembler label for code. It contains one
1865 operand, an expression, which must be a @code{code_label} or a @code{note}
1866 of type @code{NOTE_INSN_DELETED_LABEL} that appears in the instruction
1867 sequence to identify the place where the label should go.
1869 The reason for using a distinct expression type for code label
1870 references is so that jump optimization can distinguish them.
1872 The @code{label_ref} contains a mode, which is usually @code{Pmode}.
1873 Usually that is the only mode for which a label is directly valid.
1876 @item (const:@var{m} @var{exp})
1877 Represents a constant that is the result of an assembly-time
1878 arithmetic computation. The operand, @var{exp}, contains only
1879 @code{const_int}, @code{symbol_ref}, @code{label_ref} or @code{unspec}
1880 expressions, combined with @code{plus} and @code{minus}. Any such
1881 @code{unspec}s are target-specific and typically represent some form
1882 of relocation operator. @var{m} should be a valid address mode.
1885 @item (high:@var{m} @var{exp})
1886 Represents the high-order bits of @var{exp}.
1887 The number of bits is machine-dependent and is
1888 normally the number of bits specified in an instruction that initializes
1889 the high order bits of a register. It is used with @code{lo_sum} to
1890 represent the typical two-instruction sequence used in RISC machines to
1891 reference large immediate values and/or link-time constants such
1892 as global memory addresses. In the latter case, @var{m} is @code{Pmode}
1893 and @var{exp} is usually a constant expression involving @code{symbol_ref}.
1899 The macro @code{CONST0_RTX (@var{mode})} refers to an expression with
1900 value 0 in mode @var{mode}. If mode @var{mode} is of mode class
1901 @code{MODE_INT}, it returns @code{const0_rtx}. If mode @var{mode} is of
1902 mode class @code{MODE_FLOAT}, it returns a @code{CONST_DOUBLE}
1903 expression in mode @var{mode}. Otherwise, it returns a
1904 @code{CONST_VECTOR} expression in mode @var{mode}. Similarly, the macro
1905 @code{CONST1_RTX (@var{mode})} refers to an expression with value 1 in
1906 mode @var{mode} and similarly for @code{CONST2_RTX}. The
1907 @code{CONST1_RTX} and @code{CONST2_RTX} macros are undefined
1910 @node Regs and Memory
1911 @section Registers and Memory
1912 @cindex RTL register expressions
1913 @cindex RTL memory expressions
1915 Here are the RTL expression types for describing access to machine
1916 registers and to main memory.
1920 @cindex hard registers
1921 @cindex pseudo registers
1922 @item (reg:@var{m} @var{n})
1923 For small values of the integer @var{n} (those that are less than
1924 @code{FIRST_PSEUDO_REGISTER}), this stands for a reference to machine
1925 register number @var{n}: a @dfn{hard register}. For larger values of
1926 @var{n}, it stands for a temporary value or @dfn{pseudo register}.
1927 The compiler's strategy is to generate code assuming an unlimited
1928 number of such pseudo registers, and later convert them into hard
1929 registers or into memory references.
1931 @var{m} is the machine mode of the reference. It is necessary because
1932 machines can generally refer to each register in more than one mode.
1933 For example, a register may contain a full word but there may be
1934 instructions to refer to it as a half word or as a single byte, as
1935 well as instructions to refer to it as a floating point number of
1938 Even for a register that the machine can access in only one mode,
1939 the mode must always be specified.
1941 The symbol @code{FIRST_PSEUDO_REGISTER} is defined by the machine
1942 description, since the number of hard registers on the machine is an
1943 invariant characteristic of the machine. Note, however, that not
1944 all of the machine registers must be general registers. All the
1945 machine registers that can be used for storage of data are given
1946 hard register numbers, even those that can be used only in certain
1947 instructions or can hold only certain types of data.
1949 A hard register may be accessed in various modes throughout one
1950 function, but each pseudo register is given a natural mode
1951 and is accessed only in that mode. When it is necessary to describe
1952 an access to a pseudo register using a nonnatural mode, a @code{subreg}
1955 A @code{reg} expression with a machine mode that specifies more than
1956 one word of data may actually stand for several consecutive registers.
1957 If in addition the register number specifies a hardware register, then
1958 it actually represents several consecutive hardware registers starting
1959 with the specified one.
1961 Each pseudo register number used in a function's RTL code is
1962 represented by a unique @code{reg} expression.
1964 @findex FIRST_VIRTUAL_REGISTER
1965 @findex LAST_VIRTUAL_REGISTER
1966 Some pseudo register numbers, those within the range of
1967 @code{FIRST_VIRTUAL_REGISTER} to @code{LAST_VIRTUAL_REGISTER} only
1968 appear during the RTL generation phase and are eliminated before the
1969 optimization phases. These represent locations in the stack frame that
1970 cannot be determined until RTL generation for the function has been
1971 completed. The following virtual register numbers are defined:
1974 @findex VIRTUAL_INCOMING_ARGS_REGNUM
1975 @item VIRTUAL_INCOMING_ARGS_REGNUM
1976 This points to the first word of the incoming arguments passed on the
1977 stack. Normally these arguments are placed there by the caller, but the
1978 callee may have pushed some arguments that were previously passed in
1981 @cindex @code{FIRST_PARM_OFFSET} and virtual registers
1982 @cindex @code{ARG_POINTER_REGNUM} and virtual registers
1983 When RTL generation is complete, this virtual register is replaced
1984 by the sum of the register given by @code{ARG_POINTER_REGNUM} and the
1985 value of @code{FIRST_PARM_OFFSET}.
1987 @findex VIRTUAL_STACK_VARS_REGNUM
1988 @cindex @code{FRAME_GROWS_DOWNWARD} and virtual registers
1989 @item VIRTUAL_STACK_VARS_REGNUM
1990 If @code{FRAME_GROWS_DOWNWARD} is defined to a nonzero value, this points
1991 to immediately above the first variable on the stack. Otherwise, it points
1992 to the first variable on the stack.
1994 @cindex @code{TARGET_STARTING_FRAME_OFFSET} and virtual registers
1995 @cindex @code{FRAME_POINTER_REGNUM} and virtual registers
1996 @code{VIRTUAL_STACK_VARS_REGNUM} is replaced with the sum of the
1997 register given by @code{FRAME_POINTER_REGNUM} and the value
1998 @code{TARGET_STARTING_FRAME_OFFSET}.
2000 @findex VIRTUAL_STACK_DYNAMIC_REGNUM
2001 @item VIRTUAL_STACK_DYNAMIC_REGNUM
2002 This points to the location of dynamically allocated memory on the stack
2003 immediately after the stack pointer has been adjusted by the amount of
2006 @cindex @code{STACK_DYNAMIC_OFFSET} and virtual registers
2007 @cindex @code{STACK_POINTER_REGNUM} and virtual registers
2008 This virtual register is replaced by the sum of the register given by
2009 @code{STACK_POINTER_REGNUM} and the value @code{STACK_DYNAMIC_OFFSET}.
2011 @findex VIRTUAL_OUTGOING_ARGS_REGNUM
2012 @item VIRTUAL_OUTGOING_ARGS_REGNUM
2013 This points to the location in the stack at which outgoing arguments
2014 should be written when the stack is pre-pushed (arguments pushed using
2015 push insns should always use @code{STACK_POINTER_REGNUM}).
2017 @cindex @code{STACK_POINTER_OFFSET} and virtual registers
2018 This virtual register is replaced by the sum of the register given by
2019 @code{STACK_POINTER_REGNUM} and the value @code{STACK_POINTER_OFFSET}.
2023 @item (subreg:@var{m1} @var{reg:m2} @var{bytenum})
2025 @code{subreg} expressions are used to refer to a register in a machine
2026 mode other than its natural one, or to refer to one register of
2027 a multi-part @code{reg} that actually refers to several registers.
2029 Each pseudo register has a natural mode. If it is necessary to
2030 operate on it in a different mode, the register must be
2031 enclosed in a @code{subreg}.
2033 There are currently three supported types for the first operand of a
2036 @item pseudo registers
2037 This is the most common case. Most @code{subreg}s have pseudo
2038 @code{reg}s as their first operand.
2041 @code{subreg}s of @code{mem} were common in earlier versions of GCC and
2042 are still supported. During the reload pass these are replaced by plain
2043 @code{mem}s. On machines that do not do instruction scheduling, use of
2044 @code{subreg}s of @code{mem} are still used, but this is no longer
2045 recommended. Such @code{subreg}s are considered to be
2046 @code{register_operand}s rather than @code{memory_operand}s before and
2047 during reload. Because of this, the scheduling passes cannot properly
2048 schedule instructions with @code{subreg}s of @code{mem}, so for machines
2049 that do scheduling, @code{subreg}s of @code{mem} should never be used.
2050 To support this, the combine and recog passes have explicit code to
2051 inhibit the creation of @code{subreg}s of @code{mem} when
2052 @code{INSN_SCHEDULING} is defined.
2054 The use of @code{subreg}s of @code{mem} after the reload pass is an area
2055 that is not well understood and should be avoided. There is still some
2056 code in the compiler to support this, but this code has possibly rotted.
2057 This use of @code{subreg}s is discouraged and will most likely not be
2058 supported in the future.
2060 @item hard registers
2061 It is seldom necessary to wrap hard registers in @code{subreg}s; such
2062 registers would normally reduce to a single @code{reg} rtx. This use of
2063 @code{subreg}s is discouraged and may not be supported in the future.
2067 @code{subreg}s of @code{subreg}s are not supported. Using
2068 @code{simplify_gen_subreg} is the recommended way to avoid this problem.
2070 @code{subreg}s come in two distinct flavors, each having its own
2074 @item Paradoxical subregs
2075 When @var{m1} is strictly wider than @var{m2}, the @code{subreg}
2076 expression is called @dfn{paradoxical}. The canonical test for this
2077 class of @code{subreg} is:
2080 paradoxical_subreg_p (@var{m1}, @var{m2})
2083 Paradoxical @code{subreg}s can be used as both lvalues and rvalues.
2084 When used as an lvalue, the low-order bits of the source value
2085 are stored in @var{reg} and the high-order bits are discarded.
2086 When used as an rvalue, the low-order bits of the @code{subreg} are
2087 taken from @var{reg} while the high-order bits may or may not be
2090 The high-order bits of rvalues are defined in the following circumstances:
2093 @item @code{subreg}s of @code{mem}
2094 When @var{m2} is smaller than a word, the macro @code{LOAD_EXTEND_OP},
2095 can control how the high-order bits are defined.
2097 @item @code{subreg} of @code{reg}s
2098 The upper bits are defined when @code{SUBREG_PROMOTED_VAR_P} is true.
2099 @code{SUBREG_PROMOTED_UNSIGNED_P} describes what the upper bits hold.
2100 Such subregs usually represent local variables, register variables
2101 and parameter pseudo variables that have been promoted to a wider mode.
2105 @var{bytenum} is always zero for a paradoxical @code{subreg}, even on
2108 For example, the paradoxical @code{subreg}:
2111 (set (subreg:SI (reg:HI @var{x}) 0) @var{y})
2114 stores the lower 2 bytes of @var{y} in @var{x} and discards the upper
2115 2 bytes. A subsequent:
2118 (set @var{z} (subreg:SI (reg:HI @var{x}) 0))
2121 would set the lower two bytes of @var{z} to @var{y} and set the upper
2122 two bytes to an unknown value assuming @code{SUBREG_PROMOTED_VAR_P} is
2125 @item Normal subregs
2126 When @var{m1} is at least as narrow as @var{m2} the @code{subreg}
2127 expression is called @dfn{normal}.
2129 @findex REGMODE_NATURAL_SIZE
2130 Normal @code{subreg}s restrict consideration to certain bits of
2131 @var{reg}. For this purpose, @var{reg} is divided into
2132 individually-addressable blocks in which each block has:
2135 REGMODE_NATURAL_SIZE (@var{m2})
2138 bytes. Usually the value is @code{UNITS_PER_WORD}; that is,
2139 most targets usually treat each word of a register as being
2140 independently addressable.
2142 There are two types of normal @code{subreg}. If @var{m1} is known
2143 to be no bigger than a block, the @code{subreg} refers to the
2144 least-significant part (or @dfn{lowpart}) of one block of @var{reg}.
2145 If @var{m1} is known to be larger than a block, the @code{subreg} refers
2146 to two or more complete blocks.
2148 When used as an lvalue, @code{subreg} is a block-based accessor.
2149 Storing to a @code{subreg} modifies all the blocks of @var{reg} that
2150 overlap the @code{subreg}, but it leaves the other blocks of @var{reg}
2153 When storing to a normal @code{subreg} that is smaller than a block,
2154 the other bits of the referenced block are usually left in an undefined
2155 state. This laxity makes it easier to generate efficient code for
2156 such instructions. To represent an instruction that preserves all the
2157 bits outside of those in the @code{subreg}, use @code{strict_low_part}
2158 or @code{zero_extract} around the @code{subreg}.
2160 @var{bytenum} must identify the offset of the first byte of the
2161 @code{subreg} from the start of @var{reg}, assuming that @var{reg} is
2162 laid out in memory order. The memory order of bytes is defined by
2163 two target macros, @code{WORDS_BIG_ENDIAN} and @code{BYTES_BIG_ENDIAN}:
2167 @cindex @code{WORDS_BIG_ENDIAN}, effect on @code{subreg}
2168 @code{WORDS_BIG_ENDIAN}, if set to 1, says that byte number zero is
2169 part of the most significant word; otherwise, it is part of the least
2173 @cindex @code{BYTES_BIG_ENDIAN}, effect on @code{subreg}
2174 @code{BYTES_BIG_ENDIAN}, if set to 1, says that byte number zero is
2175 the most significant byte within a word; otherwise, it is the least
2176 significant byte within a word.
2179 @cindex @code{FLOAT_WORDS_BIG_ENDIAN}, (lack of) effect on @code{subreg}
2180 On a few targets, @code{FLOAT_WORDS_BIG_ENDIAN} disagrees with
2181 @code{WORDS_BIG_ENDIAN}. However, most parts of the compiler treat
2182 floating point values as if they had the same endianness as integer
2183 values. This works because they handle them solely as a collection of
2184 integer values, with no particular numerical value. Only real.c and
2185 the runtime libraries care about @code{FLOAT_WORDS_BIG_ENDIAN}.
2190 (subreg:HI (reg:SI @var{x}) 2)
2193 on a @code{BYTES_BIG_ENDIAN}, @samp{UNITS_PER_WORD == 4} target is the same as
2196 (subreg:HI (reg:SI @var{x}) 0)
2199 on a little-endian, @samp{UNITS_PER_WORD == 4} target. Both
2200 @code{subreg}s access the lower two bytes of register @var{x}.
2202 Note that the byte offset is a polynomial integer; it may not be a
2203 compile-time constant on targets with variable-sized modes. However,
2204 the restrictions above mean that there are only a certain set of
2205 acceptable offsets for a given combination of @var{m1} and @var{m2}.
2206 The compiler can always tell which blocks a valid subreg occupies, and
2207 whether the subreg is a lowpart of a block.
2211 A @code{MODE_PARTIAL_INT} mode behaves as if it were as wide as the
2212 corresponding @code{MODE_INT} mode, except that it has a number of
2213 undefined bits, which are determined by the precision of the
2216 For example, on a little-endian target which defines @code{PSImode}
2217 to have a precision of 20 bits:
2220 (subreg:PSI (reg:SI 0) 0)
2223 accesses the low 20 bits of @samp{(reg:SI 0)}.
2225 @findex REGMODE_NATURAL_SIZE
2226 Continuing with a @code{PSImode} precision of 20 bits, if we assume
2227 @samp{REGMODE_NATURAL_SIZE (DImode) <= 4},
2228 then the following two @code{subreg}s:
2231 (subreg:PSI (reg:DI 0) 0)
2232 (subreg:PSI (reg:DI 0) 4)
2235 represent accesses to the low 20 bits of the two halves of
2238 If @samp{REGMODE_NATURAL_SIZE (PSImode) <= 2} then these two @code{subreg}s:
2241 (subreg:HI (reg:PSI 0) 0)
2242 (subreg:HI (reg:PSI 0) 2)
2245 represent independent 2-byte accesses that together span the whole
2246 of @samp{(reg:PSI 0)}. Storing to the first @code{subreg} does not
2247 affect the value of the second, and vice versa, so the assignment:
2250 (set (subreg:HI (reg:PSI 0) 0) (reg:HI 4))
2253 sets the low 16 bits of @samp{(reg:PSI 0)} to @samp{(reg:HI 4)}, and
2254 the high 4 defined bits of @samp{(reg:PSI 0)} retain their
2255 original value. The behavior here is the same as for
2256 normal @code{subreg}s, when there are no
2257 @code{MODE_PARTIAL_INT} modes involved.
2259 @cindex @code{TARGET_CAN_CHANGE_MODE_CLASS} and subreg semantics
2260 The rules above apply to both pseudo @var{reg}s and hard @var{reg}s.
2261 If the semantics are not correct for particular combinations of
2262 @var{m1}, @var{m2} and hard @var{reg}, the target-specific code
2263 must ensure that those combinations are never used. For example:
2266 TARGET_CAN_CHANGE_MODE_CLASS (@var{m2}, @var{m1}, @var{class})
2269 must be false for every class @var{class} that includes @var{reg}.
2271 GCC must be able to determine at compile time whether a subreg is
2272 paradoxical, whether it occupies a whole number of blocks, or whether
2273 it is a lowpart of a block. This means that certain combinations of
2274 variable-sized mode are not permitted. For example, if @var{m2}
2275 holds @var{n} @code{SI} values, where @var{n} is greater than zero,
2276 it is not possible to form a @code{DI} @code{subreg} of it; such a
2277 @code{subreg} would be paradoxical when @var{n} is 1 but not when
2278 @var{n} is greater than 1.
2282 The first operand of a @code{subreg} expression is customarily accessed
2283 with the @code{SUBREG_REG} macro and the second operand is customarily
2284 accessed with the @code{SUBREG_BYTE} macro.
2286 It has been several years since a platform in which
2287 @code{BYTES_BIG_ENDIAN} not equal to @code{WORDS_BIG_ENDIAN} has
2288 been tested. Anyone wishing to support such a platform in the future
2289 may be confronted with code rot.
2292 @cindex scratch operands
2293 @item (scratch:@var{m})
2294 This represents a scratch register that will be required for the
2295 execution of a single instruction and not used subsequently. It is
2296 converted into a @code{reg} by either the local register allocator or
2299 @code{scratch} is usually present inside a @code{clobber} operation
2300 (@pxref{Side Effects}).
2303 @cindex condition code register
2305 This refers to the machine's condition code register. It has no
2306 operands and may not have a machine mode. There are two ways to use it:
2310 To stand for a complete set of condition code flags. This is best on
2311 most machines, where each comparison sets the entire series of flags.
2313 With this technique, @code{(cc0)} may be validly used in only two
2314 contexts: as the destination of an assignment (in test and compare
2315 instructions) and in comparison operators comparing against zero
2316 (@code{const_int} with value zero; that is to say, @code{const0_rtx}).
2319 To stand for a single flag that is the result of a single condition.
2320 This is useful on machines that have only a single flag bit, and in
2321 which comparison instructions must specify the condition to test.
2323 With this technique, @code{(cc0)} may be validly used in only two
2324 contexts: as the destination of an assignment (in test and compare
2325 instructions) where the source is a comparison operator, and as the
2326 first operand of @code{if_then_else} (in a conditional branch).
2330 There is only one expression object of code @code{cc0}; it is the
2331 value of the variable @code{cc0_rtx}. Any attempt to create an
2332 expression of code @code{cc0} will return @code{cc0_rtx}.
2334 Instructions can set the condition code implicitly. On many machines,
2335 nearly all instructions set the condition code based on the value that
2336 they compute or store. It is not necessary to record these actions
2337 explicitly in the RTL because the machine description includes a
2338 prescription for recognizing the instructions that do so (by means of
2339 the macro @code{NOTICE_UPDATE_CC}). @xref{Condition Code}. Only
2340 instructions whose sole purpose is to set the condition code, and
2341 instructions that use the condition code, need mention @code{(cc0)}.
2343 On some machines, the condition code register is given a register number
2344 and a @code{reg} is used instead of @code{(cc0)}. This is usually the
2345 preferable approach if only a small subset of instructions modify the
2346 condition code. Other machines store condition codes in general
2347 registers; in such cases a pseudo register should be used.
2349 Some machines, such as the SPARC and RS/6000, have two sets of
2350 arithmetic instructions, one that sets and one that does not set the
2351 condition code. This is best handled by normally generating the
2352 instruction that does not set the condition code, and making a pattern
2353 that both performs the arithmetic and sets the condition code register
2354 (which would not be @code{(cc0)} in this case). For examples, search
2355 for @samp{addcc} and @samp{andcc} in @file{sparc.md}.
2359 @cindex program counter
2360 This represents the machine's program counter. It has no operands and
2361 may not have a machine mode. @code{(pc)} may be validly used only in
2362 certain specific contexts in jump instructions.
2365 There is only one expression object of code @code{pc}; it is the value
2366 of the variable @code{pc_rtx}. Any attempt to create an expression of
2367 code @code{pc} will return @code{pc_rtx}.
2369 All instructions that do not jump alter the program counter implicitly
2370 by incrementing it, but there is no need to mention this in the RTL@.
2373 @item (mem:@var{m} @var{addr} @var{alias})
2374 This RTX represents a reference to main memory at an address
2375 represented by the expression @var{addr}. @var{m} specifies how large
2376 a unit of memory is accessed. @var{alias} specifies an alias set for the
2377 reference. In general two items are in different alias sets if they cannot
2378 reference the same memory address.
2380 The construct @code{(mem:BLK (scratch))} is considered to alias all
2381 other memories. Thus it may be used as a memory barrier in epilogue
2382 stack deallocation patterns.
2385 @item (concat@var{m} @var{rtx} @var{rtx})
2386 This RTX represents the concatenation of two other RTXs. This is used
2387 for complex values. It should only appear in the RTL attached to
2388 declarations and during RTL generation. It should not appear in the
2389 ordinary insn chain.
2392 @item (concatn@var{m} [@var{rtx} @dots{}])
2393 This RTX represents the concatenation of all the @var{rtx} to make a
2394 single value. Like @code{concat}, this should only appear in
2395 declarations, and not in the insn chain.
2399 @section RTL Expressions for Arithmetic
2400 @cindex arithmetic, in RTL
2401 @cindex math, in RTL
2402 @cindex RTL expressions for arithmetic
2404 Unless otherwise specified, all the operands of arithmetic expressions
2405 must be valid for mode @var{m}. An operand is valid for mode @var{m}
2406 if it has mode @var{m}, or if it is a @code{const_int} or
2407 @code{const_double} and @var{m} is a mode of class @code{MODE_INT}.
2409 For commutative binary operations, constants should be placed in the
2417 @cindex RTL addition
2418 @cindex RTL addition with signed saturation
2419 @cindex RTL addition with unsigned saturation
2420 @item (plus:@var{m} @var{x} @var{y})
2421 @itemx (ss_plus:@var{m} @var{x} @var{y})
2422 @itemx (us_plus:@var{m} @var{x} @var{y})
2424 These three expressions all represent the sum of the values
2425 represented by @var{x} and @var{y} carried out in machine mode
2426 @var{m}. They differ in their behavior on overflow of integer modes.
2427 @code{plus} wraps round modulo the width of @var{m}; @code{ss_plus}
2428 saturates at the maximum signed value representable in @var{m};
2429 @code{us_plus} saturates at the maximum unsigned value.
2431 @c ??? What happens on overflow of floating point modes?
2434 @item (lo_sum:@var{m} @var{x} @var{y})
2436 This expression represents the sum of @var{x} and the low-order bits
2437 of @var{y}. It is used with @code{high} (@pxref{Constants}) to
2438 represent the typical two-instruction sequence used in RISC machines to
2439 reference large immediate values and/or link-time constants such
2440 as global memory addresses. In the latter case, @var{m} is @code{Pmode}
2441 and @var{y} is usually a constant expression involving @code{symbol_ref}.
2443 The number of low order bits is machine-dependent but is
2444 normally the number of bits in mode @var{m} minus the number of
2445 bits set by @code{high}.
2450 @cindex RTL difference
2451 @cindex RTL subtraction
2452 @cindex RTL subtraction with signed saturation
2453 @cindex RTL subtraction with unsigned saturation
2454 @item (minus:@var{m} @var{x} @var{y})
2455 @itemx (ss_minus:@var{m} @var{x} @var{y})
2456 @itemx (us_minus:@var{m} @var{x} @var{y})
2458 These three expressions represent the result of subtracting @var{y}
2459 from @var{x}, carried out in mode @var{M}. Behavior on overflow is
2460 the same as for the three variants of @code{plus} (see above).
2463 @cindex RTL comparison
2464 @item (compare:@var{m} @var{x} @var{y})
2465 Represents the result of subtracting @var{y} from @var{x} for purposes
2466 of comparison. The result is computed without overflow, as if with
2469 Of course, machines cannot really subtract with infinite precision.
2470 However, they can pretend to do so when only the sign of the result will
2471 be used, which is the case when the result is stored in the condition
2472 code. And that is the @emph{only} way this kind of expression may
2473 validly be used: as a value to be stored in the condition codes, either
2474 @code{(cc0)} or a register. @xref{Comparisons}.
2476 The mode @var{m} is not related to the modes of @var{x} and @var{y}, but
2477 instead is the mode of the condition code value. If @code{(cc0)} is
2478 used, it is @code{VOIDmode}. Otherwise it is some mode in class
2479 @code{MODE_CC}, often @code{CCmode}. @xref{Condition Code}. If @var{m}
2480 is @code{VOIDmode} or @code{CCmode}, the operation returns sufficient
2481 information (in an unspecified format) so that any comparison operator
2482 can be applied to the result of the @code{COMPARE} operation. For other
2483 modes in class @code{MODE_CC}, the operation only returns a subset of
2486 Normally, @var{x} and @var{y} must have the same mode. Otherwise,
2487 @code{compare} is valid only if the mode of @var{x} is in class
2488 @code{MODE_INT} and @var{y} is a @code{const_int} or
2489 @code{const_double} with mode @code{VOIDmode}. The mode of @var{x}
2490 determines what mode the comparison is to be done in; thus it must not
2493 If one of the operands is a constant, it should be placed in the
2494 second operand and the comparison code adjusted as appropriate.
2496 A @code{compare} specifying two @code{VOIDmode} constants is not valid
2497 since there is no way to know in what mode the comparison is to be
2498 performed; the comparison must either be folded during the compilation
2499 or the first operand must be loaded into a register while its mode is
2506 @cindex negation with signed saturation
2507 @cindex negation with unsigned saturation
2508 @item (neg:@var{m} @var{x})
2509 @itemx (ss_neg:@var{m} @var{x})
2510 @itemx (us_neg:@var{m} @var{x})
2511 These two expressions represent the negation (subtraction from zero) of
2512 the value represented by @var{x}, carried out in mode @var{m}. They
2513 differ in the behavior on overflow of integer modes. In the case of
2514 @code{neg}, the negation of the operand may be a number not representable
2515 in mode @var{m}, in which case it is truncated to @var{m}. @code{ss_neg}
2516 and @code{us_neg} ensure that an out-of-bounds result saturates to the
2517 maximum or minimum signed or unsigned value.
2522 @cindex multiplication
2524 @cindex multiplication with signed saturation
2525 @cindex multiplication with unsigned saturation
2526 @item (mult:@var{m} @var{x} @var{y})
2527 @itemx (ss_mult:@var{m} @var{x} @var{y})
2528 @itemx (us_mult:@var{m} @var{x} @var{y})
2529 Represents the signed product of the values represented by @var{x} and
2530 @var{y} carried out in machine mode @var{m}.
2531 @code{ss_mult} and @code{us_mult} ensure that an out-of-bounds result
2532 saturates to the maximum or minimum signed or unsigned value.
2534 Some machines support a multiplication that generates a product wider
2535 than the operands. Write the pattern for this as
2538 (mult:@var{m} (sign_extend:@var{m} @var{x}) (sign_extend:@var{m} @var{y}))
2541 where @var{m} is wider than the modes of @var{x} and @var{y}, which need
2544 For unsigned widening multiplication, use the same idiom, but with
2545 @code{zero_extend} instead of @code{sign_extend}.
2548 @item (fma:@var{m} @var{x} @var{y} @var{z})
2549 Represents the @code{fma}, @code{fmaf}, and @code{fmal} builtin
2550 functions, which compute @samp{@var{x} * @var{y} + @var{z}}
2551 without doing an intermediate rounding step.
2556 @cindex signed division
2557 @cindex signed division with signed saturation
2559 @item (div:@var{m} @var{x} @var{y})
2560 @itemx (ss_div:@var{m} @var{x} @var{y})
2561 Represents the quotient in signed division of @var{x} by @var{y},
2562 carried out in machine mode @var{m}. If @var{m} is a floating point
2563 mode, it represents the exact quotient; otherwise, the integerized
2565 @code{ss_div} ensures that an out-of-bounds result saturates to the maximum
2566 or minimum signed value.
2568 Some machines have division instructions in which the operands and
2569 quotient widths are not all the same; you should represent
2570 such instructions using @code{truncate} and @code{sign_extend} as in,
2573 (truncate:@var{m1} (div:@var{m2} @var{x} (sign_extend:@var{m2} @var{y})))
2577 @cindex unsigned division
2578 @cindex unsigned division with unsigned saturation
2580 @item (udiv:@var{m} @var{x} @var{y})
2581 @itemx (us_div:@var{m} @var{x} @var{y})
2582 Like @code{div} but represents unsigned division.
2583 @code{us_div} ensures that an out-of-bounds result saturates to the maximum
2584 or minimum unsigned value.
2590 @item (mod:@var{m} @var{x} @var{y})
2591 @itemx (umod:@var{m} @var{x} @var{y})
2592 Like @code{div} and @code{udiv} but represent the remainder instead of
2597 @cindex signed minimum
2598 @cindex signed maximum
2599 @item (smin:@var{m} @var{x} @var{y})
2600 @itemx (smax:@var{m} @var{x} @var{y})
2601 Represents the smaller (for @code{smin}) or larger (for @code{smax}) of
2602 @var{x} and @var{y}, interpreted as signed values in mode @var{m}.
2603 When used with floating point, if both operands are zeros, or if either
2604 operand is @code{NaN}, then it is unspecified which of the two operands
2605 is returned as the result.
2609 @cindex unsigned minimum and maximum
2610 @item (umin:@var{m} @var{x} @var{y})
2611 @itemx (umax:@var{m} @var{x} @var{y})
2612 Like @code{smin} and @code{smax}, but the values are interpreted as unsigned
2616 @cindex complement, bitwise
2617 @cindex bitwise complement
2618 @item (not:@var{m} @var{x})
2619 Represents the bitwise complement of the value represented by @var{x},
2620 carried out in mode @var{m}, which must be a fixed-point machine mode.
2623 @cindex logical-and, bitwise
2624 @cindex bitwise logical-and
2625 @item (and:@var{m} @var{x} @var{y})
2626 Represents the bitwise logical-and of the values represented by
2627 @var{x} and @var{y}, carried out in machine mode @var{m}, which must be
2628 a fixed-point machine mode.
2631 @cindex inclusive-or, bitwise
2632 @cindex bitwise inclusive-or
2633 @item (ior:@var{m} @var{x} @var{y})
2634 Represents the bitwise inclusive-or of the values represented by @var{x}
2635 and @var{y}, carried out in machine mode @var{m}, which must be a
2639 @cindex exclusive-or, bitwise
2640 @cindex bitwise exclusive-or
2641 @item (xor:@var{m} @var{x} @var{y})
2642 Represents the bitwise exclusive-or of the values represented by @var{x}
2643 and @var{y}, carried out in machine mode @var{m}, which must be a
2651 @cindex arithmetic shift
2652 @cindex arithmetic shift with signed saturation
2653 @cindex arithmetic shift with unsigned saturation
2654 @item (ashift:@var{m} @var{x} @var{c})
2655 @itemx (ss_ashift:@var{m} @var{x} @var{c})
2656 @itemx (us_ashift:@var{m} @var{x} @var{c})
2657 These three expressions represent the result of arithmetically shifting @var{x}
2658 left by @var{c} places. They differ in their behavior on overflow of integer
2659 modes. An @code{ashift} operation is a plain shift with no special behavior
2660 in case of a change in the sign bit; @code{ss_ashift} and @code{us_ashift}
2661 saturates to the minimum or maximum representable value if any of the bits
2662 shifted out differs from the final sign bit.
2664 @var{x} have mode @var{m}, a fixed-point machine mode. @var{c}
2665 be a fixed-point mode or be a constant with mode @code{VOIDmode}; which
2666 mode is determined by the mode called for in the machine description
2667 entry for the left-shift instruction. For example, on the VAX, the mode
2668 of @var{c} is @code{QImode} regardless of @var{m}.
2673 @item (lshiftrt:@var{m} @var{x} @var{c})
2674 @itemx (ashiftrt:@var{m} @var{x} @var{c})
2675 Like @code{ashift} but for right shift. Unlike the case for left shift,
2676 these two operations are distinct.
2682 @cindex right rotate
2683 @item (rotate:@var{m} @var{x} @var{c})
2684 @itemx (rotatert:@var{m} @var{x} @var{c})
2685 Similar but represent left and right rotate. If @var{c} is a constant,
2690 @cindex absolute value
2691 @item (abs:@var{m} @var{x})
2692 @item (ss_abs:@var{m} @var{x})
2693 Represents the absolute value of @var{x}, computed in mode @var{m}.
2694 @code{ss_abs} ensures that an out-of-bounds result saturates to the
2695 maximum signed value.
2700 @item (sqrt:@var{m} @var{x})
2701 Represents the square root of @var{x}, computed in mode @var{m}.
2702 Most often @var{m} will be a floating point mode.
2705 @item (ffs:@var{m} @var{x})
2706 Represents one plus the index of the least significant 1-bit in
2707 @var{x}, represented as an integer of mode @var{m}. (The value is
2708 zero if @var{x} is zero.) The mode of @var{x} must be @var{m}
2712 @item (clrsb:@var{m} @var{x})
2713 Represents the number of redundant leading sign bits in @var{x},
2714 represented as an integer of mode @var{m}, starting at the most
2715 significant bit position. This is one less than the number of leading
2716 sign bits (either 0 or 1), with no special cases. The mode of @var{x}
2717 must be @var{m} or @code{VOIDmode}.
2720 @item (clz:@var{m} @var{x})
2721 Represents the number of leading 0-bits in @var{x}, represented as an
2722 integer of mode @var{m}, starting at the most significant bit position.
2723 If @var{x} is zero, the value is determined by
2724 @code{CLZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}). Note that this is one of
2725 the few expressions that is not invariant under widening. The mode of
2726 @var{x} must be @var{m} or @code{VOIDmode}.
2729 @item (ctz:@var{m} @var{x})
2730 Represents the number of trailing 0-bits in @var{x}, represented as an
2731 integer of mode @var{m}, starting at the least significant bit position.
2732 If @var{x} is zero, the value is determined by
2733 @code{CTZ_DEFINED_VALUE_AT_ZERO} (@pxref{Misc}). Except for this case,
2734 @code{ctz(x)} is equivalent to @code{ffs(@var{x}) - 1}. The mode of
2735 @var{x} must be @var{m} or @code{VOIDmode}.
2738 @item (popcount:@var{m} @var{x})
2739 Represents the number of 1-bits in @var{x}, represented as an integer of
2740 mode @var{m}. The mode of @var{x} must be @var{m} or @code{VOIDmode}.
2743 @item (parity:@var{m} @var{x})
2744 Represents the number of 1-bits modulo 2 in @var{x}, represented as an
2745 integer of mode @var{m}. The mode of @var{x} must be @var{m} or
2749 @item (bswap:@var{m} @var{x})
2750 Represents the value @var{x} with the order of bytes reversed, carried out
2751 in mode @var{m}, which must be a fixed-point machine mode.
2752 The mode of @var{x} must be @var{m} or @code{VOIDmode}.
2756 @section Comparison Operations
2757 @cindex RTL comparison operations
2759 Comparison operators test a relation on two operands and are considered
2760 to represent a machine-dependent nonzero value described by, but not
2761 necessarily equal to, @code{STORE_FLAG_VALUE} (@pxref{Misc})
2762 if the relation holds, or zero if it does not, for comparison operators
2763 whose results have a `MODE_INT' mode,
2764 @code{FLOAT_STORE_FLAG_VALUE} (@pxref{Misc}) if the relation holds, or
2765 zero if it does not, for comparison operators that return floating-point
2766 values, and a vector of either @code{VECTOR_STORE_FLAG_VALUE} (@pxref{Misc})
2767 if the relation holds, or of zeros if it does not, for comparison operators
2768 that return vector results.
2769 The mode of the comparison operation is independent of the mode
2770 of the data being compared. If the comparison operation is being tested
2771 (e.g., the first operand of an @code{if_then_else}), the mode must be
2774 @cindex condition codes
2775 There are two ways that comparison operations may be used. The
2776 comparison operators may be used to compare the condition codes
2777 @code{(cc0)} against zero, as in @code{(eq (cc0) (const_int 0))}. Such
2778 a construct actually refers to the result of the preceding instruction
2779 in which the condition codes were set. The instruction setting the
2780 condition code must be adjacent to the instruction using the condition
2781 code; only @code{note} insns may separate them.
2783 Alternatively, a comparison operation may directly compare two data
2784 objects. The mode of the comparison is determined by the operands; they
2785 must both be valid for a common machine mode. A comparison with both
2786 operands constant would be invalid as the machine mode could not be
2787 deduced from it, but such a comparison should never exist in RTL due to
2790 In the example above, if @code{(cc0)} were last set to
2791 @code{(compare @var{x} @var{y})}, the comparison operation is
2792 identical to @code{(eq @var{x} @var{y})}. Usually only one style
2793 of comparisons is supported on a particular machine, but the combine
2794 pass will try to merge the operations to produce the @code{eq} shown
2795 in case it exists in the context of the particular insn involved.
2797 Inequality comparisons come in two flavors, signed and unsigned. Thus,
2798 there are distinct expression codes @code{gt} and @code{gtu} for signed and
2799 unsigned greater-than. These can produce different results for the same
2800 pair of integer values: for example, 1 is signed greater-than @minus{}1 but not
2801 unsigned greater-than, because @minus{}1 when regarded as unsigned is actually
2802 @code{0xffffffff} which is greater than 1.
2804 The signed comparisons are also used for floating point values. Floating
2805 point comparisons are distinguished by the machine modes of the operands.
2810 @item (eq:@var{m} @var{x} @var{y})
2811 @code{STORE_FLAG_VALUE} if the values represented by @var{x} and @var{y}
2812 are equal, otherwise 0.
2816 @item (ne:@var{m} @var{x} @var{y})
2817 @code{STORE_FLAG_VALUE} if the values represented by @var{x} and @var{y}
2818 are not equal, otherwise 0.
2821 @cindex greater than
2822 @item (gt:@var{m} @var{x} @var{y})
2823 @code{STORE_FLAG_VALUE} if the @var{x} is greater than @var{y}. If they
2824 are fixed-point, the comparison is done in a signed sense.
2827 @cindex greater than
2828 @cindex unsigned greater than
2829 @item (gtu:@var{m} @var{x} @var{y})
2830 Like @code{gt} but does unsigned comparison, on fixed-point numbers only.
2835 @cindex unsigned less than
2836 @item (lt:@var{m} @var{x} @var{y})
2837 @itemx (ltu:@var{m} @var{x} @var{y})
2838 Like @code{gt} and @code{gtu} but test for ``less than''.
2841 @cindex greater than
2843 @cindex unsigned greater than
2844 @item (ge:@var{m} @var{x} @var{y})
2845 @itemx (geu:@var{m} @var{x} @var{y})
2846 Like @code{gt} and @code{gtu} but test for ``greater than or equal''.
2849 @cindex less than or equal
2851 @cindex unsigned less than
2852 @item (le:@var{m} @var{x} @var{y})
2853 @itemx (leu:@var{m} @var{x} @var{y})
2854 Like @code{gt} and @code{gtu} but test for ``less than or equal''.
2856 @findex if_then_else
2857 @item (if_then_else @var{cond} @var{then} @var{else})
2858 This is not a comparison operation but is listed here because it is
2859 always used in conjunction with a comparison operation. To be
2860 precise, @var{cond} is a comparison expression. This expression
2861 represents a choice, according to @var{cond}, between the value
2862 represented by @var{then} and the one represented by @var{else}.
2864 On most machines, @code{if_then_else} expressions are valid only
2865 to express conditional jumps.
2868 @item (cond [@var{test1} @var{value1} @var{test2} @var{value2} @dots{}] @var{default})
2869 Similar to @code{if_then_else}, but more general. Each of @var{test1},
2870 @var{test2}, @dots{} is performed in turn. The result of this expression is
2871 the @var{value} corresponding to the first nonzero test, or @var{default} if
2872 none of the tests are nonzero expressions.
2874 This is currently not valid for instruction patterns and is supported only
2875 for insn attributes. @xref{Insn Attributes}.
2882 Special expression codes exist to represent bit-field instructions.
2885 @findex sign_extract
2886 @cindex @code{BITS_BIG_ENDIAN}, effect on @code{sign_extract}
2887 @item (sign_extract:@var{m} @var{loc} @var{size} @var{pos})
2888 This represents a reference to a sign-extended bit-field contained or
2889 starting in @var{loc} (a memory or register reference). The bit-field
2890 is @var{size} bits wide and starts at bit @var{pos}. The compilation
2891 option @code{BITS_BIG_ENDIAN} says which end of the memory unit
2892 @var{pos} counts from.
2894 If @var{loc} is in memory, its mode must be a single-byte integer mode.
2895 If @var{loc} is in a register, the mode to use is specified by the
2896 operand of the @code{insv} or @code{extv} pattern
2897 (@pxref{Standard Names}) and is usually a full-word integer mode,
2898 which is the default if none is specified.
2900 The mode of @var{pos} is machine-specific and is also specified
2901 in the @code{insv} or @code{extv} pattern.
2903 The mode @var{m} is the same as the mode that would be used for
2904 @var{loc} if it were a register.
2906 A @code{sign_extract} cannot appear as an lvalue, or part thereof,
2909 @findex zero_extract
2910 @item (zero_extract:@var{m} @var{loc} @var{size} @var{pos})
2911 Like @code{sign_extract} but refers to an unsigned or zero-extended
2912 bit-field. The same sequence of bits are extracted, but they
2913 are filled to an entire word with zeros instead of by sign-extension.
2915 Unlike @code{sign_extract}, this type of expressions can be lvalues
2916 in RTL; they may appear on the left side of an assignment, indicating
2917 insertion of a value into the specified bit-field.
2920 @node Vector Operations
2921 @section Vector Operations
2922 @cindex vector operations
2924 All normal RTL expressions can be used with vector modes; they are
2925 interpreted as operating on each part of the vector independently.
2926 Additionally, there are a few new expressions to describe specific vector
2931 @item (vec_merge:@var{m} @var{vec1} @var{vec2} @var{items})
2932 This describes a merge operation between two vectors. The result is a vector
2933 of mode @var{m}; its elements are selected from either @var{vec1} or
2934 @var{vec2}. Which elements are selected is described by @var{items}, which
2935 is a bit mask represented by a @code{const_int}; a zero bit indicates the
2936 corresponding element in the result vector is taken from @var{vec2} while
2937 a set bit indicates it is taken from @var{vec1}.
2940 @item (vec_select:@var{m} @var{vec1} @var{selection})
2941 This describes an operation that selects parts of a vector. @var{vec1} is
2942 the source vector, and @var{selection} is a @code{parallel} that contains a
2943 @code{const_int} (or another expression, if the selection can be made at
2944 runtime) for each of the subparts of the result vector, giving the number of
2945 the source subpart that should be stored into it. The result mode @var{m} is
2946 either the submode for a single element of @var{vec1} (if only one subpart is
2947 selected), or another vector mode with that element submode (if multiple
2948 subparts are selected).
2951 @item (vec_concat:@var{m} @var{x1} @var{x2})
2952 Describes a vector concat operation. The result is a concatenation of the
2953 vectors or scalars @var{x1} and @var{x2}; its length is the sum of the
2954 lengths of the two inputs.
2956 @findex vec_duplicate
2957 @item (vec_duplicate:@var{m} @var{x})
2958 This operation converts a scalar into a vector or a small vector into a
2959 larger one by duplicating the input values. The output vector mode must have
2960 the same submodes as the input vector mode or the scalar modes, and the
2961 number of output parts must be an integer multiple of the number of input
2965 @item (vec_series:@var{m} @var{base} @var{step})
2966 This operation creates a vector in which element @var{i} is equal to
2967 @samp{@var{base} + @var{i}*@var{step}}. @var{m} must be a vector integer mode.
2971 @section Conversions
2973 @cindex machine mode conversions
2975 All conversions between machine modes must be represented by
2976 explicit conversion operations. For example, an expression
2977 which is the sum of a byte and a full word cannot be written as
2978 @code{(plus:SI (reg:QI 34) (reg:SI 80))} because the @code{plus}
2979 operation requires two operands of the same machine mode.
2980 Therefore, the byte-sized operand is enclosed in a conversion
2984 (plus:SI (sign_extend:SI (reg:QI 34)) (reg:SI 80))
2987 The conversion operation is not a mere placeholder, because there
2988 may be more than one way of converting from a given starting mode
2989 to the desired final mode. The conversion operation code says how
2992 For all conversion operations, @var{x} must not be @code{VOIDmode}
2993 because the mode in which to do the conversion would not be known.
2994 The conversion must either be done at compile-time or @var{x}
2995 must be placed into a register.
2999 @item (sign_extend:@var{m} @var{x})
3000 Represents the result of sign-extending the value @var{x}
3001 to machine mode @var{m}. @var{m} must be a fixed-point mode
3002 and @var{x} a fixed-point value of a mode narrower than @var{m}.
3005 @item (zero_extend:@var{m} @var{x})
3006 Represents the result of zero-extending the value @var{x}
3007 to machine mode @var{m}. @var{m} must be a fixed-point mode
3008 and @var{x} a fixed-point value of a mode narrower than @var{m}.
3010 @findex float_extend
3011 @item (float_extend:@var{m} @var{x})
3012 Represents the result of extending the value @var{x}
3013 to machine mode @var{m}. @var{m} must be a floating point mode
3014 and @var{x} a floating point value of a mode narrower than @var{m}.
3017 @item (truncate:@var{m} @var{x})
3018 Represents the result of truncating the value @var{x}
3019 to machine mode @var{m}. @var{m} must be a fixed-point mode
3020 and @var{x} a fixed-point value of a mode wider than @var{m}.
3023 @item (ss_truncate:@var{m} @var{x})
3024 Represents the result of truncating the value @var{x}
3025 to machine mode @var{m}, using signed saturation in the case of
3026 overflow. Both @var{m} and the mode of @var{x} must be fixed-point
3030 @item (us_truncate:@var{m} @var{x})
3031 Represents the result of truncating the value @var{x}
3032 to machine mode @var{m}, using unsigned saturation in the case of
3033 overflow. Both @var{m} and the mode of @var{x} must be fixed-point
3036 @findex float_truncate
3037 @item (float_truncate:@var{m} @var{x})
3038 Represents the result of truncating the value @var{x}
3039 to machine mode @var{m}. @var{m} must be a floating point mode
3040 and @var{x} a floating point value of a mode wider than @var{m}.
3043 @item (float:@var{m} @var{x})
3044 Represents the result of converting fixed point value @var{x},
3045 regarded as signed, to floating point mode @var{m}.
3047 @findex unsigned_float
3048 @item (unsigned_float:@var{m} @var{x})
3049 Represents the result of converting fixed point value @var{x},
3050 regarded as unsigned, to floating point mode @var{m}.
3053 @item (fix:@var{m} @var{x})
3054 When @var{m} is a floating-point mode, represents the result of
3055 converting floating point value @var{x} (valid for mode @var{m}) to an
3056 integer, still represented in floating point mode @var{m}, by rounding
3059 When @var{m} is a fixed-point mode, represents the result of
3060 converting floating point value @var{x} to mode @var{m}, regarded as
3061 signed. How rounding is done is not specified, so this operation may
3062 be used validly in compiling C code only for integer-valued operands.
3064 @findex unsigned_fix
3065 @item (unsigned_fix:@var{m} @var{x})
3066 Represents the result of converting floating point value @var{x} to
3067 fixed point mode @var{m}, regarded as unsigned. How rounding is done
3070 @findex fract_convert
3071 @item (fract_convert:@var{m} @var{x})
3072 Represents the result of converting fixed-point value @var{x} to
3073 fixed-point mode @var{m}, signed integer value @var{x} to
3074 fixed-point mode @var{m}, floating-point value @var{x} to
3075 fixed-point mode @var{m}, fixed-point value @var{x} to integer mode @var{m}
3076 regarded as signed, or fixed-point value @var{x} to floating-point mode @var{m}.
3077 When overflows or underflows happen, the results are undefined.
3080 @item (sat_fract:@var{m} @var{x})
3081 Represents the result of converting fixed-point value @var{x} to
3082 fixed-point mode @var{m}, signed integer value @var{x} to
3083 fixed-point mode @var{m}, or floating-point value @var{x} to
3084 fixed-point mode @var{m}.
3085 When overflows or underflows happen, the results are saturated to the
3086 maximum or the minimum.
3088 @findex unsigned_fract_convert
3089 @item (unsigned_fract_convert:@var{m} @var{x})
3090 Represents the result of converting fixed-point value @var{x} to
3091 integer mode @var{m} regarded as unsigned, or unsigned integer value @var{x} to
3092 fixed-point mode @var{m}.
3093 When overflows or underflows happen, the results are undefined.
3095 @findex unsigned_sat_fract
3096 @item (unsigned_sat_fract:@var{m} @var{x})
3097 Represents the result of converting unsigned integer value @var{x} to
3098 fixed-point mode @var{m}.
3099 When overflows or underflows happen, the results are saturated to the
3100 maximum or the minimum.
3103 @node RTL Declarations
3104 @section Declarations
3105 @cindex RTL declarations
3106 @cindex declarations, RTL
3108 Declaration expression codes do not represent arithmetic operations
3109 but rather state assertions about their operands.
3112 @findex strict_low_part
3113 @cindex @code{subreg}, in @code{strict_low_part}
3114 @item (strict_low_part (subreg:@var{m} (reg:@var{n} @var{r}) 0))
3115 This expression code is used in only one context: as the destination operand of a
3116 @code{set} expression. In addition, the operand of this expression
3117 must be a non-paradoxical @code{subreg} expression.
3119 The presence of @code{strict_low_part} says that the part of the
3120 register which is meaningful in mode @var{n}, but is not part of
3121 mode @var{m}, is not to be altered. Normally, an assignment to such
3122 a subreg is allowed to have undefined effects on the rest of the
3123 register when @var{m} is smaller than @samp{REGMODE_NATURAL_SIZE (@var{n})}.
3127 @section Side Effect Expressions
3128 @cindex RTL side effect expressions
3130 The expression codes described so far represent values, not actions.
3131 But machine instructions never produce values; they are meaningful
3132 only for their side effects on the state of the machine. Special
3133 expression codes are used to represent side effects.
3135 The body of an instruction is always one of these side effect codes;
3136 the codes described above, which represent values, appear only as
3137 the operands of these.
3141 @item (set @var{lval} @var{x})
3142 Represents the action of storing the value of @var{x} into the place
3143 represented by @var{lval}. @var{lval} must be an expression
3144 representing a place that can be stored in: @code{reg} (or @code{subreg},
3145 @code{strict_low_part} or @code{zero_extract}), @code{mem}, @code{pc},
3146 @code{parallel}, or @code{cc0}.
3148 If @var{lval} is a @code{reg}, @code{subreg} or @code{mem}, it has a
3149 machine mode; then @var{x} must be valid for that mode.
3151 If @var{lval} is a @code{reg} whose machine mode is less than the full
3152 width of the register, then it means that the part of the register
3153 specified by the machine mode is given the specified value and the
3154 rest of the register receives an undefined value. Likewise, if
3155 @var{lval} is a @code{subreg} whose machine mode is narrower than
3156 the mode of the register, the rest of the register can be changed in
3159 If @var{lval} is a @code{strict_low_part} of a subreg, then the part
3160 of the register specified by the machine mode of the @code{subreg} is
3161 given the value @var{x} and the rest of the register is not changed.
3163 If @var{lval} is a @code{zero_extract}, then the referenced part of
3164 the bit-field (a memory or register reference) specified by the
3165 @code{zero_extract} is given the value @var{x} and the rest of the
3166 bit-field is not changed. Note that @code{sign_extract} cannot
3167 appear in @var{lval}.
3169 If @var{lval} is @code{(cc0)}, it has no machine mode, and @var{x} may
3170 be either a @code{compare} expression or a value that may have any mode.
3171 The latter case represents a ``test'' instruction. The expression
3172 @code{(set (cc0) (reg:@var{m} @var{n}))} is equivalent to
3173 @code{(set (cc0) (compare (reg:@var{m} @var{n}) (const_int 0)))}.
3174 Use the former expression to save space during the compilation.
3176 If @var{lval} is a @code{parallel}, it is used to represent the case of
3177 a function returning a structure in multiple registers. Each element
3178 of the @code{parallel} is an @code{expr_list} whose first operand is a
3179 @code{reg} and whose second operand is a @code{const_int} representing the
3180 offset (in bytes) into the structure at which the data in that register
3181 corresponds. The first element may be null to indicate that the structure
3182 is also passed partly in memory.
3184 @cindex jump instructions and @code{set}
3185 @cindex @code{if_then_else} usage
3186 If @var{lval} is @code{(pc)}, we have a jump instruction, and the
3187 possibilities for @var{x} are very limited. It may be a
3188 @code{label_ref} expression (unconditional jump). It may be an
3189 @code{if_then_else} (conditional jump), in which case either the
3190 second or the third operand must be @code{(pc)} (for the case which
3191 does not jump) and the other of the two must be a @code{label_ref}
3192 (for the case which does jump). @var{x} may also be a @code{mem} or
3193 @code{(plus:SI (pc) @var{y})}, where @var{y} may be a @code{reg} or a
3194 @code{mem}; these unusual patterns are used to represent jumps through
3197 If @var{lval} is neither @code{(cc0)} nor @code{(pc)}, the mode of
3198 @var{lval} must not be @code{VOIDmode} and the mode of @var{x} must be
3199 valid for the mode of @var{lval}.
3203 @var{lval} is customarily accessed with the @code{SET_DEST} macro and
3204 @var{x} with the @code{SET_SRC} macro.
3208 As the sole expression in a pattern, represents a return from the
3209 current function, on machines where this can be done with one
3210 instruction, such as VAXen. On machines where a multi-instruction
3211 ``epilogue'' must be executed in order to return from the function,
3212 returning is done by jumping to a label which precedes the epilogue, and
3213 the @code{return} expression code is never used.
3215 Inside an @code{if_then_else} expression, represents the value to be
3216 placed in @code{pc} to return to the caller.
3218 Note that an insn pattern of @code{(return)} is logically equivalent to
3219 @code{(set (pc) (return))}, but the latter form is never used.
3221 @findex simple_return
3222 @item (simple_return)
3223 Like @code{(return)}, but truly represents only a function return, while
3224 @code{(return)} may represent an insn that also performs other functions
3225 of the function epilogue. Like @code{(return)}, this may also occur in
3229 @item (call @var{function} @var{nargs})
3230 Represents a function call. @var{function} is a @code{mem} expression
3231 whose address is the address of the function to be called.
3232 @var{nargs} is an expression which can be used for two purposes: on
3233 some machines it represents the number of bytes of stack argument; on
3234 others, it represents the number of argument registers.
3236 Each machine has a standard machine mode which @var{function} must
3237 have. The machine description defines macro @code{FUNCTION_MODE} to
3238 expand into the requisite mode name. The purpose of this mode is to
3239 specify what kind of addressing is allowed, on machines where the
3240 allowed kinds of addressing depend on the machine mode being
3244 @item (clobber @var{x})
3245 Represents the storing or possible storing of an unpredictable,
3246 undescribed value into @var{x}, which must be a @code{reg},
3247 @code{scratch}, @code{parallel} or @code{mem} expression.
3249 One place this is used is in string instructions that store standard
3250 values into particular hard registers. It may not be worth the
3251 trouble to describe the values that are stored, but it is essential to
3252 inform the compiler that the registers will be altered, lest it
3253 attempt to keep data in them across the string instruction.
3255 If @var{x} is @code{(mem:BLK (const_int 0))} or
3256 @code{(mem:BLK (scratch))}, it means that all memory
3257 locations must be presumed clobbered. If @var{x} is a @code{parallel},
3258 it has the same meaning as a @code{parallel} in a @code{set} expression.
3260 Note that the machine description classifies certain hard registers as
3261 ``call-clobbered''. All function call instructions are assumed by
3262 default to clobber these registers, so there is no need to use
3263 @code{clobber} expressions to indicate this fact. Also, each function
3264 call is assumed to have the potential to alter any memory location,
3265 unless the function is declared @code{const}.
3267 If the last group of expressions in a @code{parallel} are each a
3268 @code{clobber} expression whose arguments are @code{reg} or
3269 @code{match_scratch} (@pxref{RTL Template}) expressions, the combiner
3270 phase can add the appropriate @code{clobber} expressions to an insn it
3271 has constructed when doing so will cause a pattern to be matched.
3273 This feature can be used, for example, on a machine that whose multiply
3274 and add instructions don't use an MQ register but which has an
3275 add-accumulate instruction that does clobber the MQ register. Similarly,
3276 a combined instruction might require a temporary register while the
3277 constituent instructions might not.
3279 When a @code{clobber} expression for a register appears inside a
3280 @code{parallel} with other side effects, the register allocator
3281 guarantees that the register is unoccupied both before and after that
3282 insn if it is a hard register clobber. For pseudo-register clobber,
3283 the register allocator and the reload pass do not assign the same hard
3284 register to the clobber and the input operands if there is an insn
3285 alternative containing the @samp{&} constraint (@pxref{Modifiers}) for
3286 the clobber and the hard register is in register classes of the
3287 clobber in the alternative. You can clobber either a specific hard
3288 register, a pseudo register, or a @code{scratch} expression; in the
3289 latter two cases, GCC will allocate a hard register that is available
3290 there for use as a temporary.
3292 For instructions that require a temporary register, you should use
3293 @code{scratch} instead of a pseudo-register because this will allow the
3294 combiner phase to add the @code{clobber} when required. You do this by
3295 coding (@code{clobber} (@code{match_scratch} @dots{})). If you do
3296 clobber a pseudo register, use one which appears nowhere else---generate
3297 a new one each time. Otherwise, you may confuse CSE@.
3299 There is one other known use for clobbering a pseudo register in a
3300 @code{parallel}: when one of the input operands of the insn is also
3301 clobbered by the insn. In this case, using the same pseudo register in
3302 the clobber and elsewhere in the insn produces the expected results.
3306 Represents the use of the value of @var{x}. It indicates that the
3307 value in @var{x} at this point in the program is needed, even though
3308 it may not be apparent why this is so. Therefore, the compiler will
3309 not attempt to delete previous instructions whose only effect is to
3310 store a value in @var{x}. @var{x} must be a @code{reg} expression.
3312 In some situations, it may be tempting to add a @code{use} of a
3313 register in a @code{parallel} to describe a situation where the value
3314 of a special register will modify the behavior of the instruction.
3315 A hypothetical example might be a pattern for an addition that can
3316 either wrap around or use saturating addition depending on the value
3317 of a special control register:
3320 (parallel [(set (reg:SI 2) (unspec:SI [(reg:SI 3)
3327 This will not work, several of the optimizers only look at expressions
3328 locally; it is very likely that if you have multiple insns with
3329 identical inputs to the @code{unspec}, they will be optimized away even
3330 if register 1 changes in between.
3332 This means that @code{use} can @emph{only} be used to describe
3333 that the register is live. You should think twice before adding
3334 @code{use} statements, more often you will want to use @code{unspec}
3335 instead. The @code{use} RTX is most commonly useful to describe that
3336 a fixed register is implicitly used in an insn. It is also safe to use
3337 in patterns where the compiler knows for other reasons that the result
3338 of the whole pattern is variable, such as @samp{cpymem@var{m}} or
3339 @samp{call} patterns.
3341 During the reload phase, an insn that has a @code{use} as pattern
3342 can carry a reg_equal note. These @code{use} insns will be deleted
3343 before the reload phase exits.
3345 During the delayed branch scheduling phase, @var{x} may be an insn.
3346 This indicates that @var{x} previously was located at this place in the
3347 code and its data dependencies need to be taken into account. These
3348 @code{use} insns will be deleted before the delayed branch scheduling
3352 @item (parallel [@var{x0} @var{x1} @dots{}])
3353 Represents several side effects performed in parallel. The square
3354 brackets stand for a vector; the operand of @code{parallel} is a
3355 vector of expressions. @var{x0}, @var{x1} and so on are individual
3356 side effect expressions---expressions of code @code{set}, @code{call},
3357 @code{return}, @code{simple_return}, @code{clobber} or @code{use}.
3359 ``In parallel'' means that first all the values used in the individual
3360 side-effects are computed, and second all the actual side-effects are
3361 performed. For example,
3364 (parallel [(set (reg:SI 1) (mem:SI (reg:SI 1)))
3365 (set (mem:SI (reg:SI 1)) (reg:SI 1))])
3369 says unambiguously that the values of hard register 1 and the memory
3370 location addressed by it are interchanged. In both places where
3371 @code{(reg:SI 1)} appears as a memory address it refers to the value
3372 in register 1 @emph{before} the execution of the insn.
3374 It follows that it is @emph{incorrect} to use @code{parallel} and
3375 expect the result of one @code{set} to be available for the next one.
3376 For example, people sometimes attempt to represent a jump-if-zero
3377 instruction this way:
3380 (parallel [(set (cc0) (reg:SI 34))
3381 (set (pc) (if_then_else
3382 (eq (cc0) (const_int 0))
3388 But this is incorrect, because it says that the jump condition depends
3389 on the condition code value @emph{before} this instruction, not on the
3390 new value that is set by this instruction.
3392 @cindex peephole optimization, RTL representation
3393 Peephole optimization, which takes place together with final assembly
3394 code output, can produce insns whose patterns consist of a @code{parallel}
3395 whose elements are the operands needed to output the resulting
3396 assembler code---often @code{reg}, @code{mem} or constant expressions.
3397 This would not be well-formed RTL at any other stage in compilation,
3398 but it is OK then because no further optimization remains to be done.
3399 However, the definition of the macro @code{NOTICE_UPDATE_CC}, if
3400 any, must deal with such insns if you define any peephole optimizations.
3403 @item (cond_exec [@var{cond} @var{expr}])
3404 Represents a conditionally executed expression. The @var{expr} is
3405 executed only if the @var{cond} is nonzero. The @var{cond} expression
3406 must not have side-effects, but the @var{expr} may very well have
3410 @item (sequence [@var{insns} @dots{}])
3411 Represents a sequence of insns. If a @code{sequence} appears in the
3412 chain of insns, then each of the @var{insns} that appears in the sequence
3413 must be suitable for appearing in the chain of insns, i.e.@: must satisfy
3414 the @code{INSN_P} predicate.
3416 After delay-slot scheduling is completed, an insn and all the insns that
3417 reside in its delay slots are grouped together into a @code{sequence}.
3418 The insn requiring the delay slot is the first insn in the vector;
3419 subsequent insns are to be placed in the delay slot.
3421 @code{INSN_ANNULLED_BRANCH_P} is set on an insn in a delay slot to
3422 indicate that a branch insn should be used that will conditionally annul
3423 the effect of the insns in the delay slots. In such a case,
3424 @code{INSN_FROM_TARGET_P} indicates that the insn is from the target of
3425 the branch and should be executed only if the branch is taken; otherwise
3426 the insn should be executed only if the branch is not taken.
3429 Some back ends also use @code{sequence} objects for purposes other than
3430 delay-slot groups. This is not supported in the common parts of the
3431 compiler, which treat such sequences as delay-slot groups.
3433 DWARF2 Call Frame Address (CFA) adjustments are sometimes also expressed
3434 using @code{sequence} objects as the value of a @code{RTX_FRAME_RELATED_P}
3435 note. This only happens if the CFA adjustments cannot be easily derived
3436 from the pattern of the instruction to which the note is attached. In
3437 such cases, the value of the note is used instead of best-guesing the
3438 semantics of the instruction. The back end can attach notes containing
3439 a @code{sequence} of @code{set} patterns that express the effect of the
3443 These expression codes appear in place of a side effect, as the body of
3444 an insn, though strictly speaking they do not always describe side
3449 @item (asm_input @var{s})
3450 Represents literal assembler code as described by the string @var{s}.
3453 @findex unspec_volatile
3454 @item (unspec [@var{operands} @dots{}] @var{index})
3455 @itemx (unspec_volatile [@var{operands} @dots{}] @var{index})
3456 Represents a machine-specific operation on @var{operands}. @var{index}
3457 selects between multiple machine-specific operations.
3458 @code{unspec_volatile} is used for volatile operations and operations
3459 that may trap; @code{unspec} is used for other operations.
3461 These codes may appear inside a @code{pattern} of an
3462 insn, inside a @code{parallel}, or inside an expression.
3465 @item (addr_vec:@var{m} [@var{lr0} @var{lr1} @dots{}])
3466 Represents a table of jump addresses. The vector elements @var{lr0},
3467 etc., are @code{label_ref} expressions. The mode @var{m} specifies
3468 how much space is given to each address; normally @var{m} would be
3471 @findex addr_diff_vec
3472 @item (addr_diff_vec:@var{m} @var{base} [@var{lr0} @var{lr1} @dots{}] @var{min} @var{max} @var{flags})
3473 Represents a table of jump addresses expressed as offsets from
3474 @var{base}. The vector elements @var{lr0}, etc., are @code{label_ref}
3475 expressions and so is @var{base}. The mode @var{m} specifies how much
3476 space is given to each address-difference. @var{min} and @var{max}
3477 are set up by branch shortening and hold a label with a minimum and a
3478 maximum address, respectively. @var{flags} indicates the relative
3479 position of @var{base}, @var{min} and @var{max} to the containing insn
3480 and of @var{min} and @var{max} to @var{base}. See rtl.def for details.
3483 @item (prefetch:@var{m} @var{addr} @var{rw} @var{locality})
3484 Represents prefetch of memory at address @var{addr}.
3485 Operand @var{rw} is 1 if the prefetch is for data to be written, 0 otherwise;
3486 targets that do not support write prefetches should treat this as a normal
3488 Operand @var{locality} specifies the amount of temporal locality; 0 if there
3489 is none or 1, 2, or 3 for increasing levels of temporal locality;
3490 targets that do not support locality hints should ignore this.
3492 This insn is used to minimize cache-miss latency by moving data into a
3493 cache before it is accessed. It should use only non-faulting data prefetch
3498 @section Embedded Side-Effects on Addresses
3499 @cindex RTL preincrement
3500 @cindex RTL postincrement
3501 @cindex RTL predecrement
3502 @cindex RTL postdecrement
3504 Six special side-effect expression codes appear as memory addresses.
3508 @item (pre_dec:@var{m} @var{x})
3509 Represents the side effect of decrementing @var{x} by a standard
3510 amount and represents also the value that @var{x} has after being
3511 decremented. @var{x} must be a @code{reg} or @code{mem}, but most
3512 machines allow only a @code{reg}. @var{m} must be the machine mode
3513 for pointers on the machine in use. The amount @var{x} is decremented
3514 by is the length in bytes of the machine mode of the containing memory
3515 reference of which this expression serves as the address. Here is an
3519 (mem:DF (pre_dec:SI (reg:SI 39)))
3523 This says to decrement pseudo register 39 by the length of a @code{DFmode}
3524 value and use the result to address a @code{DFmode} value.
3527 @item (pre_inc:@var{m} @var{x})
3528 Similar, but specifies incrementing @var{x} instead of decrementing it.
3531 @item (post_dec:@var{m} @var{x})
3532 Represents the same side effect as @code{pre_dec} but a different
3533 value. The value represented here is the value @var{x} has @i{before}
3537 @item (post_inc:@var{m} @var{x})
3538 Similar, but specifies incrementing @var{x} instead of decrementing it.
3541 @item (post_modify:@var{m} @var{x} @var{y})
3543 Represents the side effect of setting @var{x} to @var{y} and
3544 represents @var{x} before @var{x} is modified. @var{x} must be a
3545 @code{reg} or @code{mem}, but most machines allow only a @code{reg}.
3546 @var{m} must be the machine mode for pointers on the machine in use.
3548 The expression @var{y} must be one of three forms:
3549 @code{(plus:@var{m} @var{x} @var{z})},
3550 @code{(minus:@var{m} @var{x} @var{z})}, or
3551 @code{(plus:@var{m} @var{x} @var{i})},
3552 where @var{z} is an index register and @var{i} is a constant.
3554 Here is an example of its use:
3557 (mem:SF (post_modify:SI (reg:SI 42) (plus (reg:SI 42)
3561 This says to modify pseudo register 42 by adding the contents of pseudo
3562 register 48 to it, after the use of what ever 42 points to.
3565 @item (pre_modify:@var{m} @var{x} @var{expr})
3566 Similar except side effects happen before the use.
3569 These embedded side effect expressions must be used with care. Instruction
3570 patterns may not use them. Until the @samp{flow} pass of the compiler,
3571 they may occur only to represent pushes onto the stack. The @samp{flow}
3572 pass finds cases where registers are incremented or decremented in one
3573 instruction and used as an address shortly before or after; these cases are
3574 then transformed to use pre- or post-increment or -decrement.
3576 If a register used as the operand of these expressions is used in
3577 another address in an insn, the original value of the register is used.
3578 Uses of the register outside of an address are not permitted within the
3579 same insn as a use in an embedded side effect expression because such
3580 insns behave differently on different machines and hence must be treated
3581 as ambiguous and disallowed.
3583 An instruction that can be represented with an embedded side effect
3584 could also be represented using @code{parallel} containing an additional
3585 @code{set} to describe how the address register is altered. This is not
3586 done because machines that allow these operations at all typically
3587 allow them wherever a memory address is called for. Describing them as
3588 additional parallel stores would require doubling the number of entries
3589 in the machine description.
3592 @section Assembler Instructions as Expressions
3593 @cindex assembler instructions in RTL
3595 @cindex @code{asm_operands}, usage
3596 The RTX code @code{asm_operands} represents a value produced by a
3597 user-specified assembler instruction. It is used to represent
3598 an @code{asm} statement with arguments. An @code{asm} statement with
3599 a single output operand, like this:
3602 asm ("foo %1,%2,%0" : "=a" (outputvar) : "g" (x + y), "di" (*z));
3606 is represented using a single @code{asm_operands} RTX which represents
3607 the value that is stored in @code{outputvar}:
3610 (set @var{rtx-for-outputvar}
3611 (asm_operands "foo %1,%2,%0" "a" 0
3612 [@var{rtx-for-addition-result} @var{rtx-for-*z}]
3613 [(asm_input:@var{m1} "g")
3614 (asm_input:@var{m2} "di")]))
3618 Here the operands of the @code{asm_operands} RTX are the assembler
3619 template string, the output-operand's constraint, the index-number of the
3620 output operand among the output operands specified, a vector of input
3621 operand RTX's, and a vector of input-operand modes and constraints. The
3622 mode @var{m1} is the mode of the sum @code{x+y}; @var{m2} is that of
3625 When an @code{asm} statement has multiple output values, its insn has
3626 several such @code{set} RTX's inside of a @code{parallel}. Each @code{set}
3627 contains an @code{asm_operands}; all of these share the same assembler
3628 template and vectors, but each contains the constraint for the respective
3629 output operand. They are also distinguished by the output-operand index
3630 number, which is 0, 1, @dots{} for successive output operands.
3632 @node Debug Information
3633 @section Variable Location Debug Information in RTL
3634 @cindex Variable Location Debug Information in RTL
3636 Variable tracking relies on @code{MEM_EXPR} and @code{REG_EXPR}
3637 annotations to determine what user variables memory and register
3638 references refer to.
3640 Variable tracking at assignments uses these notes only when they refer
3641 to variables that live at fixed locations (e.g., addressable
3642 variables, global non-automatic variables). For variables whose
3643 location may vary, it relies on the following types of notes.
3646 @findex var_location
3647 @item (var_location:@var{mode} @var{var} @var{exp} @var{stat})
3648 Binds variable @code{var}, a tree, to value @var{exp}, an RTL
3649 expression. It appears only in @code{NOTE_INSN_VAR_LOCATION} and
3650 @code{DEBUG_INSN}s, with slightly different meanings. @var{mode}, if
3651 present, represents the mode of @var{exp}, which is useful if it is a
3652 modeless expression. @var{stat} is only meaningful in notes,
3653 indicating whether the variable is known to be initialized or
3657 @item (debug_expr:@var{mode} @var{decl})
3658 Stands for the value bound to the @code{DEBUG_EXPR_DECL} @var{decl},
3659 that points back to it, within value expressions in
3660 @code{VAR_LOCATION} nodes.
3662 @findex debug_implicit_ptr
3663 @item (debug_implicit_ptr:@var{mode} @var{decl})
3664 Stands for the location of a @var{decl} that is no longer addressable.
3667 @item (entry_value:@var{mode} @var{decl})
3668 Stands for the value a @var{decl} had at the entry point of the
3669 containing function.
3671 @findex debug_parameter_ref
3672 @item (debug_parameter_ref:@var{mode} @var{decl})
3673 Refers to a parameter that was completely optimized out.
3675 @findex debug_marker
3676 @item (debug_marker:@var{mode})
3677 Marks a program location. With @code{VOIDmode}, it stands for the
3678 beginning of a statement, a recommended inspection point logically after
3679 all prior side effects, and before any subsequent side effects. With
3680 @code{BLKmode}, it indicates an inline entry point: the lexical block
3681 encoded in the @code{INSN_LOCATION} is the enclosing block that encloses
3682 the inlined function.
3690 The RTL representation of the code for a function is a doubly-linked
3691 chain of objects called @dfn{insns}. Insns are expressions with
3692 special codes that are used for no other purpose. Some insns are
3693 actual instructions; others represent dispatch tables for @code{switch}
3694 statements; others represent labels to jump to or various sorts of
3695 declarative information.
3697 In addition to its own specific data, each insn must have a unique
3698 id-number that distinguishes it from all other insns in the current
3699 function (after delayed branch scheduling, copies of an insn with the
3700 same id-number may be present in multiple places in a function, but
3701 these copies will always be identical and will only appear inside a
3702 @code{sequence}), and chain pointers to the preceding and following
3703 insns. These three fields occupy the same position in every insn,
3704 independent of the expression code of the insn. They could be accessed
3705 with @code{XEXP} and @code{XINT}, but instead three special macros are
3710 @item INSN_UID (@var{i})
3711 Accesses the unique id of insn @var{i}.
3714 @item PREV_INSN (@var{i})
3715 Accesses the chain pointer to the insn preceding @var{i}.
3716 If @var{i} is the first insn, this is a null pointer.
3719 @item NEXT_INSN (@var{i})
3720 Accesses the chain pointer to the insn following @var{i}.
3721 If @var{i} is the last insn, this is a null pointer.
3725 @findex get_last_insn
3726 The first insn in the chain is obtained by calling @code{get_insns}; the
3727 last insn is the result of calling @code{get_last_insn}. Within the
3728 chain delimited by these insns, the @code{NEXT_INSN} and
3729 @code{PREV_INSN} pointers must always correspond: if @var{insn} is not
3733 NEXT_INSN (PREV_INSN (@var{insn})) == @var{insn}
3737 is always true and if @var{insn} is not the last insn,
3740 PREV_INSN (NEXT_INSN (@var{insn})) == @var{insn}
3746 After delay slot scheduling, some of the insns in the chain might be
3747 @code{sequence} expressions, which contain a vector of insns. The value
3748 of @code{NEXT_INSN} in all but the last of these insns is the next insn
3749 in the vector; the value of @code{NEXT_INSN} of the last insn in the vector
3750 is the same as the value of @code{NEXT_INSN} for the @code{sequence} in
3751 which it is contained. Similar rules apply for @code{PREV_INSN}.
3753 This means that the above invariants are not necessarily true for insns
3754 inside @code{sequence} expressions. Specifically, if @var{insn} is the
3755 first insn in a @code{sequence}, @code{NEXT_INSN (PREV_INSN (@var{insn}))}
3756 is the insn containing the @code{sequence} expression, as is the value
3757 of @code{PREV_INSN (NEXT_INSN (@var{insn}))} if @var{insn} is the last
3758 insn in the @code{sequence} expression. You can use these expressions
3759 to find the containing @code{sequence} expression.
3761 Every insn has one of the following expression codes:
3766 The expression code @code{insn} is used for instructions that do not jump
3767 and do not do function calls. @code{sequence} expressions are always
3768 contained in insns with code @code{insn} even if one of those insns
3769 should jump or do function calls.
3771 Insns with code @code{insn} have four additional fields beyond the three
3772 mandatory ones listed above. These four are described in a table below.
3776 The expression code @code{jump_insn} is used for instructions that may
3777 jump (or, more generally, may contain @code{label_ref} expressions to
3778 which @code{pc} can be set in that instruction). If there is an
3779 instruction to return from the current function, it is recorded as a
3783 @code{jump_insn} insns have the same extra fields as @code{insn} insns,
3784 accessed in the same way and in addition contain a field
3785 @code{JUMP_LABEL} which is defined once jump optimization has completed.
3787 For simple conditional and unconditional jumps, this field contains
3788 the @code{code_label} to which this insn will (possibly conditionally)
3789 branch. In a more complex jump, @code{JUMP_LABEL} records one of the
3790 labels that the insn refers to; other jump target labels are recorded
3791 as @code{REG_LABEL_TARGET} notes. The exception is @code{addr_vec}
3792 and @code{addr_diff_vec}, where @code{JUMP_LABEL} is @code{NULL_RTX}
3793 and the only way to find the labels is to scan the entire body of the
3796 Return insns count as jumps, but their @code{JUMP_LABEL} is @code{RETURN}
3797 or @code{SIMPLE_RETURN}.
3801 The expression code @code{call_insn} is used for instructions that may do
3802 function calls. It is important to distinguish these instructions because
3803 they imply that certain registers and memory locations may be altered
3806 @findex CALL_INSN_FUNCTION_USAGE
3807 @code{call_insn} insns have the same extra fields as @code{insn} insns,
3808 accessed in the same way and in addition contain a field
3809 @code{CALL_INSN_FUNCTION_USAGE}, which contains a list (chain of
3810 @code{expr_list} expressions) containing @code{use}, @code{clobber} and
3811 sometimes @code{set} expressions that denote hard registers and
3812 @code{mem}s used or clobbered by the called function.
3814 A @code{mem} generally points to a stack slot in which arguments passed
3815 to the libcall by reference (@pxref{Register Arguments,
3816 TARGET_PASS_BY_REFERENCE}) are stored. If the argument is
3817 caller-copied (@pxref{Register Arguments, TARGET_CALLEE_COPIES}),
3818 the stack slot will be mentioned in @code{clobber} and @code{use}
3819 entries; if it's callee-copied, only a @code{use} will appear, and the
3820 @code{mem} may point to addresses that are not stack slots.
3822 Registers occurring inside a @code{clobber} in this list augment
3823 registers specified in @code{CALL_USED_REGISTERS} (@pxref{Register
3826 If the list contains a @code{set} involving two registers, it indicates
3827 that the function returns one of its arguments. Such a @code{set} may
3828 look like a no-op if the same register holds the argument and the return
3832 @findex CODE_LABEL_NUMBER
3834 A @code{code_label} insn represents a label that a jump insn can jump
3835 to. It contains two special fields of data in addition to the three
3836 standard ones. @code{CODE_LABEL_NUMBER} is used to hold the @dfn{label
3837 number}, a number that identifies this label uniquely among all the
3838 labels in the compilation (not just in the current function).
3839 Ultimately, the label is represented in the assembler output as an
3840 assembler label, usually of the form @samp{L@var{n}} where @var{n} is
3843 When a @code{code_label} appears in an RTL expression, it normally
3844 appears within a @code{label_ref} which represents the address of
3845 the label, as a number.
3847 Besides as a @code{code_label}, a label can also be represented as a
3848 @code{note} of type @code{NOTE_INSN_DELETED_LABEL}.
3851 The field @code{LABEL_NUSES} is only defined once the jump optimization
3852 phase is completed. It contains the number of times this label is
3853 referenced in the current function.
3856 @findex SET_LABEL_KIND
3857 @findex LABEL_ALT_ENTRY_P
3858 @cindex alternate entry points
3859 The field @code{LABEL_KIND} differentiates four different types of
3860 labels: @code{LABEL_NORMAL}, @code{LABEL_STATIC_ENTRY},
3861 @code{LABEL_GLOBAL_ENTRY}, and @code{LABEL_WEAK_ENTRY}. The only labels
3862 that do not have type @code{LABEL_NORMAL} are @dfn{alternate entry
3863 points} to the current function. These may be static (visible only in
3864 the containing translation unit), global (exposed to all translation
3865 units), or weak (global, but can be overridden by another symbol with the
3868 Much of the compiler treats all four kinds of label identically. Some
3869 of it needs to know whether or not a label is an alternate entry point;
3870 for this purpose, the macro @code{LABEL_ALT_ENTRY_P} is provided. It is
3871 equivalent to testing whether @samp{LABEL_KIND (label) == LABEL_NORMAL}.
3872 The only place that cares about the distinction between static, global,
3873 and weak alternate entry points, besides the front-end code that creates
3874 them, is the function @code{output_alternate_entry_point}, in
3877 To set the kind of a label, use the @code{SET_LABEL_KIND} macro.
3879 @findex jump_table_data
3880 @item jump_table_data
3881 A @code{jump_table_data} insn is a placeholder for the jump-table data
3882 of a @code{casesi} or @code{tablejump} insn. They are placed after
3883 a @code{tablejump_p} insn. A @code{jump_table_data} insn is not part o
3884 a basic blockm but it is associated with the basic block that ends with
3885 the @code{tablejump_p} insn. The @code{PATTERN} of a @code{jump_table_data}
3886 is always either an @code{addr_vec} or an @code{addr_diff_vec}, and a
3887 @code{jump_table_data} insn is always preceded by a @code{code_label}.
3888 The @code{tablejump_p} insn refers to that @code{code_label} via its
3893 Barriers are placed in the instruction stream when control cannot flow
3894 past them. They are placed after unconditional jump instructions to
3895 indicate that the jumps are unconditional and after calls to
3896 @code{volatile} functions, which do not return (e.g., @code{exit}).
3897 They contain no information beyond the three standard fields.
3900 @findex NOTE_LINE_NUMBER
3901 @findex NOTE_SOURCE_FILE
3903 @code{note} insns are used to represent additional debugging and
3904 declarative information. They contain two nonstandard fields, an
3905 integer which is accessed with the macro @code{NOTE_LINE_NUMBER} and a
3906 string accessed with @code{NOTE_SOURCE_FILE}.
3908 If @code{NOTE_LINE_NUMBER} is positive, the note represents the
3909 position of a source line and @code{NOTE_SOURCE_FILE} is the source file name
3910 that the line came from. These notes control generation of line
3911 number data in the assembler output.
3913 Otherwise, @code{NOTE_LINE_NUMBER} is not really a line number but a
3914 code with one of the following values (and @code{NOTE_SOURCE_FILE}
3915 must contain a null pointer):
3918 @findex NOTE_INSN_DELETED
3919 @item NOTE_INSN_DELETED
3920 Such a note is completely ignorable. Some passes of the compiler
3921 delete insns by altering them into notes of this kind.
3923 @findex NOTE_INSN_DELETED_LABEL
3924 @item NOTE_INSN_DELETED_LABEL
3925 This marks what used to be a @code{code_label}, but was not used for other
3926 purposes than taking its address and was transformed to mark that no
3929 @findex NOTE_INSN_BLOCK_BEG
3930 @findex NOTE_INSN_BLOCK_END
3931 @item NOTE_INSN_BLOCK_BEG
3932 @itemx NOTE_INSN_BLOCK_END
3933 These types of notes indicate the position of the beginning and end
3934 of a level of scoping of variable names. They control the output
3935 of debugging information.
3937 @findex NOTE_INSN_EH_REGION_BEG
3938 @findex NOTE_INSN_EH_REGION_END
3939 @item NOTE_INSN_EH_REGION_BEG
3940 @itemx NOTE_INSN_EH_REGION_END
3941 These types of notes indicate the position of the beginning and end of a
3942 level of scoping for exception handling. @code{NOTE_EH_HANDLER}
3943 identifies which region is associated with these notes.
3945 @findex NOTE_INSN_FUNCTION_BEG
3946 @item NOTE_INSN_FUNCTION_BEG
3947 Appears at the start of the function body, after the function
3950 @findex NOTE_INSN_VAR_LOCATION
3951 @findex NOTE_VAR_LOCATION
3952 @item NOTE_INSN_VAR_LOCATION
3953 This note is used to generate variable location debugging information.
3954 It indicates that the user variable in its @code{VAR_LOCATION} operand
3955 is at the location given in the RTL expression, or holds a value that
3956 can be computed by evaluating the RTL expression from that static
3957 point in the program up to the next such note for the same user
3960 @findex NOTE_INSN_BEGIN_STMT
3961 @item NOTE_INSN_BEGIN_STMT
3962 This note is used to generate @code{is_stmt} markers in line number
3963 debugging information. It indicates the beginning of a user
3966 @findex NOTE_INSN_INLINE_ENTRY
3967 @item NOTE_INSN_INLINE_ENTRY
3968 This note is used to generate @code{entry_pc} for inlined subroutines in
3969 debugging information. It indicates an inspection point at which all
3970 arguments for the inlined function have been bound, and before its first
3975 These codes are printed symbolically when they appear in debugging dumps.
3978 @findex INSN_VAR_LOCATION
3980 The expression code @code{debug_insn} is used for pseudo-instructions
3981 that hold debugging information for variable tracking at assignments
3982 (see @option{-fvar-tracking-assignments} option). They are the RTL
3983 representation of @code{GIMPLE_DEBUG} statements
3984 (@ref{@code{GIMPLE_DEBUG}}), with a @code{VAR_LOCATION} operand that
3985 binds a user variable tree to an RTL representation of the
3986 @code{value} in the corresponding statement. A @code{DEBUG_EXPR} in
3987 it stands for the value bound to the corresponding
3988 @code{DEBUG_EXPR_DECL}.
3990 @code{GIMPLE_DEBUG_BEGIN_STMT} and @code{GIMPLE_DEBUG_INLINE_ENTRY} are
3991 expanded to RTL as a @code{DEBUG_INSN} with a @code{DEBUG_MARKER}
3992 @code{PATTERN}; the difference is the RTL mode: the former's
3993 @code{DEBUG_MARKER} is @code{VOIDmode}, whereas the latter is
3994 @code{BLKmode}; information about the inlined function can be taken from
3995 the lexical block encoded in the @code{INSN_LOCATION}. These
3996 @code{DEBUG_INSN}s, that do not carry @code{VAR_LOCATION} information,
3997 just @code{DEBUG_MARKER}s, can be detected by testing
3998 @code{DEBUG_MARKER_INSN_P}, whereas those that do can be recognized as
3999 @code{DEBUG_BIND_INSN_P}.
4001 Throughout optimization passes, @code{DEBUG_INSN}s are not reordered
4002 with respect to each other, particularly during scheduling. Binding
4003 information is kept in pseudo-instruction form, so that, unlike notes,
4004 it gets the same treatment and adjustments that regular instructions
4005 would. It is the variable tracking pass that turns these
4006 pseudo-instructions into @code{NOTE_INSN_VAR_LOCATION},
4007 @code{NOTE_INSN_BEGIN_STMT} and @code{NOTE_INSN_INLINE_ENTRY} notes,
4008 analyzing control flow, value equivalences and changes to registers and
4009 memory referenced in value expressions, propagating the values of debug
4010 temporaries and determining expressions that can be used to compute the
4011 value of each user variable at as many points (ranges, actually) in the
4012 program as possible.
4014 Unlike @code{NOTE_INSN_VAR_LOCATION}, the value expression in an
4015 @code{INSN_VAR_LOCATION} denotes a value at that specific point in the
4016 program, rather than an expression that can be evaluated at any later
4017 point before an overriding @code{VAR_LOCATION} is encountered. E.g.,
4018 if a user variable is bound to a @code{REG} and then a subsequent insn
4019 modifies the @code{REG}, the note location would keep mapping the user
4020 variable to the register across the insn, whereas the insn location
4021 would keep the variable bound to the value, so that the variable
4022 tracking pass would emit another location note for the variable at the
4023 point in which the register is modified.
4027 @cindex @code{TImode}, in @code{insn}
4028 @cindex @code{HImode}, in @code{insn}
4029 @cindex @code{QImode}, in @code{insn}
4030 The machine mode of an insn is normally @code{VOIDmode}, but some
4031 phases use the mode for various purposes.
4033 The common subexpression elimination pass sets the mode of an insn to
4034 @code{QImode} when it is the first insn in a block that has already
4037 The second Haifa scheduling pass, for targets that can multiple issue,
4038 sets the mode of an insn to @code{TImode} when it is believed that the
4039 instruction begins an issue group. That is, when the instruction
4040 cannot issue simultaneously with the previous. This may be relied on
4041 by later passes, in particular machine-dependent reorg.
4043 Here is a table of the extra fields of @code{insn}, @code{jump_insn}
4044 and @code{call_insn} insns:
4048 @item PATTERN (@var{i})
4049 An expression for the side effect performed by this insn. This must
4050 be one of the following codes: @code{set}, @code{call}, @code{use},
4051 @code{clobber}, @code{return}, @code{simple_return}, @code{asm_input},
4052 @code{asm_output}, @code{addr_vec}, @code{addr_diff_vec},
4053 @code{trap_if}, @code{unspec}, @code{unspec_volatile},
4054 @code{parallel}, @code{cond_exec}, or @code{sequence}. If it is a
4055 @code{parallel}, each element of the @code{parallel} must be one these
4056 codes, except that @code{parallel} expressions cannot be nested and
4057 @code{addr_vec} and @code{addr_diff_vec} are not permitted inside a
4058 @code{parallel} expression.
4061 @item INSN_CODE (@var{i})
4062 An integer that says which pattern in the machine description matches
4063 this insn, or @minus{}1 if the matching has not yet been attempted.
4065 Such matching is never attempted and this field remains @minus{}1 on an insn
4066 whose pattern consists of a single @code{use}, @code{clobber},
4067 @code{asm_input}, @code{addr_vec} or @code{addr_diff_vec} expression.
4069 @findex asm_noperands
4070 Matching is also never attempted on insns that result from an @code{asm}
4071 statement. These contain at least one @code{asm_operands} expression.
4072 The function @code{asm_noperands} returns a non-negative value for
4075 In the debugging output, this field is printed as a number followed by
4076 a symbolic representation that locates the pattern in the @file{md}
4077 file as some small positive or negative offset from a named pattern.
4080 @item LOG_LINKS (@var{i})
4081 A list (chain of @code{insn_list} expressions) giving information about
4082 dependencies between instructions within a basic block. Neither a jump
4083 nor a label may come between the related insns. These are only used by
4084 the schedulers and by combine. This is a deprecated data structure.
4085 Def-use and use-def chains are now preferred.
4088 @item REG_NOTES (@var{i})
4089 A list (chain of @code{expr_list}, @code{insn_list} and @code{int_list}
4090 expressions) giving miscellaneous information about the insn. It is often
4091 information pertaining to the registers used in this insn.
4094 The @code{LOG_LINKS} field of an insn is a chain of @code{insn_list}
4095 expressions. Each of these has two operands: the first is an insn,
4096 and the second is another @code{insn_list} expression (the next one in
4097 the chain). The last @code{insn_list} in the chain has a null pointer
4098 as second operand. The significant thing about the chain is which
4099 insns appear in it (as first operands of @code{insn_list}
4100 expressions). Their order is not significant.
4102 This list is originally set up by the flow analysis pass; it is a null
4103 pointer until then. Flow only adds links for those data dependencies
4104 which can be used for instruction combination. For each insn, the flow
4105 analysis pass adds a link to insns which store into registers values
4106 that are used for the first time in this insn.
4108 The @code{REG_NOTES} field of an insn is a chain similar to the
4109 @code{LOG_LINKS} field but it includes @code{expr_list} and @code{int_list}
4110 expressions in addition to @code{insn_list} expressions. There are several
4111 kinds of register notes, which are distinguished by the machine mode, which
4112 in a register note is really understood as being an @code{enum reg_note}.
4113 The first operand @var{op} of the note is data whose meaning depends on
4116 @findex REG_NOTE_KIND
4117 @findex PUT_REG_NOTE_KIND
4118 The macro @code{REG_NOTE_KIND (@var{x})} returns the kind of
4119 register note. Its counterpart, the macro @code{PUT_REG_NOTE_KIND
4120 (@var{x}, @var{newkind})} sets the register note type of @var{x} to be
4123 Register notes are of three classes: They may say something about an
4124 input to an insn, they may say something about an output of an insn, or
4125 they may create a linkage between two insns. There are also a set
4126 of values that are only used in @code{LOG_LINKS}.
4128 These register notes annotate inputs to an insn:
4133 The value in @var{op} dies in this insn; that is to say, altering the
4134 value immediately after this insn would not affect the future behavior
4137 It does not follow that the register @var{op} has no useful value after
4138 this insn since @var{op} is not necessarily modified by this insn.
4139 Rather, no subsequent instruction uses the contents of @var{op}.
4143 The register @var{op} being set by this insn will not be used in a
4144 subsequent insn. This differs from a @code{REG_DEAD} note, which
4145 indicates that the value in an input will not be used subsequently.
4146 These two notes are independent; both may be present for the same
4151 The register @var{op} is incremented (or decremented; at this level
4152 there is no distinction) by an embedded side effect inside this insn.
4153 This means it appears in a @code{post_inc}, @code{pre_inc},
4154 @code{post_dec} or @code{pre_dec} expression.
4158 The register @var{op} is known to have a nonnegative value when this
4159 insn is reached. This is used by special looping instructions
4160 that terminate when the register goes negative.
4162 The @code{REG_NONNEG} note is added only to @samp{doloop_end}
4163 insns, if its pattern uses a @code{ge} condition.
4165 @findex REG_LABEL_OPERAND
4166 @item REG_LABEL_OPERAND
4167 This insn uses @var{op}, a @code{code_label} or a @code{note} of type
4168 @code{NOTE_INSN_DELETED_LABEL}, but is not a @code{jump_insn}, or it
4169 is a @code{jump_insn} that refers to the operand as an ordinary
4170 operand. The label may still eventually be a jump target, but if so
4171 in an indirect jump in a subsequent insn. The presence of this note
4172 allows jump optimization to be aware that @var{op} is, in fact, being
4173 used, and flow optimization to build an accurate flow graph.
4175 @findex REG_LABEL_TARGET
4176 @item REG_LABEL_TARGET
4177 This insn is a @code{jump_insn} but not an @code{addr_vec} or
4178 @code{addr_diff_vec}. It uses @var{op}, a @code{code_label} as a
4179 direct or indirect jump target. Its purpose is similar to that of
4180 @code{REG_LABEL_OPERAND}. This note is only present if the insn has
4181 multiple targets; the last label in the insn (in the highest numbered
4182 insn-field) goes into the @code{JUMP_LABEL} field and does not have a
4183 @code{REG_LABEL_TARGET} note. @xref{Insns, JUMP_LABEL}.
4187 Appears attached to each @code{CALL_INSN} to @code{setjmp} or a
4191 The following notes describe attributes of outputs of an insn:
4198 This note is only valid on an insn that sets only one register and
4199 indicates that that register will be equal to @var{op} at run time; the
4200 scope of this equivalence differs between the two types of notes. The
4201 value which the insn explicitly copies into the register may look
4202 different from @var{op}, but they will be equal at run time. If the
4203 output of the single @code{set} is a @code{strict_low_part} or
4204 @code{zero_extract} expression, the note refers to the register that
4205 is contained in its first operand.
4207 For @code{REG_EQUIV}, the register is equivalent to @var{op} throughout
4208 the entire function, and could validly be replaced in all its
4209 occurrences by @var{op}. (``Validly'' here refers to the data flow of
4210 the program; simple replacement may make some insns invalid.) For
4211 example, when a constant is loaded into a register that is never
4212 assigned any other value, this kind of note is used.
4214 When a parameter is copied into a pseudo-register at entry to a function,
4215 a note of this kind records that the register is equivalent to the stack
4216 slot where the parameter was passed. Although in this case the register
4217 may be set by other insns, it is still valid to replace the register
4218 by the stack slot throughout the function.
4220 A @code{REG_EQUIV} note is also used on an instruction which copies a
4221 register parameter into a pseudo-register at entry to a function, if
4222 there is a stack slot where that parameter could be stored. Although
4223 other insns may set the pseudo-register, it is valid for the compiler to
4224 replace the pseudo-register by stack slot throughout the function,
4225 provided the compiler ensures that the stack slot is properly
4226 initialized by making the replacement in the initial copy instruction as
4227 well. This is used on machines for which the calling convention
4228 allocates stack space for register parameters. See
4229 @code{REG_PARM_STACK_SPACE} in @ref{Stack Arguments}.
4231 In the case of @code{REG_EQUAL}, the register that is set by this insn
4232 will be equal to @var{op} at run time at the end of this insn but not
4233 necessarily elsewhere in the function. In this case, @var{op}
4234 is typically an arithmetic expression. For example, when a sequence of
4235 insns such as a library call is used to perform an arithmetic operation,
4236 this kind of note is attached to the insn that produces or copies the
4239 These two notes are used in different ways by the compiler passes.
4240 @code{REG_EQUAL} is used by passes prior to register allocation (such as
4241 common subexpression elimination and loop optimization) to tell them how
4242 to think of that value. @code{REG_EQUIV} notes are used by register
4243 allocation to indicate that there is an available substitute expression
4244 (either a constant or a @code{mem} expression for the location of a
4245 parameter on the stack) that may be used in place of a register if
4246 insufficient registers are available.
4248 Except for stack homes for parameters, which are indicated by a
4249 @code{REG_EQUIV} note and are not useful to the early optimization
4250 passes and pseudo registers that are equivalent to a memory location
4251 throughout their entire life, which is not detected until later in
4252 the compilation, all equivalences are initially indicated by an attached
4253 @code{REG_EQUAL} note. In the early stages of register allocation, a
4254 @code{REG_EQUAL} note is changed into a @code{REG_EQUIV} note if
4255 @var{op} is a constant and the insn represents the only set of its
4256 destination register.
4258 Thus, compiler passes prior to register allocation need only check for
4259 @code{REG_EQUAL} notes and passes subsequent to register allocation
4260 need only check for @code{REG_EQUIV} notes.
4263 These notes describe linkages between insns. They occur in pairs: one
4264 insn has one of a pair of notes that points to a second insn, which has
4265 the inverse note pointing back to the first insn.
4268 @findex REG_CC_SETTER
4272 On machines that use @code{cc0}, the insns which set and use @code{cc0}
4273 set and use @code{cc0} are adjacent. However, when branch delay slot
4274 filling is done, this may no longer be true. In this case a
4275 @code{REG_CC_USER} note will be placed on the insn setting @code{cc0} to
4276 point to the insn using @code{cc0} and a @code{REG_CC_SETTER} note will
4277 be placed on the insn using @code{cc0} to point to the insn setting
4281 These values are only used in the @code{LOG_LINKS} field, and indicate
4282 the type of dependency that each link represents. Links which indicate
4283 a data dependence (a read after write dependence) do not use any code,
4284 they simply have mode @code{VOIDmode}, and are printed without any
4288 @findex REG_DEP_TRUE
4290 This indicates a true dependence (a read after write dependence).
4292 @findex REG_DEP_OUTPUT
4293 @item REG_DEP_OUTPUT
4294 This indicates an output dependence (a write after write dependence).
4296 @findex REG_DEP_ANTI
4298 This indicates an anti dependence (a write after read dependence).
4302 These notes describe information gathered from gcov profile data. They
4303 are stored in the @code{REG_NOTES} field of an insn.
4308 This is used to specify the ratio of branches to non-branches of a
4309 branch insn according to the profile data. The note is represented
4310 as an @code{int_list} expression whose integer value is an encoding
4311 of @code{profile_probability} type. @code{profile_probability} provide
4312 member function @code{from_reg_br_prob_note} and @code{to_reg_br_prob_note}
4313 to extract and store the probability into the RTL encoding.
4317 These notes are found in JUMP insns after delayed branch scheduling
4318 has taken place. They indicate both the direction and the likelihood
4319 of the JUMP@. The format is a bitmask of ATTR_FLAG_* values.
4321 @findex REG_FRAME_RELATED_EXPR
4322 @item REG_FRAME_RELATED_EXPR
4323 This is used on an RTX_FRAME_RELATED_P insn wherein the attached expression
4324 is used in place of the actual insn pattern. This is done in cases where
4325 the pattern is either complex or misleading.
4328 The note @code{REG_CALL_NOCF_CHECK} is used in conjunction with the
4329 @option{-fcf-protection=branch} option. The note is set if a
4330 @code{nocf_check} attribute is specified for a function type or a
4331 pointer to function type. The note is stored in the @code{REG_NOTES}
4335 @findex REG_CALL_NOCF_CHECK
4336 @item REG_CALL_NOCF_CHECK
4337 Users have control through the @code{nocf_check} attribute to identify
4338 which calls to a function should be skipped from control-flow instrumentation
4339 when the option @option{-fcf-protection=branch} is specified. The compiler
4340 puts a @code{REG_CALL_NOCF_CHECK} note on each @code{CALL_INSN} instruction
4341 that has a function type marked with a @code{nocf_check} attribute.
4344 For convenience, the machine mode in an @code{insn_list} or
4345 @code{expr_list} is printed using these symbolic codes in debugging dumps.
4349 The only difference between the expression codes @code{insn_list} and
4350 @code{expr_list} is that the first operand of an @code{insn_list} is
4351 assumed to be an insn and is printed in debugging dumps as the insn's
4352 unique id; the first operand of an @code{expr_list} is printed in the
4353 ordinary way as an expression.
4356 @section RTL Representation of Function-Call Insns
4357 @cindex calling functions in RTL
4358 @cindex RTL function-call insns
4359 @cindex function-call insns
4361 Insns that call subroutines have the RTL expression code @code{call_insn}.
4362 These insns must satisfy special rules, and their bodies must use a special
4363 RTL expression code, @code{call}.
4365 @cindex @code{call} usage
4366 A @code{call} expression has two operands, as follows:
4369 (call (mem:@var{fm} @var{addr}) @var{nbytes})
4373 Here @var{nbytes} is an operand that represents the number of bytes of
4374 argument data being passed to the subroutine, @var{fm} is a machine mode
4375 (which must equal as the definition of the @code{FUNCTION_MODE} macro in
4376 the machine description) and @var{addr} represents the address of the
4379 For a subroutine that returns no value, the @code{call} expression as
4380 shown above is the entire body of the insn, except that the insn might
4381 also contain @code{use} or @code{clobber} expressions.
4383 @cindex @code{BLKmode}, and function return values
4384 For a subroutine that returns a value whose mode is not @code{BLKmode},
4385 the value is returned in a hard register. If this register's number is
4386 @var{r}, then the body of the call insn looks like this:
4389 (set (reg:@var{m} @var{r})
4390 (call (mem:@var{fm} @var{addr}) @var{nbytes}))
4394 This RTL expression makes it clear (to the optimizer passes) that the
4395 appropriate register receives a useful value in this insn.
4397 When a subroutine returns a @code{BLKmode} value, it is handled by
4398 passing to the subroutine the address of a place to store the value.
4399 So the call insn itself does not ``return'' any value, and it has the
4400 same RTL form as a call that returns nothing.
4402 On some machines, the call instruction itself clobbers some register,
4403 for example to contain the return address. @code{call_insn} insns
4404 on these machines should have a body which is a @code{parallel}
4405 that contains both the @code{call} expression and @code{clobber}
4406 expressions that indicate which registers are destroyed. Similarly,
4407 if the call instruction requires some register other than the stack
4408 pointer that is not explicitly mentioned in its RTL, a @code{use}
4409 subexpression should mention that register.
4411 Functions that are called are assumed to modify all registers listed in
4412 the configuration macro @code{CALL_USED_REGISTERS} (@pxref{Register
4413 Basics}) and, with the exception of @code{const} functions and library
4414 calls, to modify all of memory.
4416 Insns containing just @code{use} expressions directly precede the
4417 @code{call_insn} insn to indicate which registers contain inputs to the
4418 function. Similarly, if registers other than those in
4419 @code{CALL_USED_REGISTERS} are clobbered by the called function, insns
4420 containing a single @code{clobber} follow immediately after the call to
4421 indicate which registers.
4424 @section Structure Sharing Assumptions
4425 @cindex sharing of RTL components
4426 @cindex RTL structure sharing assumptions
4428 The compiler assumes that certain kinds of RTL expressions are unique;
4429 there do not exist two distinct objects representing the same value.
4430 In other cases, it makes an opposite assumption: that no RTL expression
4431 object of a certain kind appears in more than one place in the
4432 containing structure.
4434 These assumptions refer to a single function; except for the RTL
4435 objects that describe global variables and external functions,
4436 and a few standard objects such as small integer constants,
4437 no RTL objects are common to two functions.
4440 @cindex @code{reg}, RTL sharing
4442 Each pseudo-register has only a single @code{reg} object to represent it,
4443 and therefore only a single machine mode.
4445 @cindex symbolic label
4446 @cindex @code{symbol_ref}, RTL sharing
4448 For any symbolic label, there is only one @code{symbol_ref} object
4451 @cindex @code{const_int}, RTL sharing
4453 All @code{const_int} expressions with equal values are shared.
4455 @cindex @code{const_poly_int}, RTL sharing
4457 All @code{const_poly_int} expressions with equal modes and values
4460 @cindex @code{pc}, RTL sharing
4462 There is only one @code{pc} expression.
4464 @cindex @code{cc0}, RTL sharing
4466 There is only one @code{cc0} expression.
4468 @cindex @code{const_double}, RTL sharing
4470 There is only one @code{const_double} expression with value 0 for
4471 each floating point mode. Likewise for values 1 and 2.
4473 @cindex @code{const_vector}, RTL sharing
4475 There is only one @code{const_vector} expression with value 0 for
4476 each vector mode, be it an integer or a double constant vector.
4478 @cindex @code{label_ref}, RTL sharing
4479 @cindex @code{scratch}, RTL sharing
4481 No @code{label_ref} or @code{scratch} appears in more than one place in
4482 the RTL structure; in other words, it is safe to do a tree-walk of all
4483 the insns in the function and assume that each time a @code{label_ref}
4484 or @code{scratch} is seen it is distinct from all others that are seen.
4486 @cindex @code{mem}, RTL sharing
4488 Only one @code{mem} object is normally created for each static
4489 variable or stack slot, so these objects are frequently shared in all
4490 the places they appear. However, separate but equal objects for these
4491 variables are occasionally made.
4493 @cindex @code{asm_operands}, RTL sharing
4495 When a single @code{asm} statement has multiple output operands, a
4496 distinct @code{asm_operands} expression is made for each output operand.
4497 However, these all share the vector which contains the sequence of input
4498 operands. This sharing is used later on to test whether two
4499 @code{asm_operands} expressions come from the same statement, so all
4500 optimizations must carefully preserve the sharing if they copy the
4504 No RTL object appears in more than one place in the RTL structure
4505 except as described above. Many passes of the compiler rely on this
4506 by assuming that they can modify RTL objects in place without unwanted
4507 side-effects on other insns.
4509 @findex unshare_all_rtl
4511 During initial RTL generation, shared structure is freely introduced.
4512 After all the RTL for a function has been generated, all shared
4513 structure is copied by @code{unshare_all_rtl} in @file{emit-rtl.c},
4514 after which the above rules are guaranteed to be followed.
4516 @findex copy_rtx_if_shared
4518 During the combiner pass, shared structure within an insn can exist
4519 temporarily. However, the shared structure is copied before the
4520 combiner is finished with the insn. This is done by calling
4521 @code{copy_rtx_if_shared}, which is a subroutine of
4522 @code{unshare_all_rtl}.
4526 @section Reading RTL
4528 To read an RTL object from a file, call @code{read_rtx}. It takes one
4529 argument, a stdio stream, and returns a single RTL object. This routine
4530 is defined in @file{read-rtl.c}. It is not available in the compiler
4531 itself, only the various programs that generate the compiler back end
4532 from the machine description.
4534 People frequently have the idea of using RTL stored as text in a file as
4535 an interface between a language front end and the bulk of GCC@. This
4536 idea is not feasible.
4538 GCC was designed to use RTL internally only. Correct RTL for a given
4539 program is very dependent on the particular target machine. And the RTL
4540 does not contain all the information about the program.
4542 The proper way to interface GCC to a new language front end is with
4543 the ``tree'' data structure, described in the files @file{tree.h} and
4544 @file{tree.def}. The documentation for this structure (@pxref{GENERIC})