1 /* Emit RTL for the GCC expander.
2 Copyright (C) 1987-2020 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
21 /* Middle-to-low level generation of rtx code and insns.
23 This file contains support functions for creating rtl expressions
24 and manipulating them in the doubly-linked chain of insns.
26 The patterns of the insns are created by machine-dependent
27 routines in insn-emit.c, which is generated automatically from
28 the machine description. These routines make the individual rtx's
29 of the pattern with `gen_rtx_fmt_ee' and others in genrtl.[ch],
30 which are automatically generated from rtl.def; what is machine
31 dependent is the kind of rtx's they make and what arguments they
36 #include "coretypes.h"
44 #include "stringpool.h"
45 #include "insn-config.h"
49 #include "diagnostic-core.h"
51 #include "fold-const.h"
59 #include "stor-layout.h"
62 #include "rtx-vector-builder.h"
64 #include "gimple-ssa.h"
67 struct target_rtl default_target_rtl
;
69 struct target_rtl
*this_target_rtl
= &default_target_rtl
;
72 #define initial_regno_reg_rtx (this_target_rtl->x_initial_regno_reg_rtx)
74 /* Commonly used modes. */
76 scalar_int_mode byte_mode
; /* Mode whose width is BITS_PER_UNIT. */
77 scalar_int_mode word_mode
; /* Mode whose width is BITS_PER_WORD. */
78 scalar_int_mode ptr_mode
; /* Mode whose width is POINTER_SIZE. */
80 /* Datastructures maintained for currently processed function in RTL form. */
82 struct rtl_data x_rtl
;
84 /* Indexed by pseudo register number, gives the rtx for that pseudo.
85 Allocated in parallel with regno_pointer_align.
86 FIXME: We could put it into emit_status struct, but gengtype is not able to deal
87 with length attribute nested in top level structures. */
91 /* This is *not* reset after each function. It gives each CODE_LABEL
92 in the entire compilation a unique label number. */
94 static GTY(()) int label_num
= 1;
96 /* We record floating-point CONST_DOUBLEs in each floating-point mode for
97 the values of 0, 1, and 2. For the integer entries and VOIDmode, we
98 record a copy of const[012]_rtx and constm1_rtx. CONSTM1_RTX
99 is set only for MODE_INT and MODE_VECTOR_INT modes. */
101 rtx const_tiny_rtx
[4][(int) MAX_MACHINE_MODE
];
105 REAL_VALUE_TYPE dconst0
;
106 REAL_VALUE_TYPE dconst1
;
107 REAL_VALUE_TYPE dconst2
;
108 REAL_VALUE_TYPE dconstm1
;
109 REAL_VALUE_TYPE dconsthalf
;
111 /* Record fixed-point constant 0 and 1. */
112 FIXED_VALUE_TYPE fconst0
[MAX_FCONST0
];
113 FIXED_VALUE_TYPE fconst1
[MAX_FCONST1
];
115 /* We make one copy of (const_int C) where C is in
116 [- MAX_SAVED_CONST_INT, MAX_SAVED_CONST_INT]
117 to save space during the compilation and simplify comparisons of
120 rtx const_int_rtx
[MAX_SAVED_CONST_INT
* 2 + 1];
122 /* Standard pieces of rtx, to be substituted directly into things. */
125 rtx simple_return_rtx
;
128 /* Marker used for denoting an INSN, which should never be accessed (i.e.,
129 this pointer should normally never be dereferenced), but is required to be
130 distinct from NULL_RTX. Currently used by peephole2 pass. */
131 rtx_insn
*invalid_insn_rtx
;
133 /* A hash table storing CONST_INTs whose absolute value is greater
134 than MAX_SAVED_CONST_INT. */
136 struct const_int_hasher
: ggc_cache_ptr_hash
<rtx_def
>
138 typedef HOST_WIDE_INT compare_type
;
140 static hashval_t
hash (rtx i
);
141 static bool equal (rtx i
, HOST_WIDE_INT h
);
144 static GTY ((cache
)) hash_table
<const_int_hasher
> *const_int_htab
;
146 struct const_wide_int_hasher
: ggc_cache_ptr_hash
<rtx_def
>
148 static hashval_t
hash (rtx x
);
149 static bool equal (rtx x
, rtx y
);
152 static GTY ((cache
)) hash_table
<const_wide_int_hasher
> *const_wide_int_htab
;
154 struct const_poly_int_hasher
: ggc_cache_ptr_hash
<rtx_def
>
156 typedef std::pair
<machine_mode
, poly_wide_int_ref
> compare_type
;
158 static hashval_t
hash (rtx x
);
159 static bool equal (rtx x
, const compare_type
&y
);
162 static GTY ((cache
)) hash_table
<const_poly_int_hasher
> *const_poly_int_htab
;
164 /* A hash table storing register attribute structures. */
165 struct reg_attr_hasher
: ggc_cache_ptr_hash
<reg_attrs
>
167 static hashval_t
hash (reg_attrs
*x
);
168 static bool equal (reg_attrs
*a
, reg_attrs
*b
);
171 static GTY ((cache
)) hash_table
<reg_attr_hasher
> *reg_attrs_htab
;
173 /* A hash table storing all CONST_DOUBLEs. */
174 struct const_double_hasher
: ggc_cache_ptr_hash
<rtx_def
>
176 static hashval_t
hash (rtx x
);
177 static bool equal (rtx x
, rtx y
);
180 static GTY ((cache
)) hash_table
<const_double_hasher
> *const_double_htab
;
182 /* A hash table storing all CONST_FIXEDs. */
183 struct const_fixed_hasher
: ggc_cache_ptr_hash
<rtx_def
>
185 static hashval_t
hash (rtx x
);
186 static bool equal (rtx x
, rtx y
);
189 static GTY ((cache
)) hash_table
<const_fixed_hasher
> *const_fixed_htab
;
191 #define cur_insn_uid (crtl->emit.x_cur_insn_uid)
192 #define cur_debug_insn_uid (crtl->emit.x_cur_debug_insn_uid)
193 #define first_label_num (crtl->emit.x_first_label_num)
195 static void set_used_decls (tree
);
196 static void mark_label_nuses (rtx
);
197 #if TARGET_SUPPORTS_WIDE_INT
198 static rtx
lookup_const_wide_int (rtx
);
200 static rtx
lookup_const_double (rtx
);
201 static rtx
lookup_const_fixed (rtx
);
202 static rtx
gen_const_vector (machine_mode
, int);
203 static void copy_rtx_if_shared_1 (rtx
*orig
);
205 /* Probability of the conditional branch currently proceeded by try_split. */
206 profile_probability split_branch_probability
;
208 /* Returns a hash code for X (which is a really a CONST_INT). */
211 const_int_hasher::hash (rtx x
)
213 return (hashval_t
) INTVAL (x
);
216 /* Returns nonzero if the value represented by X (which is really a
217 CONST_INT) is the same as that given by Y (which is really a
221 const_int_hasher::equal (rtx x
, HOST_WIDE_INT y
)
223 return (INTVAL (x
) == y
);
226 #if TARGET_SUPPORTS_WIDE_INT
227 /* Returns a hash code for X (which is a really a CONST_WIDE_INT). */
230 const_wide_int_hasher::hash (rtx x
)
233 unsigned HOST_WIDE_INT hash
= 0;
236 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (xr
); i
++)
237 hash
+= CONST_WIDE_INT_ELT (xr
, i
);
239 return (hashval_t
) hash
;
242 /* Returns nonzero if the value represented by X (which is really a
243 CONST_WIDE_INT) is the same as that given by Y (which is really a
247 const_wide_int_hasher::equal (rtx x
, rtx y
)
252 if (CONST_WIDE_INT_NUNITS (xr
) != CONST_WIDE_INT_NUNITS (yr
))
255 for (i
= 0; i
< CONST_WIDE_INT_NUNITS (xr
); i
++)
256 if (CONST_WIDE_INT_ELT (xr
, i
) != CONST_WIDE_INT_ELT (yr
, i
))
263 /* Returns a hash code for CONST_POLY_INT X. */
266 const_poly_int_hasher::hash (rtx x
)
269 h
.add_int (GET_MODE (x
));
270 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
271 h
.add_wide_int (CONST_POLY_INT_COEFFS (x
)[i
]);
275 /* Returns nonzero if CONST_POLY_INT X is an rtx representation of Y. */
278 const_poly_int_hasher::equal (rtx x
, const compare_type
&y
)
280 if (GET_MODE (x
) != y
.first
)
282 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
283 if (CONST_POLY_INT_COEFFS (x
)[i
] != y
.second
.coeffs
[i
])
288 /* Returns a hash code for X (which is really a CONST_DOUBLE). */
290 const_double_hasher::hash (rtx x
)
292 const_rtx
const value
= x
;
295 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (value
) == VOIDmode
)
296 h
= CONST_DOUBLE_LOW (value
) ^ CONST_DOUBLE_HIGH (value
);
299 h
= real_hash (CONST_DOUBLE_REAL_VALUE (value
));
300 /* MODE is used in the comparison, so it should be in the hash. */
301 h
^= GET_MODE (value
);
306 /* Returns nonzero if the value represented by X (really a ...)
307 is the same as that represented by Y (really a ...) */
309 const_double_hasher::equal (rtx x
, rtx y
)
311 const_rtx
const a
= x
, b
= y
;
313 if (GET_MODE (a
) != GET_MODE (b
))
315 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (a
) == VOIDmode
)
316 return (CONST_DOUBLE_LOW (a
) == CONST_DOUBLE_LOW (b
)
317 && CONST_DOUBLE_HIGH (a
) == CONST_DOUBLE_HIGH (b
));
319 return real_identical (CONST_DOUBLE_REAL_VALUE (a
),
320 CONST_DOUBLE_REAL_VALUE (b
));
323 /* Returns a hash code for X (which is really a CONST_FIXED). */
326 const_fixed_hasher::hash (rtx x
)
328 const_rtx
const value
= x
;
331 h
= fixed_hash (CONST_FIXED_VALUE (value
));
332 /* MODE is used in the comparison, so it should be in the hash. */
333 h
^= GET_MODE (value
);
337 /* Returns nonzero if the value represented by X is the same as that
341 const_fixed_hasher::equal (rtx x
, rtx y
)
343 const_rtx
const a
= x
, b
= y
;
345 if (GET_MODE (a
) != GET_MODE (b
))
347 return fixed_identical (CONST_FIXED_VALUE (a
), CONST_FIXED_VALUE (b
));
350 /* Return true if the given memory attributes are equal. */
353 mem_attrs_eq_p (const class mem_attrs
*p
, const class mem_attrs
*q
)
359 return (p
->alias
== q
->alias
360 && p
->offset_known_p
== q
->offset_known_p
361 && (!p
->offset_known_p
|| known_eq (p
->offset
, q
->offset
))
362 && p
->size_known_p
== q
->size_known_p
363 && (!p
->size_known_p
|| known_eq (p
->size
, q
->size
))
364 && p
->align
== q
->align
365 && p
->addrspace
== q
->addrspace
366 && (p
->expr
== q
->expr
367 || (p
->expr
!= NULL_TREE
&& q
->expr
!= NULL_TREE
368 && operand_equal_p (p
->expr
, q
->expr
, 0))));
371 /* Set MEM's memory attributes so that they are the same as ATTRS. */
374 set_mem_attrs (rtx mem
, mem_attrs
*attrs
)
376 /* If everything is the default, we can just clear the attributes. */
377 if (mem_attrs_eq_p (attrs
, mode_mem_attrs
[(int) GET_MODE (mem
)]))
384 || !mem_attrs_eq_p (attrs
, MEM_ATTRS (mem
)))
386 MEM_ATTRS (mem
) = ggc_alloc
<mem_attrs
> ();
387 memcpy (MEM_ATTRS (mem
), attrs
, sizeof (mem_attrs
));
391 /* Returns a hash code for X (which is a really a reg_attrs *). */
394 reg_attr_hasher::hash (reg_attrs
*x
)
396 const reg_attrs
*const p
= x
;
400 h
.add_poly_hwi (p
->offset
);
404 /* Returns nonzero if the value represented by X is the same as that given by
408 reg_attr_hasher::equal (reg_attrs
*x
, reg_attrs
*y
)
410 const reg_attrs
*const p
= x
;
411 const reg_attrs
*const q
= y
;
413 return (p
->decl
== q
->decl
&& known_eq (p
->offset
, q
->offset
));
415 /* Allocate a new reg_attrs structure and insert it into the hash table if
416 one identical to it is not already in the table. We are doing this for
420 get_reg_attrs (tree decl
, poly_int64 offset
)
424 /* If everything is the default, we can just return zero. */
425 if (decl
== 0 && known_eq (offset
, 0))
429 attrs
.offset
= offset
;
431 reg_attrs
**slot
= reg_attrs_htab
->find_slot (&attrs
, INSERT
);
434 *slot
= ggc_alloc
<reg_attrs
> ();
435 memcpy (*slot
, &attrs
, sizeof (reg_attrs
));
443 /* Generate an empty ASM_INPUT, which is used to block attempts to schedule,
444 and to block register equivalences to be seen across this insn. */
449 rtx x
= gen_rtx_ASM_INPUT (VOIDmode
, "");
450 MEM_VOLATILE_P (x
) = true;
456 /* Set the mode and register number of X to MODE and REGNO. */
459 set_mode_and_regno (rtx x
, machine_mode mode
, unsigned int regno
)
461 unsigned int nregs
= (HARD_REGISTER_NUM_P (regno
)
462 ? hard_regno_nregs (regno
, mode
)
464 PUT_MODE_RAW (x
, mode
);
465 set_regno_raw (x
, regno
, nregs
);
468 /* Initialize a fresh REG rtx with mode MODE and register REGNO. */
471 init_raw_REG (rtx x
, machine_mode mode
, unsigned int regno
)
473 set_mode_and_regno (x
, mode
, regno
);
474 REG_ATTRS (x
) = NULL
;
475 ORIGINAL_REGNO (x
) = regno
;
479 /* Generate a new REG rtx. Make sure ORIGINAL_REGNO is set properly, and
480 don't attempt to share with the various global pieces of rtl (such as
481 frame_pointer_rtx). */
484 gen_raw_REG (machine_mode mode
, unsigned int regno
)
486 rtx x
= rtx_alloc (REG MEM_STAT_INFO
);
487 init_raw_REG (x
, mode
, regno
);
491 /* There are some RTL codes that require special attention; the generation
492 functions do the raw handling. If you add to this list, modify
493 special_rtx in gengenrtl.c as well. */
496 gen_rtx_EXPR_LIST (machine_mode mode
, rtx expr
, rtx expr_list
)
498 return as_a
<rtx_expr_list
*> (gen_rtx_fmt_ee (EXPR_LIST
, mode
, expr
,
503 gen_rtx_INSN_LIST (machine_mode mode
, rtx insn
, rtx insn_list
)
505 return as_a
<rtx_insn_list
*> (gen_rtx_fmt_ue (INSN_LIST
, mode
, insn
,
510 gen_rtx_INSN (machine_mode mode
, rtx_insn
*prev_insn
, rtx_insn
*next_insn
,
511 basic_block bb
, rtx pattern
, int location
, int code
,
514 return as_a
<rtx_insn
*> (gen_rtx_fmt_uuBeiie (INSN
, mode
,
515 prev_insn
, next_insn
,
516 bb
, pattern
, location
, code
,
521 gen_rtx_CONST_INT (machine_mode mode ATTRIBUTE_UNUSED
, HOST_WIDE_INT arg
)
523 if (arg
>= - MAX_SAVED_CONST_INT
&& arg
<= MAX_SAVED_CONST_INT
)
524 return const_int_rtx
[arg
+ MAX_SAVED_CONST_INT
];
526 #if STORE_FLAG_VALUE != 1 && STORE_FLAG_VALUE != -1
527 if (const_true_rtx
&& arg
== STORE_FLAG_VALUE
)
528 return const_true_rtx
;
531 /* Look up the CONST_INT in the hash table. */
532 rtx
*slot
= const_int_htab
->find_slot_with_hash (arg
, (hashval_t
) arg
,
535 *slot
= gen_rtx_raw_CONST_INT (VOIDmode
, arg
);
541 gen_int_mode (poly_int64 c
, machine_mode mode
)
543 c
= trunc_int_for_mode (c
, mode
);
544 if (c
.is_constant ())
545 return GEN_INT (c
.coeffs
[0]);
546 unsigned int prec
= GET_MODE_PRECISION (as_a
<scalar_mode
> (mode
));
547 return immed_wide_int_const (poly_wide_int::from (c
, prec
, SIGNED
), mode
);
550 /* CONST_DOUBLEs might be created from pairs of integers, or from
551 REAL_VALUE_TYPEs. Also, their length is known only at run time,
552 so we cannot use gen_rtx_raw_CONST_DOUBLE. */
554 /* Determine whether REAL, a CONST_DOUBLE, already exists in the
555 hash table. If so, return its counterpart; otherwise add it
556 to the hash table and return it. */
558 lookup_const_double (rtx real
)
560 rtx
*slot
= const_double_htab
->find_slot (real
, INSERT
);
567 /* Return a CONST_DOUBLE rtx for a floating-point value specified by
568 VALUE in mode MODE. */
570 const_double_from_real_value (REAL_VALUE_TYPE value
, machine_mode mode
)
572 rtx real
= rtx_alloc (CONST_DOUBLE
);
573 PUT_MODE (real
, mode
);
577 return lookup_const_double (real
);
580 /* Determine whether FIXED, a CONST_FIXED, already exists in the
581 hash table. If so, return its counterpart; otherwise add it
582 to the hash table and return it. */
585 lookup_const_fixed (rtx fixed
)
587 rtx
*slot
= const_fixed_htab
->find_slot (fixed
, INSERT
);
594 /* Return a CONST_FIXED rtx for a fixed-point value specified by
595 VALUE in mode MODE. */
598 const_fixed_from_fixed_value (FIXED_VALUE_TYPE value
, machine_mode mode
)
600 rtx fixed
= rtx_alloc (CONST_FIXED
);
601 PUT_MODE (fixed
, mode
);
605 return lookup_const_fixed (fixed
);
608 #if TARGET_SUPPORTS_WIDE_INT == 0
609 /* Constructs double_int from rtx CST. */
612 rtx_to_double_int (const_rtx cst
)
616 if (CONST_INT_P (cst
))
617 r
= double_int::from_shwi (INTVAL (cst
));
618 else if (CONST_DOUBLE_AS_INT_P (cst
))
620 r
.low
= CONST_DOUBLE_LOW (cst
);
621 r
.high
= CONST_DOUBLE_HIGH (cst
);
630 #if TARGET_SUPPORTS_WIDE_INT
631 /* Determine whether CONST_WIDE_INT WINT already exists in the hash table.
632 If so, return its counterpart; otherwise add it to the hash table and
636 lookup_const_wide_int (rtx wint
)
638 rtx
*slot
= const_wide_int_htab
->find_slot (wint
, INSERT
);
646 /* Return an rtx constant for V, given that the constant has mode MODE.
647 The returned rtx will be a CONST_INT if V fits, otherwise it will be
648 a CONST_DOUBLE (if !TARGET_SUPPORTS_WIDE_INT) or a CONST_WIDE_INT
649 (if TARGET_SUPPORTS_WIDE_INT). */
652 immed_wide_int_const_1 (const wide_int_ref
&v
, machine_mode mode
)
654 unsigned int len
= v
.get_len ();
655 /* Not scalar_int_mode because we also allow pointer bound modes. */
656 unsigned int prec
= GET_MODE_PRECISION (as_a
<scalar_mode
> (mode
));
658 /* Allow truncation but not extension since we do not know if the
659 number is signed or unsigned. */
660 gcc_assert (prec
<= v
.get_precision ());
662 if (len
< 2 || prec
<= HOST_BITS_PER_WIDE_INT
)
663 return gen_int_mode (v
.elt (0), mode
);
665 #if TARGET_SUPPORTS_WIDE_INT
669 unsigned int blocks_needed
670 = (prec
+ HOST_BITS_PER_WIDE_INT
- 1) / HOST_BITS_PER_WIDE_INT
;
672 if (len
> blocks_needed
)
675 value
= const_wide_int_alloc (len
);
677 /* It is so tempting to just put the mode in here. Must control
679 PUT_MODE (value
, VOIDmode
);
680 CWI_PUT_NUM_ELEM (value
, len
);
682 for (i
= 0; i
< len
; i
++)
683 CONST_WIDE_INT_ELT (value
, i
) = v
.elt (i
);
685 return lookup_const_wide_int (value
);
688 return immed_double_const (v
.elt (0), v
.elt (1), mode
);
692 #if TARGET_SUPPORTS_WIDE_INT == 0
693 /* Return a CONST_DOUBLE or CONST_INT for a value specified as a pair
694 of ints: I0 is the low-order word and I1 is the high-order word.
695 For values that are larger than HOST_BITS_PER_DOUBLE_INT, the
696 implied upper bits are copies of the high bit of i1. The value
697 itself is neither signed nor unsigned. Do not use this routine for
698 non-integer modes; convert to REAL_VALUE_TYPE and use
699 const_double_from_real_value. */
702 immed_double_const (HOST_WIDE_INT i0
, HOST_WIDE_INT i1
, machine_mode mode
)
707 /* There are the following cases (note that there are no modes with
708 HOST_BITS_PER_WIDE_INT < GET_MODE_BITSIZE (mode) < HOST_BITS_PER_DOUBLE_INT):
710 1) If GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT, then we use
712 2) If the value of the integer fits into HOST_WIDE_INT anyway
713 (i.e., i1 consists only from copies of the sign bit, and sign
714 of i0 and i1 are the same), then we return a CONST_INT for i0.
715 3) Otherwise, we create a CONST_DOUBLE for i0 and i1. */
717 if (is_a
<scalar_mode
> (mode
, &smode
)
718 && GET_MODE_BITSIZE (smode
) <= HOST_BITS_PER_WIDE_INT
)
719 return gen_int_mode (i0
, mode
);
721 /* If this integer fits in one word, return a CONST_INT. */
722 if ((i1
== 0 && i0
>= 0) || (i1
== ~0 && i0
< 0))
725 /* We use VOIDmode for integers. */
726 value
= rtx_alloc (CONST_DOUBLE
);
727 PUT_MODE (value
, VOIDmode
);
729 CONST_DOUBLE_LOW (value
) = i0
;
730 CONST_DOUBLE_HIGH (value
) = i1
;
732 for (i
= 2; i
< (sizeof CONST_DOUBLE_FORMAT
- 1); i
++)
733 XWINT (value
, i
) = 0;
735 return lookup_const_double (value
);
739 /* Return an rtx representation of C in mode MODE. */
742 immed_wide_int_const (const poly_wide_int_ref
&c
, machine_mode mode
)
744 if (c
.is_constant ())
745 return immed_wide_int_const_1 (c
.coeffs
[0], mode
);
747 /* Not scalar_int_mode because we also allow pointer bound modes. */
748 unsigned int prec
= GET_MODE_PRECISION (as_a
<scalar_mode
> (mode
));
750 /* Allow truncation but not extension since we do not know if the
751 number is signed or unsigned. */
752 gcc_assert (prec
<= c
.coeffs
[0].get_precision ());
753 poly_wide_int newc
= poly_wide_int::from (c
, prec
, SIGNED
);
755 /* See whether we already have an rtx for this constant. */
758 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
759 h
.add_wide_int (newc
.coeffs
[i
]);
760 const_poly_int_hasher::compare_type
typed_value (mode
, newc
);
761 rtx
*slot
= const_poly_int_htab
->find_slot_with_hash (typed_value
,
767 /* Create a new rtx. There's a choice to be made here between installing
768 the actual mode of the rtx or leaving it as VOIDmode (for consistency
769 with CONST_INT). In practice the handling of the codes is different
770 enough that we get no benefit from using VOIDmode, and various places
771 assume that VOIDmode implies CONST_INT. Using the real mode seems like
772 the right long-term direction anyway. */
773 typedef trailing_wide_ints
<NUM_POLY_INT_COEFFS
> twi
;
774 size_t extra_size
= twi::extra_size (prec
);
775 x
= rtx_alloc_v (CONST_POLY_INT
,
776 sizeof (struct const_poly_int_def
) + extra_size
);
778 CONST_POLY_INT_COEFFS (x
).set_precision (prec
);
779 for (unsigned int i
= 0; i
< NUM_POLY_INT_COEFFS
; ++i
)
780 CONST_POLY_INT_COEFFS (x
)[i
] = newc
.coeffs
[i
];
787 gen_rtx_REG (machine_mode mode
, unsigned int regno
)
789 /* In case the MD file explicitly references the frame pointer, have
790 all such references point to the same frame pointer. This is
791 used during frame pointer elimination to distinguish the explicit
792 references to these registers from pseudos that happened to be
795 If we have eliminated the frame pointer or arg pointer, we will
796 be using it as a normal register, for example as a spill
797 register. In such cases, we might be accessing it in a mode that
798 is not Pmode and therefore cannot use the pre-allocated rtx.
800 Also don't do this when we are making new REGs in reload, since
801 we don't want to get confused with the real pointers. */
803 if (mode
== Pmode
&& !reload_in_progress
&& !lra_in_progress
)
805 if (regno
== FRAME_POINTER_REGNUM
806 && (!reload_completed
|| frame_pointer_needed
))
807 return frame_pointer_rtx
;
809 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
810 && regno
== HARD_FRAME_POINTER_REGNUM
811 && (!reload_completed
|| frame_pointer_needed
))
812 return hard_frame_pointer_rtx
;
813 #if !HARD_FRAME_POINTER_IS_ARG_POINTER
814 if (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
815 && regno
== ARG_POINTER_REGNUM
)
816 return arg_pointer_rtx
;
818 #ifdef RETURN_ADDRESS_POINTER_REGNUM
819 if (regno
== RETURN_ADDRESS_POINTER_REGNUM
)
820 return return_address_pointer_rtx
;
822 if (regno
== (unsigned) PIC_OFFSET_TABLE_REGNUM
823 && PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
824 && fixed_regs
[PIC_OFFSET_TABLE_REGNUM
])
825 return pic_offset_table_rtx
;
826 if (regno
== STACK_POINTER_REGNUM
)
827 return stack_pointer_rtx
;
831 /* If the per-function register table has been set up, try to re-use
832 an existing entry in that table to avoid useless generation of RTL.
834 This code is disabled for now until we can fix the various backends
835 which depend on having non-shared hard registers in some cases. Long
836 term we want to re-enable this code as it can significantly cut down
837 on the amount of useless RTL that gets generated.
839 We'll also need to fix some code that runs after reload that wants to
840 set ORIGINAL_REGNO. */
845 && regno
< FIRST_PSEUDO_REGISTER
846 && reg_raw_mode
[regno
] == mode
)
847 return regno_reg_rtx
[regno
];
850 return gen_raw_REG (mode
, regno
);
854 gen_rtx_MEM (machine_mode mode
, rtx addr
)
856 rtx rt
= gen_rtx_raw_MEM (mode
, addr
);
858 /* This field is not cleared by the mere allocation of the rtx, so
865 /* Generate a memory referring to non-trapping constant memory. */
868 gen_const_mem (machine_mode mode
, rtx addr
)
870 rtx mem
= gen_rtx_MEM (mode
, addr
);
871 MEM_READONLY_P (mem
) = 1;
872 MEM_NOTRAP_P (mem
) = 1;
876 /* Generate a MEM referring to fixed portions of the frame, e.g., register
880 gen_frame_mem (machine_mode mode
, rtx addr
)
882 rtx mem
= gen_rtx_MEM (mode
, addr
);
883 MEM_NOTRAP_P (mem
) = 1;
884 set_mem_alias_set (mem
, get_frame_alias_set ());
888 /* Generate a MEM referring to a temporary use of the stack, not part
889 of the fixed stack frame. For example, something which is pushed
890 by a target splitter. */
892 gen_tmp_stack_mem (machine_mode mode
, rtx addr
)
894 rtx mem
= gen_rtx_MEM (mode
, addr
);
895 MEM_NOTRAP_P (mem
) = 1;
896 if (!cfun
->calls_alloca
)
897 set_mem_alias_set (mem
, get_frame_alias_set ());
901 /* We want to create (subreg:OMODE (obj:IMODE) OFFSET). Return true if
902 this construct would be valid, and false otherwise. */
905 validate_subreg (machine_mode omode
, machine_mode imode
,
906 const_rtx reg
, poly_uint64 offset
)
908 poly_uint64 isize
= GET_MODE_SIZE (imode
);
909 poly_uint64 osize
= GET_MODE_SIZE (omode
);
911 /* The sizes must be ordered, so that we know whether the subreg
912 is partial, paradoxical or complete. */
913 if (!ordered_p (isize
, osize
))
916 /* All subregs must be aligned. */
917 if (!multiple_p (offset
, osize
))
920 /* The subreg offset cannot be outside the inner object. */
921 if (maybe_ge (offset
, isize
))
924 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (imode
);
926 /* ??? This should not be here. Temporarily continue to allow word_mode
927 subregs of anything. The most common offender is (subreg:SI (reg:DF)).
928 Generally, backends are doing something sketchy but it'll take time to
930 if (omode
== word_mode
)
932 /* ??? Similarly, e.g. with (subreg:DF (reg:TI)). Though store_bit_field
933 is the culprit here, and not the backends. */
934 else if (known_ge (osize
, regsize
) && known_ge (isize
, osize
))
936 /* Allow component subregs of complex and vector. Though given the below
937 extraction rules, it's not always clear what that means. */
938 else if ((COMPLEX_MODE_P (imode
) || VECTOR_MODE_P (imode
))
939 && GET_MODE_INNER (imode
) == omode
)
941 /* ??? x86 sse code makes heavy use of *paradoxical* vector subregs,
942 i.e. (subreg:V4SF (reg:SF) 0). This surely isn't the cleanest way to
943 represent this. It's questionable if this ought to be represented at
944 all -- why can't this all be hidden in post-reload splitters that make
945 arbitrarily mode changes to the registers themselves. */
946 else if (VECTOR_MODE_P (omode
) && GET_MODE_INNER (omode
) == imode
)
948 /* Subregs involving floating point modes are not allowed to
949 change size. Therefore (subreg:DI (reg:DF) 0) is fine, but
950 (subreg:SI (reg:DF) 0) isn't. */
951 else if (FLOAT_MODE_P (imode
) || FLOAT_MODE_P (omode
))
953 if (! (known_eq (isize
, osize
)
954 /* LRA can use subreg to store a floating point value in
955 an integer mode. Although the floating point and the
956 integer modes need the same number of hard registers,
957 the size of floating point mode can be less than the
958 integer mode. LRA also uses subregs for a register
959 should be used in different mode in on insn. */
964 /* Paradoxical subregs must have offset zero. */
965 if (maybe_gt (osize
, isize
))
966 return known_eq (offset
, 0U);
968 /* This is a normal subreg. Verify that the offset is representable. */
970 /* For hard registers, we already have most of these rules collected in
971 subreg_offset_representable_p. */
972 if (reg
&& REG_P (reg
) && HARD_REGISTER_P (reg
))
974 unsigned int regno
= REGNO (reg
);
976 if ((COMPLEX_MODE_P (imode
) || VECTOR_MODE_P (imode
))
977 && GET_MODE_INNER (imode
) == omode
)
979 else if (!REG_CAN_CHANGE_MODE_P (regno
, imode
, omode
))
982 return subreg_offset_representable_p (regno
, imode
, offset
, omode
);
985 /* The outer size must be ordered wrt the register size, otherwise
986 we wouldn't know at compile time how many registers the outer
988 if (!ordered_p (osize
, regsize
))
991 /* For pseudo registers, we want most of the same checks. Namely:
993 Assume that the pseudo register will be allocated to hard registers
994 that can hold REGSIZE bytes each. If OSIZE is not a multiple of REGSIZE,
995 the remainder must correspond to the lowpart of the containing hard
996 register. If BYTES_BIG_ENDIAN, the lowpart is at the highest offset,
997 otherwise it is at the lowest offset.
999 Given that we've already checked the mode and offset alignment,
1000 we only have to check subblock subregs here. */
1001 if (maybe_lt (osize
, regsize
)
1002 && ! (lra_in_progress
&& (FLOAT_MODE_P (imode
) || FLOAT_MODE_P (omode
))))
1004 /* It is invalid for the target to pick a register size for a mode
1005 that isn't ordered wrt to the size of that mode. */
1006 poly_uint64 block_size
= ordered_min (isize
, regsize
);
1007 unsigned int start_reg
;
1008 poly_uint64 offset_within_reg
;
1009 if (!can_div_trunc_p (offset
, block_size
, &start_reg
, &offset_within_reg
)
1010 || (BYTES_BIG_ENDIAN
1011 ? maybe_ne (offset_within_reg
, block_size
- osize
)
1012 : maybe_ne (offset_within_reg
, 0U)))
1019 gen_rtx_SUBREG (machine_mode mode
, rtx reg
, poly_uint64 offset
)
1021 gcc_assert (validate_subreg (mode
, GET_MODE (reg
), reg
, offset
));
1022 return gen_rtx_raw_SUBREG (mode
, reg
, offset
);
1025 /* Generate a SUBREG representing the least-significant part of REG if MODE
1026 is smaller than mode of REG, otherwise paradoxical SUBREG. */
1029 gen_lowpart_SUBREG (machine_mode mode
, rtx reg
)
1031 machine_mode inmode
;
1033 inmode
= GET_MODE (reg
);
1034 if (inmode
== VOIDmode
)
1036 return gen_rtx_SUBREG (mode
, reg
,
1037 subreg_lowpart_offset (mode
, inmode
));
1041 gen_rtx_VAR_LOCATION (machine_mode mode
, tree decl
, rtx loc
,
1042 enum var_init_status status
)
1044 rtx x
= gen_rtx_fmt_te (VAR_LOCATION
, mode
, decl
, loc
);
1045 PAT_VAR_LOCATION_STATUS (x
) = status
;
1050 /* Create an rtvec and stores within it the RTXen passed in the arguments. */
1053 gen_rtvec (int n
, ...)
1061 /* Don't allocate an empty rtvec... */
1068 rt_val
= rtvec_alloc (n
);
1070 for (i
= 0; i
< n
; i
++)
1071 rt_val
->elem
[i
] = va_arg (p
, rtx
);
1078 gen_rtvec_v (int n
, rtx
*argp
)
1083 /* Don't allocate an empty rtvec... */
1087 rt_val
= rtvec_alloc (n
);
1089 for (i
= 0; i
< n
; i
++)
1090 rt_val
->elem
[i
] = *argp
++;
1096 gen_rtvec_v (int n
, rtx_insn
**argp
)
1101 /* Don't allocate an empty rtvec... */
1105 rt_val
= rtvec_alloc (n
);
1107 for (i
= 0; i
< n
; i
++)
1108 rt_val
->elem
[i
] = *argp
++;
1114 /* Return the number of bytes between the start of an OUTER_MODE
1115 in-memory value and the start of an INNER_MODE in-memory value,
1116 given that the former is a lowpart of the latter. It may be a
1117 paradoxical lowpart, in which case the offset will be negative
1118 on big-endian targets. */
1121 byte_lowpart_offset (machine_mode outer_mode
,
1122 machine_mode inner_mode
)
1124 if (paradoxical_subreg_p (outer_mode
, inner_mode
))
1125 return -subreg_lowpart_offset (inner_mode
, outer_mode
);
1127 return subreg_lowpart_offset (outer_mode
, inner_mode
);
1130 /* Return the offset of (subreg:OUTER_MODE (mem:INNER_MODE X) OFFSET)
1131 from address X. For paradoxical big-endian subregs this is a
1132 negative value, otherwise it's the same as OFFSET. */
1135 subreg_memory_offset (machine_mode outer_mode
, machine_mode inner_mode
,
1138 if (paradoxical_subreg_p (outer_mode
, inner_mode
))
1140 gcc_assert (known_eq (offset
, 0U));
1141 return -subreg_lowpart_offset (inner_mode
, outer_mode
);
1146 /* As above, but return the offset that existing subreg X would have
1147 if SUBREG_REG (X) were stored in memory. The only significant thing
1148 about the current SUBREG_REG is its mode. */
1151 subreg_memory_offset (const_rtx x
)
1153 return subreg_memory_offset (GET_MODE (x
), GET_MODE (SUBREG_REG (x
)),
1157 /* Generate a REG rtx for a new pseudo register of mode MODE.
1158 This pseudo is assigned the next sequential register number. */
1161 gen_reg_rtx (machine_mode mode
)
1164 unsigned int align
= GET_MODE_ALIGNMENT (mode
);
1166 gcc_assert (can_create_pseudo_p ());
1168 /* If a virtual register with bigger mode alignment is generated,
1169 increase stack alignment estimation because it might be spilled
1171 if (SUPPORTS_STACK_ALIGNMENT
1172 && crtl
->stack_alignment_estimated
< align
1173 && !crtl
->stack_realign_processed
)
1175 unsigned int min_align
= MINIMUM_ALIGNMENT (NULL
, mode
, align
);
1176 if (crtl
->stack_alignment_estimated
< min_align
)
1177 crtl
->stack_alignment_estimated
= min_align
;
1180 if (generating_concat_p
1181 && (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
1182 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
))
1184 /* For complex modes, don't make a single pseudo.
1185 Instead, make a CONCAT of two pseudos.
1186 This allows noncontiguous allocation of the real and imaginary parts,
1187 which makes much better code. Besides, allocating DCmode
1188 pseudos overstrains reload on some machines like the 386. */
1189 rtx realpart
, imagpart
;
1190 machine_mode partmode
= GET_MODE_INNER (mode
);
1192 realpart
= gen_reg_rtx (partmode
);
1193 imagpart
= gen_reg_rtx (partmode
);
1194 return gen_rtx_CONCAT (mode
, realpart
, imagpart
);
1197 /* Do not call gen_reg_rtx with uninitialized crtl. */
1198 gcc_assert (crtl
->emit
.regno_pointer_align_length
);
1200 crtl
->emit
.ensure_regno_capacity ();
1201 gcc_assert (reg_rtx_no
< crtl
->emit
.regno_pointer_align_length
);
1203 val
= gen_raw_REG (mode
, reg_rtx_no
);
1204 regno_reg_rtx
[reg_rtx_no
++] = val
;
1208 /* Make sure m_regno_pointer_align, and regno_reg_rtx are large
1209 enough to have elements in the range 0 <= idx <= reg_rtx_no. */
1212 emit_status::ensure_regno_capacity ()
1214 int old_size
= regno_pointer_align_length
;
1216 if (reg_rtx_no
< old_size
)
1219 int new_size
= old_size
* 2;
1220 while (reg_rtx_no
>= new_size
)
1223 char *tmp
= XRESIZEVEC (char, regno_pointer_align
, new_size
);
1224 memset (tmp
+ old_size
, 0, new_size
- old_size
);
1225 regno_pointer_align
= (unsigned char *) tmp
;
1227 rtx
*new1
= GGC_RESIZEVEC (rtx
, regno_reg_rtx
, new_size
);
1228 memset (new1
+ old_size
, 0, (new_size
- old_size
) * sizeof (rtx
));
1229 regno_reg_rtx
= new1
;
1231 crtl
->emit
.regno_pointer_align_length
= new_size
;
1234 /* Return TRUE if REG is a PARM_DECL, FALSE otherwise. */
1237 reg_is_parm_p (rtx reg
)
1241 gcc_assert (REG_P (reg
));
1242 decl
= REG_EXPR (reg
);
1243 return (decl
&& TREE_CODE (decl
) == PARM_DECL
);
1246 /* Update NEW with the same attributes as REG, but with OFFSET added
1247 to the REG_OFFSET. */
1250 update_reg_offset (rtx new_rtx
, rtx reg
, poly_int64 offset
)
1252 REG_ATTRS (new_rtx
) = get_reg_attrs (REG_EXPR (reg
),
1253 REG_OFFSET (reg
) + offset
);
1256 /* Generate a register with same attributes as REG, but with OFFSET
1257 added to the REG_OFFSET. */
1260 gen_rtx_REG_offset (rtx reg
, machine_mode mode
, unsigned int regno
,
1263 rtx new_rtx
= gen_rtx_REG (mode
, regno
);
1265 update_reg_offset (new_rtx
, reg
, offset
);
1269 /* Generate a new pseudo-register with the same attributes as REG, but
1270 with OFFSET added to the REG_OFFSET. */
1273 gen_reg_rtx_offset (rtx reg
, machine_mode mode
, int offset
)
1275 rtx new_rtx
= gen_reg_rtx (mode
);
1277 update_reg_offset (new_rtx
, reg
, offset
);
1281 /* Adjust REG in-place so that it has mode MODE. It is assumed that the
1282 new register is a (possibly paradoxical) lowpart of the old one. */
1285 adjust_reg_mode (rtx reg
, machine_mode mode
)
1287 update_reg_offset (reg
, reg
, byte_lowpart_offset (mode
, GET_MODE (reg
)));
1288 PUT_MODE (reg
, mode
);
1291 /* Copy REG's attributes from X, if X has any attributes. If REG and X
1292 have different modes, REG is a (possibly paradoxical) lowpart of X. */
1295 set_reg_attrs_from_value (rtx reg
, rtx x
)
1298 bool can_be_reg_pointer
= true;
1300 /* Don't call mark_reg_pointer for incompatible pointer sign
1302 while (GET_CODE (x
) == SIGN_EXTEND
1303 || GET_CODE (x
) == ZERO_EXTEND
1304 || GET_CODE (x
) == TRUNCATE
1305 || (GET_CODE (x
) == SUBREG
&& subreg_lowpart_p (x
)))
1307 #if defined(POINTERS_EXTEND_UNSIGNED)
1308 if (((GET_CODE (x
) == SIGN_EXTEND
&& POINTERS_EXTEND_UNSIGNED
)
1309 || (GET_CODE (x
) == ZERO_EXTEND
&& ! POINTERS_EXTEND_UNSIGNED
)
1310 || (paradoxical_subreg_p (x
)
1311 && ! (SUBREG_PROMOTED_VAR_P (x
)
1312 && SUBREG_CHECK_PROMOTED_SIGN (x
,
1313 POINTERS_EXTEND_UNSIGNED
))))
1314 && !targetm
.have_ptr_extend ())
1315 can_be_reg_pointer
= false;
1320 /* Hard registers can be reused for multiple purposes within the same
1321 function, so setting REG_ATTRS, REG_POINTER and REG_POINTER_ALIGN
1322 on them is wrong. */
1323 if (HARD_REGISTER_P (reg
))
1326 offset
= byte_lowpart_offset (GET_MODE (reg
), GET_MODE (x
));
1329 if (MEM_OFFSET_KNOWN_P (x
))
1330 REG_ATTRS (reg
) = get_reg_attrs (MEM_EXPR (x
),
1331 MEM_OFFSET (x
) + offset
);
1332 if (can_be_reg_pointer
&& MEM_POINTER (x
))
1333 mark_reg_pointer (reg
, 0);
1338 update_reg_offset (reg
, x
, offset
);
1339 if (can_be_reg_pointer
&& REG_POINTER (x
))
1340 mark_reg_pointer (reg
, REGNO_POINTER_ALIGN (REGNO (x
)));
1344 /* Generate a REG rtx for a new pseudo register, copying the mode
1345 and attributes from X. */
1348 gen_reg_rtx_and_attrs (rtx x
)
1350 rtx reg
= gen_reg_rtx (GET_MODE (x
));
1351 set_reg_attrs_from_value (reg
, x
);
1355 /* Set the register attributes for registers contained in PARM_RTX.
1356 Use needed values from memory attributes of MEM. */
1359 set_reg_attrs_for_parm (rtx parm_rtx
, rtx mem
)
1361 if (REG_P (parm_rtx
))
1362 set_reg_attrs_from_value (parm_rtx
, mem
);
1363 else if (GET_CODE (parm_rtx
) == PARALLEL
)
1365 /* Check for a NULL entry in the first slot, used to indicate that the
1366 parameter goes both on the stack and in registers. */
1367 int i
= XEXP (XVECEXP (parm_rtx
, 0, 0), 0) ? 0 : 1;
1368 for (; i
< XVECLEN (parm_rtx
, 0); i
++)
1370 rtx x
= XVECEXP (parm_rtx
, 0, i
);
1371 if (REG_P (XEXP (x
, 0)))
1372 REG_ATTRS (XEXP (x
, 0))
1373 = get_reg_attrs (MEM_EXPR (mem
),
1374 INTVAL (XEXP (x
, 1)));
1379 /* Set the REG_ATTRS for registers in value X, given that X represents
1383 set_reg_attrs_for_decl_rtl (tree t
, rtx x
)
1388 if (GET_CODE (x
) == SUBREG
)
1390 gcc_assert (subreg_lowpart_p (x
));
1395 = get_reg_attrs (t
, byte_lowpart_offset (GET_MODE (x
),
1398 : TYPE_MODE (TREE_TYPE (tdecl
))));
1399 if (GET_CODE (x
) == CONCAT
)
1401 if (REG_P (XEXP (x
, 0)))
1402 REG_ATTRS (XEXP (x
, 0)) = get_reg_attrs (t
, 0);
1403 if (REG_P (XEXP (x
, 1)))
1404 REG_ATTRS (XEXP (x
, 1))
1405 = get_reg_attrs (t
, GET_MODE_UNIT_SIZE (GET_MODE (XEXP (x
, 0))));
1407 if (GET_CODE (x
) == PARALLEL
)
1411 /* Check for a NULL entry, used to indicate that the parameter goes
1412 both on the stack and in registers. */
1413 if (XEXP (XVECEXP (x
, 0, 0), 0))
1418 for (i
= start
; i
< XVECLEN (x
, 0); i
++)
1420 rtx y
= XVECEXP (x
, 0, i
);
1421 if (REG_P (XEXP (y
, 0)))
1422 REG_ATTRS (XEXP (y
, 0)) = get_reg_attrs (t
, INTVAL (XEXP (y
, 1)));
1427 /* Assign the RTX X to declaration T. */
1430 set_decl_rtl (tree t
, rtx x
)
1432 DECL_WRTL_CHECK (t
)->decl_with_rtl
.rtl
= x
;
1434 set_reg_attrs_for_decl_rtl (t
, x
);
1437 /* Assign the RTX X to parameter declaration T. BY_REFERENCE_P is true
1438 if the ABI requires the parameter to be passed by reference. */
1441 set_decl_incoming_rtl (tree t
, rtx x
, bool by_reference_p
)
1443 DECL_INCOMING_RTL (t
) = x
;
1444 if (x
&& !by_reference_p
)
1445 set_reg_attrs_for_decl_rtl (t
, x
);
1448 /* Identify REG (which may be a CONCAT) as a user register. */
1451 mark_user_reg (rtx reg
)
1453 if (GET_CODE (reg
) == CONCAT
)
1455 REG_USERVAR_P (XEXP (reg
, 0)) = 1;
1456 REG_USERVAR_P (XEXP (reg
, 1)) = 1;
1460 gcc_assert (REG_P (reg
));
1461 REG_USERVAR_P (reg
) = 1;
1465 /* Identify REG as a probable pointer register and show its alignment
1466 as ALIGN, if nonzero. */
1469 mark_reg_pointer (rtx reg
, int align
)
1471 if (! REG_POINTER (reg
))
1473 REG_POINTER (reg
) = 1;
1476 REGNO_POINTER_ALIGN (REGNO (reg
)) = align
;
1478 else if (align
&& align
< REGNO_POINTER_ALIGN (REGNO (reg
)))
1479 /* We can no-longer be sure just how aligned this pointer is. */
1480 REGNO_POINTER_ALIGN (REGNO (reg
)) = align
;
1483 /* Return 1 plus largest pseudo reg number used in the current function. */
1491 /* Return 1 + the largest label number used so far in the current function. */
1494 max_label_num (void)
1499 /* Return first label number used in this function (if any were used). */
1502 get_first_label_num (void)
1504 return first_label_num
;
1507 /* If the rtx for label was created during the expansion of a nested
1508 function, then first_label_num won't include this label number.
1509 Fix this now so that array indices work later. */
1512 maybe_set_first_label_num (rtx_code_label
*x
)
1514 if (CODE_LABEL_NUMBER (x
) < first_label_num
)
1515 first_label_num
= CODE_LABEL_NUMBER (x
);
1518 /* For use by the RTL function loader, when mingling with normal
1520 Ensure that label_num is greater than the label num of X, to avoid
1521 duplicate labels in the generated assembler. */
1524 maybe_set_max_label_num (rtx_code_label
*x
)
1526 if (CODE_LABEL_NUMBER (x
) >= label_num
)
1527 label_num
= CODE_LABEL_NUMBER (x
) + 1;
1531 /* Return a value representing some low-order bits of X, where the number
1532 of low-order bits is given by MODE. Note that no conversion is done
1533 between floating-point and fixed-point values, rather, the bit
1534 representation is returned.
1536 This function handles the cases in common between gen_lowpart, below,
1537 and two variants in cse.c and combine.c. These are the cases that can
1538 be safely handled at all points in the compilation.
1540 If this is not a case we can handle, return 0. */
1543 gen_lowpart_common (machine_mode mode
, rtx x
)
1545 poly_uint64 msize
= GET_MODE_SIZE (mode
);
1546 machine_mode innermode
;
1548 /* Unfortunately, this routine doesn't take a parameter for the mode of X,
1549 so we have to make one up. Yuk. */
1550 innermode
= GET_MODE (x
);
1552 && known_le (msize
* BITS_PER_UNIT
,
1553 (unsigned HOST_WIDE_INT
) HOST_BITS_PER_WIDE_INT
))
1554 innermode
= int_mode_for_size (HOST_BITS_PER_WIDE_INT
, 0).require ();
1555 else if (innermode
== VOIDmode
)
1556 innermode
= int_mode_for_size (HOST_BITS_PER_DOUBLE_INT
, 0).require ();
1558 gcc_assert (innermode
!= VOIDmode
&& innermode
!= BLKmode
);
1560 if (innermode
== mode
)
1563 /* The size of the outer and inner modes must be ordered. */
1564 poly_uint64 xsize
= GET_MODE_SIZE (innermode
);
1565 if (!ordered_p (msize
, xsize
))
1568 if (SCALAR_FLOAT_MODE_P (mode
))
1570 /* Don't allow paradoxical FLOAT_MODE subregs. */
1571 if (maybe_gt (msize
, xsize
))
1576 /* MODE must occupy no more of the underlying registers than X. */
1577 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (innermode
);
1578 unsigned int mregs
, xregs
;
1579 if (!can_div_away_from_zero_p (msize
, regsize
, &mregs
)
1580 || !can_div_away_from_zero_p (xsize
, regsize
, &xregs
)
1585 scalar_int_mode int_mode
, int_innermode
, from_mode
;
1586 if ((GET_CODE (x
) == ZERO_EXTEND
|| GET_CODE (x
) == SIGN_EXTEND
)
1587 && is_a
<scalar_int_mode
> (mode
, &int_mode
)
1588 && is_a
<scalar_int_mode
> (innermode
, &int_innermode
)
1589 && is_a
<scalar_int_mode
> (GET_MODE (XEXP (x
, 0)), &from_mode
))
1591 /* If we are getting the low-order part of something that has been
1592 sign- or zero-extended, we can either just use the object being
1593 extended or make a narrower extension. If we want an even smaller
1594 piece than the size of the object being extended, call ourselves
1597 This case is used mostly by combine and cse. */
1599 if (from_mode
== int_mode
)
1601 else if (GET_MODE_SIZE (int_mode
) < GET_MODE_SIZE (from_mode
))
1602 return gen_lowpart_common (int_mode
, XEXP (x
, 0));
1603 else if (GET_MODE_SIZE (int_mode
) < GET_MODE_SIZE (int_innermode
))
1604 return gen_rtx_fmt_e (GET_CODE (x
), int_mode
, XEXP (x
, 0));
1606 else if (GET_CODE (x
) == SUBREG
|| REG_P (x
)
1607 || GET_CODE (x
) == CONCAT
|| GET_CODE (x
) == CONST_VECTOR
1608 || CONST_DOUBLE_AS_FLOAT_P (x
) || CONST_SCALAR_INT_P (x
)
1609 || CONST_POLY_INT_P (x
))
1610 return lowpart_subreg (mode
, x
, innermode
);
1612 /* Otherwise, we can't do this. */
1617 gen_highpart (machine_mode mode
, rtx x
)
1619 poly_uint64 msize
= GET_MODE_SIZE (mode
);
1622 /* This case loses if X is a subreg. To catch bugs early,
1623 complain if an invalid MODE is used even in other cases. */
1624 gcc_assert (known_le (msize
, (unsigned int) UNITS_PER_WORD
)
1625 || known_eq (msize
, GET_MODE_UNIT_SIZE (GET_MODE (x
))));
1627 result
= simplify_gen_subreg (mode
, x
, GET_MODE (x
),
1628 subreg_highpart_offset (mode
, GET_MODE (x
)));
1629 gcc_assert (result
);
1631 /* simplify_gen_subreg is not guaranteed to return a valid operand for
1632 the target if we have a MEM. gen_highpart must return a valid operand,
1633 emitting code if necessary to do so. */
1636 result
= validize_mem (result
);
1637 gcc_assert (result
);
1643 /* Like gen_highpart, but accept mode of EXP operand in case EXP can
1644 be VOIDmode constant. */
1646 gen_highpart_mode (machine_mode outermode
, machine_mode innermode
, rtx exp
)
1648 if (GET_MODE (exp
) != VOIDmode
)
1650 gcc_assert (GET_MODE (exp
) == innermode
);
1651 return gen_highpart (outermode
, exp
);
1653 return simplify_gen_subreg (outermode
, exp
, innermode
,
1654 subreg_highpart_offset (outermode
, innermode
));
1657 /* Return the SUBREG_BYTE for a lowpart subreg whose outer mode has
1658 OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */
1661 subreg_size_lowpart_offset (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
)
1663 gcc_checking_assert (ordered_p (outer_bytes
, inner_bytes
));
1664 if (maybe_gt (outer_bytes
, inner_bytes
))
1665 /* Paradoxical subregs always have a SUBREG_BYTE of 0. */
1668 if (BYTES_BIG_ENDIAN
&& WORDS_BIG_ENDIAN
)
1669 return inner_bytes
- outer_bytes
;
1670 else if (!BYTES_BIG_ENDIAN
&& !WORDS_BIG_ENDIAN
)
1673 return subreg_size_offset_from_lsb (outer_bytes
, inner_bytes
, 0);
1676 /* Return the SUBREG_BYTE for a highpart subreg whose outer mode has
1677 OUTER_BYTES bytes and whose inner mode has INNER_BYTES bytes. */
1680 subreg_size_highpart_offset (poly_uint64 outer_bytes
, poly_uint64 inner_bytes
)
1682 gcc_assert (known_ge (inner_bytes
, outer_bytes
));
1684 if (BYTES_BIG_ENDIAN
&& WORDS_BIG_ENDIAN
)
1686 else if (!BYTES_BIG_ENDIAN
&& !WORDS_BIG_ENDIAN
)
1687 return inner_bytes
- outer_bytes
;
1689 return subreg_size_offset_from_lsb (outer_bytes
, inner_bytes
,
1690 (inner_bytes
- outer_bytes
)
1694 /* Return 1 iff X, assumed to be a SUBREG,
1695 refers to the least significant part of its containing reg.
1696 If X is not a SUBREG, always return 1 (it is its own low part!). */
1699 subreg_lowpart_p (const_rtx x
)
1701 if (GET_CODE (x
) != SUBREG
)
1703 else if (GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
1706 return known_eq (subreg_lowpart_offset (GET_MODE (x
),
1707 GET_MODE (SUBREG_REG (x
))),
1711 /* Return subword OFFSET of operand OP.
1712 The word number, OFFSET, is interpreted as the word number starting
1713 at the low-order address. OFFSET 0 is the low-order word if not
1714 WORDS_BIG_ENDIAN, otherwise it is the high-order word.
1716 If we cannot extract the required word, we return zero. Otherwise,
1717 an rtx corresponding to the requested word will be returned.
1719 VALIDATE_ADDRESS is nonzero if the address should be validated. Before
1720 reload has completed, a valid address will always be returned. After
1721 reload, if a valid address cannot be returned, we return zero.
1723 If VALIDATE_ADDRESS is zero, we simply form the required address; validating
1724 it is the responsibility of the caller.
1726 MODE is the mode of OP in case it is a CONST_INT.
1728 ??? This is still rather broken for some cases. The problem for the
1729 moment is that all callers of this thing provide no 'goal mode' to
1730 tell us to work with. This exists because all callers were written
1731 in a word based SUBREG world.
1732 Now use of this function can be deprecated by simplify_subreg in most
1737 operand_subword (rtx op
, poly_uint64 offset
, int validate_address
,
1740 if (mode
== VOIDmode
)
1741 mode
= GET_MODE (op
);
1743 gcc_assert (mode
!= VOIDmode
);
1745 /* If OP is narrower than a word, fail. */
1747 && maybe_lt (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
1750 /* If we want a word outside OP, return zero. */
1752 && maybe_gt ((offset
+ 1) * UNITS_PER_WORD
, GET_MODE_SIZE (mode
)))
1755 /* Form a new MEM at the requested address. */
1758 rtx new_rtx
= adjust_address_nv (op
, word_mode
, offset
* UNITS_PER_WORD
);
1760 if (! validate_address
)
1763 else if (reload_completed
)
1765 if (! strict_memory_address_addr_space_p (word_mode
,
1767 MEM_ADDR_SPACE (op
)))
1771 return replace_equiv_address (new_rtx
, XEXP (new_rtx
, 0));
1774 /* Rest can be handled by simplify_subreg. */
1775 return simplify_gen_subreg (word_mode
, op
, mode
, (offset
* UNITS_PER_WORD
));
1778 /* Similar to `operand_subword', but never return 0. If we can't
1779 extract the required subword, put OP into a register and try again.
1780 The second attempt must succeed. We always validate the address in
1783 MODE is the mode of OP, in case it is CONST_INT. */
1786 operand_subword_force (rtx op
, poly_uint64 offset
, machine_mode mode
)
1788 rtx result
= operand_subword (op
, offset
, 1, mode
);
1793 if (mode
!= BLKmode
&& mode
!= VOIDmode
)
1795 /* If this is a register which cannot be accessed by words, copy it
1796 to a pseudo register. */
1798 op
= copy_to_reg (op
);
1800 op
= force_reg (mode
, op
);
1803 result
= operand_subword (op
, offset
, 1, mode
);
1804 gcc_assert (result
);
1809 mem_attrs::mem_attrs ()
1815 addrspace (ADDR_SPACE_GENERIC
),
1816 offset_known_p (false),
1817 size_known_p (false)
1820 /* Returns 1 if both MEM_EXPR can be considered equal
1824 mem_expr_equal_p (const_tree expr1
, const_tree expr2
)
1829 if (! expr1
|| ! expr2
)
1832 if (TREE_CODE (expr1
) != TREE_CODE (expr2
))
1835 return operand_equal_p (expr1
, expr2
, 0);
1838 /* Return OFFSET if XEXP (MEM, 0) - OFFSET is known to be ALIGN
1839 bits aligned for 0 <= OFFSET < ALIGN / BITS_PER_UNIT, or
1843 get_mem_align_offset (rtx mem
, unsigned int align
)
1848 /* This function can't use
1849 if (!MEM_EXPR (mem) || !MEM_OFFSET_KNOWN_P (mem)
1850 || (MAX (MEM_ALIGN (mem),
1851 MAX (align, get_object_alignment (MEM_EXPR (mem))))
1855 return (- MEM_OFFSET (mem)) & (align / BITS_PER_UNIT - 1);
1857 - COMPONENT_REFs in MEM_EXPR can have NULL first operand,
1858 for <variable>. get_inner_reference doesn't handle it and
1859 even if it did, the alignment in that case needs to be determined
1860 from DECL_FIELD_CONTEXT's TYPE_ALIGN.
1861 - it would do suboptimal job for COMPONENT_REFs, even if MEM_EXPR
1862 isn't sufficiently aligned, the object it is in might be. */
1863 gcc_assert (MEM_P (mem
));
1864 expr
= MEM_EXPR (mem
);
1865 if (expr
== NULL_TREE
|| !MEM_OFFSET_KNOWN_P (mem
))
1868 offset
= MEM_OFFSET (mem
);
1871 if (DECL_ALIGN (expr
) < align
)
1874 else if (INDIRECT_REF_P (expr
))
1876 if (TYPE_ALIGN (TREE_TYPE (expr
)) < (unsigned int) align
)
1879 else if (TREE_CODE (expr
) == COMPONENT_REF
)
1883 tree inner
= TREE_OPERAND (expr
, 0);
1884 tree field
= TREE_OPERAND (expr
, 1);
1885 tree byte_offset
= component_ref_field_offset (expr
);
1886 tree bit_offset
= DECL_FIELD_BIT_OFFSET (field
);
1888 poly_uint64 suboffset
;
1890 || !poly_int_tree_p (byte_offset
, &suboffset
)
1891 || !tree_fits_uhwi_p (bit_offset
))
1894 offset
+= suboffset
;
1895 offset
+= tree_to_uhwi (bit_offset
) / BITS_PER_UNIT
;
1897 if (inner
== NULL_TREE
)
1899 if (TYPE_ALIGN (DECL_FIELD_CONTEXT (field
))
1900 < (unsigned int) align
)
1904 else if (DECL_P (inner
))
1906 if (DECL_ALIGN (inner
) < align
)
1910 else if (TREE_CODE (inner
) != COMPONENT_REF
)
1918 HOST_WIDE_INT misalign
;
1919 if (!known_misalignment (offset
, align
/ BITS_PER_UNIT
, &misalign
))
1924 /* Given REF (a MEM) and T, either the type of X or the expression
1925 corresponding to REF, set the memory attributes. OBJECTP is nonzero
1926 if we are making a new object of this type. BITPOS is nonzero if
1927 there is an offset outstanding on T that will be applied later. */
1930 set_mem_attributes_minus_bitpos (rtx ref
, tree t
, int objectp
,
1933 poly_int64 apply_bitpos
= 0;
1935 class mem_attrs attrs
, *defattrs
, *refattrs
;
1938 /* It can happen that type_for_mode was given a mode for which there
1939 is no language-level type. In which case it returns NULL, which
1944 type
= TYPE_P (t
) ? t
: TREE_TYPE (t
);
1945 if (type
== error_mark_node
)
1948 /* If we have already set DECL_RTL = ref, get_alias_set will get the
1949 wrong answer, as it assumes that DECL_RTL already has the right alias
1950 info. Callers should not set DECL_RTL until after the call to
1951 set_mem_attributes. */
1952 gcc_assert (!DECL_P (t
) || ref
!= DECL_RTL_IF_SET (t
));
1954 /* Get the alias set from the expression or type (perhaps using a
1955 front-end routine) and use it. */
1956 attrs
.alias
= get_alias_set (t
);
1958 MEM_VOLATILE_P (ref
) |= TYPE_VOLATILE (type
);
1959 MEM_POINTER (ref
) = POINTER_TYPE_P (type
);
1961 /* Default values from pre-existing memory attributes if present. */
1962 refattrs
= MEM_ATTRS (ref
);
1965 /* ??? Can this ever happen? Calling this routine on a MEM that
1966 already carries memory attributes should probably be invalid. */
1967 attrs
.expr
= refattrs
->expr
;
1968 attrs
.offset_known_p
= refattrs
->offset_known_p
;
1969 attrs
.offset
= refattrs
->offset
;
1970 attrs
.size_known_p
= refattrs
->size_known_p
;
1971 attrs
.size
= refattrs
->size
;
1972 attrs
.align
= refattrs
->align
;
1975 /* Otherwise, default values from the mode of the MEM reference. */
1978 defattrs
= mode_mem_attrs
[(int) GET_MODE (ref
)];
1979 gcc_assert (!defattrs
->expr
);
1980 gcc_assert (!defattrs
->offset_known_p
);
1982 /* Respect mode size. */
1983 attrs
.size_known_p
= defattrs
->size_known_p
;
1984 attrs
.size
= defattrs
->size
;
1985 /* ??? Is this really necessary? We probably should always get
1986 the size from the type below. */
1988 /* Respect mode alignment for STRICT_ALIGNMENT targets if T is a type;
1989 if T is an object, always compute the object alignment below. */
1991 attrs
.align
= defattrs
->align
;
1993 attrs
.align
= BITS_PER_UNIT
;
1994 /* ??? If T is a type, respecting mode alignment may *also* be wrong
1995 e.g. if the type carries an alignment attribute. Should we be
1996 able to simply always use TYPE_ALIGN? */
1999 /* We can set the alignment from the type if we are making an object or if
2000 this is an INDIRECT_REF. */
2001 if (objectp
|| TREE_CODE (t
) == INDIRECT_REF
)
2002 attrs
.align
= MAX (attrs
.align
, TYPE_ALIGN (type
));
2004 /* If the size is known, we can set that. */
2005 tree new_size
= TYPE_SIZE_UNIT (type
);
2007 /* The address-space is that of the type. */
2008 as
= TYPE_ADDR_SPACE (type
);
2010 /* If T is not a type, we may be able to deduce some more information about
2016 if (TREE_THIS_VOLATILE (t
))
2017 MEM_VOLATILE_P (ref
) = 1;
2019 /* Now remove any conversions: they don't change what the underlying
2020 object is. Likewise for SAVE_EXPR. */
2021 while (CONVERT_EXPR_P (t
)
2022 || TREE_CODE (t
) == VIEW_CONVERT_EXPR
2023 || TREE_CODE (t
) == SAVE_EXPR
)
2024 t
= TREE_OPERAND (t
, 0);
2026 /* Note whether this expression can trap. */
2027 MEM_NOTRAP_P (ref
) = !tree_could_trap_p (t
);
2029 base
= get_base_address (t
);
2033 && TREE_READONLY (base
)
2034 && (TREE_STATIC (base
) || DECL_EXTERNAL (base
))
2035 && !TREE_THIS_VOLATILE (base
))
2036 MEM_READONLY_P (ref
) = 1;
2038 /* Mark static const strings readonly as well. */
2039 if (TREE_CODE (base
) == STRING_CST
2040 && TREE_READONLY (base
)
2041 && TREE_STATIC (base
))
2042 MEM_READONLY_P (ref
) = 1;
2044 /* Address-space information is on the base object. */
2045 if (TREE_CODE (base
) == MEM_REF
2046 || TREE_CODE (base
) == TARGET_MEM_REF
)
2047 as
= TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (base
,
2050 as
= TYPE_ADDR_SPACE (TREE_TYPE (base
));
2053 /* If this expression uses it's parent's alias set, mark it such
2054 that we won't change it. */
2055 if (component_uses_parent_alias_set_from (t
) != NULL_TREE
)
2056 MEM_KEEP_ALIAS_SET_P (ref
) = 1;
2058 /* If this is a decl, set the attributes of the MEM from it. */
2062 attrs
.offset_known_p
= true;
2064 apply_bitpos
= bitpos
;
2065 new_size
= DECL_SIZE_UNIT (t
);
2068 /* ??? If we end up with a constant here do record a MEM_EXPR. */
2069 else if (CONSTANT_CLASS_P (t
))
2072 /* If this is a field reference, record it. */
2073 else if (TREE_CODE (t
) == COMPONENT_REF
)
2076 attrs
.offset_known_p
= true;
2078 apply_bitpos
= bitpos
;
2079 if (DECL_BIT_FIELD (TREE_OPERAND (t
, 1)))
2080 new_size
= DECL_SIZE_UNIT (TREE_OPERAND (t
, 1));
2083 /* If this is an array reference, look for an outer field reference. */
2084 else if (TREE_CODE (t
) == ARRAY_REF
)
2086 tree off_tree
= size_zero_node
;
2087 /* We can't modify t, because we use it at the end of the
2093 tree index
= TREE_OPERAND (t2
, 1);
2094 tree low_bound
= array_ref_low_bound (t2
);
2095 tree unit_size
= array_ref_element_size (t2
);
2097 /* We assume all arrays have sizes that are a multiple of a byte.
2098 First subtract the lower bound, if any, in the type of the
2099 index, then convert to sizetype and multiply by the size of
2100 the array element. */
2101 if (! integer_zerop (low_bound
))
2102 index
= fold_build2 (MINUS_EXPR
, TREE_TYPE (index
),
2105 off_tree
= size_binop (PLUS_EXPR
,
2106 size_binop (MULT_EXPR
,
2107 fold_convert (sizetype
,
2111 t2
= TREE_OPERAND (t2
, 0);
2113 while (TREE_CODE (t2
) == ARRAY_REF
);
2116 || (TREE_CODE (t2
) == COMPONENT_REF
2117 /* For trailing arrays t2 doesn't have a size that
2118 covers all valid accesses. */
2119 && ! array_at_struct_end_p (t
)))
2122 attrs
.offset_known_p
= false;
2123 if (poly_int_tree_p (off_tree
, &attrs
.offset
))
2125 attrs
.offset_known_p
= true;
2126 apply_bitpos
= bitpos
;
2129 /* Else do not record a MEM_EXPR. */
2132 /* If this is an indirect reference, record it. */
2133 else if (TREE_CODE (t
) == MEM_REF
2134 || TREE_CODE (t
) == TARGET_MEM_REF
)
2137 attrs
.offset_known_p
= true;
2139 apply_bitpos
= bitpos
;
2142 /* If this is a reference based on a partitioned decl replace the
2143 base with a MEM_REF of the pointer representative we created
2144 during stack slot partitioning. */
2147 && ! is_global_var (base
)
2148 && cfun
->gimple_df
->decls_to_pointers
!= NULL
)
2150 tree
*namep
= cfun
->gimple_df
->decls_to_pointers
->get (base
);
2153 attrs
.expr
= unshare_expr (attrs
.expr
);
2154 tree
*orig_base
= &attrs
.expr
;
2155 while (handled_component_p (*orig_base
))
2156 orig_base
= &TREE_OPERAND (*orig_base
, 0);
2157 tree aptrt
= reference_alias_ptr_type (*orig_base
);
2158 *orig_base
= build2 (MEM_REF
, TREE_TYPE (*orig_base
), *namep
,
2159 build_int_cst (aptrt
, 0));
2163 /* Compute the alignment. */
2164 unsigned int obj_align
;
2165 unsigned HOST_WIDE_INT obj_bitpos
;
2166 get_object_alignment_1 (t
, &obj_align
, &obj_bitpos
);
2167 unsigned int diff_align
= known_alignment (obj_bitpos
- bitpos
);
2168 if (diff_align
!= 0)
2169 obj_align
= MIN (obj_align
, diff_align
);
2170 attrs
.align
= MAX (attrs
.align
, obj_align
);
2173 poly_uint64 const_size
;
2174 if (poly_int_tree_p (new_size
, &const_size
))
2176 attrs
.size_known_p
= true;
2177 attrs
.size
= const_size
;
2180 /* If we modified OFFSET based on T, then subtract the outstanding
2181 bit position offset. Similarly, increase the size of the accessed
2182 object to contain the negative offset. */
2183 if (maybe_ne (apply_bitpos
, 0))
2185 gcc_assert (attrs
.offset_known_p
);
2186 poly_int64 bytepos
= bits_to_bytes_round_down (apply_bitpos
);
2187 attrs
.offset
-= bytepos
;
2188 if (attrs
.size_known_p
)
2189 attrs
.size
+= bytepos
;
2192 /* Now set the attributes we computed above. */
2193 attrs
.addrspace
= as
;
2194 set_mem_attrs (ref
, &attrs
);
2198 set_mem_attributes (rtx ref
, tree t
, int objectp
)
2200 set_mem_attributes_minus_bitpos (ref
, t
, objectp
, 0);
2203 /* Set the alias set of MEM to SET. */
2206 set_mem_alias_set (rtx mem
, alias_set_type set
)
2208 /* If the new and old alias sets don't conflict, something is wrong. */
2209 gcc_checking_assert (alias_sets_conflict_p (set
, MEM_ALIAS_SET (mem
)));
2210 mem_attrs
attrs (*get_mem_attrs (mem
));
2212 set_mem_attrs (mem
, &attrs
);
2215 /* Set the address space of MEM to ADDRSPACE (target-defined). */
2218 set_mem_addr_space (rtx mem
, addr_space_t addrspace
)
2220 mem_attrs
attrs (*get_mem_attrs (mem
));
2221 attrs
.addrspace
= addrspace
;
2222 set_mem_attrs (mem
, &attrs
);
2225 /* Set the alignment of MEM to ALIGN bits. */
2228 set_mem_align (rtx mem
, unsigned int align
)
2230 mem_attrs
attrs (*get_mem_attrs (mem
));
2231 attrs
.align
= align
;
2232 set_mem_attrs (mem
, &attrs
);
2235 /* Set the expr for MEM to EXPR. */
2238 set_mem_expr (rtx mem
, tree expr
)
2240 mem_attrs
attrs (*get_mem_attrs (mem
));
2242 set_mem_attrs (mem
, &attrs
);
2245 /* Set the offset of MEM to OFFSET. */
2248 set_mem_offset (rtx mem
, poly_int64 offset
)
2250 mem_attrs
attrs (*get_mem_attrs (mem
));
2251 attrs
.offset_known_p
= true;
2252 attrs
.offset
= offset
;
2253 set_mem_attrs (mem
, &attrs
);
2256 /* Clear the offset of MEM. */
2259 clear_mem_offset (rtx mem
)
2261 mem_attrs
attrs (*get_mem_attrs (mem
));
2262 attrs
.offset_known_p
= false;
2263 set_mem_attrs (mem
, &attrs
);
2266 /* Set the size of MEM to SIZE. */
2269 set_mem_size (rtx mem
, poly_int64 size
)
2271 mem_attrs
attrs (*get_mem_attrs (mem
));
2272 attrs
.size_known_p
= true;
2274 set_mem_attrs (mem
, &attrs
);
2277 /* Clear the size of MEM. */
2280 clear_mem_size (rtx mem
)
2282 mem_attrs
attrs (*get_mem_attrs (mem
));
2283 attrs
.size_known_p
= false;
2284 set_mem_attrs (mem
, &attrs
);
2287 /* Return a memory reference like MEMREF, but with its mode changed to MODE
2288 and its address changed to ADDR. (VOIDmode means don't change the mode.
2289 NULL for ADDR means don't change the address.) VALIDATE is nonzero if the
2290 returned memory location is required to be valid. INPLACE is true if any
2291 changes can be made directly to MEMREF or false if MEMREF must be treated
2294 The memory attributes are not changed. */
2297 change_address_1 (rtx memref
, machine_mode mode
, rtx addr
, int validate
,
2303 gcc_assert (MEM_P (memref
));
2304 as
= MEM_ADDR_SPACE (memref
);
2305 if (mode
== VOIDmode
)
2306 mode
= GET_MODE (memref
);
2308 addr
= XEXP (memref
, 0);
2309 if (mode
== GET_MODE (memref
) && addr
== XEXP (memref
, 0)
2310 && (!validate
|| memory_address_addr_space_p (mode
, addr
, as
)))
2313 /* Don't validate address for LRA. LRA can make the address valid
2314 by itself in most efficient way. */
2315 if (validate
&& !lra_in_progress
)
2317 if (reload_in_progress
|| reload_completed
)
2318 gcc_assert (memory_address_addr_space_p (mode
, addr
, as
));
2320 addr
= memory_address_addr_space (mode
, addr
, as
);
2323 if (rtx_equal_p (addr
, XEXP (memref
, 0)) && mode
== GET_MODE (memref
))
2328 XEXP (memref
, 0) = addr
;
2332 new_rtx
= gen_rtx_MEM (mode
, addr
);
2333 MEM_COPY_ATTRIBUTES (new_rtx
, memref
);
2337 /* Like change_address_1 with VALIDATE nonzero, but we are not saying in what
2338 way we are changing MEMREF, so we only preserve the alias set. */
2341 change_address (rtx memref
, machine_mode mode
, rtx addr
)
2343 rtx new_rtx
= change_address_1 (memref
, mode
, addr
, 1, false);
2344 machine_mode mmode
= GET_MODE (new_rtx
);
2345 class mem_attrs
*defattrs
;
2347 mem_attrs
attrs (*get_mem_attrs (memref
));
2348 defattrs
= mode_mem_attrs
[(int) mmode
];
2349 attrs
.expr
= NULL_TREE
;
2350 attrs
.offset_known_p
= false;
2351 attrs
.size_known_p
= defattrs
->size_known_p
;
2352 attrs
.size
= defattrs
->size
;
2353 attrs
.align
= defattrs
->align
;
2355 /* If there are no changes, just return the original memory reference. */
2356 if (new_rtx
== memref
)
2358 if (mem_attrs_eq_p (get_mem_attrs (memref
), &attrs
))
2361 new_rtx
= gen_rtx_MEM (mmode
, XEXP (memref
, 0));
2362 MEM_COPY_ATTRIBUTES (new_rtx
, memref
);
2365 set_mem_attrs (new_rtx
, &attrs
);
2369 /* Return a memory reference like MEMREF, but with its mode changed
2370 to MODE and its address offset by OFFSET bytes. If VALIDATE is
2371 nonzero, the memory address is forced to be valid.
2372 If ADJUST_ADDRESS is zero, OFFSET is only used to update MEM_ATTRS
2373 and the caller is responsible for adjusting MEMREF base register.
2374 If ADJUST_OBJECT is zero, the underlying object associated with the
2375 memory reference is left unchanged and the caller is responsible for
2376 dealing with it. Otherwise, if the new memory reference is outside
2377 the underlying object, even partially, then the object is dropped.
2378 SIZE, if nonzero, is the size of an access in cases where MODE
2379 has no inherent size. */
2382 adjust_address_1 (rtx memref
, machine_mode mode
, poly_int64 offset
,
2383 int validate
, int adjust_address
, int adjust_object
,
2386 rtx addr
= XEXP (memref
, 0);
2388 scalar_int_mode address_mode
;
2389 class mem_attrs
attrs (*get_mem_attrs (memref
)), *defattrs
;
2390 unsigned HOST_WIDE_INT max_align
;
2391 #ifdef POINTERS_EXTEND_UNSIGNED
2392 scalar_int_mode pointer_mode
2393 = targetm
.addr_space
.pointer_mode (attrs
.addrspace
);
2396 /* VOIDmode means no mode change for change_address_1. */
2397 if (mode
== VOIDmode
)
2398 mode
= GET_MODE (memref
);
2400 /* Take the size of non-BLKmode accesses from the mode. */
2401 defattrs
= mode_mem_attrs
[(int) mode
];
2402 if (defattrs
->size_known_p
)
2403 size
= defattrs
->size
;
2405 /* If there are no changes, just return the original memory reference. */
2406 if (mode
== GET_MODE (memref
)
2407 && known_eq (offset
, 0)
2408 && (known_eq (size
, 0)
2409 || (attrs
.size_known_p
&& known_eq (attrs
.size
, size
)))
2410 && (!validate
|| memory_address_addr_space_p (mode
, addr
,
2414 /* ??? Prefer to create garbage instead of creating shared rtl.
2415 This may happen even if offset is nonzero -- consider
2416 (plus (plus reg reg) const_int) -- so do this always. */
2417 addr
= copy_rtx (addr
);
2419 /* Convert a possibly large offset to a signed value within the
2420 range of the target address space. */
2421 address_mode
= get_address_mode (memref
);
2422 offset
= trunc_int_for_mode (offset
, address_mode
);
2426 /* If MEMREF is a LO_SUM and the offset is within the alignment of the
2427 object, we can merge it into the LO_SUM. */
2428 if (GET_MODE (memref
) != BLKmode
2429 && GET_CODE (addr
) == LO_SUM
2430 && known_in_range_p (offset
,
2431 0, (GET_MODE_ALIGNMENT (GET_MODE (memref
))
2433 addr
= gen_rtx_LO_SUM (address_mode
, XEXP (addr
, 0),
2434 plus_constant (address_mode
,
2435 XEXP (addr
, 1), offset
));
2436 #ifdef POINTERS_EXTEND_UNSIGNED
2437 /* If MEMREF is a ZERO_EXTEND from pointer_mode and the offset is valid
2438 in that mode, we merge it into the ZERO_EXTEND. We take advantage of
2439 the fact that pointers are not allowed to overflow. */
2440 else if (POINTERS_EXTEND_UNSIGNED
> 0
2441 && GET_CODE (addr
) == ZERO_EXTEND
2442 && GET_MODE (XEXP (addr
, 0)) == pointer_mode
2443 && known_eq (trunc_int_for_mode (offset
, pointer_mode
), offset
))
2444 addr
= gen_rtx_ZERO_EXTEND (address_mode
,
2445 plus_constant (pointer_mode
,
2446 XEXP (addr
, 0), offset
));
2449 addr
= plus_constant (address_mode
, addr
, offset
);
2452 new_rtx
= change_address_1 (memref
, mode
, addr
, validate
, false);
2454 /* If the address is a REG, change_address_1 rightfully returns memref,
2455 but this would destroy memref's MEM_ATTRS. */
2456 if (new_rtx
== memref
&& maybe_ne (offset
, 0))
2457 new_rtx
= copy_rtx (new_rtx
);
2459 /* Conservatively drop the object if we don't know where we start from. */
2460 if (adjust_object
&& (!attrs
.offset_known_p
|| !attrs
.size_known_p
))
2462 attrs
.expr
= NULL_TREE
;
2466 /* Compute the new values of the memory attributes due to this adjustment.
2467 We add the offsets and update the alignment. */
2468 if (attrs
.offset_known_p
)
2470 attrs
.offset
+= offset
;
2472 /* Drop the object if the new left end is not within its bounds. */
2473 if (adjust_object
&& maybe_lt (attrs
.offset
, 0))
2475 attrs
.expr
= NULL_TREE
;
2480 /* Compute the new alignment by taking the MIN of the alignment and the
2481 lowest-order set bit in OFFSET, but don't change the alignment if OFFSET
2483 if (maybe_ne (offset
, 0))
2485 max_align
= known_alignment (offset
) * BITS_PER_UNIT
;
2486 attrs
.align
= MIN (attrs
.align
, max_align
);
2489 if (maybe_ne (size
, 0))
2491 /* Drop the object if the new right end is not within its bounds. */
2492 if (adjust_object
&& maybe_gt (offset
+ size
, attrs
.size
))
2494 attrs
.expr
= NULL_TREE
;
2497 attrs
.size_known_p
= true;
2500 else if (attrs
.size_known_p
)
2502 gcc_assert (!adjust_object
);
2503 attrs
.size
-= offset
;
2504 /* ??? The store_by_pieces machinery generates negative sizes,
2505 so don't assert for that here. */
2508 set_mem_attrs (new_rtx
, &attrs
);
2513 /* Return a memory reference like MEMREF, but with its mode changed
2514 to MODE and its address changed to ADDR, which is assumed to be
2515 MEMREF offset by OFFSET bytes. If VALIDATE is
2516 nonzero, the memory address is forced to be valid. */
2519 adjust_automodify_address_1 (rtx memref
, machine_mode mode
, rtx addr
,
2520 poly_int64 offset
, int validate
)
2522 memref
= change_address_1 (memref
, VOIDmode
, addr
, validate
, false);
2523 return adjust_address_1 (memref
, mode
, offset
, validate
, 0, 0, 0);
2526 /* Return a memory reference like MEMREF, but whose address is changed by
2527 adding OFFSET, an RTX, to it. POW2 is the highest power of two factor
2528 known to be in OFFSET (possibly 1). */
2531 offset_address (rtx memref
, rtx offset
, unsigned HOST_WIDE_INT pow2
)
2533 rtx new_rtx
, addr
= XEXP (memref
, 0);
2534 machine_mode address_mode
;
2535 class mem_attrs
*defattrs
;
2537 mem_attrs
attrs (*get_mem_attrs (memref
));
2538 address_mode
= get_address_mode (memref
);
2539 new_rtx
= simplify_gen_binary (PLUS
, address_mode
, addr
, offset
);
2541 /* At this point we don't know _why_ the address is invalid. It
2542 could have secondary memory references, multiplies or anything.
2544 However, if we did go and rearrange things, we can wind up not
2545 being able to recognize the magic around pic_offset_table_rtx.
2546 This stuff is fragile, and is yet another example of why it is
2547 bad to expose PIC machinery too early. */
2548 if (! memory_address_addr_space_p (GET_MODE (memref
), new_rtx
,
2550 && GET_CODE (addr
) == PLUS
2551 && XEXP (addr
, 0) == pic_offset_table_rtx
)
2553 addr
= force_reg (GET_MODE (addr
), addr
);
2554 new_rtx
= simplify_gen_binary (PLUS
, address_mode
, addr
, offset
);
2557 update_temp_slot_address (XEXP (memref
, 0), new_rtx
);
2558 new_rtx
= change_address_1 (memref
, VOIDmode
, new_rtx
, 1, false);
2560 /* If there are no changes, just return the original memory reference. */
2561 if (new_rtx
== memref
)
2564 /* Update the alignment to reflect the offset. Reset the offset, which
2566 defattrs
= mode_mem_attrs
[(int) GET_MODE (new_rtx
)];
2567 attrs
.offset_known_p
= false;
2568 attrs
.size_known_p
= defattrs
->size_known_p
;
2569 attrs
.size
= defattrs
->size
;
2570 attrs
.align
= MIN (attrs
.align
, pow2
* BITS_PER_UNIT
);
2571 set_mem_attrs (new_rtx
, &attrs
);
2575 /* Return a memory reference like MEMREF, but with its address changed to
2576 ADDR. The caller is asserting that the actual piece of memory pointed
2577 to is the same, just the form of the address is being changed, such as
2578 by putting something into a register. INPLACE is true if any changes
2579 can be made directly to MEMREF or false if MEMREF must be treated as
2583 replace_equiv_address (rtx memref
, rtx addr
, bool inplace
)
2585 /* change_address_1 copies the memory attribute structure without change
2586 and that's exactly what we want here. */
2587 update_temp_slot_address (XEXP (memref
, 0), addr
);
2588 return change_address_1 (memref
, VOIDmode
, addr
, 1, inplace
);
2591 /* Likewise, but the reference is not required to be valid. */
2594 replace_equiv_address_nv (rtx memref
, rtx addr
, bool inplace
)
2596 return change_address_1 (memref
, VOIDmode
, addr
, 0, inplace
);
2599 /* Return a memory reference like MEMREF, but with its mode widened to
2600 MODE and offset by OFFSET. This would be used by targets that e.g.
2601 cannot issue QImode memory operations and have to use SImode memory
2602 operations plus masking logic. */
2605 widen_memory_access (rtx memref
, machine_mode mode
, poly_int64 offset
)
2607 rtx new_rtx
= adjust_address_1 (memref
, mode
, offset
, 1, 1, 0, 0);
2608 poly_uint64 size
= GET_MODE_SIZE (mode
);
2610 /* If there are no changes, just return the original memory reference. */
2611 if (new_rtx
== memref
)
2614 mem_attrs
attrs (*get_mem_attrs (new_rtx
));
2616 /* If we don't know what offset we were at within the expression, then
2617 we can't know if we've overstepped the bounds. */
2618 if (! attrs
.offset_known_p
)
2619 attrs
.expr
= NULL_TREE
;
2623 if (TREE_CODE (attrs
.expr
) == COMPONENT_REF
)
2625 tree field
= TREE_OPERAND (attrs
.expr
, 1);
2626 tree offset
= component_ref_field_offset (attrs
.expr
);
2628 if (! DECL_SIZE_UNIT (field
))
2630 attrs
.expr
= NULL_TREE
;
2634 /* Is the field at least as large as the access? If so, ok,
2635 otherwise strip back to the containing structure. */
2636 if (poly_int_tree_p (DECL_SIZE_UNIT (field
))
2637 && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (field
)), size
)
2638 && known_ge (attrs
.offset
, 0))
2641 poly_uint64 suboffset
;
2642 if (!poly_int_tree_p (offset
, &suboffset
))
2644 attrs
.expr
= NULL_TREE
;
2648 attrs
.expr
= TREE_OPERAND (attrs
.expr
, 0);
2649 attrs
.offset
+= suboffset
;
2650 attrs
.offset
+= (tree_to_uhwi (DECL_FIELD_BIT_OFFSET (field
))
2653 /* Similarly for the decl. */
2654 else if (DECL_P (attrs
.expr
)
2655 && DECL_SIZE_UNIT (attrs
.expr
)
2656 && poly_int_tree_p (DECL_SIZE_UNIT (attrs
.expr
))
2657 && known_ge (wi::to_poly_offset (DECL_SIZE_UNIT (attrs
.expr
)),
2659 && known_ge (attrs
.offset
, 0))
2663 /* The widened memory access overflows the expression, which means
2664 that it could alias another expression. Zap it. */
2665 attrs
.expr
= NULL_TREE
;
2671 attrs
.offset_known_p
= false;
2673 /* The widened memory may alias other stuff, so zap the alias set. */
2674 /* ??? Maybe use get_alias_set on any remaining expression. */
2676 attrs
.size_known_p
= true;
2678 set_mem_attrs (new_rtx
, &attrs
);
2682 /* A fake decl that is used as the MEM_EXPR of spill slots. */
2683 static GTY(()) tree spill_slot_decl
;
2686 get_spill_slot_decl (bool force_build_p
)
2688 tree d
= spill_slot_decl
;
2691 if (d
|| !force_build_p
)
2694 d
= build_decl (DECL_SOURCE_LOCATION (current_function_decl
),
2695 VAR_DECL
, get_identifier ("%sfp"), void_type_node
);
2696 DECL_ARTIFICIAL (d
) = 1;
2697 DECL_IGNORED_P (d
) = 1;
2699 spill_slot_decl
= d
;
2701 rd
= gen_rtx_MEM (BLKmode
, frame_pointer_rtx
);
2702 MEM_NOTRAP_P (rd
) = 1;
2703 mem_attrs
attrs (*mode_mem_attrs
[(int) BLKmode
]);
2704 attrs
.alias
= new_alias_set ();
2706 set_mem_attrs (rd
, &attrs
);
2707 SET_DECL_RTL (d
, rd
);
2712 /* Given MEM, a result from assign_stack_local, fill in the memory
2713 attributes as appropriate for a register allocator spill slot.
2714 These slots are not aliasable by other memory. We arrange for
2715 them all to use a single MEM_EXPR, so that the aliasing code can
2716 work properly in the case of shared spill slots. */
2719 set_mem_attrs_for_spill (rtx mem
)
2723 mem_attrs
attrs (*get_mem_attrs (mem
));
2724 attrs
.expr
= get_spill_slot_decl (true);
2725 attrs
.alias
= MEM_ALIAS_SET (DECL_RTL (attrs
.expr
));
2726 attrs
.addrspace
= ADDR_SPACE_GENERIC
;
2728 /* We expect the incoming memory to be of the form:
2729 (mem:MODE (plus (reg sfp) (const_int offset)))
2730 with perhaps the plus missing for offset = 0. */
2731 addr
= XEXP (mem
, 0);
2732 attrs
.offset_known_p
= true;
2733 strip_offset (addr
, &attrs
.offset
);
2735 set_mem_attrs (mem
, &attrs
);
2736 MEM_NOTRAP_P (mem
) = 1;
2739 /* Return a newly created CODE_LABEL rtx with a unique label number. */
2742 gen_label_rtx (void)
2744 return as_a
<rtx_code_label
*> (
2745 gen_rtx_CODE_LABEL (VOIDmode
, NULL_RTX
, NULL_RTX
,
2746 NULL
, label_num
++, NULL
));
2749 /* For procedure integration. */
2751 /* Install new pointers to the first and last insns in the chain.
2752 Also, set cur_insn_uid to one higher than the last in use.
2753 Used for an inline-procedure after copying the insn chain. */
2756 set_new_first_and_last_insn (rtx_insn
*first
, rtx_insn
*last
)
2760 set_first_insn (first
);
2761 set_last_insn (last
);
2764 if (param_min_nondebug_insn_uid
|| MAY_HAVE_DEBUG_INSNS
)
2766 int debug_count
= 0;
2768 cur_insn_uid
= param_min_nondebug_insn_uid
- 1;
2769 cur_debug_insn_uid
= 0;
2771 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2772 if (INSN_UID (insn
) < param_min_nondebug_insn_uid
)
2773 cur_debug_insn_uid
= MAX (cur_debug_insn_uid
, INSN_UID (insn
));
2776 cur_insn_uid
= MAX (cur_insn_uid
, INSN_UID (insn
));
2777 if (DEBUG_INSN_P (insn
))
2782 cur_debug_insn_uid
= param_min_nondebug_insn_uid
+ debug_count
;
2784 cur_debug_insn_uid
++;
2787 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
2788 cur_insn_uid
= MAX (cur_insn_uid
, INSN_UID (insn
));
2793 /* Go through all the RTL insn bodies and copy any invalid shared
2794 structure. This routine should only be called once. */
2797 unshare_all_rtl_1 (rtx_insn
*insn
)
2799 /* Unshare just about everything else. */
2800 unshare_all_rtl_in_chain (insn
);
2802 /* Make sure the addresses of stack slots found outside the insn chain
2803 (such as, in DECL_RTL of a variable) are not shared
2804 with the insn chain.
2806 This special care is necessary when the stack slot MEM does not
2807 actually appear in the insn chain. If it does appear, its address
2808 is unshared from all else at that point. */
2811 FOR_EACH_VEC_SAFE_ELT (stack_slot_list
, i
, temp
)
2812 (*stack_slot_list
)[i
] = copy_rtx_if_shared (temp
);
2815 /* Go through all the RTL insn bodies and copy any invalid shared
2816 structure, again. This is a fairly expensive thing to do so it
2817 should be done sparingly. */
2820 unshare_all_rtl_again (rtx_insn
*insn
)
2825 for (p
= insn
; p
; p
= NEXT_INSN (p
))
2828 reset_used_flags (PATTERN (p
));
2829 reset_used_flags (REG_NOTES (p
));
2831 reset_used_flags (CALL_INSN_FUNCTION_USAGE (p
));
2834 /* Make sure that virtual stack slots are not shared. */
2835 set_used_decls (DECL_INITIAL (cfun
->decl
));
2837 /* Make sure that virtual parameters are not shared. */
2838 for (decl
= DECL_ARGUMENTS (cfun
->decl
); decl
; decl
= DECL_CHAIN (decl
))
2839 set_used_flags (DECL_RTL (decl
));
2843 FOR_EACH_VEC_SAFE_ELT (stack_slot_list
, i
, temp
)
2844 reset_used_flags (temp
);
2846 unshare_all_rtl_1 (insn
);
2850 unshare_all_rtl (void)
2852 unshare_all_rtl_1 (get_insns ());
2854 for (tree decl
= DECL_ARGUMENTS (cfun
->decl
); decl
; decl
= DECL_CHAIN (decl
))
2856 if (DECL_RTL_SET_P (decl
))
2857 SET_DECL_RTL (decl
, copy_rtx_if_shared (DECL_RTL (decl
)));
2858 DECL_INCOMING_RTL (decl
) = copy_rtx_if_shared (DECL_INCOMING_RTL (decl
));
2865 /* Check that ORIG is not marked when it should not be and mark ORIG as in use,
2866 Recursively does the same for subexpressions. */
2869 verify_rtx_sharing (rtx orig
, rtx insn
)
2874 const char *format_ptr
;
2879 code
= GET_CODE (x
);
2881 /* These types may be freely shared. */
2897 /* SCRATCH must be shared because they represent distinct values. */
2900 /* Share clobbers of hard registers (like cc0), but do not share pseudo reg
2901 clobbers or clobbers of hard registers that originated as pseudos.
2902 This is needed to allow safe register renaming. */
2903 if (REG_P (XEXP (x
, 0))
2904 && HARD_REGISTER_NUM_P (REGNO (XEXP (x
, 0)))
2905 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x
, 0))))
2910 if (shared_const_p (orig
))
2915 /* A MEM is allowed to be shared if its address is constant. */
2916 if (CONSTANT_ADDRESS_P (XEXP (x
, 0))
2917 || reload_completed
|| reload_in_progress
)
2926 /* This rtx may not be shared. If it has already been seen,
2927 replace it with a copy of itself. */
2928 if (flag_checking
&& RTX_FLAG (x
, used
))
2930 error ("invalid rtl sharing found in the insn");
2932 error ("shared rtx");
2934 internal_error ("internal consistency failure");
2936 gcc_assert (!RTX_FLAG (x
, used
));
2938 RTX_FLAG (x
, used
) = 1;
2940 /* Now scan the subexpressions recursively. */
2942 format_ptr
= GET_RTX_FORMAT (code
);
2944 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
2946 switch (*format_ptr
++)
2949 verify_rtx_sharing (XEXP (x
, i
), insn
);
2953 if (XVEC (x
, i
) != NULL
)
2956 int len
= XVECLEN (x
, i
);
2958 for (j
= 0; j
< len
; j
++)
2960 /* We allow sharing of ASM_OPERANDS inside single
2962 if (j
&& GET_CODE (XVECEXP (x
, i
, j
)) == SET
2963 && (GET_CODE (SET_SRC (XVECEXP (x
, i
, j
)))
2965 verify_rtx_sharing (SET_DEST (XVECEXP (x
, i
, j
)), insn
);
2967 verify_rtx_sharing (XVECEXP (x
, i
, j
), insn
);
2976 /* Reset used-flags for INSN. */
2979 reset_insn_used_flags (rtx insn
)
2981 gcc_assert (INSN_P (insn
));
2982 reset_used_flags (PATTERN (insn
));
2983 reset_used_flags (REG_NOTES (insn
));
2985 reset_used_flags (CALL_INSN_FUNCTION_USAGE (insn
));
2988 /* Go through all the RTL insn bodies and clear all the USED bits. */
2991 reset_all_used_flags (void)
2995 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
2998 rtx pat
= PATTERN (p
);
2999 if (GET_CODE (pat
) != SEQUENCE
)
3000 reset_insn_used_flags (p
);
3003 gcc_assert (REG_NOTES (p
) == NULL
);
3004 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
3006 rtx insn
= XVECEXP (pat
, 0, i
);
3008 reset_insn_used_flags (insn
);
3014 /* Verify sharing in INSN. */
3017 verify_insn_sharing (rtx insn
)
3019 gcc_assert (INSN_P (insn
));
3020 verify_rtx_sharing (PATTERN (insn
), insn
);
3021 verify_rtx_sharing (REG_NOTES (insn
), insn
);
3023 verify_rtx_sharing (CALL_INSN_FUNCTION_USAGE (insn
), insn
);
3026 /* Go through all the RTL insn bodies and check that there is no unexpected
3027 sharing in between the subexpressions. */
3030 verify_rtl_sharing (void)
3034 timevar_push (TV_VERIFY_RTL_SHARING
);
3036 reset_all_used_flags ();
3038 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
3041 rtx pat
= PATTERN (p
);
3042 if (GET_CODE (pat
) != SEQUENCE
)
3043 verify_insn_sharing (p
);
3045 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
3047 rtx insn
= XVECEXP (pat
, 0, i
);
3049 verify_insn_sharing (insn
);
3053 reset_all_used_flags ();
3055 timevar_pop (TV_VERIFY_RTL_SHARING
);
3058 /* Go through all the RTL insn bodies and copy any invalid shared structure.
3059 Assumes the mark bits are cleared at entry. */
3062 unshare_all_rtl_in_chain (rtx_insn
*insn
)
3064 for (; insn
; insn
= NEXT_INSN (insn
))
3067 PATTERN (insn
) = copy_rtx_if_shared (PATTERN (insn
));
3068 REG_NOTES (insn
) = copy_rtx_if_shared (REG_NOTES (insn
));
3070 CALL_INSN_FUNCTION_USAGE (insn
)
3071 = copy_rtx_if_shared (CALL_INSN_FUNCTION_USAGE (insn
));
3075 /* Go through all virtual stack slots of a function and mark them as
3076 shared. We never replace the DECL_RTLs themselves with a copy,
3077 but expressions mentioned into a DECL_RTL cannot be shared with
3078 expressions in the instruction stream.
3080 Note that reload may convert pseudo registers into memories in-place.
3081 Pseudo registers are always shared, but MEMs never are. Thus if we
3082 reset the used flags on MEMs in the instruction stream, we must set
3083 them again on MEMs that appear in DECL_RTLs. */
3086 set_used_decls (tree blk
)
3091 for (t
= BLOCK_VARS (blk
); t
; t
= DECL_CHAIN (t
))
3092 if (DECL_RTL_SET_P (t
))
3093 set_used_flags (DECL_RTL (t
));
3095 /* Now process sub-blocks. */
3096 for (t
= BLOCK_SUBBLOCKS (blk
); t
; t
= BLOCK_CHAIN (t
))
3100 /* Mark ORIG as in use, and return a copy of it if it was already in use.
3101 Recursively does the same for subexpressions. Uses
3102 copy_rtx_if_shared_1 to reduce stack space. */
3105 copy_rtx_if_shared (rtx orig
)
3107 copy_rtx_if_shared_1 (&orig
);
3111 /* Mark *ORIG1 as in use, and set it to a copy of it if it was already in
3112 use. Recursively does the same for subexpressions. */
3115 copy_rtx_if_shared_1 (rtx
*orig1
)
3121 const char *format_ptr
;
3125 /* Repeat is used to turn tail-recursion into iteration. */
3132 code
= GET_CODE (x
);
3134 /* These types may be freely shared. */
3150 /* SCRATCH must be shared because they represent distinct values. */
3153 /* Share clobbers of hard registers (like cc0), but do not share pseudo reg
3154 clobbers or clobbers of hard registers that originated as pseudos.
3155 This is needed to allow safe register renaming. */
3156 if (REG_P (XEXP (x
, 0))
3157 && HARD_REGISTER_NUM_P (REGNO (XEXP (x
, 0)))
3158 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (x
, 0))))
3163 if (shared_const_p (x
))
3173 /* The chain of insns is not being copied. */
3180 /* This rtx may not be shared. If it has already been seen,
3181 replace it with a copy of itself. */
3183 if (RTX_FLAG (x
, used
))
3185 x
= shallow_copy_rtx (x
);
3188 RTX_FLAG (x
, used
) = 1;
3190 /* Now scan the subexpressions recursively.
3191 We can store any replaced subexpressions directly into X
3192 since we know X is not shared! Any vectors in X
3193 must be copied if X was copied. */
3195 format_ptr
= GET_RTX_FORMAT (code
);
3196 length
= GET_RTX_LENGTH (code
);
3199 for (i
= 0; i
< length
; i
++)
3201 switch (*format_ptr
++)
3205 copy_rtx_if_shared_1 (last_ptr
);
3206 last_ptr
= &XEXP (x
, i
);
3210 if (XVEC (x
, i
) != NULL
)
3213 int len
= XVECLEN (x
, i
);
3215 /* Copy the vector iff I copied the rtx and the length
3217 if (copied
&& len
> 0)
3218 XVEC (x
, i
) = gen_rtvec_v (len
, XVEC (x
, i
)->elem
);
3220 /* Call recursively on all inside the vector. */
3221 for (j
= 0; j
< len
; j
++)
3224 copy_rtx_if_shared_1 (last_ptr
);
3225 last_ptr
= &XVECEXP (x
, i
, j
);
3240 /* Set the USED bit in X and its non-shareable subparts to FLAG. */
3243 mark_used_flags (rtx x
, int flag
)
3247 const char *format_ptr
;
3250 /* Repeat is used to turn tail-recursion into iteration. */
3255 code
= GET_CODE (x
);
3257 /* These types may be freely shared so we needn't do any resetting
3281 /* The chain of insns is not being copied. */
3288 RTX_FLAG (x
, used
) = flag
;
3290 format_ptr
= GET_RTX_FORMAT (code
);
3291 length
= GET_RTX_LENGTH (code
);
3293 for (i
= 0; i
< length
; i
++)
3295 switch (*format_ptr
++)
3303 mark_used_flags (XEXP (x
, i
), flag
);
3307 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3308 mark_used_flags (XVECEXP (x
, i
, j
), flag
);
3314 /* Clear all the USED bits in X to allow copy_rtx_if_shared to be used
3315 to look for shared sub-parts. */
3318 reset_used_flags (rtx x
)
3320 mark_used_flags (x
, 0);
3323 /* Set all the USED bits in X to allow copy_rtx_if_shared to be used
3324 to look for shared sub-parts. */
3327 set_used_flags (rtx x
)
3329 mark_used_flags (x
, 1);
3332 /* Copy X if necessary so that it won't be altered by changes in OTHER.
3333 Return X or the rtx for the pseudo reg the value of X was copied into.
3334 OTHER must be valid as a SET_DEST. */
3337 make_safe_from (rtx x
, rtx other
)
3340 switch (GET_CODE (other
))
3343 other
= SUBREG_REG (other
);
3345 case STRICT_LOW_PART
:
3348 other
= XEXP (other
, 0);
3357 && GET_CODE (x
) != SUBREG
)
3359 && (REGNO (other
) < FIRST_PSEUDO_REGISTER
3360 || reg_mentioned_p (other
, x
))))
3362 rtx temp
= gen_reg_rtx (GET_MODE (x
));
3363 emit_move_insn (temp
, x
);
3369 /* Emission of insns (adding them to the doubly-linked list). */
3371 /* Return the last insn emitted, even if it is in a sequence now pushed. */
3374 get_last_insn_anywhere (void)
3376 struct sequence_stack
*seq
;
3377 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
3383 /* Return the first nonnote insn emitted in current sequence or current
3384 function. This routine looks inside SEQUENCEs. */
3387 get_first_nonnote_insn (void)
3389 rtx_insn
*insn
= get_insns ();
3394 for (insn
= next_insn (insn
);
3395 insn
&& NOTE_P (insn
);
3396 insn
= next_insn (insn
))
3400 if (NONJUMP_INSN_P (insn
)
3401 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3402 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))->insn (0);
3409 /* Return the last nonnote insn emitted in current sequence or current
3410 function. This routine looks inside SEQUENCEs. */
3413 get_last_nonnote_insn (void)
3415 rtx_insn
*insn
= get_last_insn ();
3420 for (insn
= previous_insn (insn
);
3421 insn
&& NOTE_P (insn
);
3422 insn
= previous_insn (insn
))
3426 if (NONJUMP_INSN_P (insn
))
3427 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
3428 insn
= seq
->insn (seq
->len () - 1);
3435 /* Return the number of actual (non-debug) insns emitted in this
3439 get_max_insn_count (void)
3441 int n
= cur_insn_uid
;
3443 /* The table size must be stable across -g, to avoid codegen
3444 differences due to debug insns, and not be affected by
3445 -fmin-insn-uid, to avoid excessive table size and to simplify
3446 debugging of -fcompare-debug failures. */
3447 if (cur_debug_insn_uid
> param_min_nondebug_insn_uid
)
3448 n
-= cur_debug_insn_uid
;
3450 n
-= param_min_nondebug_insn_uid
;
3456 /* Return the next insn. If it is a SEQUENCE, return the first insn
3460 next_insn (rtx_insn
*insn
)
3464 insn
= NEXT_INSN (insn
);
3465 if (insn
&& NONJUMP_INSN_P (insn
)
3466 && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3467 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))->insn (0);
3473 /* Return the previous insn. If it is a SEQUENCE, return the last insn
3477 previous_insn (rtx_insn
*insn
)
3481 insn
= PREV_INSN (insn
);
3482 if (insn
&& NONJUMP_INSN_P (insn
))
3483 if (rtx_sequence
*seq
= dyn_cast
<rtx_sequence
*> (PATTERN (insn
)))
3484 insn
= seq
->insn (seq
->len () - 1);
3490 /* Return the next insn after INSN that is not a NOTE. This routine does not
3491 look inside SEQUENCEs. */
3494 next_nonnote_insn (rtx_insn
*insn
)
3498 insn
= NEXT_INSN (insn
);
3499 if (insn
== 0 || !NOTE_P (insn
))
3506 /* Return the next insn after INSN that is not a DEBUG_INSN. This
3507 routine does not look inside SEQUENCEs. */
3510 next_nondebug_insn (rtx_insn
*insn
)
3514 insn
= NEXT_INSN (insn
);
3515 if (insn
== 0 || !DEBUG_INSN_P (insn
))
3522 /* Return the previous insn before INSN that is not a NOTE. This routine does
3523 not look inside SEQUENCEs. */
3526 prev_nonnote_insn (rtx_insn
*insn
)
3530 insn
= PREV_INSN (insn
);
3531 if (insn
== 0 || !NOTE_P (insn
))
3538 /* Return the previous insn before INSN that is not a DEBUG_INSN.
3539 This routine does not look inside SEQUENCEs. */
3542 prev_nondebug_insn (rtx_insn
*insn
)
3546 insn
= PREV_INSN (insn
);
3547 if (insn
== 0 || !DEBUG_INSN_P (insn
))
3554 /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN.
3555 This routine does not look inside SEQUENCEs. */
3558 next_nonnote_nondebug_insn (rtx_insn
*insn
)
3562 insn
= NEXT_INSN (insn
);
3563 if (insn
== 0 || (!NOTE_P (insn
) && !DEBUG_INSN_P (insn
)))
3570 /* Return the next insn after INSN that is not a NOTE nor DEBUG_INSN,
3571 but stop the search before we enter another basic block. This
3572 routine does not look inside SEQUENCEs. */
3575 next_nonnote_nondebug_insn_bb (rtx_insn
*insn
)
3579 insn
= NEXT_INSN (insn
);
3582 if (DEBUG_INSN_P (insn
))
3586 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
3593 /* Return the previous insn before INSN that is not a NOTE nor DEBUG_INSN.
3594 This routine does not look inside SEQUENCEs. */
3597 prev_nonnote_nondebug_insn (rtx_insn
*insn
)
3601 insn
= PREV_INSN (insn
);
3602 if (insn
== 0 || (!NOTE_P (insn
) && !DEBUG_INSN_P (insn
)))
3609 /* Return the previous insn before INSN that is not a NOTE nor
3610 DEBUG_INSN, but stop the search before we enter another basic
3611 block. This routine does not look inside SEQUENCEs. */
3614 prev_nonnote_nondebug_insn_bb (rtx_insn
*insn
)
3618 insn
= PREV_INSN (insn
);
3621 if (DEBUG_INSN_P (insn
))
3625 if (NOTE_INSN_BASIC_BLOCK_P (insn
))
3632 /* Return the next INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN after INSN;
3633 or 0, if there is none. This routine does not look inside
3637 next_real_insn (rtx_insn
*insn
)
3641 insn
= NEXT_INSN (insn
);
3642 if (insn
== 0 || INSN_P (insn
))
3649 /* Return the last INSN, CALL_INSN, JUMP_INSN or DEBUG_INSN before INSN;
3650 or 0, if there is none. This routine does not look inside
3654 prev_real_insn (rtx_insn
*insn
)
3658 insn
= PREV_INSN (insn
);
3659 if (insn
== 0 || INSN_P (insn
))
3666 /* Return the next INSN, CALL_INSN or JUMP_INSN after INSN;
3667 or 0, if there is none. This routine does not look inside
3671 next_real_nondebug_insn (rtx uncast_insn
)
3673 rtx_insn
*insn
= safe_as_a
<rtx_insn
*> (uncast_insn
);
3677 insn
= NEXT_INSN (insn
);
3678 if (insn
== 0 || NONDEBUG_INSN_P (insn
))
3685 /* Return the last INSN, CALL_INSN or JUMP_INSN before INSN;
3686 or 0, if there is none. This routine does not look inside
3690 prev_real_nondebug_insn (rtx_insn
*insn
)
3694 insn
= PREV_INSN (insn
);
3695 if (insn
== 0 || NONDEBUG_INSN_P (insn
))
3702 /* Return the last CALL_INSN in the current list, or 0 if there is none.
3703 This routine does not look inside SEQUENCEs. */
3706 last_call_insn (void)
3710 for (insn
= get_last_insn ();
3711 insn
&& !CALL_P (insn
);
3712 insn
= PREV_INSN (insn
))
3715 return safe_as_a
<rtx_call_insn
*> (insn
);
3718 /* Find the next insn after INSN that really does something. This routine
3719 does not look inside SEQUENCEs. After reload this also skips over
3720 standalone USE and CLOBBER insn. */
3723 active_insn_p (const rtx_insn
*insn
)
3725 return (CALL_P (insn
) || JUMP_P (insn
)
3726 || JUMP_TABLE_DATA_P (insn
) /* FIXME */
3727 || (NONJUMP_INSN_P (insn
)
3728 && (! reload_completed
3729 || (GET_CODE (PATTERN (insn
)) != USE
3730 && GET_CODE (PATTERN (insn
)) != CLOBBER
))));
3734 next_active_insn (rtx_insn
*insn
)
3738 insn
= NEXT_INSN (insn
);
3739 if (insn
== 0 || active_insn_p (insn
))
3746 /* Find the last insn before INSN that really does something. This routine
3747 does not look inside SEQUENCEs. After reload this also skips over
3748 standalone USE and CLOBBER insn. */
3751 prev_active_insn (rtx_insn
*insn
)
3755 insn
= PREV_INSN (insn
);
3756 if (insn
== 0 || active_insn_p (insn
))
3763 /* Return the next insn that uses CC0 after INSN, which is assumed to
3764 set it. This is the inverse of prev_cc0_setter (i.e., prev_cc0_setter
3765 applied to the result of this function should yield INSN).
3767 Normally, this is simply the next insn. However, if a REG_CC_USER note
3768 is present, it contains the insn that uses CC0.
3770 Return 0 if we can't find the insn. */
3773 next_cc0_user (rtx_insn
*insn
)
3775 rtx note
= find_reg_note (insn
, REG_CC_USER
, NULL_RTX
);
3778 return safe_as_a
<rtx_insn
*> (XEXP (note
, 0));
3780 insn
= next_nonnote_insn (insn
);
3781 if (insn
&& NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
3782 insn
= as_a
<rtx_sequence
*> (PATTERN (insn
))->insn (0);
3784 if (insn
&& INSN_P (insn
) && reg_mentioned_p (cc0_rtx
, PATTERN (insn
)))
3790 /* Find the insn that set CC0 for INSN. Unless INSN has a REG_CC_SETTER
3791 note, it is the previous insn. */
3794 prev_cc0_setter (rtx_insn
*insn
)
3796 rtx note
= find_reg_note (insn
, REG_CC_SETTER
, NULL_RTX
);
3799 return safe_as_a
<rtx_insn
*> (XEXP (note
, 0));
3801 insn
= prev_nonnote_insn (insn
);
3802 gcc_assert (sets_cc0_p (PATTERN (insn
)));
3807 /* Find a RTX_AUTOINC class rtx which matches DATA. */
3810 find_auto_inc (const_rtx x
, const_rtx reg
)
3812 subrtx_iterator::array_type array
;
3813 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
3815 const_rtx x
= *iter
;
3816 if (GET_RTX_CLASS (GET_CODE (x
)) == RTX_AUTOINC
3817 && rtx_equal_p (reg
, XEXP (x
, 0)))
3823 /* Increment the label uses for all labels present in rtx. */
3826 mark_label_nuses (rtx x
)
3832 code
= GET_CODE (x
);
3833 if (code
== LABEL_REF
&& LABEL_P (label_ref_label (x
)))
3834 LABEL_NUSES (label_ref_label (x
))++;
3836 fmt
= GET_RTX_FORMAT (code
);
3837 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3840 mark_label_nuses (XEXP (x
, i
));
3841 else if (fmt
[i
] == 'E')
3842 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3843 mark_label_nuses (XVECEXP (x
, i
, j
));
3848 /* Try splitting insns that can be split for better scheduling.
3849 PAT is the pattern which might split.
3850 TRIAL is the insn providing PAT.
3851 LAST is nonzero if we should return the last insn of the sequence produced.
3853 If this routine succeeds in splitting, it returns the first or last
3854 replacement insn depending on the value of LAST. Otherwise, it
3855 returns TRIAL. If the insn to be returned can be split, it will be. */
3858 try_split (rtx pat
, rtx_insn
*trial
, int last
)
3860 rtx_insn
*before
, *after
;
3862 rtx_insn
*seq
, *tem
;
3863 profile_probability probability
;
3864 rtx_insn
*insn_last
, *insn
;
3866 rtx_insn
*call_insn
= NULL
;
3868 /* We're not good at redistributing frame information. */
3869 if (RTX_FRAME_RELATED_P (trial
))
3872 if (any_condjump_p (trial
)
3873 && (note
= find_reg_note (trial
, REG_BR_PROB
, 0)))
3874 split_branch_probability
3875 = profile_probability::from_reg_br_prob_note (XINT (note
, 0));
3877 split_branch_probability
= profile_probability::uninitialized ();
3879 probability
= split_branch_probability
;
3881 seq
= split_insns (pat
, trial
);
3883 split_branch_probability
= profile_probability::uninitialized ();
3888 /* Avoid infinite loop if any insn of the result matches
3889 the original pattern. */
3893 if (INSN_P (insn_last
)
3894 && rtx_equal_p (PATTERN (insn_last
), pat
))
3896 if (!NEXT_INSN (insn_last
))
3898 insn_last
= NEXT_INSN (insn_last
);
3901 /* We will be adding the new sequence to the function. The splitters
3902 may have introduced invalid RTL sharing, so unshare the sequence now. */
3903 unshare_all_rtl_in_chain (seq
);
3905 /* Mark labels and copy flags. */
3906 for (insn
= insn_last
; insn
; insn
= PREV_INSN (insn
))
3911 CROSSING_JUMP_P (insn
) = CROSSING_JUMP_P (trial
);
3912 mark_jump_label (PATTERN (insn
), insn
, 0);
3914 if (probability
.initialized_p ()
3915 && any_condjump_p (insn
)
3916 && !find_reg_note (insn
, REG_BR_PROB
, 0))
3918 /* We can preserve the REG_BR_PROB notes only if exactly
3919 one jump is created, otherwise the machine description
3920 is responsible for this step using
3921 split_branch_probability variable. */
3922 gcc_assert (njumps
== 1);
3923 add_reg_br_prob_note (insn
, probability
);
3928 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3929 in SEQ and copy any additional information across. */
3932 for (insn
= insn_last
; insn
; insn
= PREV_INSN (insn
))
3935 gcc_assert (call_insn
== NULL_RTX
);
3938 /* Add the old CALL_INSN_FUNCTION_USAGE to whatever the
3939 target may have explicitly specified. */
3940 rtx
*p
= &CALL_INSN_FUNCTION_USAGE (insn
);
3943 *p
= CALL_INSN_FUNCTION_USAGE (trial
);
3945 /* If the old call was a sibling call, the new one must
3947 SIBLING_CALL_P (insn
) = SIBLING_CALL_P (trial
);
3951 /* Copy notes, particularly those related to the CFG. */
3952 for (note
= REG_NOTES (trial
); note
; note
= XEXP (note
, 1))
3954 switch (REG_NOTE_KIND (note
))
3957 copy_reg_eh_region_note_backward (note
, insn_last
, NULL
);
3963 case REG_CALL_NOCF_CHECK
:
3964 case REG_CALL_ARG_LOCATION
:
3965 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3968 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3972 case REG_NON_LOCAL_GOTO
:
3973 case REG_LABEL_TARGET
:
3974 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3977 add_reg_note (insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3985 for (insn
= insn_last
; insn
!= NULL_RTX
; insn
= PREV_INSN (insn
))
3987 rtx reg
= XEXP (note
, 0);
3988 if (!FIND_REG_INC_NOTE (insn
, reg
)
3989 && find_auto_inc (PATTERN (insn
), reg
))
3990 add_reg_note (insn
, REG_INC
, reg
);
3995 fixup_args_size_notes (NULL
, insn_last
, get_args_size (note
));
3999 gcc_assert (call_insn
!= NULL_RTX
);
4000 add_reg_note (call_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
4008 /* If there are LABELS inside the split insns increment the
4009 usage count so we don't delete the label. */
4013 while (insn
!= NULL_RTX
)
4015 /* JUMP_P insns have already been "marked" above. */
4016 if (NONJUMP_INSN_P (insn
))
4017 mark_label_nuses (PATTERN (insn
));
4019 insn
= PREV_INSN (insn
);
4023 before
= PREV_INSN (trial
);
4024 after
= NEXT_INSN (trial
);
4026 emit_insn_after_setloc (seq
, trial
, INSN_LOCATION (trial
));
4028 delete_insn (trial
);
4030 /* Recursively call try_split for each new insn created; by the
4031 time control returns here that insn will be fully split, so
4032 set LAST and continue from the insn after the one returned.
4033 We can't use next_active_insn here since AFTER may be a note.
4034 Ignore deleted insns, which can be occur if not optimizing. */
4035 for (tem
= NEXT_INSN (before
); tem
!= after
; tem
= NEXT_INSN (tem
))
4036 if (! tem
->deleted () && INSN_P (tem
))
4037 tem
= try_split (PATTERN (tem
), tem
, 1);
4039 /* Return either the first or the last insn, depending on which was
4042 ? (after
? PREV_INSN (after
) : get_last_insn ())
4043 : NEXT_INSN (before
);
4046 /* Make and return an INSN rtx, initializing all its slots.
4047 Store PATTERN in the pattern slots. */
4050 make_insn_raw (rtx pattern
)
4054 insn
= as_a
<rtx_insn
*> (rtx_alloc (INSN
));
4056 INSN_UID (insn
) = cur_insn_uid
++;
4057 PATTERN (insn
) = pattern
;
4058 INSN_CODE (insn
) = -1;
4059 REG_NOTES (insn
) = NULL
;
4060 INSN_LOCATION (insn
) = curr_insn_location ();
4061 BLOCK_FOR_INSN (insn
) = NULL
;
4063 #ifdef ENABLE_RTL_CHECKING
4066 && (returnjump_p (insn
)
4067 || (GET_CODE (insn
) == SET
4068 && SET_DEST (insn
) == pc_rtx
)))
4070 warning (0, "ICE: emit_insn used where emit_jump_insn needed:\n");
4078 /* Like `make_insn_raw' but make a DEBUG_INSN instead of an insn. */
4081 make_debug_insn_raw (rtx pattern
)
4083 rtx_debug_insn
*insn
;
4085 insn
= as_a
<rtx_debug_insn
*> (rtx_alloc (DEBUG_INSN
));
4086 INSN_UID (insn
) = cur_debug_insn_uid
++;
4087 if (cur_debug_insn_uid
> param_min_nondebug_insn_uid
)
4088 INSN_UID (insn
) = cur_insn_uid
++;
4090 PATTERN (insn
) = pattern
;
4091 INSN_CODE (insn
) = -1;
4092 REG_NOTES (insn
) = NULL
;
4093 INSN_LOCATION (insn
) = curr_insn_location ();
4094 BLOCK_FOR_INSN (insn
) = NULL
;
4099 /* Like `make_insn_raw' but make a JUMP_INSN instead of an insn. */
4102 make_jump_insn_raw (rtx pattern
)
4104 rtx_jump_insn
*insn
;
4106 insn
= as_a
<rtx_jump_insn
*> (rtx_alloc (JUMP_INSN
));
4107 INSN_UID (insn
) = cur_insn_uid
++;
4109 PATTERN (insn
) = pattern
;
4110 INSN_CODE (insn
) = -1;
4111 REG_NOTES (insn
) = NULL
;
4112 JUMP_LABEL (insn
) = NULL
;
4113 INSN_LOCATION (insn
) = curr_insn_location ();
4114 BLOCK_FOR_INSN (insn
) = NULL
;
4119 /* Like `make_insn_raw' but make a CALL_INSN instead of an insn. */
4122 make_call_insn_raw (rtx pattern
)
4124 rtx_call_insn
*insn
;
4126 insn
= as_a
<rtx_call_insn
*> (rtx_alloc (CALL_INSN
));
4127 INSN_UID (insn
) = cur_insn_uid
++;
4129 PATTERN (insn
) = pattern
;
4130 INSN_CODE (insn
) = -1;
4131 REG_NOTES (insn
) = NULL
;
4132 CALL_INSN_FUNCTION_USAGE (insn
) = NULL
;
4133 INSN_LOCATION (insn
) = curr_insn_location ();
4134 BLOCK_FOR_INSN (insn
) = NULL
;
4139 /* Like `make_insn_raw' but make a NOTE instead of an insn. */
4142 make_note_raw (enum insn_note subtype
)
4144 /* Some notes are never created this way at all. These notes are
4145 only created by patching out insns. */
4146 gcc_assert (subtype
!= NOTE_INSN_DELETED_LABEL
4147 && subtype
!= NOTE_INSN_DELETED_DEBUG_LABEL
);
4149 rtx_note
*note
= as_a
<rtx_note
*> (rtx_alloc (NOTE
));
4150 INSN_UID (note
) = cur_insn_uid
++;
4151 NOTE_KIND (note
) = subtype
;
4152 BLOCK_FOR_INSN (note
) = NULL
;
4153 memset (&NOTE_DATA (note
), 0, sizeof (NOTE_DATA (note
)));
4157 /* Add INSN to the end of the doubly-linked list, between PREV and NEXT.
4158 INSN may be any object that can appear in the chain: INSN_P and NOTE_P objects,
4159 but also BARRIERs and JUMP_TABLE_DATAs. PREV and NEXT may be NULL. */
4162 link_insn_into_chain (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4164 SET_PREV_INSN (insn
) = prev
;
4165 SET_NEXT_INSN (insn
) = next
;
4168 SET_NEXT_INSN (prev
) = insn
;
4169 if (NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
4171 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (prev
));
4172 SET_NEXT_INSN (sequence
->insn (sequence
->len () - 1)) = insn
;
4177 SET_PREV_INSN (next
) = insn
;
4178 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
4180 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (next
));
4181 SET_PREV_INSN (sequence
->insn (0)) = insn
;
4185 if (NONJUMP_INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
)
4187 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (insn
));
4188 SET_PREV_INSN (sequence
->insn (0)) = prev
;
4189 SET_NEXT_INSN (sequence
->insn (sequence
->len () - 1)) = next
;
4193 /* Add INSN to the end of the doubly-linked list.
4194 INSN may be an INSN, JUMP_INSN, CALL_INSN, CODE_LABEL, BARRIER or NOTE. */
4197 add_insn (rtx_insn
*insn
)
4199 rtx_insn
*prev
= get_last_insn ();
4200 link_insn_into_chain (insn
, prev
, NULL
);
4201 if (get_insns () == NULL
)
4202 set_first_insn (insn
);
4203 set_last_insn (insn
);
4206 /* Add INSN into the doubly-linked list after insn AFTER. */
4209 add_insn_after_nobb (rtx_insn
*insn
, rtx_insn
*after
)
4211 rtx_insn
*next
= NEXT_INSN (after
);
4213 gcc_assert (!optimize
|| !after
->deleted ());
4215 link_insn_into_chain (insn
, after
, next
);
4219 struct sequence_stack
*seq
;
4221 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4222 if (after
== seq
->last
)
4230 /* Add INSN into the doubly-linked list before insn BEFORE. */
4233 add_insn_before_nobb (rtx_insn
*insn
, rtx_insn
*before
)
4235 rtx_insn
*prev
= PREV_INSN (before
);
4237 gcc_assert (!optimize
|| !before
->deleted ());
4239 link_insn_into_chain (insn
, prev
, before
);
4243 struct sequence_stack
*seq
;
4245 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4246 if (before
== seq
->first
)
4256 /* Like add_insn_after_nobb, but try to set BLOCK_FOR_INSN.
4257 If BB is NULL, an attempt is made to infer the bb from before.
4259 This and the next function should be the only functions called
4260 to insert an insn once delay slots have been filled since only
4261 they know how to update a SEQUENCE. */
4264 add_insn_after (rtx_insn
*insn
, rtx_insn
*after
, basic_block bb
)
4266 add_insn_after_nobb (insn
, after
);
4267 if (!BARRIER_P (after
)
4268 && !BARRIER_P (insn
)
4269 && (bb
= BLOCK_FOR_INSN (after
)))
4271 set_block_for_insn (insn
, bb
);
4273 df_insn_rescan (insn
);
4274 /* Should not happen as first in the BB is always
4275 either NOTE or LABEL. */
4276 if (BB_END (bb
) == after
4277 /* Avoid clobbering of structure when creating new BB. */
4278 && !BARRIER_P (insn
)
4279 && !NOTE_INSN_BASIC_BLOCK_P (insn
))
4284 /* Like add_insn_before_nobb, but try to set BLOCK_FOR_INSN.
4285 If BB is NULL, an attempt is made to infer the bb from before.
4287 This and the previous function should be the only functions called
4288 to insert an insn once delay slots have been filled since only
4289 they know how to update a SEQUENCE. */
4292 add_insn_before (rtx_insn
*insn
, rtx_insn
*before
, basic_block bb
)
4294 add_insn_before_nobb (insn
, before
);
4297 && !BARRIER_P (before
)
4298 && !BARRIER_P (insn
))
4299 bb
= BLOCK_FOR_INSN (before
);
4303 set_block_for_insn (insn
, bb
);
4305 df_insn_rescan (insn
);
4306 /* Should not happen as first in the BB is always either NOTE or
4308 gcc_assert (BB_HEAD (bb
) != insn
4309 /* Avoid clobbering of structure when creating new BB. */
4311 || NOTE_INSN_BASIC_BLOCK_P (insn
));
4315 /* Replace insn with an deleted instruction note. */
4318 set_insn_deleted (rtx_insn
*insn
)
4321 df_insn_delete (insn
);
4322 PUT_CODE (insn
, NOTE
);
4323 NOTE_KIND (insn
) = NOTE_INSN_DELETED
;
4327 /* Unlink INSN from the insn chain.
4329 This function knows how to handle sequences.
4331 This function does not invalidate data flow information associated with
4332 INSN (i.e. does not call df_insn_delete). That makes this function
4333 usable for only disconnecting an insn from the chain, and re-emit it
4336 To later insert INSN elsewhere in the insn chain via add_insn and
4337 similar functions, PREV_INSN and NEXT_INSN must be nullified by
4338 the caller. Nullifying them here breaks many insn chain walks.
4340 To really delete an insn and related DF information, use delete_insn. */
4343 remove_insn (rtx_insn
*insn
)
4345 rtx_insn
*next
= NEXT_INSN (insn
);
4346 rtx_insn
*prev
= PREV_INSN (insn
);
4351 SET_NEXT_INSN (prev
) = next
;
4352 if (NONJUMP_INSN_P (prev
) && GET_CODE (PATTERN (prev
)) == SEQUENCE
)
4354 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (prev
));
4355 SET_NEXT_INSN (sequence
->insn (sequence
->len () - 1)) = next
;
4360 struct sequence_stack
*seq
;
4362 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4363 if (insn
== seq
->first
)
4374 SET_PREV_INSN (next
) = prev
;
4375 if (NONJUMP_INSN_P (next
) && GET_CODE (PATTERN (next
)) == SEQUENCE
)
4377 rtx_sequence
*sequence
= as_a
<rtx_sequence
*> (PATTERN (next
));
4378 SET_PREV_INSN (sequence
->insn (0)) = prev
;
4383 struct sequence_stack
*seq
;
4385 for (seq
= get_current_sequence (); seq
; seq
= seq
->next
)
4386 if (insn
== seq
->last
)
4395 /* Fix up basic block boundaries, if necessary. */
4396 if (!BARRIER_P (insn
)
4397 && (bb
= BLOCK_FOR_INSN (insn
)))
4399 if (BB_HEAD (bb
) == insn
)
4401 /* Never ever delete the basic block note without deleting whole
4403 gcc_assert (!NOTE_P (insn
));
4404 BB_HEAD (bb
) = next
;
4406 if (BB_END (bb
) == insn
)
4411 /* Append CALL_FUSAGE to the CALL_INSN_FUNCTION_USAGE for CALL_INSN. */
4414 add_function_usage_to (rtx call_insn
, rtx call_fusage
)
4416 gcc_assert (call_insn
&& CALL_P (call_insn
));
4418 /* Put the register usage information on the CALL. If there is already
4419 some usage information, put ours at the end. */
4420 if (CALL_INSN_FUNCTION_USAGE (call_insn
))
4424 for (link
= CALL_INSN_FUNCTION_USAGE (call_insn
); XEXP (link
, 1) != 0;
4425 link
= XEXP (link
, 1))
4428 XEXP (link
, 1) = call_fusage
;
4431 CALL_INSN_FUNCTION_USAGE (call_insn
) = call_fusage
;
4434 /* Delete all insns made since FROM.
4435 FROM becomes the new last instruction. */
4438 delete_insns_since (rtx_insn
*from
)
4443 SET_NEXT_INSN (from
) = 0;
4444 set_last_insn (from
);
4447 /* This function is deprecated, please use sequences instead.
4449 Move a consecutive bunch of insns to a different place in the chain.
4450 The insns to be moved are those between FROM and TO.
4451 They are moved to a new position after the insn AFTER.
4452 AFTER must not be FROM or TO or any insn in between.
4454 This function does not know about SEQUENCEs and hence should not be
4455 called after delay-slot filling has been done. */
4458 reorder_insns_nobb (rtx_insn
*from
, rtx_insn
*to
, rtx_insn
*after
)
4462 for (rtx_insn
*x
= from
; x
!= to
; x
= NEXT_INSN (x
))
4463 gcc_assert (after
!= x
);
4464 gcc_assert (after
!= to
);
4467 /* Splice this bunch out of where it is now. */
4468 if (PREV_INSN (from
))
4469 SET_NEXT_INSN (PREV_INSN (from
)) = NEXT_INSN (to
);
4471 SET_PREV_INSN (NEXT_INSN (to
)) = PREV_INSN (from
);
4472 if (get_last_insn () == to
)
4473 set_last_insn (PREV_INSN (from
));
4474 if (get_insns () == from
)
4475 set_first_insn (NEXT_INSN (to
));
4477 /* Make the new neighbors point to it and it to them. */
4478 if (NEXT_INSN (after
))
4479 SET_PREV_INSN (NEXT_INSN (after
)) = to
;
4481 SET_NEXT_INSN (to
) = NEXT_INSN (after
);
4482 SET_PREV_INSN (from
) = after
;
4483 SET_NEXT_INSN (after
) = from
;
4484 if (after
== get_last_insn ())
4488 /* Same as function above, but take care to update BB boundaries. */
4490 reorder_insns (rtx_insn
*from
, rtx_insn
*to
, rtx_insn
*after
)
4492 rtx_insn
*prev
= PREV_INSN (from
);
4493 basic_block bb
, bb2
;
4495 reorder_insns_nobb (from
, to
, after
);
4497 if (!BARRIER_P (after
)
4498 && (bb
= BLOCK_FOR_INSN (after
)))
4501 df_set_bb_dirty (bb
);
4503 if (!BARRIER_P (from
)
4504 && (bb2
= BLOCK_FOR_INSN (from
)))
4506 if (BB_END (bb2
) == to
)
4507 BB_END (bb2
) = prev
;
4508 df_set_bb_dirty (bb2
);
4511 if (BB_END (bb
) == after
)
4514 for (x
= from
; x
!= NEXT_INSN (to
); x
= NEXT_INSN (x
))
4516 df_insn_change_bb (x
, bb
);
4521 /* Emit insn(s) of given code and pattern
4522 at a specified place within the doubly-linked list.
4524 All of the emit_foo global entry points accept an object
4525 X which is either an insn list or a PATTERN of a single
4528 There are thus a few canonical ways to generate code and
4529 emit it at a specific place in the instruction stream. For
4530 example, consider the instruction named SPOT and the fact that
4531 we would like to emit some instructions before SPOT. We might
4535 ... emit the new instructions ...
4536 insns_head = get_insns ();
4539 emit_insn_before (insns_head, SPOT);
4541 It used to be common to generate SEQUENCE rtl instead, but that
4542 is a relic of the past which no longer occurs. The reason is that
4543 SEQUENCE rtl results in much fragmented RTL memory since the SEQUENCE
4544 generated would almost certainly die right after it was created. */
4547 emit_pattern_before_noloc (rtx x
, rtx_insn
*before
, rtx_insn
*last
,
4549 rtx_insn
*(*make_raw
) (rtx
))
4553 gcc_assert (before
);
4558 switch (GET_CODE (x
))
4567 insn
= as_a
<rtx_insn
*> (x
);
4570 rtx_insn
*next
= NEXT_INSN (insn
);
4571 add_insn_before (insn
, before
, bb
);
4577 #ifdef ENABLE_RTL_CHECKING
4584 last
= (*make_raw
) (x
);
4585 add_insn_before (last
, before
, bb
);
4592 /* Make X be output before the instruction BEFORE. */
4595 emit_insn_before_noloc (rtx x
, rtx_insn
*before
, basic_block bb
)
4597 return emit_pattern_before_noloc (x
, before
, before
, bb
, make_insn_raw
);
4600 /* Make an instruction with body X and code JUMP_INSN
4601 and output it before the instruction BEFORE. */
4604 emit_jump_insn_before_noloc (rtx x
, rtx_insn
*before
)
4606 return as_a
<rtx_jump_insn
*> (
4607 emit_pattern_before_noloc (x
, before
, NULL
, NULL
,
4608 make_jump_insn_raw
));
4611 /* Make an instruction with body X and code CALL_INSN
4612 and output it before the instruction BEFORE. */
4615 emit_call_insn_before_noloc (rtx x
, rtx_insn
*before
)
4617 return emit_pattern_before_noloc (x
, before
, NULL
, NULL
,
4618 make_call_insn_raw
);
4621 /* Make an instruction with body X and code DEBUG_INSN
4622 and output it before the instruction BEFORE. */
4625 emit_debug_insn_before_noloc (rtx x
, rtx_insn
*before
)
4627 return emit_pattern_before_noloc (x
, before
, NULL
, NULL
,
4628 make_debug_insn_raw
);
4631 /* Make an insn of code BARRIER
4632 and output it before the insn BEFORE. */
4635 emit_barrier_before (rtx_insn
*before
)
4637 rtx_barrier
*insn
= as_a
<rtx_barrier
*> (rtx_alloc (BARRIER
));
4639 INSN_UID (insn
) = cur_insn_uid
++;
4641 add_insn_before (insn
, before
, NULL
);
4645 /* Emit the label LABEL before the insn BEFORE. */
4648 emit_label_before (rtx_code_label
*label
, rtx_insn
*before
)
4650 gcc_checking_assert (INSN_UID (label
) == 0);
4651 INSN_UID (label
) = cur_insn_uid
++;
4652 add_insn_before (label
, before
, NULL
);
4656 /* Helper for emit_insn_after, handles lists of instructions
4660 emit_insn_after_1 (rtx_insn
*first
, rtx_insn
*after
, basic_block bb
)
4663 rtx_insn
*after_after
;
4664 if (!bb
&& !BARRIER_P (after
))
4665 bb
= BLOCK_FOR_INSN (after
);
4669 df_set_bb_dirty (bb
);
4670 for (last
= first
; NEXT_INSN (last
); last
= NEXT_INSN (last
))
4671 if (!BARRIER_P (last
))
4673 set_block_for_insn (last
, bb
);
4674 df_insn_rescan (last
);
4676 if (!BARRIER_P (last
))
4678 set_block_for_insn (last
, bb
);
4679 df_insn_rescan (last
);
4681 if (BB_END (bb
) == after
)
4685 for (last
= first
; NEXT_INSN (last
); last
= NEXT_INSN (last
))
4688 after_after
= NEXT_INSN (after
);
4690 SET_NEXT_INSN (after
) = first
;
4691 SET_PREV_INSN (first
) = after
;
4692 SET_NEXT_INSN (last
) = after_after
;
4694 SET_PREV_INSN (after_after
) = last
;
4696 if (after
== get_last_insn ())
4697 set_last_insn (last
);
4703 emit_pattern_after_noloc (rtx x
, rtx_insn
*after
, basic_block bb
,
4704 rtx_insn
*(*make_raw
)(rtx
))
4706 rtx_insn
*last
= after
;
4713 switch (GET_CODE (x
))
4722 last
= emit_insn_after_1 (as_a
<rtx_insn
*> (x
), after
, bb
);
4725 #ifdef ENABLE_RTL_CHECKING
4732 last
= (*make_raw
) (x
);
4733 add_insn_after (last
, after
, bb
);
4740 /* Make X be output after the insn AFTER and set the BB of insn. If
4741 BB is NULL, an attempt is made to infer the BB from AFTER. */
4744 emit_insn_after_noloc (rtx x
, rtx_insn
*after
, basic_block bb
)
4746 return emit_pattern_after_noloc (x
, after
, bb
, make_insn_raw
);
4750 /* Make an insn of code JUMP_INSN with body X
4751 and output it after the insn AFTER. */
4754 emit_jump_insn_after_noloc (rtx x
, rtx_insn
*after
)
4756 return as_a
<rtx_jump_insn
*> (
4757 emit_pattern_after_noloc (x
, after
, NULL
, make_jump_insn_raw
));
4760 /* Make an instruction with body X and code CALL_INSN
4761 and output it after the instruction AFTER. */
4764 emit_call_insn_after_noloc (rtx x
, rtx_insn
*after
)
4766 return emit_pattern_after_noloc (x
, after
, NULL
, make_call_insn_raw
);
4769 /* Make an instruction with body X and code CALL_INSN
4770 and output it after the instruction AFTER. */
4773 emit_debug_insn_after_noloc (rtx x
, rtx_insn
*after
)
4775 return emit_pattern_after_noloc (x
, after
, NULL
, make_debug_insn_raw
);
4778 /* Make an insn of code BARRIER
4779 and output it after the insn AFTER. */
4782 emit_barrier_after (rtx_insn
*after
)
4784 rtx_barrier
*insn
= as_a
<rtx_barrier
*> (rtx_alloc (BARRIER
));
4786 INSN_UID (insn
) = cur_insn_uid
++;
4788 add_insn_after (insn
, after
, NULL
);
4792 /* Emit the label LABEL after the insn AFTER. */
4795 emit_label_after (rtx_insn
*label
, rtx_insn
*after
)
4797 gcc_checking_assert (INSN_UID (label
) == 0);
4798 INSN_UID (label
) = cur_insn_uid
++;
4799 add_insn_after (label
, after
, NULL
);
4803 /* Notes require a bit of special handling: Some notes need to have their
4804 BLOCK_FOR_INSN set, others should never have it set, and some should
4805 have it set or clear depending on the context. */
4807 /* Return true iff a note of kind SUBTYPE should be emitted with routines
4808 that never set BLOCK_FOR_INSN on NOTE. BB_BOUNDARY is true if the
4809 caller is asked to emit a note before BB_HEAD, or after BB_END. */
4812 note_outside_basic_block_p (enum insn_note subtype
, bool on_bb_boundary_p
)
4816 /* NOTE_INSN_SWITCH_TEXT_SECTIONS only appears between basic blocks. */
4817 case NOTE_INSN_SWITCH_TEXT_SECTIONS
:
4820 /* Notes for var tracking and EH region markers can appear between or
4821 inside basic blocks. If the caller is emitting on the basic block
4822 boundary, do not set BLOCK_FOR_INSN on the new note. */
4823 case NOTE_INSN_VAR_LOCATION
:
4824 case NOTE_INSN_EH_REGION_BEG
:
4825 case NOTE_INSN_EH_REGION_END
:
4826 return on_bb_boundary_p
;
4828 /* Otherwise, BLOCK_FOR_INSN must be set. */
4834 /* Emit a note of subtype SUBTYPE after the insn AFTER. */
4837 emit_note_after (enum insn_note subtype
, rtx_insn
*after
)
4839 rtx_note
*note
= make_note_raw (subtype
);
4840 basic_block bb
= BARRIER_P (after
) ? NULL
: BLOCK_FOR_INSN (after
);
4841 bool on_bb_boundary_p
= (bb
!= NULL
&& BB_END (bb
) == after
);
4843 if (note_outside_basic_block_p (subtype
, on_bb_boundary_p
))
4844 add_insn_after_nobb (note
, after
);
4846 add_insn_after (note
, after
, bb
);
4850 /* Emit a note of subtype SUBTYPE before the insn BEFORE. */
4853 emit_note_before (enum insn_note subtype
, rtx_insn
*before
)
4855 rtx_note
*note
= make_note_raw (subtype
);
4856 basic_block bb
= BARRIER_P (before
) ? NULL
: BLOCK_FOR_INSN (before
);
4857 bool on_bb_boundary_p
= (bb
!= NULL
&& BB_HEAD (bb
) == before
);
4859 if (note_outside_basic_block_p (subtype
, on_bb_boundary_p
))
4860 add_insn_before_nobb (note
, before
);
4862 add_insn_before (note
, before
, bb
);
4866 /* Insert PATTERN after AFTER, setting its INSN_LOCATION to LOC.
4867 MAKE_RAW indicates how to turn PATTERN into a real insn. */
4870 emit_pattern_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
,
4871 rtx_insn
*(*make_raw
) (rtx
))
4873 rtx_insn
*last
= emit_pattern_after_noloc (pattern
, after
, NULL
, make_raw
);
4875 if (pattern
== NULL_RTX
|| !loc
)
4878 after
= NEXT_INSN (after
);
4881 if (active_insn_p (after
)
4882 && !JUMP_TABLE_DATA_P (after
) /* FIXME */
4883 && !INSN_LOCATION (after
))
4884 INSN_LOCATION (after
) = loc
;
4887 after
= NEXT_INSN (after
);
4892 /* Insert PATTERN after AFTER. MAKE_RAW indicates how to turn PATTERN
4893 into a real insn. SKIP_DEBUG_INSNS indicates whether to insert after
4897 emit_pattern_after (rtx pattern
, rtx_insn
*after
, bool skip_debug_insns
,
4898 rtx_insn
*(*make_raw
) (rtx
))
4900 rtx_insn
*prev
= after
;
4902 if (skip_debug_insns
)
4903 while (DEBUG_INSN_P (prev
))
4904 prev
= PREV_INSN (prev
);
4907 return emit_pattern_after_setloc (pattern
, after
, INSN_LOCATION (prev
),
4910 return emit_pattern_after_noloc (pattern
, after
, NULL
, make_raw
);
4913 /* Like emit_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4915 emit_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4917 return emit_pattern_after_setloc (pattern
, after
, loc
, make_insn_raw
);
4920 /* Like emit_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4922 emit_insn_after (rtx pattern
, rtx_insn
*after
)
4924 return emit_pattern_after (pattern
, after
, true, make_insn_raw
);
4927 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4929 emit_jump_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4931 return as_a
<rtx_jump_insn
*> (
4932 emit_pattern_after_setloc (pattern
, after
, loc
, make_jump_insn_raw
));
4935 /* Like emit_jump_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4937 emit_jump_insn_after (rtx pattern
, rtx_insn
*after
)
4939 return as_a
<rtx_jump_insn
*> (
4940 emit_pattern_after (pattern
, after
, true, make_jump_insn_raw
));
4943 /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4945 emit_call_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4947 return emit_pattern_after_setloc (pattern
, after
, loc
, make_call_insn_raw
);
4950 /* Like emit_call_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4952 emit_call_insn_after (rtx pattern
, rtx_insn
*after
)
4954 return emit_pattern_after (pattern
, after
, true, make_call_insn_raw
);
4957 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to LOC. */
4959 emit_debug_insn_after_setloc (rtx pattern
, rtx_insn
*after
, location_t loc
)
4961 return emit_pattern_after_setloc (pattern
, after
, loc
, make_debug_insn_raw
);
4964 /* Like emit_debug_insn_after_noloc, but set INSN_LOCATION according to AFTER. */
4966 emit_debug_insn_after (rtx pattern
, rtx_insn
*after
)
4968 return emit_pattern_after (pattern
, after
, false, make_debug_insn_raw
);
4971 /* Insert PATTERN before BEFORE, setting its INSN_LOCATION to LOC.
4972 MAKE_RAW indicates how to turn PATTERN into a real insn. INSNP
4973 indicates if PATTERN is meant for an INSN as opposed to a JUMP_INSN,
4977 emit_pattern_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
,
4978 bool insnp
, rtx_insn
*(*make_raw
) (rtx
))
4980 rtx_insn
*first
= PREV_INSN (before
);
4981 rtx_insn
*last
= emit_pattern_before_noloc (pattern
, before
,
4982 insnp
? before
: NULL
,
4985 if (pattern
== NULL_RTX
|| !loc
)
4989 first
= get_insns ();
4991 first
= NEXT_INSN (first
);
4994 if (active_insn_p (first
)
4995 && !JUMP_TABLE_DATA_P (first
) /* FIXME */
4996 && !INSN_LOCATION (first
))
4997 INSN_LOCATION (first
) = loc
;
5000 first
= NEXT_INSN (first
);
5005 /* Insert PATTERN before BEFORE. MAKE_RAW indicates how to turn PATTERN
5006 into a real insn. SKIP_DEBUG_INSNS indicates whether to insert
5007 before any DEBUG_INSNs. INSNP indicates if PATTERN is meant for an
5008 INSN as opposed to a JUMP_INSN, CALL_INSN, etc. */
5011 emit_pattern_before (rtx pattern
, rtx_insn
*before
, bool skip_debug_insns
,
5012 bool insnp
, rtx_insn
*(*make_raw
) (rtx
))
5014 rtx_insn
*next
= before
;
5016 if (skip_debug_insns
)
5017 while (DEBUG_INSN_P (next
))
5018 next
= PREV_INSN (next
);
5021 return emit_pattern_before_setloc (pattern
, before
, INSN_LOCATION (next
),
5024 return emit_pattern_before_noloc (pattern
, before
,
5025 insnp
? before
: NULL
,
5029 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5031 emit_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
5033 return emit_pattern_before_setloc (pattern
, before
, loc
, true,
5037 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */
5039 emit_insn_before (rtx pattern
, rtx_insn
*before
)
5041 return emit_pattern_before (pattern
, before
, true, true, make_insn_raw
);
5044 /* like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5046 emit_jump_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
5048 return as_a
<rtx_jump_insn
*> (
5049 emit_pattern_before_setloc (pattern
, before
, loc
, false,
5050 make_jump_insn_raw
));
5053 /* Like emit_jump_insn_before_noloc, but set INSN_LOCATION according to BEFORE. */
5055 emit_jump_insn_before (rtx pattern
, rtx_insn
*before
)
5057 return as_a
<rtx_jump_insn
*> (
5058 emit_pattern_before (pattern
, before
, true, false,
5059 make_jump_insn_raw
));
5062 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5064 emit_call_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
5066 return emit_pattern_before_setloc (pattern
, before
, loc
, false,
5067 make_call_insn_raw
);
5070 /* Like emit_call_insn_before_noloc,
5071 but set insn_location according to BEFORE. */
5073 emit_call_insn_before (rtx pattern
, rtx_insn
*before
)
5075 return emit_pattern_before (pattern
, before
, true, false,
5076 make_call_insn_raw
);
5079 /* Like emit_insn_before_noloc, but set INSN_LOCATION according to LOC. */
5081 emit_debug_insn_before_setloc (rtx pattern
, rtx_insn
*before
, location_t loc
)
5083 return emit_pattern_before_setloc (pattern
, before
, loc
, false,
5084 make_debug_insn_raw
);
5087 /* Like emit_debug_insn_before_noloc,
5088 but set insn_location according to BEFORE. */
5090 emit_debug_insn_before (rtx pattern
, rtx_insn
*before
)
5092 return emit_pattern_before (pattern
, before
, false, false,
5093 make_debug_insn_raw
);
5096 /* Take X and emit it at the end of the doubly-linked
5099 Returns the last insn emitted. */
5104 rtx_insn
*last
= get_last_insn ();
5110 switch (GET_CODE (x
))
5119 insn
= as_a
<rtx_insn
*> (x
);
5122 rtx_insn
*next
= NEXT_INSN (insn
);
5129 #ifdef ENABLE_RTL_CHECKING
5130 case JUMP_TABLE_DATA
:
5137 last
= make_insn_raw (x
);
5145 /* Make an insn of code DEBUG_INSN with pattern X
5146 and add it to the end of the doubly-linked list. */
5149 emit_debug_insn (rtx x
)
5151 rtx_insn
*last
= get_last_insn ();
5157 switch (GET_CODE (x
))
5166 insn
= as_a
<rtx_insn
*> (x
);
5169 rtx_insn
*next
= NEXT_INSN (insn
);
5176 #ifdef ENABLE_RTL_CHECKING
5177 case JUMP_TABLE_DATA
:
5184 last
= make_debug_insn_raw (x
);
5192 /* Make an insn of code JUMP_INSN with pattern X
5193 and add it to the end of the doubly-linked list. */
5196 emit_jump_insn (rtx x
)
5198 rtx_insn
*last
= NULL
;
5201 switch (GET_CODE (x
))
5210 insn
= as_a
<rtx_insn
*> (x
);
5213 rtx_insn
*next
= NEXT_INSN (insn
);
5220 #ifdef ENABLE_RTL_CHECKING
5221 case JUMP_TABLE_DATA
:
5228 last
= make_jump_insn_raw (x
);
5236 /* Make an insn of code CALL_INSN with pattern X
5237 and add it to the end of the doubly-linked list. */
5240 emit_call_insn (rtx x
)
5244 switch (GET_CODE (x
))
5253 insn
= emit_insn (x
);
5256 #ifdef ENABLE_RTL_CHECKING
5258 case JUMP_TABLE_DATA
:
5264 insn
= make_call_insn_raw (x
);
5272 /* Add the label LABEL to the end of the doubly-linked list. */
5275 emit_label (rtx uncast_label
)
5277 rtx_code_label
*label
= as_a
<rtx_code_label
*> (uncast_label
);
5279 gcc_checking_assert (INSN_UID (label
) == 0);
5280 INSN_UID (label
) = cur_insn_uid
++;
5285 /* Make an insn of code JUMP_TABLE_DATA
5286 and add it to the end of the doubly-linked list. */
5288 rtx_jump_table_data
*
5289 emit_jump_table_data (rtx table
)
5291 rtx_jump_table_data
*jump_table_data
=
5292 as_a
<rtx_jump_table_data
*> (rtx_alloc (JUMP_TABLE_DATA
));
5293 INSN_UID (jump_table_data
) = cur_insn_uid
++;
5294 PATTERN (jump_table_data
) = table
;
5295 BLOCK_FOR_INSN (jump_table_data
) = NULL
;
5296 add_insn (jump_table_data
);
5297 return jump_table_data
;
5300 /* Make an insn of code BARRIER
5301 and add it to the end of the doubly-linked list. */
5306 rtx_barrier
*barrier
= as_a
<rtx_barrier
*> (rtx_alloc (BARRIER
));
5307 INSN_UID (barrier
) = cur_insn_uid
++;
5312 /* Emit a copy of note ORIG. */
5315 emit_note_copy (rtx_note
*orig
)
5317 enum insn_note kind
= (enum insn_note
) NOTE_KIND (orig
);
5318 rtx_note
*note
= make_note_raw (kind
);
5319 NOTE_DATA (note
) = NOTE_DATA (orig
);
5324 /* Make an insn of code NOTE or type NOTE_NO
5325 and add it to the end of the doubly-linked list. */
5328 emit_note (enum insn_note kind
)
5330 rtx_note
*note
= make_note_raw (kind
);
5335 /* Emit a clobber of lvalue X. */
5338 emit_clobber (rtx x
)
5340 /* CONCATs should not appear in the insn stream. */
5341 if (GET_CODE (x
) == CONCAT
)
5343 emit_clobber (XEXP (x
, 0));
5344 return emit_clobber (XEXP (x
, 1));
5346 return emit_insn (gen_rtx_CLOBBER (VOIDmode
, x
));
5349 /* Return a sequence of insns to clobber lvalue X. */
5363 /* Emit a use of rvalue X. */
5368 /* CONCATs should not appear in the insn stream. */
5369 if (GET_CODE (x
) == CONCAT
)
5371 emit_use (XEXP (x
, 0));
5372 return emit_use (XEXP (x
, 1));
5374 return emit_insn (gen_rtx_USE (VOIDmode
, x
));
5377 /* Return a sequence of insns to use rvalue X. */
5391 /* Notes like REG_EQUAL and REG_EQUIV refer to a set in an instruction.
5392 Return the set in INSN that such notes describe, or NULL if the notes
5393 have no meaning for INSN. */
5396 set_for_reg_notes (rtx insn
)
5403 pat
= PATTERN (insn
);
5404 if (GET_CODE (pat
) == PARALLEL
)
5406 /* We do not use single_set because that ignores SETs of unused
5407 registers. REG_EQUAL and REG_EQUIV notes really do require the
5408 PARALLEL to have a single SET. */
5409 if (multiple_sets (insn
))
5411 pat
= XVECEXP (pat
, 0, 0);
5414 if (GET_CODE (pat
) != SET
)
5417 reg
= SET_DEST (pat
);
5419 /* Notes apply to the contents of a STRICT_LOW_PART. */
5420 if (GET_CODE (reg
) == STRICT_LOW_PART
5421 || GET_CODE (reg
) == ZERO_EXTRACT
)
5422 reg
= XEXP (reg
, 0);
5424 /* Check that we have a register. */
5425 if (!(REG_P (reg
) || GET_CODE (reg
) == SUBREG
))
5431 /* Place a note of KIND on insn INSN with DATUM as the datum. If a
5432 note of this type already exists, remove it first. */
5435 set_unique_reg_note (rtx insn
, enum reg_note kind
, rtx datum
)
5437 rtx note
= find_reg_note (insn
, kind
, NULL_RTX
);
5443 /* We need to support the REG_EQUAL on USE trick of find_reloads. */
5444 if (!set_for_reg_notes (insn
) && GET_CODE (PATTERN (insn
)) != USE
)
5447 /* Don't add ASM_OPERAND REG_EQUAL/REG_EQUIV notes.
5448 It serves no useful purpose and breaks eliminate_regs. */
5449 if (GET_CODE (datum
) == ASM_OPERANDS
)
5452 /* Notes with side effects are dangerous. Even if the side-effect
5453 initially mirrors one in PATTERN (INSN), later optimizations
5454 might alter the way that the final register value is calculated
5455 and so move or alter the side-effect in some way. The note would
5456 then no longer be a valid substitution for SET_SRC. */
5457 if (side_effects_p (datum
))
5466 XEXP (note
, 0) = datum
;
5469 add_reg_note (insn
, kind
, datum
);
5470 note
= REG_NOTES (insn
);
5477 df_notes_rescan (as_a
<rtx_insn
*> (insn
));
5486 /* Like set_unique_reg_note, but don't do anything unless INSN sets DST. */
5488 set_dst_reg_note (rtx insn
, enum reg_note kind
, rtx datum
, rtx dst
)
5490 rtx set
= set_for_reg_notes (insn
);
5492 if (set
&& SET_DEST (set
) == dst
)
5493 return set_unique_reg_note (insn
, kind
, datum
);
5497 /* Emit the rtl pattern X as an appropriate kind of insn. Also emit a
5498 following barrier if the instruction needs one and if ALLOW_BARRIER_P
5501 If X is a label, it is simply added into the insn chain. */
5504 emit (rtx x
, bool allow_barrier_p
)
5506 enum rtx_code code
= classify_insn (x
);
5511 return emit_label (x
);
5513 return emit_insn (x
);
5516 rtx_insn
*insn
= emit_jump_insn (x
);
5518 && (any_uncondjump_p (insn
) || GET_CODE (x
) == RETURN
))
5519 return emit_barrier ();
5523 return emit_call_insn (x
);
5525 return emit_debug_insn (x
);
5531 /* Space for free sequence stack entries. */
5532 static GTY ((deletable
)) struct sequence_stack
*free_sequence_stack
;
5534 /* Begin emitting insns to a sequence. If this sequence will contain
5535 something that might cause the compiler to pop arguments to function
5536 calls (because those pops have previously been deferred; see
5537 INHIBIT_DEFER_POP for more details), use do_pending_stack_adjust
5538 before calling this function. That will ensure that the deferred
5539 pops are not accidentally emitted in the middle of this sequence. */
5542 start_sequence (void)
5544 struct sequence_stack
*tem
;
5546 if (free_sequence_stack
!= NULL
)
5548 tem
= free_sequence_stack
;
5549 free_sequence_stack
= tem
->next
;
5552 tem
= ggc_alloc
<sequence_stack
> ();
5554 tem
->next
= get_current_sequence ()->next
;
5555 tem
->first
= get_insns ();
5556 tem
->last
= get_last_insn ();
5557 get_current_sequence ()->next
= tem
;
5563 /* Set up the insn chain starting with FIRST as the current sequence,
5564 saving the previously current one. See the documentation for
5565 start_sequence for more information about how to use this function. */
5568 push_to_sequence (rtx_insn
*first
)
5574 for (last
= first
; last
&& NEXT_INSN (last
); last
= NEXT_INSN (last
))
5577 set_first_insn (first
);
5578 set_last_insn (last
);
5581 /* Like push_to_sequence, but take the last insn as an argument to avoid
5582 looping through the list. */
5585 push_to_sequence2 (rtx_insn
*first
, rtx_insn
*last
)
5589 set_first_insn (first
);
5590 set_last_insn (last
);
5593 /* Set up the outer-level insn chain
5594 as the current sequence, saving the previously current one. */
5597 push_topmost_sequence (void)
5599 struct sequence_stack
*top
;
5603 top
= get_topmost_sequence ();
5604 set_first_insn (top
->first
);
5605 set_last_insn (top
->last
);
5608 /* After emitting to the outer-level insn chain, update the outer-level
5609 insn chain, and restore the previous saved state. */
5612 pop_topmost_sequence (void)
5614 struct sequence_stack
*top
;
5616 top
= get_topmost_sequence ();
5617 top
->first
= get_insns ();
5618 top
->last
= get_last_insn ();
5623 /* After emitting to a sequence, restore previous saved state.
5625 To get the contents of the sequence just made, you must call
5626 `get_insns' *before* calling here.
5628 If the compiler might have deferred popping arguments while
5629 generating this sequence, and this sequence will not be immediately
5630 inserted into the instruction stream, use do_pending_stack_adjust
5631 before calling get_insns. That will ensure that the deferred
5632 pops are inserted into this sequence, and not into some random
5633 location in the instruction stream. See INHIBIT_DEFER_POP for more
5634 information about deferred popping of arguments. */
5639 struct sequence_stack
*tem
= get_current_sequence ()->next
;
5641 set_first_insn (tem
->first
);
5642 set_last_insn (tem
->last
);
5643 get_current_sequence ()->next
= tem
->next
;
5645 memset (tem
, 0, sizeof (*tem
));
5646 tem
->next
= free_sequence_stack
;
5647 free_sequence_stack
= tem
;
5650 /* Return 1 if currently emitting into a sequence. */
5653 in_sequence_p (void)
5655 return get_current_sequence ()->next
!= 0;
5658 /* Put the various virtual registers into REGNO_REG_RTX. */
5661 init_virtual_regs (void)
5663 regno_reg_rtx
[VIRTUAL_INCOMING_ARGS_REGNUM
] = virtual_incoming_args_rtx
;
5664 regno_reg_rtx
[VIRTUAL_STACK_VARS_REGNUM
] = virtual_stack_vars_rtx
;
5665 regno_reg_rtx
[VIRTUAL_STACK_DYNAMIC_REGNUM
] = virtual_stack_dynamic_rtx
;
5666 regno_reg_rtx
[VIRTUAL_OUTGOING_ARGS_REGNUM
] = virtual_outgoing_args_rtx
;
5667 regno_reg_rtx
[VIRTUAL_CFA_REGNUM
] = virtual_cfa_rtx
;
5668 regno_reg_rtx
[VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
]
5669 = virtual_preferred_stack_boundary_rtx
;
5673 /* Used by copy_insn_1 to avoid copying SCRATCHes more than once. */
5674 static rtx copy_insn_scratch_in
[MAX_RECOG_OPERANDS
];
5675 static rtx copy_insn_scratch_out
[MAX_RECOG_OPERANDS
];
5676 static int copy_insn_n_scratches
;
5678 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5679 copied an ASM_OPERANDS.
5680 In that case, it is the original input-operand vector. */
5681 static rtvec orig_asm_operands_vector
;
5683 /* When an insn is being copied by copy_insn_1, this is nonzero if we have
5684 copied an ASM_OPERANDS.
5685 In that case, it is the copied input-operand vector. */
5686 static rtvec copy_asm_operands_vector
;
5688 /* Likewise for the constraints vector. */
5689 static rtvec orig_asm_constraints_vector
;
5690 static rtvec copy_asm_constraints_vector
;
5692 /* Recursively create a new copy of an rtx for copy_insn.
5693 This function differs from copy_rtx in that it handles SCRATCHes and
5694 ASM_OPERANDs properly.
5695 Normally, this function is not used directly; use copy_insn as front end.
5696 However, you could first copy an insn pattern with copy_insn and then use
5697 this function afterwards to properly copy any REG_NOTEs containing
5701 copy_insn_1 (rtx orig
)
5706 const char *format_ptr
;
5711 code
= GET_CODE (orig
);
5726 /* Share clobbers of hard registers (like cc0), but do not share pseudo reg
5727 clobbers or clobbers of hard registers that originated as pseudos.
5728 This is needed to allow safe register renaming. */
5729 if (REG_P (XEXP (orig
, 0))
5730 && HARD_REGISTER_NUM_P (REGNO (XEXP (orig
, 0)))
5731 && HARD_REGISTER_NUM_P (ORIGINAL_REGNO (XEXP (orig
, 0))))
5736 for (i
= 0; i
< copy_insn_n_scratches
; i
++)
5737 if (copy_insn_scratch_in
[i
] == orig
)
5738 return copy_insn_scratch_out
[i
];
5742 if (shared_const_p (orig
))
5746 /* A MEM with a constant address is not sharable. The problem is that
5747 the constant address may need to be reloaded. If the mem is shared,
5748 then reloading one copy of this mem will cause all copies to appear
5749 to have been reloaded. */
5755 /* Copy the various flags, fields, and other information. We assume
5756 that all fields need copying, and then clear the fields that should
5757 not be copied. That is the sensible default behavior, and forces
5758 us to explicitly document why we are *not* copying a flag. */
5759 copy
= shallow_copy_rtx (orig
);
5761 /* We do not copy JUMP, CALL, or FRAME_RELATED for INSNs. */
5764 RTX_FLAG (copy
, jump
) = 0;
5765 RTX_FLAG (copy
, call
) = 0;
5766 RTX_FLAG (copy
, frame_related
) = 0;
5769 format_ptr
= GET_RTX_FORMAT (GET_CODE (copy
));
5771 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (copy
)); i
++)
5772 switch (*format_ptr
++)
5775 if (XEXP (orig
, i
) != NULL
)
5776 XEXP (copy
, i
) = copy_insn_1 (XEXP (orig
, i
));
5781 if (XVEC (orig
, i
) == orig_asm_constraints_vector
)
5782 XVEC (copy
, i
) = copy_asm_constraints_vector
;
5783 else if (XVEC (orig
, i
) == orig_asm_operands_vector
)
5784 XVEC (copy
, i
) = copy_asm_operands_vector
;
5785 else if (XVEC (orig
, i
) != NULL
)
5787 XVEC (copy
, i
) = rtvec_alloc (XVECLEN (orig
, i
));
5788 for (j
= 0; j
< XVECLEN (copy
, i
); j
++)
5789 XVECEXP (copy
, i
, j
) = copy_insn_1 (XVECEXP (orig
, i
, j
));
5801 /* These are left unchanged. */
5808 if (code
== SCRATCH
)
5810 i
= copy_insn_n_scratches
++;
5811 gcc_assert (i
< MAX_RECOG_OPERANDS
);
5812 copy_insn_scratch_in
[i
] = orig
;
5813 copy_insn_scratch_out
[i
] = copy
;
5815 else if (code
== ASM_OPERANDS
)
5817 orig_asm_operands_vector
= ASM_OPERANDS_INPUT_VEC (orig
);
5818 copy_asm_operands_vector
= ASM_OPERANDS_INPUT_VEC (copy
);
5819 orig_asm_constraints_vector
= ASM_OPERANDS_INPUT_CONSTRAINT_VEC (orig
);
5820 copy_asm_constraints_vector
= ASM_OPERANDS_INPUT_CONSTRAINT_VEC (copy
);
5826 /* Create a new copy of an rtx.
5827 This function differs from copy_rtx in that it handles SCRATCHes and
5828 ASM_OPERANDs properly.
5829 INSN doesn't really have to be a full INSN; it could be just the
5832 copy_insn (rtx insn
)
5834 copy_insn_n_scratches
= 0;
5835 orig_asm_operands_vector
= 0;
5836 orig_asm_constraints_vector
= 0;
5837 copy_asm_operands_vector
= 0;
5838 copy_asm_constraints_vector
= 0;
5839 return copy_insn_1 (insn
);
5842 /* Return a copy of INSN that can be used in a SEQUENCE delay slot,
5843 on that assumption that INSN itself remains in its original place. */
5846 copy_delay_slot_insn (rtx_insn
*insn
)
5848 /* Copy INSN with its rtx_code, all its notes, location etc. */
5849 insn
= as_a
<rtx_insn
*> (copy_rtx (insn
));
5850 INSN_UID (insn
) = cur_insn_uid
++;
5854 /* Initialize data structures and variables in this file
5855 before generating rtl for each function. */
5860 set_first_insn (NULL
);
5861 set_last_insn (NULL
);
5862 if (param_min_nondebug_insn_uid
)
5863 cur_insn_uid
= param_min_nondebug_insn_uid
;
5866 cur_debug_insn_uid
= 1;
5867 reg_rtx_no
= LAST_VIRTUAL_REGISTER
+ 1;
5868 first_label_num
= label_num
;
5869 get_current_sequence ()->next
= NULL
;
5871 /* Init the tables that describe all the pseudo regs. */
5873 crtl
->emit
.regno_pointer_align_length
= LAST_VIRTUAL_REGISTER
+ 101;
5875 crtl
->emit
.regno_pointer_align
5876 = XCNEWVEC (unsigned char, crtl
->emit
.regno_pointer_align_length
);
5879 = ggc_cleared_vec_alloc
<rtx
> (crtl
->emit
.regno_pointer_align_length
);
5881 /* Put copies of all the hard registers into regno_reg_rtx. */
5882 memcpy (regno_reg_rtx
,
5883 initial_regno_reg_rtx
,
5884 FIRST_PSEUDO_REGISTER
* sizeof (rtx
));
5886 /* Put copies of all the virtual register rtx into regno_reg_rtx. */
5887 init_virtual_regs ();
5889 /* Indicate that the virtual registers and stack locations are
5891 REG_POINTER (stack_pointer_rtx
) = 1;
5892 REG_POINTER (frame_pointer_rtx
) = 1;
5893 REG_POINTER (hard_frame_pointer_rtx
) = 1;
5894 REG_POINTER (arg_pointer_rtx
) = 1;
5896 REG_POINTER (virtual_incoming_args_rtx
) = 1;
5897 REG_POINTER (virtual_stack_vars_rtx
) = 1;
5898 REG_POINTER (virtual_stack_dynamic_rtx
) = 1;
5899 REG_POINTER (virtual_outgoing_args_rtx
) = 1;
5900 REG_POINTER (virtual_cfa_rtx
) = 1;
5902 #ifdef STACK_BOUNDARY
5903 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM
) = STACK_BOUNDARY
;
5904 REGNO_POINTER_ALIGN (FRAME_POINTER_REGNUM
) = STACK_BOUNDARY
;
5905 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = STACK_BOUNDARY
;
5906 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM
) = STACK_BOUNDARY
;
5908 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM
) = STACK_BOUNDARY
;
5909 REGNO_POINTER_ALIGN (VIRTUAL_STACK_VARS_REGNUM
) = STACK_BOUNDARY
;
5910 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM
) = STACK_BOUNDARY
;
5911 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM
) = STACK_BOUNDARY
;
5913 REGNO_POINTER_ALIGN (VIRTUAL_CFA_REGNUM
) = BITS_PER_WORD
;
5916 #ifdef INIT_EXPANDERS
5921 /* Return the value of element I of CONST_VECTOR X as a wide_int. */
5924 const_vector_int_elt (const_rtx x
, unsigned int i
)
5926 /* First handle elements that are directly encoded. */
5927 machine_mode elt_mode
= GET_MODE_INNER (GET_MODE (x
));
5928 if (i
< (unsigned int) XVECLEN (x
, 0))
5929 return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x
, i
), elt_mode
);
5931 /* Identify the pattern that contains element I and work out the index of
5932 the last encoded element for that pattern. */
5933 unsigned int encoded_nelts
= const_vector_encoded_nelts (x
);
5934 unsigned int npatterns
= CONST_VECTOR_NPATTERNS (x
);
5935 unsigned int count
= i
/ npatterns
;
5936 unsigned int pattern
= i
% npatterns
;
5937 unsigned int final_i
= encoded_nelts
- npatterns
+ pattern
;
5939 /* If there are no steps, the final encoded value is the right one. */
5940 if (!CONST_VECTOR_STEPPED_P (x
))
5941 return rtx_mode_t (CONST_VECTOR_ENCODED_ELT (x
, final_i
), elt_mode
);
5943 /* Otherwise work out the value from the last two encoded elements. */
5944 rtx v1
= CONST_VECTOR_ENCODED_ELT (x
, final_i
- npatterns
);
5945 rtx v2
= CONST_VECTOR_ENCODED_ELT (x
, final_i
);
5946 wide_int diff
= wi::sub (rtx_mode_t (v2
, elt_mode
),
5947 rtx_mode_t (v1
, elt_mode
));
5948 return wi::add (rtx_mode_t (v2
, elt_mode
), (count
- 2) * diff
);
5951 /* Return the value of element I of CONST_VECTOR X. */
5954 const_vector_elt (const_rtx x
, unsigned int i
)
5956 /* First handle elements that are directly encoded. */
5957 if (i
< (unsigned int) XVECLEN (x
, 0))
5958 return CONST_VECTOR_ENCODED_ELT (x
, i
);
5960 /* If there are no steps, the final encoded value is the right one. */
5961 if (!CONST_VECTOR_STEPPED_P (x
))
5963 /* Identify the pattern that contains element I and work out the index of
5964 the last encoded element for that pattern. */
5965 unsigned int encoded_nelts
= const_vector_encoded_nelts (x
);
5966 unsigned int npatterns
= CONST_VECTOR_NPATTERNS (x
);
5967 unsigned int pattern
= i
% npatterns
;
5968 unsigned int final_i
= encoded_nelts
- npatterns
+ pattern
;
5969 return CONST_VECTOR_ENCODED_ELT (x
, final_i
);
5972 /* Otherwise work out the value from the last two encoded elements. */
5973 return immed_wide_int_const (const_vector_int_elt (x
, i
),
5974 GET_MODE_INNER (GET_MODE (x
)));
5977 /* Return true if X is a valid element for a CONST_VECTOR of the given
5981 valid_for_const_vector_p (machine_mode
, rtx x
)
5983 return (CONST_SCALAR_INT_P (x
)
5984 || CONST_DOUBLE_AS_FLOAT_P (x
)
5985 || CONST_FIXED_P (x
));
5988 /* Generate a vector constant of mode MODE in which every element has
5992 gen_const_vec_duplicate (machine_mode mode
, rtx elt
)
5994 rtx_vector_builder
builder (mode
, 1, 1);
5995 builder
.quick_push (elt
);
5996 return builder
.build ();
5999 /* Return a vector rtx of mode MODE in which every element has value X.
6000 The result will be a constant if X is constant. */
6003 gen_vec_duplicate (machine_mode mode
, rtx x
)
6005 if (valid_for_const_vector_p (mode
, x
))
6006 return gen_const_vec_duplicate (mode
, x
);
6007 return gen_rtx_VEC_DUPLICATE (mode
, x
);
6010 /* A subroutine of const_vec_series_p that handles the case in which:
6012 (GET_CODE (X) == CONST_VECTOR
6013 && CONST_VECTOR_NPATTERNS (X) == 1
6014 && !CONST_VECTOR_DUPLICATE_P (X))
6016 is known to hold. */
6019 const_vec_series_p_1 (const_rtx x
, rtx
*base_out
, rtx
*step_out
)
6021 /* Stepped sequences are only defined for integers, to avoid specifying
6022 rounding behavior. */
6023 if (GET_MODE_CLASS (GET_MODE (x
)) != MODE_VECTOR_INT
)
6026 /* A non-duplicated vector with two elements can always be seen as a
6027 series with a nonzero step. Longer vectors must have a stepped
6029 if (maybe_ne (CONST_VECTOR_NUNITS (x
), 2)
6030 && !CONST_VECTOR_STEPPED_P (x
))
6033 /* Calculate the step between the first and second elements. */
6034 scalar_mode inner
= GET_MODE_INNER (GET_MODE (x
));
6035 rtx base
= CONST_VECTOR_ELT (x
, 0);
6036 rtx step
= simplify_binary_operation (MINUS
, inner
,
6037 CONST_VECTOR_ENCODED_ELT (x
, 1), base
);
6038 if (rtx_equal_p (step
, CONST0_RTX (inner
)))
6041 /* If we have a stepped encoding, check that the step between the
6042 second and third elements is the same as STEP. */
6043 if (CONST_VECTOR_STEPPED_P (x
))
6045 rtx diff
= simplify_binary_operation (MINUS
, inner
,
6046 CONST_VECTOR_ENCODED_ELT (x
, 2),
6047 CONST_VECTOR_ENCODED_ELT (x
, 1));
6048 if (!rtx_equal_p (step
, diff
))
6057 /* Generate a vector constant of mode MODE in which element I has
6058 the value BASE + I * STEP. */
6061 gen_const_vec_series (machine_mode mode
, rtx base
, rtx step
)
6063 gcc_assert (valid_for_const_vector_p (mode
, base
)
6064 && valid_for_const_vector_p (mode
, step
));
6066 rtx_vector_builder
builder (mode
, 1, 3);
6067 builder
.quick_push (base
);
6068 for (int i
= 1; i
< 3; ++i
)
6069 builder
.quick_push (simplify_gen_binary (PLUS
, GET_MODE_INNER (mode
),
6070 builder
[i
- 1], step
));
6071 return builder
.build ();
6074 /* Generate a vector of mode MODE in which element I has the value
6075 BASE + I * STEP. The result will be a constant if BASE and STEP
6076 are both constants. */
6079 gen_vec_series (machine_mode mode
, rtx base
, rtx step
)
6081 if (step
== const0_rtx
)
6082 return gen_vec_duplicate (mode
, base
);
6083 if (valid_for_const_vector_p (mode
, base
)
6084 && valid_for_const_vector_p (mode
, step
))
6085 return gen_const_vec_series (mode
, base
, step
);
6086 return gen_rtx_VEC_SERIES (mode
, base
, step
);
6089 /* Generate a new vector constant for mode MODE and constant value
6093 gen_const_vector (machine_mode mode
, int constant
)
6095 machine_mode inner
= GET_MODE_INNER (mode
);
6097 gcc_assert (!DECIMAL_FLOAT_MODE_P (inner
));
6099 rtx el
= const_tiny_rtx
[constant
][(int) inner
];
6102 return gen_const_vec_duplicate (mode
, el
);
6105 /* Generate a vector like gen_rtx_raw_CONST_VEC, but use the zero vector when
6106 all elements are zero, and the one vector when all elements are one. */
6108 gen_rtx_CONST_VECTOR (machine_mode mode
, rtvec v
)
6110 gcc_assert (known_eq (GET_MODE_NUNITS (mode
), GET_NUM_ELEM (v
)));
6112 /* If the values are all the same, check to see if we can use one of the
6113 standard constant vectors. */
6114 if (rtvec_all_equal_p (v
))
6115 return gen_const_vec_duplicate (mode
, RTVEC_ELT (v
, 0));
6117 unsigned int nunits
= GET_NUM_ELEM (v
);
6118 rtx_vector_builder
builder (mode
, nunits
, 1);
6119 for (unsigned int i
= 0; i
< nunits
; ++i
)
6120 builder
.quick_push (RTVEC_ELT (v
, i
));
6121 return builder
.build (v
);
6124 /* Initialise global register information required by all functions. */
6127 init_emit_regs (void)
6133 /* Reset register attributes */
6134 reg_attrs_htab
->empty ();
6136 /* We need reg_raw_mode, so initialize the modes now. */
6137 init_reg_modes_target ();
6139 /* Assign register numbers to the globally defined register rtx. */
6140 stack_pointer_rtx
= gen_raw_REG (Pmode
, STACK_POINTER_REGNUM
);
6141 frame_pointer_rtx
= gen_raw_REG (Pmode
, FRAME_POINTER_REGNUM
);
6142 hard_frame_pointer_rtx
= gen_raw_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
);
6143 arg_pointer_rtx
= gen_raw_REG (Pmode
, ARG_POINTER_REGNUM
);
6144 virtual_incoming_args_rtx
=
6145 gen_raw_REG (Pmode
, VIRTUAL_INCOMING_ARGS_REGNUM
);
6146 virtual_stack_vars_rtx
=
6147 gen_raw_REG (Pmode
, VIRTUAL_STACK_VARS_REGNUM
);
6148 virtual_stack_dynamic_rtx
=
6149 gen_raw_REG (Pmode
, VIRTUAL_STACK_DYNAMIC_REGNUM
);
6150 virtual_outgoing_args_rtx
=
6151 gen_raw_REG (Pmode
, VIRTUAL_OUTGOING_ARGS_REGNUM
);
6152 virtual_cfa_rtx
= gen_raw_REG (Pmode
, VIRTUAL_CFA_REGNUM
);
6153 virtual_preferred_stack_boundary_rtx
=
6154 gen_raw_REG (Pmode
, VIRTUAL_PREFERRED_STACK_BOUNDARY_REGNUM
);
6156 /* Initialize RTL for commonly used hard registers. These are
6157 copied into regno_reg_rtx as we begin to compile each function. */
6158 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
6159 initial_regno_reg_rtx
[i
] = gen_raw_REG (reg_raw_mode
[i
], i
);
6161 #ifdef RETURN_ADDRESS_POINTER_REGNUM
6162 return_address_pointer_rtx
6163 = gen_raw_REG (Pmode
, RETURN_ADDRESS_POINTER_REGNUM
);
6166 pic_offset_table_rtx
= NULL_RTX
;
6167 if ((unsigned) PIC_OFFSET_TABLE_REGNUM
!= INVALID_REGNUM
)
6168 pic_offset_table_rtx
= gen_raw_REG (Pmode
, PIC_OFFSET_TABLE_REGNUM
);
6170 for (i
= 0; i
< (int) MAX_MACHINE_MODE
; i
++)
6172 mode
= (machine_mode
) i
;
6173 attrs
= ggc_cleared_alloc
<mem_attrs
> ();
6174 attrs
->align
= BITS_PER_UNIT
;
6175 attrs
->addrspace
= ADDR_SPACE_GENERIC
;
6176 if (mode
!= BLKmode
&& mode
!= VOIDmode
)
6178 attrs
->size_known_p
= true;
6179 attrs
->size
= GET_MODE_SIZE (mode
);
6180 if (STRICT_ALIGNMENT
)
6181 attrs
->align
= GET_MODE_ALIGNMENT (mode
);
6183 mode_mem_attrs
[i
] = attrs
;
6186 split_branch_probability
= profile_probability::uninitialized ();
6189 /* Initialize global machine_mode variables. */
6192 init_derived_machine_modes (void)
6194 opt_scalar_int_mode mode_iter
, opt_byte_mode
, opt_word_mode
;
6195 FOR_EACH_MODE_IN_CLASS (mode_iter
, MODE_INT
)
6197 scalar_int_mode mode
= mode_iter
.require ();
6199 if (GET_MODE_BITSIZE (mode
) == BITS_PER_UNIT
6200 && !opt_byte_mode
.exists ())
6201 opt_byte_mode
= mode
;
6203 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
6204 && !opt_word_mode
.exists ())
6205 opt_word_mode
= mode
;
6208 byte_mode
= opt_byte_mode
.require ();
6209 word_mode
= opt_word_mode
.require ();
6210 ptr_mode
= as_a
<scalar_int_mode
>
6211 (mode_for_size (POINTER_SIZE
, GET_MODE_CLASS (Pmode
), 0).require ());
6214 /* Create some permanent unique rtl objects shared between all functions. */
6217 init_emit_once (void)
6221 scalar_float_mode double_mode
;
6222 opt_scalar_mode smode_iter
;
6224 /* Initialize the CONST_INT, CONST_WIDE_INT, CONST_DOUBLE,
6225 CONST_FIXED, and memory attribute hash tables. */
6226 const_int_htab
= hash_table
<const_int_hasher
>::create_ggc (37);
6228 #if TARGET_SUPPORTS_WIDE_INT
6229 const_wide_int_htab
= hash_table
<const_wide_int_hasher
>::create_ggc (37);
6231 const_double_htab
= hash_table
<const_double_hasher
>::create_ggc (37);
6233 if (NUM_POLY_INT_COEFFS
> 1)
6234 const_poly_int_htab
= hash_table
<const_poly_int_hasher
>::create_ggc (37);
6236 const_fixed_htab
= hash_table
<const_fixed_hasher
>::create_ggc (37);
6238 reg_attrs_htab
= hash_table
<reg_attr_hasher
>::create_ggc (37);
6240 #ifdef INIT_EXPANDERS
6241 /* This is to initialize {init|mark|free}_machine_status before the first
6242 call to push_function_context_to. This is needed by the Chill front
6243 end which calls push_function_context_to before the first call to
6244 init_function_start. */
6248 /* Create the unique rtx's for certain rtx codes and operand values. */
6250 /* Process stack-limiting command-line options. */
6251 if (opt_fstack_limit_symbol_arg
!= NULL
)
6253 = gen_rtx_SYMBOL_REF (Pmode
, ggc_strdup (opt_fstack_limit_symbol_arg
));
6254 if (opt_fstack_limit_register_no
>= 0)
6255 stack_limit_rtx
= gen_rtx_REG (Pmode
, opt_fstack_limit_register_no
);
6257 /* Don't use gen_rtx_CONST_INT here since gen_rtx_CONST_INT in this case
6258 tries to use these variables. */
6259 for (i
= - MAX_SAVED_CONST_INT
; i
<= MAX_SAVED_CONST_INT
; i
++)
6260 const_int_rtx
[i
+ MAX_SAVED_CONST_INT
] =
6261 gen_rtx_raw_CONST_INT (VOIDmode
, (HOST_WIDE_INT
) i
);
6263 if (STORE_FLAG_VALUE
>= - MAX_SAVED_CONST_INT
6264 && STORE_FLAG_VALUE
<= MAX_SAVED_CONST_INT
)
6265 const_true_rtx
= const_int_rtx
[STORE_FLAG_VALUE
+ MAX_SAVED_CONST_INT
];
6267 const_true_rtx
= gen_rtx_CONST_INT (VOIDmode
, STORE_FLAG_VALUE
);
6269 double_mode
= float_mode_for_size (DOUBLE_TYPE_SIZE
).require ();
6271 real_from_integer (&dconst0
, double_mode
, 0, SIGNED
);
6272 real_from_integer (&dconst1
, double_mode
, 1, SIGNED
);
6273 real_from_integer (&dconst2
, double_mode
, 2, SIGNED
);
6278 dconsthalf
= dconst1
;
6279 SET_REAL_EXP (&dconsthalf
, REAL_EXP (&dconsthalf
) - 1);
6281 for (i
= 0; i
< 3; i
++)
6283 const REAL_VALUE_TYPE
*const r
=
6284 (i
== 0 ? &dconst0
: i
== 1 ? &dconst1
: &dconst2
);
6286 FOR_EACH_MODE_IN_CLASS (mode
, MODE_FLOAT
)
6287 const_tiny_rtx
[i
][(int) mode
] =
6288 const_double_from_real_value (*r
, mode
);
6290 FOR_EACH_MODE_IN_CLASS (mode
, MODE_DECIMAL_FLOAT
)
6291 const_tiny_rtx
[i
][(int) mode
] =
6292 const_double_from_real_value (*r
, mode
);
6294 const_tiny_rtx
[i
][(int) VOIDmode
] = GEN_INT (i
);
6296 FOR_EACH_MODE_IN_CLASS (mode
, MODE_INT
)
6297 const_tiny_rtx
[i
][(int) mode
] = GEN_INT (i
);
6299 for (mode
= MIN_MODE_PARTIAL_INT
;
6300 mode
<= MAX_MODE_PARTIAL_INT
;
6301 mode
= (machine_mode
)((int)(mode
) + 1))
6302 const_tiny_rtx
[i
][(int) mode
] = GEN_INT (i
);
6305 const_tiny_rtx
[3][(int) VOIDmode
] = constm1_rtx
;
6307 FOR_EACH_MODE_IN_CLASS (mode
, MODE_INT
)
6308 const_tiny_rtx
[3][(int) mode
] = constm1_rtx
;
6310 /* For BImode, 1 and -1 are unsigned and signed interpretations
6311 of the same value. */
6312 const_tiny_rtx
[0][(int) BImode
] = const0_rtx
;
6313 const_tiny_rtx
[1][(int) BImode
] = const_true_rtx
;
6314 const_tiny_rtx
[3][(int) BImode
] = const_true_rtx
;
6316 for (mode
= MIN_MODE_PARTIAL_INT
;
6317 mode
<= MAX_MODE_PARTIAL_INT
;
6318 mode
= (machine_mode
)((int)(mode
) + 1))
6319 const_tiny_rtx
[3][(int) mode
] = constm1_rtx
;
6321 FOR_EACH_MODE_IN_CLASS (mode
, MODE_COMPLEX_INT
)
6323 rtx inner
= const_tiny_rtx
[0][(int)GET_MODE_INNER (mode
)];
6324 const_tiny_rtx
[0][(int) mode
] = gen_rtx_CONCAT (mode
, inner
, inner
);
6327 FOR_EACH_MODE_IN_CLASS (mode
, MODE_COMPLEX_FLOAT
)
6329 rtx inner
= const_tiny_rtx
[0][(int)GET_MODE_INNER (mode
)];
6330 const_tiny_rtx
[0][(int) mode
] = gen_rtx_CONCAT (mode
, inner
, inner
);
6333 /* As for BImode, "all 1" and "all -1" are unsigned and signed
6334 interpretations of the same value. */
6335 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_BOOL
)
6337 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6338 const_tiny_rtx
[3][(int) mode
] = gen_const_vector (mode
, 3);
6339 const_tiny_rtx
[1][(int) mode
] = const_tiny_rtx
[3][(int) mode
];
6342 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_INT
)
6344 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6345 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6346 const_tiny_rtx
[3][(int) mode
] = gen_const_vector (mode
, 3);
6349 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_FLOAT
)
6351 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6352 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6355 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_FRACT
)
6357 scalar_mode smode
= smode_iter
.require ();
6358 FCONST0 (smode
).data
.high
= 0;
6359 FCONST0 (smode
).data
.low
= 0;
6360 FCONST0 (smode
).mode
= smode
;
6361 const_tiny_rtx
[0][(int) smode
]
6362 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6365 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_UFRACT
)
6367 scalar_mode smode
= smode_iter
.require ();
6368 FCONST0 (smode
).data
.high
= 0;
6369 FCONST0 (smode
).data
.low
= 0;
6370 FCONST0 (smode
).mode
= smode
;
6371 const_tiny_rtx
[0][(int) smode
]
6372 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6375 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_ACCUM
)
6377 scalar_mode smode
= smode_iter
.require ();
6378 FCONST0 (smode
).data
.high
= 0;
6379 FCONST0 (smode
).data
.low
= 0;
6380 FCONST0 (smode
).mode
= smode
;
6381 const_tiny_rtx
[0][(int) smode
]
6382 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6384 /* We store the value 1. */
6385 FCONST1 (smode
).data
.high
= 0;
6386 FCONST1 (smode
).data
.low
= 0;
6387 FCONST1 (smode
).mode
= smode
;
6388 FCONST1 (smode
).data
6389 = double_int_one
.lshift (GET_MODE_FBIT (smode
),
6390 HOST_BITS_PER_DOUBLE_INT
,
6391 SIGNED_FIXED_POINT_MODE_P (smode
));
6392 const_tiny_rtx
[1][(int) smode
]
6393 = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode
), smode
);
6396 FOR_EACH_MODE_IN_CLASS (smode_iter
, MODE_UACCUM
)
6398 scalar_mode smode
= smode_iter
.require ();
6399 FCONST0 (smode
).data
.high
= 0;
6400 FCONST0 (smode
).data
.low
= 0;
6401 FCONST0 (smode
).mode
= smode
;
6402 const_tiny_rtx
[0][(int) smode
]
6403 = CONST_FIXED_FROM_FIXED_VALUE (FCONST0 (smode
), smode
);
6405 /* We store the value 1. */
6406 FCONST1 (smode
).data
.high
= 0;
6407 FCONST1 (smode
).data
.low
= 0;
6408 FCONST1 (smode
).mode
= smode
;
6409 FCONST1 (smode
).data
6410 = double_int_one
.lshift (GET_MODE_FBIT (smode
),
6411 HOST_BITS_PER_DOUBLE_INT
,
6412 SIGNED_FIXED_POINT_MODE_P (smode
));
6413 const_tiny_rtx
[1][(int) smode
]
6414 = CONST_FIXED_FROM_FIXED_VALUE (FCONST1 (smode
), smode
);
6417 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_FRACT
)
6419 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6422 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_UFRACT
)
6424 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6427 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_ACCUM
)
6429 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6430 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6433 FOR_EACH_MODE_IN_CLASS (mode
, MODE_VECTOR_UACCUM
)
6435 const_tiny_rtx
[0][(int) mode
] = gen_const_vector (mode
, 0);
6436 const_tiny_rtx
[1][(int) mode
] = gen_const_vector (mode
, 1);
6439 for (i
= (int) CCmode
; i
< (int) MAX_MACHINE_MODE
; ++i
)
6440 if (GET_MODE_CLASS ((machine_mode
) i
) == MODE_CC
)
6441 const_tiny_rtx
[0][i
] = const0_rtx
;
6443 pc_rtx
= gen_rtx_fmt_ (PC
, VOIDmode
);
6444 ret_rtx
= gen_rtx_fmt_ (RETURN
, VOIDmode
);
6445 simple_return_rtx
= gen_rtx_fmt_ (SIMPLE_RETURN
, VOIDmode
);
6446 cc0_rtx
= gen_rtx_fmt_ (CC0
, VOIDmode
);
6447 invalid_insn_rtx
= gen_rtx_INSN (VOIDmode
,
6451 /*pattern=*/NULL_RTX
,
6454 /*reg_notes=*/NULL_RTX
);
6457 /* Produce exact duplicate of insn INSN after AFTER.
6458 Care updating of libcall regions if present. */
6461 emit_copy_of_insn_after (rtx_insn
*insn
, rtx_insn
*after
)
6466 switch (GET_CODE (insn
))
6469 new_rtx
= emit_insn_after (copy_insn (PATTERN (insn
)), after
);
6473 new_rtx
= emit_jump_insn_after (copy_insn (PATTERN (insn
)), after
);
6474 CROSSING_JUMP_P (new_rtx
) = CROSSING_JUMP_P (insn
);
6478 new_rtx
= emit_debug_insn_after (copy_insn (PATTERN (insn
)), after
);
6482 new_rtx
= emit_call_insn_after (copy_insn (PATTERN (insn
)), after
);
6483 if (CALL_INSN_FUNCTION_USAGE (insn
))
6484 CALL_INSN_FUNCTION_USAGE (new_rtx
)
6485 = copy_insn (CALL_INSN_FUNCTION_USAGE (insn
));
6486 SIBLING_CALL_P (new_rtx
) = SIBLING_CALL_P (insn
);
6487 RTL_CONST_CALL_P (new_rtx
) = RTL_CONST_CALL_P (insn
);
6488 RTL_PURE_CALL_P (new_rtx
) = RTL_PURE_CALL_P (insn
);
6489 RTL_LOOPING_CONST_OR_PURE_CALL_P (new_rtx
)
6490 = RTL_LOOPING_CONST_OR_PURE_CALL_P (insn
);
6497 /* Update LABEL_NUSES. */
6498 mark_jump_label (PATTERN (new_rtx
), new_rtx
, 0);
6500 INSN_LOCATION (new_rtx
) = INSN_LOCATION (insn
);
6502 /* If the old insn is frame related, then so is the new one. This is
6503 primarily needed for IA-64 unwind info which marks epilogue insns,
6504 which may be duplicated by the basic block reordering code. */
6505 RTX_FRAME_RELATED_P (new_rtx
) = RTX_FRAME_RELATED_P (insn
);
6507 /* Locate the end of existing REG_NOTES in NEW_RTX. */
6508 rtx
*ptail
= ®_NOTES (new_rtx
);
6509 while (*ptail
!= NULL_RTX
)
6510 ptail
= &XEXP (*ptail
, 1);
6512 /* Copy all REG_NOTES except REG_LABEL_OPERAND since mark_jump_label
6513 will make them. REG_LABEL_TARGETs are created there too, but are
6514 supposed to be sticky, so we copy them. */
6515 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
6516 if (REG_NOTE_KIND (link
) != REG_LABEL_OPERAND
)
6518 *ptail
= duplicate_reg_note (link
);
6519 ptail
= &XEXP (*ptail
, 1);
6522 INSN_CODE (new_rtx
) = INSN_CODE (insn
);
6526 static GTY((deletable
)) rtx hard_reg_clobbers
[NUM_MACHINE_MODES
][FIRST_PSEUDO_REGISTER
];
6528 gen_hard_reg_clobber (machine_mode mode
, unsigned int regno
)
6530 if (hard_reg_clobbers
[mode
][regno
])
6531 return hard_reg_clobbers
[mode
][regno
];
6533 return (hard_reg_clobbers
[mode
][regno
] =
6534 gen_rtx_CLOBBER (VOIDmode
, gen_rtx_REG (mode
, regno
)));
6537 location_t prologue_location
;
6538 location_t epilogue_location
;
6540 /* Hold current location information and last location information, so the
6541 datastructures are built lazily only when some instructions in given
6542 place are needed. */
6543 static location_t curr_location
;
6545 /* Allocate insn location datastructure. */
6547 insn_locations_init (void)
6549 prologue_location
= epilogue_location
= 0;
6550 curr_location
= UNKNOWN_LOCATION
;
6553 /* At the end of emit stage, clear current location. */
6555 insn_locations_finalize (void)
6557 epilogue_location
= curr_location
;
6558 curr_location
= UNKNOWN_LOCATION
;
6561 /* Set current location. */
6563 set_curr_insn_location (location_t location
)
6565 curr_location
= location
;
6568 /* Get current location. */
6570 curr_insn_location (void)
6572 return curr_location
;
6575 /* Set the location of the insn chain starting at INSN to LOC. */
6577 set_insn_locations (rtx_insn
*insn
, location_t loc
)
6582 INSN_LOCATION (insn
) = loc
;
6583 insn
= NEXT_INSN (insn
);
6587 /* Return lexical scope block insn belongs to. */
6589 insn_scope (const rtx_insn
*insn
)
6591 return LOCATION_BLOCK (INSN_LOCATION (insn
));
6594 /* Return line number of the statement that produced this insn. */
6596 insn_line (const rtx_insn
*insn
)
6598 return LOCATION_LINE (INSN_LOCATION (insn
));
6601 /* Return source file of the statement that produced this insn. */
6603 insn_file (const rtx_insn
*insn
)
6605 return LOCATION_FILE (INSN_LOCATION (insn
));
6608 /* Return expanded location of the statement that produced this insn. */
6610 insn_location (const rtx_insn
*insn
)
6612 return expand_location (INSN_LOCATION (insn
));
6615 /* Return true if memory model MODEL requires a pre-operation (release-style)
6616 barrier or a post-operation (acquire-style) barrier. While not universal,
6617 this function matches behavior of several targets. */
6620 need_atomic_barrier_p (enum memmodel model
, bool pre
)
6622 switch (model
& MEMMODEL_BASE_MASK
)
6624 case MEMMODEL_RELAXED
:
6625 case MEMMODEL_CONSUME
:
6627 case MEMMODEL_RELEASE
:
6629 case MEMMODEL_ACQUIRE
:
6631 case MEMMODEL_ACQ_REL
:
6632 case MEMMODEL_SEQ_CST
:
6639 /* Return a constant shift amount for shifting a value of mode MODE
6643 gen_int_shift_amount (machine_mode
, poly_int64 value
)
6645 /* Use a 64-bit mode, to avoid any truncation.
6647 ??? Perhaps this should be automatically derived from the .md files
6648 instead, or perhaps have a target hook. */
6649 scalar_int_mode shift_mode
= (BITS_PER_UNIT
== 8
6651 : int_mode_for_size (64, 0).require ());
6652 return gen_int_mode (value
, shift_mode
);
6655 /* Initialize fields of rtl_data related to stack alignment. */
6658 rtl_data::init_stack_alignment ()
6660 stack_alignment_needed
= STACK_BOUNDARY
;
6661 max_used_stack_slot_alignment
= STACK_BOUNDARY
;
6662 stack_alignment_estimated
= 0;
6663 preferred_stack_boundary
= STACK_BOUNDARY
;
6667 #include "gt-emit-rtl.h"