1 /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "hash-table.h"
26 #include "hard-reg-set.h"
38 #include "dominance.h"
40 #include "basic-block.h"
42 #include "addresses.h"
43 #include "insn-config.h"
46 #include "diagnostic-core.h"
51 /* The flags is set up every time when we calculate pseudo register
52 classes through function ira_set_pseudo_classes. */
53 static bool pseudo_classes_defined_p
= false;
55 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
56 static bool allocno_p
;
58 /* Number of elements in array `costs'. */
59 static int cost_elements_num
;
61 /* The `costs' struct records the cost of using hard registers of each
62 class considered for the calculation and of using memory for each
67 /* Costs for register classes start here. We process only some
72 #define max_struct_costs_size \
73 (this_target_ira_int->x_max_struct_costs_size)
75 (this_target_ira_int->x_init_cost)
77 (this_target_ira_int->x_temp_costs)
79 (this_target_ira_int->x_op_costs)
80 #define this_op_costs \
81 (this_target_ira_int->x_this_op_costs)
83 /* Costs of each class for each allocno or pseudo. */
84 static struct costs
*costs
;
86 /* Accumulated costs of each class for each allocno. */
87 static struct costs
*total_allocno_costs
;
89 /* It is the current size of struct costs. */
90 static int struct_costs_size
;
92 /* Return pointer to structure containing costs of allocno or pseudo
93 with given NUM in array ARR. */
94 #define COSTS(arr, num) \
95 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
97 /* Return index in COSTS when processing reg with REGNO. */
98 #define COST_INDEX(regno) (allocno_p \
99 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
102 /* Record register class preferences of each allocno or pseudo. Null
103 value means no preferences. It happens on the 1st iteration of the
105 static enum reg_class
*pref
;
107 /* Allocated buffers for pref. */
108 static enum reg_class
*pref_buffer
;
110 /* Record allocno class of each allocno with the same regno. */
111 static enum reg_class
*regno_aclass
;
113 /* Record cost gains for not allocating a register with an invariant
115 static int *regno_equiv_gains
;
117 /* Execution frequency of the current insn. */
118 static int frequency
;
122 /* Info about reg classes whose costs are calculated for a pseudo. */
125 /* Number of the cost classes in the subsequent array. */
127 /* Container of the cost classes. */
128 enum reg_class classes
[N_REG_CLASSES
];
129 /* Map reg class -> index of the reg class in the previous array.
130 -1 if it is not a cost class. */
131 int index
[N_REG_CLASSES
];
132 /* Map hard regno index of first class in array CLASSES containing
133 the hard regno, -1 otherwise. */
134 int hard_regno_index
[FIRST_PSEUDO_REGISTER
];
137 /* Types of pointers to the structure above. */
138 typedef struct cost_classes
*cost_classes_t
;
139 typedef const struct cost_classes
*const_cost_classes_t
;
141 /* Info about cost classes for each pseudo. */
142 static cost_classes_t
*regno_cost_classes
;
144 /* Helper for cost_classes hashing. */
146 struct cost_classes_hasher
148 typedef cost_classes value_type
;
149 typedef cost_classes compare_type
;
150 static inline hashval_t
hash (const value_type
*);
151 static inline bool equal (const value_type
*, const compare_type
*);
152 static inline void remove (value_type
*);
155 /* Returns hash value for cost classes info HV. */
157 cost_classes_hasher::hash (const value_type
*hv
)
159 return iterative_hash (&hv
->classes
, sizeof (enum reg_class
) * hv
->num
, 0);
162 /* Compares cost classes info HV1 and HV2. */
164 cost_classes_hasher::equal (const value_type
*hv1
, const compare_type
*hv2
)
166 return (hv1
->num
== hv2
->num
167 && memcmp (hv1
->classes
, hv2
->classes
,
168 sizeof (enum reg_class
) * hv1
->num
) == 0);
171 /* Delete cost classes info V from the hash table. */
173 cost_classes_hasher::remove (value_type
*v
)
178 /* Hash table of unique cost classes. */
179 static hash_table
<cost_classes_hasher
> *cost_classes_htab
;
181 /* Map allocno class -> cost classes for pseudo of given allocno
183 static cost_classes_t cost_classes_aclass_cache
[N_REG_CLASSES
];
185 /* Map mode -> cost classes for pseudo of give mode. */
186 static cost_classes_t cost_classes_mode_cache
[MAX_MACHINE_MODE
];
188 /* Initialize info about the cost classes for each pseudo. */
190 initiate_regno_cost_classes (void)
192 int size
= sizeof (cost_classes_t
) * max_reg_num ();
194 regno_cost_classes
= (cost_classes_t
*) ira_allocate (size
);
195 memset (regno_cost_classes
, 0, size
);
196 memset (cost_classes_aclass_cache
, 0,
197 sizeof (cost_classes_t
) * N_REG_CLASSES
);
198 memset (cost_classes_mode_cache
, 0,
199 sizeof (cost_classes_t
) * MAX_MACHINE_MODE
);
200 cost_classes_htab
= new hash_table
<cost_classes_hasher
> (200);
203 /* Create new cost classes from cost classes FROM and set up members
204 index and hard_regno_index. Return the new classes. The function
205 implements some common code of two functions
206 setup_regno_cost_classes_by_aclass and
207 setup_regno_cost_classes_by_mode. */
208 static cost_classes_t
209 setup_cost_classes (cost_classes_t from
)
211 cost_classes_t classes_ptr
;
213 int i
, j
, hard_regno
;
215 classes_ptr
= (cost_classes_t
) ira_allocate (sizeof (struct cost_classes
));
216 classes_ptr
->num
= from
->num
;
217 for (i
= 0; i
< N_REG_CLASSES
; i
++)
218 classes_ptr
->index
[i
] = -1;
219 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
220 classes_ptr
->hard_regno_index
[i
] = -1;
221 for (i
= 0; i
< from
->num
; i
++)
223 cl
= classes_ptr
->classes
[i
] = from
->classes
[i
];
224 classes_ptr
->index
[cl
] = i
;
225 for (j
= ira_class_hard_regs_num
[cl
] - 1; j
>= 0; j
--)
227 hard_regno
= ira_class_hard_regs
[cl
][j
];
228 if (classes_ptr
->hard_regno_index
[hard_regno
] < 0)
229 classes_ptr
->hard_regno_index
[hard_regno
] = i
;
235 /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
236 This function is used when we know an initial approximation of
237 allocno class of the pseudo already, e.g. on the second iteration
238 of class cost calculation or after class cost calculation in
239 register-pressure sensitive insn scheduling or register-pressure
240 sensitive loop-invariant motion. */
242 setup_regno_cost_classes_by_aclass (int regno
, enum reg_class aclass
)
244 static struct cost_classes classes
;
245 cost_classes_t classes_ptr
;
249 HARD_REG_SET temp
, temp2
;
252 if ((classes_ptr
= cost_classes_aclass_cache
[aclass
]) == NULL
)
254 COPY_HARD_REG_SET (temp
, reg_class_contents
[aclass
]);
255 AND_COMPL_HARD_REG_SET (temp
, ira_no_alloc_regs
);
256 /* We exclude classes from consideration which are subsets of
257 ACLASS only if ACLASS is an uniform class. */
258 exclude_p
= ira_uniform_class_p
[aclass
];
260 for (i
= 0; i
< ira_important_classes_num
; i
++)
262 cl
= ira_important_classes
[i
];
265 /* Exclude non-uniform classes which are subsets of
267 COPY_HARD_REG_SET (temp2
, reg_class_contents
[cl
]);
268 AND_COMPL_HARD_REG_SET (temp2
, ira_no_alloc_regs
);
269 if (hard_reg_set_subset_p (temp2
, temp
) && cl
!= aclass
)
272 classes
.classes
[classes
.num
++] = cl
;
274 slot
= cost_classes_htab
->find_slot (&classes
, INSERT
);
277 classes_ptr
= setup_cost_classes (&classes
);
280 classes_ptr
= cost_classes_aclass_cache
[aclass
] = (cost_classes_t
) *slot
;
282 regno_cost_classes
[regno
] = classes_ptr
;
285 /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
286 decrease number of cost classes for the pseudo, if hard registers
287 of some important classes can not hold a value of MODE. So the
288 pseudo can not get hard register of some important classes and cost
289 calculation for such important classes is only wasting CPU
292 setup_regno_cost_classes_by_mode (int regno
, enum machine_mode mode
)
294 static struct cost_classes classes
;
295 cost_classes_t classes_ptr
;
301 if ((classes_ptr
= cost_classes_mode_cache
[mode
]) == NULL
)
304 for (i
= 0; i
< ira_important_classes_num
; i
++)
306 cl
= ira_important_classes
[i
];
307 COPY_HARD_REG_SET (temp
, ira_prohibited_class_mode_regs
[cl
][mode
]);
308 IOR_HARD_REG_SET (temp
, ira_no_alloc_regs
);
309 if (hard_reg_set_subset_p (reg_class_contents
[cl
], temp
))
311 classes
.classes
[classes
.num
++] = cl
;
313 slot
= cost_classes_htab
->find_slot (&classes
, INSERT
);
316 classes_ptr
= setup_cost_classes (&classes
);
320 classes_ptr
= (cost_classes_t
) *slot
;
321 cost_classes_mode_cache
[mode
] = (cost_classes_t
) *slot
;
323 regno_cost_classes
[regno
] = classes_ptr
;
326 /* Finalize info about the cost classes for each pseudo. */
328 finish_regno_cost_classes (void)
330 ira_free (regno_cost_classes
);
331 delete cost_classes_htab
;
332 cost_classes_htab
= NULL
;
337 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
338 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
339 be a pseudo register. */
341 copy_cost (rtx x
, enum machine_mode mode
, reg_class_t rclass
, bool to_p
,
342 secondary_reload_info
*prev_sri
)
344 secondary_reload_info sri
;
345 reg_class_t secondary_class
= NO_REGS
;
347 /* If X is a SCRATCH, there is actually nothing to move since we are
348 assuming optimal allocation. */
349 if (GET_CODE (x
) == SCRATCH
)
352 /* Get the class we will actually use for a reload. */
353 rclass
= targetm
.preferred_reload_class (x
, rclass
);
355 /* If we need a secondary reload for an intermediate, the cost is
356 that to load the input into the intermediate register, then to
358 sri
.prev_sri
= prev_sri
;
360 secondary_class
= targetm
.secondary_reload (to_p
, x
, rclass
, mode
, &sri
);
362 if (secondary_class
!= NO_REGS
)
364 ira_init_register_move_cost_if_necessary (mode
);
365 return (ira_register_move_cost
[mode
][(int) secondary_class
][(int) rclass
]
367 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
370 /* For memory, use the memory move cost, for (hard) registers, use
371 the cost to move between the register classes, and use 2 for
372 everything else (constants). */
373 if (MEM_P (x
) || rclass
== NO_REGS
)
374 return sri
.extra_cost
375 + ira_memory_move_cost
[mode
][(int) rclass
][to_p
!= 0];
378 reg_class_t x_class
= REGNO_REG_CLASS (REGNO (x
));
380 ira_init_register_move_cost_if_necessary (mode
);
381 return (sri
.extra_cost
382 + ira_register_move_cost
[mode
][(int) x_class
][(int) rclass
]);
385 /* If this is a constant, we may eventually want to call rtx_cost
387 return sri
.extra_cost
+ COSTS_N_INSNS (1);
392 /* Record the cost of using memory or hard registers of various
393 classes for the operands in INSN.
395 N_ALTS is the number of alternatives.
396 N_OPS is the number of operands.
397 OPS is an array of the operands.
398 MODES are the modes of the operands, in case any are VOIDmode.
399 CONSTRAINTS are the constraints to use for the operands. This array
400 is modified by this procedure.
402 This procedure works alternative by alternative. For each
403 alternative we assume that we will be able to allocate all allocnos
404 to their ideal register class and calculate the cost of using that
405 alternative. Then we compute, for each operand that is a
406 pseudo-register, the cost of having the allocno allocated to each
407 register class and using it in that alternative. To this cost is
408 added the cost of the alternative.
410 The cost of each class for this insn is its lowest cost among all
413 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
414 enum machine_mode
*modes
, const char **constraints
,
415 rtx_insn
*insn
, enum reg_class
*pref
)
419 int insn_allows_mem
[MAX_RECOG_OPERANDS
];
420 move_table
*move_in_cost
, *move_out_cost
;
421 short (*mem_cost
)[2];
423 for (i
= 0; i
< n_ops
; i
++)
424 insn_allows_mem
[i
] = 0;
426 /* Process each alternative, each time minimizing an operand's cost
427 with the cost for each operand in that alternative. */
428 alternative_mask preferred
= get_preferred_alternatives (insn
);
429 for (alt
= 0; alt
< n_alts
; alt
++)
431 enum reg_class classes
[MAX_RECOG_OPERANDS
];
432 int allows_mem
[MAX_RECOG_OPERANDS
];
433 enum reg_class rclass
;
435 int alt_cost
= 0, op_cost_add
;
437 if (!TEST_BIT (preferred
, alt
))
439 for (i
= 0; i
< recog_data
.n_operands
; i
++)
440 constraints
[i
] = skip_alternative (constraints
[i
]);
445 for (i
= 0; i
< n_ops
; i
++)
448 const char *p
= constraints
[i
];
450 enum machine_mode mode
= modes
[i
];
454 /* Initially show we know nothing about the register class. */
455 classes
[i
] = NO_REGS
;
458 /* If this operand has no constraints at all, we can
459 conclude nothing about it since anything is valid. */
462 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
463 memset (this_op_costs
[i
], 0, struct_costs_size
);
467 /* If this alternative is only relevant when this operand
468 matches a previous operand, we do different things
469 depending on whether this operand is a allocno-reg or not.
470 We must process any modifiers for the operand before we
471 can make this test. */
472 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
475 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
477 /* Copy class and whether memory is allowed from the
478 matching alternative. Then perform any needed cost
479 computations and/or adjustments. */
481 classes
[i
] = classes
[j
];
482 allows_mem
[i
] = allows_mem
[j
];
484 insn_allows_mem
[i
] = 1;
486 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
488 /* If this matches the other operand, we have no
489 added cost and we win. */
490 if (rtx_equal_p (ops
[j
], op
))
492 /* If we can put the other operand into a register,
493 add to the cost of this alternative the cost to
494 copy this operand to the register used for the
496 else if (classes
[j
] != NO_REGS
)
498 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
502 else if (! REG_P (ops
[j
])
503 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
505 /* This op is an allocno but the one it matches is
508 /* If we can't put the other operand into a
509 register, this alternative can't be used. */
511 if (classes
[j
] == NO_REGS
)
513 /* Otherwise, add to the cost of this alternative
514 the cost to copy the other operand to the hard
515 register used for this operand. */
517 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
521 /* The costs of this operand are not the same as the
522 other operand since move costs are not symmetric.
523 Moreover, if we cannot tie them, this alternative
524 needs to do a copy, which is one insn. */
525 struct costs
*pp
= this_op_costs
[i
];
526 int *pp_costs
= pp
->cost
;
527 cost_classes_t cost_classes_ptr
528 = regno_cost_classes
[REGNO (op
)];
529 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
530 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
531 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
532 enum reg_class op_class
= classes
[i
];
534 ira_init_register_move_cost_if_necessary (mode
);
538 if (op_class
== NO_REGS
)
540 mem_cost
= ira_memory_move_cost
[mode
];
541 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
543 rclass
= cost_classes
[k
];
544 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
549 move_out_cost
= ira_may_move_out_cost
[mode
];
550 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
552 rclass
= cost_classes
[k
];
554 = move_out_cost
[op_class
][rclass
] * frequency
;
561 if (op_class
== NO_REGS
)
563 mem_cost
= ira_memory_move_cost
[mode
];
564 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
566 rclass
= cost_classes
[k
];
567 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
572 move_in_cost
= ira_may_move_in_cost
[mode
];
573 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
575 rclass
= cost_classes
[k
];
577 = move_in_cost
[rclass
][op_class
] * frequency
;
583 if (op_class
== NO_REGS
)
585 mem_cost
= ira_memory_move_cost
[mode
];
586 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
588 rclass
= cost_classes
[k
];
589 pp_costs
[k
] = ((mem_cost
[rclass
][0]
590 + mem_cost
[rclass
][1])
596 move_in_cost
= ira_may_move_in_cost
[mode
];
597 move_out_cost
= ira_may_move_out_cost
[mode
];
598 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
600 rclass
= cost_classes
[k
];
601 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
602 + move_out_cost
[op_class
][rclass
])
608 /* If the alternative actually allows memory, make
609 things a bit cheaper since we won't need an extra
612 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
613 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
614 - allows_mem
[i
]) * frequency
;
616 /* If we have assigned a class to this allocno in
617 our first pass, add a cost to this alternative
618 corresponding to what we would add if this
619 allocno were not in the appropriate class. */
622 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
624 if (pref_class
== NO_REGS
)
627 ? ira_memory_move_cost
[mode
][op_class
][0] : 0)
629 ? ira_memory_move_cost
[mode
][op_class
][1]
631 else if (ira_reg_class_intersect
632 [pref_class
][op_class
] == NO_REGS
)
634 += ira_register_move_cost
[mode
][pref_class
][op_class
];
636 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
637 && ! find_reg_note (insn
, REG_DEAD
, op
))
640 /* This is in place of ordinary cost computation for
641 this operand, so skip to the end of the
642 alternative (should be just one character). */
643 while (*p
&& *p
++ != ',')
651 /* Scan all the constraint letters. See if the operand
652 matches any of the constraints. Collect the valid
653 register classes and see if this operand accepts
660 /* Ignore the next letter for this pass. */
671 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
673 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
674 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][GENERAL_REGS
];
678 enum constraint_num cn
= lookup_constraint (p
);
680 switch (get_constraint_type (cn
))
683 cl
= reg_class_for_constraint (cn
);
685 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][cl
];
690 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
695 /* Every MEM can be reloaded to fit. */
696 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
702 /* Every address can be reloaded to fit. */
704 if (address_operand (op
, GET_MODE (op
))
705 || constraint_satisfied_p (op
, cn
))
707 /* We know this operand is an address, so we
708 want it to be allocated to a hard register
709 that can be the base of an address,
710 i.e. BASE_REG_CLASS. */
712 = ira_reg_class_subunion
[classes
[i
]]
713 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
718 if (constraint_satisfied_p (op
, cn
))
724 p
+= CONSTRAINT_LEN (c
, p
);
731 /* How we account for this operand now depends on whether it
732 is a pseudo register or not. If it is, we first check if
733 any register classes are valid. If not, we ignore this
734 alternative, since we want to assume that all allocnos get
735 allocated for register preferencing. If some register
736 class is valid, compute the costs of moving the allocno
738 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
740 if (classes
[i
] == NO_REGS
&& ! allows_mem
[i
])
742 /* We must always fail if the operand is a REG, but
743 we did not find a suitable class and memory is
746 Otherwise we may perform an uninitialized read
747 from this_op_costs after the `continue' statement
753 unsigned int regno
= REGNO (op
);
754 struct costs
*pp
= this_op_costs
[i
];
755 int *pp_costs
= pp
->cost
;
756 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
757 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
758 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
759 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
760 enum reg_class op_class
= classes
[i
];
762 ira_init_register_move_cost_if_necessary (mode
);
766 if (op_class
== NO_REGS
)
768 mem_cost
= ira_memory_move_cost
[mode
];
769 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
771 rclass
= cost_classes
[k
];
772 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
777 move_out_cost
= ira_may_move_out_cost
[mode
];
778 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
780 rclass
= cost_classes
[k
];
782 = move_out_cost
[op_class
][rclass
] * frequency
;
789 if (op_class
== NO_REGS
)
791 mem_cost
= ira_memory_move_cost
[mode
];
792 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
794 rclass
= cost_classes
[k
];
795 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
800 move_in_cost
= ira_may_move_in_cost
[mode
];
801 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
803 rclass
= cost_classes
[k
];
805 = move_in_cost
[rclass
][op_class
] * frequency
;
811 if (op_class
== NO_REGS
)
813 mem_cost
= ira_memory_move_cost
[mode
];
814 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
816 rclass
= cost_classes
[k
];
817 pp_costs
[k
] = ((mem_cost
[rclass
][0]
818 + mem_cost
[rclass
][1])
824 move_in_cost
= ira_may_move_in_cost
[mode
];
825 move_out_cost
= ira_may_move_out_cost
[mode
];
826 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
828 rclass
= cost_classes
[k
];
829 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
830 + move_out_cost
[op_class
][rclass
])
836 if (op_class
== NO_REGS
)
837 /* Although we don't need insn to reload from
838 memory, still accessing memory is usually more
839 expensive than a register. */
840 pp
->mem_cost
= frequency
;
842 /* If the alternative actually allows memory, make
843 things a bit cheaper since we won't need an
844 extra insn to load it. */
846 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
847 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
848 - allows_mem
[i
]) * frequency
;
849 /* If we have assigned a class to this allocno in
850 our first pass, add a cost to this alternative
851 corresponding to what we would add if this
852 allocno were not in the appropriate class. */
855 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
857 if (pref_class
== NO_REGS
)
859 if (op_class
!= NO_REGS
)
862 ? ira_memory_move_cost
[mode
][op_class
][0]
865 ? ira_memory_move_cost
[mode
][op_class
][1]
868 else if (op_class
== NO_REGS
)
871 ? ira_memory_move_cost
[mode
][pref_class
][1]
874 ? ira_memory_move_cost
[mode
][pref_class
][0]
876 else if (ira_reg_class_intersect
[pref_class
][op_class
]
878 alt_cost
+= (ira_register_move_cost
879 [mode
][pref_class
][op_class
]);
884 /* Otherwise, if this alternative wins, either because we
885 have already determined that or if we have a hard
886 register of the proper class, there is no cost for this
888 else if (win
|| (REG_P (op
)
889 && reg_fits_class_p (op
, classes
[i
],
893 /* If registers are valid, the cost of this alternative
894 includes copying the object to and/or from a
896 else if (classes
[i
] != NO_REGS
)
898 if (recog_data
.operand_type
[i
] != OP_OUT
)
899 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
901 if (recog_data
.operand_type
[i
] != OP_IN
)
902 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
904 /* The only other way this alternative can be used is if
905 this is a constant that could be placed into memory. */
906 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
907 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
915 op_cost_add
= alt_cost
* frequency
;
916 /* Finally, update the costs with the information we've
917 calculated about this alternative. */
918 for (i
= 0; i
< n_ops
; i
++)
919 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
921 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
922 int *pp_costs
= pp
->cost
, *qq_costs
= qq
->cost
;
923 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
924 cost_classes_t cost_classes_ptr
925 = regno_cost_classes
[REGNO (ops
[i
])];
927 pp
->mem_cost
= MIN (pp
->mem_cost
,
928 (qq
->mem_cost
+ op_cost_add
) * scale
);
930 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
932 = MIN (pp_costs
[k
], (qq_costs
[k
] + op_cost_add
) * scale
);
937 for (i
= 0; i
< n_ops
; i
++)
942 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
944 a
= ira_curr_regno_allocno_map
[REGNO (op
)];
945 if (! ALLOCNO_BAD_SPILL_P (a
) && insn_allows_mem
[i
] == 0)
946 ALLOCNO_BAD_SPILL_P (a
) = true;
953 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
955 ok_for_index_p_nonstrict (rtx reg
)
957 unsigned regno
= REGNO (reg
);
959 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
962 /* A version of regno_ok_for_base_p for use here, when all
963 pseudo-registers should count as OK. Arguments as for
964 regno_ok_for_base_p. */
966 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
967 enum rtx_code outer_code
, enum rtx_code index_code
)
969 unsigned regno
= REGNO (reg
);
971 if (regno
>= FIRST_PSEUDO_REGISTER
)
973 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
976 /* Record the pseudo registers we must reload into hard registers in a
977 subexpression of a memory address, X.
979 If CONTEXT is 0, we are looking at the base part of an address,
980 otherwise we are looking at the index part.
982 MODE and AS are the mode and address space of the memory reference;
983 OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
984 These four arguments are passed down to base_reg_class.
986 SCALE is twice the amount to multiply the cost by (it is twice so
987 we can represent half-cost adjustments). */
989 record_address_regs (enum machine_mode mode
, addr_space_t as
, rtx x
,
990 int context
, enum rtx_code outer_code
,
991 enum rtx_code index_code
, int scale
)
993 enum rtx_code code
= GET_CODE (x
);
994 enum reg_class rclass
;
997 rclass
= INDEX_REG_CLASS
;
999 rclass
= base_reg_class (mode
, as
, outer_code
, index_code
);
1012 /* When we have an address that is a sum, we must determine
1013 whether registers are "base" or "index" regs. If there is a
1014 sum of two registers, we must choose one to be the "base".
1015 Luckily, we can use the REG_POINTER to make a good choice
1016 most of the time. We only need to do this on machines that
1017 can have two registers in an address and where the base and
1018 index register classes are different.
1020 ??? This code used to set REGNO_POINTER_FLAG in some cases,
1021 but that seems bogus since it should only be set when we are
1022 sure the register is being used as a pointer. */
1024 rtx arg0
= XEXP (x
, 0);
1025 rtx arg1
= XEXP (x
, 1);
1026 enum rtx_code code0
= GET_CODE (arg0
);
1027 enum rtx_code code1
= GET_CODE (arg1
);
1029 /* Look inside subregs. */
1030 if (code0
== SUBREG
)
1031 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1032 if (code1
== SUBREG
)
1033 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1035 /* If this machine only allows one register per address, it
1036 must be in the first operand. */
1037 if (MAX_REGS_PER_ADDRESS
== 1)
1038 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1040 /* If index and base registers are the same on this machine,
1041 just record registers in any non-constant operands. We
1042 assume here, as well as in the tests below, that all
1043 addresses are in canonical form. */
1044 else if (INDEX_REG_CLASS
1045 == base_reg_class (VOIDmode
, as
, PLUS
, SCRATCH
))
1047 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1048 if (! CONSTANT_P (arg1
))
1049 record_address_regs (mode
, as
, arg1
, context
, PLUS
, code0
, scale
);
1052 /* If the second operand is a constant integer, it doesn't
1053 change what class the first operand must be. */
1054 else if (CONST_SCALAR_INT_P (arg1
))
1055 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1056 /* If the second operand is a symbolic constant, the first
1057 operand must be an index register. */
1058 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1059 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1060 /* If both operands are registers but one is already a hard
1061 register of index or reg-base class, give the other the
1062 class that the hard register is not. */
1063 else if (code0
== REG
&& code1
== REG
1064 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1065 && (ok_for_base_p_nonstrict (arg0
, mode
, as
, PLUS
, REG
)
1066 || ok_for_index_p_nonstrict (arg0
)))
1067 record_address_regs (mode
, as
, arg1
,
1068 ok_for_base_p_nonstrict (arg0
, mode
, as
,
1071 else if (code0
== REG
&& code1
== REG
1072 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1073 && (ok_for_base_p_nonstrict (arg1
, mode
, as
, PLUS
, REG
)
1074 || ok_for_index_p_nonstrict (arg1
)))
1075 record_address_regs (mode
, as
, arg0
,
1076 ok_for_base_p_nonstrict (arg1
, mode
, as
,
1079 /* If one operand is known to be a pointer, it must be the
1080 base with the other operand the index. Likewise if the
1081 other operand is a MULT. */
1082 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
1084 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1085 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
);
1087 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
1089 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1090 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
);
1092 /* Otherwise, count equal chances that each might be a base or
1093 index register. This case should be rare. */
1096 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
/ 2);
1097 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
/ 2);
1098 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
/ 2);
1099 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
/ 2);
1104 /* Double the importance of an allocno that is incremented or
1105 decremented, since it would take two extra insns if it ends
1106 up in the wrong place. */
1109 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
,
1110 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
1111 if (REG_P (XEXP (XEXP (x
, 1), 1)))
1112 record_address_regs (mode
, as
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
1120 /* Double the importance of an allocno that is incremented or
1121 decremented, since it would take two extra insns if it ends
1122 up in the wrong place. */
1123 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
1131 int k
, regno
, add_cost
;
1132 cost_classes_t cost_classes_ptr
;
1133 enum reg_class
*cost_classes
;
1134 move_table
*move_in_cost
;
1136 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1141 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map
[regno
]) = true;
1142 pp
= COSTS (costs
, COST_INDEX (regno
));
1143 add_cost
= (ira_memory_move_cost
[Pmode
][rclass
][1] * scale
) / 2;
1144 if (INT_MAX
- add_cost
< pp
->mem_cost
)
1145 pp
->mem_cost
= INT_MAX
;
1147 pp
->mem_cost
+= add_cost
;
1148 cost_classes_ptr
= regno_cost_classes
[regno
];
1149 cost_classes
= cost_classes_ptr
->classes
;
1150 pp_costs
= pp
->cost
;
1151 ira_init_register_move_cost_if_necessary (Pmode
);
1152 move_in_cost
= ira_may_move_in_cost
[Pmode
];
1153 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1155 i
= cost_classes
[k
];
1156 add_cost
= (move_in_cost
[i
][rclass
] * scale
) / 2;
1157 if (INT_MAX
- add_cost
< pp_costs
[k
])
1158 pp_costs
[k
] = INT_MAX
;
1160 pp_costs
[k
] += add_cost
;
1167 const char *fmt
= GET_RTX_FORMAT (code
);
1169 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1171 record_address_regs (mode
, as
, XEXP (x
, i
), context
, code
, SCRATCH
,
1179 /* Calculate the costs of insn operands. */
1181 record_operand_costs (rtx_insn
*insn
, enum reg_class
*pref
)
1183 const char *constraints
[MAX_RECOG_OPERANDS
];
1184 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
1185 rtx ops
[MAX_RECOG_OPERANDS
];
1189 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1191 constraints
[i
] = recog_data
.constraints
[i
];
1192 modes
[i
] = recog_data
.operand_mode
[i
];
1195 /* If we get here, we are set up to record the costs of all the
1196 operands for this insn. Start by initializing the costs. Then
1197 handle any address registers. Finally record the desired classes
1198 for any allocnos, doing it twice if some pair of operands are
1200 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1202 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
1204 ops
[i
] = recog_data
.operand
[i
];
1205 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
1206 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
1208 if (MEM_P (recog_data
.operand
[i
]))
1209 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
1210 MEM_ADDR_SPACE (recog_data
.operand
[i
]),
1211 XEXP (recog_data
.operand
[i
], 0),
1212 0, MEM
, SCRATCH
, frequency
* 2);
1213 else if (constraints
[i
][0] == 'p'
1214 || (insn_extra_address_constraint
1215 (lookup_constraint (constraints
[i
]))))
1216 record_address_regs (VOIDmode
, ADDR_SPACE_GENERIC
,
1217 recog_data
.operand
[i
], 0, ADDRESS
, SCRATCH
,
1221 /* Check for commutative in a separate loop so everything will have
1222 been initialized. We must do this even if one operand is a
1223 constant--see addsi3 in m68k.md. */
1224 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1225 if (constraints
[i
][0] == '%')
1227 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1230 /* Handle commutative operands by swapping the constraints.
1231 We assume the modes are the same. */
1232 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1233 xconstraints
[j
] = constraints
[j
];
1235 xconstraints
[i
] = constraints
[i
+1];
1236 xconstraints
[i
+1] = constraints
[i
];
1237 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1238 recog_data
.operand
, modes
,
1239 xconstraints
, insn
, pref
);
1241 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1242 recog_data
.operand
, modes
,
1243 constraints
, insn
, pref
);
1245 /* If this insn is a single set copying operand 1 to operand 0 and
1246 one operand is an allocno with the other a hard reg or an allocno
1247 that prefers a hard register that is in its own register class
1248 then we may want to adjust the cost of that register class to -1.
1250 Avoid the adjustment if the source does not die to avoid
1251 stressing of register allocator by preferencing two colliding
1252 registers into single class.
1254 Also avoid the adjustment if a copy between hard registers of the
1255 class is expensive (ten times the cost of a default copy is
1256 considered arbitrarily expensive). This avoids losing when the
1257 preferred class is very expensive as the source of a copy
1259 if ((set
= single_set (insn
)) != NULL_RTX
1260 /* In rare cases the single set insn might have less 2 operands
1261 as the source can be a fixed special reg. */
1262 && recog_data
.n_operands
> 1
1263 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
))
1265 int regno
, other_regno
;
1266 rtx dest
= SET_DEST (set
);
1267 rtx src
= SET_SRC (set
);
1269 dest
= SET_DEST (set
);
1270 src
= SET_SRC (set
);
1271 if (GET_CODE (dest
) == SUBREG
1272 && (GET_MODE_SIZE (GET_MODE (dest
))
1273 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))))
1274 dest
= SUBREG_REG (dest
);
1275 if (GET_CODE (src
) == SUBREG
1276 && (GET_MODE_SIZE (GET_MODE (src
))
1277 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
1278 src
= SUBREG_REG (src
);
1279 if (REG_P (src
) && REG_P (dest
)
1280 && find_regno_note (insn
, REG_DEAD
, REGNO (src
))
1281 && (((regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
1282 && (other_regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
)
1283 || ((regno
= REGNO (dest
)) >= FIRST_PSEUDO_REGISTER
1284 && (other_regno
= REGNO (src
)) < FIRST_PSEUDO_REGISTER
)))
1286 enum machine_mode mode
= GET_MODE (src
);
1287 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1288 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1292 i
= regno
== (int) REGNO (src
) ? 1 : 0;
1293 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1295 rclass
= cost_classes
[k
];
1296 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], other_regno
)
1297 && (reg_class_size
[(int) rclass
]
1298 == ira_reg_class_max_nregs
[(int) rclass
][(int) mode
]))
1300 if (reg_class_size
[rclass
] == 1)
1301 op_costs
[i
]->cost
[k
] = -frequency
;
1305 nr
< hard_regno_nregs
[other_regno
][mode
];
1307 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
],
1311 if (nr
== hard_regno_nregs
[other_regno
][mode
])
1312 op_costs
[i
]->cost
[k
] = -frequency
;
1322 /* Process one insn INSN. Scan it and record each time it would save
1323 code to put a certain allocnos in a certain class. Return the last
1324 insn processed, so that the scan can be continued from there. */
1326 scan_one_insn (rtx_insn
*insn
)
1328 enum rtx_code pat_code
;
1333 if (!NONDEBUG_INSN_P (insn
))
1336 pat_code
= GET_CODE (PATTERN (insn
));
1337 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
)
1340 counted_mem
= false;
1341 set
= single_set (insn
);
1342 extract_insn (insn
);
1344 /* If this insn loads a parameter from its stack slot, then it
1345 represents a savings, rather than a cost, if the parameter is
1346 stored in memory. Record this fact.
1348 Similarly if we're loading other constants from memory (constant
1349 pool, TOC references, small data areas, etc) and this is the only
1350 assignment to the destination pseudo.
1352 Don't do this if SET_SRC (set) isn't a general operand, if it is
1353 a memory requiring special instructions to load it, decreasing
1354 mem_cost might result in it being loaded using the specialized
1355 instruction into a register, then stored into stack and loaded
1356 again from the stack. See PR52208.
1358 Don't do this if SET_SRC (set) has side effect. See PR56124. */
1359 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
1360 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
1361 && ((MEM_P (XEXP (note
, 0))
1362 && !side_effects_p (SET_SRC (set
)))
1363 || (CONSTANT_P (XEXP (note
, 0))
1364 && targetm
.legitimate_constant_p (GET_MODE (SET_DEST (set
)),
1366 && REG_N_SETS (REGNO (SET_DEST (set
))) == 1))
1367 && general_operand (SET_SRC (set
), GET_MODE (SET_SRC (set
))))
1369 enum reg_class cl
= GENERAL_REGS
;
1370 rtx reg
= SET_DEST (set
);
1371 int num
= COST_INDEX (REGNO (reg
));
1373 COSTS (costs
, num
)->mem_cost
1374 -= ira_memory_move_cost
[GET_MODE (reg
)][cl
][1] * frequency
;
1375 record_address_regs (GET_MODE (SET_SRC (set
)),
1376 MEM_ADDR_SPACE (SET_SRC (set
)),
1377 XEXP (SET_SRC (set
), 0), 0, MEM
, SCRATCH
,
1382 record_operand_costs (insn
, pref
);
1384 /* Now add the cost for each operand to the total costs for its
1386 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1387 if (REG_P (recog_data
.operand
[i
])
1388 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1390 int regno
= REGNO (recog_data
.operand
[i
]);
1391 struct costs
*p
= COSTS (costs
, COST_INDEX (regno
));
1392 struct costs
*q
= op_costs
[i
];
1393 int *p_costs
= p
->cost
, *q_costs
= q
->cost
;
1394 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1397 /* If the already accounted for the memory "cost" above, don't
1401 add_cost
= q
->mem_cost
;
1402 if (add_cost
> 0 && INT_MAX
- add_cost
< p
->mem_cost
)
1403 p
->mem_cost
= INT_MAX
;
1405 p
->mem_cost
+= add_cost
;
1407 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1409 add_cost
= q_costs
[k
];
1410 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1411 p_costs
[k
] = INT_MAX
;
1413 p_costs
[k
] += add_cost
;
1422 /* Print allocnos costs to file F. */
1424 print_allocno_costs (FILE *f
)
1428 ira_allocno_iterator ai
;
1430 ira_assert (allocno_p
);
1432 FOR_EACH_ALLOCNO (a
, ai
)
1436 int regno
= ALLOCNO_REGNO (a
);
1437 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1438 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1440 i
= ALLOCNO_NUM (a
);
1441 fprintf (f
, " a%d(r%d,", i
, regno
);
1442 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1443 fprintf (f
, "b%d", bb
->index
);
1445 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1446 fprintf (f
, ") costs:");
1447 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1449 rclass
= cost_classes
[k
];
1450 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1451 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
))
1453 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1454 COSTS (costs
, i
)->cost
[k
]);
1455 if (flag_ira_region
== IRA_REGION_ALL
1456 || flag_ira_region
== IRA_REGION_MIXED
)
1457 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->cost
[k
]);
1460 fprintf (f
, " MEM:%i", COSTS (costs
, i
)->mem_cost
);
1461 if (flag_ira_region
== IRA_REGION_ALL
1462 || flag_ira_region
== IRA_REGION_MIXED
)
1463 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->mem_cost
);
1468 /* Print pseudo costs to file F. */
1470 print_pseudo_costs (FILE *f
)
1474 cost_classes_t cost_classes_ptr
;
1475 enum reg_class
*cost_classes
;
1477 ira_assert (! allocno_p
);
1479 for (regno
= max_reg_num () - 1; regno
>= FIRST_PSEUDO_REGISTER
; regno
--)
1481 if (REG_N_REFS (regno
) <= 0)
1483 cost_classes_ptr
= regno_cost_classes
[regno
];
1484 cost_classes
= cost_classes_ptr
->classes
;
1485 fprintf (f
, " r%d costs:", regno
);
1486 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1488 rclass
= cost_classes
[k
];
1489 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1490 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
))
1491 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1492 COSTS (costs
, regno
)->cost
[k
]);
1494 fprintf (f
, " MEM:%i\n", COSTS (costs
, regno
)->mem_cost
);
1498 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1501 process_bb_for_costs (basic_block bb
)
1505 frequency
= REG_FREQ_FROM_BB (bb
);
1508 FOR_BB_INSNS (bb
, insn
)
1509 insn
= scan_one_insn (insn
);
1512 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1515 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1519 bb
= loop_tree_node
->bb
;
1521 process_bb_for_costs (bb
);
1524 /* Find costs of register classes and memory for allocnos or pseudos
1525 and their best costs. Set up preferred, alternative and allocno
1526 classes for pseudos. */
1528 find_costs_and_classes (FILE *dump_file
)
1530 int i
, k
, start
, max_cost_classes_num
;
1533 enum reg_class
*regno_best_class
;
1537 = (enum reg_class
*) ira_allocate (max_reg_num ()
1538 * sizeof (enum reg_class
));
1539 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1540 regno_best_class
[i
] = NO_REGS
;
1541 if (!resize_reg_info () && allocno_p
1542 && pseudo_classes_defined_p
&& flag_expensive_optimizations
)
1545 ira_allocno_iterator ai
;
1548 max_cost_classes_num
= 1;
1549 FOR_EACH_ALLOCNO (a
, ai
)
1551 pref
[ALLOCNO_NUM (a
)] = reg_preferred_class (ALLOCNO_REGNO (a
));
1552 setup_regno_cost_classes_by_aclass
1553 (ALLOCNO_REGNO (a
), pref
[ALLOCNO_NUM (a
)]);
1554 max_cost_classes_num
1555 = MAX (max_cost_classes_num
,
1556 regno_cost_classes
[ALLOCNO_REGNO (a
)]->num
);
1563 max_cost_classes_num
= ira_important_classes_num
;
1564 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1565 if (regno_reg_rtx
[i
] != NULL_RTX
)
1566 setup_regno_cost_classes_by_mode (i
, PSEUDO_REGNO_MODE (i
));
1568 setup_regno_cost_classes_by_aclass (i
, ALL_REGS
);
1572 /* Clear the flag for the next compiled function. */
1573 pseudo_classes_defined_p
= false;
1574 /* Normally we scan the insns once and determine the best class to
1575 use for each allocno. However, if -fexpensive-optimizations are
1576 on, we do so twice, the second time using the tentative best
1577 classes to guide the selection. */
1578 for (pass
= start
; pass
<= flag_expensive_optimizations
; pass
++)
1580 if ((!allocno_p
|| internal_flag_ira_verbose
> 0) && dump_file
)
1582 "\nPass %i for finding pseudo/allocno costs\n\n", pass
);
1586 max_cost_classes_num
= 1;
1587 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1589 setup_regno_cost_classes_by_aclass (i
, regno_best_class
[i
]);
1590 max_cost_classes_num
1591 = MAX (max_cost_classes_num
, regno_cost_classes
[i
]->num
);
1596 = sizeof (struct costs
) + sizeof (int) * (max_cost_classes_num
- 1);
1597 /* Zero out our accumulation of the cost of each class for each
1599 memset (costs
, 0, cost_elements_num
* struct_costs_size
);
1603 /* Scan the instructions and record each time it would save code
1604 to put a certain allocno in a certain class. */
1605 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1606 process_bb_node_for_costs
, NULL
);
1608 memcpy (total_allocno_costs
, costs
,
1609 max_struct_costs_size
* ira_allocnos_num
);
1615 FOR_EACH_BB_FN (bb
, cfun
)
1616 process_bb_for_costs (bb
);
1622 /* Now for each allocno look at how desirable each class is and
1623 find which class is preferred. */
1624 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1626 ira_allocno_t a
, parent_a
;
1627 int rclass
, a_num
, parent_a_num
, add_cost
;
1628 ira_loop_tree_node_t parent
;
1629 int best_cost
, allocno_cost
;
1630 enum reg_class best
, alt_class
;
1631 cost_classes_t cost_classes_ptr
= regno_cost_classes
[i
];
1632 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1633 int *i_costs
= temp_costs
->cost
;
1635 int equiv_savings
= regno_equiv_gains
[i
];
1639 if (regno_reg_rtx
[i
] == NULL_RTX
)
1641 memcpy (temp_costs
, COSTS (costs
, i
), struct_costs_size
);
1642 i_mem_cost
= temp_costs
->mem_cost
;
1646 if (ira_regno_allocno_map
[i
] == NULL
)
1648 memset (temp_costs
, 0, struct_costs_size
);
1650 /* Find cost of all allocnos with the same regno. */
1651 for (a
= ira_regno_allocno_map
[i
];
1653 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1655 int *a_costs
, *p_costs
;
1657 a_num
= ALLOCNO_NUM (a
);
1658 if ((flag_ira_region
== IRA_REGION_ALL
1659 || flag_ira_region
== IRA_REGION_MIXED
)
1660 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1661 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
1662 /* There are no caps yet. */
1663 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
1664 (a
)->border_allocnos
,
1667 /* Propagate costs to upper levels in the region
1669 parent_a_num
= ALLOCNO_NUM (parent_a
);
1670 a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1671 p_costs
= COSTS (total_allocno_costs
, parent_a_num
)->cost
;
1672 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1674 add_cost
= a_costs
[k
];
1675 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1676 p_costs
[k
] = INT_MAX
;
1678 p_costs
[k
] += add_cost
;
1680 add_cost
= COSTS (total_allocno_costs
, a_num
)->mem_cost
;
1682 && (INT_MAX
- add_cost
1683 < COSTS (total_allocno_costs
,
1684 parent_a_num
)->mem_cost
))
1685 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1688 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1691 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1692 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
= 0;
1694 a_costs
= COSTS (costs
, a_num
)->cost
;
1695 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1697 add_cost
= a_costs
[k
];
1698 if (add_cost
> 0 && INT_MAX
- add_cost
< i_costs
[k
])
1699 i_costs
[k
] = INT_MAX
;
1701 i_costs
[k
] += add_cost
;
1703 add_cost
= COSTS (costs
, a_num
)->mem_cost
;
1704 if (add_cost
> 0 && INT_MAX
- add_cost
< i_mem_cost
)
1705 i_mem_cost
= INT_MAX
;
1707 i_mem_cost
+= add_cost
;
1710 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1712 else if (equiv_savings
< 0)
1713 i_mem_cost
= -equiv_savings
;
1714 else if (equiv_savings
> 0)
1717 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1718 i_costs
[k
] += equiv_savings
;
1721 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1723 alt_class
= NO_REGS
;
1724 /* Find best common class for all allocnos with the same
1726 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1728 rclass
= cost_classes
[k
];
1729 /* Ignore classes that are too small or invalid for this
1731 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1732 || invalid_mode_change_p (i
, (enum reg_class
) rclass
))
1734 if (i_costs
[k
] < best_cost
)
1736 best_cost
= i_costs
[k
];
1737 best
= (enum reg_class
) rclass
;
1739 else if (i_costs
[k
] == best_cost
)
1740 best
= ira_reg_class_subunion
[best
][rclass
];
1741 if (pass
== flag_expensive_optimizations
1742 /* We still prefer registers to memory even at this
1743 stage if their costs are the same. We will make
1744 a final decision during assigning hard registers
1745 when we have all info including more accurate
1746 costs which might be affected by assigning hard
1747 registers to other pseudos because the pseudos
1748 involved in moves can be coalesced. */
1749 && i_costs
[k
] <= i_mem_cost
1750 && (reg_class_size
[reg_class_subunion
[alt_class
][rclass
]]
1751 > reg_class_size
[alt_class
]))
1752 alt_class
= reg_class_subunion
[alt_class
][rclass
];
1754 alt_class
= ira_allocno_class_translate
[alt_class
];
1755 if (best_cost
> i_mem_cost
)
1756 regno_aclass
[i
] = NO_REGS
;
1757 else if (!optimize
&& !targetm
.class_likely_spilled_p (best
))
1758 /* Registers in the alternative class are likely to need
1759 longer or slower sequences than registers in the best class.
1760 When optimizing we make some effort to use the best class
1761 over the alternative class where possible, but at -O0 we
1762 effectively give the alternative class equal weight.
1763 We then run the risk of using slower alternative registers
1764 when plenty of registers from the best class are still free.
1765 This is especially true because live ranges tend to be very
1766 short in -O0 code and so register pressure tends to be low.
1768 Avoid that by ignoring the alternative class if the best
1769 class has plenty of registers. */
1770 regno_aclass
[i
] = best
;
1773 /* Make the common class the biggest class of best and
1776 = ira_reg_class_superunion
[best
][alt_class
];
1777 ira_assert (regno_aclass
[i
] != NO_REGS
1778 && ira_reg_allocno_class_p
[regno_aclass
[i
]]);
1780 if (pass
== flag_expensive_optimizations
)
1782 if (best_cost
> i_mem_cost
)
1783 best
= alt_class
= NO_REGS
;
1784 else if (best
== alt_class
)
1785 alt_class
= NO_REGS
;
1786 setup_reg_classes (i
, best
, alt_class
, regno_aclass
[i
]);
1787 if ((!allocno_p
|| internal_flag_ira_verbose
> 2)
1788 && dump_file
!= NULL
)
1790 " r%d: preferred %s, alternative %s, allocno %s\n",
1791 i
, reg_class_names
[best
], reg_class_names
[alt_class
],
1792 reg_class_names
[regno_aclass
[i
]]);
1794 regno_best_class
[i
] = best
;
1797 pref
[i
] = best_cost
> i_mem_cost
? NO_REGS
: best
;
1800 for (a
= ira_regno_allocno_map
[i
];
1802 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1804 enum reg_class aclass
= regno_aclass
[i
];
1805 int a_num
= ALLOCNO_NUM (a
);
1806 int *total_a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1807 int *a_costs
= COSTS (costs
, a_num
)->cost
;
1809 if (aclass
== NO_REGS
)
1813 /* Finding best class which is subset of the common
1815 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1816 allocno_cost
= best_cost
;
1818 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1820 rclass
= cost_classes
[k
];
1821 if (! ira_class_subset_p
[rclass
][aclass
])
1823 /* Ignore classes that are too small or invalid
1824 for this operand. */
1825 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1826 || invalid_mode_change_p (i
, (enum reg_class
) rclass
))
1828 else if (total_a_costs
[k
] < best_cost
)
1830 best_cost
= total_a_costs
[k
];
1831 allocno_cost
= a_costs
[k
];
1832 best
= (enum reg_class
) rclass
;
1834 else if (total_a_costs
[k
] == best_cost
)
1836 best
= ira_reg_class_subunion
[best
][rclass
];
1837 allocno_cost
= MAX (allocno_cost
, a_costs
[k
]);
1840 ALLOCNO_CLASS_COST (a
) = allocno_cost
;
1842 if (internal_flag_ira_verbose
> 2 && dump_file
!= NULL
1843 && (pass
== 0 || pref
[a_num
] != best
))
1845 fprintf (dump_file
, " a%d (r%d,", a_num
, i
);
1846 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1847 fprintf (dump_file
, "b%d", bb
->index
);
1849 fprintf (dump_file
, "l%d",
1850 ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1851 fprintf (dump_file
, ") best %s, allocno %s\n",
1852 reg_class_names
[best
],
1853 reg_class_names
[aclass
]);
1856 if (pass
== flag_expensive_optimizations
&& best
!= aclass
1857 && ira_class_hard_regs_num
[best
] > 0
1858 && (ira_reg_class_max_nregs
[best
][ALLOCNO_MODE (a
)]
1859 >= ira_class_hard_regs_num
[best
]))
1861 int ind
= cost_classes_ptr
->index
[aclass
];
1863 ira_assert (ind
>= 0);
1864 ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a
));
1865 ira_add_allocno_pref (a
, ira_class_hard_regs
[best
][0],
1866 (a_costs
[ind
] - ALLOCNO_CLASS_COST (a
))
1867 / (ira_register_move_cost
1868 [ALLOCNO_MODE (a
)][best
][aclass
]));
1869 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1870 if (ira_class_subset_p
[cost_classes
[k
]][best
])
1871 a_costs
[k
] = a_costs
[ind
];
1876 if (internal_flag_ira_verbose
> 4 && dump_file
)
1879 print_allocno_costs (dump_file
);
1881 print_pseudo_costs (dump_file
);
1882 fprintf (dump_file
,"\n");
1885 ira_free (regno_best_class
);
1890 /* Process moves involving hard regs to modify allocno hard register
1891 costs. We can do this only after determining allocno class. If a
1892 hard register forms a register class, then moves with the hard
1893 register are already taken into account in class costs for the
1896 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1898 int i
, freq
, src_regno
, dst_regno
, hard_regno
, a_regno
;
1900 ira_allocno_t a
, curr_a
;
1901 ira_loop_tree_node_t curr_loop_tree_node
;
1902 enum reg_class rclass
;
1907 bb
= loop_tree_node
->bb
;
1910 freq
= REG_FREQ_FROM_BB (bb
);
1913 FOR_BB_INSNS (bb
, insn
)
1915 if (!NONDEBUG_INSN_P (insn
))
1917 set
= single_set (insn
);
1918 if (set
== NULL_RTX
)
1920 dst
= SET_DEST (set
);
1921 src
= SET_SRC (set
);
1922 if (! REG_P (dst
) || ! REG_P (src
))
1924 dst_regno
= REGNO (dst
);
1925 src_regno
= REGNO (src
);
1926 if (dst_regno
>= FIRST_PSEUDO_REGISTER
1927 && src_regno
< FIRST_PSEUDO_REGISTER
)
1929 hard_regno
= src_regno
;
1930 a
= ira_curr_regno_allocno_map
[dst_regno
];
1933 else if (src_regno
>= FIRST_PSEUDO_REGISTER
1934 && dst_regno
< FIRST_PSEUDO_REGISTER
)
1936 hard_regno
= dst_regno
;
1937 a
= ira_curr_regno_allocno_map
[src_regno
];
1942 rclass
= ALLOCNO_CLASS (a
);
1943 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
], hard_regno
))
1945 i
= ira_class_hard_reg_index
[rclass
][hard_regno
];
1948 a_regno
= ALLOCNO_REGNO (a
);
1949 for (curr_loop_tree_node
= ALLOCNO_LOOP_TREE_NODE (a
);
1950 curr_loop_tree_node
!= NULL
;
1951 curr_loop_tree_node
= curr_loop_tree_node
->parent
)
1952 if ((curr_a
= curr_loop_tree_node
->regno_allocno_map
[a_regno
]) != NULL
)
1953 ira_add_allocno_pref (curr_a
, hard_regno
, freq
);
1956 enum reg_class hard_reg_class
;
1957 enum machine_mode mode
;
1959 mode
= ALLOCNO_MODE (a
);
1960 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
1961 ira_init_register_move_cost_if_necessary (mode
);
1962 cost
= (to_p
? ira_register_move_cost
[mode
][hard_reg_class
][rclass
]
1963 : ira_register_move_cost
[mode
][rclass
][hard_reg_class
]) * freq
;
1964 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), rclass
,
1965 ALLOCNO_CLASS_COST (a
));
1966 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
1968 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
1969 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
1970 ALLOCNO_CLASS_COST (a
) = MIN (ALLOCNO_CLASS_COST (a
),
1971 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
1976 /* After we find hard register and memory costs for allocnos, define
1977 its class and modify hard register cost because insns moving
1978 allocno to/from hard registers. */
1980 setup_allocno_class_and_costs (void)
1982 int i
, j
, n
, regno
, hard_regno
, num
;
1984 enum reg_class aclass
, rclass
;
1986 ira_allocno_iterator ai
;
1987 cost_classes_t cost_classes_ptr
;
1989 ira_assert (allocno_p
);
1990 FOR_EACH_ALLOCNO (a
, ai
)
1992 i
= ALLOCNO_NUM (a
);
1993 regno
= ALLOCNO_REGNO (a
);
1994 aclass
= regno_aclass
[regno
];
1995 cost_classes_ptr
= regno_cost_classes
[regno
];
1996 ira_assert (pref
[i
] == NO_REGS
|| aclass
!= NO_REGS
);
1997 ALLOCNO_MEMORY_COST (a
) = COSTS (costs
, i
)->mem_cost
;
1998 ira_set_allocno_class (a
, aclass
);
1999 if (aclass
== NO_REGS
)
2001 if (optimize
&& ALLOCNO_CLASS (a
) != pref
[i
])
2003 n
= ira_class_hard_regs_num
[aclass
];
2004 ALLOCNO_HARD_REG_COSTS (a
)
2005 = reg_costs
= ira_allocate_cost_vector (aclass
);
2006 for (j
= n
- 1; j
>= 0; j
--)
2008 hard_regno
= ira_class_hard_regs
[aclass
][j
];
2009 if (TEST_HARD_REG_BIT (reg_class_contents
[pref
[i
]], hard_regno
))
2010 reg_costs
[j
] = ALLOCNO_CLASS_COST (a
);
2013 rclass
= REGNO_REG_CLASS (hard_regno
);
2014 num
= cost_classes_ptr
->index
[rclass
];
2017 num
= cost_classes_ptr
->hard_regno_index
[hard_regno
];
2018 ira_assert (num
>= 0);
2020 reg_costs
[j
] = COSTS (costs
, i
)->cost
[num
];
2026 ira_traverse_loop_tree (true, ira_loop_tree_root
,
2027 process_bb_node_for_hard_reg_moves
, NULL
);
2032 /* Function called once during compiler work. */
2034 ira_init_costs_once (void)
2039 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2042 this_op_costs
[i
] = NULL
;
2047 /* Free allocated temporary cost vectors. */
2049 target_ira_int::free_ira_costs ()
2055 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2057 free (x_op_costs
[i
]);
2058 free (x_this_op_costs
[i
]);
2059 x_op_costs
[i
] = x_this_op_costs
[i
] = NULL
;
2061 free (x_temp_costs
);
2062 x_temp_costs
= NULL
;
2065 /* This is called each time register related information is
2068 ira_init_costs (void)
2072 this_target_ira_int
->free_ira_costs ();
2073 max_struct_costs_size
2074 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
2075 /* Don't use ira_allocate because vectors live through several IRA
2077 init_cost
= (struct costs
*) xmalloc (max_struct_costs_size
);
2078 init_cost
->mem_cost
= 1000000;
2079 for (i
= 0; i
< ira_important_classes_num
; i
++)
2080 init_cost
->cost
[i
] = 1000000;
2081 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2083 op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2084 this_op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2086 temp_costs
= (struct costs
*) xmalloc (max_struct_costs_size
);
2091 /* Common initialization function for ira_costs and
2092 ira_set_pseudo_classes. */
2096 init_subregs_of_mode ();
2097 costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2098 * cost_elements_num
);
2099 pref_buffer
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2100 * cost_elements_num
);
2101 regno_aclass
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2103 regno_equiv_gains
= (int *) ira_allocate (sizeof (int) * max_reg_num ());
2104 memset (regno_equiv_gains
, 0, sizeof (int) * max_reg_num ());
2107 /* Common finalization function for ira_costs and
2108 ira_set_pseudo_classes. */
2112 finish_subregs_of_mode ();
2113 ira_free (regno_equiv_gains
);
2114 ira_free (regno_aclass
);
2115 ira_free (pref_buffer
);
2119 /* Entry function which defines register class, memory and hard
2120 register costs for each allocno. */
2125 cost_elements_num
= ira_allocnos_num
;
2127 total_allocno_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2128 * ira_allocnos_num
);
2129 initiate_regno_cost_classes ();
2130 calculate_elim_costs_all_insns ();
2131 find_costs_and_classes (ira_dump_file
);
2132 setup_allocno_class_and_costs ();
2133 finish_regno_cost_classes ();
2135 ira_free (total_allocno_costs
);
2138 /* Entry function which defines classes for pseudos.
2139 Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2141 ira_set_pseudo_classes (bool define_pseudo_classes
, FILE *dump_file
)
2144 internal_flag_ira_verbose
= flag_ira_verbose
;
2145 cost_elements_num
= max_reg_num ();
2147 initiate_regno_cost_classes ();
2148 find_costs_and_classes (dump_file
);
2149 finish_regno_cost_classes ();
2150 if (define_pseudo_classes
)
2151 pseudo_classes_defined_p
= true;
2158 /* Change hard register costs for allocnos which lives through
2159 function calls. This is called only when we found all intersected
2160 calls during building allocno live ranges. */
2162 ira_tune_allocno_costs (void)
2165 int cost
, min_cost
, *reg_costs
;
2166 enum reg_class aclass
, rclass
;
2167 enum machine_mode mode
;
2169 ira_allocno_iterator ai
;
2170 ira_allocno_object_iterator oi
;
2173 HARD_REG_SET
*crossed_calls_clobber_regs
;
2175 FOR_EACH_ALLOCNO (a
, ai
)
2177 aclass
= ALLOCNO_CLASS (a
);
2178 if (aclass
== NO_REGS
)
2180 mode
= ALLOCNO_MODE (a
);
2181 n
= ira_class_hard_regs_num
[aclass
];
2183 if (ALLOCNO_CALLS_CROSSED_NUM (a
)
2184 != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2186 ira_allocate_and_set_costs
2187 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
,
2188 ALLOCNO_CLASS_COST (a
));
2189 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2190 for (j
= n
- 1; j
>= 0; j
--)
2192 regno
= ira_class_hard_regs
[aclass
][j
];
2194 FOR_EACH_ALLOCNO_OBJECT (a
, obj
, oi
)
2196 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2197 OBJECT_CONFLICT_HARD_REGS
2206 rclass
= REGNO_REG_CLASS (regno
);
2208 crossed_calls_clobber_regs
2209 = &(ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
));
2210 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2211 *crossed_calls_clobber_regs
)
2212 && (ira_hard_reg_set_intersection_p (regno
, mode
,
2214 || HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2215 cost
+= (ALLOCNO_CALL_FREQ (a
)
2216 * (ira_memory_move_cost
[mode
][rclass
][0]
2217 + ira_memory_move_cost
[mode
][rclass
][1]));
2218 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2219 cost
+= ((ira_memory_move_cost
[mode
][rclass
][0]
2220 + ira_memory_move_cost
[mode
][rclass
][1])
2222 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
2224 if (INT_MAX
- cost
< reg_costs
[j
])
2225 reg_costs
[j
] = INT_MAX
;
2227 reg_costs
[j
] += cost
;
2228 if (min_cost
> reg_costs
[j
])
2229 min_cost
= reg_costs
[j
];
2232 if (min_cost
!= INT_MAX
)
2233 ALLOCNO_CLASS_COST (a
) = min_cost
;
2235 /* Some targets allow pseudos to be allocated to unaligned sequences
2236 of hard registers. However, selecting an unaligned sequence can
2237 unnecessarily restrict later allocations. So increase the cost of
2238 unaligned hard regs to encourage the use of aligned hard regs. */
2240 const int nregs
= ira_reg_class_max_nregs
[aclass
][ALLOCNO_MODE (a
)];
2244 ira_allocate_and_set_costs
2245 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
, ALLOCNO_CLASS_COST (a
));
2246 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2247 for (j
= n
- 1; j
>= 0; j
--)
2249 regno
= ira_non_ordered_class_hard_regs
[aclass
][j
];
2250 if ((regno
% nregs
) != 0)
2252 int index
= ira_class_hard_reg_index
[aclass
][regno
];
2253 ira_assert (index
!= -1);
2254 reg_costs
[index
] += ALLOCNO_FREQ (a
);
2262 /* Add COST to the estimated gain for eliminating REGNO with its
2263 equivalence. If COST is zero, record that no such elimination is
2267 ira_adjust_equiv_reg_cost (unsigned regno
, int cost
)
2270 regno_equiv_gains
[regno
] = 0;
2272 regno_equiv_gains
[regno
] += cost
;