1 /* IRA hard register and memory cost calculation for allocnos or pseudos.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "hash-table.h"
26 #include "hard-reg-set.h"
31 #include "basic-block.h"
33 #include "addresses.h"
34 #include "insn-config.h"
37 #include "diagnostic-core.h"
42 /* The flags is set up every time when we calculate pseudo register
43 classes through function ira_set_pseudo_classes. */
44 static bool pseudo_classes_defined_p
= false;
46 /* TRUE if we work with allocnos. Otherwise we work with pseudos. */
47 static bool allocno_p
;
49 /* Number of elements in array `costs'. */
50 static int cost_elements_num
;
52 /* The `costs' struct records the cost of using hard registers of each
53 class considered for the calculation and of using memory for each
58 /* Costs for register classes start here. We process only some
63 #define max_struct_costs_size \
64 (this_target_ira_int->x_max_struct_costs_size)
66 (this_target_ira_int->x_init_cost)
68 (this_target_ira_int->x_temp_costs)
70 (this_target_ira_int->x_op_costs)
71 #define this_op_costs \
72 (this_target_ira_int->x_this_op_costs)
74 /* Costs of each class for each allocno or pseudo. */
75 static struct costs
*costs
;
77 /* Accumulated costs of each class for each allocno. */
78 static struct costs
*total_allocno_costs
;
80 /* It is the current size of struct costs. */
81 static int struct_costs_size
;
83 /* Return pointer to structure containing costs of allocno or pseudo
84 with given NUM in array ARR. */
85 #define COSTS(arr, num) \
86 ((struct costs *) ((char *) (arr) + (num) * struct_costs_size))
88 /* Return index in COSTS when processing reg with REGNO. */
89 #define COST_INDEX(regno) (allocno_p \
90 ? ALLOCNO_NUM (ira_curr_regno_allocno_map[regno]) \
93 /* Record register class preferences of each allocno or pseudo. Null
94 value means no preferences. It happens on the 1st iteration of the
96 static enum reg_class
*pref
;
98 /* Allocated buffers for pref. */
99 static enum reg_class
*pref_buffer
;
101 /* Record allocno class of each allocno with the same regno. */
102 static enum reg_class
*regno_aclass
;
104 /* Record cost gains for not allocating a register with an invariant
106 static int *regno_equiv_gains
;
108 /* Execution frequency of the current insn. */
109 static int frequency
;
113 /* Info about reg classes whose costs are calculated for a pseudo. */
116 /* Number of the cost classes in the subsequent array. */
118 /* Container of the cost classes. */
119 enum reg_class classes
[N_REG_CLASSES
];
120 /* Map reg class -> index of the reg class in the previous array.
121 -1 if it is not a cost classe. */
122 int index
[N_REG_CLASSES
];
123 /* Map hard regno index of first class in array CLASSES containing
124 the hard regno, -1 otherwise. */
125 int hard_regno_index
[FIRST_PSEUDO_REGISTER
];
128 /* Types of pointers to the structure above. */
129 typedef struct cost_classes
*cost_classes_t
;
130 typedef const struct cost_classes
*const_cost_classes_t
;
132 /* Info about cost classes for each pseudo. */
133 static cost_classes_t
*regno_cost_classes
;
135 /* Helper for cost_classes hashing. */
137 struct cost_classes_hasher
139 typedef cost_classes value_type
;
140 typedef cost_classes compare_type
;
141 static inline hashval_t
hash (const value_type
*);
142 static inline bool equal (const value_type
*, const compare_type
*);
143 static inline void remove (value_type
*);
146 /* Returns hash value for cost classes info HV. */
148 cost_classes_hasher::hash (const value_type
*hv
)
150 return iterative_hash (&hv
->classes
, sizeof (enum reg_class
) * hv
->num
, 0);
153 /* Compares cost classes info HV1 and HV2. */
155 cost_classes_hasher::equal (const value_type
*hv1
, const compare_type
*hv2
)
157 return (hv1
->num
== hv2
->num
158 && memcmp (hv1
->classes
, hv2
->classes
,
159 sizeof (enum reg_class
) * hv1
->num
) == 0);
162 /* Delete cost classes info V from the hash table. */
164 cost_classes_hasher::remove (value_type
*v
)
169 /* Hash table of unique cost classes. */
170 static hash_table
<cost_classes_hasher
> cost_classes_htab
;
172 /* Map allocno class -> cost classes for pseudo of given allocno
174 static cost_classes_t cost_classes_aclass_cache
[N_REG_CLASSES
];
176 /* Map mode -> cost classes for pseudo of give mode. */
177 static cost_classes_t cost_classes_mode_cache
[MAX_MACHINE_MODE
];
179 /* Initialize info about the cost classes for each pseudo. */
181 initiate_regno_cost_classes (void)
183 int size
= sizeof (cost_classes_t
) * max_reg_num ();
185 regno_cost_classes
= (cost_classes_t
*) ira_allocate (size
);
186 memset (regno_cost_classes
, 0, size
);
187 memset (cost_classes_aclass_cache
, 0,
188 sizeof (cost_classes_t
) * N_REG_CLASSES
);
189 memset (cost_classes_mode_cache
, 0,
190 sizeof (cost_classes_t
) * MAX_MACHINE_MODE
);
191 cost_classes_htab
.create (200);
194 /* Create new cost classes from cost classes FROM and set up members
195 index and hard_regno_index. Return the new classes. The function
196 implements some common code of two functions
197 setup_regno_cost_classes_by_aclass and
198 setup_regno_cost_classes_by_mode. */
199 static cost_classes_t
200 setup_cost_classes (cost_classes_t from
)
202 cost_classes_t classes_ptr
;
204 int i
, j
, hard_regno
;
206 classes_ptr
= (cost_classes_t
) ira_allocate (sizeof (struct cost_classes
));
207 classes_ptr
->num
= from
->num
;
208 for (i
= 0; i
< N_REG_CLASSES
; i
++)
209 classes_ptr
->index
[i
] = -1;
210 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
211 classes_ptr
->hard_regno_index
[i
] = -1;
212 for (i
= 0; i
< from
->num
; i
++)
214 cl
= classes_ptr
->classes
[i
] = from
->classes
[i
];
215 classes_ptr
->index
[cl
] = i
;
216 for (j
= ira_class_hard_regs_num
[cl
] - 1; j
>= 0; j
--)
218 hard_regno
= ira_class_hard_regs
[cl
][j
];
219 if (classes_ptr
->hard_regno_index
[hard_regno
] < 0)
220 classes_ptr
->hard_regno_index
[hard_regno
] = i
;
226 /* Setup cost classes for pseudo REGNO whose allocno class is ACLASS.
227 This function is used when we know an initial approximation of
228 allocno class of the pseudo already, e.g. on the second iteration
229 of class cost calculation or after class cost calculation in
230 register-pressure sensitive insn scheduling or register-pressure
231 sensitive loop-invariant motion. */
233 setup_regno_cost_classes_by_aclass (int regno
, enum reg_class aclass
)
235 static struct cost_classes classes
;
236 cost_classes_t classes_ptr
;
240 HARD_REG_SET temp
, temp2
;
243 if ((classes_ptr
= cost_classes_aclass_cache
[aclass
]) == NULL
)
245 COPY_HARD_REG_SET (temp
, reg_class_contents
[aclass
]);
246 AND_COMPL_HARD_REG_SET (temp
, ira_no_alloc_regs
);
247 /* We exclude classes from consideration which are subsets of
248 ACLASS only if ACLASS is an uniform class. */
249 exclude_p
= ira_uniform_class_p
[aclass
];
251 for (i
= 0; i
< ira_important_classes_num
; i
++)
253 cl
= ira_important_classes
[i
];
256 /* Exclude non-uniform classes which are subsets of
258 COPY_HARD_REG_SET (temp2
, reg_class_contents
[cl
]);
259 AND_COMPL_HARD_REG_SET (temp2
, ira_no_alloc_regs
);
260 if (hard_reg_set_subset_p (temp2
, temp
) && cl
!= aclass
)
263 classes
.classes
[classes
.num
++] = cl
;
265 slot
= cost_classes_htab
.find_slot (&classes
, INSERT
);
268 classes_ptr
= setup_cost_classes (&classes
);
271 classes_ptr
= cost_classes_aclass_cache
[aclass
] = (cost_classes_t
) *slot
;
273 regno_cost_classes
[regno
] = classes_ptr
;
276 /* Setup cost classes for pseudo REGNO with MODE. Usage of MODE can
277 decrease number of cost classes for the pseudo, if hard registers
278 of some important classes can not hold a value of MODE. So the
279 pseudo can not get hard register of some important classes and cost
280 calculation for such important classes is only waisting CPU
283 setup_regno_cost_classes_by_mode (int regno
, enum machine_mode mode
)
285 static struct cost_classes classes
;
286 cost_classes_t classes_ptr
;
292 if ((classes_ptr
= cost_classes_mode_cache
[mode
]) == NULL
)
295 for (i
= 0; i
< ira_important_classes_num
; i
++)
297 cl
= ira_important_classes
[i
];
298 COPY_HARD_REG_SET (temp
, ira_prohibited_class_mode_regs
[cl
][mode
]);
299 IOR_HARD_REG_SET (temp
, ira_no_alloc_regs
);
300 if (hard_reg_set_subset_p (reg_class_contents
[cl
], temp
))
302 classes
.classes
[classes
.num
++] = cl
;
304 slot
= cost_classes_htab
.find_slot (&classes
, INSERT
);
307 classes_ptr
= setup_cost_classes (&classes
);
311 classes_ptr
= (cost_classes_t
) *slot
;
312 cost_classes_mode_cache
[mode
] = (cost_classes_t
) *slot
;
314 regno_cost_classes
[regno
] = classes_ptr
;
317 /* Finilize info about the cost classes for each pseudo. */
319 finish_regno_cost_classes (void)
321 ira_free (regno_cost_classes
);
322 cost_classes_htab
.dispose ();
327 /* Compute the cost of loading X into (if TO_P is TRUE) or from (if
328 TO_P is FALSE) a register of class RCLASS in mode MODE. X must not
329 be a pseudo register. */
331 copy_cost (rtx x
, enum machine_mode mode
, reg_class_t rclass
, bool to_p
,
332 secondary_reload_info
*prev_sri
)
334 secondary_reload_info sri
;
335 reg_class_t secondary_class
= NO_REGS
;
337 /* If X is a SCRATCH, there is actually nothing to move since we are
338 assuming optimal allocation. */
339 if (GET_CODE (x
) == SCRATCH
)
342 /* Get the class we will actually use for a reload. */
343 rclass
= targetm
.preferred_reload_class (x
, rclass
);
345 /* If we need a secondary reload for an intermediate, the cost is
346 that to load the input into the intermediate register, then to
348 sri
.prev_sri
= prev_sri
;
350 secondary_class
= targetm
.secondary_reload (to_p
, x
, rclass
, mode
, &sri
);
352 if (secondary_class
!= NO_REGS
)
354 ira_init_register_move_cost_if_necessary (mode
);
355 return (ira_register_move_cost
[mode
][(int) secondary_class
][(int) rclass
]
357 + copy_cost (x
, mode
, secondary_class
, to_p
, &sri
));
360 /* For memory, use the memory move cost, for (hard) registers, use
361 the cost to move between the register classes, and use 2 for
362 everything else (constants). */
363 if (MEM_P (x
) || rclass
== NO_REGS
)
364 return sri
.extra_cost
365 + ira_memory_move_cost
[mode
][(int) rclass
][to_p
!= 0];
368 reg_class_t x_class
= REGNO_REG_CLASS (REGNO (x
));
370 ira_init_register_move_cost_if_necessary (mode
);
371 return (sri
.extra_cost
372 + ira_register_move_cost
[mode
][(int) x_class
][(int) rclass
]);
375 /* If this is a constant, we may eventually want to call rtx_cost
377 return sri
.extra_cost
+ COSTS_N_INSNS (1);
382 /* Record the cost of using memory or hard registers of various
383 classes for the operands in INSN.
385 N_ALTS is the number of alternatives.
386 N_OPS is the number of operands.
387 OPS is an array of the operands.
388 MODES are the modes of the operands, in case any are VOIDmode.
389 CONSTRAINTS are the constraints to use for the operands. This array
390 is modified by this procedure.
392 This procedure works alternative by alternative. For each
393 alternative we assume that we will be able to allocate all allocnos
394 to their ideal register class and calculate the cost of using that
395 alternative. Then we compute, for each operand that is a
396 pseudo-register, the cost of having the allocno allocated to each
397 register class and using it in that alternative. To this cost is
398 added the cost of the alternative.
400 The cost of each class for this insn is its lowest cost among all
403 record_reg_classes (int n_alts
, int n_ops
, rtx
*ops
,
404 enum machine_mode
*modes
, const char **constraints
,
405 rtx insn
, enum reg_class
*pref
)
409 int insn_allows_mem
[MAX_RECOG_OPERANDS
];
411 for (i
= 0; i
< n_ops
; i
++)
412 insn_allows_mem
[i
] = 0;
414 /* Process each alternative, each time minimizing an operand's cost
415 with the cost for each operand in that alternative. */
416 for (alt
= 0; alt
< n_alts
; alt
++)
418 enum reg_class classes
[MAX_RECOG_OPERANDS
];
419 int allows_mem
[MAX_RECOG_OPERANDS
];
420 enum reg_class rclass
;
422 int alt_cost
= 0, op_cost_add
;
424 if (!recog_data
.alternative_enabled_p
[alt
])
426 for (i
= 0; i
< recog_data
.n_operands
; i
++)
427 constraints
[i
] = skip_alternative (constraints
[i
]);
432 for (i
= 0; i
< n_ops
; i
++)
435 const char *p
= constraints
[i
];
437 enum machine_mode mode
= modes
[i
];
441 /* Initially show we know nothing about the register class. */
442 classes
[i
] = NO_REGS
;
445 /* If this operand has no constraints at all, we can
446 conclude nothing about it since anything is valid. */
449 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
450 memset (this_op_costs
[i
], 0, struct_costs_size
);
454 /* If this alternative is only relevant when this operand
455 matches a previous operand, we do different things
456 depending on whether this operand is a allocno-reg or not.
457 We must process any modifiers for the operand before we
458 can make this test. */
459 while (*p
== '%' || *p
== '=' || *p
== '+' || *p
== '&')
462 if (p
[0] >= '0' && p
[0] <= '0' + i
&& (p
[1] == ',' || p
[1] == 0))
464 /* Copy class and whether memory is allowed from the
465 matching alternative. Then perform any needed cost
466 computations and/or adjustments. */
468 classes
[i
] = classes
[j
];
469 allows_mem
[i
] = allows_mem
[j
];
471 insn_allows_mem
[i
] = 1;
473 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
475 /* If this matches the other operand, we have no
476 added cost and we win. */
477 if (rtx_equal_p (ops
[j
], op
))
479 /* If we can put the other operand into a register,
480 add to the cost of this alternative the cost to
481 copy this operand to the register used for the
483 else if (classes
[j
] != NO_REGS
)
485 alt_cost
+= copy_cost (op
, mode
, classes
[j
], 1, NULL
);
489 else if (! REG_P (ops
[j
])
490 || REGNO (ops
[j
]) < FIRST_PSEUDO_REGISTER
)
492 /* This op is an allocno but the one it matches is
495 /* If we can't put the other operand into a
496 register, this alternative can't be used. */
498 if (classes
[j
] == NO_REGS
)
500 /* Otherwise, add to the cost of this alternative
501 the cost to copy the other operand to the hard
502 register used for this operand. */
504 alt_cost
+= copy_cost (ops
[j
], mode
, classes
[j
], 1, NULL
);
508 /* The costs of this operand are not the same as the
509 other operand since move costs are not symmetric.
510 Moreover, if we cannot tie them, this alternative
511 needs to do a copy, which is one insn. */
512 struct costs
*pp
= this_op_costs
[i
];
513 int *pp_costs
= pp
->cost
;
514 cost_classes_t cost_classes_ptr
515 = regno_cost_classes
[REGNO (op
)];
516 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
517 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
518 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
519 enum reg_class op_class
= classes
[i
];
520 move_table
*move_in_cost
, *move_out_cost
;
522 ira_init_register_move_cost_if_necessary (mode
);
526 move_out_cost
= ira_may_move_out_cost
[mode
];
527 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
529 rclass
= cost_classes
[k
];
531 = move_out_cost
[op_class
][rclass
] * frequency
;
537 move_in_cost
= ira_may_move_in_cost
[mode
];
538 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
540 rclass
= cost_classes
[k
];
542 = move_in_cost
[rclass
][op_class
] * frequency
;
547 move_in_cost
= ira_may_move_in_cost
[mode
];
548 move_out_cost
= ira_may_move_out_cost
[mode
];
549 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
551 rclass
= cost_classes
[k
];
552 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
553 + move_out_cost
[op_class
][rclass
])
558 /* If the alternative actually allows memory, make
559 things a bit cheaper since we won't need an extra
562 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
563 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
564 - allows_mem
[i
]) * frequency
;
566 /* If we have assigned a class to this allocno in
567 our first pass, add a cost to this alternative
568 corresponding to what we would add if this
569 allocno were not in the appropriate class. */
572 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
574 if (pref_class
== NO_REGS
)
577 ? ira_memory_move_cost
[mode
][op_class
][0] : 0)
579 ? ira_memory_move_cost
[mode
][op_class
][1]
581 else if (ira_reg_class_intersect
582 [pref_class
][op_class
] == NO_REGS
)
584 += ira_register_move_cost
[mode
][pref_class
][op_class
];
586 if (REGNO (ops
[i
]) != REGNO (ops
[j
])
587 && ! find_reg_note (insn
, REG_DEAD
, op
))
590 /* This is in place of ordinary cost computation for
591 this operand, so skip to the end of the
592 alternative (should be just one character). */
593 while (*p
&& *p
++ != ',')
601 /* Scan all the constraint letters. See if the operand
602 matches any of the constraints. Collect the valid
603 register classes and see if this operand accepts
612 /* Ignore the next letter for this pass. */
618 case '!': case '#': case '&':
619 case '0': case '1': case '2': case '3': case '4':
620 case '5': case '6': case '7': case '8': case '9':
625 win
= address_operand (op
, GET_MODE (op
));
626 /* We know this operand is an address, so we want it
627 to be allocated to a register that can be the
628 base of an address, i.e. BASE_REG_CLASS. */
630 = ira_reg_class_subunion
[classes
[i
]]
631 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
635 case 'm': case 'o': case 'V':
636 /* It doesn't seem worth distinguishing between
637 offsettable and non-offsettable addresses
639 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
646 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
647 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
653 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
654 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
660 if (CONST_DOUBLE_AS_FLOAT_P (op
)
661 || (GET_CODE (op
) == CONST_VECTOR
662 && (GET_MODE_CLASS (GET_MODE (op
))
663 == MODE_VECTOR_FLOAT
)))
669 if (CONST_DOUBLE_AS_FLOAT_P (op
)
670 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
675 if (CONST_SCALAR_INT_P (op
))
680 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
)))
685 if (CONST_SCALAR_INT_P (op
))
698 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
709 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))))
711 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
713 classes
[i
] = ira_reg_class_subunion
[classes
[i
]][GENERAL_REGS
];
717 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) != NO_REGS
)
718 classes
[i
] = ira_reg_class_subunion
[classes
[i
]]
719 [REG_CLASS_FROM_CONSTRAINT (c
, p
)];
720 #ifdef EXTRA_CONSTRAINT_STR
721 else if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
724 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
726 /* Every MEM can be reloaded to fit. */
727 insn_allows_mem
[i
] = allows_mem
[i
] = 1;
731 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
733 /* Every address can be reloaded to fit. */
735 if (address_operand (op
, GET_MODE (op
)))
737 /* We know this operand is an address, so we
738 want it to be allocated to a hard register
739 that can be the base of an address,
740 i.e. BASE_REG_CLASS. */
742 = ira_reg_class_subunion
[classes
[i
]]
743 [base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
749 p
+= CONSTRAINT_LEN (c
, p
);
756 /* How we account for this operand now depends on whether it
757 is a pseudo register or not. If it is, we first check if
758 any register classes are valid. If not, we ignore this
759 alternative, since we want to assume that all allocnos get
760 allocated for register preferencing. If some register
761 class is valid, compute the costs of moving the allocno
763 if (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
765 if (classes
[i
] == NO_REGS
&& ! allows_mem
[i
])
767 /* We must always fail if the operand is a REG, but
768 we did not find a suitable class and memory is
771 Otherwise we may perform an uninitialized read
772 from this_op_costs after the `continue' statement
778 unsigned int regno
= REGNO (op
);
779 struct costs
*pp
= this_op_costs
[i
];
780 int *pp_costs
= pp
->cost
;
781 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
782 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
783 bool in_p
= recog_data
.operand_type
[i
] != OP_OUT
;
784 bool out_p
= recog_data
.operand_type
[i
] != OP_IN
;
785 enum reg_class op_class
= classes
[i
];
786 move_table
*move_in_cost
, *move_out_cost
;
787 short (*mem_cost
)[2];
789 ira_init_register_move_cost_if_necessary (mode
);
793 if (op_class
== NO_REGS
)
795 mem_cost
= ira_memory_move_cost
[mode
];
796 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
798 rclass
= cost_classes
[k
];
799 pp_costs
[k
] = mem_cost
[rclass
][0] * frequency
;
804 move_out_cost
= ira_may_move_out_cost
[mode
];
805 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
807 rclass
= cost_classes
[k
];
809 = move_out_cost
[op_class
][rclass
] * frequency
;
816 if (op_class
== NO_REGS
)
818 mem_cost
= ira_memory_move_cost
[mode
];
819 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
821 rclass
= cost_classes
[k
];
822 pp_costs
[k
] = mem_cost
[rclass
][1] * frequency
;
827 move_in_cost
= ira_may_move_in_cost
[mode
];
828 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
830 rclass
= cost_classes
[k
];
832 = move_in_cost
[rclass
][op_class
] * frequency
;
838 if (op_class
== NO_REGS
)
840 mem_cost
= ira_memory_move_cost
[mode
];
841 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
843 rclass
= cost_classes
[k
];
844 pp_costs
[k
] = ((mem_cost
[rclass
][0]
845 + mem_cost
[rclass
][1])
851 move_in_cost
= ira_may_move_in_cost
[mode
];
852 move_out_cost
= ira_may_move_out_cost
[mode
];
853 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
855 rclass
= cost_classes
[k
];
856 pp_costs
[k
] = ((move_in_cost
[rclass
][op_class
]
857 + move_out_cost
[op_class
][rclass
])
863 /* If the alternative actually allows memory, make
864 things a bit cheaper since we won't need an extra
866 if (op_class
!= NO_REGS
)
868 = ((out_p
? ira_memory_move_cost
[mode
][op_class
][0] : 0)
869 + (in_p
? ira_memory_move_cost
[mode
][op_class
][1] : 0)
870 - allows_mem
[i
]) * frequency
;
871 /* If we have assigned a class to this allocno in
872 our first pass, add a cost to this alternative
873 corresponding to what we would add if this
874 allocno were not in the appropriate class. */
877 enum reg_class pref_class
= pref
[COST_INDEX (REGNO (op
))];
879 if (pref_class
== NO_REGS
)
881 if (op_class
!= NO_REGS
)
884 ? ira_memory_move_cost
[mode
][op_class
][0]
887 ? ira_memory_move_cost
[mode
][op_class
][1]
890 else if (op_class
== NO_REGS
)
893 ? ira_memory_move_cost
[mode
][pref_class
][1]
896 ? ira_memory_move_cost
[mode
][pref_class
][0]
898 else if (ira_reg_class_intersect
[pref_class
][op_class
]
900 alt_cost
+= (ira_register_move_cost
901 [mode
][pref_class
][op_class
]);
906 /* Otherwise, if this alternative wins, either because we
907 have already determined that or if we have a hard
908 register of the proper class, there is no cost for this
910 else if (win
|| (REG_P (op
)
911 && reg_fits_class_p (op
, classes
[i
],
915 /* If registers are valid, the cost of this alternative
916 includes copying the object to and/or from a
918 else if (classes
[i
] != NO_REGS
)
920 if (recog_data
.operand_type
[i
] != OP_OUT
)
921 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 1, NULL
);
923 if (recog_data
.operand_type
[i
] != OP_IN
)
924 alt_cost
+= copy_cost (op
, mode
, classes
[i
], 0, NULL
);
926 /* The only other way this alternative can be used is if
927 this is a constant that could be placed into memory. */
928 else if (CONSTANT_P (op
) && (allows_addr
|| allows_mem
[i
]))
929 alt_cost
+= ira_memory_move_cost
[mode
][classes
[i
]][1];
937 op_cost_add
= alt_cost
* frequency
;
938 /* Finally, update the costs with the information we've
939 calculated about this alternative. */
940 for (i
= 0; i
< n_ops
; i
++)
941 if (REG_P (ops
[i
]) && REGNO (ops
[i
]) >= FIRST_PSEUDO_REGISTER
)
943 struct costs
*pp
= op_costs
[i
], *qq
= this_op_costs
[i
];
944 int *pp_costs
= pp
->cost
, *qq_costs
= qq
->cost
;
945 int scale
= 1 + (recog_data
.operand_type
[i
] == OP_INOUT
);
946 cost_classes_t cost_classes_ptr
947 = regno_cost_classes
[REGNO (ops
[i
])];
949 pp
->mem_cost
= MIN (pp
->mem_cost
,
950 (qq
->mem_cost
+ op_cost_add
) * scale
);
952 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
954 = MIN (pp_costs
[k
], (qq_costs
[k
] + op_cost_add
) * scale
);
959 for (i
= 0; i
< n_ops
; i
++)
964 if (! REG_P (op
) || REGNO (op
) < FIRST_PSEUDO_REGISTER
)
966 a
= ira_curr_regno_allocno_map
[REGNO (op
)];
967 if (! ALLOCNO_BAD_SPILL_P (a
) && insn_allows_mem
[i
] == 0)
968 ALLOCNO_BAD_SPILL_P (a
) = true;
975 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudo registers. */
977 ok_for_index_p_nonstrict (rtx reg
)
979 unsigned regno
= REGNO (reg
);
981 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
984 /* A version of regno_ok_for_base_p for use here, when all
985 pseudo-registers should count as OK. Arguments as for
986 regno_ok_for_base_p. */
988 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
989 enum rtx_code outer_code
, enum rtx_code index_code
)
991 unsigned regno
= REGNO (reg
);
993 if (regno
>= FIRST_PSEUDO_REGISTER
)
995 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
998 /* Record the pseudo registers we must reload into hard registers in a
999 subexpression of a memory address, X.
1001 If CONTEXT is 0, we are looking at the base part of an address,
1002 otherwise we are looking at the index part.
1004 MODE and AS are the mode and address space of the memory reference;
1005 OUTER_CODE and INDEX_CODE give the context that the rtx appears in.
1006 These four arguments are passed down to base_reg_class.
1008 SCALE is twice the amount to multiply the cost by (it is twice so
1009 we can represent half-cost adjustments). */
1011 record_address_regs (enum machine_mode mode
, addr_space_t as
, rtx x
,
1012 int context
, enum rtx_code outer_code
,
1013 enum rtx_code index_code
, int scale
)
1015 enum rtx_code code
= GET_CODE (x
);
1016 enum reg_class rclass
;
1019 rclass
= INDEX_REG_CLASS
;
1021 rclass
= base_reg_class (mode
, as
, outer_code
, index_code
);
1034 /* When we have an address that is a sum, we must determine
1035 whether registers are "base" or "index" regs. If there is a
1036 sum of two registers, we must choose one to be the "base".
1037 Luckily, we can use the REG_POINTER to make a good choice
1038 most of the time. We only need to do this on machines that
1039 can have two registers in an address and where the base and
1040 index register classes are different.
1042 ??? This code used to set REGNO_POINTER_FLAG in some cases,
1043 but that seems bogus since it should only be set when we are
1044 sure the register is being used as a pointer. */
1046 rtx arg0
= XEXP (x
, 0);
1047 rtx arg1
= XEXP (x
, 1);
1048 enum rtx_code code0
= GET_CODE (arg0
);
1049 enum rtx_code code1
= GET_CODE (arg1
);
1051 /* Look inside subregs. */
1052 if (code0
== SUBREG
)
1053 arg0
= SUBREG_REG (arg0
), code0
= GET_CODE (arg0
);
1054 if (code1
== SUBREG
)
1055 arg1
= SUBREG_REG (arg1
), code1
= GET_CODE (arg1
);
1057 /* If this machine only allows one register per address, it
1058 must be in the first operand. */
1059 if (MAX_REGS_PER_ADDRESS
== 1)
1060 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1062 /* If index and base registers are the same on this machine,
1063 just record registers in any non-constant operands. We
1064 assume here, as well as in the tests below, that all
1065 addresses are in canonical form. */
1066 else if (INDEX_REG_CLASS
1067 == base_reg_class (VOIDmode
, as
, PLUS
, SCRATCH
))
1069 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1070 if (! CONSTANT_P (arg1
))
1071 record_address_regs (mode
, as
, arg1
, context
, PLUS
, code0
, scale
);
1074 /* If the second operand is a constant integer, it doesn't
1075 change what class the first operand must be. */
1076 else if (CONST_SCALAR_INT_P (arg1
))
1077 record_address_regs (mode
, as
, arg0
, context
, PLUS
, code1
, scale
);
1078 /* If the second operand is a symbolic constant, the first
1079 operand must be an index register. */
1080 else if (code1
== SYMBOL_REF
|| code1
== CONST
|| code1
== LABEL_REF
)
1081 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1082 /* If both operands are registers but one is already a hard
1083 register of index or reg-base class, give the other the
1084 class that the hard register is not. */
1085 else if (code0
== REG
&& code1
== REG
1086 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
1087 && (ok_for_base_p_nonstrict (arg0
, mode
, as
, PLUS
, REG
)
1088 || ok_for_index_p_nonstrict (arg0
)))
1089 record_address_regs (mode
, as
, arg1
,
1090 ok_for_base_p_nonstrict (arg0
, mode
, as
,
1093 else if (code0
== REG
&& code1
== REG
1094 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
1095 && (ok_for_base_p_nonstrict (arg1
, mode
, as
, PLUS
, REG
)
1096 || ok_for_index_p_nonstrict (arg1
)))
1097 record_address_regs (mode
, as
, arg0
,
1098 ok_for_base_p_nonstrict (arg1
, mode
, as
,
1101 /* If one operand is known to be a pointer, it must be the
1102 base with the other operand the index. Likewise if the
1103 other operand is a MULT. */
1104 else if ((code0
== REG
&& REG_POINTER (arg0
)) || code1
== MULT
)
1106 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
);
1107 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
);
1109 else if ((code1
== REG
&& REG_POINTER (arg1
)) || code0
== MULT
)
1111 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
);
1112 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
);
1114 /* Otherwise, count equal chances that each might be a base or
1115 index register. This case should be rare. */
1118 record_address_regs (mode
, as
, arg0
, 0, PLUS
, code1
, scale
/ 2);
1119 record_address_regs (mode
, as
, arg0
, 1, PLUS
, code1
, scale
/ 2);
1120 record_address_regs (mode
, as
, arg1
, 0, PLUS
, code0
, scale
/ 2);
1121 record_address_regs (mode
, as
, arg1
, 1, PLUS
, code0
, scale
/ 2);
1126 /* Double the importance of an allocno that is incremented or
1127 decremented, since it would take two extra insns if it ends
1128 up in the wrong place. */
1131 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
,
1132 GET_CODE (XEXP (XEXP (x
, 1), 1)), 2 * scale
);
1133 if (REG_P (XEXP (XEXP (x
, 1), 1)))
1134 record_address_regs (mode
, as
, XEXP (XEXP (x
, 1), 1), 1, code
, REG
,
1142 /* Double the importance of an allocno that is incremented or
1143 decremented, since it would take two extra insns if it ends
1144 up in the wrong place. */
1145 record_address_regs (mode
, as
, XEXP (x
, 0), 0, code
, SCRATCH
, 2 * scale
);
1153 int k
, regno
, add_cost
;
1154 cost_classes_t cost_classes_ptr
;
1155 enum reg_class
*cost_classes
;
1156 move_table
*move_in_cost
;
1158 if (REGNO (x
) < FIRST_PSEUDO_REGISTER
)
1163 ALLOCNO_BAD_SPILL_P (ira_curr_regno_allocno_map
[regno
]) = true;
1164 pp
= COSTS (costs
, COST_INDEX (regno
));
1165 add_cost
= (ira_memory_move_cost
[Pmode
][rclass
][1] * scale
) / 2;
1166 if (INT_MAX
- add_cost
< pp
->mem_cost
)
1167 pp
->mem_cost
= INT_MAX
;
1169 pp
->mem_cost
+= add_cost
;
1170 cost_classes_ptr
= regno_cost_classes
[regno
];
1171 cost_classes
= cost_classes_ptr
->classes
;
1172 pp_costs
= pp
->cost
;
1173 ira_init_register_move_cost_if_necessary (Pmode
);
1174 move_in_cost
= ira_may_move_in_cost
[Pmode
];
1175 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1177 i
= cost_classes
[k
];
1178 add_cost
= (move_in_cost
[i
][rclass
] * scale
) / 2;
1179 if (INT_MAX
- add_cost
< pp_costs
[k
])
1180 pp_costs
[k
] = INT_MAX
;
1182 pp_costs
[k
] += add_cost
;
1189 const char *fmt
= GET_RTX_FORMAT (code
);
1191 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1193 record_address_regs (mode
, as
, XEXP (x
, i
), context
, code
, SCRATCH
,
1201 /* Calculate the costs of insn operands. */
1203 record_operand_costs (rtx insn
, enum reg_class
*pref
)
1205 const char *constraints
[MAX_RECOG_OPERANDS
];
1206 enum machine_mode modes
[MAX_RECOG_OPERANDS
];
1207 rtx ops
[MAX_RECOG_OPERANDS
];
1211 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1213 constraints
[i
] = recog_data
.constraints
[i
];
1214 modes
[i
] = recog_data
.operand_mode
[i
];
1217 /* If we get here, we are set up to record the costs of all the
1218 operands for this insn. Start by initializing the costs. Then
1219 handle any address registers. Finally record the desired classes
1220 for any allocnos, doing it twice if some pair of operands are
1222 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1224 memcpy (op_costs
[i
], init_cost
, struct_costs_size
);
1226 ops
[i
] = recog_data
.operand
[i
];
1227 if (GET_CODE (recog_data
.operand
[i
]) == SUBREG
)
1228 recog_data
.operand
[i
] = SUBREG_REG (recog_data
.operand
[i
]);
1230 if (MEM_P (recog_data
.operand
[i
]))
1231 record_address_regs (GET_MODE (recog_data
.operand
[i
]),
1232 MEM_ADDR_SPACE (recog_data
.operand
[i
]),
1233 XEXP (recog_data
.operand
[i
], 0),
1234 0, MEM
, SCRATCH
, frequency
* 2);
1235 else if (constraints
[i
][0] == 'p'
1236 || EXTRA_ADDRESS_CONSTRAINT (constraints
[i
][0],
1238 record_address_regs (VOIDmode
, ADDR_SPACE_GENERIC
,
1239 recog_data
.operand
[i
], 0, ADDRESS
, SCRATCH
,
1243 /* Check for commutative in a separate loop so everything will have
1244 been initialized. We must do this even if one operand is a
1245 constant--see addsi3 in m68k.md. */
1246 for (i
= 0; i
< (int) recog_data
.n_operands
- 1; i
++)
1247 if (constraints
[i
][0] == '%')
1249 const char *xconstraints
[MAX_RECOG_OPERANDS
];
1252 /* Handle commutative operands by swapping the constraints.
1253 We assume the modes are the same. */
1254 for (j
= 0; j
< recog_data
.n_operands
; j
++)
1255 xconstraints
[j
] = constraints
[j
];
1257 xconstraints
[i
] = constraints
[i
+1];
1258 xconstraints
[i
+1] = constraints
[i
];
1259 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1260 recog_data
.operand
, modes
,
1261 xconstraints
, insn
, pref
);
1263 record_reg_classes (recog_data
.n_alternatives
, recog_data
.n_operands
,
1264 recog_data
.operand
, modes
,
1265 constraints
, insn
, pref
);
1267 /* If this insn is a single set copying operand 1 to operand 0 and
1268 one operand is an allocno with the other a hard reg or an allocno
1269 that prefers a hard register that is in its own register class
1270 then we may want to adjust the cost of that register class to -1.
1272 Avoid the adjustment if the source does not die to avoid
1273 stressing of register allocator by preferrencing two colliding
1274 registers into single class.
1276 Also avoid the adjustment if a copy between hard registers of the
1277 class is expensive (ten times the cost of a default copy is
1278 considered arbitrarily expensive). This avoids losing when the
1279 preferred class is very expensive as the source of a copy
1281 if ((set
= single_set (insn
)) != NULL_RTX
1282 /* In rare cases the single set insn might have less 2 operands
1283 as the source can be a fixed special reg. */
1284 && recog_data
.n_operands
> 1
1285 && ops
[0] == SET_DEST (set
) && ops
[1] == SET_SRC (set
))
1287 int regno
, other_regno
;
1288 rtx dest
= SET_DEST (set
);
1289 rtx src
= SET_SRC (set
);
1291 dest
= SET_DEST (set
);
1292 src
= SET_SRC (set
);
1293 if (GET_CODE (dest
) == SUBREG
1294 && (GET_MODE_SIZE (GET_MODE (dest
))
1295 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))))
1296 dest
= SUBREG_REG (dest
);
1297 if (GET_CODE (src
) == SUBREG
1298 && (GET_MODE_SIZE (GET_MODE (src
))
1299 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
1300 src
= SUBREG_REG (src
);
1301 if (REG_P (src
) && REG_P (dest
)
1302 && find_regno_note (insn
, REG_DEAD
, REGNO (src
))
1303 && (((regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
1304 && (other_regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
)
1305 || ((regno
= REGNO (dest
)) >= FIRST_PSEUDO_REGISTER
1306 && (other_regno
= REGNO (src
)) < FIRST_PSEUDO_REGISTER
)))
1308 enum machine_mode mode
= GET_MODE (src
);
1309 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1310 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1314 i
= regno
== (int) REGNO (src
) ? 1 : 0;
1315 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1317 rclass
= cost_classes
[k
];
1318 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], other_regno
)
1319 && (reg_class_size
[(int) rclass
]
1320 == ira_reg_class_max_nregs
[(int) rclass
][(int) mode
]))
1322 if (reg_class_size
[rclass
] == 1)
1323 op_costs
[i
]->cost
[k
] = -frequency
;
1327 nr
< hard_regno_nregs
[other_regno
][mode
];
1329 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
],
1333 if (nr
== hard_regno_nregs
[other_regno
][mode
])
1334 op_costs
[i
]->cost
[k
] = -frequency
;
1344 /* Process one insn INSN. Scan it and record each time it would save
1345 code to put a certain allocnos in a certain class. Return the last
1346 insn processed, so that the scan can be continued from there. */
1348 scan_one_insn (rtx insn
)
1350 enum rtx_code pat_code
;
1355 if (!NONDEBUG_INSN_P (insn
))
1358 pat_code
= GET_CODE (PATTERN (insn
));
1359 if (pat_code
== USE
|| pat_code
== CLOBBER
|| pat_code
== ASM_INPUT
)
1362 counted_mem
= false;
1363 set
= single_set (insn
);
1364 extract_insn (insn
);
1366 /* If this insn loads a parameter from its stack slot, then it
1367 represents a savings, rather than a cost, if the parameter is
1368 stored in memory. Record this fact.
1370 Similarly if we're loading other constants from memory (constant
1371 pool, TOC references, small data areas, etc) and this is the only
1372 assignment to the destination pseudo.
1374 Don't do this if SET_SRC (set) isn't a general operand, if it is
1375 a memory requiring special instructions to load it, decreasing
1376 mem_cost might result in it being loaded using the specialized
1377 instruction into a register, then stored into stack and loaded
1378 again from the stack. See PR52208.
1380 Don't do this if SET_SRC (set) has side effect. See PR56124. */
1381 if (set
!= 0 && REG_P (SET_DEST (set
)) && MEM_P (SET_SRC (set
))
1382 && (note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL_RTX
1383 && ((MEM_P (XEXP (note
, 0))
1384 && !side_effects_p (SET_SRC (set
)))
1385 || (CONSTANT_P (XEXP (note
, 0))
1386 && targetm
.legitimate_constant_p (GET_MODE (SET_DEST (set
)),
1388 && REG_N_SETS (REGNO (SET_DEST (set
))) == 1))
1389 && general_operand (SET_SRC (set
), GET_MODE (SET_SRC (set
))))
1391 enum reg_class cl
= GENERAL_REGS
;
1392 rtx reg
= SET_DEST (set
);
1393 int num
= COST_INDEX (REGNO (reg
));
1395 COSTS (costs
, num
)->mem_cost
1396 -= ira_memory_move_cost
[GET_MODE (reg
)][cl
][1] * frequency
;
1397 record_address_regs (GET_MODE (SET_SRC (set
)),
1398 MEM_ADDR_SPACE (SET_SRC (set
)),
1399 XEXP (SET_SRC (set
), 0), 0, MEM
, SCRATCH
,
1404 record_operand_costs (insn
, pref
);
1406 /* Now add the cost for each operand to the total costs for its
1408 for (i
= 0; i
< recog_data
.n_operands
; i
++)
1409 if (REG_P (recog_data
.operand
[i
])
1410 && REGNO (recog_data
.operand
[i
]) >= FIRST_PSEUDO_REGISTER
)
1412 int regno
= REGNO (recog_data
.operand
[i
]);
1413 struct costs
*p
= COSTS (costs
, COST_INDEX (regno
));
1414 struct costs
*q
= op_costs
[i
];
1415 int *p_costs
= p
->cost
, *q_costs
= q
->cost
;
1416 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1419 /* If the already accounted for the memory "cost" above, don't
1423 add_cost
= q
->mem_cost
;
1424 if (add_cost
> 0 && INT_MAX
- add_cost
< p
->mem_cost
)
1425 p
->mem_cost
= INT_MAX
;
1427 p
->mem_cost
+= add_cost
;
1429 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1431 add_cost
= q_costs
[k
];
1432 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1433 p_costs
[k
] = INT_MAX
;
1435 p_costs
[k
] += add_cost
;
1444 /* Print allocnos costs to file F. */
1446 print_allocno_costs (FILE *f
)
1450 ira_allocno_iterator ai
;
1452 ira_assert (allocno_p
);
1454 FOR_EACH_ALLOCNO (a
, ai
)
1458 int regno
= ALLOCNO_REGNO (a
);
1459 cost_classes_t cost_classes_ptr
= regno_cost_classes
[regno
];
1460 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1462 i
= ALLOCNO_NUM (a
);
1463 fprintf (f
, " a%d(r%d,", i
, regno
);
1464 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1465 fprintf (f
, "b%d", bb
->index
);
1467 fprintf (f
, "l%d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1468 fprintf (f
, ") costs:");
1469 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1471 rclass
= cost_classes
[k
];
1472 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1473 #ifdef CANNOT_CHANGE_MODE_CLASS
1474 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
)
1478 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1479 COSTS (costs
, i
)->cost
[k
]);
1480 if (flag_ira_region
== IRA_REGION_ALL
1481 || flag_ira_region
== IRA_REGION_MIXED
)
1482 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->cost
[k
]);
1485 fprintf (f
, " MEM:%i", COSTS (costs
, i
)->mem_cost
);
1486 if (flag_ira_region
== IRA_REGION_ALL
1487 || flag_ira_region
== IRA_REGION_MIXED
)
1488 fprintf (f
, ",%d", COSTS (total_allocno_costs
, i
)->mem_cost
);
1493 /* Print pseudo costs to file F. */
1495 print_pseudo_costs (FILE *f
)
1499 cost_classes_t cost_classes_ptr
;
1500 enum reg_class
*cost_classes
;
1502 ira_assert (! allocno_p
);
1504 for (regno
= max_reg_num () - 1; regno
>= FIRST_PSEUDO_REGISTER
; regno
--)
1506 if (REG_N_REFS (regno
) <= 0)
1508 cost_classes_ptr
= regno_cost_classes
[regno
];
1509 cost_classes
= cost_classes_ptr
->classes
;
1510 fprintf (f
, " r%d costs:", regno
);
1511 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1513 rclass
= cost_classes
[k
];
1514 if (contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (regno
)]
1515 #ifdef CANNOT_CHANGE_MODE_CLASS
1516 && ! invalid_mode_change_p (regno
, (enum reg_class
) rclass
)
1519 fprintf (f
, " %s:%d", reg_class_names
[rclass
],
1520 COSTS (costs
, regno
)->cost
[k
]);
1522 fprintf (f
, " MEM:%i\n", COSTS (costs
, regno
)->mem_cost
);
1526 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1529 process_bb_for_costs (basic_block bb
)
1533 frequency
= REG_FREQ_FROM_BB (bb
);
1536 FOR_BB_INSNS (bb
, insn
)
1537 insn
= scan_one_insn (insn
);
1540 /* Traverse the BB represented by LOOP_TREE_NODE to update the allocno
1543 process_bb_node_for_costs (ira_loop_tree_node_t loop_tree_node
)
1547 bb
= loop_tree_node
->bb
;
1549 process_bb_for_costs (bb
);
1552 /* Find costs of register classes and memory for allocnos or pseudos
1553 and their best costs. Set up preferred, alternative and allocno
1554 classes for pseudos. */
1556 find_costs_and_classes (FILE *dump_file
)
1558 int i
, k
, start
, max_cost_classes_num
;
1561 enum reg_class
*regno_best_class
;
1565 = (enum reg_class
*) ira_allocate (max_reg_num ()
1566 * sizeof (enum reg_class
));
1567 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1568 regno_best_class
[i
] = NO_REGS
;
1569 if (!resize_reg_info () && allocno_p
1570 && pseudo_classes_defined_p
&& flag_expensive_optimizations
)
1573 ira_allocno_iterator ai
;
1576 max_cost_classes_num
= 1;
1577 FOR_EACH_ALLOCNO (a
, ai
)
1579 pref
[ALLOCNO_NUM (a
)] = reg_preferred_class (ALLOCNO_REGNO (a
));
1580 setup_regno_cost_classes_by_aclass
1581 (ALLOCNO_REGNO (a
), pref
[ALLOCNO_NUM (a
)]);
1582 max_cost_classes_num
1583 = MAX (max_cost_classes_num
,
1584 regno_cost_classes
[ALLOCNO_REGNO (a
)]->num
);
1591 max_cost_classes_num
= ira_important_classes_num
;
1592 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1593 if (regno_reg_rtx
[i
] != NULL_RTX
)
1594 setup_regno_cost_classes_by_mode (i
, PSEUDO_REGNO_MODE (i
));
1596 setup_regno_cost_classes_by_aclass (i
, ALL_REGS
);
1600 /* Clear the flag for the next compiled function. */
1601 pseudo_classes_defined_p
= false;
1602 /* Normally we scan the insns once and determine the best class to
1603 use for each allocno. However, if -fexpensive-optimizations are
1604 on, we do so twice, the second time using the tentative best
1605 classes to guide the selection. */
1606 for (pass
= start
; pass
<= flag_expensive_optimizations
; pass
++)
1608 if ((!allocno_p
|| internal_flag_ira_verbose
> 0) && dump_file
)
1610 "\nPass %i for finding pseudo/allocno costs\n\n", pass
);
1614 max_cost_classes_num
= 1;
1615 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1617 setup_regno_cost_classes_by_aclass (i
, regno_best_class
[i
]);
1618 max_cost_classes_num
1619 = MAX (max_cost_classes_num
, regno_cost_classes
[i
]->num
);
1624 = sizeof (struct costs
) + sizeof (int) * (max_cost_classes_num
- 1);
1625 /* Zero out our accumulation of the cost of each class for each
1627 memset (costs
, 0, cost_elements_num
* struct_costs_size
);
1631 /* Scan the instructions and record each time it would save code
1632 to put a certain allocno in a certain class. */
1633 ira_traverse_loop_tree (true, ira_loop_tree_root
,
1634 process_bb_node_for_costs
, NULL
);
1636 memcpy (total_allocno_costs
, costs
,
1637 max_struct_costs_size
* ira_allocnos_num
);
1643 FOR_EACH_BB_FN (bb
, cfun
)
1644 process_bb_for_costs (bb
);
1650 /* Now for each allocno look at how desirable each class is and
1651 find which class is preferred. */
1652 for (i
= max_reg_num () - 1; i
>= FIRST_PSEUDO_REGISTER
; i
--)
1654 ira_allocno_t a
, parent_a
;
1655 int rclass
, a_num
, parent_a_num
, add_cost
;
1656 ira_loop_tree_node_t parent
;
1657 int best_cost
, allocno_cost
;
1658 enum reg_class best
, alt_class
;
1659 cost_classes_t cost_classes_ptr
= regno_cost_classes
[i
];
1660 enum reg_class
*cost_classes
= cost_classes_ptr
->classes
;
1661 int *i_costs
= temp_costs
->cost
;
1663 int equiv_savings
= regno_equiv_gains
[i
];
1667 if (regno_reg_rtx
[i
] == NULL_RTX
)
1669 memcpy (temp_costs
, COSTS (costs
, i
), struct_costs_size
);
1670 i_mem_cost
= temp_costs
->mem_cost
;
1674 if (ira_regno_allocno_map
[i
] == NULL
)
1676 memset (temp_costs
, 0, struct_costs_size
);
1678 /* Find cost of all allocnos with the same regno. */
1679 for (a
= ira_regno_allocno_map
[i
];
1681 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1683 int *a_costs
, *p_costs
;
1685 a_num
= ALLOCNO_NUM (a
);
1686 if ((flag_ira_region
== IRA_REGION_ALL
1687 || flag_ira_region
== IRA_REGION_MIXED
)
1688 && (parent
= ALLOCNO_LOOP_TREE_NODE (a
)->parent
) != NULL
1689 && (parent_a
= parent
->regno_allocno_map
[i
]) != NULL
1690 /* There are no caps yet. */
1691 && bitmap_bit_p (ALLOCNO_LOOP_TREE_NODE
1692 (a
)->border_allocnos
,
1695 /* Propagate costs to upper levels in the region
1697 parent_a_num
= ALLOCNO_NUM (parent_a
);
1698 a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1699 p_costs
= COSTS (total_allocno_costs
, parent_a_num
)->cost
;
1700 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1702 add_cost
= a_costs
[k
];
1703 if (add_cost
> 0 && INT_MAX
- add_cost
< p_costs
[k
])
1704 p_costs
[k
] = INT_MAX
;
1706 p_costs
[k
] += add_cost
;
1708 add_cost
= COSTS (total_allocno_costs
, a_num
)->mem_cost
;
1710 && (INT_MAX
- add_cost
1711 < COSTS (total_allocno_costs
,
1712 parent_a_num
)->mem_cost
))
1713 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1716 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
1719 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1720 COSTS (total_allocno_costs
, parent_a_num
)->mem_cost
= 0;
1722 a_costs
= COSTS (costs
, a_num
)->cost
;
1723 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1725 add_cost
= a_costs
[k
];
1726 if (add_cost
> 0 && INT_MAX
- add_cost
< i_costs
[k
])
1727 i_costs
[k
] = INT_MAX
;
1729 i_costs
[k
] += add_cost
;
1731 add_cost
= COSTS (costs
, a_num
)->mem_cost
;
1732 if (add_cost
> 0 && INT_MAX
- add_cost
< i_mem_cost
)
1733 i_mem_cost
= INT_MAX
;
1735 i_mem_cost
+= add_cost
;
1738 if (i
>= first_moveable_pseudo
&& i
< last_moveable_pseudo
)
1740 else if (equiv_savings
< 0)
1741 i_mem_cost
= -equiv_savings
;
1742 else if (equiv_savings
> 0)
1745 for (k
= cost_classes_ptr
->num
- 1; k
>= 0; k
--)
1746 i_costs
[k
] += equiv_savings
;
1749 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1751 alt_class
= NO_REGS
;
1752 /* Find best common class for all allocnos with the same
1754 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1756 rclass
= cost_classes
[k
];
1757 /* Ignore classes that are too small or invalid for this
1759 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1760 #ifdef CANNOT_CHANGE_MODE_CLASS
1761 || invalid_mode_change_p (i
, (enum reg_class
) rclass
)
1765 if (i_costs
[k
] < best_cost
)
1767 best_cost
= i_costs
[k
];
1768 best
= (enum reg_class
) rclass
;
1770 else if (i_costs
[k
] == best_cost
)
1771 best
= ira_reg_class_subunion
[best
][rclass
];
1772 if (pass
== flag_expensive_optimizations
1773 /* We still prefer registers to memory even at this
1774 stage if their costs are the same. We will make
1775 a final decision during assigning hard registers
1776 when we have all info including more accurate
1777 costs which might be affected by assigning hard
1778 registers to other pseudos because the pseudos
1779 involved in moves can be coalesced. */
1780 && i_costs
[k
] <= i_mem_cost
1781 && (reg_class_size
[reg_class_subunion
[alt_class
][rclass
]]
1782 > reg_class_size
[alt_class
]))
1783 alt_class
= reg_class_subunion
[alt_class
][rclass
];
1785 alt_class
= ira_allocno_class_translate
[alt_class
];
1786 if (best_cost
> i_mem_cost
)
1787 regno_aclass
[i
] = NO_REGS
;
1790 /* Make the common class the biggest class of best and
1793 = ira_reg_class_superunion
[best
][alt_class
];
1794 ira_assert (regno_aclass
[i
] != NO_REGS
1795 && ira_reg_allocno_class_p
[regno_aclass
[i
]]);
1797 if (pass
== flag_expensive_optimizations
)
1799 if (best_cost
> i_mem_cost
)
1800 best
= alt_class
= NO_REGS
;
1801 else if (best
== alt_class
)
1802 alt_class
= NO_REGS
;
1803 setup_reg_classes (i
, best
, alt_class
, regno_aclass
[i
]);
1804 if ((!allocno_p
|| internal_flag_ira_verbose
> 2)
1805 && dump_file
!= NULL
)
1807 " r%d: preferred %s, alternative %s, allocno %s\n",
1808 i
, reg_class_names
[best
], reg_class_names
[alt_class
],
1809 reg_class_names
[regno_aclass
[i
]]);
1811 regno_best_class
[i
] = best
;
1814 pref
[i
] = best_cost
> i_mem_cost
? NO_REGS
: best
;
1817 for (a
= ira_regno_allocno_map
[i
];
1819 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
1821 enum reg_class aclass
= regno_aclass
[i
];
1822 int a_num
= ALLOCNO_NUM (a
);
1823 int *total_a_costs
= COSTS (total_allocno_costs
, a_num
)->cost
;
1824 int *a_costs
= COSTS (costs
, a_num
)->cost
;
1826 if (aclass
== NO_REGS
)
1830 /* Finding best class which is subset of the common
1832 best_cost
= (1 << (HOST_BITS_PER_INT
- 2)) - 1;
1833 allocno_cost
= best_cost
;
1835 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1837 rclass
= cost_classes
[k
];
1838 if (! ira_class_subset_p
[rclass
][aclass
])
1840 /* Ignore classes that are too small or invalid
1841 for this operand. */
1842 if (! contains_reg_of_mode
[rclass
][PSEUDO_REGNO_MODE (i
)]
1843 #ifdef CANNOT_CHANGE_MODE_CLASS
1844 || invalid_mode_change_p (i
, (enum reg_class
) rclass
)
1848 else if (total_a_costs
[k
] < best_cost
)
1850 best_cost
= total_a_costs
[k
];
1851 allocno_cost
= a_costs
[k
];
1852 best
= (enum reg_class
) rclass
;
1854 else if (total_a_costs
[k
] == best_cost
)
1856 best
= ira_reg_class_subunion
[best
][rclass
];
1857 allocno_cost
= MAX (allocno_cost
, a_costs
[k
]);
1860 ALLOCNO_CLASS_COST (a
) = allocno_cost
;
1862 if (internal_flag_ira_verbose
> 2 && dump_file
!= NULL
1863 && (pass
== 0 || pref
[a_num
] != best
))
1865 fprintf (dump_file
, " a%d (r%d,", a_num
, i
);
1866 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
1867 fprintf (dump_file
, "b%d", bb
->index
);
1869 fprintf (dump_file
, "l%d",
1870 ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
1871 fprintf (dump_file
, ") best %s, allocno %s\n",
1872 reg_class_names
[best
],
1873 reg_class_names
[aclass
]);
1876 if (pass
== flag_expensive_optimizations
&& best
!= aclass
1877 && ira_class_hard_regs_num
[best
] > 0
1878 && (ira_reg_class_max_nregs
[best
][ALLOCNO_MODE (a
)]
1879 >= ira_class_hard_regs_num
[best
]))
1881 int ind
= cost_classes_ptr
->index
[aclass
];
1883 ira_assert (ind
>= 0);
1884 ira_init_register_move_cost_if_necessary (ALLOCNO_MODE (a
));
1885 ira_add_allocno_pref (a
, ira_class_hard_regs
[best
][0],
1886 (a_costs
[ind
] - ALLOCNO_CLASS_COST (a
))
1887 / (ira_register_move_cost
1888 [ALLOCNO_MODE (a
)][best
][aclass
]));
1889 for (k
= 0; k
< cost_classes_ptr
->num
; k
++)
1890 if (ira_class_subset_p
[cost_classes
[k
]][best
])
1891 a_costs
[k
] = a_costs
[ind
];
1896 if (internal_flag_ira_verbose
> 4 && dump_file
)
1899 print_allocno_costs (dump_file
);
1901 print_pseudo_costs (dump_file
);
1902 fprintf (dump_file
,"\n");
1905 ira_free (regno_best_class
);
1910 /* Process moves involving hard regs to modify allocno hard register
1911 costs. We can do this only after determining allocno class. If a
1912 hard register forms a register class, than moves with the hard
1913 register are already taken into account in class costs for the
1916 process_bb_node_for_hard_reg_moves (ira_loop_tree_node_t loop_tree_node
)
1918 int i
, freq
, src_regno
, dst_regno
, hard_regno
, a_regno
;
1920 ira_allocno_t a
, curr_a
;
1921 ira_loop_tree_node_t curr_loop_tree_node
;
1922 enum reg_class rclass
;
1924 rtx insn
, set
, src
, dst
;
1926 bb
= loop_tree_node
->bb
;
1929 freq
= REG_FREQ_FROM_BB (bb
);
1932 FOR_BB_INSNS (bb
, insn
)
1934 if (!NONDEBUG_INSN_P (insn
))
1936 set
= single_set (insn
);
1937 if (set
== NULL_RTX
)
1939 dst
= SET_DEST (set
);
1940 src
= SET_SRC (set
);
1941 if (! REG_P (dst
) || ! REG_P (src
))
1943 dst_regno
= REGNO (dst
);
1944 src_regno
= REGNO (src
);
1945 if (dst_regno
>= FIRST_PSEUDO_REGISTER
1946 && src_regno
< FIRST_PSEUDO_REGISTER
)
1948 hard_regno
= src_regno
;
1949 a
= ira_curr_regno_allocno_map
[dst_regno
];
1952 else if (src_regno
>= FIRST_PSEUDO_REGISTER
1953 && dst_regno
< FIRST_PSEUDO_REGISTER
)
1955 hard_regno
= dst_regno
;
1956 a
= ira_curr_regno_allocno_map
[src_regno
];
1961 rclass
= ALLOCNO_CLASS (a
);
1962 if (! TEST_HARD_REG_BIT (reg_class_contents
[rclass
], hard_regno
))
1964 i
= ira_class_hard_reg_index
[rclass
][hard_regno
];
1967 a_regno
= ALLOCNO_REGNO (a
);
1968 for (curr_loop_tree_node
= ALLOCNO_LOOP_TREE_NODE (a
);
1969 curr_loop_tree_node
!= NULL
;
1970 curr_loop_tree_node
= curr_loop_tree_node
->parent
)
1971 if ((curr_a
= curr_loop_tree_node
->regno_allocno_map
[a_regno
]) != NULL
)
1972 ira_add_allocno_pref (curr_a
, hard_regno
, freq
);
1975 enum reg_class hard_reg_class
;
1976 enum machine_mode mode
;
1978 mode
= ALLOCNO_MODE (a
);
1979 hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
1980 ira_init_register_move_cost_if_necessary (mode
);
1981 cost
= (to_p
? ira_register_move_cost
[mode
][hard_reg_class
][rclass
]
1982 : ira_register_move_cost
[mode
][rclass
][hard_reg_class
]) * freq
;
1983 ira_allocate_and_set_costs (&ALLOCNO_HARD_REG_COSTS (a
), rclass
,
1984 ALLOCNO_CLASS_COST (a
));
1985 ira_allocate_and_set_costs (&ALLOCNO_CONFLICT_HARD_REG_COSTS (a
),
1987 ALLOCNO_HARD_REG_COSTS (a
)[i
] -= cost
;
1988 ALLOCNO_CONFLICT_HARD_REG_COSTS (a
)[i
] -= cost
;
1989 ALLOCNO_CLASS_COST (a
) = MIN (ALLOCNO_CLASS_COST (a
),
1990 ALLOCNO_HARD_REG_COSTS (a
)[i
]);
1995 /* After we find hard register and memory costs for allocnos, define
1996 its class and modify hard register cost because insns moving
1997 allocno to/from hard registers. */
1999 setup_allocno_class_and_costs (void)
2001 int i
, j
, n
, regno
, hard_regno
, num
;
2003 enum reg_class aclass
, rclass
;
2005 ira_allocno_iterator ai
;
2006 cost_classes_t cost_classes_ptr
;
2008 ira_assert (allocno_p
);
2009 FOR_EACH_ALLOCNO (a
, ai
)
2011 i
= ALLOCNO_NUM (a
);
2012 regno
= ALLOCNO_REGNO (a
);
2013 aclass
= regno_aclass
[regno
];
2014 cost_classes_ptr
= regno_cost_classes
[regno
];
2015 ira_assert (pref
[i
] == NO_REGS
|| aclass
!= NO_REGS
);
2016 ALLOCNO_MEMORY_COST (a
) = COSTS (costs
, i
)->mem_cost
;
2017 ira_set_allocno_class (a
, aclass
);
2018 if (aclass
== NO_REGS
)
2020 if (optimize
&& ALLOCNO_CLASS (a
) != pref
[i
])
2022 n
= ira_class_hard_regs_num
[aclass
];
2023 ALLOCNO_HARD_REG_COSTS (a
)
2024 = reg_costs
= ira_allocate_cost_vector (aclass
);
2025 for (j
= n
- 1; j
>= 0; j
--)
2027 hard_regno
= ira_class_hard_regs
[aclass
][j
];
2028 if (TEST_HARD_REG_BIT (reg_class_contents
[pref
[i
]], hard_regno
))
2029 reg_costs
[j
] = ALLOCNO_CLASS_COST (a
);
2032 rclass
= REGNO_REG_CLASS (hard_regno
);
2033 num
= cost_classes_ptr
->index
[rclass
];
2036 num
= cost_classes_ptr
->hard_regno_index
[hard_regno
];
2037 ira_assert (num
>= 0);
2039 reg_costs
[j
] = COSTS (costs
, i
)->cost
[num
];
2045 ira_traverse_loop_tree (true, ira_loop_tree_root
,
2046 process_bb_node_for_hard_reg_moves
, NULL
);
2051 /* Function called once during compiler work. */
2053 ira_init_costs_once (void)
2058 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2061 this_op_costs
[i
] = NULL
;
2066 /* Free allocated temporary cost vectors. */
2068 free_ira_costs (void)
2074 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2077 free (this_op_costs
[i
]);
2078 op_costs
[i
] = this_op_costs
[i
] = NULL
;
2084 /* This is called each time register related information is
2087 ira_init_costs (void)
2092 max_struct_costs_size
2093 = sizeof (struct costs
) + sizeof (int) * (ira_important_classes_num
- 1);
2094 /* Don't use ira_allocate because vectors live through several IRA
2096 init_cost
= (struct costs
*) xmalloc (max_struct_costs_size
);
2097 init_cost
->mem_cost
= 1000000;
2098 for (i
= 0; i
< ira_important_classes_num
; i
++)
2099 init_cost
->cost
[i
] = 1000000;
2100 for (i
= 0; i
< MAX_RECOG_OPERANDS
; i
++)
2102 op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2103 this_op_costs
[i
] = (struct costs
*) xmalloc (max_struct_costs_size
);
2105 temp_costs
= (struct costs
*) xmalloc (max_struct_costs_size
);
2108 /* Function called once at the end of compiler work. */
2110 ira_finish_costs_once (void)
2117 /* Common initialization function for ira_costs and
2118 ira_set_pseudo_classes. */
2122 init_subregs_of_mode ();
2123 costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2124 * cost_elements_num
);
2125 pref_buffer
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2126 * cost_elements_num
);
2127 regno_aclass
= (enum reg_class
*) ira_allocate (sizeof (enum reg_class
)
2129 regno_equiv_gains
= (int *) ira_allocate (sizeof (int) * max_reg_num ());
2130 memset (regno_equiv_gains
, 0, sizeof (int) * max_reg_num ());
2133 /* Common finalization function for ira_costs and
2134 ira_set_pseudo_classes. */
2138 finish_subregs_of_mode ();
2139 ira_free (regno_equiv_gains
);
2140 ira_free (regno_aclass
);
2141 ira_free (pref_buffer
);
2145 /* Entry function which defines register class, memory and hard
2146 register costs for each allocno. */
2151 cost_elements_num
= ira_allocnos_num
;
2153 total_allocno_costs
= (struct costs
*) ira_allocate (max_struct_costs_size
2154 * ira_allocnos_num
);
2155 initiate_regno_cost_classes ();
2156 calculate_elim_costs_all_insns ();
2157 find_costs_and_classes (ira_dump_file
);
2158 setup_allocno_class_and_costs ();
2159 finish_regno_cost_classes ();
2161 ira_free (total_allocno_costs
);
2164 /* Entry function which defines classes for pseudos.
2165 Set pseudo_classes_defined_p only if DEFINE_PSEUDO_CLASSES is true. */
2167 ira_set_pseudo_classes (bool define_pseudo_classes
, FILE *dump_file
)
2170 internal_flag_ira_verbose
= flag_ira_verbose
;
2171 cost_elements_num
= max_reg_num ();
2173 initiate_regno_cost_classes ();
2174 find_costs_and_classes (dump_file
);
2175 finish_regno_cost_classes ();
2176 if (define_pseudo_classes
)
2177 pseudo_classes_defined_p
= true;
2184 /* Change hard register costs for allocnos which lives through
2185 function calls. This is called only when we found all intersected
2186 calls during building allocno live ranges. */
2188 ira_tune_allocno_costs (void)
2191 int cost
, min_cost
, *reg_costs
;
2192 enum reg_class aclass
, rclass
;
2193 enum machine_mode mode
;
2195 ira_allocno_iterator ai
;
2196 ira_allocno_object_iterator oi
;
2200 FOR_EACH_ALLOCNO (a
, ai
)
2202 aclass
= ALLOCNO_CLASS (a
);
2203 if (aclass
== NO_REGS
)
2205 mode
= ALLOCNO_MODE (a
);
2206 n
= ira_class_hard_regs_num
[aclass
];
2208 if (ALLOCNO_CALLS_CROSSED_NUM (a
)
2209 != ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2211 ira_allocate_and_set_costs
2212 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
,
2213 ALLOCNO_CLASS_COST (a
));
2214 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2215 for (j
= n
- 1; j
>= 0; j
--)
2217 regno
= ira_class_hard_regs
[aclass
][j
];
2219 FOR_EACH_ALLOCNO_OBJECT (a
, obj
, oi
)
2221 if (ira_hard_reg_set_intersection_p (regno
, mode
,
2222 OBJECT_CONFLICT_HARD_REGS
2231 rclass
= REGNO_REG_CLASS (regno
);
2233 if (ira_hard_reg_set_intersection_p (regno
, mode
, call_used_reg_set
)
2234 || HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
))
2235 cost
+= (ALLOCNO_CALL_FREQ (a
)
2236 * (ira_memory_move_cost
[mode
][rclass
][0]
2237 + ira_memory_move_cost
[mode
][rclass
][1]));
2238 #ifdef IRA_HARD_REGNO_ADD_COST_MULTIPLIER
2239 cost
+= ((ira_memory_move_cost
[mode
][rclass
][0]
2240 + ira_memory_move_cost
[mode
][rclass
][1])
2242 * IRA_HARD_REGNO_ADD_COST_MULTIPLIER (regno
) / 2);
2244 if (INT_MAX
- cost
< reg_costs
[j
])
2245 reg_costs
[j
] = INT_MAX
;
2247 reg_costs
[j
] += cost
;
2248 if (min_cost
> reg_costs
[j
])
2249 min_cost
= reg_costs
[j
];
2252 if (min_cost
!= INT_MAX
)
2253 ALLOCNO_CLASS_COST (a
) = min_cost
;
2255 /* Some targets allow pseudos to be allocated to unaligned sequences
2256 of hard registers. However, selecting an unaligned sequence can
2257 unnecessarily restrict later allocations. So increase the cost of
2258 unaligned hard regs to encourage the use of aligned hard regs. */
2260 const int nregs
= ira_reg_class_max_nregs
[aclass
][ALLOCNO_MODE (a
)];
2264 ira_allocate_and_set_costs
2265 (&ALLOCNO_HARD_REG_COSTS (a
), aclass
, ALLOCNO_CLASS_COST (a
));
2266 reg_costs
= ALLOCNO_HARD_REG_COSTS (a
);
2267 for (j
= n
- 1; j
>= 0; j
--)
2269 regno
= ira_non_ordered_class_hard_regs
[aclass
][j
];
2270 if ((regno
% nregs
) != 0)
2272 int index
= ira_class_hard_reg_index
[aclass
][regno
];
2273 ira_assert (index
!= -1);
2274 reg_costs
[index
] += ALLOCNO_FREQ (a
);
2282 /* Add COST to the estimated gain for eliminating REGNO with its
2283 equivalence. If COST is zero, record that no such elimination is
2287 ira_adjust_equiv_reg_cost (unsigned regno
, int cost
)
2290 regno_equiv_gains
[regno
] = 0;
2292 regno_equiv_gains
[regno
] += cost
;