1 /* IRA processing allocno lives to build allocno live ranges.
2 Copyright (C) 2006-2015 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
30 #include "insn-config.h"
34 #include "diagnostic-core.h"
38 #include "sparseset.h"
41 /* The code in this file is similar to one in global but the code
42 works on the allocno basis and creates live ranges instead of
43 pseudo-register conflicts. */
45 /* Program points are enumerated by numbers from range
46 0..IRA_MAX_POINT-1. There are approximately two times more program
47 points than insns. Program points are places in the program where
48 liveness info can be changed. In most general case (there are more
49 complicated cases too) some program points correspond to places
50 where input operand dies and other ones correspond to places where
51 output operands are born. */
54 /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
55 live ranges with given start/finish point. */
56 live_range_t
*ira_start_point_ranges
, *ira_finish_point_ranges
;
58 /* Number of the current program point. */
59 static int curr_point
;
61 /* Point where register pressure excess started or -1 if there is no
62 register pressure excess. Excess pressure for a register class at
63 some point means that there are more allocnos of given register
64 class living at the point than number of hard-registers of the
65 class available for the allocation. It is defined only for
67 static int high_pressure_start_point
[N_REG_CLASSES
];
69 /* Objects live at current point in the scan. */
70 static sparseset objects_live
;
72 /* A temporary bitmap used in functions that wish to avoid visiting an allocno
74 static sparseset allocnos_processed
;
76 /* Set of hard regs (except eliminable ones) currently live. */
77 static HARD_REG_SET hard_regs_live
;
79 /* The loop tree node corresponding to the current basic block. */
80 static ira_loop_tree_node_t curr_bb_node
;
82 /* The number of the last processed call. */
83 static int last_call_num
;
84 /* The number of last call at which given allocno was saved. */
85 static int *allocno_saved_at_call
;
87 /* The value of get_preferred_alternatives for the current instruction,
88 supplemental to recog_data. */
89 static alternative_mask preferred_alternatives
;
91 /* Record the birth of hard register REGNO, updating hard_regs_live and
92 hard reg conflict information for living allocnos. */
94 make_hard_regno_born (int regno
)
98 SET_HARD_REG_BIT (hard_regs_live
, regno
);
99 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
101 ira_object_t obj
= ira_object_id_map
[i
];
103 SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj
), regno
);
104 SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
);
108 /* Process the death of hard register REGNO. This updates
111 make_hard_regno_dead (int regno
)
113 CLEAR_HARD_REG_BIT (hard_regs_live
, regno
);
116 /* Record the birth of object OBJ. Set a bit for it in objects_live,
117 start a new live range for it if necessary and update hard register
120 make_object_born (ira_object_t obj
)
122 live_range_t lr
= OBJECT_LIVE_RANGES (obj
);
124 sparseset_set_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
125 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
126 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
129 || (lr
->finish
!= curr_point
&& lr
->finish
+ 1 != curr_point
))
130 ira_add_live_range_to_object (obj
, curr_point
, -1);
133 /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
134 associated with object OBJ. */
136 update_allocno_pressure_excess_length (ira_object_t obj
)
138 ira_allocno_t a
= OBJECT_ALLOCNO (obj
);
140 enum reg_class aclass
, pclass
, cl
;
143 aclass
= ALLOCNO_CLASS (a
);
144 pclass
= ira_pressure_class_translate
[aclass
];
146 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
149 if (! ira_reg_pressure_class_p
[cl
])
151 if (high_pressure_start_point
[cl
] < 0)
153 p
= OBJECT_LIVE_RANGES (obj
);
154 ira_assert (p
!= NULL
);
155 start
= (high_pressure_start_point
[cl
] > p
->start
156 ? high_pressure_start_point
[cl
] : p
->start
);
157 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a
) += curr_point
- start
+ 1;
161 /* Process the death of object OBJ, which is associated with allocno
162 A. This finishes the current live range for it. */
164 make_object_dead (ira_object_t obj
)
168 sparseset_clear_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
169 lr
= OBJECT_LIVE_RANGES (obj
);
170 ira_assert (lr
!= NULL
);
171 lr
->finish
= curr_point
;
172 update_allocno_pressure_excess_length (obj
);
175 /* The current register pressures for each pressure class for the current
177 static int curr_reg_pressure
[N_REG_CLASSES
];
179 /* Record that register pressure for PCLASS increased by N registers.
180 Update the current register pressure, maximal register pressure for
181 the current BB and the start point of the register pressure
184 inc_register_pressure (enum reg_class pclass
, int n
)
190 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
193 if (! ira_reg_pressure_class_p
[cl
])
195 curr_reg_pressure
[cl
] += n
;
196 if (high_pressure_start_point
[cl
] < 0
197 && (curr_reg_pressure
[cl
] > ira_class_hard_regs_num
[cl
]))
198 high_pressure_start_point
[cl
] = curr_point
;
199 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
200 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
204 /* Record that register pressure for PCLASS has decreased by NREGS
205 registers; update current register pressure, start point of the
206 register pressure excess, and register pressure excess length for
210 dec_register_pressure (enum reg_class pclass
, int nregs
)
218 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
221 if (! ira_reg_pressure_class_p
[cl
])
223 curr_reg_pressure
[cl
] -= nregs
;
224 ira_assert (curr_reg_pressure
[cl
] >= 0);
225 if (high_pressure_start_point
[cl
] >= 0
226 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
231 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, j
)
232 update_allocno_pressure_excess_length (ira_object_id_map
[j
]);
234 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
237 if (! ira_reg_pressure_class_p
[cl
])
239 if (high_pressure_start_point
[cl
] >= 0
240 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
241 high_pressure_start_point
[cl
] = -1;
246 /* Determine from the objects_live bitmap whether REGNO is currently live,
247 and occupies only one object. Return false if we have no information. */
249 pseudo_regno_single_word_and_live_p (int regno
)
251 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
256 if (ALLOCNO_NUM_OBJECTS (a
) > 1)
259 obj
= ALLOCNO_OBJECT (a
, 0);
261 return sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
));
264 /* Mark the pseudo register REGNO as live. Update all information about
265 live ranges and register pressure. */
267 mark_pseudo_regno_live (int regno
)
269 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
270 enum reg_class pclass
;
276 /* Invalidate because it is referenced. */
277 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
279 n
= ALLOCNO_NUM_OBJECTS (a
);
280 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
281 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
284 /* We track every subobject separately. */
285 gcc_assert (nregs
== n
);
289 for (i
= 0; i
< n
; i
++)
291 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
293 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
296 inc_register_pressure (pclass
, nregs
);
297 make_object_born (obj
);
301 /* Like mark_pseudo_regno_live, but try to only mark one subword of
302 the pseudo as live. SUBWORD indicates which; a value of 0
303 indicates the low part. */
305 mark_pseudo_regno_subword_live (int regno
, int subword
)
307 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
309 enum reg_class pclass
;
315 /* Invalidate because it is referenced. */
316 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
318 n
= ALLOCNO_NUM_OBJECTS (a
);
321 mark_pseudo_regno_live (regno
);
325 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
327 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
328 obj
= ALLOCNO_OBJECT (a
, subword
);
330 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
333 inc_register_pressure (pclass
, 1);
334 make_object_born (obj
);
337 /* Mark the register REG as live. Store a 1 in hard_regs_live for
338 this register, record how many consecutive hardware registers it
341 mark_hard_reg_live (rtx reg
)
343 int regno
= REGNO (reg
);
345 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
347 int last
= END_REGNO (reg
);
348 enum reg_class aclass
, pclass
;
352 if (! TEST_HARD_REG_BIT (hard_regs_live
, regno
)
353 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
355 aclass
= ira_hard_regno_allocno_class
[regno
];
356 pclass
= ira_pressure_class_translate
[aclass
];
357 inc_register_pressure (pclass
, 1);
358 make_hard_regno_born (regno
);
365 /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
366 register number; ORIG_REG is the access in the insn, which may be a
369 mark_pseudo_reg_live (rtx orig_reg
, unsigned regno
)
371 if (df_read_modify_subreg_p (orig_reg
))
373 mark_pseudo_regno_subword_live (regno
,
374 subreg_lowpart_p (orig_reg
) ? 0 : 1);
377 mark_pseudo_regno_live (regno
);
380 /* Mark the register referenced by use or def REF as live. */
382 mark_ref_live (df_ref ref
)
384 rtx reg
= DF_REF_REG (ref
);
387 if (GET_CODE (reg
) == SUBREG
)
388 reg
= SUBREG_REG (reg
);
390 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
391 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
393 mark_hard_reg_live (reg
);
396 /* Mark the pseudo register REGNO as dead. Update all information about
397 live ranges and register pressure. */
399 mark_pseudo_regno_dead (int regno
)
401 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
408 /* Invalidate because it is referenced. */
409 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
411 n
= ALLOCNO_NUM_OBJECTS (a
);
412 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
413 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
416 /* We track every subobject separately. */
417 gcc_assert (nregs
== n
);
420 for (i
= 0; i
< n
; i
++)
422 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
423 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
426 dec_register_pressure (cl
, nregs
);
427 make_object_dead (obj
);
431 /* Like mark_pseudo_regno_dead, but called when we know that only part of the
432 register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
434 mark_pseudo_regno_subword_dead (int regno
, int subword
)
436 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
444 /* Invalidate because it is referenced. */
445 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
447 n
= ALLOCNO_NUM_OBJECTS (a
);
449 /* The allocno as a whole doesn't die in this case. */
452 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
454 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
456 obj
= ALLOCNO_OBJECT (a
, subword
);
457 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
460 dec_register_pressure (cl
, 1);
461 make_object_dead (obj
);
464 /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the
467 mark_hard_reg_dead (rtx reg
)
469 int regno
= REGNO (reg
);
471 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
473 int last
= END_REGNO (reg
);
474 enum reg_class aclass
, pclass
;
478 if (TEST_HARD_REG_BIT (hard_regs_live
, regno
))
480 aclass
= ira_hard_regno_allocno_class
[regno
];
481 pclass
= ira_pressure_class_translate
[aclass
];
482 dec_register_pressure (pclass
, 1);
483 make_hard_regno_dead (regno
);
490 /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
491 register number; ORIG_REG is the access in the insn, which may be a
494 mark_pseudo_reg_dead (rtx orig_reg
, unsigned regno
)
496 if (df_read_modify_subreg_p (orig_reg
))
498 mark_pseudo_regno_subword_dead (regno
,
499 subreg_lowpart_p (orig_reg
) ? 0 : 1);
502 mark_pseudo_regno_dead (regno
);
505 /* Mark the register referenced by definition DEF as dead, if the
506 definition is a total one. */
508 mark_ref_dead (df_ref def
)
510 rtx reg
= DF_REF_REG (def
);
513 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
))
516 if (GET_CODE (reg
) == SUBREG
)
517 reg
= SUBREG_REG (reg
);
519 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
)
520 && (GET_CODE (orig_reg
) != SUBREG
521 || REGNO (reg
) < FIRST_PSEUDO_REGISTER
522 || !df_read_modify_subreg_p (orig_reg
)))
525 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
526 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
528 mark_hard_reg_dead (reg
);
531 /* If REG is a pseudo or a subreg of it, and the class of its allocno
532 intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
533 rtx actually accessed, it may be identical to DREG or a subreg of it.
534 Advance the current program point before making the conflict if
535 ADVANCE_P. Return TRUE if we will need to advance the current
538 make_pseudo_conflict (rtx reg
, enum reg_class cl
, rtx dreg
, rtx orig_dreg
,
544 if (GET_CODE (reg
) == SUBREG
)
545 reg
= SUBREG_REG (reg
);
547 if (! REG_P (reg
) || REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
550 a
= ira_curr_regno_allocno_map
[REGNO (reg
)];
551 if (! reg_classes_intersect_p (cl
, ALLOCNO_CLASS (a
)))
557 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
558 mark_pseudo_reg_live (orig_dreg
, REGNO (dreg
));
559 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
560 mark_pseudo_reg_dead (orig_dreg
, REGNO (dreg
));
565 /* Check and make if necessary conflicts for pseudo DREG of class
566 DEF_CL of the current insn with input operand USE of class USE_CL.
567 ORIG_DREG is the rtx actually accessed, it may be identical to
568 DREG or a subreg of it. Advance the current program point before
569 making the conflict if ADVANCE_P. Return TRUE if we will need to
570 advance the current program point. */
572 check_and_make_def_use_conflict (rtx dreg
, rtx orig_dreg
,
573 enum reg_class def_cl
, int use
,
574 enum reg_class use_cl
, bool advance_p
)
576 if (! reg_classes_intersect_p (def_cl
, use_cl
))
579 advance_p
= make_pseudo_conflict (recog_data
.operand
[use
],
580 use_cl
, dreg
, orig_dreg
, advance_p
);
582 /* Reload may end up swapping commutative operands, so you
583 have to take both orderings into account. The
584 constraints for the two operands can be completely
585 different. (Indeed, if the constraints for the two
586 operands are the same for all alternatives, there's no
587 point marking them as commutative.) */
588 if (use
< recog_data
.n_operands
- 1
589 && recog_data
.constraints
[use
][0] == '%')
591 = make_pseudo_conflict (recog_data
.operand
[use
+ 1],
592 use_cl
, dreg
, orig_dreg
, advance_p
);
594 && recog_data
.constraints
[use
- 1][0] == '%')
596 = make_pseudo_conflict (recog_data
.operand
[use
- 1],
597 use_cl
, dreg
, orig_dreg
, advance_p
);
601 /* Check and make if necessary conflicts for definition DEF of class
602 DEF_CL of the current insn with input operands. Process only
603 constraints of alternative ALT. */
605 check_and_make_def_conflict (int alt
, int def
, enum reg_class def_cl
)
609 enum reg_class use_cl
, acl
;
611 rtx dreg
= recog_data
.operand
[def
];
612 rtx orig_dreg
= dreg
;
614 if (def_cl
== NO_REGS
)
617 if (GET_CODE (dreg
) == SUBREG
)
618 dreg
= SUBREG_REG (dreg
);
620 if (! REG_P (dreg
) || REGNO (dreg
) < FIRST_PSEUDO_REGISTER
)
623 a
= ira_curr_regno_allocno_map
[REGNO (dreg
)];
624 acl
= ALLOCNO_CLASS (a
);
625 if (! reg_classes_intersect_p (acl
, def_cl
))
630 int n_operands
= recog_data
.n_operands
;
631 const operand_alternative
*op_alt
= &recog_op_alt
[alt
* n_operands
];
632 for (use
= 0; use
< n_operands
; use
++)
636 if (use
== def
|| recog_data
.operand_type
[use
] == OP_OUT
)
639 if (op_alt
[use
].anything_ok
)
642 use_cl
= op_alt
[use
].cl
;
644 /* If there's any alternative that allows USE to match DEF, do not
645 record a conflict. If that causes us to create an invalid
646 instruction due to the earlyclobber, reload must fix it up. */
647 for (alt1
= 0; alt1
< recog_data
.n_alternatives
; alt1
++)
649 if (!TEST_BIT (preferred_alternatives
, alt1
))
651 const operand_alternative
*op_alt1
652 = &recog_op_alt
[alt1
* n_operands
];
653 if (op_alt1
[use
].matches
== def
654 || (use
< n_operands
- 1
655 && recog_data
.constraints
[use
][0] == '%'
656 && op_alt1
[use
+ 1].matches
== def
)
658 && recog_data
.constraints
[use
- 1][0] == '%'
659 && op_alt1
[use
- 1].matches
== def
))
663 if (alt1
< recog_data
.n_alternatives
)
666 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
667 use
, use_cl
, advance_p
);
669 if ((use_match
= op_alt
[use
].matches
) >= 0)
671 if (use_match
== def
)
674 if (op_alt
[use_match
].anything_ok
)
677 use_cl
= op_alt
[use_match
].cl
;
678 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
679 use
, use_cl
, advance_p
);
684 /* Make conflicts of early clobber pseudo registers of the current
685 insn with its inputs. Avoid introducing unnecessary conflicts by
686 checking classes of the constraints and pseudos because otherwise
687 significant code degradation is possible for some targets. */
689 make_early_clobber_and_input_conflicts (void)
693 enum reg_class def_cl
;
695 int n_alternatives
= recog_data
.n_alternatives
;
696 int n_operands
= recog_data
.n_operands
;
697 const operand_alternative
*op_alt
= recog_op_alt
;
698 for (alt
= 0; alt
< n_alternatives
; alt
++, op_alt
+= n_operands
)
699 if (TEST_BIT (preferred_alternatives
, alt
))
700 for (def
= 0; def
< n_operands
; def
++)
703 if (op_alt
[def
].earlyclobber
)
705 if (op_alt
[def
].anything_ok
)
708 def_cl
= op_alt
[def
].cl
;
709 check_and_make_def_conflict (alt
, def
, def_cl
);
711 if ((def_match
= op_alt
[def
].matches
) >= 0
712 && (op_alt
[def_match
].earlyclobber
713 || op_alt
[def
].earlyclobber
))
715 if (op_alt
[def_match
].anything_ok
)
718 def_cl
= op_alt
[def_match
].cl
;
719 check_and_make_def_conflict (alt
, def
, def_cl
);
724 /* Mark early clobber hard registers of the current INSN as live (if
725 LIVE_P) or dead. Return true if there are such registers. */
727 mark_hard_reg_early_clobbers (rtx_insn
*insn
, bool live_p
)
732 FOR_EACH_INSN_DEF (def
, insn
)
733 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_MUST_CLOBBER
))
735 rtx dreg
= DF_REF_REG (def
);
737 if (GET_CODE (dreg
) == SUBREG
)
738 dreg
= SUBREG_REG (dreg
);
739 if (! REG_P (dreg
) || REGNO (dreg
) >= FIRST_PSEUDO_REGISTER
)
742 /* Hard register clobbers are believed to be early clobber
743 because there is no way to say that non-operand hard
744 register clobbers are not early ones. */
755 /* Checks that CONSTRAINTS permits to use only one hard register. If
756 it is so, the function returns the class of the hard register.
757 Otherwise it returns NO_REGS. */
758 static enum reg_class
759 single_reg_class (const char *constraints
, rtx op
, rtx equiv_const
)
762 enum reg_class cl
, next_cl
;
763 enum constraint_num cn
;
766 alternative_mask preferred
= preferred_alternatives
;
767 for (; (c
= *constraints
); constraints
+= CONSTRAINT_LEN (c
, constraints
))
769 preferred
&= ~ALTERNATIVE_BIT (0);
772 else if (preferred
& 1)
779 /* ??? Is this the best way to handle memory constraints? */
780 cn
= lookup_constraint (constraints
);
781 if (insn_extra_memory_constraint (cn
)
782 || insn_extra_address_constraint (cn
))
784 if (constraint_satisfied_p (op
, cn
)
785 || (equiv_const
!= NULL_RTX
786 && CONSTANT_P (equiv_const
)
787 && constraint_satisfied_p (equiv_const
, cn
)))
789 next_cl
= reg_class_for_constraint (cn
);
790 if (next_cl
== NO_REGS
)
793 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
794 : (ira_class_singleton
[cl
][GET_MODE (op
)]
795 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
800 case '0': case '1': case '2': case '3': case '4':
801 case '5': case '6': case '7': case '8': case '9':
803 = single_reg_class (recog_data
.constraints
[c
- '0'],
804 recog_data
.operand
[c
- '0'], NULL_RTX
);
806 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
807 : (ira_class_singleton
[cl
][GET_MODE (op
)]
808 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
816 /* The function checks that operand OP_NUM of the current insn can use
817 only one hard register. If it is so, the function returns the
818 class of the hard register. Otherwise it returns NO_REGS. */
819 static enum reg_class
820 single_reg_operand_class (int op_num
)
822 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
824 return single_reg_class (recog_data
.constraints
[op_num
],
825 recog_data
.operand
[op_num
], NULL_RTX
);
828 /* The function sets up hard register set *SET to hard registers which
829 might be used by insn reloads because the constraints are too
832 ira_implicitly_set_insn_hard_regs (HARD_REG_SET
*set
,
833 alternative_mask preferred
)
840 CLEAR_HARD_REG_SET (*set
);
841 for (i
= 0; i
< recog_data
.n_operands
; i
++)
843 op
= recog_data
.operand
[i
];
845 if (GET_CODE (op
) == SUBREG
)
846 op
= SUBREG_REG (op
);
848 if (GET_CODE (op
) == SCRATCH
849 || (REG_P (op
) && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
))
851 const char *p
= recog_data
.constraints
[i
];
853 mode
= (GET_CODE (op
) == SCRATCH
854 ? GET_MODE (op
) : PSEUDO_REGNO_MODE (regno
));
856 for (; (c
= *p
); p
+= CONSTRAINT_LEN (c
, p
))
858 preferred
&= ~ALTERNATIVE_BIT (0);
861 else if (preferred
& 1)
863 cl
= reg_class_for_constraint (lookup_constraint (p
));
866 /* There is no register pressure problem if all of the
867 regs in this class are fixed. */
868 int regno
= ira_class_singleton
[cl
][mode
];
870 add_to_hard_reg_set (set
, mode
, regno
);
876 /* Processes input operands, if IN_P, or output operands otherwise of
877 the current insn with FREQ to find allocno which can use only one
878 hard register and makes other currently living allocnos conflicting
879 with the hard register. */
881 process_single_reg_class_operands (bool in_p
, int freq
)
887 ira_allocno_t operand_a
, a
;
889 for (i
= 0; i
< recog_data
.n_operands
; i
++)
891 operand
= recog_data
.operand
[i
];
892 if (in_p
&& recog_data
.operand_type
[i
] != OP_IN
893 && recog_data
.operand_type
[i
] != OP_INOUT
)
895 if (! in_p
&& recog_data
.operand_type
[i
] != OP_OUT
896 && recog_data
.operand_type
[i
] != OP_INOUT
)
898 cl
= single_reg_operand_class (i
);
904 if (GET_CODE (operand
) == SUBREG
)
905 operand
= SUBREG_REG (operand
);
908 && (regno
= REGNO (operand
)) >= FIRST_PSEUDO_REGISTER
)
910 enum reg_class aclass
;
912 operand_a
= ira_curr_regno_allocno_map
[regno
];
913 aclass
= ALLOCNO_CLASS (operand_a
);
914 if (ira_class_subset_p
[cl
][aclass
])
916 /* View the desired allocation of OPERAND as:
922 (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
923 machine_mode ymode
, xmode
;
925 HOST_WIDE_INT offset
;
927 xmode
= recog_data
.operand_mode
[i
];
928 xregno
= ira_class_singleton
[cl
][xmode
];
929 gcc_assert (xregno
>= 0);
930 ymode
= ALLOCNO_MODE (operand_a
);
931 offset
= subreg_lowpart_offset (ymode
, xmode
);
932 yregno
= simplify_subreg_regno (xregno
, xmode
, offset
, ymode
);
934 && ira_class_hard_reg_index
[aclass
][yregno
] >= 0)
938 ira_allocate_and_set_costs
939 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
),
941 ira_init_register_move_cost_if_necessary (xmode
);
943 ? ira_register_move_cost
[xmode
][aclass
][cl
]
944 : ira_register_move_cost
[xmode
][cl
][aclass
]);
945 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
)
946 [ira_class_hard_reg_index
[aclass
][yregno
]] -= cost
;
951 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
953 ira_object_t obj
= ira_object_id_map
[px
];
954 a
= OBJECT_ALLOCNO (obj
);
957 /* We could increase costs of A instead of making it
958 conflicting with the hard register. But it works worse
959 because it will be spilled in reload in anyway. */
960 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
961 reg_class_contents
[cl
]);
962 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
963 reg_class_contents
[cl
]);
969 /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
970 we find a SET rtx that we can use to deduce that a register can be cheaply
971 caller-saved. Return such a register, or NULL_RTX if none is found. */
973 find_call_crossed_cheap_reg (rtx_insn
*insn
)
975 rtx cheap_reg
= NULL_RTX
;
976 rtx exp
= CALL_INSN_FUNCTION_USAGE (insn
);
980 rtx x
= XEXP (exp
, 0);
981 if (GET_CODE (x
) == SET
)
990 basic_block bb
= BLOCK_FOR_INSN (insn
);
991 rtx reg
= SET_SRC (exp
);
992 rtx_insn
*prev
= PREV_INSN (insn
);
993 while (prev
&& !(INSN_P (prev
)
994 && BLOCK_FOR_INSN (prev
) != bb
))
996 if (NONDEBUG_INSN_P (prev
))
998 rtx set
= single_set (prev
);
1000 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
1002 rtx src
= SET_SRC (set
);
1003 if (!REG_P (src
) || HARD_REGISTER_P (src
)
1004 || !pseudo_regno_single_word_and_live_p (REGNO (src
)))
1006 if (!modified_between_p (src
, prev
, insn
))
1010 if (set
&& rtx_equal_p (SET_SRC (set
), reg
))
1012 rtx dest
= SET_DEST (set
);
1013 if (!REG_P (dest
) || HARD_REGISTER_P (dest
)
1014 || !pseudo_regno_single_word_and_live_p (REGNO (dest
)))
1016 if (!modified_between_p (dest
, prev
, insn
))
1021 if (reg_overlap_mentioned_p (reg
, PATTERN (prev
)))
1024 prev
= PREV_INSN (prev
);
1030 /* Process insns of the basic block given by its LOOP_TREE_NODE to
1031 update allocno live ranges, allocno hard register conflicts,
1032 intersected calls, and register pressure info for allocnos for the
1033 basic block for and regions containing the basic block. */
1035 process_bb_node_lives (ira_loop_tree_node_t loop_tree_node
)
1042 bitmap reg_live_out
;
1046 bb
= loop_tree_node
->bb
;
1049 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1051 curr_reg_pressure
[ira_pressure_classes
[i
]] = 0;
1052 high_pressure_start_point
[ira_pressure_classes
[i
]] = -1;
1054 curr_bb_node
= loop_tree_node
;
1055 reg_live_out
= df_get_live_out (bb
);
1056 sparseset_clear (objects_live
);
1057 REG_SET_TO_HARD_REG_SET (hard_regs_live
, reg_live_out
);
1058 AND_COMPL_HARD_REG_SET (hard_regs_live
, eliminable_regset
);
1059 AND_COMPL_HARD_REG_SET (hard_regs_live
, ira_no_alloc_regs
);
1060 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1061 if (TEST_HARD_REG_BIT (hard_regs_live
, i
))
1063 enum reg_class aclass
, pclass
, cl
;
1065 aclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (i
)];
1066 pclass
= ira_pressure_class_translate
[aclass
];
1068 (cl
= ira_reg_class_super_classes
[pclass
][j
])
1072 if (! ira_reg_pressure_class_p
[cl
])
1074 curr_reg_pressure
[cl
]++;
1075 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
1076 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
1077 ira_assert (curr_reg_pressure
[cl
]
1078 <= ira_class_hard_regs_num
[cl
]);
1081 EXECUTE_IF_SET_IN_BITMAP (reg_live_out
, FIRST_PSEUDO_REGISTER
, j
, bi
)
1082 mark_pseudo_regno_live (j
);
1084 freq
= REG_FREQ_FROM_BB (bb
);
1088 /* Invalidate all allocno_saved_at_call entries. */
1091 /* Scan the code of this basic block, noting which allocnos and
1092 hard regs are born or die.
1094 Note that this loop treats uninitialized values as live until
1095 the beginning of the block. For example, if an instruction
1096 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1097 set, FOO will remain live until the beginning of the block.
1098 Likewise if FOO is not set at all. This is unnecessarily
1099 pessimistic, but it probably doesn't matter much in practice. */
1100 FOR_BB_INSNS_REVERSE (bb
, insn
)
1106 if (!NONDEBUG_INSN_P (insn
))
1109 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1110 fprintf (ira_dump_file
, " Insn %u(l%d): point = %d\n",
1111 INSN_UID (insn
), loop_tree_node
->parent
->loop_num
,
1114 call_p
= CALL_P (insn
);
1115 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1117 bool clear_pic_use_conflict_p
= false;
1118 /* Processing insn usage in call insn can create conflict
1119 with pic pseudo and pic hard reg and that is wrong.
1120 Check this situation and fix it at the end of the insn
1122 if (call_p
&& pic_offset_table_rtx
!= NULL_RTX
1123 && (regno
= REGNO (pic_offset_table_rtx
)) >= FIRST_PSEUDO_REGISTER
1124 && (a
= ira_curr_regno_allocno_map
[regno
]) != NULL
)
1125 clear_pic_use_conflict_p
1126 = (find_regno_fusage (insn
, USE
, REAL_PIC_OFFSET_TABLE_REGNUM
)
1127 && ! TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS
1128 (ALLOCNO_OBJECT (a
, 0)),
1129 REAL_PIC_OFFSET_TABLE_REGNUM
));
1132 /* Mark each defined value as live. We need to do this for
1133 unused values because they still conflict with quantities
1134 that are live at the time of the definition.
1136 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1137 references represent the effect of the called function
1138 on a call-clobbered register. Marking the register as
1139 live would stop us from allocating it to a call-crossing
1141 FOR_EACH_INSN_DEF (def
, insn
)
1142 if (!call_p
|| !DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
1143 mark_ref_live (def
);
1145 /* If INSN has multiple outputs, then any value used in one
1146 of the outputs conflicts with the other outputs. Model this
1147 by making the used value live during the output phase.
1149 It is unsafe to use !single_set here since it will ignore
1150 an unused output. Just because an output is unused does
1151 not mean the compiler can assume the side effect will not
1152 occur. Consider if ALLOCNO appears in the address of an
1153 output and we reload the output. If we allocate ALLOCNO
1154 to the same hard register as an unused output we could
1155 set the hard register before the output reload insn. */
1156 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
1157 FOR_EACH_INSN_USE (use
, insn
)
1162 reg
= DF_REF_REG (use
);
1163 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
1167 set
= XVECEXP (PATTERN (insn
), 0, i
);
1168 if (GET_CODE (set
) == SET
1169 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1171 /* After the previous loop, this is a no-op if
1172 REG is contained within SET_DEST (SET). */
1173 mark_ref_live (use
);
1179 extract_insn (insn
);
1180 preferred_alternatives
= get_preferred_alternatives (insn
);
1181 preprocess_constraints (insn
);
1182 process_single_reg_class_operands (false, freq
);
1184 /* See which defined values die here. */
1185 FOR_EACH_INSN_DEF (def
, insn
)
1186 if (!call_p
|| !DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
1187 mark_ref_dead (def
);
1191 /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1192 there, try to find a pseudo that is live across the call but
1193 can be cheaply reconstructed from the return value. */
1194 rtx cheap_reg
= find_call_crossed_cheap_reg (insn
);
1195 if (cheap_reg
!= NULL_RTX
)
1196 add_reg_note (insn
, REG_RETURNED
, cheap_reg
);
1199 sparseset_clear (allocnos_processed
);
1200 /* The current set of live allocnos are live across the call. */
1201 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1203 ira_object_t obj
= ira_object_id_map
[i
];
1204 a
= OBJECT_ALLOCNO (obj
);
1205 int num
= ALLOCNO_NUM (a
);
1206 HARD_REG_SET this_call_used_reg_set
;
1208 get_call_reg_set_usage (insn
, &this_call_used_reg_set
,
1211 /* Don't allocate allocnos that cross setjmps or any
1212 call, if this function receives a nonlocal
1214 if (cfun
->has_nonlocal_label
1215 || find_reg_note (insn
, REG_SETJMP
,
1216 NULL_RTX
) != NULL_RTX
)
1218 SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
));
1219 SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
));
1221 if (can_throw_internal (insn
))
1223 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
1224 this_call_used_reg_set
);
1225 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
1226 this_call_used_reg_set
);
1229 if (sparseset_bit_p (allocnos_processed
, num
))
1231 sparseset_set_bit (allocnos_processed
, num
);
1233 if (allocno_saved_at_call
[num
] != last_call_num
)
1234 /* Here we are mimicking caller-save.c behavior
1235 which does not save hard register at a call if
1236 it was saved on previous call in the same basic
1237 block and the hard register was not mentioned
1238 between the two calls. */
1239 ALLOCNO_CALL_FREQ (a
) += freq
;
1240 /* Mark it as saved at the next call. */
1241 allocno_saved_at_call
[num
] = last_call_num
+ 1;
1242 ALLOCNO_CALLS_CROSSED_NUM (a
)++;
1243 IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
),
1244 this_call_used_reg_set
);
1245 if (cheap_reg
!= NULL_RTX
1246 && ALLOCNO_REGNO (a
) == (int) REGNO (cheap_reg
))
1247 ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
)++;
1251 make_early_clobber_and_input_conflicts ();
1255 /* Mark each used value as live. */
1256 FOR_EACH_INSN_USE (use
, insn
)
1257 mark_ref_live (use
);
1259 process_single_reg_class_operands (true, freq
);
1261 set_p
= mark_hard_reg_early_clobbers (insn
, true);
1265 mark_hard_reg_early_clobbers (insn
, false);
1267 /* Mark each hard reg as live again. For example, a
1268 hard register can be in clobber and in an insn
1270 FOR_EACH_INSN_USE (use
, insn
)
1272 rtx ureg
= DF_REF_REG (use
);
1274 if (GET_CODE (ureg
) == SUBREG
)
1275 ureg
= SUBREG_REG (ureg
);
1276 if (! REG_P (ureg
) || REGNO (ureg
) >= FIRST_PSEUDO_REGISTER
)
1279 mark_ref_live (use
);
1283 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1284 if (clear_pic_use_conflict_p
)
1286 regno
= REGNO (pic_offset_table_rtx
);
1287 a
= ira_curr_regno_allocno_map
[regno
];
1288 CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (ALLOCNO_OBJECT (a
, 0)),
1289 REAL_PIC_OFFSET_TABLE_REGNUM
);
1290 CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS
1291 (ALLOCNO_OBJECT (a
, 0)),
1292 REAL_PIC_OFFSET_TABLE_REGNUM
);
1298 if (bb_has_eh_pred (bb
))
1301 unsigned int regno
= EH_RETURN_DATA_REGNO (j
);
1302 if (regno
== INVALID_REGNUM
)
1304 make_hard_regno_born (regno
);
1307 /* Allocnos can't go in stack regs at the start of a basic block
1308 that is reached by an abnormal edge. Likewise for call
1309 clobbered regs, because caller-save, fixup_abnormal_edges and
1310 possibly the table driven EH machinery are not quite ready to
1311 handle such allocnos live across such edges. */
1312 if (bb_has_abnormal_pred (bb
))
1315 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
1317 ira_allocno_t a
= OBJECT_ALLOCNO (ira_object_id_map
[px
]);
1319 ALLOCNO_NO_STACK_REG_P (a
) = true;
1320 ALLOCNO_TOTAL_NO_STACK_REG_P (a
) = true;
1322 for (px
= FIRST_STACK_REG
; px
<= LAST_STACK_REG
; px
++)
1323 make_hard_regno_born (px
);
1325 /* No need to record conflicts for call clobbered regs if we
1326 have nonlocal labels around, as we don't ever try to
1327 allocate such regs in this case. */
1328 if (!cfun
->has_nonlocal_label
1329 && has_abnormal_call_or_eh_pred_edge_p (bb
))
1330 for (px
= 0; px
< FIRST_PSEUDO_REGISTER
; px
++)
1331 if (call_used_regs
[px
]
1332 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1333 /* We should create a conflict of PIC pseudo with
1334 PIC hard reg as PIC hard reg can have a wrong
1335 value after jump described by the abnormal edge.
1336 In this case we can not allocate PIC hard reg to
1337 PIC pseudo as PIC pseudo will also have a wrong
1338 value. This code is not critical as LRA can fix
1339 it but it is better to have the right allocation
1341 || (px
== REAL_PIC_OFFSET_TABLE_REGNUM
1342 && pic_offset_table_rtx
!= NULL_RTX
1343 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
1346 make_hard_regno_born (px
);
1349 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1350 make_object_dead (ira_object_id_map
[i
]);
1355 /* Propagate register pressure to upper loop tree nodes. */
1356 if (loop_tree_node
!= ira_loop_tree_root
)
1357 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1359 enum reg_class pclass
;
1361 pclass
= ira_pressure_classes
[i
];
1362 if (loop_tree_node
->reg_pressure
[pclass
]
1363 > loop_tree_node
->parent
->reg_pressure
[pclass
])
1364 loop_tree_node
->parent
->reg_pressure
[pclass
]
1365 = loop_tree_node
->reg_pressure
[pclass
];
1369 /* Create and set up IRA_START_POINT_RANGES and
1370 IRA_FINISH_POINT_RANGES. */
1372 create_start_finish_chains (void)
1375 ira_object_iterator oi
;
1378 ira_start_point_ranges
1379 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1380 memset (ira_start_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1381 ira_finish_point_ranges
1382 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1383 memset (ira_finish_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1384 FOR_EACH_OBJECT (obj
, oi
)
1385 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1387 r
->start_next
= ira_start_point_ranges
[r
->start
];
1388 ira_start_point_ranges
[r
->start
] = r
;
1389 r
->finish_next
= ira_finish_point_ranges
[r
->finish
];
1390 ira_finish_point_ranges
[r
->finish
] = r
;
1394 /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1395 new live ranges and program points were added as a result if new
1398 ira_rebuild_start_finish_chains (void)
1400 ira_free (ira_finish_point_ranges
);
1401 ira_free (ira_start_point_ranges
);
1402 create_start_finish_chains ();
1405 /* Compress allocno live ranges by removing program points where
1408 remove_some_program_points_and_update_live_ranges (void)
1414 ira_object_iterator oi
;
1415 live_range_t r
, prev_r
, next_r
;
1416 sbitmap born_or_dead
, born
, dead
;
1417 sbitmap_iterator sbi
;
1418 bool born_p
, dead_p
, prev_born_p
, prev_dead_p
;
1420 born
= sbitmap_alloc (ira_max_point
);
1421 dead
= sbitmap_alloc (ira_max_point
);
1422 bitmap_clear (born
);
1423 bitmap_clear (dead
);
1424 FOR_EACH_OBJECT (obj
, oi
)
1425 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1427 ira_assert (r
->start
<= r
->finish
);
1428 bitmap_set_bit (born
, r
->start
);
1429 bitmap_set_bit (dead
, r
->finish
);
1432 born_or_dead
= sbitmap_alloc (ira_max_point
);
1433 bitmap_ior (born_or_dead
, born
, dead
);
1434 map
= (int *) ira_allocate (sizeof (int) * ira_max_point
);
1436 prev_born_p
= prev_dead_p
= false;
1437 EXECUTE_IF_SET_IN_BITMAP (born_or_dead
, 0, i
, sbi
)
1439 born_p
= bitmap_bit_p (born
, i
);
1440 dead_p
= bitmap_bit_p (dead
, i
);
1441 if ((prev_born_p
&& ! prev_dead_p
&& born_p
&& ! dead_p
)
1442 || (prev_dead_p
&& ! prev_born_p
&& dead_p
&& ! born_p
))
1446 prev_born_p
= born_p
;
1447 prev_dead_p
= dead_p
;
1449 sbitmap_free (born_or_dead
);
1450 sbitmap_free (born
);
1451 sbitmap_free (dead
);
1453 if (internal_flag_ira_verbose
> 1 && ira_dump_file
!= NULL
)
1454 fprintf (ira_dump_file
, "Compressing live ranges: from %d to %d - %d%%\n",
1455 ira_max_point
, n
, 100 * n
/ ira_max_point
);
1458 FOR_EACH_OBJECT (obj
, oi
)
1459 for (r
= OBJECT_LIVE_RANGES (obj
), prev_r
= NULL
; r
!= NULL
; r
= next_r
)
1462 r
->start
= map
[r
->start
];
1463 r
->finish
= map
[r
->finish
];
1464 if (prev_r
== NULL
|| prev_r
->start
> r
->finish
+ 1)
1469 prev_r
->start
= r
->start
;
1470 prev_r
->next
= next_r
;
1471 ira_finish_live_range (r
);
1477 /* Print live ranges R to file F. */
1479 ira_print_live_range_list (FILE *f
, live_range_t r
)
1481 for (; r
!= NULL
; r
= r
->next
)
1482 fprintf (f
, " [%d..%d]", r
->start
, r
->finish
);
1487 debug (live_range
&ref
)
1489 ira_print_live_range_list (stderr
, &ref
);
1493 debug (live_range
*ptr
)
1498 fprintf (stderr
, "<nil>\n");
1501 /* Print live ranges R to stderr. */
1503 ira_debug_live_range_list (live_range_t r
)
1505 ira_print_live_range_list (stderr
, r
);
1508 /* Print live ranges of object OBJ to file F. */
1510 print_object_live_ranges (FILE *f
, ira_object_t obj
)
1512 ira_print_live_range_list (f
, OBJECT_LIVE_RANGES (obj
));
1515 /* Print live ranges of allocno A to file F. */
1517 print_allocno_live_ranges (FILE *f
, ira_allocno_t a
)
1519 int n
= ALLOCNO_NUM_OBJECTS (a
);
1522 for (i
= 0; i
< n
; i
++)
1524 fprintf (f
, " a%d(r%d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
1526 fprintf (f
, " [%d]", i
);
1528 print_object_live_ranges (f
, ALLOCNO_OBJECT (a
, i
));
1532 /* Print live ranges of allocno A to stderr. */
1534 ira_debug_allocno_live_ranges (ira_allocno_t a
)
1536 print_allocno_live_ranges (stderr
, a
);
1539 /* Print live ranges of all allocnos to file F. */
1541 print_live_ranges (FILE *f
)
1544 ira_allocno_iterator ai
;
1546 FOR_EACH_ALLOCNO (a
, ai
)
1547 print_allocno_live_ranges (f
, a
);
1550 /* Print live ranges of all allocnos to stderr. */
1552 ira_debug_live_ranges (void)
1554 print_live_ranges (stderr
);
1557 /* The main entry function creates live ranges, set up
1558 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1559 calculate register pressure info. */
1561 ira_create_allocno_live_ranges (void)
1563 objects_live
= sparseset_alloc (ira_objects_num
);
1564 allocnos_processed
= sparseset_alloc (ira_allocnos_num
);
1567 allocno_saved_at_call
1568 = (int *) ira_allocate (ira_allocnos_num
* sizeof (int));
1569 memset (allocno_saved_at_call
, 0, ira_allocnos_num
* sizeof (int));
1570 ira_traverse_loop_tree (true, ira_loop_tree_root
, NULL
,
1571 process_bb_node_lives
);
1572 ira_max_point
= curr_point
;
1573 create_start_finish_chains ();
1574 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1575 print_live_ranges (ira_dump_file
);
1577 ira_free (allocno_saved_at_call
);
1578 sparseset_free (objects_live
);
1579 sparseset_free (allocnos_processed
);
1582 /* Compress allocno live ranges. */
1584 ira_compress_allocno_live_ranges (void)
1586 remove_some_program_points_and_update_live_ranges ();
1587 ira_rebuild_start_finish_chains ();
1588 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1590 fprintf (ira_dump_file
, "Ranges after the compression:\n");
1591 print_live_ranges (ira_dump_file
);
1595 /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1597 ira_finish_allocno_live_ranges (void)
1599 ira_free (ira_finish_point_ranges
);
1600 ira_free (ira_start_point_ranges
);