1 /* IRA processing allocno lives to build allocno live ranges.
2 Copyright (C) 2006-2018 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "insn-config.h"
35 #include "sparseset.h"
37 /* The code in this file is similar to one in global but the code
38 works on the allocno basis and creates live ranges instead of
39 pseudo-register conflicts. */
41 /* Program points are enumerated by numbers from range
42 0..IRA_MAX_POINT-1. There are approximately two times more program
43 points than insns. Program points are places in the program where
44 liveness info can be changed. In most general case (there are more
45 complicated cases too) some program points correspond to places
46 where input operand dies and other ones correspond to places where
47 output operands are born. */
50 /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
51 live ranges with given start/finish point. */
52 live_range_t
*ira_start_point_ranges
, *ira_finish_point_ranges
;
54 /* Number of the current program point. */
55 static int curr_point
;
57 /* Point where register pressure excess started or -1 if there is no
58 register pressure excess. Excess pressure for a register class at
59 some point means that there are more allocnos of given register
60 class living at the point than number of hard-registers of the
61 class available for the allocation. It is defined only for
63 static int high_pressure_start_point
[N_REG_CLASSES
];
65 /* Objects live at current point in the scan. */
66 static sparseset objects_live
;
68 /* A temporary bitmap used in functions that wish to avoid visiting an allocno
70 static sparseset allocnos_processed
;
72 /* Set of hard regs (except eliminable ones) currently live. */
73 static HARD_REG_SET hard_regs_live
;
75 /* The loop tree node corresponding to the current basic block. */
76 static ira_loop_tree_node_t curr_bb_node
;
78 /* The number of the last processed call. */
79 static int last_call_num
;
80 /* The number of last call at which given allocno was saved. */
81 static int *allocno_saved_at_call
;
83 /* The value of get_preferred_alternatives for the current instruction,
84 supplemental to recog_data. */
85 static alternative_mask preferred_alternatives
;
87 /* Record hard register REGNO as now being live. */
89 make_hard_regno_live (int regno
)
91 SET_HARD_REG_BIT (hard_regs_live
, regno
);
94 /* Process the definition of hard register REGNO. This updates
95 hard_regs_live and hard reg conflict information for living allocnos. */
97 make_hard_regno_dead (int regno
)
100 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
102 ira_object_t obj
= ira_object_id_map
[i
];
104 SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj
), regno
);
105 SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
);
107 CLEAR_HARD_REG_BIT (hard_regs_live
, regno
);
110 /* Record object OBJ as now being live. Set a bit for it in objects_live,
111 and start a new live range for it if necessary. */
113 make_object_live (ira_object_t obj
)
115 sparseset_set_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
117 live_range_t lr
= OBJECT_LIVE_RANGES (obj
);
119 || (lr
->finish
!= curr_point
&& lr
->finish
+ 1 != curr_point
))
120 ira_add_live_range_to_object (obj
, curr_point
, -1);
123 /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
124 associated with object OBJ. */
126 update_allocno_pressure_excess_length (ira_object_t obj
)
128 ira_allocno_t a
= OBJECT_ALLOCNO (obj
);
130 enum reg_class aclass
, pclass
, cl
;
133 aclass
= ALLOCNO_CLASS (a
);
134 pclass
= ira_pressure_class_translate
[aclass
];
136 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
139 if (! ira_reg_pressure_class_p
[cl
])
141 if (high_pressure_start_point
[cl
] < 0)
143 p
= OBJECT_LIVE_RANGES (obj
);
144 ira_assert (p
!= NULL
);
145 start
= (high_pressure_start_point
[cl
] > p
->start
146 ? high_pressure_start_point
[cl
] : p
->start
);
147 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a
) += curr_point
- start
+ 1;
151 /* Process the definition of object OBJ, which is associated with allocno A.
152 This finishes the current live range for it. */
154 make_object_dead (ira_object_t obj
)
158 sparseset_clear_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
160 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
161 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
163 lr
= OBJECT_LIVE_RANGES (obj
);
164 ira_assert (lr
!= NULL
);
165 lr
->finish
= curr_point
;
166 update_allocno_pressure_excess_length (obj
);
169 /* The current register pressures for each pressure class for the current
171 static int curr_reg_pressure
[N_REG_CLASSES
];
173 /* Record that register pressure for PCLASS increased by N registers.
174 Update the current register pressure, maximal register pressure for
175 the current BB and the start point of the register pressure
178 inc_register_pressure (enum reg_class pclass
, int n
)
184 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
187 if (! ira_reg_pressure_class_p
[cl
])
189 curr_reg_pressure
[cl
] += n
;
190 if (high_pressure_start_point
[cl
] < 0
191 && (curr_reg_pressure
[cl
] > ira_class_hard_regs_num
[cl
]))
192 high_pressure_start_point
[cl
] = curr_point
;
193 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
194 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
198 /* Record that register pressure for PCLASS has decreased by NREGS
199 registers; update current register pressure, start point of the
200 register pressure excess, and register pressure excess length for
204 dec_register_pressure (enum reg_class pclass
, int nregs
)
212 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
215 if (! ira_reg_pressure_class_p
[cl
])
217 curr_reg_pressure
[cl
] -= nregs
;
218 ira_assert (curr_reg_pressure
[cl
] >= 0);
219 if (high_pressure_start_point
[cl
] >= 0
220 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
225 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, j
)
226 update_allocno_pressure_excess_length (ira_object_id_map
[j
]);
228 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
231 if (! ira_reg_pressure_class_p
[cl
])
233 if (high_pressure_start_point
[cl
] >= 0
234 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
235 high_pressure_start_point
[cl
] = -1;
240 /* Determine from the objects_live bitmap whether REGNO is currently live,
241 and occupies only one object. Return false if we have no information. */
243 pseudo_regno_single_word_and_live_p (int regno
)
245 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
250 if (ALLOCNO_NUM_OBJECTS (a
) > 1)
253 obj
= ALLOCNO_OBJECT (a
, 0);
255 return sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
));
258 /* Mark the pseudo register REGNO as live. Update all information about
259 live ranges and register pressure. */
261 mark_pseudo_regno_live (int regno
)
263 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
264 enum reg_class pclass
;
270 /* Invalidate because it is referenced. */
271 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
273 n
= ALLOCNO_NUM_OBJECTS (a
);
274 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
275 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
278 /* We track every subobject separately. */
279 gcc_assert (nregs
== n
);
283 for (i
= 0; i
< n
; i
++)
285 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
287 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
290 inc_register_pressure (pclass
, nregs
);
291 make_object_live (obj
);
295 /* Like mark_pseudo_regno_live, but try to only mark one subword of
296 the pseudo as live. SUBWORD indicates which; a value of 0
297 indicates the low part. */
299 mark_pseudo_regno_subword_live (int regno
, int subword
)
301 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
303 enum reg_class pclass
;
309 /* Invalidate because it is referenced. */
310 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
312 n
= ALLOCNO_NUM_OBJECTS (a
);
315 mark_pseudo_regno_live (regno
);
319 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
321 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
322 obj
= ALLOCNO_OBJECT (a
, subword
);
324 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
327 inc_register_pressure (pclass
, 1);
328 make_object_live (obj
);
331 /* Mark the register REG as live. Store a 1 in hard_regs_live for
332 this register, record how many consecutive hardware registers it
335 mark_hard_reg_live (rtx reg
)
337 int regno
= REGNO (reg
);
339 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
341 int last
= END_REGNO (reg
);
342 enum reg_class aclass
, pclass
;
346 if (! TEST_HARD_REG_BIT (hard_regs_live
, regno
)
347 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
349 aclass
= ira_hard_regno_allocno_class
[regno
];
350 pclass
= ira_pressure_class_translate
[aclass
];
351 inc_register_pressure (pclass
, 1);
352 make_hard_regno_live (regno
);
359 /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
360 register number; ORIG_REG is the access in the insn, which may be a
363 mark_pseudo_reg_live (rtx orig_reg
, unsigned regno
)
365 if (read_modify_subreg_p (orig_reg
))
367 mark_pseudo_regno_subword_live (regno
,
368 subreg_lowpart_p (orig_reg
) ? 0 : 1);
371 mark_pseudo_regno_live (regno
);
374 /* Mark the register referenced by use or def REF as live. */
376 mark_ref_live (df_ref ref
)
378 rtx reg
= DF_REF_REG (ref
);
381 if (GET_CODE (reg
) == SUBREG
)
382 reg
= SUBREG_REG (reg
);
384 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
385 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
387 mark_hard_reg_live (reg
);
390 /* Mark the pseudo register REGNO as dead. Update all information about
391 live ranges and register pressure. */
393 mark_pseudo_regno_dead (int regno
)
395 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
402 /* Invalidate because it is referenced. */
403 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
405 n
= ALLOCNO_NUM_OBJECTS (a
);
406 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
407 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
410 /* We track every subobject separately. */
411 gcc_assert (nregs
== n
);
414 for (i
= 0; i
< n
; i
++)
416 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
417 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
420 dec_register_pressure (cl
, nregs
);
421 make_object_dead (obj
);
425 /* Like mark_pseudo_regno_dead, but called when we know that only part of the
426 register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
428 mark_pseudo_regno_subword_dead (int regno
, int subword
)
430 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
438 /* Invalidate because it is referenced. */
439 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
441 n
= ALLOCNO_NUM_OBJECTS (a
);
443 /* The allocno as a whole doesn't die in this case. */
446 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
448 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
450 obj
= ALLOCNO_OBJECT (a
, subword
);
451 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
454 dec_register_pressure (cl
, 1);
455 make_object_dead (obj
);
458 /* Process the definition of hard register REG. This updates hard_regs_live
459 and hard reg conflict information for living allocnos. */
461 mark_hard_reg_dead (rtx reg
)
463 int regno
= REGNO (reg
);
465 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
467 int last
= END_REGNO (reg
);
468 enum reg_class aclass
, pclass
;
472 if (TEST_HARD_REG_BIT (hard_regs_live
, regno
))
474 aclass
= ira_hard_regno_allocno_class
[regno
];
475 pclass
= ira_pressure_class_translate
[aclass
];
476 dec_register_pressure (pclass
, 1);
477 make_hard_regno_dead (regno
);
484 /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
485 register number; ORIG_REG is the access in the insn, which may be a
488 mark_pseudo_reg_dead (rtx orig_reg
, unsigned regno
)
490 if (read_modify_subreg_p (orig_reg
))
492 mark_pseudo_regno_subword_dead (regno
,
493 subreg_lowpart_p (orig_reg
) ? 0 : 1);
496 mark_pseudo_regno_dead (regno
);
499 /* Mark the register referenced by definition DEF as dead, if the
500 definition is a total one. */
502 mark_ref_dead (df_ref def
)
504 rtx reg
= DF_REF_REG (def
);
507 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
))
510 if (GET_CODE (reg
) == SUBREG
)
511 reg
= SUBREG_REG (reg
);
513 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
)
514 && (GET_CODE (orig_reg
) != SUBREG
515 || REGNO (reg
) < FIRST_PSEUDO_REGISTER
516 || !read_modify_subreg_p (orig_reg
)))
519 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
520 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
522 mark_hard_reg_dead (reg
);
525 /* If REG is a pseudo or a subreg of it, and the class of its allocno
526 intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
527 rtx actually accessed, it may be identical to DREG or a subreg of it.
528 Advance the current program point before making the conflict if
529 ADVANCE_P. Return TRUE if we will need to advance the current
532 make_pseudo_conflict (rtx reg
, enum reg_class cl
, rtx dreg
, rtx orig_dreg
,
538 if (GET_CODE (reg
) == SUBREG
)
539 reg
= SUBREG_REG (reg
);
541 if (! REG_P (reg
) || REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
544 a
= ira_curr_regno_allocno_map
[REGNO (reg
)];
545 if (! reg_classes_intersect_p (cl
, ALLOCNO_CLASS (a
)))
551 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
552 mark_pseudo_reg_live (orig_dreg
, REGNO (dreg
));
553 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
554 mark_pseudo_reg_dead (orig_dreg
, REGNO (dreg
));
559 /* Check and make if necessary conflicts for pseudo DREG of class
560 DEF_CL of the current insn with input operand USE of class USE_CL.
561 ORIG_DREG is the rtx actually accessed, it may be identical to
562 DREG or a subreg of it. Advance the current program point before
563 making the conflict if ADVANCE_P. Return TRUE if we will need to
564 advance the current program point. */
566 check_and_make_def_use_conflict (rtx dreg
, rtx orig_dreg
,
567 enum reg_class def_cl
, int use
,
568 enum reg_class use_cl
, bool advance_p
)
570 if (! reg_classes_intersect_p (def_cl
, use_cl
))
573 advance_p
= make_pseudo_conflict (recog_data
.operand
[use
],
574 use_cl
, dreg
, orig_dreg
, advance_p
);
576 /* Reload may end up swapping commutative operands, so you
577 have to take both orderings into account. The
578 constraints for the two operands can be completely
579 different. (Indeed, if the constraints for the two
580 operands are the same for all alternatives, there's no
581 point marking them as commutative.) */
582 if (use
< recog_data
.n_operands
- 1
583 && recog_data
.constraints
[use
][0] == '%')
585 = make_pseudo_conflict (recog_data
.operand
[use
+ 1],
586 use_cl
, dreg
, orig_dreg
, advance_p
);
588 && recog_data
.constraints
[use
- 1][0] == '%')
590 = make_pseudo_conflict (recog_data
.operand
[use
- 1],
591 use_cl
, dreg
, orig_dreg
, advance_p
);
595 /* Check and make if necessary conflicts for definition DEF of class
596 DEF_CL of the current insn with input operands. Process only
597 constraints of alternative ALT. */
599 check_and_make_def_conflict (int alt
, int def
, enum reg_class def_cl
)
603 enum reg_class use_cl
, acl
;
605 rtx dreg
= recog_data
.operand
[def
];
606 rtx orig_dreg
= dreg
;
608 if (def_cl
== NO_REGS
)
611 if (GET_CODE (dreg
) == SUBREG
)
612 dreg
= SUBREG_REG (dreg
);
614 if (! REG_P (dreg
) || REGNO (dreg
) < FIRST_PSEUDO_REGISTER
)
617 a
= ira_curr_regno_allocno_map
[REGNO (dreg
)];
618 acl
= ALLOCNO_CLASS (a
);
619 if (! reg_classes_intersect_p (acl
, def_cl
))
624 int n_operands
= recog_data
.n_operands
;
625 const operand_alternative
*op_alt
= &recog_op_alt
[alt
* n_operands
];
626 for (use
= 0; use
< n_operands
; use
++)
630 if (use
== def
|| recog_data
.operand_type
[use
] == OP_OUT
)
633 if (op_alt
[use
].anything_ok
)
636 use_cl
= op_alt
[use
].cl
;
638 /* If there's any alternative that allows USE to match DEF, do not
639 record a conflict. If that causes us to create an invalid
640 instruction due to the earlyclobber, reload must fix it up. */
641 for (alt1
= 0; alt1
< recog_data
.n_alternatives
; alt1
++)
643 if (!TEST_BIT (preferred_alternatives
, alt1
))
645 const operand_alternative
*op_alt1
646 = &recog_op_alt
[alt1
* n_operands
];
647 if (op_alt1
[use
].matches
== def
648 || (use
< n_operands
- 1
649 && recog_data
.constraints
[use
][0] == '%'
650 && op_alt1
[use
+ 1].matches
== def
)
652 && recog_data
.constraints
[use
- 1][0] == '%'
653 && op_alt1
[use
- 1].matches
== def
))
657 if (alt1
< recog_data
.n_alternatives
)
660 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
661 use
, use_cl
, advance_p
);
663 if ((use_match
= op_alt
[use
].matches
) >= 0)
665 if (use_match
== def
)
668 if (op_alt
[use_match
].anything_ok
)
671 use_cl
= op_alt
[use_match
].cl
;
672 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
673 use
, use_cl
, advance_p
);
678 /* Make conflicts of early clobber pseudo registers of the current
679 insn with its inputs. Avoid introducing unnecessary conflicts by
680 checking classes of the constraints and pseudos because otherwise
681 significant code degradation is possible for some targets. */
683 make_early_clobber_and_input_conflicts (void)
687 enum reg_class def_cl
;
689 int n_alternatives
= recog_data
.n_alternatives
;
690 int n_operands
= recog_data
.n_operands
;
691 const operand_alternative
*op_alt
= recog_op_alt
;
692 for (alt
= 0; alt
< n_alternatives
; alt
++, op_alt
+= n_operands
)
693 if (TEST_BIT (preferred_alternatives
, alt
))
694 for (def
= 0; def
< n_operands
; def
++)
697 if (op_alt
[def
].earlyclobber
)
699 if (op_alt
[def
].anything_ok
)
702 def_cl
= op_alt
[def
].cl
;
703 check_and_make_def_conflict (alt
, def
, def_cl
);
705 if ((def_match
= op_alt
[def
].matches
) >= 0
706 && (op_alt
[def_match
].earlyclobber
707 || op_alt
[def
].earlyclobber
))
709 if (op_alt
[def_match
].anything_ok
)
712 def_cl
= op_alt
[def_match
].cl
;
713 check_and_make_def_conflict (alt
, def
, def_cl
);
718 /* Mark early clobber hard registers of the current INSN as live (if
719 LIVE_P) or dead. Return true if there are such registers. */
721 mark_hard_reg_early_clobbers (rtx_insn
*insn
, bool live_p
)
726 FOR_EACH_INSN_DEF (def
, insn
)
727 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_MUST_CLOBBER
))
729 rtx dreg
= DF_REF_REG (def
);
731 if (GET_CODE (dreg
) == SUBREG
)
732 dreg
= SUBREG_REG (dreg
);
733 if (! REG_P (dreg
) || REGNO (dreg
) >= FIRST_PSEUDO_REGISTER
)
736 /* Hard register clobbers are believed to be early clobber
737 because there is no way to say that non-operand hard
738 register clobbers are not early ones. */
749 /* Checks that CONSTRAINTS permits to use only one hard register. If
750 it is so, the function returns the class of the hard register.
751 Otherwise it returns NO_REGS. */
752 static enum reg_class
753 single_reg_class (const char *constraints
, rtx op
, rtx equiv_const
)
756 enum reg_class cl
, next_cl
;
757 enum constraint_num cn
;
760 alternative_mask preferred
= preferred_alternatives
;
761 for (; (c
= *constraints
); constraints
+= CONSTRAINT_LEN (c
, constraints
))
763 preferred
&= ~ALTERNATIVE_BIT (0);
766 else if (preferred
& 1)
773 /* ??? Is this the best way to handle memory constraints? */
774 cn
= lookup_constraint (constraints
);
775 if (insn_extra_memory_constraint (cn
)
776 || insn_extra_special_memory_constraint (cn
)
777 || insn_extra_address_constraint (cn
))
779 if (constraint_satisfied_p (op
, cn
)
780 || (equiv_const
!= NULL_RTX
781 && CONSTANT_P (equiv_const
)
782 && constraint_satisfied_p (equiv_const
, cn
)))
784 next_cl
= reg_class_for_constraint (cn
);
785 if (next_cl
== NO_REGS
)
788 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
789 : (ira_class_singleton
[cl
][GET_MODE (op
)]
790 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
795 case '0': case '1': case '2': case '3': case '4':
796 case '5': case '6': case '7': case '8': case '9':
798 = single_reg_class (recog_data
.constraints
[c
- '0'],
799 recog_data
.operand
[c
- '0'], NULL_RTX
);
801 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
802 : (ira_class_singleton
[cl
][GET_MODE (op
)]
803 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
811 /* The function checks that operand OP_NUM of the current insn can use
812 only one hard register. If it is so, the function returns the
813 class of the hard register. Otherwise it returns NO_REGS. */
814 static enum reg_class
815 single_reg_operand_class (int op_num
)
817 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
819 return single_reg_class (recog_data
.constraints
[op_num
],
820 recog_data
.operand
[op_num
], NULL_RTX
);
823 /* The function sets up hard register set *SET to hard registers which
824 might be used by insn reloads because the constraints are too
827 ira_implicitly_set_insn_hard_regs (HARD_REG_SET
*set
,
828 alternative_mask preferred
)
835 CLEAR_HARD_REG_SET (*set
);
836 for (i
= 0; i
< recog_data
.n_operands
; i
++)
838 op
= recog_data
.operand
[i
];
840 if (GET_CODE (op
) == SUBREG
)
841 op
= SUBREG_REG (op
);
843 if (GET_CODE (op
) == SCRATCH
844 || (REG_P (op
) && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
))
846 const char *p
= recog_data
.constraints
[i
];
848 mode
= (GET_CODE (op
) == SCRATCH
849 ? GET_MODE (op
) : PSEUDO_REGNO_MODE (regno
));
851 for (; (c
= *p
); p
+= CONSTRAINT_LEN (c
, p
))
853 preferred
&= ~ALTERNATIVE_BIT (0);
856 else if (preferred
& 1)
858 cl
= reg_class_for_constraint (lookup_constraint (p
));
861 /* There is no register pressure problem if all of the
862 regs in this class are fixed. */
863 int regno
= ira_class_singleton
[cl
][mode
];
865 add_to_hard_reg_set (set
, mode
, regno
);
871 /* Processes input operands, if IN_P, or output operands otherwise of
872 the current insn with FREQ to find allocno which can use only one
873 hard register and makes other currently living allocnos conflicting
874 with the hard register. */
876 process_single_reg_class_operands (bool in_p
, int freq
)
882 ira_allocno_t operand_a
, a
;
884 for (i
= 0; i
< recog_data
.n_operands
; i
++)
886 operand
= recog_data
.operand
[i
];
887 if (in_p
&& recog_data
.operand_type
[i
] != OP_IN
888 && recog_data
.operand_type
[i
] != OP_INOUT
)
890 if (! in_p
&& recog_data
.operand_type
[i
] != OP_OUT
891 && recog_data
.operand_type
[i
] != OP_INOUT
)
893 cl
= single_reg_operand_class (i
);
899 if (GET_CODE (operand
) == SUBREG
)
900 operand
= SUBREG_REG (operand
);
903 && (regno
= REGNO (operand
)) >= FIRST_PSEUDO_REGISTER
)
905 enum reg_class aclass
;
907 operand_a
= ira_curr_regno_allocno_map
[regno
];
908 aclass
= ALLOCNO_CLASS (operand_a
);
909 if (ira_class_subset_p
[cl
][aclass
])
911 /* View the desired allocation of OPERAND as:
917 (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
918 machine_mode ymode
, xmode
;
922 xmode
= recog_data
.operand_mode
[i
];
923 xregno
= ira_class_singleton
[cl
][xmode
];
924 gcc_assert (xregno
>= 0);
925 ymode
= ALLOCNO_MODE (operand_a
);
926 offset
= subreg_lowpart_offset (ymode
, xmode
);
927 yregno
= simplify_subreg_regno (xregno
, xmode
, offset
, ymode
);
929 && ira_class_hard_reg_index
[aclass
][yregno
] >= 0)
933 ira_allocate_and_set_costs
934 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
),
936 ira_init_register_move_cost_if_necessary (xmode
);
938 ? ira_register_move_cost
[xmode
][aclass
][cl
]
939 : ira_register_move_cost
[xmode
][cl
][aclass
]);
940 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
)
941 [ira_class_hard_reg_index
[aclass
][yregno
]] -= cost
;
946 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
948 ira_object_t obj
= ira_object_id_map
[px
];
949 a
= OBJECT_ALLOCNO (obj
);
952 /* We could increase costs of A instead of making it
953 conflicting with the hard register. But it works worse
954 because it will be spilled in reload in anyway. */
955 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
956 reg_class_contents
[cl
]);
957 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
958 reg_class_contents
[cl
]);
964 /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
965 we find a SET rtx that we can use to deduce that a register can be cheaply
966 caller-saved. Return such a register, or NULL_RTX if none is found. */
968 find_call_crossed_cheap_reg (rtx_insn
*insn
)
970 rtx cheap_reg
= NULL_RTX
;
971 rtx exp
= CALL_INSN_FUNCTION_USAGE (insn
);
975 rtx x
= XEXP (exp
, 0);
976 if (GET_CODE (x
) == SET
)
985 basic_block bb
= BLOCK_FOR_INSN (insn
);
986 rtx reg
= SET_SRC (exp
);
987 rtx_insn
*prev
= PREV_INSN (insn
);
988 while (prev
&& !(INSN_P (prev
)
989 && BLOCK_FOR_INSN (prev
) != bb
))
991 if (NONDEBUG_INSN_P (prev
))
993 rtx set
= single_set (prev
);
995 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
997 rtx src
= SET_SRC (set
);
998 if (!REG_P (src
) || HARD_REGISTER_P (src
)
999 || !pseudo_regno_single_word_and_live_p (REGNO (src
)))
1001 if (!modified_between_p (src
, prev
, insn
))
1005 if (set
&& rtx_equal_p (SET_SRC (set
), reg
))
1007 rtx dest
= SET_DEST (set
);
1008 if (!REG_P (dest
) || HARD_REGISTER_P (dest
)
1009 || !pseudo_regno_single_word_and_live_p (REGNO (dest
)))
1011 if (!modified_between_p (dest
, prev
, insn
))
1016 if (reg_set_p (reg
, prev
))
1019 prev
= PREV_INSN (prev
);
1025 /* Process insns of the basic block given by its LOOP_TREE_NODE to
1026 update allocno live ranges, allocno hard register conflicts,
1027 intersected calls, and register pressure info for allocnos for the
1028 basic block for and regions containing the basic block. */
1030 process_bb_node_lives (ira_loop_tree_node_t loop_tree_node
)
1037 bitmap reg_live_out
;
1041 bb
= loop_tree_node
->bb
;
1044 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1046 curr_reg_pressure
[ira_pressure_classes
[i
]] = 0;
1047 high_pressure_start_point
[ira_pressure_classes
[i
]] = -1;
1049 curr_bb_node
= loop_tree_node
;
1050 reg_live_out
= df_get_live_out (bb
);
1051 sparseset_clear (objects_live
);
1052 REG_SET_TO_HARD_REG_SET (hard_regs_live
, reg_live_out
);
1053 AND_COMPL_HARD_REG_SET (hard_regs_live
, eliminable_regset
);
1054 AND_COMPL_HARD_REG_SET (hard_regs_live
, ira_no_alloc_regs
);
1055 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1056 if (TEST_HARD_REG_BIT (hard_regs_live
, i
))
1058 enum reg_class aclass
, pclass
, cl
;
1060 aclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (i
)];
1061 pclass
= ira_pressure_class_translate
[aclass
];
1063 (cl
= ira_reg_class_super_classes
[pclass
][j
])
1067 if (! ira_reg_pressure_class_p
[cl
])
1069 curr_reg_pressure
[cl
]++;
1070 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
1071 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
1072 ira_assert (curr_reg_pressure
[cl
]
1073 <= ira_class_hard_regs_num
[cl
]);
1076 EXECUTE_IF_SET_IN_BITMAP (reg_live_out
, FIRST_PSEUDO_REGISTER
, j
, bi
)
1077 mark_pseudo_regno_live (j
);
1079 freq
= REG_FREQ_FROM_BB (bb
);
1083 /* Invalidate all allocno_saved_at_call entries. */
1086 /* Scan the code of this basic block, noting which allocnos and
1087 hard regs are born or die.
1089 Note that this loop treats uninitialized values as live until
1090 the beginning of the block. For example, if an instruction
1091 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1092 set, FOO will remain live until the beginning of the block.
1093 Likewise if FOO is not set at all. This is unnecessarily
1094 pessimistic, but it probably doesn't matter much in practice. */
1095 FOR_BB_INSNS_REVERSE (bb
, insn
)
1101 if (!NONDEBUG_INSN_P (insn
))
1104 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1105 fprintf (ira_dump_file
, " Insn %u(l%d): point = %d\n",
1106 INSN_UID (insn
), loop_tree_node
->parent
->loop_num
,
1109 call_p
= CALL_P (insn
);
1110 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1112 bool clear_pic_use_conflict_p
= false;
1113 /* Processing insn usage in call insn can create conflict
1114 with pic pseudo and pic hard reg and that is wrong.
1115 Check this situation and fix it at the end of the insn
1117 if (call_p
&& pic_offset_table_rtx
!= NULL_RTX
1118 && (regno
= REGNO (pic_offset_table_rtx
)) >= FIRST_PSEUDO_REGISTER
1119 && (a
= ira_curr_regno_allocno_map
[regno
]) != NULL
)
1120 clear_pic_use_conflict_p
1121 = (find_regno_fusage (insn
, USE
, REAL_PIC_OFFSET_TABLE_REGNUM
)
1122 && ! TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS
1123 (ALLOCNO_OBJECT (a
, 0)),
1124 REAL_PIC_OFFSET_TABLE_REGNUM
));
1127 /* Mark each defined value as live. We need to do this for
1128 unused values because they still conflict with quantities
1129 that are live at the time of the definition.
1131 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1132 references represent the effect of the called function
1133 on a call-clobbered register. Marking the register as
1134 live would stop us from allocating it to a call-crossing
1136 FOR_EACH_INSN_DEF (def
, insn
)
1137 if (!call_p
|| !DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
1138 mark_ref_live (def
);
1140 /* If INSN has multiple outputs, then any value used in one
1141 of the outputs conflicts with the other outputs. Model this
1142 by making the used value live during the output phase.
1144 It is unsafe to use !single_set here since it will ignore
1145 an unused output. Just because an output is unused does
1146 not mean the compiler can assume the side effect will not
1147 occur. Consider if ALLOCNO appears in the address of an
1148 output and we reload the output. If we allocate ALLOCNO
1149 to the same hard register as an unused output we could
1150 set the hard register before the output reload insn. */
1151 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
1152 FOR_EACH_INSN_USE (use
, insn
)
1157 reg
= DF_REF_REG (use
);
1158 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
1162 set
= XVECEXP (PATTERN (insn
), 0, i
);
1163 if (GET_CODE (set
) == SET
1164 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1166 /* After the previous loop, this is a no-op if
1167 REG is contained within SET_DEST (SET). */
1168 mark_ref_live (use
);
1174 extract_insn (insn
);
1175 preferred_alternatives
= get_preferred_alternatives (insn
);
1176 preprocess_constraints (insn
);
1177 process_single_reg_class_operands (false, freq
);
1179 /* See which defined values die here. */
1180 FOR_EACH_INSN_DEF (def
, insn
)
1181 if (!call_p
|| !DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
1182 mark_ref_dead (def
);
1186 /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1187 there, try to find a pseudo that is live across the call but
1188 can be cheaply reconstructed from the return value. */
1189 rtx cheap_reg
= find_call_crossed_cheap_reg (insn
);
1190 if (cheap_reg
!= NULL_RTX
)
1191 add_reg_note (insn
, REG_RETURNED
, cheap_reg
);
1194 sparseset_clear (allocnos_processed
);
1195 /* The current set of live allocnos are live across the call. */
1196 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1198 ira_object_t obj
= ira_object_id_map
[i
];
1199 a
= OBJECT_ALLOCNO (obj
);
1200 int num
= ALLOCNO_NUM (a
);
1201 HARD_REG_SET this_call_used_reg_set
;
1203 get_call_reg_set_usage (insn
, &this_call_used_reg_set
,
1206 /* Don't allocate allocnos that cross setjmps or any
1207 call, if this function receives a nonlocal
1209 if (cfun
->has_nonlocal_label
1210 || find_reg_note (insn
, REG_SETJMP
,
1211 NULL_RTX
) != NULL_RTX
)
1213 SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
));
1214 SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
));
1216 if (can_throw_internal (insn
))
1218 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
1219 this_call_used_reg_set
);
1220 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
1221 this_call_used_reg_set
);
1224 if (sparseset_bit_p (allocnos_processed
, num
))
1226 sparseset_set_bit (allocnos_processed
, num
);
1228 if (allocno_saved_at_call
[num
] != last_call_num
)
1229 /* Here we are mimicking caller-save.c behavior
1230 which does not save hard register at a call if
1231 it was saved on previous call in the same basic
1232 block and the hard register was not mentioned
1233 between the two calls. */
1234 ALLOCNO_CALL_FREQ (a
) += freq
;
1235 /* Mark it as saved at the next call. */
1236 allocno_saved_at_call
[num
] = last_call_num
+ 1;
1237 ALLOCNO_CALLS_CROSSED_NUM (a
)++;
1238 IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
),
1239 this_call_used_reg_set
);
1240 if (cheap_reg
!= NULL_RTX
1241 && ALLOCNO_REGNO (a
) == (int) REGNO (cheap_reg
))
1242 ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
)++;
1246 make_early_clobber_and_input_conflicts ();
1250 /* Mark each used value as live. */
1251 FOR_EACH_INSN_USE (use
, insn
)
1252 mark_ref_live (use
);
1254 process_single_reg_class_operands (true, freq
);
1256 set_p
= mark_hard_reg_early_clobbers (insn
, true);
1260 mark_hard_reg_early_clobbers (insn
, false);
1262 /* Mark each hard reg as live again. For example, a
1263 hard register can be in clobber and in an insn
1265 FOR_EACH_INSN_USE (use
, insn
)
1267 rtx ureg
= DF_REF_REG (use
);
1269 if (GET_CODE (ureg
) == SUBREG
)
1270 ureg
= SUBREG_REG (ureg
);
1271 if (! REG_P (ureg
) || REGNO (ureg
) >= FIRST_PSEUDO_REGISTER
)
1274 mark_ref_live (use
);
1278 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1279 if (clear_pic_use_conflict_p
)
1281 regno
= REGNO (pic_offset_table_rtx
);
1282 a
= ira_curr_regno_allocno_map
[regno
];
1283 CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (ALLOCNO_OBJECT (a
, 0)),
1284 REAL_PIC_OFFSET_TABLE_REGNUM
);
1285 CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS
1286 (ALLOCNO_OBJECT (a
, 0)),
1287 REAL_PIC_OFFSET_TABLE_REGNUM
);
1293 if (bb_has_eh_pred (bb
))
1296 unsigned int regno
= EH_RETURN_DATA_REGNO (j
);
1297 if (regno
== INVALID_REGNUM
)
1299 make_hard_regno_live (regno
);
1302 /* Allocnos can't go in stack regs at the start of a basic block
1303 that is reached by an abnormal edge. Likewise for call
1304 clobbered regs, because caller-save, fixup_abnormal_edges and
1305 possibly the table driven EH machinery are not quite ready to
1306 handle such allocnos live across such edges. */
1307 if (bb_has_abnormal_pred (bb
))
1310 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
1312 ira_allocno_t a
= OBJECT_ALLOCNO (ira_object_id_map
[px
]);
1314 ALLOCNO_NO_STACK_REG_P (a
) = true;
1315 ALLOCNO_TOTAL_NO_STACK_REG_P (a
) = true;
1317 for (px
= FIRST_STACK_REG
; px
<= LAST_STACK_REG
; px
++)
1318 make_hard_regno_live (px
);
1320 /* No need to record conflicts for call clobbered regs if we
1321 have nonlocal labels around, as we don't ever try to
1322 allocate such regs in this case. */
1323 if (!cfun
->has_nonlocal_label
1324 && has_abnormal_call_or_eh_pred_edge_p (bb
))
1325 for (px
= 0; px
< FIRST_PSEUDO_REGISTER
; px
++)
1326 if (call_used_regs
[px
]
1327 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1328 /* We should create a conflict of PIC pseudo with
1329 PIC hard reg as PIC hard reg can have a wrong
1330 value after jump described by the abnormal edge.
1331 In this case we can not allocate PIC hard reg to
1332 PIC pseudo as PIC pseudo will also have a wrong
1333 value. This code is not critical as LRA can fix
1334 it but it is better to have the right allocation
1336 || (px
== REAL_PIC_OFFSET_TABLE_REGNUM
1337 && pic_offset_table_rtx
!= NULL_RTX
1338 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
1341 make_hard_regno_live (px
);
1344 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1345 make_object_dead (ira_object_id_map
[i
]);
1350 /* Propagate register pressure to upper loop tree nodes. */
1351 if (loop_tree_node
!= ira_loop_tree_root
)
1352 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1354 enum reg_class pclass
;
1356 pclass
= ira_pressure_classes
[i
];
1357 if (loop_tree_node
->reg_pressure
[pclass
]
1358 > loop_tree_node
->parent
->reg_pressure
[pclass
])
1359 loop_tree_node
->parent
->reg_pressure
[pclass
]
1360 = loop_tree_node
->reg_pressure
[pclass
];
1364 /* Create and set up IRA_START_POINT_RANGES and
1365 IRA_FINISH_POINT_RANGES. */
1367 create_start_finish_chains (void)
1370 ira_object_iterator oi
;
1373 ira_start_point_ranges
1374 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1375 memset (ira_start_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1376 ira_finish_point_ranges
1377 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1378 memset (ira_finish_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1379 FOR_EACH_OBJECT (obj
, oi
)
1380 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1382 r
->start_next
= ira_start_point_ranges
[r
->start
];
1383 ira_start_point_ranges
[r
->start
] = r
;
1384 r
->finish_next
= ira_finish_point_ranges
[r
->finish
];
1385 ira_finish_point_ranges
[r
->finish
] = r
;
1389 /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1390 new live ranges and program points were added as a result if new
1393 ira_rebuild_start_finish_chains (void)
1395 ira_free (ira_finish_point_ranges
);
1396 ira_free (ira_start_point_ranges
);
1397 create_start_finish_chains ();
1400 /* Compress allocno live ranges by removing program points where
1403 remove_some_program_points_and_update_live_ranges (void)
1409 ira_object_iterator oi
;
1410 live_range_t r
, prev_r
, next_r
;
1411 sbitmap_iterator sbi
;
1412 bool born_p
, dead_p
, prev_born_p
, prev_dead_p
;
1414 auto_sbitmap
born (ira_max_point
);
1415 auto_sbitmap
dead (ira_max_point
);
1416 bitmap_clear (born
);
1417 bitmap_clear (dead
);
1418 FOR_EACH_OBJECT (obj
, oi
)
1419 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1421 ira_assert (r
->start
<= r
->finish
);
1422 bitmap_set_bit (born
, r
->start
);
1423 bitmap_set_bit (dead
, r
->finish
);
1426 auto_sbitmap
born_or_dead (ira_max_point
);
1427 bitmap_ior (born_or_dead
, born
, dead
);
1428 map
= (int *) ira_allocate (sizeof (int) * ira_max_point
);
1430 prev_born_p
= prev_dead_p
= false;
1431 EXECUTE_IF_SET_IN_BITMAP (born_or_dead
, 0, i
, sbi
)
1433 born_p
= bitmap_bit_p (born
, i
);
1434 dead_p
= bitmap_bit_p (dead
, i
);
1435 if ((prev_born_p
&& ! prev_dead_p
&& born_p
&& ! dead_p
)
1436 || (prev_dead_p
&& ! prev_born_p
&& dead_p
&& ! born_p
))
1440 prev_born_p
= born_p
;
1441 prev_dead_p
= dead_p
;
1445 if (internal_flag_ira_verbose
> 1 && ira_dump_file
!= NULL
)
1446 fprintf (ira_dump_file
, "Compressing live ranges: from %d to %d - %d%%\n",
1447 ira_max_point
, n
, 100 * n
/ ira_max_point
);
1450 FOR_EACH_OBJECT (obj
, oi
)
1451 for (r
= OBJECT_LIVE_RANGES (obj
), prev_r
= NULL
; r
!= NULL
; r
= next_r
)
1454 r
->start
= map
[r
->start
];
1455 r
->finish
= map
[r
->finish
];
1456 if (prev_r
== NULL
|| prev_r
->start
> r
->finish
+ 1)
1461 prev_r
->start
= r
->start
;
1462 prev_r
->next
= next_r
;
1463 ira_finish_live_range (r
);
1469 /* Print live ranges R to file F. */
1471 ira_print_live_range_list (FILE *f
, live_range_t r
)
1473 for (; r
!= NULL
; r
= r
->next
)
1474 fprintf (f
, " [%d..%d]", r
->start
, r
->finish
);
1479 debug (live_range
&ref
)
1481 ira_print_live_range_list (stderr
, &ref
);
1485 debug (live_range
*ptr
)
1490 fprintf (stderr
, "<nil>\n");
1493 /* Print live ranges R to stderr. */
1495 ira_debug_live_range_list (live_range_t r
)
1497 ira_print_live_range_list (stderr
, r
);
1500 /* Print live ranges of object OBJ to file F. */
1502 print_object_live_ranges (FILE *f
, ira_object_t obj
)
1504 ira_print_live_range_list (f
, OBJECT_LIVE_RANGES (obj
));
1507 /* Print live ranges of allocno A to file F. */
1509 print_allocno_live_ranges (FILE *f
, ira_allocno_t a
)
1511 int n
= ALLOCNO_NUM_OBJECTS (a
);
1514 for (i
= 0; i
< n
; i
++)
1516 fprintf (f
, " a%d(r%d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
1518 fprintf (f
, " [%d]", i
);
1520 print_object_live_ranges (f
, ALLOCNO_OBJECT (a
, i
));
1524 /* Print live ranges of allocno A to stderr. */
1526 ira_debug_allocno_live_ranges (ira_allocno_t a
)
1528 print_allocno_live_ranges (stderr
, a
);
1531 /* Print live ranges of all allocnos to file F. */
1533 print_live_ranges (FILE *f
)
1536 ira_allocno_iterator ai
;
1538 FOR_EACH_ALLOCNO (a
, ai
)
1539 print_allocno_live_ranges (f
, a
);
1542 /* Print live ranges of all allocnos to stderr. */
1544 ira_debug_live_ranges (void)
1546 print_live_ranges (stderr
);
1549 /* The main entry function creates live ranges, set up
1550 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1551 calculate register pressure info. */
1553 ira_create_allocno_live_ranges (void)
1555 objects_live
= sparseset_alloc (ira_objects_num
);
1556 allocnos_processed
= sparseset_alloc (ira_allocnos_num
);
1559 allocno_saved_at_call
1560 = (int *) ira_allocate (ira_allocnos_num
* sizeof (int));
1561 memset (allocno_saved_at_call
, 0, ira_allocnos_num
* sizeof (int));
1562 ira_traverse_loop_tree (true, ira_loop_tree_root
, NULL
,
1563 process_bb_node_lives
);
1564 ira_max_point
= curr_point
;
1565 create_start_finish_chains ();
1566 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1567 print_live_ranges (ira_dump_file
);
1569 ira_free (allocno_saved_at_call
);
1570 sparseset_free (objects_live
);
1571 sparseset_free (allocnos_processed
);
1574 /* Compress allocno live ranges. */
1576 ira_compress_allocno_live_ranges (void)
1578 remove_some_program_points_and_update_live_ranges ();
1579 ira_rebuild_start_finish_chains ();
1580 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1582 fprintf (ira_dump_file
, "Ranges after the compression:\n");
1583 print_live_ranges (ira_dump_file
);
1587 /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1589 ira_finish_allocno_live_ranges (void)
1591 ira_free (ira_finish_point_ranges
);
1592 ira_free (ira_start_point_ranges
);