1 /* IRA processing allocno lives to build allocno live ranges.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "basic-block.h"
33 #include "insn-config.h"
35 #include "diagnostic-core.h"
39 #include "sparseset.h"
42 /* The code in this file is similar to one in global but the code
43 works on the allocno basis and creates live ranges instead of
44 pseudo-register conflicts. */
46 /* Program points are enumerated by numbers from range
47 0..IRA_MAX_POINT-1. There are approximately two times more program
48 points than insns. Program points are places in the program where
49 liveness info can be changed. In most general case (there are more
50 complicated cases too) some program points correspond to places
51 where input operand dies and other ones correspond to places where
52 output operands are born. */
55 /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
56 live ranges with given start/finish point. */
57 live_range_t
*ira_start_point_ranges
, *ira_finish_point_ranges
;
59 /* Number of the current program point. */
60 static int curr_point
;
62 /* Point where register pressure excess started or -1 if there is no
63 register pressure excess. Excess pressure for a register class at
64 some point means that there are more allocnos of given register
65 class living at the point than number of hard-registers of the
66 class available for the allocation. It is defined only for
68 static int high_pressure_start_point
[N_REG_CLASSES
];
70 /* Objects live at current point in the scan. */
71 static sparseset objects_live
;
73 /* A temporary bitmap used in functions that wish to avoid visiting an allocno
75 static sparseset allocnos_processed
;
77 /* Set of hard regs (except eliminable ones) currently live. */
78 static HARD_REG_SET hard_regs_live
;
80 /* The loop tree node corresponding to the current basic block. */
81 static ira_loop_tree_node_t curr_bb_node
;
83 /* The number of the last processed call. */
84 static int last_call_num
;
85 /* The number of last call at which given allocno was saved. */
86 static int *allocno_saved_at_call
;
88 /* Record the birth of hard register REGNO, updating hard_regs_live and
89 hard reg conflict information for living allocnos. */
91 make_hard_regno_born (int regno
)
95 SET_HARD_REG_BIT (hard_regs_live
, regno
);
96 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
98 ira_object_t obj
= ira_object_id_map
[i
];
100 SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj
), regno
);
101 SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
);
105 /* Process the death of hard register REGNO. This updates
108 make_hard_regno_dead (int regno
)
110 CLEAR_HARD_REG_BIT (hard_regs_live
, regno
);
113 /* Record the birth of object OBJ. Set a bit for it in objects_live,
114 start a new live range for it if necessary and update hard register
117 make_object_born (ira_object_t obj
)
119 live_range_t lr
= OBJECT_LIVE_RANGES (obj
);
121 sparseset_set_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
122 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
123 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
126 || (lr
->finish
!= curr_point
&& lr
->finish
+ 1 != curr_point
))
127 ira_add_live_range_to_object (obj
, curr_point
, -1);
130 /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
131 associated with object OBJ. */
133 update_allocno_pressure_excess_length (ira_object_t obj
)
135 ira_allocno_t a
= OBJECT_ALLOCNO (obj
);
137 enum reg_class aclass
, pclass
, cl
;
140 aclass
= ALLOCNO_CLASS (a
);
141 pclass
= ira_pressure_class_translate
[aclass
];
143 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
146 if (! ira_reg_pressure_class_p
[cl
])
148 if (high_pressure_start_point
[cl
] < 0)
150 p
= OBJECT_LIVE_RANGES (obj
);
151 ira_assert (p
!= NULL
);
152 start
= (high_pressure_start_point
[cl
] > p
->start
153 ? high_pressure_start_point
[cl
] : p
->start
);
154 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a
) += curr_point
- start
+ 1;
158 /* Process the death of object OBJ, which is associated with allocno
159 A. This finishes the current live range for it. */
161 make_object_dead (ira_object_t obj
)
165 sparseset_clear_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
166 lr
= OBJECT_LIVE_RANGES (obj
);
167 ira_assert (lr
!= NULL
);
168 lr
->finish
= curr_point
;
169 update_allocno_pressure_excess_length (obj
);
172 /* The current register pressures for each pressure class for the current
174 static int curr_reg_pressure
[N_REG_CLASSES
];
176 /* Record that register pressure for PCLASS increased by N registers.
177 Update the current register pressure, maximal register pressure for
178 the current BB and the start point of the register pressure
181 inc_register_pressure (enum reg_class pclass
, int n
)
187 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
190 if (! ira_reg_pressure_class_p
[cl
])
192 curr_reg_pressure
[cl
] += n
;
193 if (high_pressure_start_point
[cl
] < 0
194 && (curr_reg_pressure
[cl
] > ira_class_hard_regs_num
[cl
]))
195 high_pressure_start_point
[cl
] = curr_point
;
196 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
197 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
201 /* Record that register pressure for PCLASS has decreased by NREGS
202 registers; update current register pressure, start point of the
203 register pressure excess, and register pressure excess length for
207 dec_register_pressure (enum reg_class pclass
, int nregs
)
215 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
218 if (! ira_reg_pressure_class_p
[cl
])
220 curr_reg_pressure
[cl
] -= nregs
;
221 ira_assert (curr_reg_pressure
[cl
] >= 0);
222 if (high_pressure_start_point
[cl
] >= 0
223 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
228 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, j
)
229 update_allocno_pressure_excess_length (ira_object_id_map
[j
]);
231 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
234 if (! ira_reg_pressure_class_p
[cl
])
236 if (high_pressure_start_point
[cl
] >= 0
237 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
238 high_pressure_start_point
[cl
] = -1;
243 /* Determine from the objects_live bitmap whether REGNO is currently live,
244 and occupies only one object. Return false if we have no information. */
246 pseudo_regno_single_word_and_live_p (int regno
)
248 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
253 if (ALLOCNO_NUM_OBJECTS (a
) > 1)
256 obj
= ALLOCNO_OBJECT (a
, 0);
258 return sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
));
261 /* Mark the pseudo register REGNO as live. Update all information about
262 live ranges and register pressure. */
264 mark_pseudo_regno_live (int regno
)
266 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
267 enum reg_class pclass
;
273 /* Invalidate because it is referenced. */
274 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
276 n
= ALLOCNO_NUM_OBJECTS (a
);
277 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
278 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
281 /* We track every subobject separately. */
282 gcc_assert (nregs
== n
);
286 for (i
= 0; i
< n
; i
++)
288 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
290 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
293 inc_register_pressure (pclass
, nregs
);
294 make_object_born (obj
);
298 /* Like mark_pseudo_regno_live, but try to only mark one subword of
299 the pseudo as live. SUBWORD indicates which; a value of 0
300 indicates the low part. */
302 mark_pseudo_regno_subword_live (int regno
, int subword
)
304 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
306 enum reg_class pclass
;
312 /* Invalidate because it is referenced. */
313 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
315 n
= ALLOCNO_NUM_OBJECTS (a
);
318 mark_pseudo_regno_live (regno
);
322 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
324 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
325 obj
= ALLOCNO_OBJECT (a
, subword
);
327 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
330 inc_register_pressure (pclass
, 1);
331 make_object_born (obj
);
334 /* Mark the register REG as live. Store a 1 in hard_regs_live for
335 this register, record how many consecutive hardware registers it
338 mark_hard_reg_live (rtx reg
)
340 int regno
= REGNO (reg
);
342 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
344 int last
= regno
+ hard_regno_nregs
[regno
][GET_MODE (reg
)];
345 enum reg_class aclass
, pclass
;
349 if (! TEST_HARD_REG_BIT (hard_regs_live
, regno
)
350 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
352 aclass
= ira_hard_regno_allocno_class
[regno
];
353 pclass
= ira_pressure_class_translate
[aclass
];
354 inc_register_pressure (pclass
, 1);
355 make_hard_regno_born (regno
);
362 /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
363 register number; ORIG_REG is the access in the insn, which may be a
366 mark_pseudo_reg_live (rtx orig_reg
, unsigned regno
)
368 if (df_read_modify_subreg_p (orig_reg
))
370 mark_pseudo_regno_subword_live (regno
,
371 subreg_lowpart_p (orig_reg
) ? 0 : 1);
374 mark_pseudo_regno_live (regno
);
377 /* Mark the register referenced by use or def REF as live. */
379 mark_ref_live (df_ref ref
)
381 rtx reg
= DF_REF_REG (ref
);
384 if (GET_CODE (reg
) == SUBREG
)
385 reg
= SUBREG_REG (reg
);
387 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
388 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
390 mark_hard_reg_live (reg
);
393 /* Mark the pseudo register REGNO as dead. Update all information about
394 live ranges and register pressure. */
396 mark_pseudo_regno_dead (int regno
)
398 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
405 /* Invalidate because it is referenced. */
406 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
408 n
= ALLOCNO_NUM_OBJECTS (a
);
409 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
410 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
413 /* We track every subobject separately. */
414 gcc_assert (nregs
== n
);
417 for (i
= 0; i
< n
; i
++)
419 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
420 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
423 dec_register_pressure (cl
, nregs
);
424 make_object_dead (obj
);
428 /* Like mark_pseudo_regno_dead, but called when we know that only part of the
429 register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
431 mark_pseudo_regno_subword_dead (int regno
, int subword
)
433 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
441 /* Invalidate because it is referenced. */
442 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
444 n
= ALLOCNO_NUM_OBJECTS (a
);
446 /* The allocno as a whole doesn't die in this case. */
449 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
451 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
453 obj
= ALLOCNO_OBJECT (a
, subword
);
454 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
457 dec_register_pressure (cl
, 1);
458 make_object_dead (obj
);
461 /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the
464 mark_hard_reg_dead (rtx reg
)
466 int regno
= REGNO (reg
);
468 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
470 int last
= regno
+ hard_regno_nregs
[regno
][GET_MODE (reg
)];
471 enum reg_class aclass
, pclass
;
475 if (TEST_HARD_REG_BIT (hard_regs_live
, regno
))
477 aclass
= ira_hard_regno_allocno_class
[regno
];
478 pclass
= ira_pressure_class_translate
[aclass
];
479 dec_register_pressure (pclass
, 1);
480 make_hard_regno_dead (regno
);
487 /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
488 register number; ORIG_REG is the access in the insn, which may be a
491 mark_pseudo_reg_dead (rtx orig_reg
, unsigned regno
)
493 if (df_read_modify_subreg_p (orig_reg
))
495 mark_pseudo_regno_subword_dead (regno
,
496 subreg_lowpart_p (orig_reg
) ? 0 : 1);
499 mark_pseudo_regno_dead (regno
);
502 /* Mark the register referenced by definition DEF as dead, if the
503 definition is a total one. */
505 mark_ref_dead (df_ref def
)
507 rtx reg
= DF_REF_REG (def
);
510 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
))
513 if (GET_CODE (reg
) == SUBREG
)
514 reg
= SUBREG_REG (reg
);
516 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
)
517 && (GET_CODE (orig_reg
) != SUBREG
518 || REGNO (reg
) < FIRST_PSEUDO_REGISTER
519 || !df_read_modify_subreg_p (orig_reg
)))
522 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
523 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
525 mark_hard_reg_dead (reg
);
528 /* If REG is a pseudo or a subreg of it, and the class of its allocno
529 intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
530 rtx actually accessed, it may be identical to DREG or a subreg of it.
531 Advance the current program point before making the conflict if
532 ADVANCE_P. Return TRUE if we will need to advance the current
535 make_pseudo_conflict (rtx reg
, enum reg_class cl
, rtx dreg
, rtx orig_dreg
,
541 if (GET_CODE (reg
) == SUBREG
)
542 reg
= SUBREG_REG (reg
);
544 if (! REG_P (reg
) || REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
547 a
= ira_curr_regno_allocno_map
[REGNO (reg
)];
548 if (! reg_classes_intersect_p (cl
, ALLOCNO_CLASS (a
)))
554 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
555 mark_pseudo_reg_live (orig_dreg
, REGNO (dreg
));
556 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
557 mark_pseudo_reg_dead (orig_dreg
, REGNO (dreg
));
562 /* Check and make if necessary conflicts for pseudo DREG of class
563 DEF_CL of the current insn with input operand USE of class USE_CL.
564 ORIG_DREG is the rtx actually accessed, it may be identical to
565 DREG or a subreg of it. Advance the current program point before
566 making the conflict if ADVANCE_P. Return TRUE if we will need to
567 advance the current program point. */
569 check_and_make_def_use_conflict (rtx dreg
, rtx orig_dreg
,
570 enum reg_class def_cl
, int use
,
571 enum reg_class use_cl
, bool advance_p
)
573 if (! reg_classes_intersect_p (def_cl
, use_cl
))
576 advance_p
= make_pseudo_conflict (recog_data
.operand
[use
],
577 use_cl
, dreg
, orig_dreg
, advance_p
);
579 /* Reload may end up swapping commutative operands, so you
580 have to take both orderings into account. The
581 constraints for the two operands can be completely
582 different. (Indeed, if the constraints for the two
583 operands are the same for all alternatives, there's no
584 point marking them as commutative.) */
585 if (use
< recog_data
.n_operands
- 1
586 && recog_data
.constraints
[use
][0] == '%')
588 = make_pseudo_conflict (recog_data
.operand
[use
+ 1],
589 use_cl
, dreg
, orig_dreg
, advance_p
);
591 && recog_data
.constraints
[use
- 1][0] == '%')
593 = make_pseudo_conflict (recog_data
.operand
[use
- 1],
594 use_cl
, dreg
, orig_dreg
, advance_p
);
598 /* Check and make if necessary conflicts for definition DEF of class
599 DEF_CL of the current insn with input operands. Process only
600 constraints of alternative ALT. */
602 check_and_make_def_conflict (int alt
, int def
, enum reg_class def_cl
)
606 enum reg_class use_cl
, acl
;
608 rtx dreg
= recog_data
.operand
[def
];
609 rtx orig_dreg
= dreg
;
611 if (def_cl
== NO_REGS
)
614 if (GET_CODE (dreg
) == SUBREG
)
615 dreg
= SUBREG_REG (dreg
);
617 if (! REG_P (dreg
) || REGNO (dreg
) < FIRST_PSEUDO_REGISTER
)
620 a
= ira_curr_regno_allocno_map
[REGNO (dreg
)];
621 acl
= ALLOCNO_CLASS (a
);
622 if (! reg_classes_intersect_p (acl
, def_cl
))
627 int n_operands
= recog_data
.n_operands
;
628 operand_alternative
*op_alt
= &recog_op_alt
[alt
* n_operands
];
629 for (use
= 0; use
< n_operands
; use
++)
633 if (use
== def
|| recog_data
.operand_type
[use
] == OP_OUT
)
636 if (op_alt
[use
].anything_ok
)
639 use_cl
= op_alt
[use
].cl
;
641 /* If there's any alternative that allows USE to match DEF, do not
642 record a conflict. If that causes us to create an invalid
643 instruction due to the earlyclobber, reload must fix it up. */
644 alternative_mask enabled
= recog_data
.enabled_alternatives
;
645 for (alt1
= 0; alt1
< recog_data
.n_alternatives
; alt1
++)
647 if (!TEST_BIT (enabled
, alt1
))
649 operand_alternative
*op_alt1
= &recog_op_alt
[alt1
* n_operands
];
650 if (op_alt1
[use
].matches
== def
651 || (use
< n_operands
- 1
652 && recog_data
.constraints
[use
][0] == '%'
653 && op_alt1
[use
+ 1].matches
== def
)
655 && recog_data
.constraints
[use
- 1][0] == '%'
656 && op_alt1
[use
- 1].matches
== def
))
660 if (alt1
< recog_data
.n_alternatives
)
663 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
664 use
, use_cl
, advance_p
);
666 if ((use_match
= op_alt
[use
].matches
) >= 0)
668 if (use_match
== def
)
671 if (op_alt
[use_match
].anything_ok
)
674 use_cl
= op_alt
[use_match
].cl
;
675 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
676 use
, use_cl
, advance_p
);
681 /* Make conflicts of early clobber pseudo registers of the current
682 insn with its inputs. Avoid introducing unnecessary conflicts by
683 checking classes of the constraints and pseudos because otherwise
684 significant code degradation is possible for some targets. */
686 make_early_clobber_and_input_conflicts (void)
690 enum reg_class def_cl
;
692 int n_alternatives
= recog_data
.n_alternatives
;
693 int n_operands
= recog_data
.n_operands
;
694 alternative_mask enabled
= recog_data
.enabled_alternatives
;
695 operand_alternative
*op_alt
= recog_op_alt
;
696 for (alt
= 0; alt
< n_alternatives
; alt
++, op_alt
+= n_operands
)
697 if (TEST_BIT (enabled
, alt
))
698 for (def
= 0; def
< n_operands
; def
++)
701 if (op_alt
[def
].earlyclobber
)
703 if (op_alt
[def
].anything_ok
)
706 def_cl
= op_alt
[def
].cl
;
707 check_and_make_def_conflict (alt
, def
, def_cl
);
709 if ((def_match
= op_alt
[def
].matches
) >= 0
710 && (op_alt
[def_match
].earlyclobber
711 || op_alt
[def
].earlyclobber
))
713 if (op_alt
[def_match
].anything_ok
)
716 def_cl
= op_alt
[def_match
].cl
;
717 check_and_make_def_conflict (alt
, def
, def_cl
);
722 /* Mark early clobber hard registers of the current INSN as live (if
723 LIVE_P) or dead. Return true if there are such registers. */
725 mark_hard_reg_early_clobbers (rtx insn
, bool live_p
)
730 for (def_rec
= DF_INSN_DEFS (insn
); *def_rec
; def_rec
++)
731 if (DF_REF_FLAGS_IS_SET (*def_rec
, DF_REF_MUST_CLOBBER
))
733 rtx dreg
= DF_REF_REG (*def_rec
);
735 if (GET_CODE (dreg
) == SUBREG
)
736 dreg
= SUBREG_REG (dreg
);
737 if (! REG_P (dreg
) || REGNO (dreg
) >= FIRST_PSEUDO_REGISTER
)
740 /* Hard register clobbers are believed to be early clobber
741 because there is no way to say that non-operand hard
742 register clobbers are not early ones. */
744 mark_ref_live (*def_rec
);
746 mark_ref_dead (*def_rec
);
753 /* Checks that CONSTRAINTS permits to use only one hard register. If
754 it is so, the function returns the class of the hard register.
755 Otherwise it returns NO_REGS. */
756 static enum reg_class
757 single_reg_class (const char *constraints
, rtx op
, rtx equiv_const
)
760 enum reg_class cl
, next_cl
;
763 alternative_mask enabled
= recog_data
.enabled_alternatives
;
764 for (; (c
= *constraints
); constraints
+= CONSTRAINT_LEN (c
, constraints
))
766 enabled
&= ~ALTERNATIVE_BIT (0);
769 else if (enabled
& 1)
784 || (equiv_const
!= NULL_RTX
&& CONSTANT_P (equiv_const
)))
789 if (CONST_SCALAR_INT_P (op
)
790 || (equiv_const
!= NULL_RTX
&& CONST_SCALAR_INT_P (equiv_const
)))
795 if ((CONSTANT_P (op
) && !CONST_SCALAR_INT_P (op
))
796 || (equiv_const
!= NULL_RTX
797 && CONSTANT_P (equiv_const
)
798 && !CONST_SCALAR_INT_P (equiv_const
)))
810 if ((CONST_INT_P (op
)
811 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, constraints
))
812 || (equiv_const
!= NULL_RTX
813 && CONST_INT_P (equiv_const
)
814 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (equiv_const
),
821 if (CONST_DOUBLE_AS_FLOAT_P (op
)
822 || (GET_CODE (op
) == CONST_VECTOR
823 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
)
824 || (equiv_const
!= NULL_RTX
825 && (CONST_DOUBLE_AS_FLOAT_P (equiv_const
)
826 || (GET_CODE (equiv_const
) == CONST_VECTOR
827 && (GET_MODE_CLASS (GET_MODE (equiv_const
))
828 == MODE_VECTOR_FLOAT
)))))
834 if ((CONST_DOUBLE_AS_FLOAT_P (op
)
835 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, constraints
))
836 || (equiv_const
!= NULL_RTX
837 && CONST_DOUBLE_AS_FLOAT_P (equiv_const
)
838 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (equiv_const
,
841 /* ??? what about memory */
843 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
844 case 'h': case 'j': case 'k': case 'l':
845 case 'q': case 't': case 'u':
846 case 'v': case 'w': case 'x': case 'y': case 'z':
847 case 'A': case 'B': case 'C': case 'D':
848 case 'Q': case 'R': case 'S': case 'T': case 'U':
849 case 'W': case 'Y': case 'Z':
852 : REG_CLASS_FROM_CONSTRAINT (c
, constraints
));
854 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
855 : (ira_class_singleton
[cl
][GET_MODE (op
)]
856 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
861 case '0': case '1': case '2': case '3': case '4':
862 case '5': case '6': case '7': case '8': case '9':
864 = single_reg_class (recog_data
.constraints
[c
- '0'],
865 recog_data
.operand
[c
- '0'], NULL_RTX
);
867 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
868 : (ira_class_singleton
[cl
][GET_MODE (op
)]
869 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
880 /* The function checks that operand OP_NUM of the current insn can use
881 only one hard register. If it is so, the function returns the
882 class of the hard register. Otherwise it returns NO_REGS. */
883 static enum reg_class
884 single_reg_operand_class (int op_num
)
886 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
888 return single_reg_class (recog_data
.constraints
[op_num
],
889 recog_data
.operand
[op_num
], NULL_RTX
);
892 /* The function sets up hard register set *SET to hard registers which
893 might be used by insn reloads because the constraints are too
896 ira_implicitly_set_insn_hard_regs (HARD_REG_SET
*set
)
901 enum machine_mode mode
;
903 CLEAR_HARD_REG_SET (*set
);
904 for (i
= 0; i
< recog_data
.n_operands
; i
++)
906 op
= recog_data
.operand
[i
];
908 if (GET_CODE (op
) == SUBREG
)
909 op
= SUBREG_REG (op
);
911 if (GET_CODE (op
) == SCRATCH
912 || (REG_P (op
) && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
))
914 const char *p
= recog_data
.constraints
[i
];
916 mode
= (GET_CODE (op
) == SCRATCH
917 ? GET_MODE (op
) : PSEUDO_REGNO_MODE (regno
));
919 alternative_mask enabled
= recog_data
.enabled_alternatives
;
920 for (; (c
= *p
); p
+= CONSTRAINT_LEN (c
, p
))
922 enabled
&= ~ALTERNATIVE_BIT (0);
925 else if (enabled
& 1)
929 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
930 case 'h': case 'j': case 'k': case 'l':
931 case 'q': case 't': case 'u':
932 case 'v': case 'w': case 'x': case 'y': case 'z':
933 case 'A': case 'B': case 'C': case 'D':
934 case 'Q': case 'R': case 'S': case 'T': case 'U':
935 case 'W': case 'Y': case 'Z':
938 : REG_CLASS_FROM_CONSTRAINT (c
, p
));
941 /* There is no register pressure problem if all of the
942 regs in this class are fixed. */
943 int regno
= ira_class_singleton
[cl
][mode
];
945 add_to_hard_reg_set (set
, mode
, regno
);
952 /* Processes input operands, if IN_P, or output operands otherwise of
953 the current insn with FREQ to find allocno which can use only one
954 hard register and makes other currently living allocnos conflicting
955 with the hard register. */
957 process_single_reg_class_operands (bool in_p
, int freq
)
963 ira_allocno_t operand_a
, a
;
965 for (i
= 0; i
< recog_data
.n_operands
; i
++)
967 operand
= recog_data
.operand
[i
];
968 if (in_p
&& recog_data
.operand_type
[i
] != OP_IN
969 && recog_data
.operand_type
[i
] != OP_INOUT
)
971 if (! in_p
&& recog_data
.operand_type
[i
] != OP_OUT
972 && recog_data
.operand_type
[i
] != OP_INOUT
)
974 cl
= single_reg_operand_class (i
);
980 if (GET_CODE (operand
) == SUBREG
)
981 operand
= SUBREG_REG (operand
);
984 && (regno
= REGNO (operand
)) >= FIRST_PSEUDO_REGISTER
)
986 enum reg_class aclass
;
988 operand_a
= ira_curr_regno_allocno_map
[regno
];
989 aclass
= ALLOCNO_CLASS (operand_a
);
990 if (ira_class_subset_p
[cl
][aclass
])
992 /* View the desired allocation of OPERAND as:
998 (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
999 enum machine_mode ymode
, xmode
;
1001 HOST_WIDE_INT offset
;
1003 xmode
= recog_data
.operand_mode
[i
];
1004 xregno
= ira_class_singleton
[cl
][xmode
];
1005 gcc_assert (xregno
>= 0);
1006 ymode
= ALLOCNO_MODE (operand_a
);
1007 offset
= subreg_lowpart_offset (ymode
, xmode
);
1008 yregno
= simplify_subreg_regno (xregno
, xmode
, offset
, ymode
);
1010 && ira_class_hard_reg_index
[aclass
][yregno
] >= 0)
1014 ira_allocate_and_set_costs
1015 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
),
1017 ira_init_register_move_cost_if_necessary (xmode
);
1019 ? ira_register_move_cost
[xmode
][aclass
][cl
]
1020 : ira_register_move_cost
[xmode
][cl
][aclass
]);
1021 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
)
1022 [ira_class_hard_reg_index
[aclass
][yregno
]] -= cost
;
1027 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
1029 ira_object_t obj
= ira_object_id_map
[px
];
1030 a
= OBJECT_ALLOCNO (obj
);
1033 /* We could increase costs of A instead of making it
1034 conflicting with the hard register. But it works worse
1035 because it will be spilled in reload in anyway. */
1036 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
1037 reg_class_contents
[cl
]);
1038 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
1039 reg_class_contents
[cl
]);
1045 /* Return true when one of the predecessor edges of BB is marked with
1046 EDGE_ABNORMAL_CALL or EDGE_EH. */
1048 bb_has_abnormal_call_pred (basic_block bb
)
1053 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
1055 if (e
->flags
& (EDGE_ABNORMAL_CALL
| EDGE_EH
))
1061 /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1062 we find a SET rtx that we can use to deduce that a register can be cheaply
1063 caller-saved. Return such a register, or NULL_RTX if none is found. */
1065 find_call_crossed_cheap_reg (rtx insn
)
1067 rtx cheap_reg
= NULL_RTX
;
1068 rtx exp
= CALL_INSN_FUNCTION_USAGE (insn
);
1072 rtx x
= XEXP (exp
, 0);
1073 if (GET_CODE (x
) == SET
)
1078 exp
= XEXP (exp
, 1);
1082 basic_block bb
= BLOCK_FOR_INSN (insn
);
1083 rtx reg
= SET_SRC (exp
);
1084 rtx prev
= PREV_INSN (insn
);
1085 while (prev
&& !(INSN_P (prev
)
1086 && BLOCK_FOR_INSN (prev
) != bb
))
1088 if (NONDEBUG_INSN_P (prev
))
1090 rtx set
= single_set (prev
);
1092 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
1094 rtx src
= SET_SRC (set
);
1095 if (!REG_P (src
) || HARD_REGISTER_P (src
)
1096 || !pseudo_regno_single_word_and_live_p (REGNO (src
)))
1098 if (!modified_between_p (src
, prev
, insn
))
1102 if (set
&& rtx_equal_p (SET_SRC (set
), reg
))
1104 rtx dest
= SET_DEST (set
);
1105 if (!REG_P (dest
) || HARD_REGISTER_P (dest
)
1106 || !pseudo_regno_single_word_and_live_p (REGNO (dest
)))
1108 if (!modified_between_p (dest
, prev
, insn
))
1113 if (reg_overlap_mentioned_p (reg
, PATTERN (prev
)))
1116 prev
= PREV_INSN (prev
);
1122 /* Process insns of the basic block given by its LOOP_TREE_NODE to
1123 update allocno live ranges, allocno hard register conflicts,
1124 intersected calls, and register pressure info for allocnos for the
1125 basic block for and regions containing the basic block. */
1127 process_bb_node_lives (ira_loop_tree_node_t loop_tree_node
)
1134 bitmap reg_live_out
;
1138 bb
= loop_tree_node
->bb
;
1141 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1143 curr_reg_pressure
[ira_pressure_classes
[i
]] = 0;
1144 high_pressure_start_point
[ira_pressure_classes
[i
]] = -1;
1146 curr_bb_node
= loop_tree_node
;
1147 reg_live_out
= df_get_live_out (bb
);
1148 sparseset_clear (objects_live
);
1149 REG_SET_TO_HARD_REG_SET (hard_regs_live
, reg_live_out
);
1150 AND_COMPL_HARD_REG_SET (hard_regs_live
, eliminable_regset
);
1151 AND_COMPL_HARD_REG_SET (hard_regs_live
, ira_no_alloc_regs
);
1152 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1153 if (TEST_HARD_REG_BIT (hard_regs_live
, i
))
1155 enum reg_class aclass
, pclass
, cl
;
1157 aclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (i
)];
1158 pclass
= ira_pressure_class_translate
[aclass
];
1160 (cl
= ira_reg_class_super_classes
[pclass
][j
])
1164 if (! ira_reg_pressure_class_p
[cl
])
1166 curr_reg_pressure
[cl
]++;
1167 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
1168 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
1169 ira_assert (curr_reg_pressure
[cl
]
1170 <= ira_class_hard_regs_num
[cl
]);
1173 EXECUTE_IF_SET_IN_BITMAP (reg_live_out
, FIRST_PSEUDO_REGISTER
, j
, bi
)
1174 mark_pseudo_regno_live (j
);
1176 freq
= REG_FREQ_FROM_BB (bb
);
1180 /* Invalidate all allocno_saved_at_call entries. */
1183 /* Scan the code of this basic block, noting which allocnos and
1184 hard regs are born or die.
1186 Note that this loop treats uninitialized values as live until
1187 the beginning of the block. For example, if an instruction
1188 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1189 set, FOO will remain live until the beginning of the block.
1190 Likewise if FOO is not set at all. This is unnecessarily
1191 pessimistic, but it probably doesn't matter much in practice. */
1192 FOR_BB_INSNS_REVERSE (bb
, insn
)
1194 df_ref
*def_rec
, *use_rec
;
1197 if (!NONDEBUG_INSN_P (insn
))
1200 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1201 fprintf (ira_dump_file
, " Insn %u(l%d): point = %d\n",
1202 INSN_UID (insn
), loop_tree_node
->parent
->loop_num
,
1205 /* Mark each defined value as live. We need to do this for
1206 unused values because they still conflict with quantities
1207 that are live at the time of the definition.
1209 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1210 references represent the effect of the called function
1211 on a call-clobbered register. Marking the register as
1212 live would stop us from allocating it to a call-crossing
1214 call_p
= CALL_P (insn
);
1215 for (def_rec
= DF_INSN_DEFS (insn
); *def_rec
; def_rec
++)
1216 if (!call_p
|| !DF_REF_FLAGS_IS_SET (*def_rec
, DF_REF_MAY_CLOBBER
))
1217 mark_ref_live (*def_rec
);
1219 /* If INSN has multiple outputs, then any value used in one
1220 of the outputs conflicts with the other outputs. Model this
1221 by making the used value live during the output phase.
1223 It is unsafe to use !single_set here since it will ignore
1224 an unused output. Just because an output is unused does
1225 not mean the compiler can assume the side effect will not
1226 occur. Consider if ALLOCNO appears in the address of an
1227 output and we reload the output. If we allocate ALLOCNO
1228 to the same hard register as an unused output we could
1229 set the hard register before the output reload insn. */
1230 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
1231 for (use_rec
= DF_INSN_USES (insn
); *use_rec
; use_rec
++)
1236 reg
= DF_REF_REG (*use_rec
);
1237 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
1241 set
= XVECEXP (PATTERN (insn
), 0, i
);
1242 if (GET_CODE (set
) == SET
1243 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1245 /* After the previous loop, this is a no-op if
1246 REG is contained within SET_DEST (SET). */
1247 mark_ref_live (*use_rec
);
1253 extract_insn (insn
);
1254 preprocess_constraints ();
1255 process_single_reg_class_operands (false, freq
);
1257 /* See which defined values die here. */
1258 for (def_rec
= DF_INSN_DEFS (insn
); *def_rec
; def_rec
++)
1259 if (!call_p
|| !DF_REF_FLAGS_IS_SET (*def_rec
, DF_REF_MAY_CLOBBER
))
1260 mark_ref_dead (*def_rec
);
1264 /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1265 there, try to find a pseudo that is live across the call but
1266 can be cheaply reconstructed from the return value. */
1267 rtx cheap_reg
= find_call_crossed_cheap_reg (insn
);
1268 if (cheap_reg
!= NULL_RTX
)
1269 add_reg_note (insn
, REG_RETURNED
, cheap_reg
);
1272 sparseset_clear (allocnos_processed
);
1273 /* The current set of live allocnos are live across the call. */
1274 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1276 ira_object_t obj
= ira_object_id_map
[i
];
1277 ira_allocno_t a
= OBJECT_ALLOCNO (obj
);
1278 int num
= ALLOCNO_NUM (a
);
1279 HARD_REG_SET this_call_used_reg_set
;
1281 get_call_reg_set_usage (insn
, &this_call_used_reg_set
,
1284 /* Don't allocate allocnos that cross setjmps or any
1285 call, if this function receives a nonlocal
1287 if (cfun
->has_nonlocal_label
1288 || find_reg_note (insn
, REG_SETJMP
,
1289 NULL_RTX
) != NULL_RTX
)
1291 SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
));
1292 SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
));
1294 if (can_throw_internal (insn
))
1296 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
1297 this_call_used_reg_set
);
1298 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
1299 this_call_used_reg_set
);
1302 if (sparseset_bit_p (allocnos_processed
, num
))
1304 sparseset_set_bit (allocnos_processed
, num
);
1306 if (allocno_saved_at_call
[num
] != last_call_num
)
1307 /* Here we are mimicking caller-save.c behaviour
1308 which does not save hard register at a call if
1309 it was saved on previous call in the same basic
1310 block and the hard register was not mentioned
1311 between the two calls. */
1312 ALLOCNO_CALL_FREQ (a
) += freq
;
1313 /* Mark it as saved at the next call. */
1314 allocno_saved_at_call
[num
] = last_call_num
+ 1;
1315 ALLOCNO_CALLS_CROSSED_NUM (a
)++;
1316 IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
),
1317 this_call_used_reg_set
);
1318 if (cheap_reg
!= NULL_RTX
1319 && ALLOCNO_REGNO (a
) == (int) REGNO (cheap_reg
))
1320 ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
)++;
1324 make_early_clobber_and_input_conflicts ();
1328 /* Mark each used value as live. */
1329 for (use_rec
= DF_INSN_USES (insn
); *use_rec
; use_rec
++)
1330 mark_ref_live (*use_rec
);
1332 process_single_reg_class_operands (true, freq
);
1334 set_p
= mark_hard_reg_early_clobbers (insn
, true);
1338 mark_hard_reg_early_clobbers (insn
, false);
1340 /* Mark each hard reg as live again. For example, a
1341 hard register can be in clobber and in an insn
1343 for (use_rec
= DF_INSN_USES (insn
); *use_rec
; use_rec
++)
1345 rtx ureg
= DF_REF_REG (*use_rec
);
1347 if (GET_CODE (ureg
) == SUBREG
)
1348 ureg
= SUBREG_REG (ureg
);
1349 if (! REG_P (ureg
) || REGNO (ureg
) >= FIRST_PSEUDO_REGISTER
)
1352 mark_ref_live (*use_rec
);
1359 #ifdef EH_RETURN_DATA_REGNO
1360 if (bb_has_eh_pred (bb
))
1363 unsigned int regno
= EH_RETURN_DATA_REGNO (j
);
1364 if (regno
== INVALID_REGNUM
)
1366 make_hard_regno_born (regno
);
1370 /* Allocnos can't go in stack regs at the start of a basic block
1371 that is reached by an abnormal edge. Likewise for call
1372 clobbered regs, because caller-save, fixup_abnormal_edges and
1373 possibly the table driven EH machinery are not quite ready to
1374 handle such allocnos live across such edges. */
1375 if (bb_has_abnormal_pred (bb
))
1378 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
1380 ira_allocno_t a
= OBJECT_ALLOCNO (ira_object_id_map
[px
]);
1382 ALLOCNO_NO_STACK_REG_P (a
) = true;
1383 ALLOCNO_TOTAL_NO_STACK_REG_P (a
) = true;
1385 for (px
= FIRST_STACK_REG
; px
<= LAST_STACK_REG
; px
++)
1386 make_hard_regno_born (px
);
1388 /* No need to record conflicts for call clobbered regs if we
1389 have nonlocal labels around, as we don't ever try to
1390 allocate such regs in this case. */
1391 if (!cfun
->has_nonlocal_label
&& bb_has_abnormal_call_pred (bb
))
1392 for (px
= 0; px
< FIRST_PSEUDO_REGISTER
; px
++)
1393 if (call_used_regs
[px
])
1394 make_hard_regno_born (px
);
1397 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1398 make_object_dead (ira_object_id_map
[i
]);
1403 /* Propagate register pressure to upper loop tree nodes: */
1404 if (loop_tree_node
!= ira_loop_tree_root
)
1405 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1407 enum reg_class pclass
;
1409 pclass
= ira_pressure_classes
[i
];
1410 if (loop_tree_node
->reg_pressure
[pclass
]
1411 > loop_tree_node
->parent
->reg_pressure
[pclass
])
1412 loop_tree_node
->parent
->reg_pressure
[pclass
]
1413 = loop_tree_node
->reg_pressure
[pclass
];
1417 /* Create and set up IRA_START_POINT_RANGES and
1418 IRA_FINISH_POINT_RANGES. */
1420 create_start_finish_chains (void)
1423 ira_object_iterator oi
;
1426 ira_start_point_ranges
1427 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1428 memset (ira_start_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1429 ira_finish_point_ranges
1430 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1431 memset (ira_finish_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1432 FOR_EACH_OBJECT (obj
, oi
)
1433 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1435 r
->start_next
= ira_start_point_ranges
[r
->start
];
1436 ira_start_point_ranges
[r
->start
] = r
;
1437 r
->finish_next
= ira_finish_point_ranges
[r
->finish
];
1438 ira_finish_point_ranges
[r
->finish
] = r
;
1442 /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1443 new live ranges and program points were added as a result if new
1446 ira_rebuild_start_finish_chains (void)
1448 ira_free (ira_finish_point_ranges
);
1449 ira_free (ira_start_point_ranges
);
1450 create_start_finish_chains ();
1453 /* Compress allocno live ranges by removing program points where
1456 remove_some_program_points_and_update_live_ranges (void)
1462 ira_object_iterator oi
;
1463 live_range_t r
, prev_r
, next_r
;
1464 sbitmap born_or_dead
, born
, dead
;
1465 sbitmap_iterator sbi
;
1466 bool born_p
, dead_p
, prev_born_p
, prev_dead_p
;
1468 born
= sbitmap_alloc (ira_max_point
);
1469 dead
= sbitmap_alloc (ira_max_point
);
1470 bitmap_clear (born
);
1471 bitmap_clear (dead
);
1472 FOR_EACH_OBJECT (obj
, oi
)
1473 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1475 ira_assert (r
->start
<= r
->finish
);
1476 bitmap_set_bit (born
, r
->start
);
1477 bitmap_set_bit (dead
, r
->finish
);
1480 born_or_dead
= sbitmap_alloc (ira_max_point
);
1481 bitmap_ior (born_or_dead
, born
, dead
);
1482 map
= (int *) ira_allocate (sizeof (int) * ira_max_point
);
1484 prev_born_p
= prev_dead_p
= false;
1485 EXECUTE_IF_SET_IN_BITMAP (born_or_dead
, 0, i
, sbi
)
1487 born_p
= bitmap_bit_p (born
, i
);
1488 dead_p
= bitmap_bit_p (dead
, i
);
1489 if ((prev_born_p
&& ! prev_dead_p
&& born_p
&& ! dead_p
)
1490 || (prev_dead_p
&& ! prev_born_p
&& dead_p
&& ! born_p
))
1494 prev_born_p
= born_p
;
1495 prev_dead_p
= dead_p
;
1497 sbitmap_free (born_or_dead
);
1498 sbitmap_free (born
);
1499 sbitmap_free (dead
);
1501 if (internal_flag_ira_verbose
> 1 && ira_dump_file
!= NULL
)
1502 fprintf (ira_dump_file
, "Compressing live ranges: from %d to %d - %d%%\n",
1503 ira_max_point
, n
, 100 * n
/ ira_max_point
);
1506 FOR_EACH_OBJECT (obj
, oi
)
1507 for (r
= OBJECT_LIVE_RANGES (obj
), prev_r
= NULL
; r
!= NULL
; r
= next_r
)
1510 r
->start
= map
[r
->start
];
1511 r
->finish
= map
[r
->finish
];
1512 if (prev_r
== NULL
|| prev_r
->start
> r
->finish
+ 1)
1517 prev_r
->start
= r
->start
;
1518 prev_r
->next
= next_r
;
1519 ira_finish_live_range (r
);
1525 /* Print live ranges R to file F. */
1527 ira_print_live_range_list (FILE *f
, live_range_t r
)
1529 for (; r
!= NULL
; r
= r
->next
)
1530 fprintf (f
, " [%d..%d]", r
->start
, r
->finish
);
1535 debug (live_range
&ref
)
1537 ira_print_live_range_list (stderr
, &ref
);
1541 debug (live_range
*ptr
)
1546 fprintf (stderr
, "<nil>\n");
1549 /* Print live ranges R to stderr. */
1551 ira_debug_live_range_list (live_range_t r
)
1553 ira_print_live_range_list (stderr
, r
);
1556 /* Print live ranges of object OBJ to file F. */
1558 print_object_live_ranges (FILE *f
, ira_object_t obj
)
1560 ira_print_live_range_list (f
, OBJECT_LIVE_RANGES (obj
));
1563 /* Print live ranges of allocno A to file F. */
1565 print_allocno_live_ranges (FILE *f
, ira_allocno_t a
)
1567 int n
= ALLOCNO_NUM_OBJECTS (a
);
1570 for (i
= 0; i
< n
; i
++)
1572 fprintf (f
, " a%d(r%d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
1574 fprintf (f
, " [%d]", i
);
1576 print_object_live_ranges (f
, ALLOCNO_OBJECT (a
, i
));
1580 /* Print live ranges of allocno A to stderr. */
1582 ira_debug_allocno_live_ranges (ira_allocno_t a
)
1584 print_allocno_live_ranges (stderr
, a
);
1587 /* Print live ranges of all allocnos to file F. */
1589 print_live_ranges (FILE *f
)
1592 ira_allocno_iterator ai
;
1594 FOR_EACH_ALLOCNO (a
, ai
)
1595 print_allocno_live_ranges (f
, a
);
1598 /* Print live ranges of all allocnos to stderr. */
1600 ira_debug_live_ranges (void)
1602 print_live_ranges (stderr
);
1605 /* The main entry function creates live ranges, set up
1606 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1607 calculate register pressure info. */
1609 ira_create_allocno_live_ranges (void)
1611 objects_live
= sparseset_alloc (ira_objects_num
);
1612 allocnos_processed
= sparseset_alloc (ira_allocnos_num
);
1615 allocno_saved_at_call
1616 = (int *) ira_allocate (ira_allocnos_num
* sizeof (int));
1617 memset (allocno_saved_at_call
, 0, ira_allocnos_num
* sizeof (int));
1618 ira_traverse_loop_tree (true, ira_loop_tree_root
, NULL
,
1619 process_bb_node_lives
);
1620 ira_max_point
= curr_point
;
1621 create_start_finish_chains ();
1622 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1623 print_live_ranges (ira_dump_file
);
1625 ira_free (allocno_saved_at_call
);
1626 sparseset_free (objects_live
);
1627 sparseset_free (allocnos_processed
);
1630 /* Compress allocno live ranges. */
1632 ira_compress_allocno_live_ranges (void)
1634 remove_some_program_points_and_update_live_ranges ();
1635 ira_rebuild_start_finish_chains ();
1636 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1638 fprintf (ira_dump_file
, "Ranges after the compression:\n");
1639 print_live_ranges (ira_dump_file
);
1643 /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1645 ira_finish_allocno_live_ranges (void)
1647 ira_free (ira_finish_point_ranges
);
1648 ira_free (ira_start_point_ranges
);