1 /* IRA processing allocno lives to build allocno live ranges.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "hard-reg-set.h"
32 #include "basic-block.h"
33 #include "insn-config.h"
35 #include "diagnostic-core.h"
39 #include "sparseset.h"
42 /* The code in this file is similar to one in global but the code
43 works on the allocno basis and creates live ranges instead of
44 pseudo-register conflicts. */
46 /* Program points are enumerated by numbers from range
47 0..IRA_MAX_POINT-1. There are approximately two times more program
48 points than insns. Program points are places in the program where
49 liveness info can be changed. In most general case (there are more
50 complicated cases too) some program points correspond to places
51 where input operand dies and other ones correspond to places where
52 output operands are born. */
55 /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
56 live ranges with given start/finish point. */
57 live_range_t
*ira_start_point_ranges
, *ira_finish_point_ranges
;
59 /* Number of the current program point. */
60 static int curr_point
;
62 /* Point where register pressure excess started or -1 if there is no
63 register pressure excess. Excess pressure for a register class at
64 some point means that there are more allocnos of given register
65 class living at the point than number of hard-registers of the
66 class available for the allocation. It is defined only for
68 static int high_pressure_start_point
[N_REG_CLASSES
];
70 /* Objects live at current point in the scan. */
71 static sparseset objects_live
;
73 /* A temporary bitmap used in functions that wish to avoid visiting an allocno
75 static sparseset allocnos_processed
;
77 /* Set of hard regs (except eliminable ones) currently live. */
78 static HARD_REG_SET hard_regs_live
;
80 /* The loop tree node corresponding to the current basic block. */
81 static ira_loop_tree_node_t curr_bb_node
;
83 /* The number of the last processed call. */
84 static int last_call_num
;
85 /* The number of last call at which given allocno was saved. */
86 static int *allocno_saved_at_call
;
88 /* Record the birth of hard register REGNO, updating hard_regs_live and
89 hard reg conflict information for living allocnos. */
91 make_hard_regno_born (int regno
)
95 SET_HARD_REG_BIT (hard_regs_live
, regno
);
96 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
98 ira_object_t obj
= ira_object_id_map
[i
];
100 SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj
), regno
);
101 SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
);
105 /* Process the death of hard register REGNO. This updates
108 make_hard_regno_dead (int regno
)
110 CLEAR_HARD_REG_BIT (hard_regs_live
, regno
);
113 /* Record the birth of object OBJ. Set a bit for it in objects_live,
114 start a new live range for it if necessary and update hard register
117 make_object_born (ira_object_t obj
)
119 live_range_t lr
= OBJECT_LIVE_RANGES (obj
);
121 sparseset_set_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
122 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
123 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), hard_regs_live
);
126 || (lr
->finish
!= curr_point
&& lr
->finish
+ 1 != curr_point
))
127 ira_add_live_range_to_object (obj
, curr_point
, -1);
130 /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
131 associated with object OBJ. */
133 update_allocno_pressure_excess_length (ira_object_t obj
)
135 ira_allocno_t a
= OBJECT_ALLOCNO (obj
);
137 enum reg_class aclass
, pclass
, cl
;
140 aclass
= ALLOCNO_CLASS (a
);
141 pclass
= ira_pressure_class_translate
[aclass
];
143 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
146 if (! ira_reg_pressure_class_p
[cl
])
148 if (high_pressure_start_point
[cl
] < 0)
150 p
= OBJECT_LIVE_RANGES (obj
);
151 ira_assert (p
!= NULL
);
152 start
= (high_pressure_start_point
[cl
] > p
->start
153 ? high_pressure_start_point
[cl
] : p
->start
);
154 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a
) += curr_point
- start
+ 1;
158 /* Process the death of object OBJ, which is associated with allocno
159 A. This finishes the current live range for it. */
161 make_object_dead (ira_object_t obj
)
165 sparseset_clear_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
166 lr
= OBJECT_LIVE_RANGES (obj
);
167 ira_assert (lr
!= NULL
);
168 lr
->finish
= curr_point
;
169 update_allocno_pressure_excess_length (obj
);
172 /* The current register pressures for each pressure class for the current
174 static int curr_reg_pressure
[N_REG_CLASSES
];
176 /* Record that register pressure for PCLASS increased by N registers.
177 Update the current register pressure, maximal register pressure for
178 the current BB and the start point of the register pressure
181 inc_register_pressure (enum reg_class pclass
, int n
)
187 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
190 if (! ira_reg_pressure_class_p
[cl
])
192 curr_reg_pressure
[cl
] += n
;
193 if (high_pressure_start_point
[cl
] < 0
194 && (curr_reg_pressure
[cl
] > ira_class_hard_regs_num
[cl
]))
195 high_pressure_start_point
[cl
] = curr_point
;
196 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
197 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
201 /* Record that register pressure for PCLASS has decreased by NREGS
202 registers; update current register pressure, start point of the
203 register pressure excess, and register pressure excess length for
207 dec_register_pressure (enum reg_class pclass
, int nregs
)
215 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
218 if (! ira_reg_pressure_class_p
[cl
])
220 curr_reg_pressure
[cl
] -= nregs
;
221 ira_assert (curr_reg_pressure
[cl
] >= 0);
222 if (high_pressure_start_point
[cl
] >= 0
223 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
228 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, j
)
229 update_allocno_pressure_excess_length (ira_object_id_map
[j
]);
231 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
234 if (! ira_reg_pressure_class_p
[cl
])
236 if (high_pressure_start_point
[cl
] >= 0
237 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
238 high_pressure_start_point
[cl
] = -1;
243 /* Determine from the objects_live bitmap whether REGNO is currently live,
244 and occupies only one object. Return false if we have no information. */
246 pseudo_regno_single_word_and_live_p (int regno
)
248 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
253 if (ALLOCNO_NUM_OBJECTS (a
) > 1)
256 obj
= ALLOCNO_OBJECT (a
, 0);
258 return sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
));
261 /* Mark the pseudo register REGNO as live. Update all information about
262 live ranges and register pressure. */
264 mark_pseudo_regno_live (int regno
)
266 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
267 enum reg_class pclass
;
273 /* Invalidate because it is referenced. */
274 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
276 n
= ALLOCNO_NUM_OBJECTS (a
);
277 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
278 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
281 /* We track every subobject separately. */
282 gcc_assert (nregs
== n
);
286 for (i
= 0; i
< n
; i
++)
288 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
290 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
293 inc_register_pressure (pclass
, nregs
);
294 make_object_born (obj
);
298 /* Like mark_pseudo_regno_live, but try to only mark one subword of
299 the pseudo as live. SUBWORD indicates which; a value of 0
300 indicates the low part. */
302 mark_pseudo_regno_subword_live (int regno
, int subword
)
304 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
306 enum reg_class pclass
;
312 /* Invalidate because it is referenced. */
313 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
315 n
= ALLOCNO_NUM_OBJECTS (a
);
318 mark_pseudo_regno_live (regno
);
322 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
324 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
325 obj
= ALLOCNO_OBJECT (a
, subword
);
327 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
330 inc_register_pressure (pclass
, 1);
331 make_object_born (obj
);
334 /* Mark the register REG as live. Store a 1 in hard_regs_live for
335 this register, record how many consecutive hardware registers it
338 mark_hard_reg_live (rtx reg
)
340 int regno
= REGNO (reg
);
342 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
344 int last
= regno
+ hard_regno_nregs
[regno
][GET_MODE (reg
)];
345 enum reg_class aclass
, pclass
;
349 if (! TEST_HARD_REG_BIT (hard_regs_live
, regno
)
350 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
352 aclass
= ira_hard_regno_allocno_class
[regno
];
353 pclass
= ira_pressure_class_translate
[aclass
];
354 inc_register_pressure (pclass
, 1);
355 make_hard_regno_born (regno
);
362 /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
363 register number; ORIG_REG is the access in the insn, which may be a
366 mark_pseudo_reg_live (rtx orig_reg
, unsigned regno
)
368 if (df_read_modify_subreg_p (orig_reg
))
370 mark_pseudo_regno_subword_live (regno
,
371 subreg_lowpart_p (orig_reg
) ? 0 : 1);
374 mark_pseudo_regno_live (regno
);
377 /* Mark the register referenced by use or def REF as live. */
379 mark_ref_live (df_ref ref
)
381 rtx reg
= DF_REF_REG (ref
);
384 if (GET_CODE (reg
) == SUBREG
)
385 reg
= SUBREG_REG (reg
);
387 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
388 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
390 mark_hard_reg_live (reg
);
393 /* Mark the pseudo register REGNO as dead. Update all information about
394 live ranges and register pressure. */
396 mark_pseudo_regno_dead (int regno
)
398 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
405 /* Invalidate because it is referenced. */
406 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
408 n
= ALLOCNO_NUM_OBJECTS (a
);
409 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
410 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
413 /* We track every subobject separately. */
414 gcc_assert (nregs
== n
);
417 for (i
= 0; i
< n
; i
++)
419 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
420 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
423 dec_register_pressure (cl
, nregs
);
424 make_object_dead (obj
);
428 /* Like mark_pseudo_regno_dead, but called when we know that only part of the
429 register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
431 mark_pseudo_regno_subword_dead (int regno
, int subword
)
433 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
441 /* Invalidate because it is referenced. */
442 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
444 n
= ALLOCNO_NUM_OBJECTS (a
);
446 /* The allocno as a whole doesn't die in this case. */
449 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
451 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
453 obj
= ALLOCNO_OBJECT (a
, subword
);
454 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
457 dec_register_pressure (cl
, 1);
458 make_object_dead (obj
);
461 /* Mark the hard register REG as dead. Store a 0 in hard_regs_live for the
464 mark_hard_reg_dead (rtx reg
)
466 int regno
= REGNO (reg
);
468 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
470 int last
= regno
+ hard_regno_nregs
[regno
][GET_MODE (reg
)];
471 enum reg_class aclass
, pclass
;
475 if (TEST_HARD_REG_BIT (hard_regs_live
, regno
))
477 aclass
= ira_hard_regno_allocno_class
[regno
];
478 pclass
= ira_pressure_class_translate
[aclass
];
479 dec_register_pressure (pclass
, 1);
480 make_hard_regno_dead (regno
);
487 /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
488 register number; ORIG_REG is the access in the insn, which may be a
491 mark_pseudo_reg_dead (rtx orig_reg
, unsigned regno
)
493 if (df_read_modify_subreg_p (orig_reg
))
495 mark_pseudo_regno_subword_dead (regno
,
496 subreg_lowpart_p (orig_reg
) ? 0 : 1);
499 mark_pseudo_regno_dead (regno
);
502 /* Mark the register referenced by definition DEF as dead, if the
503 definition is a total one. */
505 mark_ref_dead (df_ref def
)
507 rtx reg
= DF_REF_REG (def
);
510 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
))
513 if (GET_CODE (reg
) == SUBREG
)
514 reg
= SUBREG_REG (reg
);
516 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
)
517 && (GET_CODE (orig_reg
) != SUBREG
518 || REGNO (reg
) < FIRST_PSEUDO_REGISTER
519 || !df_read_modify_subreg_p (orig_reg
)))
522 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
523 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
525 mark_hard_reg_dead (reg
);
528 /* If REG is a pseudo or a subreg of it, and the class of its allocno
529 intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
530 rtx actually accessed, it may be identical to DREG or a subreg of it.
531 Advance the current program point before making the conflict if
532 ADVANCE_P. Return TRUE if we will need to advance the current
535 make_pseudo_conflict (rtx reg
, enum reg_class cl
, rtx dreg
, rtx orig_dreg
,
541 if (GET_CODE (reg
) == SUBREG
)
542 reg
= SUBREG_REG (reg
);
544 if (! REG_P (reg
) || REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
547 a
= ira_curr_regno_allocno_map
[REGNO (reg
)];
548 if (! reg_classes_intersect_p (cl
, ALLOCNO_CLASS (a
)))
554 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
555 mark_pseudo_reg_live (orig_dreg
, REGNO (dreg
));
556 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
557 mark_pseudo_reg_dead (orig_dreg
, REGNO (dreg
));
562 /* Check and make if necessary conflicts for pseudo DREG of class
563 DEF_CL of the current insn with input operand USE of class USE_CL.
564 ORIG_DREG is the rtx actually accessed, it may be identical to
565 DREG or a subreg of it. Advance the current program point before
566 making the conflict if ADVANCE_P. Return TRUE if we will need to
567 advance the current program point. */
569 check_and_make_def_use_conflict (rtx dreg
, rtx orig_dreg
,
570 enum reg_class def_cl
, int use
,
571 enum reg_class use_cl
, bool advance_p
)
573 if (! reg_classes_intersect_p (def_cl
, use_cl
))
576 advance_p
= make_pseudo_conflict (recog_data
.operand
[use
],
577 use_cl
, dreg
, orig_dreg
, advance_p
);
579 /* Reload may end up swapping commutative operands, so you
580 have to take both orderings into account. The
581 constraints for the two operands can be completely
582 different. (Indeed, if the constraints for the two
583 operands are the same for all alternatives, there's no
584 point marking them as commutative.) */
585 if (use
< recog_data
.n_operands
- 1
586 && recog_data
.constraints
[use
][0] == '%')
588 = make_pseudo_conflict (recog_data
.operand
[use
+ 1],
589 use_cl
, dreg
, orig_dreg
, advance_p
);
591 && recog_data
.constraints
[use
- 1][0] == '%')
593 = make_pseudo_conflict (recog_data
.operand
[use
- 1],
594 use_cl
, dreg
, orig_dreg
, advance_p
);
598 /* Check and make if necessary conflicts for definition DEF of class
599 DEF_CL of the current insn with input operands. Process only
600 constraints of alternative ALT. */
602 check_and_make_def_conflict (int alt
, int def
, enum reg_class def_cl
)
606 enum reg_class use_cl
, acl
;
608 rtx dreg
= recog_data
.operand
[def
];
609 rtx orig_dreg
= dreg
;
611 if (def_cl
== NO_REGS
)
614 if (GET_CODE (dreg
) == SUBREG
)
615 dreg
= SUBREG_REG (dreg
);
617 if (! REG_P (dreg
) || REGNO (dreg
) < FIRST_PSEUDO_REGISTER
)
620 a
= ira_curr_regno_allocno_map
[REGNO (dreg
)];
621 acl
= ALLOCNO_CLASS (a
);
622 if (! reg_classes_intersect_p (acl
, def_cl
))
627 int n_operands
= recog_data
.n_operands
;
628 const operand_alternative
*op_alt
= &recog_op_alt
[alt
* n_operands
];
629 for (use
= 0; use
< n_operands
; use
++)
633 if (use
== def
|| recog_data
.operand_type
[use
] == OP_OUT
)
636 if (op_alt
[use
].anything_ok
)
639 use_cl
= op_alt
[use
].cl
;
641 /* If there's any alternative that allows USE to match DEF, do not
642 record a conflict. If that causes us to create an invalid
643 instruction due to the earlyclobber, reload must fix it up. */
644 alternative_mask enabled
= recog_data
.enabled_alternatives
;
645 for (alt1
= 0; alt1
< recog_data
.n_alternatives
; alt1
++)
647 if (!TEST_BIT (enabled
, alt1
))
649 const operand_alternative
*op_alt1
650 = &recog_op_alt
[alt1
* n_operands
];
651 if (op_alt1
[use
].matches
== def
652 || (use
< n_operands
- 1
653 && recog_data
.constraints
[use
][0] == '%'
654 && op_alt1
[use
+ 1].matches
== def
)
656 && recog_data
.constraints
[use
- 1][0] == '%'
657 && op_alt1
[use
- 1].matches
== def
))
661 if (alt1
< recog_data
.n_alternatives
)
664 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
665 use
, use_cl
, advance_p
);
667 if ((use_match
= op_alt
[use
].matches
) >= 0)
669 if (use_match
== def
)
672 if (op_alt
[use_match
].anything_ok
)
675 use_cl
= op_alt
[use_match
].cl
;
676 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
677 use
, use_cl
, advance_p
);
682 /* Make conflicts of early clobber pseudo registers of the current
683 insn with its inputs. Avoid introducing unnecessary conflicts by
684 checking classes of the constraints and pseudos because otherwise
685 significant code degradation is possible for some targets. */
687 make_early_clobber_and_input_conflicts (void)
691 enum reg_class def_cl
;
693 int n_alternatives
= recog_data
.n_alternatives
;
694 int n_operands
= recog_data
.n_operands
;
695 alternative_mask enabled
= recog_data
.enabled_alternatives
;
696 const operand_alternative
*op_alt
= recog_op_alt
;
697 for (alt
= 0; alt
< n_alternatives
; alt
++, op_alt
+= n_operands
)
698 if (TEST_BIT (enabled
, alt
))
699 for (def
= 0; def
< n_operands
; def
++)
702 if (op_alt
[def
].earlyclobber
)
704 if (op_alt
[def
].anything_ok
)
707 def_cl
= op_alt
[def
].cl
;
708 check_and_make_def_conflict (alt
, def
, def_cl
);
710 if ((def_match
= op_alt
[def
].matches
) >= 0
711 && (op_alt
[def_match
].earlyclobber
712 || op_alt
[def
].earlyclobber
))
714 if (op_alt
[def_match
].anything_ok
)
717 def_cl
= op_alt
[def_match
].cl
;
718 check_and_make_def_conflict (alt
, def
, def_cl
);
723 /* Mark early clobber hard registers of the current INSN as live (if
724 LIVE_P) or dead. Return true if there are such registers. */
726 mark_hard_reg_early_clobbers (rtx insn
, bool live_p
)
731 for (def_rec
= DF_INSN_DEFS (insn
); *def_rec
; def_rec
++)
732 if (DF_REF_FLAGS_IS_SET (*def_rec
, DF_REF_MUST_CLOBBER
))
734 rtx dreg
= DF_REF_REG (*def_rec
);
736 if (GET_CODE (dreg
) == SUBREG
)
737 dreg
= SUBREG_REG (dreg
);
738 if (! REG_P (dreg
) || REGNO (dreg
) >= FIRST_PSEUDO_REGISTER
)
741 /* Hard register clobbers are believed to be early clobber
742 because there is no way to say that non-operand hard
743 register clobbers are not early ones. */
745 mark_ref_live (*def_rec
);
747 mark_ref_dead (*def_rec
);
754 /* Checks that CONSTRAINTS permits to use only one hard register. If
755 it is so, the function returns the class of the hard register.
756 Otherwise it returns NO_REGS. */
757 static enum reg_class
758 single_reg_class (const char *constraints
, rtx op
, rtx equiv_const
)
761 enum reg_class cl
, next_cl
;
762 enum constraint_num cn
;
765 alternative_mask enabled
= recog_data
.enabled_alternatives
;
766 for (; (c
= *constraints
); constraints
+= CONSTRAINT_LEN (c
, constraints
))
768 enabled
&= ~ALTERNATIVE_BIT (0);
771 else if (enabled
& 1)
786 || (equiv_const
!= NULL_RTX
&& CONSTANT_P (equiv_const
)))
791 if (CONST_SCALAR_INT_P (op
)
792 || (equiv_const
!= NULL_RTX
&& CONST_SCALAR_INT_P (equiv_const
)))
797 if ((CONSTANT_P (op
) && !CONST_SCALAR_INT_P (op
))
798 || (equiv_const
!= NULL_RTX
799 && CONSTANT_P (equiv_const
)
800 && !CONST_SCALAR_INT_P (equiv_const
)))
806 if (CONST_DOUBLE_AS_FLOAT_P (op
)
807 || (GET_CODE (op
) == CONST_VECTOR
808 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_VECTOR_FLOAT
)
809 || (equiv_const
!= NULL_RTX
810 && (CONST_DOUBLE_AS_FLOAT_P (equiv_const
)
811 || (GET_CODE (equiv_const
) == CONST_VECTOR
812 && (GET_MODE_CLASS (GET_MODE (equiv_const
))
813 == MODE_VECTOR_FLOAT
)))))
817 case 'I': case 'J': case 'K': case 'L': case 'M': case 'N':
821 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
822 case 'h': case 'j': case 'k': case 'l':
823 case 'q': case 't': case 'u':
824 case 'v': case 'w': case 'x': case 'y': case 'z':
825 case 'A': case 'B': case 'C': case 'D':
826 case 'Q': case 'R': case 'S': case 'T': case 'U':
827 case 'W': case 'Y': case 'Z':
828 /* ??? Is this the best way to handle memory constraints? */
829 cn
= lookup_constraint (constraints
);
830 if (insn_extra_memory_constraint (cn
)
831 || insn_extra_address_constraint (cn
))
833 if (constraint_satisfied_p (op
, cn
)
834 || (equiv_const
!= NULL_RTX
835 && CONSTANT_P (equiv_const
)
836 && constraint_satisfied_p (equiv_const
, cn
)))
840 : reg_class_for_constraint (cn
));
841 if (next_cl
== NO_REGS
)
844 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
845 : (ira_class_singleton
[cl
][GET_MODE (op
)]
846 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
851 case '0': case '1': case '2': case '3': case '4':
852 case '5': case '6': case '7': case '8': case '9':
854 = single_reg_class (recog_data
.constraints
[c
- '0'],
855 recog_data
.operand
[c
- '0'], NULL_RTX
);
857 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
858 : (ira_class_singleton
[cl
][GET_MODE (op
)]
859 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
870 /* The function checks that operand OP_NUM of the current insn can use
871 only one hard register. If it is so, the function returns the
872 class of the hard register. Otherwise it returns NO_REGS. */
873 static enum reg_class
874 single_reg_operand_class (int op_num
)
876 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
878 return single_reg_class (recog_data
.constraints
[op_num
],
879 recog_data
.operand
[op_num
], NULL_RTX
);
882 /* The function sets up hard register set *SET to hard registers which
883 might be used by insn reloads because the constraints are too
886 ira_implicitly_set_insn_hard_regs (HARD_REG_SET
*set
)
891 enum machine_mode mode
;
893 CLEAR_HARD_REG_SET (*set
);
894 for (i
= 0; i
< recog_data
.n_operands
; i
++)
896 op
= recog_data
.operand
[i
];
898 if (GET_CODE (op
) == SUBREG
)
899 op
= SUBREG_REG (op
);
901 if (GET_CODE (op
) == SCRATCH
902 || (REG_P (op
) && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
))
904 const char *p
= recog_data
.constraints
[i
];
906 mode
= (GET_CODE (op
) == SCRATCH
907 ? GET_MODE (op
) : PSEUDO_REGNO_MODE (regno
));
909 alternative_mask enabled
= recog_data
.enabled_alternatives
;
910 for (; (c
= *p
); p
+= CONSTRAINT_LEN (c
, p
))
912 enabled
&= ~ALTERNATIVE_BIT (0);
915 else if (enabled
& 1)
919 case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
920 case 'h': case 'j': case 'k': case 'l':
921 case 'q': case 't': case 'u':
922 case 'v': case 'w': case 'x': case 'y': case 'z':
923 case 'A': case 'B': case 'C': case 'D':
924 case 'Q': case 'R': case 'S': case 'T': case 'U':
925 case 'W': case 'Y': case 'Z':
928 : reg_class_for_constraint (lookup_constraint (p
)));
931 /* There is no register pressure problem if all of the
932 regs in this class are fixed. */
933 int regno
= ira_class_singleton
[cl
][mode
];
935 add_to_hard_reg_set (set
, mode
, regno
);
942 /* Processes input operands, if IN_P, or output operands otherwise of
943 the current insn with FREQ to find allocno which can use only one
944 hard register and makes other currently living allocnos conflicting
945 with the hard register. */
947 process_single_reg_class_operands (bool in_p
, int freq
)
953 ira_allocno_t operand_a
, a
;
955 for (i
= 0; i
< recog_data
.n_operands
; i
++)
957 operand
= recog_data
.operand
[i
];
958 if (in_p
&& recog_data
.operand_type
[i
] != OP_IN
959 && recog_data
.operand_type
[i
] != OP_INOUT
)
961 if (! in_p
&& recog_data
.operand_type
[i
] != OP_OUT
962 && recog_data
.operand_type
[i
] != OP_INOUT
)
964 cl
= single_reg_operand_class (i
);
970 if (GET_CODE (operand
) == SUBREG
)
971 operand
= SUBREG_REG (operand
);
974 && (regno
= REGNO (operand
)) >= FIRST_PSEUDO_REGISTER
)
976 enum reg_class aclass
;
978 operand_a
= ira_curr_regno_allocno_map
[regno
];
979 aclass
= ALLOCNO_CLASS (operand_a
);
980 if (ira_class_subset_p
[cl
][aclass
])
982 /* View the desired allocation of OPERAND as:
988 (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
989 enum machine_mode ymode
, xmode
;
991 HOST_WIDE_INT offset
;
993 xmode
= recog_data
.operand_mode
[i
];
994 xregno
= ira_class_singleton
[cl
][xmode
];
995 gcc_assert (xregno
>= 0);
996 ymode
= ALLOCNO_MODE (operand_a
);
997 offset
= subreg_lowpart_offset (ymode
, xmode
);
998 yregno
= simplify_subreg_regno (xregno
, xmode
, offset
, ymode
);
1000 && ira_class_hard_reg_index
[aclass
][yregno
] >= 0)
1004 ira_allocate_and_set_costs
1005 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
),
1007 ira_init_register_move_cost_if_necessary (xmode
);
1009 ? ira_register_move_cost
[xmode
][aclass
][cl
]
1010 : ira_register_move_cost
[xmode
][cl
][aclass
]);
1011 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
)
1012 [ira_class_hard_reg_index
[aclass
][yregno
]] -= cost
;
1017 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
1019 ira_object_t obj
= ira_object_id_map
[px
];
1020 a
= OBJECT_ALLOCNO (obj
);
1023 /* We could increase costs of A instead of making it
1024 conflicting with the hard register. But it works worse
1025 because it will be spilled in reload in anyway. */
1026 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
1027 reg_class_contents
[cl
]);
1028 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
1029 reg_class_contents
[cl
]);
1035 /* Return true when one of the predecessor edges of BB is marked with
1036 EDGE_ABNORMAL_CALL or EDGE_EH. */
1038 bb_has_abnormal_call_pred (basic_block bb
)
1043 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
1045 if (e
->flags
& (EDGE_ABNORMAL_CALL
| EDGE_EH
))
1051 /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1052 we find a SET rtx that we can use to deduce that a register can be cheaply
1053 caller-saved. Return such a register, or NULL_RTX if none is found. */
1055 find_call_crossed_cheap_reg (rtx insn
)
1057 rtx cheap_reg
= NULL_RTX
;
1058 rtx exp
= CALL_INSN_FUNCTION_USAGE (insn
);
1062 rtx x
= XEXP (exp
, 0);
1063 if (GET_CODE (x
) == SET
)
1068 exp
= XEXP (exp
, 1);
1072 basic_block bb
= BLOCK_FOR_INSN (insn
);
1073 rtx reg
= SET_SRC (exp
);
1074 rtx prev
= PREV_INSN (insn
);
1075 while (prev
&& !(INSN_P (prev
)
1076 && BLOCK_FOR_INSN (prev
) != bb
))
1078 if (NONDEBUG_INSN_P (prev
))
1080 rtx set
= single_set (prev
);
1082 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
1084 rtx src
= SET_SRC (set
);
1085 if (!REG_P (src
) || HARD_REGISTER_P (src
)
1086 || !pseudo_regno_single_word_and_live_p (REGNO (src
)))
1088 if (!modified_between_p (src
, prev
, insn
))
1092 if (set
&& rtx_equal_p (SET_SRC (set
), reg
))
1094 rtx dest
= SET_DEST (set
);
1095 if (!REG_P (dest
) || HARD_REGISTER_P (dest
)
1096 || !pseudo_regno_single_word_and_live_p (REGNO (dest
)))
1098 if (!modified_between_p (dest
, prev
, insn
))
1103 if (reg_overlap_mentioned_p (reg
, PATTERN (prev
)))
1106 prev
= PREV_INSN (prev
);
1112 /* Process insns of the basic block given by its LOOP_TREE_NODE to
1113 update allocno live ranges, allocno hard register conflicts,
1114 intersected calls, and register pressure info for allocnos for the
1115 basic block for and regions containing the basic block. */
1117 process_bb_node_lives (ira_loop_tree_node_t loop_tree_node
)
1124 bitmap reg_live_out
;
1128 bb
= loop_tree_node
->bb
;
1131 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1133 curr_reg_pressure
[ira_pressure_classes
[i
]] = 0;
1134 high_pressure_start_point
[ira_pressure_classes
[i
]] = -1;
1136 curr_bb_node
= loop_tree_node
;
1137 reg_live_out
= df_get_live_out (bb
);
1138 sparseset_clear (objects_live
);
1139 REG_SET_TO_HARD_REG_SET (hard_regs_live
, reg_live_out
);
1140 AND_COMPL_HARD_REG_SET (hard_regs_live
, eliminable_regset
);
1141 AND_COMPL_HARD_REG_SET (hard_regs_live
, ira_no_alloc_regs
);
1142 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1143 if (TEST_HARD_REG_BIT (hard_regs_live
, i
))
1145 enum reg_class aclass
, pclass
, cl
;
1147 aclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (i
)];
1148 pclass
= ira_pressure_class_translate
[aclass
];
1150 (cl
= ira_reg_class_super_classes
[pclass
][j
])
1154 if (! ira_reg_pressure_class_p
[cl
])
1156 curr_reg_pressure
[cl
]++;
1157 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
1158 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
1159 ira_assert (curr_reg_pressure
[cl
]
1160 <= ira_class_hard_regs_num
[cl
]);
1163 EXECUTE_IF_SET_IN_BITMAP (reg_live_out
, FIRST_PSEUDO_REGISTER
, j
, bi
)
1164 mark_pseudo_regno_live (j
);
1166 freq
= REG_FREQ_FROM_BB (bb
);
1170 /* Invalidate all allocno_saved_at_call entries. */
1173 /* Scan the code of this basic block, noting which allocnos and
1174 hard regs are born or die.
1176 Note that this loop treats uninitialized values as live until
1177 the beginning of the block. For example, if an instruction
1178 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1179 set, FOO will remain live until the beginning of the block.
1180 Likewise if FOO is not set at all. This is unnecessarily
1181 pessimistic, but it probably doesn't matter much in practice. */
1182 FOR_BB_INSNS_REVERSE (bb
, insn
)
1184 df_ref
*def_rec
, *use_rec
;
1187 if (!NONDEBUG_INSN_P (insn
))
1190 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1191 fprintf (ira_dump_file
, " Insn %u(l%d): point = %d\n",
1192 INSN_UID (insn
), loop_tree_node
->parent
->loop_num
,
1195 /* Mark each defined value as live. We need to do this for
1196 unused values because they still conflict with quantities
1197 that are live at the time of the definition.
1199 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1200 references represent the effect of the called function
1201 on a call-clobbered register. Marking the register as
1202 live would stop us from allocating it to a call-crossing
1204 call_p
= CALL_P (insn
);
1205 for (def_rec
= DF_INSN_DEFS (insn
); *def_rec
; def_rec
++)
1206 if (!call_p
|| !DF_REF_FLAGS_IS_SET (*def_rec
, DF_REF_MAY_CLOBBER
))
1207 mark_ref_live (*def_rec
);
1209 /* If INSN has multiple outputs, then any value used in one
1210 of the outputs conflicts with the other outputs. Model this
1211 by making the used value live during the output phase.
1213 It is unsafe to use !single_set here since it will ignore
1214 an unused output. Just because an output is unused does
1215 not mean the compiler can assume the side effect will not
1216 occur. Consider if ALLOCNO appears in the address of an
1217 output and we reload the output. If we allocate ALLOCNO
1218 to the same hard register as an unused output we could
1219 set the hard register before the output reload insn. */
1220 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
1221 for (use_rec
= DF_INSN_USES (insn
); *use_rec
; use_rec
++)
1226 reg
= DF_REF_REG (*use_rec
);
1227 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
1231 set
= XVECEXP (PATTERN (insn
), 0, i
);
1232 if (GET_CODE (set
) == SET
1233 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1235 /* After the previous loop, this is a no-op if
1236 REG is contained within SET_DEST (SET). */
1237 mark_ref_live (*use_rec
);
1243 extract_insn (insn
);
1244 preprocess_constraints (insn
);
1245 process_single_reg_class_operands (false, freq
);
1247 /* See which defined values die here. */
1248 for (def_rec
= DF_INSN_DEFS (insn
); *def_rec
; def_rec
++)
1249 if (!call_p
|| !DF_REF_FLAGS_IS_SET (*def_rec
, DF_REF_MAY_CLOBBER
))
1250 mark_ref_dead (*def_rec
);
1254 /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1255 there, try to find a pseudo that is live across the call but
1256 can be cheaply reconstructed from the return value. */
1257 rtx cheap_reg
= find_call_crossed_cheap_reg (insn
);
1258 if (cheap_reg
!= NULL_RTX
)
1259 add_reg_note (insn
, REG_RETURNED
, cheap_reg
);
1262 sparseset_clear (allocnos_processed
);
1263 /* The current set of live allocnos are live across the call. */
1264 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1266 ira_object_t obj
= ira_object_id_map
[i
];
1267 ira_allocno_t a
= OBJECT_ALLOCNO (obj
);
1268 int num
= ALLOCNO_NUM (a
);
1269 HARD_REG_SET this_call_used_reg_set
;
1271 get_call_reg_set_usage (insn
, &this_call_used_reg_set
,
1274 /* Don't allocate allocnos that cross setjmps or any
1275 call, if this function receives a nonlocal
1277 if (cfun
->has_nonlocal_label
1278 || find_reg_note (insn
, REG_SETJMP
,
1279 NULL_RTX
) != NULL_RTX
)
1281 SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
));
1282 SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
));
1284 if (can_throw_internal (insn
))
1286 IOR_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
),
1287 this_call_used_reg_set
);
1288 IOR_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
1289 this_call_used_reg_set
);
1292 if (sparseset_bit_p (allocnos_processed
, num
))
1294 sparseset_set_bit (allocnos_processed
, num
);
1296 if (allocno_saved_at_call
[num
] != last_call_num
)
1297 /* Here we are mimicking caller-save.c behaviour
1298 which does not save hard register at a call if
1299 it was saved on previous call in the same basic
1300 block and the hard register was not mentioned
1301 between the two calls. */
1302 ALLOCNO_CALL_FREQ (a
) += freq
;
1303 /* Mark it as saved at the next call. */
1304 allocno_saved_at_call
[num
] = last_call_num
+ 1;
1305 ALLOCNO_CALLS_CROSSED_NUM (a
)++;
1306 IOR_HARD_REG_SET (ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
),
1307 this_call_used_reg_set
);
1308 if (cheap_reg
!= NULL_RTX
1309 && ALLOCNO_REGNO (a
) == (int) REGNO (cheap_reg
))
1310 ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
)++;
1314 make_early_clobber_and_input_conflicts ();
1318 /* Mark each used value as live. */
1319 for (use_rec
= DF_INSN_USES (insn
); *use_rec
; use_rec
++)
1320 mark_ref_live (*use_rec
);
1322 process_single_reg_class_operands (true, freq
);
1324 set_p
= mark_hard_reg_early_clobbers (insn
, true);
1328 mark_hard_reg_early_clobbers (insn
, false);
1330 /* Mark each hard reg as live again. For example, a
1331 hard register can be in clobber and in an insn
1333 for (use_rec
= DF_INSN_USES (insn
); *use_rec
; use_rec
++)
1335 rtx ureg
= DF_REF_REG (*use_rec
);
1337 if (GET_CODE (ureg
) == SUBREG
)
1338 ureg
= SUBREG_REG (ureg
);
1339 if (! REG_P (ureg
) || REGNO (ureg
) >= FIRST_PSEUDO_REGISTER
)
1342 mark_ref_live (*use_rec
);
1349 #ifdef EH_RETURN_DATA_REGNO
1350 if (bb_has_eh_pred (bb
))
1353 unsigned int regno
= EH_RETURN_DATA_REGNO (j
);
1354 if (regno
== INVALID_REGNUM
)
1356 make_hard_regno_born (regno
);
1360 /* Allocnos can't go in stack regs at the start of a basic block
1361 that is reached by an abnormal edge. Likewise for call
1362 clobbered regs, because caller-save, fixup_abnormal_edges and
1363 possibly the table driven EH machinery are not quite ready to
1364 handle such allocnos live across such edges. */
1365 if (bb_has_abnormal_pred (bb
))
1368 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
1370 ira_allocno_t a
= OBJECT_ALLOCNO (ira_object_id_map
[px
]);
1372 ALLOCNO_NO_STACK_REG_P (a
) = true;
1373 ALLOCNO_TOTAL_NO_STACK_REG_P (a
) = true;
1375 for (px
= FIRST_STACK_REG
; px
<= LAST_STACK_REG
; px
++)
1376 make_hard_regno_born (px
);
1378 /* No need to record conflicts for call clobbered regs if we
1379 have nonlocal labels around, as we don't ever try to
1380 allocate such regs in this case. */
1381 if (!cfun
->has_nonlocal_label
&& bb_has_abnormal_call_pred (bb
))
1382 for (px
= 0; px
< FIRST_PSEUDO_REGISTER
; px
++)
1383 if (call_used_regs
[px
])
1384 make_hard_regno_born (px
);
1387 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1388 make_object_dead (ira_object_id_map
[i
]);
1393 /* Propagate register pressure to upper loop tree nodes: */
1394 if (loop_tree_node
!= ira_loop_tree_root
)
1395 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1397 enum reg_class pclass
;
1399 pclass
= ira_pressure_classes
[i
];
1400 if (loop_tree_node
->reg_pressure
[pclass
]
1401 > loop_tree_node
->parent
->reg_pressure
[pclass
])
1402 loop_tree_node
->parent
->reg_pressure
[pclass
]
1403 = loop_tree_node
->reg_pressure
[pclass
];
1407 /* Create and set up IRA_START_POINT_RANGES and
1408 IRA_FINISH_POINT_RANGES. */
1410 create_start_finish_chains (void)
1413 ira_object_iterator oi
;
1416 ira_start_point_ranges
1417 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1418 memset (ira_start_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1419 ira_finish_point_ranges
1420 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1421 memset (ira_finish_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1422 FOR_EACH_OBJECT (obj
, oi
)
1423 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1425 r
->start_next
= ira_start_point_ranges
[r
->start
];
1426 ira_start_point_ranges
[r
->start
] = r
;
1427 r
->finish_next
= ira_finish_point_ranges
[r
->finish
];
1428 ira_finish_point_ranges
[r
->finish
] = r
;
1432 /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1433 new live ranges and program points were added as a result if new
1436 ira_rebuild_start_finish_chains (void)
1438 ira_free (ira_finish_point_ranges
);
1439 ira_free (ira_start_point_ranges
);
1440 create_start_finish_chains ();
1443 /* Compress allocno live ranges by removing program points where
1446 remove_some_program_points_and_update_live_ranges (void)
1452 ira_object_iterator oi
;
1453 live_range_t r
, prev_r
, next_r
;
1454 sbitmap born_or_dead
, born
, dead
;
1455 sbitmap_iterator sbi
;
1456 bool born_p
, dead_p
, prev_born_p
, prev_dead_p
;
1458 born
= sbitmap_alloc (ira_max_point
);
1459 dead
= sbitmap_alloc (ira_max_point
);
1460 bitmap_clear (born
);
1461 bitmap_clear (dead
);
1462 FOR_EACH_OBJECT (obj
, oi
)
1463 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1465 ira_assert (r
->start
<= r
->finish
);
1466 bitmap_set_bit (born
, r
->start
);
1467 bitmap_set_bit (dead
, r
->finish
);
1470 born_or_dead
= sbitmap_alloc (ira_max_point
);
1471 bitmap_ior (born_or_dead
, born
, dead
);
1472 map
= (int *) ira_allocate (sizeof (int) * ira_max_point
);
1474 prev_born_p
= prev_dead_p
= false;
1475 EXECUTE_IF_SET_IN_BITMAP (born_or_dead
, 0, i
, sbi
)
1477 born_p
= bitmap_bit_p (born
, i
);
1478 dead_p
= bitmap_bit_p (dead
, i
);
1479 if ((prev_born_p
&& ! prev_dead_p
&& born_p
&& ! dead_p
)
1480 || (prev_dead_p
&& ! prev_born_p
&& dead_p
&& ! born_p
))
1484 prev_born_p
= born_p
;
1485 prev_dead_p
= dead_p
;
1487 sbitmap_free (born_or_dead
);
1488 sbitmap_free (born
);
1489 sbitmap_free (dead
);
1491 if (internal_flag_ira_verbose
> 1 && ira_dump_file
!= NULL
)
1492 fprintf (ira_dump_file
, "Compressing live ranges: from %d to %d - %d%%\n",
1493 ira_max_point
, n
, 100 * n
/ ira_max_point
);
1496 FOR_EACH_OBJECT (obj
, oi
)
1497 for (r
= OBJECT_LIVE_RANGES (obj
), prev_r
= NULL
; r
!= NULL
; r
= next_r
)
1500 r
->start
= map
[r
->start
];
1501 r
->finish
= map
[r
->finish
];
1502 if (prev_r
== NULL
|| prev_r
->start
> r
->finish
+ 1)
1507 prev_r
->start
= r
->start
;
1508 prev_r
->next
= next_r
;
1509 ira_finish_live_range (r
);
1515 /* Print live ranges R to file F. */
1517 ira_print_live_range_list (FILE *f
, live_range_t r
)
1519 for (; r
!= NULL
; r
= r
->next
)
1520 fprintf (f
, " [%d..%d]", r
->start
, r
->finish
);
1525 debug (live_range
&ref
)
1527 ira_print_live_range_list (stderr
, &ref
);
1531 debug (live_range
*ptr
)
1536 fprintf (stderr
, "<nil>\n");
1539 /* Print live ranges R to stderr. */
1541 ira_debug_live_range_list (live_range_t r
)
1543 ira_print_live_range_list (stderr
, r
);
1546 /* Print live ranges of object OBJ to file F. */
1548 print_object_live_ranges (FILE *f
, ira_object_t obj
)
1550 ira_print_live_range_list (f
, OBJECT_LIVE_RANGES (obj
));
1553 /* Print live ranges of allocno A to file F. */
1555 print_allocno_live_ranges (FILE *f
, ira_allocno_t a
)
1557 int n
= ALLOCNO_NUM_OBJECTS (a
);
1560 for (i
= 0; i
< n
; i
++)
1562 fprintf (f
, " a%d(r%d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
1564 fprintf (f
, " [%d]", i
);
1566 print_object_live_ranges (f
, ALLOCNO_OBJECT (a
, i
));
1570 /* Print live ranges of allocno A to stderr. */
1572 ira_debug_allocno_live_ranges (ira_allocno_t a
)
1574 print_allocno_live_ranges (stderr
, a
);
1577 /* Print live ranges of all allocnos to file F. */
1579 print_live_ranges (FILE *f
)
1582 ira_allocno_iterator ai
;
1584 FOR_EACH_ALLOCNO (a
, ai
)
1585 print_allocno_live_ranges (f
, a
);
1588 /* Print live ranges of all allocnos to stderr. */
1590 ira_debug_live_ranges (void)
1592 print_live_ranges (stderr
);
1595 /* The main entry function creates live ranges, set up
1596 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1597 calculate register pressure info. */
1599 ira_create_allocno_live_ranges (void)
1601 objects_live
= sparseset_alloc (ira_objects_num
);
1602 allocnos_processed
= sparseset_alloc (ira_allocnos_num
);
1605 allocno_saved_at_call
1606 = (int *) ira_allocate (ira_allocnos_num
* sizeof (int));
1607 memset (allocno_saved_at_call
, 0, ira_allocnos_num
* sizeof (int));
1608 ira_traverse_loop_tree (true, ira_loop_tree_root
, NULL
,
1609 process_bb_node_lives
);
1610 ira_max_point
= curr_point
;
1611 create_start_finish_chains ();
1612 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1613 print_live_ranges (ira_dump_file
);
1615 ira_free (allocno_saved_at_call
);
1616 sparseset_free (objects_live
);
1617 sparseset_free (allocnos_processed
);
1620 /* Compress allocno live ranges. */
1622 ira_compress_allocno_live_ranges (void)
1624 remove_some_program_points_and_update_live_ranges ();
1625 ira_rebuild_start_finish_chains ();
1626 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1628 fprintf (ira_dump_file
, "Ranges after the compression:\n");
1629 print_live_ranges (ira_dump_file
);
1633 /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1635 ira_finish_allocno_live_ranges (void)
1637 ira_free (ira_finish_point_ranges
);
1638 ira_free (ira_start_point_ranges
);