1 /* IRA processing allocno lives to build allocno live ranges.
2 Copyright (C) 2006-2019 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
31 #include "insn-config.h"
35 #include "sparseset.h"
36 #include "function-abi.h"
38 /* The code in this file is similar to one in global but the code
39 works on the allocno basis and creates live ranges instead of
40 pseudo-register conflicts. */
42 /* Program points are enumerated by numbers from range
43 0..IRA_MAX_POINT-1. There are approximately two times more program
44 points than insns. Program points are places in the program where
45 liveness info can be changed. In most general case (there are more
46 complicated cases too) some program points correspond to places
47 where input operand dies and other ones correspond to places where
48 output operands are born. */
51 /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
52 live ranges with given start/finish point. */
53 live_range_t
*ira_start_point_ranges
, *ira_finish_point_ranges
;
55 /* Number of the current program point. */
56 static int curr_point
;
58 /* Point where register pressure excess started or -1 if there is no
59 register pressure excess. Excess pressure for a register class at
60 some point means that there are more allocnos of given register
61 class living at the point than number of hard-registers of the
62 class available for the allocation. It is defined only for
64 static int high_pressure_start_point
[N_REG_CLASSES
];
66 /* Objects live at current point in the scan. */
67 static sparseset objects_live
;
69 /* A temporary bitmap used in functions that wish to avoid visiting an allocno
71 static sparseset allocnos_processed
;
73 /* Set of hard regs (except eliminable ones) currently live. */
74 static HARD_REG_SET hard_regs_live
;
76 /* The loop tree node corresponding to the current basic block. */
77 static ira_loop_tree_node_t curr_bb_node
;
79 /* The number of the last processed call. */
80 static int last_call_num
;
81 /* The number of last call at which given allocno was saved. */
82 static int *allocno_saved_at_call
;
84 /* The value returned by ira_setup_alts for the current instruction;
85 i.e. the set of alternatives that we should consider to be likely
86 candidates during reloading. */
87 static alternative_mask preferred_alternatives
;
89 /* If non-NULL, the source operand of a register to register copy for which
90 we should not add a conflict with the copy's destination operand. */
91 static rtx ignore_reg_for_conflicts
;
93 /* Record hard register REGNO as now being live. */
95 make_hard_regno_live (int regno
)
97 SET_HARD_REG_BIT (hard_regs_live
, regno
);
100 /* Process the definition of hard register REGNO. This updates
101 hard_regs_live and hard reg conflict information for living allocnos. */
103 make_hard_regno_dead (int regno
)
106 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
108 ira_object_t obj
= ira_object_id_map
[i
];
110 if (ignore_reg_for_conflicts
!= NULL_RTX
111 && REGNO (ignore_reg_for_conflicts
)
112 == (unsigned int) ALLOCNO_REGNO (OBJECT_ALLOCNO (obj
)))
115 SET_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj
), regno
);
116 SET_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
);
118 CLEAR_HARD_REG_BIT (hard_regs_live
, regno
);
121 /* Record object OBJ as now being live. Set a bit for it in objects_live,
122 and start a new live range for it if necessary. */
124 make_object_live (ira_object_t obj
)
126 sparseset_set_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
128 live_range_t lr
= OBJECT_LIVE_RANGES (obj
);
130 || (lr
->finish
!= curr_point
&& lr
->finish
+ 1 != curr_point
))
131 ira_add_live_range_to_object (obj
, curr_point
, -1);
134 /* Update ALLOCNO_EXCESS_PRESSURE_POINTS_NUM for the allocno
135 associated with object OBJ. */
137 update_allocno_pressure_excess_length (ira_object_t obj
)
139 ira_allocno_t a
= OBJECT_ALLOCNO (obj
);
141 enum reg_class aclass
, pclass
, cl
;
144 aclass
= ALLOCNO_CLASS (a
);
145 pclass
= ira_pressure_class_translate
[aclass
];
147 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
150 if (! ira_reg_pressure_class_p
[cl
])
152 if (high_pressure_start_point
[cl
] < 0)
154 p
= OBJECT_LIVE_RANGES (obj
);
155 ira_assert (p
!= NULL
);
156 start
= (high_pressure_start_point
[cl
] > p
->start
157 ? high_pressure_start_point
[cl
] : p
->start
);
158 ALLOCNO_EXCESS_PRESSURE_POINTS_NUM (a
) += curr_point
- start
+ 1;
162 /* Process the definition of object OBJ, which is associated with allocno A.
163 This finishes the current live range for it. */
165 make_object_dead (ira_object_t obj
)
169 int ignore_regno
= -1;
170 int ignore_total_regno
= -1;
173 sparseset_clear_bit (objects_live
, OBJECT_CONFLICT_ID (obj
));
175 /* Check whether any part of IGNORE_REG_FOR_CONFLICTS already conflicts
177 if (ignore_reg_for_conflicts
!= NULL_RTX
178 && REGNO (ignore_reg_for_conflicts
) < FIRST_PSEUDO_REGISTER
)
180 end_regno
= END_REGNO (ignore_reg_for_conflicts
);
181 ignore_regno
= ignore_total_regno
= REGNO (ignore_reg_for_conflicts
);
183 for (regno
= ignore_regno
; regno
< end_regno
; regno
++)
185 if (TEST_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj
), regno
))
186 ignore_regno
= end_regno
;
187 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
))
188 ignore_total_regno
= end_regno
;
192 OBJECT_CONFLICT_HARD_REGS (obj
) |= hard_regs_live
;
193 OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
) |= hard_regs_live
;
195 /* If IGNORE_REG_FOR_CONFLICTS did not already conflict with OBJ, make
196 sure it still doesn't. */
197 for (regno
= ignore_regno
; regno
< end_regno
; regno
++)
198 CLEAR_HARD_REG_BIT (OBJECT_CONFLICT_HARD_REGS (obj
), regno
);
199 for (regno
= ignore_total_regno
; regno
< end_regno
; regno
++)
200 CLEAR_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
);
202 lr
= OBJECT_LIVE_RANGES (obj
);
203 ira_assert (lr
!= NULL
);
204 lr
->finish
= curr_point
;
205 update_allocno_pressure_excess_length (obj
);
208 /* The current register pressures for each pressure class for the current
210 static int curr_reg_pressure
[N_REG_CLASSES
];
212 /* Record that register pressure for PCLASS increased by N registers.
213 Update the current register pressure, maximal register pressure for
214 the current BB and the start point of the register pressure
217 inc_register_pressure (enum reg_class pclass
, int n
)
223 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
226 if (! ira_reg_pressure_class_p
[cl
])
228 curr_reg_pressure
[cl
] += n
;
229 if (high_pressure_start_point
[cl
] < 0
230 && (curr_reg_pressure
[cl
] > ira_class_hard_regs_num
[cl
]))
231 high_pressure_start_point
[cl
] = curr_point
;
232 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
233 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
237 /* Record that register pressure for PCLASS has decreased by NREGS
238 registers; update current register pressure, start point of the
239 register pressure excess, and register pressure excess length for
243 dec_register_pressure (enum reg_class pclass
, int nregs
)
251 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
254 if (! ira_reg_pressure_class_p
[cl
])
256 curr_reg_pressure
[cl
] -= nregs
;
257 ira_assert (curr_reg_pressure
[cl
] >= 0);
258 if (high_pressure_start_point
[cl
] >= 0
259 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
264 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, j
)
265 update_allocno_pressure_excess_length (ira_object_id_map
[j
]);
267 (cl
= ira_reg_class_super_classes
[pclass
][i
]) != LIM_REG_CLASSES
;
270 if (! ira_reg_pressure_class_p
[cl
])
272 if (high_pressure_start_point
[cl
] >= 0
273 && curr_reg_pressure
[cl
] <= ira_class_hard_regs_num
[cl
])
274 high_pressure_start_point
[cl
] = -1;
279 /* Determine from the objects_live bitmap whether REGNO is currently live,
280 and occupies only one object. Return false if we have no information. */
282 pseudo_regno_single_word_and_live_p (int regno
)
284 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
289 if (ALLOCNO_NUM_OBJECTS (a
) > 1)
292 obj
= ALLOCNO_OBJECT (a
, 0);
294 return sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
));
297 /* Mark the pseudo register REGNO as live. Update all information about
298 live ranges and register pressure. */
300 mark_pseudo_regno_live (int regno
)
302 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
303 enum reg_class pclass
;
309 /* Invalidate because it is referenced. */
310 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
312 n
= ALLOCNO_NUM_OBJECTS (a
);
313 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
314 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
317 /* We track every subobject separately. */
318 gcc_assert (nregs
== n
);
322 for (i
= 0; i
< n
; i
++)
324 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
326 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
329 inc_register_pressure (pclass
, nregs
);
330 make_object_live (obj
);
334 /* Like mark_pseudo_regno_live, but try to only mark one subword of
335 the pseudo as live. SUBWORD indicates which; a value of 0
336 indicates the low part. */
338 mark_pseudo_regno_subword_live (int regno
, int subword
)
340 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
342 enum reg_class pclass
;
348 /* Invalidate because it is referenced. */
349 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
351 n
= ALLOCNO_NUM_OBJECTS (a
);
354 mark_pseudo_regno_live (regno
);
358 pclass
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
360 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
361 obj
= ALLOCNO_OBJECT (a
, subword
);
363 if (sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
366 inc_register_pressure (pclass
, 1);
367 make_object_live (obj
);
370 /* Mark the register REG as live. Store a 1 in hard_regs_live for
371 this register, record how many consecutive hardware registers it
374 mark_hard_reg_live (rtx reg
)
376 int regno
= REGNO (reg
);
378 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
380 int last
= END_REGNO (reg
);
381 enum reg_class aclass
, pclass
;
385 if (! TEST_HARD_REG_BIT (hard_regs_live
, regno
)
386 && ! TEST_HARD_REG_BIT (eliminable_regset
, regno
))
388 aclass
= ira_hard_regno_allocno_class
[regno
];
389 pclass
= ira_pressure_class_translate
[aclass
];
390 inc_register_pressure (pclass
, 1);
391 make_hard_regno_live (regno
);
398 /* Mark a pseudo, or one of its subwords, as live. REGNO is the pseudo's
399 register number; ORIG_REG is the access in the insn, which may be a
402 mark_pseudo_reg_live (rtx orig_reg
, unsigned regno
)
404 if (read_modify_subreg_p (orig_reg
))
406 mark_pseudo_regno_subword_live (regno
,
407 subreg_lowpart_p (orig_reg
) ? 0 : 1);
410 mark_pseudo_regno_live (regno
);
413 /* Mark the register referenced by use or def REF as live. */
415 mark_ref_live (df_ref ref
)
417 rtx reg
= DF_REF_REG (ref
);
420 if (GET_CODE (reg
) == SUBREG
)
421 reg
= SUBREG_REG (reg
);
423 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
424 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
426 mark_hard_reg_live (reg
);
429 /* Mark the pseudo register REGNO as dead. Update all information about
430 live ranges and register pressure. */
432 mark_pseudo_regno_dead (int regno
)
434 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
441 /* Invalidate because it is referenced. */
442 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
444 n
= ALLOCNO_NUM_OBJECTS (a
);
445 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
446 nregs
= ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)];
449 /* We track every subobject separately. */
450 gcc_assert (nregs
== n
);
453 for (i
= 0; i
< n
; i
++)
455 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
456 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
459 dec_register_pressure (cl
, nregs
);
460 make_object_dead (obj
);
464 /* Like mark_pseudo_regno_dead, but called when we know that only part of the
465 register dies. SUBWORD indicates which; a value of 0 indicates the low part. */
467 mark_pseudo_regno_subword_dead (int regno
, int subword
)
469 ira_allocno_t a
= ira_curr_regno_allocno_map
[regno
];
477 /* Invalidate because it is referenced. */
478 allocno_saved_at_call
[ALLOCNO_NUM (a
)] = 0;
480 n
= ALLOCNO_NUM_OBJECTS (a
);
482 /* The allocno as a whole doesn't die in this case. */
485 cl
= ira_pressure_class_translate
[ALLOCNO_CLASS (a
)];
487 (n
== ira_reg_class_max_nregs
[ALLOCNO_CLASS (a
)][ALLOCNO_MODE (a
)]);
489 obj
= ALLOCNO_OBJECT (a
, subword
);
490 if (!sparseset_bit_p (objects_live
, OBJECT_CONFLICT_ID (obj
)))
493 dec_register_pressure (cl
, 1);
494 make_object_dead (obj
);
497 /* Process the definition of hard register REG. This updates hard_regs_live
498 and hard reg conflict information for living allocnos. */
500 mark_hard_reg_dead (rtx reg
)
502 int regno
= REGNO (reg
);
504 if (! TEST_HARD_REG_BIT (ira_no_alloc_regs
, regno
))
506 int last
= END_REGNO (reg
);
507 enum reg_class aclass
, pclass
;
511 if (TEST_HARD_REG_BIT (hard_regs_live
, regno
))
513 aclass
= ira_hard_regno_allocno_class
[regno
];
514 pclass
= ira_pressure_class_translate
[aclass
];
515 dec_register_pressure (pclass
, 1);
516 make_hard_regno_dead (regno
);
523 /* Mark a pseudo, or one of its subwords, as dead. REGNO is the pseudo's
524 register number; ORIG_REG is the access in the insn, which may be a
527 mark_pseudo_reg_dead (rtx orig_reg
, unsigned regno
)
529 if (read_modify_subreg_p (orig_reg
))
531 mark_pseudo_regno_subword_dead (regno
,
532 subreg_lowpart_p (orig_reg
) ? 0 : 1);
535 mark_pseudo_regno_dead (regno
);
538 /* Mark the register referenced by definition DEF as dead, if the
539 definition is a total one. */
541 mark_ref_dead (df_ref def
)
543 rtx reg
= DF_REF_REG (def
);
546 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
))
549 if (GET_CODE (reg
) == SUBREG
)
550 reg
= SUBREG_REG (reg
);
552 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
)
553 && (GET_CODE (orig_reg
) != SUBREG
554 || REGNO (reg
) < FIRST_PSEUDO_REGISTER
555 || !read_modify_subreg_p (orig_reg
)))
558 if (REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
559 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
561 mark_hard_reg_dead (reg
);
564 /* If REG is a pseudo or a subreg of it, and the class of its allocno
565 intersects CL, make a conflict with pseudo DREG. ORIG_DREG is the
566 rtx actually accessed, it may be identical to DREG or a subreg of it.
567 Advance the current program point before making the conflict if
568 ADVANCE_P. Return TRUE if we will need to advance the current
571 make_pseudo_conflict (rtx reg
, enum reg_class cl
, rtx dreg
, rtx orig_dreg
,
577 if (GET_CODE (reg
) == SUBREG
)
578 reg
= SUBREG_REG (reg
);
580 if (! REG_P (reg
) || REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
583 a
= ira_curr_regno_allocno_map
[REGNO (reg
)];
584 if (! reg_classes_intersect_p (cl
, ALLOCNO_CLASS (a
)))
590 mark_pseudo_reg_live (orig_reg
, REGNO (reg
));
591 mark_pseudo_reg_live (orig_dreg
, REGNO (dreg
));
592 mark_pseudo_reg_dead (orig_reg
, REGNO (reg
));
593 mark_pseudo_reg_dead (orig_dreg
, REGNO (dreg
));
598 /* Check and make if necessary conflicts for pseudo DREG of class
599 DEF_CL of the current insn with input operand USE of class USE_CL.
600 ORIG_DREG is the rtx actually accessed, it may be identical to
601 DREG or a subreg of it. Advance the current program point before
602 making the conflict if ADVANCE_P. Return TRUE if we will need to
603 advance the current program point. */
605 check_and_make_def_use_conflict (rtx dreg
, rtx orig_dreg
,
606 enum reg_class def_cl
, int use
,
607 enum reg_class use_cl
, bool advance_p
)
609 if (! reg_classes_intersect_p (def_cl
, use_cl
))
612 advance_p
= make_pseudo_conflict (recog_data
.operand
[use
],
613 use_cl
, dreg
, orig_dreg
, advance_p
);
615 /* Reload may end up swapping commutative operands, so you
616 have to take both orderings into account. The
617 constraints for the two operands can be completely
618 different. (Indeed, if the constraints for the two
619 operands are the same for all alternatives, there's no
620 point marking them as commutative.) */
621 if (use
< recog_data
.n_operands
- 1
622 && recog_data
.constraints
[use
][0] == '%')
624 = make_pseudo_conflict (recog_data
.operand
[use
+ 1],
625 use_cl
, dreg
, orig_dreg
, advance_p
);
627 && recog_data
.constraints
[use
- 1][0] == '%')
629 = make_pseudo_conflict (recog_data
.operand
[use
- 1],
630 use_cl
, dreg
, orig_dreg
, advance_p
);
634 /* Check and make if necessary conflicts for definition DEF of class
635 DEF_CL of the current insn with input operands. Process only
636 constraints of alternative ALT.
638 One of three things is true when this function is called:
640 (1) DEF is an earlyclobber for alternative ALT. Input operands then
641 conflict with DEF in ALT unless they explicitly match DEF via 0-9
644 (2) DEF matches (via 0-9 constraints) an operand that is an
645 earlyclobber for alternative ALT. Other input operands then
646 conflict with DEF in ALT.
648 (3) [FOR_TIE_P] Some input operand X matches DEF for alternative ALT.
649 Input operands with a different value from X then conflict with
652 However, there's still a judgement call to make when deciding
653 whether a conflict in ALT is important enough to be reflected
654 in the pan-alternative allocno conflict set. */
656 check_and_make_def_conflict (int alt
, int def
, enum reg_class def_cl
,
661 enum reg_class use_cl
, acl
;
663 rtx dreg
= recog_data
.operand
[def
];
664 rtx orig_dreg
= dreg
;
666 if (def_cl
== NO_REGS
)
669 if (GET_CODE (dreg
) == SUBREG
)
670 dreg
= SUBREG_REG (dreg
);
672 if (! REG_P (dreg
) || REGNO (dreg
) < FIRST_PSEUDO_REGISTER
)
675 a
= ira_curr_regno_allocno_map
[REGNO (dreg
)];
676 acl
= ALLOCNO_CLASS (a
);
677 if (! reg_classes_intersect_p (acl
, def_cl
))
682 int n_operands
= recog_data
.n_operands
;
683 const operand_alternative
*op_alt
= &recog_op_alt
[alt
* n_operands
];
684 for (use
= 0; use
< n_operands
; use
++)
688 if (use
== def
|| recog_data
.operand_type
[use
] == OP_OUT
)
691 /* An earlyclobber on DEF doesn't apply to an input operand X if X
692 explicitly matches DEF, but it applies to other input operands
693 even if they happen to be the same value as X.
695 In contrast, if an input operand X is tied to a non-earlyclobber
696 DEF, there's no conflict with other input operands that have the
698 if (op_alt
[use
].matches
== def
700 && rtx_equal_p (recog_data
.operand
[use
],
701 recog_data
.operand
[op_alt
[def
].matched
])))
704 if (op_alt
[use
].anything_ok
)
707 use_cl
= op_alt
[use
].cl
;
708 if (use_cl
== NO_REGS
)
711 /* If DEF is simply a tied operand, ignore cases in which this
712 alternative requires USE to have a likely-spilled class.
713 Adding a conflict would just constrain USE further if DEF
714 happens to be allocated first. */
715 if (for_tie_p
&& targetm
.class_likely_spilled_p (use_cl
))
718 /* If there's any alternative that allows USE to match DEF, do not
719 record a conflict. If that causes us to create an invalid
720 instruction due to the earlyclobber, reload must fix it up.
722 Likewise, if we're treating a tied DEF like a partial earlyclobber,
723 do not record a conflict if there's another alternative in which
724 DEF is neither tied nor earlyclobber. */
725 for (alt1
= 0; alt1
< recog_data
.n_alternatives
; alt1
++)
727 if (!TEST_BIT (preferred_alternatives
, alt1
))
729 const operand_alternative
*op_alt1
730 = &recog_op_alt
[alt1
* n_operands
];
731 if (op_alt1
[use
].matches
== def
732 || (use
< n_operands
- 1
733 && recog_data
.constraints
[use
][0] == '%'
734 && op_alt1
[use
+ 1].matches
== def
)
736 && recog_data
.constraints
[use
- 1][0] == '%'
737 && op_alt1
[use
- 1].matches
== def
))
740 && !op_alt1
[def
].earlyclobber
741 && op_alt1
[def
].matched
< 0
742 && alternative_class (op_alt1
, def
) != NO_REGS
743 && alternative_class (op_alt1
, use
) != NO_REGS
)
747 if (alt1
< recog_data
.n_alternatives
)
750 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
751 use
, use_cl
, advance_p
);
753 if ((use_match
= op_alt
[use
].matches
) >= 0)
755 gcc_checking_assert (use_match
!= def
);
757 if (op_alt
[use_match
].anything_ok
)
760 use_cl
= op_alt
[use_match
].cl
;
761 advance_p
= check_and_make_def_use_conflict (dreg
, orig_dreg
, def_cl
,
762 use
, use_cl
, advance_p
);
767 /* Make conflicts of early clobber pseudo registers of the current
768 insn with its inputs. Avoid introducing unnecessary conflicts by
769 checking classes of the constraints and pseudos because otherwise
770 significant code degradation is possible for some targets.
772 For these purposes, tying an input to an output makes that output act
773 like an earlyclobber for inputs with a different value, since the output
774 register then has a predetermined purpose on input to the instruction. */
776 make_early_clobber_and_input_conflicts (void)
780 enum reg_class def_cl
;
782 int n_alternatives
= recog_data
.n_alternatives
;
783 int n_operands
= recog_data
.n_operands
;
784 const operand_alternative
*op_alt
= recog_op_alt
;
785 for (alt
= 0; alt
< n_alternatives
; alt
++, op_alt
+= n_operands
)
786 if (TEST_BIT (preferred_alternatives
, alt
))
787 for (def
= 0; def
< n_operands
; def
++)
789 if (op_alt
[def
].anything_ok
)
792 def_cl
= op_alt
[def
].cl
;
793 if (def_cl
!= NO_REGS
)
795 if (op_alt
[def
].earlyclobber
)
796 check_and_make_def_conflict (alt
, def
, def_cl
, false);
797 else if (op_alt
[def
].matched
>= 0
798 && !targetm
.class_likely_spilled_p (def_cl
))
799 check_and_make_def_conflict (alt
, def
, def_cl
, true);
802 if ((def_match
= op_alt
[def
].matches
) >= 0
803 && (op_alt
[def_match
].earlyclobber
804 || op_alt
[def
].earlyclobber
))
806 if (op_alt
[def_match
].anything_ok
)
809 def_cl
= op_alt
[def_match
].cl
;
810 check_and_make_def_conflict (alt
, def
, def_cl
, false);
815 /* Mark early clobber hard registers of the current INSN as live (if
816 LIVE_P) or dead. Return true if there are such registers. */
818 mark_hard_reg_early_clobbers (rtx_insn
*insn
, bool live_p
)
823 FOR_EACH_INSN_DEF (def
, insn
)
824 if (DF_REF_FLAGS_IS_SET (def
, DF_REF_MUST_CLOBBER
))
826 rtx dreg
= DF_REF_REG (def
);
828 if (GET_CODE (dreg
) == SUBREG
)
829 dreg
= SUBREG_REG (dreg
);
830 if (! REG_P (dreg
) || REGNO (dreg
) >= FIRST_PSEUDO_REGISTER
)
833 /* Hard register clobbers are believed to be early clobber
834 because there is no way to say that non-operand hard
835 register clobbers are not early ones. */
846 /* Checks that CONSTRAINTS permits to use only one hard register. If
847 it is so, the function returns the class of the hard register.
848 Otherwise it returns NO_REGS. */
849 static enum reg_class
850 single_reg_class (const char *constraints
, rtx op
, rtx equiv_const
)
853 enum reg_class cl
, next_cl
;
854 enum constraint_num cn
;
857 alternative_mask preferred
= preferred_alternatives
;
858 for (; (c
= *constraints
); constraints
+= CONSTRAINT_LEN (c
, constraints
))
860 preferred
&= ~ALTERNATIVE_BIT (0);
863 else if (preferred
& 1)
870 /* ??? Is this the best way to handle memory constraints? */
871 cn
= lookup_constraint (constraints
);
872 if (insn_extra_memory_constraint (cn
)
873 || insn_extra_special_memory_constraint (cn
)
874 || insn_extra_address_constraint (cn
))
876 if (constraint_satisfied_p (op
, cn
)
877 || (equiv_const
!= NULL_RTX
878 && CONSTANT_P (equiv_const
)
879 && constraint_satisfied_p (equiv_const
, cn
)))
881 next_cl
= reg_class_for_constraint (cn
);
882 if (next_cl
== NO_REGS
)
885 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
886 : (ira_class_singleton
[cl
][GET_MODE (op
)]
887 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
892 case '0': case '1': case '2': case '3': case '4':
893 case '5': case '6': case '7': case '8': case '9':
895 = single_reg_class (recog_data
.constraints
[c
- '0'],
896 recog_data
.operand
[c
- '0'], NULL_RTX
);
898 ? ira_class_singleton
[next_cl
][GET_MODE (op
)] < 0
899 : (ira_class_singleton
[cl
][GET_MODE (op
)]
900 != ira_class_singleton
[next_cl
][GET_MODE (op
)]))
908 /* The function checks that operand OP_NUM of the current insn can use
909 only one hard register. If it is so, the function returns the
910 class of the hard register. Otherwise it returns NO_REGS. */
911 static enum reg_class
912 single_reg_operand_class (int op_num
)
914 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
916 return single_reg_class (recog_data
.constraints
[op_num
],
917 recog_data
.operand
[op_num
], NULL_RTX
);
920 /* The function sets up hard register set *SET to hard registers which
921 might be used by insn reloads because the constraints are too
924 ira_implicitly_set_insn_hard_regs (HARD_REG_SET
*set
,
925 alternative_mask preferred
)
932 CLEAR_HARD_REG_SET (*set
);
933 for (i
= 0; i
< recog_data
.n_operands
; i
++)
935 op
= recog_data
.operand
[i
];
937 if (GET_CODE (op
) == SUBREG
)
938 op
= SUBREG_REG (op
);
940 if (GET_CODE (op
) == SCRATCH
941 || (REG_P (op
) && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
))
943 const char *p
= recog_data
.constraints
[i
];
945 mode
= (GET_CODE (op
) == SCRATCH
946 ? GET_MODE (op
) : PSEUDO_REGNO_MODE (regno
));
948 for (; (c
= *p
); p
+= CONSTRAINT_LEN (c
, p
))
950 preferred
&= ~ALTERNATIVE_BIT (0);
953 else if (preferred
& 1)
955 cl
= reg_class_for_constraint (lookup_constraint (p
));
958 /* There is no register pressure problem if all of the
959 regs in this class are fixed. */
960 int regno
= ira_class_singleton
[cl
][mode
];
962 add_to_hard_reg_set (set
, mode
, regno
);
968 /* Processes input operands, if IN_P, or output operands otherwise of
969 the current insn with FREQ to find allocno which can use only one
970 hard register and makes other currently living allocnos conflicting
971 with the hard register. */
973 process_single_reg_class_operands (bool in_p
, int freq
)
979 ira_allocno_t operand_a
, a
;
981 for (i
= 0; i
< recog_data
.n_operands
; i
++)
983 operand
= recog_data
.operand
[i
];
984 if (in_p
&& recog_data
.operand_type
[i
] != OP_IN
985 && recog_data
.operand_type
[i
] != OP_INOUT
)
987 if (! in_p
&& recog_data
.operand_type
[i
] != OP_OUT
988 && recog_data
.operand_type
[i
] != OP_INOUT
)
990 cl
= single_reg_operand_class (i
);
996 if (GET_CODE (operand
) == SUBREG
)
997 operand
= SUBREG_REG (operand
);
1000 && (regno
= REGNO (operand
)) >= FIRST_PSEUDO_REGISTER
)
1002 enum reg_class aclass
;
1004 operand_a
= ira_curr_regno_allocno_map
[regno
];
1005 aclass
= ALLOCNO_CLASS (operand_a
);
1006 if (ira_class_subset_p
[cl
][aclass
])
1008 /* View the desired allocation of OPERAND as:
1012 a simplification of:
1014 (subreg:YMODE (reg:XMODE XREGNO) OFFSET). */
1015 machine_mode ymode
, xmode
;
1019 xmode
= recog_data
.operand_mode
[i
];
1020 xregno
= ira_class_singleton
[cl
][xmode
];
1021 gcc_assert (xregno
>= 0);
1022 ymode
= ALLOCNO_MODE (operand_a
);
1023 offset
= subreg_lowpart_offset (ymode
, xmode
);
1024 yregno
= simplify_subreg_regno (xregno
, xmode
, offset
, ymode
);
1026 && ira_class_hard_reg_index
[aclass
][yregno
] >= 0)
1030 ira_allocate_and_set_costs
1031 (&ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
),
1033 ira_init_register_move_cost_if_necessary (xmode
);
1035 ? ira_register_move_cost
[xmode
][aclass
][cl
]
1036 : ira_register_move_cost
[xmode
][cl
][aclass
]);
1037 ALLOCNO_CONFLICT_HARD_REG_COSTS (operand_a
)
1038 [ira_class_hard_reg_index
[aclass
][yregno
]] -= cost
;
1043 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
1045 ira_object_t obj
= ira_object_id_map
[px
];
1046 a
= OBJECT_ALLOCNO (obj
);
1049 /* We could increase costs of A instead of making it
1050 conflicting with the hard register. But it works worse
1051 because it will be spilled in reload in anyway. */
1052 OBJECT_CONFLICT_HARD_REGS (obj
) |= reg_class_contents
[cl
];
1053 OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
) |= reg_class_contents
[cl
];
1059 /* Look through the CALL_INSN_FUNCTION_USAGE of a call insn INSN, and see if
1060 we find a SET rtx that we can use to deduce that a register can be cheaply
1061 caller-saved. Return such a register, or NULL_RTX if none is found. */
1063 find_call_crossed_cheap_reg (rtx_insn
*insn
)
1065 rtx cheap_reg
= NULL_RTX
;
1066 rtx exp
= CALL_INSN_FUNCTION_USAGE (insn
);
1070 rtx x
= XEXP (exp
, 0);
1071 if (GET_CODE (x
) == SET
)
1076 exp
= XEXP (exp
, 1);
1080 basic_block bb
= BLOCK_FOR_INSN (insn
);
1081 rtx reg
= SET_SRC (exp
);
1082 rtx_insn
*prev
= PREV_INSN (insn
);
1083 while (prev
&& !(INSN_P (prev
)
1084 && BLOCK_FOR_INSN (prev
) != bb
))
1086 if (NONDEBUG_INSN_P (prev
))
1088 rtx set
= single_set (prev
);
1090 if (set
&& rtx_equal_p (SET_DEST (set
), reg
))
1092 rtx src
= SET_SRC (set
);
1093 if (!REG_P (src
) || HARD_REGISTER_P (src
)
1094 || !pseudo_regno_single_word_and_live_p (REGNO (src
)))
1096 if (!modified_between_p (src
, prev
, insn
))
1100 if (set
&& rtx_equal_p (SET_SRC (set
), reg
))
1102 rtx dest
= SET_DEST (set
);
1103 if (!REG_P (dest
) || HARD_REGISTER_P (dest
)
1104 || !pseudo_regno_single_word_and_live_p (REGNO (dest
)))
1106 if (!modified_between_p (dest
, prev
, insn
))
1111 if (reg_set_p (reg
, prev
))
1114 prev
= PREV_INSN (prev
);
1120 /* Determine whether INSN is a register to register copy of the type where
1121 we do not need to make the source and destiniation registers conflict.
1122 If this is a copy instruction, then return the source reg. Otherwise,
1125 non_conflicting_reg_copy_p (rtx_insn
*insn
)
1127 /* Reload has issues with overlapping pseudos being assigned to the
1128 same hard register, so don't allow it. See PR87600 for details. */
1129 if (!targetm
.lra_p ())
1132 rtx set
= single_set (insn
);
1134 /* Disallow anything other than a simple register to register copy
1135 that has no side effects. */
1137 || !REG_P (SET_DEST (set
))
1138 || !REG_P (SET_SRC (set
))
1139 || side_effects_p (set
))
1142 int dst_regno
= REGNO (SET_DEST (set
));
1143 int src_regno
= REGNO (SET_SRC (set
));
1144 machine_mode mode
= GET_MODE (SET_DEST (set
));
1146 /* By definition, a register does not conflict with itself, therefore we
1147 do not have to handle it specially. Returning NULL_RTX now, helps
1148 simplify the callers of this function. */
1149 if (dst_regno
== src_regno
)
1152 /* Computing conflicts for register pairs is difficult to get right, so
1153 for now, disallow it. */
1154 if ((HARD_REGISTER_NUM_P (dst_regno
)
1155 && hard_regno_nregs (dst_regno
, mode
) != 1)
1156 || (HARD_REGISTER_NUM_P (src_regno
)
1157 && hard_regno_nregs (src_regno
, mode
) != 1))
1160 return SET_SRC (set
);
1163 /* Process insns of the basic block given by its LOOP_TREE_NODE to
1164 update allocno live ranges, allocno hard register conflicts,
1165 intersected calls, and register pressure info for allocnos for the
1166 basic block for and regions containing the basic block. */
1168 process_bb_node_lives (ira_loop_tree_node_t loop_tree_node
)
1175 bitmap reg_live_out
;
1179 bb
= loop_tree_node
->bb
;
1182 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1184 curr_reg_pressure
[ira_pressure_classes
[i
]] = 0;
1185 high_pressure_start_point
[ira_pressure_classes
[i
]] = -1;
1187 curr_bb_node
= loop_tree_node
;
1188 reg_live_out
= df_get_live_out (bb
);
1189 sparseset_clear (objects_live
);
1190 REG_SET_TO_HARD_REG_SET (hard_regs_live
, reg_live_out
);
1191 hard_regs_live
&= ~(eliminable_regset
| ira_no_alloc_regs
);
1192 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1193 if (TEST_HARD_REG_BIT (hard_regs_live
, i
))
1195 enum reg_class aclass
, pclass
, cl
;
1197 aclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (i
)];
1198 pclass
= ira_pressure_class_translate
[aclass
];
1200 (cl
= ira_reg_class_super_classes
[pclass
][j
])
1204 if (! ira_reg_pressure_class_p
[cl
])
1206 curr_reg_pressure
[cl
]++;
1207 if (curr_bb_node
->reg_pressure
[cl
] < curr_reg_pressure
[cl
])
1208 curr_bb_node
->reg_pressure
[cl
] = curr_reg_pressure
[cl
];
1209 ira_assert (curr_reg_pressure
[cl
]
1210 <= ira_class_hard_regs_num
[cl
]);
1213 EXECUTE_IF_SET_IN_BITMAP (reg_live_out
, FIRST_PSEUDO_REGISTER
, j
, bi
)
1214 mark_pseudo_regno_live (j
);
1216 freq
= REG_FREQ_FROM_BB (bb
);
1220 /* Invalidate all allocno_saved_at_call entries. */
1223 /* Scan the code of this basic block, noting which allocnos and
1224 hard regs are born or die.
1226 Note that this loop treats uninitialized values as live until
1227 the beginning of the block. For example, if an instruction
1228 uses (reg:DI foo), and only (subreg:SI (reg:DI foo) 0) is ever
1229 set, FOO will remain live until the beginning of the block.
1230 Likewise if FOO is not set at all. This is unnecessarily
1231 pessimistic, but it probably doesn't matter much in practice. */
1232 FOR_BB_INSNS_REVERSE (bb
, insn
)
1238 if (!NONDEBUG_INSN_P (insn
))
1241 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1242 fprintf (ira_dump_file
, " Insn %u(l%d): point = %d\n",
1243 INSN_UID (insn
), loop_tree_node
->parent
->loop_num
,
1246 call_p
= CALL_P (insn
);
1247 ignore_reg_for_conflicts
= non_conflicting_reg_copy_p (insn
);
1249 /* Mark each defined value as live. We need to do this for
1250 unused values because they still conflict with quantities
1251 that are live at the time of the definition.
1253 Ignore DF_REF_MAY_CLOBBERs on a call instruction. Such
1254 references represent the effect of the called function
1255 on a call-clobbered register. Marking the register as
1256 live would stop us from allocating it to a call-crossing
1258 FOR_EACH_INSN_DEF (def
, insn
)
1259 if (!call_p
|| !DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
1260 mark_ref_live (def
);
1262 /* If INSN has multiple outputs, then any value used in one
1263 of the outputs conflicts with the other outputs. Model this
1264 by making the used value live during the output phase.
1266 It is unsafe to use !single_set here since it will ignore
1267 an unused output. Just because an output is unused does
1268 not mean the compiler can assume the side effect will not
1269 occur. Consider if ALLOCNO appears in the address of an
1270 output and we reload the output. If we allocate ALLOCNO
1271 to the same hard register as an unused output we could
1272 set the hard register before the output reload insn. */
1273 if (GET_CODE (PATTERN (insn
)) == PARALLEL
&& multiple_sets (insn
))
1274 FOR_EACH_INSN_USE (use
, insn
)
1279 reg
= DF_REF_REG (use
);
1280 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
1284 set
= XVECEXP (PATTERN (insn
), 0, i
);
1285 if (GET_CODE (set
) == SET
1286 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1288 /* After the previous loop, this is a no-op if
1289 REG is contained within SET_DEST (SET). */
1290 mark_ref_live (use
);
1296 preferred_alternatives
= ira_setup_alts (insn
);
1297 process_single_reg_class_operands (false, freq
);
1301 /* Try to find a SET in the CALL_INSN_FUNCTION_USAGE, and from
1302 there, try to find a pseudo that is live across the call but
1303 can be cheaply reconstructed from the return value. */
1304 rtx cheap_reg
= find_call_crossed_cheap_reg (insn
);
1305 if (cheap_reg
!= NULL_RTX
)
1306 add_reg_note (insn
, REG_RETURNED
, cheap_reg
);
1309 sparseset_clear (allocnos_processed
);
1310 /* The current set of live allocnos are live across the call. */
1311 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1313 ira_object_t obj
= ira_object_id_map
[i
];
1314 a
= OBJECT_ALLOCNO (obj
);
1315 int num
= ALLOCNO_NUM (a
);
1316 function_abi callee_abi
= insn_callee_abi (insn
);
1318 /* Don't allocate allocnos that cross setjmps or any
1319 call, if this function receives a nonlocal
1321 if (cfun
->has_nonlocal_label
1322 || (!targetm
.setjmp_preserves_nonvolatile_regs_p ()
1323 && (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
)
1326 SET_HARD_REG_SET (OBJECT_CONFLICT_HARD_REGS (obj
));
1327 SET_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
));
1329 if (can_throw_internal (insn
))
1331 OBJECT_CONFLICT_HARD_REGS (obj
)
1332 |= callee_abi
.mode_clobbers (ALLOCNO_MODE (a
));
1333 OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
)
1334 |= callee_abi
.mode_clobbers (ALLOCNO_MODE (a
));
1337 if (sparseset_bit_p (allocnos_processed
, num
))
1339 sparseset_set_bit (allocnos_processed
, num
);
1341 if (allocno_saved_at_call
[num
] != last_call_num
)
1342 /* Here we are mimicking caller-save.c behavior
1343 which does not save hard register at a call if
1344 it was saved on previous call in the same basic
1345 block and the hard register was not mentioned
1346 between the two calls. */
1347 ALLOCNO_CALL_FREQ (a
) += freq
;
1348 /* Mark it as saved at the next call. */
1349 allocno_saved_at_call
[num
] = last_call_num
+ 1;
1350 ALLOCNO_CALLS_CROSSED_NUM (a
)++;
1351 ALLOCNO_CROSSED_CALLS_ABIS (a
) |= 1 << callee_abi
.id ();
1352 ALLOCNO_CROSSED_CALLS_CLOBBERED_REGS (a
)
1353 |= callee_abi
.full_and_partial_reg_clobbers ();
1354 if (cheap_reg
!= NULL_RTX
1355 && ALLOCNO_REGNO (a
) == (int) REGNO (cheap_reg
))
1356 ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
)++;
1360 /* See which defined values die here. Note that we include
1361 the call insn in the lifetimes of these values, so we don't
1362 mistakenly consider, for e.g. an addressing mode with a
1363 side-effect like a post-increment fetching the address,
1364 that the use happens before the call, and the def to happen
1365 after the call: we believe both to happen before the actual
1366 call. (We don't handle return-values here.) */
1367 FOR_EACH_INSN_DEF (def
, insn
)
1368 if (!call_p
|| !DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
1369 mark_ref_dead (def
);
1371 make_early_clobber_and_input_conflicts ();
1375 /* Mark each used value as live. */
1376 FOR_EACH_INSN_USE (use
, insn
)
1377 mark_ref_live (use
);
1379 process_single_reg_class_operands (true, freq
);
1381 set_p
= mark_hard_reg_early_clobbers (insn
, true);
1385 mark_hard_reg_early_clobbers (insn
, false);
1387 /* Mark each hard reg as live again. For example, a
1388 hard register can be in clobber and in an insn
1390 FOR_EACH_INSN_USE (use
, insn
)
1392 rtx ureg
= DF_REF_REG (use
);
1394 if (GET_CODE (ureg
) == SUBREG
)
1395 ureg
= SUBREG_REG (ureg
);
1396 if (! REG_P (ureg
) || REGNO (ureg
) >= FIRST_PSEUDO_REGISTER
)
1399 mark_ref_live (use
);
1405 ignore_reg_for_conflicts
= NULL_RTX
;
1407 if (bb_has_eh_pred (bb
))
1410 unsigned int regno
= EH_RETURN_DATA_REGNO (j
);
1411 if (regno
== INVALID_REGNUM
)
1413 make_hard_regno_live (regno
);
1416 /* Allocnos can't go in stack regs at the start of a basic block
1417 that is reached by an abnormal edge. Likewise for registers
1418 that are at least partly call clobbered, because caller-save,
1419 fixup_abnormal_edges and possibly the table driven EH machinery
1420 are not quite ready to handle such allocnos live across such
1422 if (bb_has_abnormal_pred (bb
))
1425 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, px
)
1427 ira_allocno_t a
= OBJECT_ALLOCNO (ira_object_id_map
[px
]);
1429 ALLOCNO_NO_STACK_REG_P (a
) = true;
1430 ALLOCNO_TOTAL_NO_STACK_REG_P (a
) = true;
1432 for (px
= FIRST_STACK_REG
; px
<= LAST_STACK_REG
; px
++)
1433 make_hard_regno_live (px
);
1435 /* No need to record conflicts for call clobbered regs if we
1436 have nonlocal labels around, as we don't ever try to
1437 allocate such regs in this case. */
1438 if (!cfun
->has_nonlocal_label
1439 && has_abnormal_call_or_eh_pred_edge_p (bb
))
1440 for (px
= 0; px
< FIRST_PSEUDO_REGISTER
; px
++)
1441 if (eh_edge_abi
.clobbers_at_least_part_of_reg_p (px
)
1442 #ifdef REAL_PIC_OFFSET_TABLE_REGNUM
1443 /* We should create a conflict of PIC pseudo with
1444 PIC hard reg as PIC hard reg can have a wrong
1445 value after jump described by the abnormal edge.
1446 In this case we cannot allocate PIC hard reg to
1447 PIC pseudo as PIC pseudo will also have a wrong
1448 value. This code is not critical as LRA can fix
1449 it but it is better to have the right allocation
1451 || (px
== REAL_PIC_OFFSET_TABLE_REGNUM
1452 && pic_offset_table_rtx
!= NULL_RTX
1453 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
1456 make_hard_regno_live (px
);
1459 EXECUTE_IF_SET_IN_SPARSESET (objects_live
, i
)
1460 make_object_dead (ira_object_id_map
[i
]);
1465 /* Propagate register pressure to upper loop tree nodes. */
1466 if (loop_tree_node
!= ira_loop_tree_root
)
1467 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
1469 enum reg_class pclass
;
1471 pclass
= ira_pressure_classes
[i
];
1472 if (loop_tree_node
->reg_pressure
[pclass
]
1473 > loop_tree_node
->parent
->reg_pressure
[pclass
])
1474 loop_tree_node
->parent
->reg_pressure
[pclass
]
1475 = loop_tree_node
->reg_pressure
[pclass
];
1479 /* Create and set up IRA_START_POINT_RANGES and
1480 IRA_FINISH_POINT_RANGES. */
1482 create_start_finish_chains (void)
1485 ira_object_iterator oi
;
1488 ira_start_point_ranges
1489 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1490 memset (ira_start_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1491 ira_finish_point_ranges
1492 = (live_range_t
*) ira_allocate (ira_max_point
* sizeof (live_range_t
));
1493 memset (ira_finish_point_ranges
, 0, ira_max_point
* sizeof (live_range_t
));
1494 FOR_EACH_OBJECT (obj
, oi
)
1495 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1497 r
->start_next
= ira_start_point_ranges
[r
->start
];
1498 ira_start_point_ranges
[r
->start
] = r
;
1499 r
->finish_next
= ira_finish_point_ranges
[r
->finish
];
1500 ira_finish_point_ranges
[r
->finish
] = r
;
1504 /* Rebuild IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES after
1505 new live ranges and program points were added as a result if new
1508 ira_rebuild_start_finish_chains (void)
1510 ira_free (ira_finish_point_ranges
);
1511 ira_free (ira_start_point_ranges
);
1512 create_start_finish_chains ();
1515 /* Compress allocno live ranges by removing program points where
1518 remove_some_program_points_and_update_live_ranges (void)
1524 ira_object_iterator oi
;
1525 live_range_t r
, prev_r
, next_r
;
1526 sbitmap_iterator sbi
;
1527 bool born_p
, dead_p
, prev_born_p
, prev_dead_p
;
1529 auto_sbitmap
born (ira_max_point
);
1530 auto_sbitmap
dead (ira_max_point
);
1531 bitmap_clear (born
);
1532 bitmap_clear (dead
);
1533 FOR_EACH_OBJECT (obj
, oi
)
1534 for (r
= OBJECT_LIVE_RANGES (obj
); r
!= NULL
; r
= r
->next
)
1536 ira_assert (r
->start
<= r
->finish
);
1537 bitmap_set_bit (born
, r
->start
);
1538 bitmap_set_bit (dead
, r
->finish
);
1541 auto_sbitmap
born_or_dead (ira_max_point
);
1542 bitmap_ior (born_or_dead
, born
, dead
);
1543 map
= (int *) ira_allocate (sizeof (int) * ira_max_point
);
1545 prev_born_p
= prev_dead_p
= false;
1546 EXECUTE_IF_SET_IN_BITMAP (born_or_dead
, 0, i
, sbi
)
1548 born_p
= bitmap_bit_p (born
, i
);
1549 dead_p
= bitmap_bit_p (dead
, i
);
1550 if ((prev_born_p
&& ! prev_dead_p
&& born_p
&& ! dead_p
)
1551 || (prev_dead_p
&& ! prev_born_p
&& dead_p
&& ! born_p
))
1555 prev_born_p
= born_p
;
1556 prev_dead_p
= dead_p
;
1560 if (internal_flag_ira_verbose
> 1 && ira_dump_file
!= NULL
)
1561 fprintf (ira_dump_file
, "Compressing live ranges: from %d to %d - %d%%\n",
1562 ira_max_point
, n
, 100 * n
/ ira_max_point
);
1565 FOR_EACH_OBJECT (obj
, oi
)
1566 for (r
= OBJECT_LIVE_RANGES (obj
), prev_r
= NULL
; r
!= NULL
; r
= next_r
)
1569 r
->start
= map
[r
->start
];
1570 r
->finish
= map
[r
->finish
];
1571 if (prev_r
== NULL
|| prev_r
->start
> r
->finish
+ 1)
1576 prev_r
->start
= r
->start
;
1577 prev_r
->next
= next_r
;
1578 ira_finish_live_range (r
);
1584 /* Print live ranges R to file F. */
1586 ira_print_live_range_list (FILE *f
, live_range_t r
)
1588 for (; r
!= NULL
; r
= r
->next
)
1589 fprintf (f
, " [%d..%d]", r
->start
, r
->finish
);
1594 debug (live_range
&ref
)
1596 ira_print_live_range_list (stderr
, &ref
);
1600 debug (live_range
*ptr
)
1605 fprintf (stderr
, "<nil>\n");
1608 /* Print live ranges R to stderr. */
1610 ira_debug_live_range_list (live_range_t r
)
1612 ira_print_live_range_list (stderr
, r
);
1615 /* Print live ranges of object OBJ to file F. */
1617 print_object_live_ranges (FILE *f
, ira_object_t obj
)
1619 ira_print_live_range_list (f
, OBJECT_LIVE_RANGES (obj
));
1622 /* Print live ranges of allocno A to file F. */
1624 print_allocno_live_ranges (FILE *f
, ira_allocno_t a
)
1626 int n
= ALLOCNO_NUM_OBJECTS (a
);
1629 for (i
= 0; i
< n
; i
++)
1631 fprintf (f
, " a%d(r%d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
1633 fprintf (f
, " [%d]", i
);
1635 print_object_live_ranges (f
, ALLOCNO_OBJECT (a
, i
));
1639 /* Print live ranges of allocno A to stderr. */
1641 ira_debug_allocno_live_ranges (ira_allocno_t a
)
1643 print_allocno_live_ranges (stderr
, a
);
1646 /* Print live ranges of all allocnos to file F. */
1648 print_live_ranges (FILE *f
)
1651 ira_allocno_iterator ai
;
1653 FOR_EACH_ALLOCNO (a
, ai
)
1654 print_allocno_live_ranges (f
, a
);
1657 /* Print live ranges of all allocnos to stderr. */
1659 ira_debug_live_ranges (void)
1661 print_live_ranges (stderr
);
1664 /* The main entry function creates live ranges, set up
1665 CONFLICT_HARD_REGS and TOTAL_CONFLICT_HARD_REGS for objects, and
1666 calculate register pressure info. */
1668 ira_create_allocno_live_ranges (void)
1670 objects_live
= sparseset_alloc (ira_objects_num
);
1671 allocnos_processed
= sparseset_alloc (ira_allocnos_num
);
1674 allocno_saved_at_call
1675 = (int *) ira_allocate (ira_allocnos_num
* sizeof (int));
1676 memset (allocno_saved_at_call
, 0, ira_allocnos_num
* sizeof (int));
1677 ira_traverse_loop_tree (true, ira_loop_tree_root
, NULL
,
1678 process_bb_node_lives
);
1679 ira_max_point
= curr_point
;
1680 create_start_finish_chains ();
1681 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1682 print_live_ranges (ira_dump_file
);
1684 ira_free (allocno_saved_at_call
);
1685 sparseset_free (objects_live
);
1686 sparseset_free (allocnos_processed
);
1689 /* Compress allocno live ranges. */
1691 ira_compress_allocno_live_ranges (void)
1693 remove_some_program_points_and_update_live_ranges ();
1694 ira_rebuild_start_finish_chains ();
1695 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
1697 fprintf (ira_dump_file
, "Ranges after the compression:\n");
1698 print_live_ranges (ira_dump_file
);
1702 /* Free arrays IRA_START_POINT_RANGES and IRA_FINISH_POINT_RANGES. */
1704 ira_finish_allocno_live_ranges (void)
1706 ira_free (ira_finish_point_ranges
);
1707 ira_free (ira_start_point_ranges
);