1 /* Integrated Register Allocator (IRA) entry point.
2 Copyright (C) 2006-2013 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* The integrated register allocator (IRA) is a
22 regional register allocator performing graph coloring on a top-down
23 traversal of nested regions. Graph coloring in a region is based
24 on Chaitin-Briggs algorithm. It is called integrated because
25 register coalescing, register live range splitting, and choosing a
26 better hard register are done on-the-fly during coloring. Register
27 coalescing and choosing a cheaper hard register is done by hard
28 register preferencing during hard register assigning. The live
29 range splitting is a byproduct of the regional register allocation.
31 Major IRA notions are:
33 o *Region* is a part of CFG where graph coloring based on
34 Chaitin-Briggs algorithm is done. IRA can work on any set of
35 nested CFG regions forming a tree. Currently the regions are
36 the entire function for the root region and natural loops for
37 the other regions. Therefore data structure representing a
38 region is called loop_tree_node.
40 o *Allocno class* is a register class used for allocation of
41 given allocno. It means that only hard register of given
42 register class can be assigned to given allocno. In reality,
43 even smaller subset of (*profitable*) hard registers can be
44 assigned. In rare cases, the subset can be even smaller
45 because our modification of Chaitin-Briggs algorithm requires
46 that sets of hard registers can be assigned to allocnos forms a
47 forest, i.e. the sets can be ordered in a way where any
48 previous set is not intersected with given set or is a superset
51 o *Pressure class* is a register class belonging to a set of
52 register classes containing all of the hard-registers available
53 for register allocation. The set of all pressure classes for a
54 target is defined in the corresponding machine-description file
55 according some criteria. Register pressure is calculated only
56 for pressure classes and it affects some IRA decisions as
57 forming allocation regions.
59 o *Allocno* represents the live range of a pseudo-register in a
60 region. Besides the obvious attributes like the corresponding
61 pseudo-register number, allocno class, conflicting allocnos and
62 conflicting hard-registers, there are a few allocno attributes
63 which are important for understanding the allocation algorithm:
65 - *Live ranges*. This is a list of ranges of *program points*
66 where the allocno lives. Program points represent places
67 where a pseudo can be born or become dead (there are
68 approximately two times more program points than the insns)
69 and they are represented by integers starting with 0. The
70 live ranges are used to find conflicts between allocnos.
71 They also play very important role for the transformation of
72 the IRA internal representation of several regions into a one
73 region representation. The later is used during the reload
74 pass work because each allocno represents all of the
75 corresponding pseudo-registers.
77 - *Hard-register costs*. This is a vector of size equal to the
78 number of available hard-registers of the allocno class. The
79 cost of a callee-clobbered hard-register for an allocno is
80 increased by the cost of save/restore code around the calls
81 through the given allocno's life. If the allocno is a move
82 instruction operand and another operand is a hard-register of
83 the allocno class, the cost of the hard-register is decreased
86 When an allocno is assigned, the hard-register with minimal
87 full cost is used. Initially, a hard-register's full cost is
88 the corresponding value from the hard-register's cost vector.
89 If the allocno is connected by a *copy* (see below) to
90 another allocno which has just received a hard-register, the
91 cost of the hard-register is decreased. Before choosing a
92 hard-register for an allocno, the allocno's current costs of
93 the hard-registers are modified by the conflict hard-register
94 costs of all of the conflicting allocnos which are not
97 - *Conflict hard-register costs*. This is a vector of the same
98 size as the hard-register costs vector. To permit an
99 unassigned allocno to get a better hard-register, IRA uses
100 this vector to calculate the final full cost of the
101 available hard-registers. Conflict hard-register costs of an
102 unassigned allocno are also changed with a change of the
103 hard-register cost of the allocno when a copy involving the
104 allocno is processed as described above. This is done to
105 show other unassigned allocnos that a given allocno prefers
106 some hard-registers in order to remove the move instruction
107 corresponding to the copy.
109 o *Cap*. If a pseudo-register does not live in a region but
110 lives in a nested region, IRA creates a special allocno called
111 a cap in the outer region. A region cap is also created for a
114 o *Copy*. Allocnos can be connected by copies. Copies are used
115 to modify hard-register costs for allocnos during coloring.
116 Such modifications reflects a preference to use the same
117 hard-register for the allocnos connected by copies. Usually
118 copies are created for move insns (in this case it results in
119 register coalescing). But IRA also creates copies for operands
120 of an insn which should be assigned to the same hard-register
121 due to constraints in the machine description (it usually
122 results in removing a move generated in reload to satisfy
123 the constraints) and copies referring to the allocno which is
124 the output operand of an instruction and the allocno which is
125 an input operand dying in the instruction (creation of such
126 copies results in less register shuffling). IRA *does not*
127 create copies between the same register allocnos from different
128 regions because we use another technique for propagating
129 hard-register preference on the borders of regions.
131 Allocnos (including caps) for the upper region in the region tree
132 *accumulate* information important for coloring from allocnos with
133 the same pseudo-register from nested regions. This includes
134 hard-register and memory costs, conflicts with hard-registers,
135 allocno conflicts, allocno copies and more. *Thus, attributes for
136 allocnos in a region have the same values as if the region had no
137 subregions*. It means that attributes for allocnos in the
138 outermost region corresponding to the function have the same values
139 as though the allocation used only one region which is the entire
140 function. It also means that we can look at IRA work as if the
141 first IRA did allocation for all function then it improved the
142 allocation for loops then their subloops and so on.
144 IRA major passes are:
146 o Building IRA internal representation which consists of the
149 * First, IRA builds regions and creates allocnos (file
150 ira-build.c) and initializes most of their attributes.
152 * Then IRA finds an allocno class for each allocno and
153 calculates its initial (non-accumulated) cost of memory and
154 each hard-register of its allocno class (file ira-cost.c).
156 * IRA creates live ranges of each allocno, calulates register
157 pressure for each pressure class in each region, sets up
158 conflict hard registers for each allocno and info about calls
159 the allocno lives through (file ira-lives.c).
161 * IRA removes low register pressure loops from the regions
162 mostly to speed IRA up (file ira-build.c).
164 * IRA propagates accumulated allocno info from lower region
165 allocnos to corresponding upper region allocnos (file
168 * IRA creates all caps (file ira-build.c).
170 * Having live-ranges of allocnos and their classes, IRA creates
171 conflicting allocnos for each allocno. Conflicting allocnos
172 are stored as a bit vector or array of pointers to the
173 conflicting allocnos whatever is more profitable (file
174 ira-conflicts.c). At this point IRA creates allocno copies.
176 o Coloring. Now IRA has all necessary info to start graph coloring
177 process. It is done in each region on top-down traverse of the
178 region tree (file ira-color.c). There are following subpasses:
180 * Finding profitable hard registers of corresponding allocno
181 class for each allocno. For example, only callee-saved hard
182 registers are frequently profitable for allocnos living
183 through colors. If the profitable hard register set of
184 allocno does not form a tree based on subset relation, we use
185 some approximation to form the tree. This approximation is
186 used to figure out trivial colorability of allocnos. The
187 approximation is a pretty rare case.
189 * Putting allocnos onto the coloring stack. IRA uses Briggs
190 optimistic coloring which is a major improvement over
191 Chaitin's coloring. Therefore IRA does not spill allocnos at
192 this point. There is some freedom in the order of putting
193 allocnos on the stack which can affect the final result of
194 the allocation. IRA uses some heuristics to improve the
197 We also use a modification of Chaitin-Briggs algorithm which
198 works for intersected register classes of allocnos. To
199 figure out trivial colorability of allocnos, the mentioned
200 above tree of hard register sets is used. To get an idea how
201 the algorithm works in i386 example, let us consider an
202 allocno to which any general hard register can be assigned.
203 If the allocno conflicts with eight allocnos to which only
204 EAX register can be assigned, given allocno is still
205 trivially colorable because all conflicting allocnos might be
206 assigned only to EAX and all other general hard registers are
209 To get an idea of the used trivial colorability criterion, it
210 is also useful to read article "Graph-Coloring Register
211 Allocation for Irregular Architectures" by Michael D. Smith
212 and Glen Holloway. Major difference between the article
213 approach and approach used in IRA is that Smith's approach
214 takes register classes only from machine description and IRA
215 calculate register classes from intermediate code too
216 (e.g. an explicit usage of hard registers in RTL code for
217 parameter passing can result in creation of additional
218 register classes which contain or exclude the hard
219 registers). That makes IRA approach useful for improving
220 coloring even for architectures with regular register files
221 and in fact some benchmarking shows the improvement for
222 regular class architectures is even bigger than for irregular
223 ones. Another difference is that Smith's approach chooses
224 intersection of classes of all insn operands in which a given
225 pseudo occurs. IRA can use bigger classes if it is still
226 more profitable than memory usage.
228 * Popping the allocnos from the stack and assigning them hard
229 registers. If IRA can not assign a hard register to an
230 allocno and the allocno is coalesced, IRA undoes the
231 coalescing and puts the uncoalesced allocnos onto the stack in
232 the hope that some such allocnos will get a hard register
233 separately. If IRA fails to assign hard register or memory
234 is more profitable for it, IRA spills the allocno. IRA
235 assigns the allocno the hard-register with minimal full
236 allocation cost which reflects the cost of usage of the
237 hard-register for the allocno and cost of usage of the
238 hard-register for allocnos conflicting with given allocno.
240 * Chaitin-Briggs coloring assigns as many pseudos as possible
241 to hard registers. After coloringh we try to improve
242 allocation with cost point of view. We improve the
243 allocation by spilling some allocnos and assigning the freed
244 hard registers to other allocnos if it decreases the overall
247 * After allono assigning in the region, IRA modifies the hard
248 register and memory costs for the corresponding allocnos in
249 the subregions to reflect the cost of possible loads, stores,
250 or moves on the border of the region and its subregions.
251 When default regional allocation algorithm is used
252 (-fira-algorithm=mixed), IRA just propagates the assignment
253 for allocnos if the register pressure in the region for the
254 corresponding pressure class is less than number of available
255 hard registers for given pressure class.
257 o Spill/restore code moving. When IRA performs an allocation
258 by traversing regions in top-down order, it does not know what
259 happens below in the region tree. Therefore, sometimes IRA
260 misses opportunities to perform a better allocation. A simple
261 optimization tries to improve allocation in a region having
262 subregions and containing in another region. If the
263 corresponding allocnos in the subregion are spilled, it spills
264 the region allocno if it is profitable. The optimization
265 implements a simple iterative algorithm performing profitable
266 transformations while they are still possible. It is fast in
267 practice, so there is no real need for a better time complexity
270 o Code change. After coloring, two allocnos representing the
271 same pseudo-register outside and inside a region respectively
272 may be assigned to different locations (hard-registers or
273 memory). In this case IRA creates and uses a new
274 pseudo-register inside the region and adds code to move allocno
275 values on the region's borders. This is done during top-down
276 traversal of the regions (file ira-emit.c). In some
277 complicated cases IRA can create a new allocno to move allocno
278 values (e.g. when a swap of values stored in two hard-registers
279 is needed). At this stage, the new allocno is marked as
280 spilled. IRA still creates the pseudo-register and the moves
281 on the region borders even when both allocnos were assigned to
282 the same hard-register. If the reload pass spills a
283 pseudo-register for some reason, the effect will be smaller
284 because another allocno will still be in the hard-register. In
285 most cases, this is better then spilling both allocnos. If
286 reload does not change the allocation for the two
287 pseudo-registers, the trivial move will be removed by
288 post-reload optimizations. IRA does not generate moves for
289 allocnos assigned to the same hard register when the default
290 regional allocation algorithm is used and the register pressure
291 in the region for the corresponding pressure class is less than
292 number of available hard registers for given pressure class.
293 IRA also does some optimizations to remove redundant stores and
294 to reduce code duplication on the region borders.
296 o Flattening internal representation. After changing code, IRA
297 transforms its internal representation for several regions into
298 one region representation (file ira-build.c). This process is
299 called IR flattening. Such process is more complicated than IR
300 rebuilding would be, but is much faster.
302 o After IR flattening, IRA tries to assign hard registers to all
303 spilled allocnos. This is impelemented by a simple and fast
304 priority coloring algorithm (see function
305 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
306 created during the code change pass can be assigned to hard
309 o At the end IRA calls the reload pass. The reload pass
310 communicates with IRA through several functions in file
311 ira-color.c to improve its decisions in
313 * sharing stack slots for the spilled pseudos based on IRA info
314 about pseudo-register conflicts.
316 * reassigning hard-registers to all spilled pseudos at the end
317 of each reload iteration.
319 * choosing a better hard-register to spill based on IRA info
320 about pseudo-register live ranges and the register pressure
321 in places where the pseudo-register lives.
323 IRA uses a lot of data representing the target processors. These
324 data are initilized in file ira.c.
326 If function has no loops (or the loops are ignored when
327 -fira-algorithm=CB is used), we have classic Chaitin-Briggs
328 coloring (only instead of separate pass of coalescing, we use hard
329 register preferencing). In such case, IRA works much faster
330 because many things are not made (like IR flattening, the
331 spill/restore optimization, and the code change).
333 Literature is worth to read for better understanding the code:
335 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
336 Graph Coloring Register Allocation.
338 o David Callahan, Brian Koblenz. Register allocation via
339 hierarchical graph coloring.
341 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
342 Coloring Register Allocation: A Study of the Chaitin-Briggs and
343 Callahan-Koblenz Algorithms.
345 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
346 Register Allocation Based on Graph Fusion.
348 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
349 Allocation for Irregular Architectures
351 o Vladimir Makarov. The Integrated Register Allocator for GCC.
353 o Vladimir Makarov. The top-down register allocator for irregular
354 register file architectures.
361 #include "coretypes.h"
371 #include "hard-reg-set.h"
372 #include "basic-block.h"
377 #include "tree-pass.h"
381 #include "diagnostic-core.h"
382 #include "function.h"
389 struct target_ira default_target_ira
;
390 struct target_ira_int default_target_ira_int
;
391 #if SWITCHABLE_TARGET
392 struct target_ira
*this_target_ira
= &default_target_ira
;
393 struct target_ira_int
*this_target_ira_int
= &default_target_ira_int
;
396 /* A modified value of flag `-fira-verbose' used internally. */
397 int internal_flag_ira_verbose
;
399 /* Dump file of the allocator if it is not NULL. */
402 /* The number of elements in the following array. */
403 int ira_spilled_reg_stack_slots_num
;
405 /* The following array contains info about spilled pseudo-registers
406 stack slots used in current function so far. */
407 struct ira_spilled_reg_stack_slot
*ira_spilled_reg_stack_slots
;
409 /* Correspondingly overall cost of the allocation, overall cost before
410 reload, cost of the allocnos assigned to hard-registers, cost of
411 the allocnos assigned to memory, cost of loads, stores and register
412 move insns generated for pseudo-register live range splitting (see
414 int ira_overall_cost
, overall_cost_before
;
415 int ira_reg_cost
, ira_mem_cost
;
416 int ira_load_cost
, ira_store_cost
, ira_shuffle_cost
;
417 int ira_move_loops_num
, ira_additional_jumps_num
;
419 /* All registers that can be eliminated. */
421 HARD_REG_SET eliminable_regset
;
423 /* Value of max_reg_num () before IRA work start. This value helps
424 us to recognize a situation when new pseudos were created during
426 static int max_regno_before_ira
;
428 /* Temporary hard reg set used for a different calculation. */
429 static HARD_REG_SET temp_hard_regset
;
431 #define last_mode_for_init_move_cost \
432 (this_target_ira_int->x_last_mode_for_init_move_cost)
435 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
437 setup_reg_mode_hard_regset (void)
439 int i
, m
, hard_regno
;
441 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
442 for (hard_regno
= 0; hard_regno
< FIRST_PSEUDO_REGISTER
; hard_regno
++)
444 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset
[hard_regno
][m
]);
445 for (i
= hard_regno_nregs
[hard_regno
][m
] - 1; i
>= 0; i
--)
446 if (hard_regno
+ i
< FIRST_PSEUDO_REGISTER
)
447 SET_HARD_REG_BIT (ira_reg_mode_hard_regset
[hard_regno
][m
],
453 #define no_unit_alloc_regs \
454 (this_target_ira_int->x_no_unit_alloc_regs)
456 /* The function sets up the three arrays declared above. */
458 setup_class_hard_regs (void)
460 int cl
, i
, hard_regno
, n
;
461 HARD_REG_SET processed_hard_reg_set
;
463 ira_assert (SHRT_MAX
>= FIRST_PSEUDO_REGISTER
);
464 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
466 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
467 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
468 CLEAR_HARD_REG_SET (processed_hard_reg_set
);
469 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
471 ira_non_ordered_class_hard_regs
[cl
][i
] = -1;
472 ira_class_hard_reg_index
[cl
][i
] = -1;
474 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
476 #ifdef REG_ALLOC_ORDER
477 hard_regno
= reg_alloc_order
[i
];
481 if (TEST_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
))
483 SET_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
);
484 if (! TEST_HARD_REG_BIT (temp_hard_regset
, hard_regno
))
485 ira_class_hard_reg_index
[cl
][hard_regno
] = -1;
488 ira_class_hard_reg_index
[cl
][hard_regno
] = n
;
489 ira_class_hard_regs
[cl
][n
++] = hard_regno
;
492 ira_class_hard_regs_num
[cl
] = n
;
493 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
494 if (TEST_HARD_REG_BIT (temp_hard_regset
, i
))
495 ira_non_ordered_class_hard_regs
[cl
][n
++] = i
;
496 ira_assert (ira_class_hard_regs_num
[cl
] == n
);
500 /* Set up global variables defining info about hard registers for the
501 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
502 that we can use the hard frame pointer for the allocation. */
504 setup_alloc_regs (bool use_hard_frame_p
)
506 #ifdef ADJUST_REG_ALLOC_ORDER
507 ADJUST_REG_ALLOC_ORDER
;
509 COPY_HARD_REG_SET (no_unit_alloc_regs
, fixed_reg_set
);
510 if (! use_hard_frame_p
)
511 SET_HARD_REG_BIT (no_unit_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
512 setup_class_hard_regs ();
517 #define alloc_reg_class_subclasses \
518 (this_target_ira_int->x_alloc_reg_class_subclasses)
520 /* Initialize the table of subclasses of each reg class. */
522 setup_reg_subclasses (void)
525 HARD_REG_SET temp_hard_regset2
;
527 for (i
= 0; i
< N_REG_CLASSES
; i
++)
528 for (j
= 0; j
< N_REG_CLASSES
; j
++)
529 alloc_reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
531 for (i
= 0; i
< N_REG_CLASSES
; i
++)
533 if (i
== (int) NO_REGS
)
536 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
537 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
538 if (hard_reg_set_empty_p (temp_hard_regset
))
540 for (j
= 0; j
< N_REG_CLASSES
; j
++)
545 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[j
]);
546 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
547 if (! hard_reg_set_subset_p (temp_hard_regset
,
550 p
= &alloc_reg_class_subclasses
[j
][0];
551 while (*p
!= LIM_REG_CLASSES
) p
++;
552 *p
= (enum reg_class
) i
;
559 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
561 setup_class_subset_and_memory_move_costs (void)
563 int cl
, cl2
, mode
, cost
;
564 HARD_REG_SET temp_hard_regset2
;
566 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
567 ira_memory_move_cost
[mode
][NO_REGS
][0]
568 = ira_memory_move_cost
[mode
][NO_REGS
][1] = SHRT_MAX
;
569 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
571 if (cl
!= (int) NO_REGS
)
572 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
574 ira_max_memory_move_cost
[mode
][cl
][0]
575 = ira_memory_move_cost
[mode
][cl
][0]
576 = memory_move_cost ((enum machine_mode
) mode
,
577 (reg_class_t
) cl
, false);
578 ira_max_memory_move_cost
[mode
][cl
][1]
579 = ira_memory_move_cost
[mode
][cl
][1]
580 = memory_move_cost ((enum machine_mode
) mode
,
581 (reg_class_t
) cl
, true);
582 /* Costs for NO_REGS are used in cost calculation on the
583 1st pass when the preferred register classes are not
584 known yet. In this case we take the best scenario. */
585 if (ira_memory_move_cost
[mode
][NO_REGS
][0]
586 > ira_memory_move_cost
[mode
][cl
][0])
587 ira_max_memory_move_cost
[mode
][NO_REGS
][0]
588 = ira_memory_move_cost
[mode
][NO_REGS
][0]
589 = ira_memory_move_cost
[mode
][cl
][0];
590 if (ira_memory_move_cost
[mode
][NO_REGS
][1]
591 > ira_memory_move_cost
[mode
][cl
][1])
592 ira_max_memory_move_cost
[mode
][NO_REGS
][1]
593 = ira_memory_move_cost
[mode
][NO_REGS
][1]
594 = ira_memory_move_cost
[mode
][cl
][1];
597 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
598 for (cl2
= (int) N_REG_CLASSES
- 1; cl2
>= 0; cl2
--)
600 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
601 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
602 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
603 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
604 ira_class_subset_p
[cl
][cl2
]
605 = hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
);
606 if (! hard_reg_set_empty_p (temp_hard_regset2
)
607 && hard_reg_set_subset_p (reg_class_contents
[cl2
],
608 reg_class_contents
[cl
]))
609 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
611 cost
= ira_memory_move_cost
[mode
][cl2
][0];
612 if (cost
> ira_max_memory_move_cost
[mode
][cl
][0])
613 ira_max_memory_move_cost
[mode
][cl
][0] = cost
;
614 cost
= ira_memory_move_cost
[mode
][cl2
][1];
615 if (cost
> ira_max_memory_move_cost
[mode
][cl
][1])
616 ira_max_memory_move_cost
[mode
][cl
][1] = cost
;
619 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
620 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
622 ira_memory_move_cost
[mode
][cl
][0]
623 = ira_max_memory_move_cost
[mode
][cl
][0];
624 ira_memory_move_cost
[mode
][cl
][1]
625 = ira_max_memory_move_cost
[mode
][cl
][1];
627 setup_reg_subclasses ();
632 /* Define the following macro if allocation through malloc if
634 #define IRA_NO_OBSTACK
636 #ifndef IRA_NO_OBSTACK
637 /* Obstack used for storing all dynamic data (except bitmaps) of the
639 static struct obstack ira_obstack
;
642 /* Obstack used for storing all bitmaps of the IRA. */
643 static struct bitmap_obstack ira_bitmap_obstack
;
645 /* Allocate memory of size LEN for IRA data. */
647 ira_allocate (size_t len
)
651 #ifndef IRA_NO_OBSTACK
652 res
= obstack_alloc (&ira_obstack
, len
);
659 /* Free memory ADDR allocated for IRA data. */
661 ira_free (void *addr ATTRIBUTE_UNUSED
)
663 #ifndef IRA_NO_OBSTACK
671 /* Allocate and returns bitmap for IRA. */
673 ira_allocate_bitmap (void)
675 return BITMAP_ALLOC (&ira_bitmap_obstack
);
678 /* Free bitmap B allocated for IRA. */
680 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED
)
687 /* Output information about allocation of all allocnos (except for
688 caps) into file F. */
690 ira_print_disposition (FILE *f
)
696 fprintf (f
, "Disposition:");
697 max_regno
= max_reg_num ();
698 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
699 for (a
= ira_regno_allocno_map
[i
];
701 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
706 fprintf (f
, " %4d:r%-4d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
707 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
708 fprintf (f
, "b%-3d", bb
->index
);
710 fprintf (f
, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
711 if (ALLOCNO_HARD_REGNO (a
) >= 0)
712 fprintf (f
, " %3d", ALLOCNO_HARD_REGNO (a
));
719 /* Outputs information about allocation of all allocnos into
722 ira_debug_disposition (void)
724 ira_print_disposition (stderr
);
729 /* Set up ira_stack_reg_pressure_class which is the biggest pressure
730 register class containing stack registers or NO_REGS if there are
731 no stack registers. To find this class, we iterate through all
732 register pressure classes and choose the first register pressure
733 class containing all the stack registers and having the biggest
736 setup_stack_reg_pressure_class (void)
738 ira_stack_reg_pressure_class
= NO_REGS
;
743 HARD_REG_SET temp_hard_regset2
;
745 CLEAR_HARD_REG_SET (temp_hard_regset
);
746 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
747 SET_HARD_REG_BIT (temp_hard_regset
, i
);
749 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
751 cl
= ira_pressure_classes
[i
];
752 COPY_HARD_REG_SET (temp_hard_regset2
, temp_hard_regset
);
753 AND_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
754 size
= hard_reg_set_size (temp_hard_regset2
);
758 ira_stack_reg_pressure_class
= cl
;
765 /* Find pressure classes which are register classes for which we
766 calculate register pressure in IRA, register pressure sensitive
767 insn scheduling, and register pressure sensitive loop invariant
770 To make register pressure calculation easy, we always use
771 non-intersected register pressure classes. A move of hard
772 registers from one register pressure class is not more expensive
773 than load and store of the hard registers. Most likely an allocno
774 class will be a subset of a register pressure class and in many
775 cases a register pressure class. That makes usage of register
776 pressure classes a good approximation to find a high register
779 setup_pressure_classes (void)
781 int cost
, i
, n
, curr
;
783 enum reg_class pressure_classes
[N_REG_CLASSES
];
785 HARD_REG_SET temp_hard_regset2
;
789 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
791 if (ira_class_hard_regs_num
[cl
] == 0)
793 if (ira_class_hard_regs_num
[cl
] != 1
794 /* A register class without subclasses may contain a few
795 hard registers and movement between them is costly
796 (e.g. SPARC FPCC registers). We still should consider it
797 as a candidate for a pressure class. */
798 && alloc_reg_class_subclasses
[cl
][0] < cl
)
800 /* Check that the moves between any hard registers of the
801 current class are not more expensive for a legal mode
802 than load/store of the hard registers of the current
803 class. Such class is a potential candidate to be a
804 register pressure class. */
805 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
807 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
808 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
809 AND_COMPL_HARD_REG_SET (temp_hard_regset
,
810 ira_prohibited_class_mode_regs
[cl
][m
]);
811 if (hard_reg_set_empty_p (temp_hard_regset
))
813 ira_init_register_move_cost_if_necessary ((enum machine_mode
) m
);
814 cost
= ira_register_move_cost
[m
][cl
][cl
];
815 if (cost
<= ira_max_memory_move_cost
[m
][cl
][1]
816 || cost
<= ira_max_memory_move_cost
[m
][cl
][0])
819 if (m
>= NUM_MACHINE_MODES
)
824 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
825 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
826 /* Remove so far added pressure classes which are subset of the
827 current candidate class. Prefer GENERAL_REGS as a pressure
828 register class to another class containing the same
829 allocatable hard registers. We do this because machine
830 dependent cost hooks might give wrong costs for the latter
831 class but always give the right cost for the former class
833 for (i
= 0; i
< n
; i
++)
835 cl2
= pressure_classes
[i
];
836 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
837 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
838 if (hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
)
839 && (! hard_reg_set_equal_p (temp_hard_regset
, temp_hard_regset2
)
840 || cl2
== (int) GENERAL_REGS
))
842 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
846 if (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
)
847 && (! hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
)
848 || cl
== (int) GENERAL_REGS
))
850 if (hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
))
852 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
854 /* If the current candidate is a subset of a so far added
855 pressure class, don't add it to the list of the pressure
858 pressure_classes
[curr
++] = (enum reg_class
) cl
;
861 #ifdef ENABLE_IRA_CHECKING
863 HARD_REG_SET ignore_hard_regs
;
865 /* Check pressure classes correctness: here we check that hard
866 registers from all register pressure classes contains all hard
867 registers available for the allocation. */
868 CLEAR_HARD_REG_SET (temp_hard_regset
);
869 CLEAR_HARD_REG_SET (temp_hard_regset2
);
870 COPY_HARD_REG_SET (ignore_hard_regs
, no_unit_alloc_regs
);
871 for (cl
= 0; cl
< LIM_REG_CLASSES
; cl
++)
873 /* For some targets (like MIPS with MD_REGS), there are some
874 classes with hard registers available for allocation but
875 not able to hold value of any mode. */
876 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
877 if (contains_reg_of_mode
[cl
][m
])
879 if (m
>= NUM_MACHINE_MODES
)
881 IOR_HARD_REG_SET (ignore_hard_regs
, reg_class_contents
[cl
]);
884 for (i
= 0; i
< n
; i
++)
885 if ((int) pressure_classes
[i
] == cl
)
887 IOR_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
889 IOR_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
891 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
892 /* Some targets (like SPARC with ICC reg) have alocatable regs
893 for which no reg class is defined. */
894 if (REGNO_REG_CLASS (i
) == NO_REGS
)
895 SET_HARD_REG_BIT (ignore_hard_regs
, i
);
896 AND_COMPL_HARD_REG_SET (temp_hard_regset
, ignore_hard_regs
);
897 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, ignore_hard_regs
);
898 ira_assert (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
));
901 ira_pressure_classes_num
= 0;
902 for (i
= 0; i
< n
; i
++)
904 cl
= (int) pressure_classes
[i
];
905 ira_reg_pressure_class_p
[cl
] = true;
906 ira_pressure_classes
[ira_pressure_classes_num
++] = (enum reg_class
) cl
;
908 setup_stack_reg_pressure_class ();
911 /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class
912 whose register move cost between any registers of the class is the
913 same as for all its subclasses. We use the data to speed up the
914 2nd pass of calculations of allocno costs. */
916 setup_uniform_class_p (void)
920 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
922 ira_uniform_class_p
[cl
] = false;
923 if (ira_class_hard_regs_num
[cl
] == 0)
925 /* We can not use alloc_reg_class_subclasses here because move
926 cost hooks does not take into account that some registers are
927 unavailable for the subtarget. E.g. for i686, INT_SSE_REGS
928 is element of alloc_reg_class_subclasses for GENERAL_REGS
929 because SSE regs are unavailable. */
930 for (i
= 0; (cl2
= reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
; i
++)
932 if (ira_class_hard_regs_num
[cl2
] == 0)
934 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
935 if (contains_reg_of_mode
[cl
][m
] && contains_reg_of_mode
[cl2
][m
])
937 ira_init_register_move_cost_if_necessary ((enum machine_mode
) m
);
938 if (ira_register_move_cost
[m
][cl
][cl
]
939 != ira_register_move_cost
[m
][cl2
][cl2
])
942 if (m
< NUM_MACHINE_MODES
)
945 if (cl2
== LIM_REG_CLASSES
)
946 ira_uniform_class_p
[cl
] = true;
950 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
951 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
953 Target may have many subtargets and not all target hard regiters can
954 be used for allocation, e.g. x86 port in 32-bit mode can not use
955 hard registers introduced in x86-64 like r8-r15). Some classes
956 might have the same allocatable hard registers, e.g. INDEX_REGS
957 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
958 calculations efforts we introduce allocno classes which contain
959 unique non-empty sets of allocatable hard-registers.
961 Pseudo class cost calculation in ira-costs.c is very expensive.
962 Therefore we are trying to decrease number of classes involved in
963 such calculation. Register classes used in the cost calculation
964 are called important classes. They are allocno classes and other
965 non-empty classes whose allocatable hard register sets are inside
966 of an allocno class hard register set. From the first sight, it
967 looks like that they are just allocno classes. It is not true. In
968 example of x86-port in 32-bit mode, allocno classes will contain
969 GENERAL_REGS but not LEGACY_REGS (because allocatable hard
970 registers are the same for the both classes). The important
971 classes will contain GENERAL_REGS and LEGACY_REGS. It is done
972 because a machine description insn constraint may refers for
973 LEGACY_REGS and code in ira-costs.c is mostly base on investigation
974 of the insn constraints. */
976 setup_allocno_and_important_classes (void)
980 HARD_REG_SET temp_hard_regset2
;
981 static enum reg_class classes
[LIM_REG_CLASSES
+ 1];
984 /* Collect classes which contain unique sets of allocatable hard
985 registers. Prefer GENERAL_REGS to other classes containing the
986 same set of hard registers. */
987 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
989 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
990 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
991 for (j
= 0; j
< n
; j
++)
994 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
995 AND_COMPL_HARD_REG_SET (temp_hard_regset2
,
997 if (hard_reg_set_equal_p (temp_hard_regset
,
1002 classes
[n
++] = (enum reg_class
) i
;
1003 else if (i
== GENERAL_REGS
)
1004 /* Prefer general regs. For i386 example, it means that
1005 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
1006 (all of them consists of the same available hard
1008 classes
[j
] = (enum reg_class
) i
;
1010 classes
[n
] = LIM_REG_CLASSES
;
1012 /* Set up classes which can be used for allocnos as classes
1013 conatining non-empty unique sets of allocatable hard
1015 ira_allocno_classes_num
= 0;
1016 for (i
= 0; (cl
= classes
[i
]) != LIM_REG_CLASSES
; i
++)
1017 if (ira_class_hard_regs_num
[cl
] > 0)
1018 ira_allocno_classes
[ira_allocno_classes_num
++] = (enum reg_class
) cl
;
1019 ira_important_classes_num
= 0;
1020 /* Add non-allocno classes containing to non-empty set of
1021 allocatable hard regs. */
1022 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1023 if (ira_class_hard_regs_num
[cl
] > 0)
1025 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1026 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1028 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1030 COPY_HARD_REG_SET (temp_hard_regset2
,
1031 reg_class_contents
[ira_allocno_classes
[j
]]);
1032 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
1033 if ((enum reg_class
) cl
== ira_allocno_classes
[j
])
1035 else if (hard_reg_set_subset_p (temp_hard_regset
,
1039 if (set_p
&& j
>= ira_allocno_classes_num
)
1040 ira_important_classes
[ira_important_classes_num
++]
1041 = (enum reg_class
) cl
;
1043 /* Now add allocno classes to the important classes. */
1044 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1045 ira_important_classes
[ira_important_classes_num
++]
1046 = ira_allocno_classes
[j
];
1047 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1049 ira_reg_allocno_class_p
[cl
] = false;
1050 ira_reg_pressure_class_p
[cl
] = false;
1052 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1053 ira_reg_allocno_class_p
[ira_allocno_classes
[j
]] = true;
1054 setup_pressure_classes ();
1055 setup_uniform_class_p ();
1058 /* Setup translation in CLASS_TRANSLATE of all classes into a class
1059 given by array CLASSES of length CLASSES_NUM. The function is used
1060 make translation any reg class to an allocno class or to an
1061 pressure class. This translation is necessary for some
1062 calculations when we can use only allocno or pressure classes and
1063 such translation represents an approximate representation of all
1066 The translation in case when allocatable hard register set of a
1067 given class is subset of allocatable hard register set of a class
1068 in CLASSES is pretty simple. We use smallest classes from CLASSES
1069 containing a given class. If allocatable hard register set of a
1070 given class is not a subset of any corresponding set of a class
1071 from CLASSES, we use the cheapest (with load/store point of view)
1072 class from CLASSES whose set intersects with given class set */
1074 setup_class_translate_array (enum reg_class
*class_translate
,
1075 int classes_num
, enum reg_class
*classes
)
1078 enum reg_class aclass
, best_class
, *cl_ptr
;
1079 int i
, cost
, min_cost
, best_cost
;
1081 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1082 class_translate
[cl
] = NO_REGS
;
1084 for (i
= 0; i
< classes_num
; i
++)
1086 aclass
= classes
[i
];
1087 for (cl_ptr
= &alloc_reg_class_subclasses
[aclass
][0];
1088 (cl
= *cl_ptr
) != LIM_REG_CLASSES
;
1090 if (class_translate
[cl
] == NO_REGS
)
1091 class_translate
[cl
] = aclass
;
1092 class_translate
[aclass
] = aclass
;
1094 /* For classes which are not fully covered by one of given classes
1095 (in other words covered by more one given class), use the
1097 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1099 if (cl
== NO_REGS
|| class_translate
[cl
] != NO_REGS
)
1101 best_class
= NO_REGS
;
1102 best_cost
= INT_MAX
;
1103 for (i
= 0; i
< classes_num
; i
++)
1105 aclass
= classes
[i
];
1106 COPY_HARD_REG_SET (temp_hard_regset
,
1107 reg_class_contents
[aclass
]);
1108 AND_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1109 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1110 if (! hard_reg_set_empty_p (temp_hard_regset
))
1113 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1115 cost
= (ira_memory_move_cost
[mode
][aclass
][0]
1116 + ira_memory_move_cost
[mode
][aclass
][1]);
1117 if (min_cost
> cost
)
1120 if (best_class
== NO_REGS
|| best_cost
> min_cost
)
1122 best_class
= aclass
;
1123 best_cost
= min_cost
;
1127 class_translate
[cl
] = best_class
;
1131 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
1132 IRA_PRESSURE_CLASS_TRANSLATE. */
1134 setup_class_translate (void)
1136 setup_class_translate_array (ira_allocno_class_translate
,
1137 ira_allocno_classes_num
, ira_allocno_classes
);
1138 setup_class_translate_array (ira_pressure_class_translate
,
1139 ira_pressure_classes_num
, ira_pressure_classes
);
1142 /* Order numbers of allocno classes in original target allocno class
1143 array, -1 for non-allocno classes. */
1144 static int allocno_class_order
[N_REG_CLASSES
];
1146 /* The function used to sort the important classes. */
1148 comp_reg_classes_func (const void *v1p
, const void *v2p
)
1150 enum reg_class cl1
= *(const enum reg_class
*) v1p
;
1151 enum reg_class cl2
= *(const enum reg_class
*) v2p
;
1152 enum reg_class tcl1
, tcl2
;
1155 tcl1
= ira_allocno_class_translate
[cl1
];
1156 tcl2
= ira_allocno_class_translate
[cl2
];
1157 if (tcl1
!= NO_REGS
&& tcl2
!= NO_REGS
1158 && (diff
= allocno_class_order
[tcl1
] - allocno_class_order
[tcl2
]) != 0)
1160 return (int) cl1
- (int) cl2
;
1163 /* For correct work of function setup_reg_class_relation we need to
1164 reorder important classes according to the order of their allocno
1165 classes. It places important classes containing the same
1166 allocatable hard register set adjacent to each other and allocno
1167 class with the allocatable hard register set right after the other
1168 important classes with the same set.
1170 In example from comments of function
1171 setup_allocno_and_important_classes, it places LEGACY_REGS and
1172 GENERAL_REGS close to each other and GENERAL_REGS is after
1175 reorder_important_classes (void)
1179 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1180 allocno_class_order
[i
] = -1;
1181 for (i
= 0; i
< ira_allocno_classes_num
; i
++)
1182 allocno_class_order
[ira_allocno_classes
[i
]] = i
;
1183 qsort (ira_important_classes
, ira_important_classes_num
,
1184 sizeof (enum reg_class
), comp_reg_classes_func
);
1185 for (i
= 0; i
< ira_important_classes_num
; i
++)
1186 ira_important_class_nums
[ira_important_classes
[i
]] = i
;
1189 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
1190 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
1191 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
1192 please see corresponding comments in ira-int.h. */
1194 setup_reg_class_relations (void)
1196 int i
, cl1
, cl2
, cl3
;
1197 HARD_REG_SET intersection_set
, union_set
, temp_set2
;
1198 bool important_class_p
[N_REG_CLASSES
];
1200 memset (important_class_p
, 0, sizeof (important_class_p
));
1201 for (i
= 0; i
< ira_important_classes_num
; i
++)
1202 important_class_p
[ira_important_classes
[i
]] = true;
1203 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1205 ira_reg_class_super_classes
[cl1
][0] = LIM_REG_CLASSES
;
1206 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1208 ira_reg_classes_intersect_p
[cl1
][cl2
] = false;
1209 ira_reg_class_intersect
[cl1
][cl2
] = NO_REGS
;
1210 ira_reg_class_subset
[cl1
][cl2
] = NO_REGS
;
1211 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl1
]);
1212 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1213 COPY_HARD_REG_SET (temp_set2
, reg_class_contents
[cl2
]);
1214 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1215 if (hard_reg_set_empty_p (temp_hard_regset
)
1216 && hard_reg_set_empty_p (temp_set2
))
1218 /* The both classes have no allocatable hard registers
1219 -- take all class hard registers into account and use
1220 reg_class_subunion and reg_class_superunion. */
1223 cl3
= reg_class_subclasses
[cl1
][i
];
1224 if (cl3
== LIM_REG_CLASSES
)
1226 if (reg_class_subset_p (ira_reg_class_intersect
[cl1
][cl2
],
1227 (enum reg_class
) cl3
))
1228 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1230 ira_reg_class_subunion
[cl1
][cl2
] = reg_class_subunion
[cl1
][cl2
];
1231 ira_reg_class_superunion
[cl1
][cl2
] = reg_class_superunion
[cl1
][cl2
];
1234 ira_reg_classes_intersect_p
[cl1
][cl2
]
1235 = hard_reg_set_intersect_p (temp_hard_regset
, temp_set2
);
1236 if (important_class_p
[cl1
] && important_class_p
[cl2
]
1237 && hard_reg_set_subset_p (temp_hard_regset
, temp_set2
))
1239 /* CL1 and CL2 are important classes and CL1 allocatable
1240 hard register set is inside of CL2 allocatable hard
1241 registers -- make CL1 a superset of CL2. */
1244 p
= &ira_reg_class_super_classes
[cl1
][0];
1245 while (*p
!= LIM_REG_CLASSES
)
1247 *p
++ = (enum reg_class
) cl2
;
1248 *p
= LIM_REG_CLASSES
;
1250 ira_reg_class_subunion
[cl1
][cl2
] = NO_REGS
;
1251 ira_reg_class_superunion
[cl1
][cl2
] = NO_REGS
;
1252 COPY_HARD_REG_SET (intersection_set
, reg_class_contents
[cl1
]);
1253 AND_HARD_REG_SET (intersection_set
, reg_class_contents
[cl2
]);
1254 AND_COMPL_HARD_REG_SET (intersection_set
, no_unit_alloc_regs
);
1255 COPY_HARD_REG_SET (union_set
, reg_class_contents
[cl1
]);
1256 IOR_HARD_REG_SET (union_set
, reg_class_contents
[cl2
]);
1257 AND_COMPL_HARD_REG_SET (union_set
, no_unit_alloc_regs
);
1258 for (cl3
= 0; cl3
< N_REG_CLASSES
; cl3
++)
1260 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl3
]);
1261 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1262 if (hard_reg_set_subset_p (temp_hard_regset
, intersection_set
))
1264 /* CL3 allocatable hard register set is inside of
1265 intersection of allocatable hard register sets
1267 if (important_class_p
[cl3
])
1272 [(int) ira_reg_class_intersect
[cl1
][cl2
]]);
1273 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1274 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1275 /* If the allocatable hard register sets are
1276 the same, prefer GENERAL_REGS or the
1277 smallest class for debugging
1279 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1280 && (cl3
== GENERAL_REGS
1281 || ((ira_reg_class_intersect
[cl1
][cl2
]
1283 && hard_reg_set_subset_p
1284 (reg_class_contents
[cl3
],
1287 ira_reg_class_intersect
[cl1
][cl2
]])))))
1288 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1292 reg_class_contents
[(int) ira_reg_class_subset
[cl1
][cl2
]]);
1293 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1294 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1295 /* Ignore unavailable hard registers and prefer
1296 smallest class for debugging purposes. */
1297 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1298 && hard_reg_set_subset_p
1299 (reg_class_contents
[cl3
],
1301 [(int) ira_reg_class_subset
[cl1
][cl2
]])))
1302 ira_reg_class_subset
[cl1
][cl2
] = (enum reg_class
) cl3
;
1304 if (important_class_p
[cl3
]
1305 && hard_reg_set_subset_p (temp_hard_regset
, union_set
))
1307 /* CL3 allocatbale hard register set is inside of
1308 union of allocatable hard register sets of CL1
1312 reg_class_contents
[(int) ira_reg_class_subunion
[cl1
][cl2
]]);
1313 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1314 if (ira_reg_class_subunion
[cl1
][cl2
] == NO_REGS
1315 || (hard_reg_set_subset_p (temp_set2
, temp_hard_regset
)
1317 && (! hard_reg_set_equal_p (temp_set2
,
1319 || cl3
== GENERAL_REGS
1320 /* If the allocatable hard register sets are the
1321 same, prefer GENERAL_REGS or the smallest
1322 class for debugging purposes. */
1323 || (ira_reg_class_subunion
[cl1
][cl2
] != GENERAL_REGS
1324 && hard_reg_set_subset_p
1325 (reg_class_contents
[cl3
],
1327 [(int) ira_reg_class_subunion
[cl1
][cl2
]])))))
1328 ira_reg_class_subunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1330 if (hard_reg_set_subset_p (union_set
, temp_hard_regset
))
1332 /* CL3 allocatable hard register set contains union
1333 of allocatable hard register sets of CL1 and
1337 reg_class_contents
[(int) ira_reg_class_superunion
[cl1
][cl2
]]);
1338 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1339 if (ira_reg_class_superunion
[cl1
][cl2
] == NO_REGS
1340 || (hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1342 && (! hard_reg_set_equal_p (temp_set2
,
1344 || cl3
== GENERAL_REGS
1345 /* If the allocatable hard register sets are the
1346 same, prefer GENERAL_REGS or the smallest
1347 class for debugging purposes. */
1348 || (ira_reg_class_superunion
[cl1
][cl2
] != GENERAL_REGS
1349 && hard_reg_set_subset_p
1350 (reg_class_contents
[cl3
],
1352 [(int) ira_reg_class_superunion
[cl1
][cl2
]])))))
1353 ira_reg_class_superunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1360 /* Output all unifrom and important classes into file F. */
1362 print_unform_and_important_classes (FILE *f
)
1364 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1367 fprintf (f
, "Uniform classes:\n");
1368 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1369 if (ira_uniform_class_p
[cl
])
1370 fprintf (f
, " %s", reg_class_names
[cl
]);
1371 fprintf (f
, "\nImportant classes:\n");
1372 for (i
= 0; i
< ira_important_classes_num
; i
++)
1373 fprintf (f
, " %s", reg_class_names
[ira_important_classes
[i
]]);
1377 /* Output all possible allocno or pressure classes and their
1378 translation map into file F. */
1380 print_translated_classes (FILE *f
, bool pressure_p
)
1382 int classes_num
= (pressure_p
1383 ? ira_pressure_classes_num
: ira_allocno_classes_num
);
1384 enum reg_class
*classes
= (pressure_p
1385 ? ira_pressure_classes
: ira_allocno_classes
);
1386 enum reg_class
*class_translate
= (pressure_p
1387 ? ira_pressure_class_translate
1388 : ira_allocno_class_translate
);
1389 static const char *const reg_class_names
[] = REG_CLASS_NAMES
;
1392 fprintf (f
, "%s classes:\n", pressure_p
? "Pressure" : "Allocno");
1393 for (i
= 0; i
< classes_num
; i
++)
1394 fprintf (f
, " %s", reg_class_names
[classes
[i
]]);
1395 fprintf (f
, "\nClass translation:\n");
1396 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1397 fprintf (f
, " %s -> %s\n", reg_class_names
[i
],
1398 reg_class_names
[class_translate
[i
]]);
1401 /* Output all possible allocno and translation classes and the
1402 translation maps into stderr. */
1404 ira_debug_allocno_classes (void)
1406 print_unform_and_important_classes (stderr
);
1407 print_translated_classes (stderr
, false);
1408 print_translated_classes (stderr
, true);
1411 /* Set up different arrays concerning class subsets, allocno and
1412 important classes. */
1414 find_reg_classes (void)
1416 setup_allocno_and_important_classes ();
1417 setup_class_translate ();
1418 reorder_important_classes ();
1419 setup_reg_class_relations ();
1424 /* Set up the array above. */
1426 setup_hard_regno_aclass (void)
1430 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1433 ira_hard_regno_allocno_class
[i
]
1434 = (TEST_HARD_REG_BIT (no_unit_alloc_regs
, i
)
1436 : ira_allocno_class_translate
[REGNO_REG_CLASS (i
)]);
1440 ira_hard_regno_allocno_class
[i
] = NO_REGS
;
1441 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1443 cl
= ira_allocno_classes
[j
];
1444 if (ira_class_hard_reg_index
[cl
][i
] >= 0)
1446 ira_hard_regno_allocno_class
[i
] = cl
;
1456 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
1458 setup_reg_class_nregs (void)
1462 for (m
= 0; m
< MAX_MACHINE_MODE
; m
++)
1464 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1465 ira_reg_class_max_nregs
[cl
][m
]
1466 = ira_reg_class_min_nregs
[cl
][m
]
1467 = targetm
.class_max_nregs ((reg_class_t
) cl
, (enum machine_mode
) m
);
1468 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1470 (cl2
= alloc_reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
;
1472 if (ira_reg_class_min_nregs
[cl2
][m
]
1473 < ira_reg_class_min_nregs
[cl
][m
])
1474 ira_reg_class_min_nregs
[cl
][m
] = ira_reg_class_min_nregs
[cl2
][m
];
1480 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON.
1481 This function is called once IRA_CLASS_HARD_REGS has been initialized. */
1483 setup_prohibited_class_mode_regs (void)
1485 int j
, k
, hard_regno
, cl
, last_hard_regno
, count
;
1487 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1489 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1490 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1491 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1494 last_hard_regno
= -1;
1495 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs
[cl
][j
]);
1496 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1498 hard_regno
= ira_class_hard_regs
[cl
][k
];
1499 if (! HARD_REGNO_MODE_OK (hard_regno
, (enum machine_mode
) j
))
1500 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1502 else if (in_hard_reg_set_p (temp_hard_regset
,
1503 (enum machine_mode
) j
, hard_regno
))
1505 last_hard_regno
= hard_regno
;
1509 ira_class_singleton
[cl
][j
] = (count
== 1 ? last_hard_regno
: -1);
1514 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
1515 spanning from one register pressure class to another one. It is
1516 called after defining the pressure classes. */
1518 clarify_prohibited_class_mode_regs (void)
1520 int j
, k
, hard_regno
, cl
, pclass
, nregs
;
1522 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1523 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1525 CLEAR_HARD_REG_SET (ira_useful_class_mode_regs
[cl
][j
]);
1526 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1528 hard_regno
= ira_class_hard_regs
[cl
][k
];
1529 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
], hard_regno
))
1531 nregs
= hard_regno_nregs
[hard_regno
][j
];
1532 if (hard_regno
+ nregs
> FIRST_PSEUDO_REGISTER
)
1534 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1538 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1539 for (nregs
-- ;nregs
>= 0; nregs
--)
1540 if (((enum reg_class
) pclass
1541 != ira_pressure_class_translate
[REGNO_REG_CLASS
1542 (hard_regno
+ nregs
)]))
1544 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1548 if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1550 add_to_hard_reg_set (&ira_useful_class_mode_regs
[cl
][j
],
1551 (enum machine_mode
) j
, hard_regno
);
1556 /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST
1557 and IRA_MAY_MOVE_OUT_COST for MODE. */
1559 ira_init_register_move_cost (enum machine_mode mode
)
1561 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
1562 bool all_match
= true;
1563 unsigned int cl1
, cl2
;
1565 ira_assert (ira_register_move_cost
[mode
] == NULL
1566 && ira_may_move_in_cost
[mode
] == NULL
1567 && ira_may_move_out_cost
[mode
] == NULL
);
1568 ira_assert (have_regs_of_mode
[mode
]);
1569 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1570 if (contains_reg_of_mode
[cl1
][mode
])
1571 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1574 if (!contains_reg_of_mode
[cl2
][mode
])
1578 cost
= register_move_cost (mode
, (enum reg_class
) cl1
,
1579 (enum reg_class
) cl2
);
1580 ira_assert (cost
< 65535);
1582 all_match
&= (last_move_cost
[cl1
][cl2
] == cost
);
1583 last_move_cost
[cl1
][cl2
] = cost
;
1585 if (all_match
&& last_mode_for_init_move_cost
!= -1)
1587 ira_register_move_cost
[mode
]
1588 = ira_register_move_cost
[last_mode_for_init_move_cost
];
1589 ira_may_move_in_cost
[mode
]
1590 = ira_may_move_in_cost
[last_mode_for_init_move_cost
];
1591 ira_may_move_out_cost
[mode
]
1592 = ira_may_move_out_cost
[last_mode_for_init_move_cost
];
1595 last_mode_for_init_move_cost
= mode
;
1596 ira_register_move_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1597 ira_may_move_in_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1598 ira_may_move_out_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1599 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1600 if (contains_reg_of_mode
[cl1
][mode
])
1601 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1604 enum reg_class
*p1
, *p2
;
1606 if (last_move_cost
[cl1
][cl2
] == 65535)
1608 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1609 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1610 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1614 cost
= last_move_cost
[cl1
][cl2
];
1616 for (p2
= ®_class_subclasses
[cl2
][0];
1617 *p2
!= LIM_REG_CLASSES
; p2
++)
1618 if (ira_class_hard_regs_num
[*p2
] > 0
1619 && (ira_reg_class_max_nregs
[*p2
][mode
]
1620 <= ira_class_hard_regs_num
[*p2
]))
1621 cost
= MAX (cost
, ira_register_move_cost
[mode
][cl1
][*p2
]);
1623 for (p1
= ®_class_subclasses
[cl1
][0];
1624 *p1
!= LIM_REG_CLASSES
; p1
++)
1625 if (ira_class_hard_regs_num
[*p1
] > 0
1626 && (ira_reg_class_max_nregs
[*p1
][mode
]
1627 <= ira_class_hard_regs_num
[*p1
]))
1628 cost
= MAX (cost
, ira_register_move_cost
[mode
][*p1
][cl2
]);
1630 ira_assert (cost
<= 65535);
1631 ira_register_move_cost
[mode
][cl1
][cl2
] = cost
;
1633 if (ira_class_subset_p
[cl1
][cl2
])
1634 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 0;
1636 ira_may_move_in_cost
[mode
][cl1
][cl2
] = cost
;
1638 if (ira_class_subset_p
[cl2
][cl1
])
1639 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 0;
1641 ira_may_move_out_cost
[mode
][cl1
][cl2
] = cost
;
1645 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1647 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1648 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1649 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1654 /* This is called once during compiler work. It sets up
1655 different arrays whose values don't depend on the compiled
1658 ira_init_once (void)
1660 ira_init_costs_once ();
1664 /* Free ira_max_register_move_cost, ira_may_move_in_cost and
1665 ira_may_move_out_cost for each mode. */
1667 free_register_move_costs (void)
1671 /* Reset move_cost and friends, making sure we only free shared
1672 table entries once. */
1673 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1674 if (ira_register_move_cost
[mode
])
1677 i
< mode
&& (ira_register_move_cost
[i
]
1678 != ira_register_move_cost
[mode
]);
1683 free (ira_register_move_cost
[mode
]);
1684 free (ira_may_move_in_cost
[mode
]);
1685 free (ira_may_move_out_cost
[mode
]);
1688 memset (ira_register_move_cost
, 0, sizeof ira_register_move_cost
);
1689 memset (ira_may_move_in_cost
, 0, sizeof ira_may_move_in_cost
);
1690 memset (ira_may_move_out_cost
, 0, sizeof ira_may_move_out_cost
);
1691 last_mode_for_init_move_cost
= -1;
1694 /* This is called every time when register related information is
1699 free_register_move_costs ();
1700 setup_reg_mode_hard_regset ();
1701 setup_alloc_regs (flag_omit_frame_pointer
!= 0);
1702 setup_class_subset_and_memory_move_costs ();
1703 setup_reg_class_nregs ();
1704 setup_prohibited_class_mode_regs ();
1705 find_reg_classes ();
1706 clarify_prohibited_class_mode_regs ();
1707 setup_hard_regno_aclass ();
1712 /* Function called once at the end of compiler work. */
1714 ira_finish_once (void)
1716 ira_finish_costs_once ();
1717 free_register_move_costs ();
1722 #define ira_prohibited_mode_move_regs_initialized_p \
1723 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p)
1725 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */
1727 setup_prohibited_mode_move_regs (void)
1730 rtx test_reg1
, test_reg2
, move_pat
, move_insn
;
1732 if (ira_prohibited_mode_move_regs_initialized_p
)
1734 ira_prohibited_mode_move_regs_initialized_p
= true;
1735 test_reg1
= gen_rtx_REG (VOIDmode
, 0);
1736 test_reg2
= gen_rtx_REG (VOIDmode
, 0);
1737 move_pat
= gen_rtx_SET (VOIDmode
, test_reg1
, test_reg2
);
1738 move_insn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, 0, move_pat
, 0, -1, 0);
1739 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1741 SET_HARD_REG_SET (ira_prohibited_mode_move_regs
[i
]);
1742 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1744 if (! HARD_REGNO_MODE_OK (j
, (enum machine_mode
) i
))
1746 SET_REGNO_RAW (test_reg1
, j
);
1747 PUT_MODE (test_reg1
, (enum machine_mode
) i
);
1748 SET_REGNO_RAW (test_reg2
, j
);
1749 PUT_MODE (test_reg2
, (enum machine_mode
) i
);
1750 INSN_CODE (move_insn
) = -1;
1751 recog_memoized (move_insn
);
1752 if (INSN_CODE (move_insn
) < 0)
1754 extract_insn (move_insn
);
1755 if (! constrain_operands (1))
1757 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs
[i
], j
);
1764 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */
1766 ira_bad_reload_regno_1 (int regno
, rtx x
)
1770 enum reg_class pref
;
1772 /* We only deal with pseudo regs. */
1773 if (! x
|| GET_CODE (x
) != REG
)
1776 x_regno
= REGNO (x
);
1777 if (x_regno
< FIRST_PSEUDO_REGISTER
)
1780 /* If the pseudo prefers REGNO explicitly, then do not consider
1781 REGNO a bad spill choice. */
1782 pref
= reg_preferred_class (x_regno
);
1783 if (reg_class_size
[pref
] == 1)
1784 return !TEST_HARD_REG_BIT (reg_class_contents
[pref
], regno
);
1786 /* If the pseudo conflicts with REGNO, then we consider REGNO a
1787 poor choice for a reload regno. */
1788 a
= ira_regno_allocno_map
[x_regno
];
1789 n
= ALLOCNO_NUM_OBJECTS (a
);
1790 for (i
= 0; i
< n
; i
++)
1792 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
1793 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
))
1799 /* Return nonzero if REGNO is a particularly bad choice for reloading
1802 ira_bad_reload_regno (int regno
, rtx in
, rtx out
)
1804 return (ira_bad_reload_regno_1 (regno
, in
)
1805 || ira_bad_reload_regno_1 (regno
, out
));
1808 /* Return TRUE if *LOC contains an asm. */
1810 insn_contains_asm_1 (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
1814 if (GET_CODE (*loc
) == ASM_OPERANDS
)
1820 /* Return TRUE if INSN contains an ASM. */
1822 insn_contains_asm (rtx insn
)
1824 return for_each_rtx (&insn
, insn_contains_asm_1
, NULL
);
1827 /* Add register clobbers from asm statements. */
1829 compute_regs_asm_clobbered (void)
1836 FOR_BB_INSNS_REVERSE (bb
, insn
)
1840 if (insn_contains_asm (insn
))
1841 for (def_rec
= DF_INSN_DEFS (insn
); *def_rec
; def_rec
++)
1843 df_ref def
= *def_rec
;
1844 unsigned int dregno
= DF_REF_REGNO (def
);
1845 if (HARD_REGISTER_NUM_P (dregno
))
1846 add_to_hard_reg_set (&crtl
->asm_clobbers
,
1847 GET_MODE (DF_REF_REAL_REG (def
)),
1855 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and REGS_EVER_LIVE.
1856 If the function is called from IRA (not from the insn scheduler or
1857 RTL loop invariant motion), FROM_IRA_P is true. */
1859 ira_setup_eliminable_regset (bool from_ira_p
)
1861 #ifdef ELIMINABLE_REGS
1863 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
1865 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore
1866 sp for alloca. So we can't eliminate the frame pointer in that
1867 case. At some point, we should improve this by emitting the
1868 sp-adjusting insns for this case. */
1869 frame_pointer_needed
1870 = (! flag_omit_frame_pointer
1871 || (cfun
->calls_alloca
&& EXIT_IGNORE_STACK
)
1872 /* We need the frame pointer to catch stack overflow exceptions
1873 if the stack pointer is moving. */
1874 || (flag_stack_check
&& STACK_CHECK_MOVING_SP
)
1875 || crtl
->accesses_prior_frames
1876 || crtl
->stack_realign_needed
1877 /* We need a frame pointer for all Cilk Plus functions that use
1879 || (flag_enable_cilkplus
&& cfun
->is_cilk_function
)
1880 || targetm
.frame_pointer_required ());
1882 if (from_ira_p
&& ira_use_lra_p
)
1883 /* It can change FRAME_POINTER_NEEDED. We call it only from IRA
1884 because it is expensive. */
1885 lra_init_elimination ();
1887 if (frame_pointer_needed
)
1888 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
1890 COPY_HARD_REG_SET (ira_no_alloc_regs
, no_unit_alloc_regs
);
1891 CLEAR_HARD_REG_SET (eliminable_regset
);
1893 compute_regs_asm_clobbered ();
1895 /* Build the regset of all eliminable registers and show we can't
1896 use those that we already know won't be eliminated. */
1897 #ifdef ELIMINABLE_REGS
1898 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
1901 = (! targetm
.can_eliminate (eliminables
[i
].from
, eliminables
[i
].to
)
1902 || (eliminables
[i
].to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
1904 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, eliminables
[i
].from
))
1906 SET_HARD_REG_BIT (eliminable_regset
, eliminables
[i
].from
);
1909 SET_HARD_REG_BIT (ira_no_alloc_regs
, eliminables
[i
].from
);
1911 else if (cannot_elim
)
1912 error ("%s cannot be used in asm here",
1913 reg_names
[eliminables
[i
].from
]);
1915 df_set_regs_ever_live (eliminables
[i
].from
, true);
1917 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1918 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
1920 SET_HARD_REG_BIT (eliminable_regset
, HARD_FRAME_POINTER_REGNUM
);
1921 if (frame_pointer_needed
)
1922 SET_HARD_REG_BIT (ira_no_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
1924 else if (frame_pointer_needed
)
1925 error ("%s cannot be used in asm here",
1926 reg_names
[HARD_FRAME_POINTER_REGNUM
]);
1928 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
1932 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
1934 SET_HARD_REG_BIT (eliminable_regset
, FRAME_POINTER_REGNUM
);
1935 if (frame_pointer_needed
)
1936 SET_HARD_REG_BIT (ira_no_alloc_regs
, FRAME_POINTER_REGNUM
);
1938 else if (frame_pointer_needed
)
1939 error ("%s cannot be used in asm here", reg_names
[FRAME_POINTER_REGNUM
]);
1941 df_set_regs_ever_live (FRAME_POINTER_REGNUM
, true);
1947 /* Vector of substitutions of register numbers,
1948 used to map pseudo regs into hardware regs.
1949 This is set up as a result of register allocation.
1950 Element N is the hard reg assigned to pseudo reg N,
1951 or is -1 if no hard reg was assigned.
1952 If N is a hard reg number, element N is N. */
1953 short *reg_renumber
;
1955 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from
1956 the allocation found by IRA. */
1958 setup_reg_renumber (void)
1960 int regno
, hard_regno
;
1962 ira_allocno_iterator ai
;
1964 caller_save_needed
= 0;
1965 FOR_EACH_ALLOCNO (a
, ai
)
1967 if (ira_use_lra_p
&& ALLOCNO_CAP_MEMBER (a
) != NULL
)
1969 /* There are no caps at this point. */
1970 ira_assert (ALLOCNO_CAP_MEMBER (a
) == NULL
);
1971 if (! ALLOCNO_ASSIGNED_P (a
))
1972 /* It can happen if A is not referenced but partially anticipated
1973 somewhere in a region. */
1974 ALLOCNO_ASSIGNED_P (a
) = true;
1975 ira_free_allocno_updated_costs (a
);
1976 hard_regno
= ALLOCNO_HARD_REGNO (a
);
1977 regno
= ALLOCNO_REGNO (a
);
1978 reg_renumber
[regno
] = (hard_regno
< 0 ? -1 : hard_regno
);
1979 if (hard_regno
>= 0)
1982 enum reg_class pclass
;
1985 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1986 nwords
= ALLOCNO_NUM_OBJECTS (a
);
1987 for (i
= 0; i
< nwords
; i
++)
1989 obj
= ALLOCNO_OBJECT (a
, i
);
1990 IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
1991 reg_class_contents
[pclass
]);
1993 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0
1994 && ira_hard_reg_set_intersection_p (hard_regno
, ALLOCNO_MODE (a
),
1997 ira_assert (!optimize
|| flag_caller_saves
1998 || (ALLOCNO_CALLS_CROSSED_NUM (a
)
1999 == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2000 || regno
>= ira_reg_equiv_len
2001 || ira_equiv_no_lvalue_p (regno
));
2002 caller_save_needed
= 1;
2008 /* Set up allocno assignment flags for further allocation
2011 setup_allocno_assignment_flags (void)
2015 ira_allocno_iterator ai
;
2017 FOR_EACH_ALLOCNO (a
, ai
)
2019 if (! ALLOCNO_ASSIGNED_P (a
))
2020 /* It can happen if A is not referenced but partially anticipated
2021 somewhere in a region. */
2022 ira_free_allocno_updated_costs (a
);
2023 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2024 /* Don't assign hard registers to allocnos which are destination
2025 of removed store at the end of loop. It has no sense to keep
2026 the same value in different hard registers. It is also
2027 impossible to assign hard registers correctly to such
2028 allocnos because the cost info and info about intersected
2029 calls are incorrect for them. */
2030 ALLOCNO_ASSIGNED_P (a
) = (hard_regno
>= 0
2031 || ALLOCNO_EMIT_DATA (a
)->mem_optimized_dest_p
2032 || (ALLOCNO_MEMORY_COST (a
)
2033 - ALLOCNO_CLASS_COST (a
)) < 0);
2036 || ira_hard_reg_in_set_p (hard_regno
, ALLOCNO_MODE (a
),
2037 reg_class_contents
[ALLOCNO_CLASS (a
)]));
2041 /* Evaluate overall allocation cost and the costs for using hard
2042 registers and memory for allocnos. */
2044 calculate_allocation_cost (void)
2046 int hard_regno
, cost
;
2048 ira_allocno_iterator ai
;
2050 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
2051 FOR_EACH_ALLOCNO (a
, ai
)
2053 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2054 ira_assert (hard_regno
< 0
2055 || (ira_hard_reg_in_set_p
2056 (hard_regno
, ALLOCNO_MODE (a
),
2057 reg_class_contents
[ALLOCNO_CLASS (a
)])));
2060 cost
= ALLOCNO_MEMORY_COST (a
);
2061 ira_mem_cost
+= cost
;
2063 else if (ALLOCNO_HARD_REG_COSTS (a
) != NULL
)
2065 cost
= (ALLOCNO_HARD_REG_COSTS (a
)
2066 [ira_class_hard_reg_index
2067 [ALLOCNO_CLASS (a
)][hard_regno
]]);
2068 ira_reg_cost
+= cost
;
2072 cost
= ALLOCNO_CLASS_COST (a
);
2073 ira_reg_cost
+= cost
;
2075 ira_overall_cost
+= cost
;
2078 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
2080 fprintf (ira_dump_file
,
2081 "+++Costs: overall %d, reg %d, mem %d, ld %d, st %d, move %d\n",
2082 ira_overall_cost
, ira_reg_cost
, ira_mem_cost
,
2083 ira_load_cost
, ira_store_cost
, ira_shuffle_cost
);
2084 fprintf (ira_dump_file
, "+++ move loops %d, new jumps %d\n",
2085 ira_move_loops_num
, ira_additional_jumps_num
);
2090 #ifdef ENABLE_IRA_CHECKING
2091 /* Check the correctness of the allocation. We do need this because
2092 of complicated code to transform more one region internal
2093 representation into one region representation. */
2095 check_allocation (void)
2098 int hard_regno
, nregs
, conflict_nregs
;
2099 ira_allocno_iterator ai
;
2101 FOR_EACH_ALLOCNO (a
, ai
)
2103 int n
= ALLOCNO_NUM_OBJECTS (a
);
2106 if (ALLOCNO_CAP_MEMBER (a
) != NULL
2107 || (hard_regno
= ALLOCNO_HARD_REGNO (a
)) < 0)
2109 nregs
= hard_regno_nregs
[hard_regno
][ALLOCNO_MODE (a
)];
2111 /* We allocated a single hard register. */
2114 /* We allocated multiple hard registers, and we will test
2115 conflicts in a granularity of single hard regs. */
2118 for (i
= 0; i
< n
; i
++)
2120 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2121 ira_object_t conflict_obj
;
2122 ira_object_conflict_iterator oci
;
2123 int this_regno
= hard_regno
;
2126 if (REG_WORDS_BIG_ENDIAN
)
2127 this_regno
+= n
- i
- 1;
2131 FOR_EACH_OBJECT_CONFLICT (obj
, conflict_obj
, oci
)
2133 ira_allocno_t conflict_a
= OBJECT_ALLOCNO (conflict_obj
);
2134 int conflict_hard_regno
= ALLOCNO_HARD_REGNO (conflict_a
);
2135 if (conflict_hard_regno
< 0)
2140 [conflict_hard_regno
][ALLOCNO_MODE (conflict_a
)]);
2142 if (ALLOCNO_NUM_OBJECTS (conflict_a
) > 1
2143 && conflict_nregs
== ALLOCNO_NUM_OBJECTS (conflict_a
))
2145 if (REG_WORDS_BIG_ENDIAN
)
2146 conflict_hard_regno
+= (ALLOCNO_NUM_OBJECTS (conflict_a
)
2147 - OBJECT_SUBWORD (conflict_obj
) - 1);
2149 conflict_hard_regno
+= OBJECT_SUBWORD (conflict_obj
);
2153 if ((conflict_hard_regno
<= this_regno
2154 && this_regno
< conflict_hard_regno
+ conflict_nregs
)
2155 || (this_regno
<= conflict_hard_regno
2156 && conflict_hard_regno
< this_regno
+ nregs
))
2158 fprintf (stderr
, "bad allocation for %d and %d\n",
2159 ALLOCNO_REGNO (a
), ALLOCNO_REGNO (conflict_a
));
2168 /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should
2169 be already calculated. */
2171 setup_reg_equiv_init (void)
2174 int max_regno
= max_reg_num ();
2176 for (i
= 0; i
< max_regno
; i
++)
2177 reg_equiv_init (i
) = ira_reg_equiv
[i
].init_insns
;
2180 /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS
2181 are insns which were generated for such movement. It is assumed
2182 that FROM_REGNO and TO_REGNO always have the same value at the
2183 point of any move containing such registers. This function is used
2184 to update equiv info for register shuffles on the region borders
2185 and for caller save/restore insns. */
2187 ira_update_equiv_info_by_shuffle_insn (int to_regno
, int from_regno
, rtx insns
)
2191 if (! ira_reg_equiv
[from_regno
].defined_p
2192 && (! ira_reg_equiv
[to_regno
].defined_p
2193 || ((x
= ira_reg_equiv
[to_regno
].memory
) != NULL_RTX
2194 && ! MEM_READONLY_P (x
))))
2197 if (NEXT_INSN (insn
) != NULL_RTX
)
2199 if (! ira_reg_equiv
[to_regno
].defined_p
)
2201 ira_assert (ira_reg_equiv
[to_regno
].init_insns
== NULL_RTX
);
2204 ira_reg_equiv
[to_regno
].defined_p
= false;
2205 ira_reg_equiv
[to_regno
].memory
2206 = ira_reg_equiv
[to_regno
].constant
2207 = ira_reg_equiv
[to_regno
].invariant
2208 = ira_reg_equiv
[to_regno
].init_insns
= NULL_RTX
;
2209 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2210 fprintf (ira_dump_file
,
2211 " Invalidating equiv info for reg %d\n", to_regno
);
2214 /* It is possible that FROM_REGNO still has no equivalence because
2215 in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd
2216 insn was not processed yet. */
2217 if (ira_reg_equiv
[from_regno
].defined_p
)
2219 ira_reg_equiv
[to_regno
].defined_p
= true;
2220 if ((x
= ira_reg_equiv
[from_regno
].memory
) != NULL_RTX
)
2222 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
2223 && ira_reg_equiv
[from_regno
].constant
== NULL_RTX
);
2224 ira_assert (ira_reg_equiv
[to_regno
].memory
== NULL_RTX
2225 || rtx_equal_p (ira_reg_equiv
[to_regno
].memory
, x
));
2226 ira_reg_equiv
[to_regno
].memory
= x
;
2227 if (! MEM_READONLY_P (x
))
2228 /* We don't add the insn to insn init list because memory
2229 equivalence is just to say what memory is better to use
2230 when the pseudo is spilled. */
2233 else if ((x
= ira_reg_equiv
[from_regno
].constant
) != NULL_RTX
)
2235 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
);
2236 ira_assert (ira_reg_equiv
[to_regno
].constant
== NULL_RTX
2237 || rtx_equal_p (ira_reg_equiv
[to_regno
].constant
, x
));
2238 ira_reg_equiv
[to_regno
].constant
= x
;
2242 x
= ira_reg_equiv
[from_regno
].invariant
;
2243 ira_assert (x
!= NULL_RTX
);
2244 ira_assert (ira_reg_equiv
[to_regno
].invariant
== NULL_RTX
2245 || rtx_equal_p (ira_reg_equiv
[to_regno
].invariant
, x
));
2246 ira_reg_equiv
[to_regno
].invariant
= x
;
2248 if (find_reg_note (insn
, REG_EQUIV
, x
) == NULL_RTX
)
2250 note
= set_unique_reg_note (insn
, REG_EQUIV
, x
);
2251 gcc_assert (note
!= NULL_RTX
);
2252 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2254 fprintf (ira_dump_file
,
2255 " Adding equiv note to insn %u for reg %d ",
2256 INSN_UID (insn
), to_regno
);
2257 dump_value_slim (ira_dump_file
, x
, 1);
2258 fprintf (ira_dump_file
, "\n");
2262 ira_reg_equiv
[to_regno
].init_insns
2263 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
2264 ira_reg_equiv
[to_regno
].init_insns
);
2265 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2266 fprintf (ira_dump_file
,
2267 " Adding equiv init move insn %u to reg %d\n",
2268 INSN_UID (insn
), to_regno
);
2271 /* Fix values of array REG_EQUIV_INIT after live range splitting done
2274 fix_reg_equiv_init (void)
2276 int max_regno
= max_reg_num ();
2277 int i
, new_regno
, max
;
2278 rtx x
, prev
, next
, insn
, set
;
2280 if (max_regno_before_ira
< max_regno
)
2282 max
= vec_safe_length (reg_equivs
);
2284 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; i
++)
2285 for (prev
= NULL_RTX
, x
= reg_equiv_init (i
);
2291 set
= single_set (insn
);
2292 ira_assert (set
!= NULL_RTX
2293 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))));
2294 if (REG_P (SET_DEST (set
))
2295 && ((int) REGNO (SET_DEST (set
)) == i
2296 || (int) ORIGINAL_REGNO (SET_DEST (set
)) == i
))
2297 new_regno
= REGNO (SET_DEST (set
));
2298 else if (REG_P (SET_SRC (set
))
2299 && ((int) REGNO (SET_SRC (set
)) == i
2300 || (int) ORIGINAL_REGNO (SET_SRC (set
)) == i
))
2301 new_regno
= REGNO (SET_SRC (set
));
2308 /* Remove the wrong list element. */
2309 if (prev
== NULL_RTX
)
2310 reg_equiv_init (i
) = next
;
2312 XEXP (prev
, 1) = next
;
2313 XEXP (x
, 1) = reg_equiv_init (new_regno
);
2314 reg_equiv_init (new_regno
) = x
;
2320 #ifdef ENABLE_IRA_CHECKING
2321 /* Print redundant memory-memory copies. */
2323 print_redundant_copies (void)
2327 ira_copy_t cp
, next_cp
;
2328 ira_allocno_iterator ai
;
2330 FOR_EACH_ALLOCNO (a
, ai
)
2332 if (ALLOCNO_CAP_MEMBER (a
) != NULL
)
2335 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2336 if (hard_regno
>= 0)
2338 for (cp
= ALLOCNO_COPIES (a
); cp
!= NULL
; cp
= next_cp
)
2340 next_cp
= cp
->next_first_allocno_copy
;
2343 next_cp
= cp
->next_second_allocno_copy
;
2344 if (internal_flag_ira_verbose
> 4 && ira_dump_file
!= NULL
2345 && cp
->insn
!= NULL_RTX
2346 && ALLOCNO_HARD_REGNO (cp
->first
) == hard_regno
)
2347 fprintf (ira_dump_file
,
2348 " Redundant move from %d(freq %d):%d\n",
2349 INSN_UID (cp
->insn
), cp
->freq
, hard_regno
);
2355 /* Setup preferred and alternative classes for new pseudo-registers
2356 created by IRA starting with START. */
2358 setup_preferred_alternate_classes_for_new_pseudos (int start
)
2361 int max_regno
= max_reg_num ();
2363 for (i
= start
; i
< max_regno
; i
++)
2365 old_regno
= ORIGINAL_REGNO (regno_reg_rtx
[i
]);
2366 ira_assert (i
!= old_regno
);
2367 setup_reg_classes (i
, reg_preferred_class (old_regno
),
2368 reg_alternate_class (old_regno
),
2369 reg_allocno_class (old_regno
));
2370 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
2371 fprintf (ira_dump_file
,
2372 " New r%d: setting preferred %s, alternative %s\n",
2373 i
, reg_class_names
[reg_preferred_class (old_regno
)],
2374 reg_class_names
[reg_alternate_class (old_regno
)]);
2379 /* The number of entries allocated in teg_info. */
2380 static int allocated_reg_info_size
;
2382 /* Regional allocation can create new pseudo-registers. This function
2383 expands some arrays for pseudo-registers. */
2385 expand_reg_info (void)
2388 int size
= max_reg_num ();
2391 for (i
= allocated_reg_info_size
; i
< size
; i
++)
2392 setup_reg_classes (i
, GENERAL_REGS
, ALL_REGS
, GENERAL_REGS
);
2393 setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size
);
2394 allocated_reg_info_size
= size
;
2397 /* Return TRUE if there is too high register pressure in the function.
2398 It is used to decide when stack slot sharing is worth to do. */
2400 too_high_register_pressure_p (void)
2403 enum reg_class pclass
;
2405 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
2407 pclass
= ira_pressure_classes
[i
];
2408 if (ira_loop_tree_root
->reg_pressure
[pclass
] > 10000)
2416 /* Indicate that hard register number FROM was eliminated and replaced with
2417 an offset from hard register number TO. The status of hard registers live
2418 at the start of a basic block is updated by replacing a use of FROM with
2422 mark_elimination (int from
, int to
)
2430 if (bitmap_bit_p (r
, from
))
2432 bitmap_clear_bit (r
, from
);
2433 bitmap_set_bit (r
, to
);
2437 r
= DF_LIVE_IN (bb
);
2438 if (bitmap_bit_p (r
, from
))
2440 bitmap_clear_bit (r
, from
);
2441 bitmap_set_bit (r
, to
);
2448 /* The length of the following array. */
2449 int ira_reg_equiv_len
;
2451 /* Info about equiv. info for each register. */
2452 struct ira_reg_equiv
*ira_reg_equiv
;
2454 /* Expand ira_reg_equiv if necessary. */
2456 ira_expand_reg_equiv (void)
2458 int old
= ira_reg_equiv_len
;
2460 if (ira_reg_equiv_len
> max_reg_num ())
2462 ira_reg_equiv_len
= max_reg_num () * 3 / 2 + 1;
2464 = (struct ira_reg_equiv
*) xrealloc (ira_reg_equiv
,
2466 * sizeof (struct ira_reg_equiv
));
2467 gcc_assert (old
< ira_reg_equiv_len
);
2468 memset (ira_reg_equiv
+ old
, 0,
2469 sizeof (struct ira_reg_equiv
) * (ira_reg_equiv_len
- old
));
2473 init_reg_equiv (void)
2475 ira_reg_equiv_len
= 0;
2476 ira_reg_equiv
= NULL
;
2477 ira_expand_reg_equiv ();
2481 finish_reg_equiv (void)
2483 free (ira_reg_equiv
);
2490 /* Set when a REG_EQUIV note is found or created. Use to
2491 keep track of what memory accesses might be created later,
2495 /* The list of each instruction which initializes this register. */
2497 /* Loop depth is used to recognize equivalences which appear
2498 to be present within the same loop (or in an inner loop). */
2500 /* Nonzero if this had a preexisting REG_EQUIV note. */
2501 int is_arg_equivalence
;
2502 /* Set when an attempt should be made to replace a register
2503 with the associated src_p entry. */
2507 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
2508 structure for that register. */
2509 static struct equivalence
*reg_equiv
;
2511 /* Used for communication between the following two functions: contains
2512 a MEM that we wish to ensure remains unchanged. */
2513 static rtx equiv_mem
;
2515 /* Set nonzero if EQUIV_MEM is modified. */
2516 static int equiv_mem_modified
;
2518 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
2519 Called via note_stores. */
2521 validate_equiv_mem_from_store (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
,
2522 void *data ATTRIBUTE_UNUSED
)
2525 && reg_overlap_mentioned_p (dest
, equiv_mem
))
2527 && anti_dependence (equiv_mem
, dest
)))
2528 equiv_mem_modified
= 1;
2531 /* Verify that no store between START and the death of REG invalidates
2532 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
2533 by storing into an overlapping memory location, or with a non-const
2536 Return 1 if MEMREF remains valid. */
2538 validate_equiv_mem (rtx start
, rtx reg
, rtx memref
)
2544 equiv_mem_modified
= 0;
2546 /* If the memory reference has side effects or is volatile, it isn't a
2547 valid equivalence. */
2548 if (side_effects_p (memref
))
2551 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
2553 if (! INSN_P (insn
))
2556 if (find_reg_note (insn
, REG_DEAD
, reg
))
2559 /* This used to ignore readonly memory and const/pure calls. The problem
2560 is the equivalent form may reference a pseudo which gets assigned a
2561 call clobbered hard reg. When we later replace REG with its
2562 equivalent form, the value in the call-clobbered reg has been
2563 changed and all hell breaks loose. */
2567 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
2569 /* If a register mentioned in MEMREF is modified via an
2570 auto-increment, we lose the equivalence. Do the same if one
2571 dies; although we could extend the life, it doesn't seem worth
2574 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2575 if ((REG_NOTE_KIND (note
) == REG_INC
2576 || REG_NOTE_KIND (note
) == REG_DEAD
)
2577 && REG_P (XEXP (note
, 0))
2578 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
2585 /* Returns zero if X is known to be invariant. */
2587 equiv_init_varies_p (rtx x
)
2589 RTX_CODE code
= GET_CODE (x
);
2596 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
2605 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
2608 if (MEM_VOLATILE_P (x
))
2617 fmt
= GET_RTX_FORMAT (code
);
2618 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2621 if (equiv_init_varies_p (XEXP (x
, i
)))
2624 else if (fmt
[i
] == 'E')
2627 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2628 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
2635 /* Returns nonzero if X (used to initialize register REGNO) is movable.
2636 X is only movable if the registers it uses have equivalent initializations
2637 which appear to be within the same loop (or in an inner loop) and movable
2638 or if they are not candidates for local_alloc and don't vary. */
2640 equiv_init_movable_p (rtx x
, int regno
)
2644 enum rtx_code code
= GET_CODE (x
);
2649 return equiv_init_movable_p (SET_SRC (x
), regno
);
2664 return ((reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
2665 && reg_equiv
[REGNO (x
)].replace
)
2666 || (REG_BASIC_BLOCK (REGNO (x
)) < NUM_FIXED_BLOCKS
2667 && ! rtx_varies_p (x
, 0)));
2669 case UNSPEC_VOLATILE
:
2673 if (MEM_VOLATILE_P (x
))
2682 fmt
= GET_RTX_FORMAT (code
);
2683 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2687 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
2691 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2692 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
2700 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is
2703 contains_replace_regs (rtx x
)
2707 enum rtx_code code
= GET_CODE (x
);
2721 return reg_equiv
[REGNO (x
)].replace
;
2727 fmt
= GET_RTX_FORMAT (code
);
2728 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2732 if (contains_replace_regs (XEXP (x
, i
)))
2736 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2737 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
2745 /* TRUE if X references a memory location that would be affected by a store
2748 memref_referenced_p (rtx memref
, rtx x
)
2752 enum rtx_code code
= GET_CODE (x
);
2767 return (reg_equiv
[REGNO (x
)].replacement
2768 && memref_referenced_p (memref
,
2769 reg_equiv
[REGNO (x
)].replacement
));
2772 if (true_dependence (memref
, VOIDmode
, x
))
2777 /* If we are setting a MEM, it doesn't count (its address does), but any
2778 other SET_DEST that has a MEM in it is referencing the MEM. */
2779 if (MEM_P (SET_DEST (x
)))
2781 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
2784 else if (memref_referenced_p (memref
, SET_DEST (x
)))
2787 return memref_referenced_p (memref
, SET_SRC (x
));
2793 fmt
= GET_RTX_FORMAT (code
);
2794 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2798 if (memref_referenced_p (memref
, XEXP (x
, i
)))
2802 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2803 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
2811 /* TRUE if some insn in the range (START, END] references a memory location
2812 that would be affected by a store to MEMREF. */
2814 memref_used_between_p (rtx memref
, rtx start
, rtx end
)
2818 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
2819 insn
= NEXT_INSN (insn
))
2821 if (!NONDEBUG_INSN_P (insn
))
2824 if (memref_referenced_p (memref
, PATTERN (insn
)))
2827 /* Nonconst functions may access memory. */
2828 if (CALL_P (insn
) && (! RTL_CONST_CALL_P (insn
)))
2835 /* Mark REG as having no known equivalence.
2836 Some instructions might have been processed before and furnished
2837 with REG_EQUIV notes for this register; these notes will have to be
2839 STORE is the piece of RTL that does the non-constant / conflicting
2840 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
2841 but needs to be there because this function is called from note_stores. */
2843 no_equiv (rtx reg
, const_rtx store ATTRIBUTE_UNUSED
,
2844 void *data ATTRIBUTE_UNUSED
)
2851 regno
= REGNO (reg
);
2852 list
= reg_equiv
[regno
].init_insns
;
2853 if (list
== const0_rtx
)
2855 reg_equiv
[regno
].init_insns
= const0_rtx
;
2856 reg_equiv
[regno
].replacement
= NULL_RTX
;
2857 /* This doesn't matter for equivalences made for argument registers, we
2858 should keep their initialization insns. */
2859 if (reg_equiv
[regno
].is_arg_equivalence
)
2861 ira_reg_equiv
[regno
].defined_p
= false;
2862 ira_reg_equiv
[regno
].init_insns
= NULL_RTX
;
2863 for (; list
; list
= XEXP (list
, 1))
2865 rtx insn
= XEXP (list
, 0);
2866 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
2870 /* Check whether the SUBREG is a paradoxical subreg and set the result
2874 set_paradoxical_subreg (rtx
*subreg
, void *pdx_subregs
)
2878 if ((*subreg
) == NULL_RTX
)
2880 if (GET_CODE (*subreg
) != SUBREG
)
2882 reg
= SUBREG_REG (*subreg
);
2886 if (paradoxical_subreg_p (*subreg
))
2887 ((bool *)pdx_subregs
)[REGNO (reg
)] = true;
2892 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the
2893 equivalent replacement. */
2896 adjust_cleared_regs (rtx loc
, const_rtx old_rtx ATTRIBUTE_UNUSED
, void *data
)
2900 bitmap cleared_regs
= (bitmap
) data
;
2901 if (bitmap_bit_p (cleared_regs
, REGNO (loc
)))
2902 return simplify_replace_fn_rtx (*reg_equiv
[REGNO (loc
)].src_p
,
2903 NULL_RTX
, adjust_cleared_regs
, data
);
2908 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
2909 static int recorded_label_ref
;
2911 /* Find registers that are equivalent to a single value throughout the
2912 compilation (either because they can be referenced in memory or are
2913 set once from a single constant). Lower their priority for a
2916 If such a register is only referenced once, try substituting its
2917 value into the using insn. If it succeeds, we can eliminate the
2918 register completely.
2920 Initialize init_insns in ira_reg_equiv array.
2922 Return non-zero if jump label rebuilding should be done. */
2924 update_equiv_regs (void)
2929 bitmap cleared_regs
;
2932 /* We need to keep track of whether or not we recorded a LABEL_REF so
2933 that we know if the jump optimizer needs to be rerun. */
2934 recorded_label_ref
= 0;
2936 /* Use pdx_subregs to show whether a reg is used in a paradoxical
2938 pdx_subregs
= XCNEWVEC (bool, max_regno
);
2940 reg_equiv
= XCNEWVEC (struct equivalence
, max_regno
);
2943 init_alias_analysis ();
2945 /* Scan insns and set pdx_subregs[regno] if the reg is used in a
2946 paradoxical subreg. Don't set such reg sequivalent to a mem,
2947 because lra will not substitute such equiv memory in order to
2948 prevent access beyond allocated memory for paradoxical memory subreg. */
2950 FOR_BB_INSNS (bb
, insn
)
2951 if (NONDEBUG_INSN_P (insn
))
2952 for_each_rtx (&insn
, set_paradoxical_subreg
, (void *) pdx_subregs
);
2954 /* Scan the insns and find which registers have equivalences. Do this
2955 in a separate scan of the insns because (due to -fcse-follow-jumps)
2956 a register can be set below its use. */
2959 loop_depth
= bb_loop_depth (bb
);
2961 for (insn
= BB_HEAD (bb
);
2962 insn
!= NEXT_INSN (BB_END (bb
));
2963 insn
= NEXT_INSN (insn
))
2970 if (! INSN_P (insn
))
2973 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2974 if (REG_NOTE_KIND (note
) == REG_INC
)
2975 no_equiv (XEXP (note
, 0), note
, NULL
);
2977 set
= single_set (insn
);
2979 /* If this insn contains more (or less) than a single SET,
2980 only mark all destinations as having no known equivalence. */
2983 note_stores (PATTERN (insn
), no_equiv
, NULL
);
2986 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
2990 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
2992 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
2994 note_stores (part
, no_equiv
, NULL
);
2998 dest
= SET_DEST (set
);
2999 src
= SET_SRC (set
);
3001 /* See if this is setting up the equivalence between an argument
3002 register and its stack slot. */
3003 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3006 gcc_assert (REG_P (dest
));
3007 regno
= REGNO (dest
);
3009 /* Note that we don't want to clear init_insns in
3010 ira_reg_equiv even if there are multiple sets of this
3012 reg_equiv
[regno
].is_arg_equivalence
= 1;
3014 /* The insn result can have equivalence memory although
3015 the equivalence is not set up by the insn. We add
3016 this insn to init insns as it is a flag for now that
3017 regno has an equivalence. We will remove the insn
3018 from init insn list later. */
3019 if (rtx_equal_p (src
, XEXP (note
, 0)) || MEM_P (XEXP (note
, 0)))
3020 ira_reg_equiv
[regno
].init_insns
3021 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3022 ira_reg_equiv
[regno
].init_insns
);
3024 /* Continue normally in case this is a candidate for
3031 /* We only handle the case of a pseudo register being set
3032 once, or always to the same value. */
3033 /* ??? The mn10200 port breaks if we add equivalences for
3034 values that need an ADDRESS_REGS register and set them equivalent
3035 to a MEM of a pseudo. The actual problem is in the over-conservative
3036 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
3037 calculate_needs, but we traditionally work around this problem
3038 here by rejecting equivalences when the destination is in a register
3039 that's likely spilled. This is fragile, of course, since the
3040 preferred class of a pseudo depends on all instructions that set
3044 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
3045 || reg_equiv
[regno
].init_insns
== const0_rtx
3046 || (targetm
.class_likely_spilled_p (reg_preferred_class (regno
))
3047 && MEM_P (src
) && ! reg_equiv
[regno
].is_arg_equivalence
))
3049 /* This might be setting a SUBREG of a pseudo, a pseudo that is
3050 also set somewhere else to a constant. */
3051 note_stores (set
, no_equiv
, NULL
);
3055 /* Don't set reg (if pdx_subregs[regno] == true) equivalent to a mem. */
3056 if (MEM_P (src
) && pdx_subregs
[regno
])
3058 note_stores (set
, no_equiv
, NULL
);
3062 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
3064 /* cse sometimes generates function invariants, but doesn't put a
3065 REG_EQUAL note on the insn. Since this note would be redundant,
3066 there's no point creating it earlier than here. */
3067 if (! note
&& ! rtx_varies_p (src
, 0))
3068 note
= set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
3070 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
3071 since it represents a function call */
3072 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
3075 if (DF_REG_DEF_COUNT (regno
) != 1
3077 || rtx_varies_p (XEXP (note
, 0), 0)
3078 || (reg_equiv
[regno
].replacement
3079 && ! rtx_equal_p (XEXP (note
, 0),
3080 reg_equiv
[regno
].replacement
))))
3082 no_equiv (dest
, set
, NULL
);
3085 /* Record this insn as initializing this register. */
3086 reg_equiv
[regno
].init_insns
3087 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
3089 /* If this register is known to be equal to a constant, record that
3090 it is always equivalent to the constant. */
3091 if (DF_REG_DEF_COUNT (regno
) == 1
3092 && note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
3094 rtx note_value
= XEXP (note
, 0);
3095 remove_note (insn
, note
);
3096 set_unique_reg_note (insn
, REG_EQUIV
, note_value
);
3099 /* If this insn introduces a "constant" register, decrease the priority
3100 of that register. Record this insn if the register is only used once
3101 more and the equivalence value is the same as our source.
3103 The latter condition is checked for two reasons: First, it is an
3104 indication that it may be more efficient to actually emit the insn
3105 as written (if no registers are available, reload will substitute
3106 the equivalence). Secondly, it avoids problems with any registers
3107 dying in this insn whose death notes would be missed.
3109 If we don't have a REG_EQUIV note, see if this insn is loading
3110 a register used only in one basic block from a MEM. If so, and the
3111 MEM remains unchanged for the life of the register, add a REG_EQUIV
3114 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3116 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3117 && MEM_P (SET_SRC (set
))
3118 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
3119 note
= set_unique_reg_note (insn
, REG_EQUIV
, copy_rtx (SET_SRC (set
)));
3123 int regno
= REGNO (dest
);
3124 rtx x
= XEXP (note
, 0);
3126 /* If we haven't done so, record for reload that this is an
3127 equivalencing insn. */
3128 if (!reg_equiv
[regno
].is_arg_equivalence
)
3129 ira_reg_equiv
[regno
].init_insns
3130 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3131 ira_reg_equiv
[regno
].init_insns
);
3133 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
3134 We might end up substituting the LABEL_REF for uses of the
3135 pseudo here or later. That kind of transformation may turn an
3136 indirect jump into a direct jump, in which case we must rerun the
3137 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
3138 if (GET_CODE (x
) == LABEL_REF
3139 || (GET_CODE (x
) == CONST
3140 && GET_CODE (XEXP (x
, 0)) == PLUS
3141 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == LABEL_REF
)))
3142 recorded_label_ref
= 1;
3144 reg_equiv
[regno
].replacement
= x
;
3145 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
3146 reg_equiv
[regno
].loop_depth
= loop_depth
;
3148 /* Don't mess with things live during setjmp. */
3149 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
3151 /* Note that the statement below does not affect the priority
3153 REG_LIVE_LENGTH (regno
) *= 2;
3155 /* If the register is referenced exactly twice, meaning it is
3156 set once and used once, indicate that the reference may be
3157 replaced by the equivalence we computed above. Do this
3158 even if the register is only used in one block so that
3159 dependencies can be handled where the last register is
3160 used in a different block (i.e. HIGH / LO_SUM sequences)
3161 and to reduce the number of registers alive across
3164 if (REG_N_REFS (regno
) == 2
3165 && (rtx_equal_p (x
, src
)
3166 || ! equiv_init_varies_p (src
))
3167 && NONJUMP_INSN_P (insn
)
3168 && equiv_init_movable_p (PATTERN (insn
), regno
))
3169 reg_equiv
[regno
].replace
= 1;
3178 /* A second pass, to gather additional equivalences with memory. This needs
3179 to be done after we know which registers we are going to replace. */
3181 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3186 if (! INSN_P (insn
))
3189 set
= single_set (insn
);
3193 dest
= SET_DEST (set
);
3194 src
= SET_SRC (set
);
3196 /* If this sets a MEM to the contents of a REG that is only used
3197 in a single basic block, see if the register is always equivalent
3198 to that memory location and if moving the store from INSN to the
3199 insn that set REG is safe. If so, put a REG_EQUIV note on the
3202 Don't add a REG_EQUIV note if the insn already has one. The existing
3203 REG_EQUIV is likely more useful than the one we are adding.
3205 If one of the regs in the address has reg_equiv[REGNO].replace set,
3206 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
3207 optimization may move the set of this register immediately before
3208 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
3209 the mention in the REG_EQUIV note would be to an uninitialized
3212 if (MEM_P (dest
) && REG_P (src
)
3213 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
3214 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3215 && DF_REG_DEF_COUNT (regno
) == 1
3216 && reg_equiv
[regno
].init_insns
!= 0
3217 && reg_equiv
[regno
].init_insns
!= const0_rtx
3218 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
3219 REG_EQUIV
, NULL_RTX
)
3220 && ! contains_replace_regs (XEXP (dest
, 0))
3221 && ! pdx_subregs
[regno
])
3223 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
3224 if (validate_equiv_mem (init_insn
, src
, dest
)
3225 && ! memref_used_between_p (dest
, init_insn
, insn
)
3226 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
3228 && set_unique_reg_note (init_insn
, REG_EQUIV
, copy_rtx (dest
)))
3230 /* This insn makes the equivalence, not the one initializing
3232 ira_reg_equiv
[regno
].init_insns
3233 = gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
);
3234 df_notes_rescan (init_insn
);
3239 cleared_regs
= BITMAP_ALLOC (NULL
);
3240 /* Now scan all regs killed in an insn to see if any of them are
3241 registers only used that once. If so, see if we can replace the
3242 reference with the equivalent form. If we can, delete the
3243 initializing reference and this register will go away. If we
3244 can't replace the reference, and the initializing reference is
3245 within the same loop (or in an inner loop), then move the register
3246 initialization just before the use, so that they are in the same
3248 FOR_EACH_BB_REVERSE (bb
)
3250 loop_depth
= bb_loop_depth (bb
);
3251 for (insn
= BB_END (bb
);
3252 insn
!= PREV_INSN (BB_HEAD (bb
));
3253 insn
= PREV_INSN (insn
))
3257 if (! INSN_P (insn
))
3260 /* Don't substitute into a non-local goto, this confuses CFG. */
3262 && find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
3265 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
3267 if (REG_NOTE_KIND (link
) == REG_DEAD
3268 /* Make sure this insn still refers to the register. */
3269 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
3271 int regno
= REGNO (XEXP (link
, 0));
3274 if (! reg_equiv
[regno
].replace
3275 || reg_equiv
[regno
].loop_depth
< loop_depth
3276 /* There is no sense to move insns if we did
3277 register pressure-sensitive scheduling was
3278 done because it will not improve allocation
3279 but worsen insn schedule with a big
3281 || (flag_sched_pressure
&& flag_schedule_insns
))
3284 /* reg_equiv[REGNO].replace gets set only when
3285 REG_N_REFS[REGNO] is 2, i.e. the register is set
3286 once and used once. (If it were only set, but
3287 not used, flow would have deleted the setting
3288 insns.) Hence there can only be one insn in
3289 reg_equiv[REGNO].init_insns. */
3290 gcc_assert (reg_equiv
[regno
].init_insns
3291 && !XEXP (reg_equiv
[regno
].init_insns
, 1));
3292 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
3294 /* We may not move instructions that can throw, since
3295 that changes basic block boundaries and we are not
3296 prepared to adjust the CFG to match. */
3297 if (can_throw_internal (equiv_insn
))
3300 if (asm_noperands (PATTERN (equiv_insn
)) < 0
3301 && validate_replace_rtx (regno_reg_rtx
[regno
],
3302 *(reg_equiv
[regno
].src_p
), insn
))
3308 /* Find the last note. */
3309 for (last_link
= link
; XEXP (last_link
, 1);
3310 last_link
= XEXP (last_link
, 1))
3313 /* Append the REG_DEAD notes from equiv_insn. */
3314 equiv_link
= REG_NOTES (equiv_insn
);
3318 equiv_link
= XEXP (equiv_link
, 1);
3319 if (REG_NOTE_KIND (note
) == REG_DEAD
)
3321 remove_note (equiv_insn
, note
);
3322 XEXP (last_link
, 1) = note
;
3323 XEXP (note
, 1) = NULL_RTX
;
3328 remove_death (regno
, insn
);
3329 SET_REG_N_REFS (regno
, 0);
3330 REG_FREQ (regno
) = 0;
3331 delete_insn (equiv_insn
);
3333 reg_equiv
[regno
].init_insns
3334 = XEXP (reg_equiv
[regno
].init_insns
, 1);
3336 ira_reg_equiv
[regno
].init_insns
= NULL_RTX
;
3337 bitmap_set_bit (cleared_regs
, regno
);
3339 /* Move the initialization of the register to just before
3340 INSN. Update the flow information. */
3341 else if (prev_nondebug_insn (insn
) != equiv_insn
)
3345 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
3346 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
3347 REG_NOTES (equiv_insn
) = 0;
3348 /* Rescan it to process the notes. */
3349 df_insn_rescan (new_insn
);
3351 /* Make sure this insn is recognized before
3352 reload begins, otherwise
3353 eliminate_regs_in_insn will die. */
3354 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
3356 delete_insn (equiv_insn
);
3358 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
3360 REG_BASIC_BLOCK (regno
) = bb
->index
;
3361 REG_N_CALLS_CROSSED (regno
) = 0;
3362 REG_FREQ_CALLS_CROSSED (regno
) = 0;
3363 REG_N_THROWING_CALLS_CROSSED (regno
) = 0;
3364 REG_LIVE_LENGTH (regno
) = 2;
3366 if (insn
== BB_HEAD (bb
))
3367 BB_HEAD (bb
) = PREV_INSN (insn
);
3369 ira_reg_equiv
[regno
].init_insns
3370 = gen_rtx_INSN_LIST (VOIDmode
, new_insn
, NULL_RTX
);
3371 bitmap_set_bit (cleared_regs
, regno
);
3378 if (!bitmap_empty_p (cleared_regs
))
3382 bitmap_and_compl_into (DF_LR_IN (bb
), cleared_regs
);
3383 bitmap_and_compl_into (DF_LR_OUT (bb
), cleared_regs
);
3386 bitmap_and_compl_into (DF_LIVE_IN (bb
), cleared_regs
);
3387 bitmap_and_compl_into (DF_LIVE_OUT (bb
), cleared_regs
);
3390 /* Last pass - adjust debug insns referencing cleared regs. */
3391 if (MAY_HAVE_DEBUG_INSNS
)
3392 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3393 if (DEBUG_INSN_P (insn
))
3395 rtx old_loc
= INSN_VAR_LOCATION_LOC (insn
);
3396 INSN_VAR_LOCATION_LOC (insn
)
3397 = simplify_replace_fn_rtx (old_loc
, NULL_RTX
,
3398 adjust_cleared_regs
,
3399 (void *) cleared_regs
);
3400 if (old_loc
!= INSN_VAR_LOCATION_LOC (insn
))
3401 df_insn_rescan (insn
);
3405 BITMAP_FREE (cleared_regs
);
3410 end_alias_analysis ();
3413 return recorded_label_ref
;
3418 /* Set up fields memory, constant, and invariant from init_insns in
3419 the structures of array ira_reg_equiv. */
3421 setup_reg_equiv (void)
3424 rtx elem
, prev_elem
, next_elem
, insn
, set
, x
;
3426 for (i
= FIRST_PSEUDO_REGISTER
; i
< ira_reg_equiv_len
; i
++)
3427 for (prev_elem
= NULL
, elem
= ira_reg_equiv
[i
].init_insns
;
3429 prev_elem
= elem
, elem
= next_elem
)
3431 next_elem
= XEXP (elem
, 1);
3432 insn
= XEXP (elem
, 0);
3433 set
= single_set (insn
);
3435 /* Init insns can set up equivalence when the reg is a destination or
3436 a source (in this case the destination is memory). */
3437 if (set
!= 0 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))))
3439 if ((x
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL
)
3442 if (REG_P (SET_DEST (set
))
3443 && REGNO (SET_DEST (set
)) == (unsigned int) i
3444 && ! rtx_equal_p (SET_SRC (set
), x
) && MEM_P (x
))
3446 /* This insn reporting the equivalence but
3447 actually not setting it. Remove it from the
3449 if (prev_elem
== NULL
)
3450 ira_reg_equiv
[i
].init_insns
= next_elem
;
3452 XEXP (prev_elem
, 1) = next_elem
;
3456 else if (REG_P (SET_DEST (set
))
3457 && REGNO (SET_DEST (set
)) == (unsigned int) i
)
3461 gcc_assert (REG_P (SET_SRC (set
))
3462 && REGNO (SET_SRC (set
)) == (unsigned int) i
);
3465 if (! function_invariant_p (x
)
3467 /* A function invariant is often CONSTANT_P but may
3468 include a register. We promise to only pass
3469 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
3470 || (CONSTANT_P (x
) && LEGITIMATE_PIC_OPERAND_P (x
)))
3472 /* It can happen that a REG_EQUIV note contains a MEM
3473 that is not a legitimate memory operand. As later
3474 stages of reload assume that all addresses found in
3475 the lra_regno_equiv_* arrays were originally
3476 legitimate, we ignore such REG_EQUIV notes. */
3477 if (memory_operand (x
, VOIDmode
))
3479 ira_reg_equiv
[i
].defined_p
= true;
3480 ira_reg_equiv
[i
].memory
= x
;
3483 else if (function_invariant_p (x
))
3485 enum machine_mode mode
;
3487 mode
= GET_MODE (SET_DEST (set
));
3488 if (GET_CODE (x
) == PLUS
3489 || x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
3490 /* This is PLUS of frame pointer and a constant,
3492 ira_reg_equiv
[i
].invariant
= x
;
3493 else if (targetm
.legitimate_constant_p (mode
, x
))
3494 ira_reg_equiv
[i
].constant
= x
;
3497 ira_reg_equiv
[i
].memory
= force_const_mem (mode
, x
);
3498 if (ira_reg_equiv
[i
].memory
== NULL_RTX
)
3500 ira_reg_equiv
[i
].defined_p
= false;
3501 ira_reg_equiv
[i
].init_insns
= NULL_RTX
;
3505 ira_reg_equiv
[i
].defined_p
= true;
3510 ira_reg_equiv
[i
].defined_p
= false;
3511 ira_reg_equiv
[i
].init_insns
= NULL_RTX
;
3518 /* Print chain C to FILE. */
3520 print_insn_chain (FILE *file
, struct insn_chain
*c
)
3522 fprintf (file
, "insn=%d, ", INSN_UID (c
->insn
));
3523 bitmap_print (file
, &c
->live_throughout
, "live_throughout: ", ", ");
3524 bitmap_print (file
, &c
->dead_or_set
, "dead_or_set: ", "\n");
3528 /* Print all reload_insn_chains to FILE. */
3530 print_insn_chains (FILE *file
)
3532 struct insn_chain
*c
;
3533 for (c
= reload_insn_chain
; c
; c
= c
->next
)
3534 print_insn_chain (file
, c
);
3537 /* Return true if pseudo REGNO should be added to set live_throughout
3538 or dead_or_set of the insn chains for reload consideration. */
3540 pseudo_for_reload_consideration_p (int regno
)
3542 /* Consider spilled pseudos too for IRA because they still have a
3543 chance to get hard-registers in the reload when IRA is used. */
3544 return (reg_renumber
[regno
] >= 0 || ira_conflicts_p
);
3547 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using
3548 REG to the number of nregs, and INIT_VALUE to get the
3549 initialization. ALLOCNUM need not be the regno of REG. */
3551 init_live_subregs (bool init_value
, sbitmap
*live_subregs
,
3552 bitmap live_subregs_used
, int allocnum
, rtx reg
)
3554 unsigned int regno
= REGNO (SUBREG_REG (reg
));
3555 int size
= GET_MODE_SIZE (GET_MODE (regno_reg_rtx
[regno
]));
3557 gcc_assert (size
> 0);
3559 /* Been there, done that. */
3560 if (bitmap_bit_p (live_subregs_used
, allocnum
))
3563 /* Create a new one. */
3564 if (live_subregs
[allocnum
] == NULL
)
3565 live_subregs
[allocnum
] = sbitmap_alloc (size
);
3567 /* If the entire reg was live before blasting into subregs, we need
3568 to init all of the subregs to ones else init to 0. */
3570 bitmap_ones (live_subregs
[allocnum
]);
3572 bitmap_clear (live_subregs
[allocnum
]);
3574 bitmap_set_bit (live_subregs_used
, allocnum
);
3577 /* Walk the insns of the current function and build reload_insn_chain,
3578 and record register life information. */
3580 build_insn_chain (void)
3583 struct insn_chain
**p
= &reload_insn_chain
;
3585 struct insn_chain
*c
= NULL
;
3586 struct insn_chain
*next
= NULL
;
3587 bitmap live_relevant_regs
= BITMAP_ALLOC (NULL
);
3588 bitmap elim_regset
= BITMAP_ALLOC (NULL
);
3589 /* live_subregs is a vector used to keep accurate information about
3590 which hardregs are live in multiword pseudos. live_subregs and
3591 live_subregs_used are indexed by pseudo number. The live_subreg
3592 entry for a particular pseudo is only used if the corresponding
3593 element is non zero in live_subregs_used. The sbitmap size of
3594 live_subreg[allocno] is number of bytes that the pseudo can
3596 sbitmap
*live_subregs
= XCNEWVEC (sbitmap
, max_regno
);
3597 bitmap live_subregs_used
= BITMAP_ALLOC (NULL
);
3599 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3600 if (TEST_HARD_REG_BIT (eliminable_regset
, i
))
3601 bitmap_set_bit (elim_regset
, i
);
3602 FOR_EACH_BB_REVERSE (bb
)
3607 CLEAR_REG_SET (live_relevant_regs
);
3608 bitmap_clear (live_subregs_used
);
3610 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
), 0, i
, bi
)
3612 if (i
>= FIRST_PSEUDO_REGISTER
)
3614 bitmap_set_bit (live_relevant_regs
, i
);
3617 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
),
3618 FIRST_PSEUDO_REGISTER
, i
, bi
)
3620 if (pseudo_for_reload_consideration_p (i
))
3621 bitmap_set_bit (live_relevant_regs
, i
);
3624 FOR_BB_INSNS_REVERSE (bb
, insn
)
3626 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
3628 unsigned int uid
= INSN_UID (insn
);
3632 c
= new_insn_chain ();
3639 c
->block
= bb
->index
;
3641 if (NONDEBUG_INSN_P (insn
))
3642 for (def_rec
= DF_INSN_UID_DEFS (uid
); *def_rec
; def_rec
++)
3644 df_ref def
= *def_rec
;
3645 unsigned int regno
= DF_REF_REGNO (def
);
3647 /* Ignore may clobbers because these are generated
3648 from calls. However, every other kind of def is
3649 added to dead_or_set. */
3650 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
3652 if (regno
< FIRST_PSEUDO_REGISTER
)
3654 if (!fixed_regs
[regno
])
3655 bitmap_set_bit (&c
->dead_or_set
, regno
);
3657 else if (pseudo_for_reload_consideration_p (regno
))
3658 bitmap_set_bit (&c
->dead_or_set
, regno
);
3661 if ((regno
< FIRST_PSEUDO_REGISTER
3662 || reg_renumber
[regno
] >= 0
3664 && (!DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
)))
3666 rtx reg
= DF_REF_REG (def
);
3668 /* We can model subregs, but not if they are
3669 wrapped in ZERO_EXTRACTS. */
3670 if (GET_CODE (reg
) == SUBREG
3671 && !DF_REF_FLAGS_IS_SET (def
, DF_REF_ZERO_EXTRACT
))
3673 unsigned int start
= SUBREG_BYTE (reg
);
3674 unsigned int last
= start
3675 + GET_MODE_SIZE (GET_MODE (reg
));
3678 (bitmap_bit_p (live_relevant_regs
, regno
),
3679 live_subregs
, live_subregs_used
, regno
, reg
);
3681 if (!DF_REF_FLAGS_IS_SET
3682 (def
, DF_REF_STRICT_LOW_PART
))
3684 /* Expand the range to cover entire words.
3685 Bytes added here are "don't care". */
3687 = start
/ UNITS_PER_WORD
* UNITS_PER_WORD
;
3688 last
= ((last
+ UNITS_PER_WORD
- 1)
3689 / UNITS_PER_WORD
* UNITS_PER_WORD
);
3692 /* Ignore the paradoxical bits. */
3693 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
3694 last
= SBITMAP_SIZE (live_subregs
[regno
]);
3696 while (start
< last
)
3698 bitmap_clear_bit (live_subregs
[regno
], start
);
3702 if (bitmap_empty_p (live_subregs
[regno
]))
3704 bitmap_clear_bit (live_subregs_used
, regno
);
3705 bitmap_clear_bit (live_relevant_regs
, regno
);
3708 /* Set live_relevant_regs here because
3709 that bit has to be true to get us to
3710 look at the live_subregs fields. */
3711 bitmap_set_bit (live_relevant_regs
, regno
);
3715 /* DF_REF_PARTIAL is generated for
3716 subregs, STRICT_LOW_PART, and
3717 ZERO_EXTRACT. We handle the subreg
3718 case above so here we have to keep from
3719 modeling the def as a killing def. */
3720 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
))
3722 bitmap_clear_bit (live_subregs_used
, regno
);
3723 bitmap_clear_bit (live_relevant_regs
, regno
);
3729 bitmap_and_compl_into (live_relevant_regs
, elim_regset
);
3730 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
3732 if (NONDEBUG_INSN_P (insn
))
3733 for (use_rec
= DF_INSN_UID_USES (uid
); *use_rec
; use_rec
++)
3735 df_ref use
= *use_rec
;
3736 unsigned int regno
= DF_REF_REGNO (use
);
3737 rtx reg
= DF_REF_REG (use
);
3739 /* DF_REF_READ_WRITE on a use means that this use
3740 is fabricated from a def that is a partial set
3741 to a multiword reg. Here, we only model the
3742 subreg case that is not wrapped in ZERO_EXTRACT
3743 precisely so we do not need to look at the
3745 if (DF_REF_FLAGS_IS_SET (use
, DF_REF_READ_WRITE
)
3746 && !DF_REF_FLAGS_IS_SET (use
, DF_REF_ZERO_EXTRACT
)
3747 && DF_REF_FLAGS_IS_SET (use
, DF_REF_SUBREG
))
3750 /* Add the last use of each var to dead_or_set. */
3751 if (!bitmap_bit_p (live_relevant_regs
, regno
))
3753 if (regno
< FIRST_PSEUDO_REGISTER
)
3755 if (!fixed_regs
[regno
])
3756 bitmap_set_bit (&c
->dead_or_set
, regno
);
3758 else if (pseudo_for_reload_consideration_p (regno
))
3759 bitmap_set_bit (&c
->dead_or_set
, regno
);
3762 if (regno
< FIRST_PSEUDO_REGISTER
3763 || pseudo_for_reload_consideration_p (regno
))
3765 if (GET_CODE (reg
) == SUBREG
3766 && !DF_REF_FLAGS_IS_SET (use
,
3768 | DF_REF_ZERO_EXTRACT
))
3770 unsigned int start
= SUBREG_BYTE (reg
);
3771 unsigned int last
= start
3772 + GET_MODE_SIZE (GET_MODE (reg
));
3775 (bitmap_bit_p (live_relevant_regs
, regno
),
3776 live_subregs
, live_subregs_used
, regno
, reg
);
3778 /* Ignore the paradoxical bits. */
3779 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
3780 last
= SBITMAP_SIZE (live_subregs
[regno
]);
3782 while (start
< last
)
3784 bitmap_set_bit (live_subregs
[regno
], start
);
3789 /* Resetting the live_subregs_used is
3790 effectively saying do not use the subregs
3791 because we are reading the whole
3793 bitmap_clear_bit (live_subregs_used
, regno
);
3794 bitmap_set_bit (live_relevant_regs
, regno
);
3800 /* FIXME!! The following code is a disaster. Reload needs to see the
3801 labels and jump tables that are just hanging out in between
3802 the basic blocks. See pr33676. */
3803 insn
= BB_HEAD (bb
);
3805 /* Skip over the barriers and cruft. */
3806 while (insn
&& (BARRIER_P (insn
) || NOTE_P (insn
)
3807 || BLOCK_FOR_INSN (insn
) == bb
))
3808 insn
= PREV_INSN (insn
);
3810 /* While we add anything except barriers and notes, the focus is
3811 to get the labels and jump tables into the
3812 reload_insn_chain. */
3815 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
3817 if (BLOCK_FOR_INSN (insn
))
3820 c
= new_insn_chain ();
3826 /* The block makes no sense here, but it is what the old
3828 c
->block
= bb
->index
;
3830 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
3832 insn
= PREV_INSN (insn
);
3836 reload_insn_chain
= c
;
3839 for (i
= 0; i
< (unsigned int) max_regno
; i
++)
3840 if (live_subregs
[i
] != NULL
)
3841 sbitmap_free (live_subregs
[i
]);
3842 free (live_subregs
);
3843 BITMAP_FREE (live_subregs_used
);
3844 BITMAP_FREE (live_relevant_regs
);
3845 BITMAP_FREE (elim_regset
);
3848 print_insn_chains (dump_file
);
3851 /* Examine the rtx found in *LOC, which is read or written to as determined
3852 by TYPE. Return false if we find a reason why an insn containing this
3853 rtx should not be moved (such as accesses to non-constant memory), true
3856 rtx_moveable_p (rtx
*loc
, enum op_type type
)
3860 enum rtx_code code
= GET_CODE (x
);
3863 code
= GET_CODE (x
);
3873 return type
== OP_IN
;
3879 if (x
== frame_pointer_rtx
)
3881 if (HARD_REGISTER_P (x
))
3887 if (type
== OP_IN
&& MEM_READONLY_P (x
))
3888 return rtx_moveable_p (&XEXP (x
, 0), OP_IN
);
3892 return (rtx_moveable_p (&SET_SRC (x
), OP_IN
)
3893 && rtx_moveable_p (&SET_DEST (x
), OP_OUT
));
3895 case STRICT_LOW_PART
:
3896 return rtx_moveable_p (&XEXP (x
, 0), OP_OUT
);
3900 return (rtx_moveable_p (&XEXP (x
, 0), type
)
3901 && rtx_moveable_p (&XEXP (x
, 1), OP_IN
)
3902 && rtx_moveable_p (&XEXP (x
, 2), OP_IN
));
3905 return rtx_moveable_p (&SET_DEST (x
), OP_OUT
);
3911 fmt
= GET_RTX_FORMAT (code
);
3912 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3916 if (!rtx_moveable_p (&XEXP (x
, i
), type
))
3919 else if (fmt
[i
] == 'E')
3920 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3922 if (!rtx_moveable_p (&XVECEXP (x
, i
, j
), type
))
3929 /* A wrapper around dominated_by_p, which uses the information in UID_LUID
3930 to give dominance relationships between two insns I1 and I2. */
3932 insn_dominated_by_p (rtx i1
, rtx i2
, int *uid_luid
)
3934 basic_block bb1
= BLOCK_FOR_INSN (i1
);
3935 basic_block bb2
= BLOCK_FOR_INSN (i2
);
3938 return uid_luid
[INSN_UID (i2
)] < uid_luid
[INSN_UID (i1
)];
3939 return dominated_by_p (CDI_DOMINATORS
, bb1
, bb2
);
3942 /* Record the range of register numbers added by find_moveable_pseudos. */
3943 int first_moveable_pseudo
, last_moveable_pseudo
;
3945 /* These two vectors hold data for every register added by
3946 find_movable_pseudos, with index 0 holding data for the
3947 first_moveable_pseudo. */
3948 /* The original home register. */
3949 static vec
<rtx
> pseudo_replaced_reg
;
3951 /* Look for instances where we have an instruction that is known to increase
3952 register pressure, and whose result is not used immediately. If it is
3953 possible to move the instruction downwards to just before its first use,
3954 split its lifetime into two ranges. We create a new pseudo to compute the
3955 value, and emit a move instruction just before the first use. If, after
3956 register allocation, the new pseudo remains unallocated, the function
3957 move_unallocated_pseudos then deletes the move instruction and places
3958 the computation just before the first use.
3960 Such a move is safe and profitable if all the input registers remain live
3961 and unchanged between the original computation and its first use. In such
3962 a situation, the computation is known to increase register pressure, and
3963 moving it is known to at least not worsen it.
3965 We restrict moves to only those cases where a register remains unallocated,
3966 in order to avoid interfering too much with the instruction schedule. As
3967 an exception, we may move insns which only modify their input register
3968 (typically induction variables), as this increases the freedom for our
3969 intended transformation, and does not limit the second instruction
3973 find_moveable_pseudos (void)
3976 int max_regs
= max_reg_num ();
3977 int max_uid
= get_max_uid ();
3979 int *uid_luid
= XNEWVEC (int, max_uid
);
3980 rtx
*closest_uses
= XNEWVEC (rtx
, max_regs
);
3981 /* A set of registers which are live but not modified throughout a block. */
3982 bitmap_head
*bb_transp_live
= XNEWVEC (bitmap_head
, last_basic_block
);
3983 /* A set of registers which only exist in a given basic block. */
3984 bitmap_head
*bb_local
= XNEWVEC (bitmap_head
, last_basic_block
);
3985 /* A set of registers which are set once, in an instruction that can be
3986 moved freely downwards, but are otherwise transparent to a block. */
3987 bitmap_head
*bb_moveable_reg_sets
= XNEWVEC (bitmap_head
, last_basic_block
);
3988 bitmap_head live
, used
, set
, interesting
, unusable_as_input
;
3990 bitmap_initialize (&interesting
, 0);
3992 first_moveable_pseudo
= max_regs
;
3993 pseudo_replaced_reg
.release ();
3994 pseudo_replaced_reg
.safe_grow_cleared (max_regs
);
3997 calculate_dominance_info (CDI_DOMINATORS
);
4000 bitmap_initialize (&live
, 0);
4001 bitmap_initialize (&used
, 0);
4002 bitmap_initialize (&set
, 0);
4003 bitmap_initialize (&unusable_as_input
, 0);
4007 bitmap transp
= bb_transp_live
+ bb
->index
;
4008 bitmap moveable
= bb_moveable_reg_sets
+ bb
->index
;
4009 bitmap local
= bb_local
+ bb
->index
;
4011 bitmap_initialize (local
, 0);
4012 bitmap_initialize (transp
, 0);
4013 bitmap_initialize (moveable
, 0);
4014 bitmap_copy (&live
, df_get_live_out (bb
));
4015 bitmap_and_into (&live
, df_get_live_in (bb
));
4016 bitmap_copy (transp
, &live
);
4017 bitmap_clear (moveable
);
4018 bitmap_clear (&live
);
4019 bitmap_clear (&used
);
4020 bitmap_clear (&set
);
4021 FOR_BB_INSNS (bb
, insn
)
4022 if (NONDEBUG_INSN_P (insn
))
4024 df_ref
*u_rec
, *d_rec
;
4026 uid_luid
[INSN_UID (insn
)] = i
++;
4028 u_rec
= DF_INSN_USES (insn
);
4029 d_rec
= DF_INSN_DEFS (insn
);
4030 if (d_rec
[0] != NULL
&& d_rec
[1] == NULL
4031 && u_rec
[0] != NULL
&& u_rec
[1] == NULL
4032 && DF_REF_REGNO (*u_rec
) == DF_REF_REGNO (*d_rec
)
4033 && !bitmap_bit_p (&set
, DF_REF_REGNO (*u_rec
))
4034 && rtx_moveable_p (&PATTERN (insn
), OP_IN
))
4036 unsigned regno
= DF_REF_REGNO (*u_rec
);
4037 bitmap_set_bit (moveable
, regno
);
4038 bitmap_set_bit (&set
, regno
);
4039 bitmap_set_bit (&used
, regno
);
4040 bitmap_clear_bit (transp
, regno
);
4045 unsigned regno
= DF_REF_REGNO (*u_rec
);
4046 bitmap_set_bit (&used
, regno
);
4047 if (bitmap_clear_bit (moveable
, regno
))
4048 bitmap_clear_bit (transp
, regno
);
4054 unsigned regno
= DF_REF_REGNO (*d_rec
);
4055 bitmap_set_bit (&set
, regno
);
4056 bitmap_clear_bit (transp
, regno
);
4057 bitmap_clear_bit (moveable
, regno
);
4063 bitmap_clear (&live
);
4064 bitmap_clear (&used
);
4065 bitmap_clear (&set
);
4069 bitmap local
= bb_local
+ bb
->index
;
4072 FOR_BB_INSNS (bb
, insn
)
4073 if (NONDEBUG_INSN_P (insn
))
4075 rtx def_insn
, closest_use
, note
;
4076 df_ref
*def_rec
, def
, use
;
4078 bool all_dominated
, all_local
;
4079 enum machine_mode mode
;
4081 def_rec
= DF_INSN_DEFS (insn
);
4082 /* There must be exactly one def in this insn. */
4084 if (!def
|| def_rec
[1] || !single_set (insn
))
4086 /* This must be the only definition of the reg. We also limit
4087 which modes we deal with so that we can assume we can generate
4088 move instructions. */
4089 regno
= DF_REF_REGNO (def
);
4090 mode
= GET_MODE (DF_REF_REG (def
));
4091 if (DF_REG_DEF_COUNT (regno
) != 1
4092 || !DF_REF_INSN_INFO (def
)
4093 || HARD_REGISTER_NUM_P (regno
)
4094 || DF_REG_EQ_USE_COUNT (regno
) > 0
4095 || (!INTEGRAL_MODE_P (mode
) && !FLOAT_MODE_P (mode
)))
4097 def_insn
= DF_REF_INSN (def
);
4099 for (note
= REG_NOTES (def_insn
); note
; note
= XEXP (note
, 1))
4100 if (REG_NOTE_KIND (note
) == REG_EQUIV
&& MEM_P (XEXP (note
, 0)))
4106 fprintf (dump_file
, "Ignoring reg %d, has equiv memory\n",
4108 bitmap_set_bit (&unusable_as_input
, regno
);
4112 use
= DF_REG_USE_CHAIN (regno
);
4113 all_dominated
= true;
4115 closest_use
= NULL_RTX
;
4116 for (; use
; use
= DF_REF_NEXT_REG (use
))
4119 if (!DF_REF_INSN_INFO (use
))
4121 all_dominated
= false;
4125 insn
= DF_REF_INSN (use
);
4126 if (DEBUG_INSN_P (insn
))
4128 if (BLOCK_FOR_INSN (insn
) != BLOCK_FOR_INSN (def_insn
))
4130 if (!insn_dominated_by_p (insn
, def_insn
, uid_luid
))
4131 all_dominated
= false;
4132 if (closest_use
!= insn
&& closest_use
!= const0_rtx
)
4134 if (closest_use
== NULL_RTX
)
4136 else if (insn_dominated_by_p (closest_use
, insn
, uid_luid
))
4138 else if (!insn_dominated_by_p (insn
, closest_use
, uid_luid
))
4139 closest_use
= const0_rtx
;
4145 fprintf (dump_file
, "Reg %d not all uses dominated by set\n",
4150 bitmap_set_bit (local
, regno
);
4151 if (closest_use
== const0_rtx
|| closest_use
== NULL
4152 || next_nonnote_nondebug_insn (def_insn
) == closest_use
)
4155 fprintf (dump_file
, "Reg %d uninteresting%s\n", regno
,
4156 closest_use
== const0_rtx
|| closest_use
== NULL
4157 ? " (no unique first use)" : "");
4161 if (reg_referenced_p (cc0_rtx
, PATTERN (closest_use
)))
4164 fprintf (dump_file
, "Reg %d: closest user uses cc0\n",
4169 bitmap_set_bit (&interesting
, regno
);
4170 closest_uses
[regno
] = closest_use
;
4172 if (dump_file
&& (all_local
|| all_dominated
))
4174 fprintf (dump_file
, "Reg %u:", regno
);
4176 fprintf (dump_file
, " local to bb %d", bb
->index
);
4178 fprintf (dump_file
, " def dominates all uses");
4179 if (closest_use
!= const0_rtx
)
4180 fprintf (dump_file
, " has unique first use");
4181 fputs ("\n", dump_file
);
4186 EXECUTE_IF_SET_IN_BITMAP (&interesting
, 0, i
, bi
)
4188 df_ref def
= DF_REG_DEF_CHAIN (i
);
4189 rtx def_insn
= DF_REF_INSN (def
);
4190 basic_block def_block
= BLOCK_FOR_INSN (def_insn
);
4191 bitmap def_bb_local
= bb_local
+ def_block
->index
;
4192 bitmap def_bb_moveable
= bb_moveable_reg_sets
+ def_block
->index
;
4193 bitmap def_bb_transp
= bb_transp_live
+ def_block
->index
;
4194 bool local_to_bb_p
= bitmap_bit_p (def_bb_local
, i
);
4195 rtx use_insn
= closest_uses
[i
];
4196 df_ref
*def_insn_use_rec
= DF_INSN_USES (def_insn
);
4198 bool all_transp
= true;
4200 if (!REG_P (DF_REF_REG (def
)))
4206 fprintf (dump_file
, "Reg %u not local to one basic block\n",
4210 if (reg_equiv_init (i
) != NULL_RTX
)
4213 fprintf (dump_file
, "Ignoring reg %u with equiv init insn\n",
4217 if (!rtx_moveable_p (&PATTERN (def_insn
), OP_IN
))
4220 fprintf (dump_file
, "Found def insn %d for %d to be not moveable\n",
4221 INSN_UID (def_insn
), i
);
4225 fprintf (dump_file
, "Examining insn %d, def for %d\n",
4226 INSN_UID (def_insn
), i
);
4227 while (*def_insn_use_rec
!= NULL
)
4229 df_ref use
= *def_insn_use_rec
;
4230 unsigned regno
= DF_REF_REGNO (use
);
4231 if (bitmap_bit_p (&unusable_as_input
, regno
))
4235 fprintf (dump_file
, " found unusable input reg %u.\n", regno
);
4238 if (!bitmap_bit_p (def_bb_transp
, regno
))
4240 if (bitmap_bit_p (def_bb_moveable
, regno
)
4241 && !control_flow_insn_p (use_insn
)
4243 && !sets_cc0_p (use_insn
)
4247 if (modified_between_p (DF_REF_REG (use
), def_insn
, use_insn
))
4249 rtx x
= NEXT_INSN (def_insn
);
4250 while (!modified_in_p (DF_REF_REG (use
), x
))
4252 gcc_assert (x
!= use_insn
);
4256 fprintf (dump_file
, " input reg %u modified but insn %d moveable\n",
4257 regno
, INSN_UID (x
));
4258 emit_insn_after (PATTERN (x
), use_insn
);
4259 set_insn_deleted (x
);
4264 fprintf (dump_file
, " input reg %u modified between def and use\n",
4277 if (!dbg_cnt (ira_move
))
4280 fprintf (dump_file
, " all ok%s\n", all_transp
? " and transp" : "");
4284 rtx def_reg
= DF_REF_REG (def
);
4285 rtx newreg
= ira_create_new_reg (def_reg
);
4286 if (validate_change (def_insn
, DF_REF_LOC (def
), newreg
, 0))
4288 unsigned nregno
= REGNO (newreg
);
4289 emit_insn_before (gen_move_insn (def_reg
, newreg
), use_insn
);
4291 pseudo_replaced_reg
[nregno
] = def_reg
;
4298 bitmap_clear (bb_local
+ bb
->index
);
4299 bitmap_clear (bb_transp_live
+ bb
->index
);
4300 bitmap_clear (bb_moveable_reg_sets
+ bb
->index
);
4302 bitmap_clear (&interesting
);
4303 bitmap_clear (&unusable_as_input
);
4305 free (closest_uses
);
4307 free (bb_transp_live
);
4308 free (bb_moveable_reg_sets
);
4310 last_moveable_pseudo
= max_reg_num ();
4312 fix_reg_equiv_init ();
4314 regstat_free_n_sets_and_refs ();
4316 regstat_init_n_sets_and_refs ();
4317 regstat_compute_ri ();
4318 free_dominance_info (CDI_DOMINATORS
);
4321 /* Perform the second half of the transformation started in
4322 find_moveable_pseudos. We look for instances where the newly introduced
4323 pseudo remains unallocated, and remove it by moving the definition to
4324 just before its use, replacing the move instruction generated by
4325 find_moveable_pseudos. */
4327 move_unallocated_pseudos (void)
4330 for (i
= first_moveable_pseudo
; i
< last_moveable_pseudo
; i
++)
4331 if (reg_renumber
[i
] < 0)
4333 int idx
= i
- first_moveable_pseudo
;
4334 rtx other_reg
= pseudo_replaced_reg
[idx
];
4335 rtx def_insn
= DF_REF_INSN (DF_REG_DEF_CHAIN (i
));
4336 /* The use must follow all definitions of OTHER_REG, so we can
4337 insert the new definition immediately after any of them. */
4338 df_ref other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
));
4339 rtx move_insn
= DF_REF_INSN (other_def
);
4340 rtx newinsn
= emit_insn_after (PATTERN (def_insn
), move_insn
);
4345 fprintf (dump_file
, "moving def of %d (insn %d now) ",
4346 REGNO (other_reg
), INSN_UID (def_insn
));
4348 delete_insn (move_insn
);
4349 while ((other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
))))
4350 delete_insn (DF_REF_INSN (other_def
));
4351 delete_insn (def_insn
);
4353 set
= single_set (newinsn
);
4354 success
= validate_change (newinsn
, &SET_DEST (set
), other_reg
, 0);
4355 gcc_assert (success
);
4357 fprintf (dump_file
, " %d) rather than keep unallocated replacement %d\n",
4358 INSN_UID (newinsn
), i
);
4359 SET_REG_N_REFS (i
, 0);
4363 /* If the backend knows where to allocate pseudos for hard
4364 register initial values, register these allocations now. */
4366 allocate_initial_values (void)
4368 if (targetm
.allocate_initial_value
)
4373 for (i
= 0; HARD_REGISTER_NUM_P (i
); i
++)
4375 if (! initial_value_entry (i
, &hreg
, &preg
))
4378 x
= targetm
.allocate_initial_value (hreg
);
4379 regno
= REGNO (preg
);
4380 if (x
&& REG_N_SETS (regno
) <= 1)
4383 reg_equiv_memory_loc (regno
) = x
;
4389 gcc_assert (REG_P (x
));
4390 new_regno
= REGNO (x
);
4391 reg_renumber
[regno
] = new_regno
;
4392 /* Poke the regno right into regno_reg_rtx so that even
4393 fixed regs are accepted. */
4394 SET_REGNO (preg
, new_regno
);
4395 /* Update global register liveness information. */
4398 if (REGNO_REG_SET_P (df_get_live_in (bb
), regno
))
4399 SET_REGNO_REG_SET (df_get_live_in (bb
), new_regno
);
4400 if (REGNO_REG_SET_P (df_get_live_out (bb
), regno
))
4401 SET_REGNO_REG_SET (df_get_live_out (bb
), new_regno
);
4407 gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER
,
4413 /* True when we use LRA instead of reload pass for the current
4417 /* True if we have allocno conflicts. It is false for non-optimized
4418 mode or when the conflict table is too big. */
4419 bool ira_conflicts_p
;
4421 /* Saved between IRA and reload. */
4422 static int saved_flag_ira_share_spill_slots
;
4424 /* This is the main entry of IRA. */
4429 int ira_max_point_before_emit
;
4431 bool saved_flag_caller_saves
= flag_caller_saves
;
4432 enum ira_region saved_flag_ira_region
= flag_ira_region
;
4434 ira_conflicts_p
= optimize
> 0;
4436 ira_use_lra_p
= targetm
.lra_p ();
4437 /* If there are too many pseudos and/or basic blocks (e.g. 10K
4438 pseudos and 10K blocks or 100K pseudos and 1K blocks), we will
4439 use simplified and faster algorithms in LRA. */
4441 = (ira_use_lra_p
&& max_reg_num () >= (1 << 26) / last_basic_block
);
4444 /* It permits to skip live range splitting in LRA. */
4445 flag_caller_saves
= false;
4446 /* There is no sense to do regional allocation when we use
4448 flag_ira_region
= IRA_REGION_ONE
;
4449 ira_conflicts_p
= false;
4452 #ifndef IRA_NO_OBSTACK
4453 gcc_obstack_init (&ira_obstack
);
4455 bitmap_obstack_initialize (&ira_bitmap_obstack
);
4457 if (flag_caller_saves
)
4458 init_caller_save ();
4460 if (flag_ira_verbose
< 10)
4462 internal_flag_ira_verbose
= flag_ira_verbose
;
4467 internal_flag_ira_verbose
= flag_ira_verbose
- 10;
4468 ira_dump_file
= stderr
;
4471 setup_prohibited_mode_move_regs ();
4473 df_note_add_problem ();
4475 /* DF_LIVE can't be used in the register allocator, too many other
4476 parts of the compiler depend on using the "classic" liveness
4477 interpretation of the DF_LR problem. See PR38711.
4478 Remove the problem, so that we don't spend time updating it in
4479 any of the df_analyze() calls during IRA/LRA. */
4481 df_remove_problem (df_live
);
4482 gcc_checking_assert (df_live
== NULL
);
4484 #ifdef ENABLE_CHECKING
4485 df
->changeable_flags
|= DF_VERIFY_SCHEDULED
;
4488 df_clear_flags (DF_NO_INSN_RESCAN
);
4489 regstat_init_n_sets_and_refs ();
4490 regstat_compute_ri ();
4492 /* If we are not optimizing, then this is the only place before
4493 register allocation where dataflow is done. And that is needed
4494 to generate these warnings. */
4496 generate_setjmp_warnings ();
4498 /* Determine if the current function is a leaf before running IRA
4499 since this can impact optimizations done by the prologue and
4500 epilogue thus changing register elimination offsets. */
4501 crtl
->is_leaf
= leaf_function_p ();
4503 if (resize_reg_info () && flag_ira_loop_pressure
)
4504 ira_set_pseudo_classes (true, ira_dump_file
);
4507 rebuild_p
= update_equiv_regs ();
4509 setup_reg_equiv_init ();
4511 if (optimize
&& rebuild_p
)
4513 timevar_push (TV_JUMP
);
4514 rebuild_jump_labels (get_insns ());
4515 if (purge_all_dead_edges ())
4516 delete_unreachable_blocks ();
4517 timevar_pop (TV_JUMP
);
4520 allocated_reg_info_size
= max_reg_num ();
4522 if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
4525 /* It is not worth to do such improvement when we use a simple
4526 allocation because of -O0 usage or because the function is too
4528 if (ira_conflicts_p
)
4529 find_moveable_pseudos ();
4531 max_regno_before_ira
= max_reg_num ();
4532 ira_setup_eliminable_regset (true);
4534 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
4535 ira_load_cost
= ira_store_cost
= ira_shuffle_cost
= 0;
4536 ira_move_loops_num
= ira_additional_jumps_num
= 0;
4538 ira_assert (current_loops
== NULL
);
4539 if (flag_ira_region
== IRA_REGION_ALL
|| flag_ira_region
== IRA_REGION_MIXED
)
4540 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
| LOOPS_HAVE_RECORDED_EXITS
);
4542 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
4543 fprintf (ira_dump_file
, "Building IRA IR\n");
4544 loops_p
= ira_build ();
4546 ira_assert (ira_conflicts_p
|| !loops_p
);
4548 saved_flag_ira_share_spill_slots
= flag_ira_share_spill_slots
;
4549 if (too_high_register_pressure_p () || cfun
->calls_setjmp
)
4550 /* It is just wasting compiler's time to pack spilled pseudos into
4551 stack slots in this case -- prohibit it. We also do this if
4552 there is setjmp call because a variable not modified between
4553 setjmp and longjmp the compiler is required to preserve its
4554 value and sharing slots does not guarantee it. */
4555 flag_ira_share_spill_slots
= FALSE
;
4559 ira_max_point_before_emit
= ira_max_point
;
4561 ira_initiate_emit_data ();
4565 max_regno
= max_reg_num ();
4566 if (ira_conflicts_p
)
4570 if (! ira_use_lra_p
)
4571 ira_initiate_assign ();
4580 ira_allocno_iterator ai
;
4582 FOR_EACH_ALLOCNO (a
, ai
)
4583 ALLOCNO_REGNO (a
) = REGNO (ALLOCNO_EMIT_DATA (a
)->reg
);
4587 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
4588 fprintf (ira_dump_file
, "Flattening IR\n");
4589 ira_flattening (max_regno_before_ira
, ira_max_point_before_emit
);
4591 /* New insns were generated: add notes and recalculate live
4595 /* ??? Rebuild the loop tree, but why? Does the loop tree
4596 change if new insns were generated? Can that be handled
4597 by updating the loop tree incrementally? */
4598 loop_optimizer_finalize ();
4599 free_dominance_info (CDI_DOMINATORS
);
4600 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
4601 | LOOPS_HAVE_RECORDED_EXITS
);
4603 if (! ira_use_lra_p
)
4605 setup_allocno_assignment_flags ();
4606 ira_initiate_assign ();
4607 ira_reassign_conflict_allocnos (max_regno
);
4612 ira_finish_emit_data ();
4614 setup_reg_renumber ();
4616 calculate_allocation_cost ();
4618 #ifdef ENABLE_IRA_CHECKING
4619 if (ira_conflicts_p
)
4620 check_allocation ();
4623 if (max_regno
!= max_regno_before_ira
)
4625 regstat_free_n_sets_and_refs ();
4627 regstat_init_n_sets_and_refs ();
4628 regstat_compute_ri ();
4631 overall_cost_before
= ira_overall_cost
;
4632 if (! ira_conflicts_p
)
4636 fix_reg_equiv_init ();
4638 #ifdef ENABLE_IRA_CHECKING
4639 print_redundant_copies ();
4642 ira_spilled_reg_stack_slots_num
= 0;
4643 ira_spilled_reg_stack_slots
4644 = ((struct ira_spilled_reg_stack_slot
*)
4645 ira_allocate (max_regno
4646 * sizeof (struct ira_spilled_reg_stack_slot
)));
4647 memset (ira_spilled_reg_stack_slots
, 0,
4648 max_regno
* sizeof (struct ira_spilled_reg_stack_slot
));
4650 allocate_initial_values ();
4652 /* See comment for find_moveable_pseudos call. */
4653 if (ira_conflicts_p
)
4654 move_unallocated_pseudos ();
4656 /* Restore original values. */
4659 flag_caller_saves
= saved_flag_caller_saves
;
4660 flag_ira_region
= saved_flag_ira_region
;
4670 if (flag_ira_verbose
< 10)
4671 ira_dump_file
= dump_file
;
4673 timevar_push (TV_RELOAD
);
4676 if (current_loops
!= NULL
)
4678 loop_optimizer_finalize ();
4679 free_dominance_info (CDI_DOMINATORS
);
4682 bb
->loop_father
= NULL
;
4683 current_loops
= NULL
;
4685 if (ira_conflicts_p
)
4686 ira_free (ira_spilled_reg_stack_slots
);
4690 lra (ira_dump_file
);
4691 /* ???!!! Move it before lra () when we use ira_reg_equiv in
4693 vec_free (reg_equivs
);
4699 df_set_flags (DF_NO_INSN_RESCAN
);
4700 build_insn_chain ();
4702 need_dce
= reload (get_insns (), ira_conflicts_p
);
4706 timevar_pop (TV_RELOAD
);
4708 timevar_push (TV_IRA
);
4710 if (ira_conflicts_p
&& ! ira_use_lra_p
)
4712 ira_free (ira_spilled_reg_stack_slots
);
4713 ira_finish_assign ();
4716 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
4717 && overall_cost_before
!= ira_overall_cost
)
4718 fprintf (ira_dump_file
, "+++Overall after reload %d\n", ira_overall_cost
);
4720 flag_ira_share_spill_slots
= saved_flag_ira_share_spill_slots
;
4722 if (! ira_use_lra_p
)
4725 if (current_loops
!= NULL
)
4727 loop_optimizer_finalize ();
4728 free_dominance_info (CDI_DOMINATORS
);
4731 bb
->loop_father
= NULL
;
4732 current_loops
= NULL
;
4735 regstat_free_n_sets_and_refs ();
4739 cleanup_cfg (CLEANUP_EXPENSIVE
);
4741 finish_reg_equiv ();
4743 bitmap_obstack_release (&ira_bitmap_obstack
);
4744 #ifndef IRA_NO_OBSTACK
4745 obstack_free (&ira_obstack
, NULL
);
4748 /* The code after the reload has changed so much that at this point
4749 we might as well just rescan everything. Note that
4750 df_rescan_all_insns is not going to help here because it does not
4751 touch the artificial uses and defs. */
4752 df_finish_pass (true);
4753 df_scan_alloc (NULL
);
4758 df_live_add_problem ();
4759 df_live_set_all_dirty ();
4765 if (need_dce
&& optimize
)
4768 timevar_pop (TV_IRA
);
4771 /* Run the integrated register allocator. */
4773 rest_of_handle_ira (void)
4781 const pass_data pass_data_ira
=
4783 RTL_PASS
, /* type */
4785 OPTGROUP_NONE
, /* optinfo_flags */
4786 false, /* has_gate */
4787 true, /* has_execute */
4789 0, /* properties_required */
4790 0, /* properties_provided */
4791 0, /* properties_destroyed */
4792 0, /* todo_flags_start */
4793 TODO_do_not_ggc_collect
, /* todo_flags_finish */
4796 class pass_ira
: public rtl_opt_pass
4799 pass_ira (gcc::context
*ctxt
)
4800 : rtl_opt_pass (pass_data_ira
, ctxt
)
4803 /* opt_pass methods: */
4804 unsigned int execute () { return rest_of_handle_ira (); }
4806 }; // class pass_ira
4811 make_pass_ira (gcc::context
*ctxt
)
4813 return new pass_ira (ctxt
);
4817 rest_of_handle_reload (void)
4825 const pass_data pass_data_reload
=
4827 RTL_PASS
, /* type */
4828 "reload", /* name */
4829 OPTGROUP_NONE
, /* optinfo_flags */
4830 false, /* has_gate */
4831 true, /* has_execute */
4832 TV_RELOAD
, /* tv_id */
4833 0, /* properties_required */
4834 0, /* properties_provided */
4835 0, /* properties_destroyed */
4836 0, /* todo_flags_start */
4837 0, /* todo_flags_finish */
4840 class pass_reload
: public rtl_opt_pass
4843 pass_reload (gcc::context
*ctxt
)
4844 : rtl_opt_pass (pass_data_reload
, ctxt
)
4847 /* opt_pass methods: */
4848 unsigned int execute () { return rest_of_handle_reload (); }
4850 }; // class pass_reload
4855 make_pass_reload (gcc::context
*ctxt
)
4857 return new pass_reload (ctxt
);