1 /* Integrated Register Allocator (IRA) entry point.
2 Copyright (C) 2006-2021 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* The integrated register allocator (IRA) is a
22 regional register allocator performing graph coloring on a top-down
23 traversal of nested regions. Graph coloring in a region is based
24 on Chaitin-Briggs algorithm. It is called integrated because
25 register coalescing, register live range splitting, and choosing a
26 better hard register are done on-the-fly during coloring. Register
27 coalescing and choosing a cheaper hard register is done by hard
28 register preferencing during hard register assigning. The live
29 range splitting is a byproduct of the regional register allocation.
31 Major IRA notions are:
33 o *Region* is a part of CFG where graph coloring based on
34 Chaitin-Briggs algorithm is done. IRA can work on any set of
35 nested CFG regions forming a tree. Currently the regions are
36 the entire function for the root region and natural loops for
37 the other regions. Therefore data structure representing a
38 region is called loop_tree_node.
40 o *Allocno class* is a register class used for allocation of
41 given allocno. It means that only hard register of given
42 register class can be assigned to given allocno. In reality,
43 even smaller subset of (*profitable*) hard registers can be
44 assigned. In rare cases, the subset can be even smaller
45 because our modification of Chaitin-Briggs algorithm requires
46 that sets of hard registers can be assigned to allocnos forms a
47 forest, i.e. the sets can be ordered in a way where any
48 previous set is not intersected with given set or is a superset
51 o *Pressure class* is a register class belonging to a set of
52 register classes containing all of the hard-registers available
53 for register allocation. The set of all pressure classes for a
54 target is defined in the corresponding machine-description file
55 according some criteria. Register pressure is calculated only
56 for pressure classes and it affects some IRA decisions as
57 forming allocation regions.
59 o *Allocno* represents the live range of a pseudo-register in a
60 region. Besides the obvious attributes like the corresponding
61 pseudo-register number, allocno class, conflicting allocnos and
62 conflicting hard-registers, there are a few allocno attributes
63 which are important for understanding the allocation algorithm:
65 - *Live ranges*. This is a list of ranges of *program points*
66 where the allocno lives. Program points represent places
67 where a pseudo can be born or become dead (there are
68 approximately two times more program points than the insns)
69 and they are represented by integers starting with 0. The
70 live ranges are used to find conflicts between allocnos.
71 They also play very important role for the transformation of
72 the IRA internal representation of several regions into a one
73 region representation. The later is used during the reload
74 pass work because each allocno represents all of the
75 corresponding pseudo-registers.
77 - *Hard-register costs*. This is a vector of size equal to the
78 number of available hard-registers of the allocno class. The
79 cost of a callee-clobbered hard-register for an allocno is
80 increased by the cost of save/restore code around the calls
81 through the given allocno's life. If the allocno is a move
82 instruction operand and another operand is a hard-register of
83 the allocno class, the cost of the hard-register is decreased
86 When an allocno is assigned, the hard-register with minimal
87 full cost is used. Initially, a hard-register's full cost is
88 the corresponding value from the hard-register's cost vector.
89 If the allocno is connected by a *copy* (see below) to
90 another allocno which has just received a hard-register, the
91 cost of the hard-register is decreased. Before choosing a
92 hard-register for an allocno, the allocno's current costs of
93 the hard-registers are modified by the conflict hard-register
94 costs of all of the conflicting allocnos which are not
97 - *Conflict hard-register costs*. This is a vector of the same
98 size as the hard-register costs vector. To permit an
99 unassigned allocno to get a better hard-register, IRA uses
100 this vector to calculate the final full cost of the
101 available hard-registers. Conflict hard-register costs of an
102 unassigned allocno are also changed with a change of the
103 hard-register cost of the allocno when a copy involving the
104 allocno is processed as described above. This is done to
105 show other unassigned allocnos that a given allocno prefers
106 some hard-registers in order to remove the move instruction
107 corresponding to the copy.
109 o *Cap*. If a pseudo-register does not live in a region but
110 lives in a nested region, IRA creates a special allocno called
111 a cap in the outer region. A region cap is also created for a
114 o *Copy*. Allocnos can be connected by copies. Copies are used
115 to modify hard-register costs for allocnos during coloring.
116 Such modifications reflects a preference to use the same
117 hard-register for the allocnos connected by copies. Usually
118 copies are created for move insns (in this case it results in
119 register coalescing). But IRA also creates copies for operands
120 of an insn which should be assigned to the same hard-register
121 due to constraints in the machine description (it usually
122 results in removing a move generated in reload to satisfy
123 the constraints) and copies referring to the allocno which is
124 the output operand of an instruction and the allocno which is
125 an input operand dying in the instruction (creation of such
126 copies results in less register shuffling). IRA *does not*
127 create copies between the same register allocnos from different
128 regions because we use another technique for propagating
129 hard-register preference on the borders of regions.
131 Allocnos (including caps) for the upper region in the region tree
132 *accumulate* information important for coloring from allocnos with
133 the same pseudo-register from nested regions. This includes
134 hard-register and memory costs, conflicts with hard-registers,
135 allocno conflicts, allocno copies and more. *Thus, attributes for
136 allocnos in a region have the same values as if the region had no
137 subregions*. It means that attributes for allocnos in the
138 outermost region corresponding to the function have the same values
139 as though the allocation used only one region which is the entire
140 function. It also means that we can look at IRA work as if the
141 first IRA did allocation for all function then it improved the
142 allocation for loops then their subloops and so on.
144 IRA major passes are:
146 o Building IRA internal representation which consists of the
149 * First, IRA builds regions and creates allocnos (file
150 ira-build.c) and initializes most of their attributes.
152 * Then IRA finds an allocno class for each allocno and
153 calculates its initial (non-accumulated) cost of memory and
154 each hard-register of its allocno class (file ira-cost.c).
156 * IRA creates live ranges of each allocno, calculates register
157 pressure for each pressure class in each region, sets up
158 conflict hard registers for each allocno and info about calls
159 the allocno lives through (file ira-lives.c).
161 * IRA removes low register pressure loops from the regions
162 mostly to speed IRA up (file ira-build.c).
164 * IRA propagates accumulated allocno info from lower region
165 allocnos to corresponding upper region allocnos (file
168 * IRA creates all caps (file ira-build.c).
170 * Having live-ranges of allocnos and their classes, IRA creates
171 conflicting allocnos for each allocno. Conflicting allocnos
172 are stored as a bit vector or array of pointers to the
173 conflicting allocnos whatever is more profitable (file
174 ira-conflicts.c). At this point IRA creates allocno copies.
176 o Coloring. Now IRA has all necessary info to start graph coloring
177 process. It is done in each region on top-down traverse of the
178 region tree (file ira-color.c). There are following subpasses:
180 * Finding profitable hard registers of corresponding allocno
181 class for each allocno. For example, only callee-saved hard
182 registers are frequently profitable for allocnos living
183 through colors. If the profitable hard register set of
184 allocno does not form a tree based on subset relation, we use
185 some approximation to form the tree. This approximation is
186 used to figure out trivial colorability of allocnos. The
187 approximation is a pretty rare case.
189 * Putting allocnos onto the coloring stack. IRA uses Briggs
190 optimistic coloring which is a major improvement over
191 Chaitin's coloring. Therefore IRA does not spill allocnos at
192 this point. There is some freedom in the order of putting
193 allocnos on the stack which can affect the final result of
194 the allocation. IRA uses some heuristics to improve the
195 order. The major one is to form *threads* from colorable
196 allocnos and push them on the stack by threads. Thread is a
197 set of non-conflicting colorable allocnos connected by
198 copies. The thread contains allocnos from the colorable
199 bucket or colorable allocnos already pushed onto the coloring
200 stack. Pushing thread allocnos one after another onto the
201 stack increases chances of removing copies when the allocnos
202 get the same hard reg.
204 We also use a modification of Chaitin-Briggs algorithm which
205 works for intersected register classes of allocnos. To
206 figure out trivial colorability of allocnos, the mentioned
207 above tree of hard register sets is used. To get an idea how
208 the algorithm works in i386 example, let us consider an
209 allocno to which any general hard register can be assigned.
210 If the allocno conflicts with eight allocnos to which only
211 EAX register can be assigned, given allocno is still
212 trivially colorable because all conflicting allocnos might be
213 assigned only to EAX and all other general hard registers are
216 To get an idea of the used trivial colorability criterion, it
217 is also useful to read article "Graph-Coloring Register
218 Allocation for Irregular Architectures" by Michael D. Smith
219 and Glen Holloway. Major difference between the article
220 approach and approach used in IRA is that Smith's approach
221 takes register classes only from machine description and IRA
222 calculate register classes from intermediate code too
223 (e.g. an explicit usage of hard registers in RTL code for
224 parameter passing can result in creation of additional
225 register classes which contain or exclude the hard
226 registers). That makes IRA approach useful for improving
227 coloring even for architectures with regular register files
228 and in fact some benchmarking shows the improvement for
229 regular class architectures is even bigger than for irregular
230 ones. Another difference is that Smith's approach chooses
231 intersection of classes of all insn operands in which a given
232 pseudo occurs. IRA can use bigger classes if it is still
233 more profitable than memory usage.
235 * Popping the allocnos from the stack and assigning them hard
236 registers. If IRA cannot assign a hard register to an
237 allocno and the allocno is coalesced, IRA undoes the
238 coalescing and puts the uncoalesced allocnos onto the stack in
239 the hope that some such allocnos will get a hard register
240 separately. If IRA fails to assign hard register or memory
241 is more profitable for it, IRA spills the allocno. IRA
242 assigns the allocno the hard-register with minimal full
243 allocation cost which reflects the cost of usage of the
244 hard-register for the allocno and cost of usage of the
245 hard-register for allocnos conflicting with given allocno.
247 * Chaitin-Briggs coloring assigns as many pseudos as possible
248 to hard registers. After coloring we try to improve
249 allocation with cost point of view. We improve the
250 allocation by spilling some allocnos and assigning the freed
251 hard registers to other allocnos if it decreases the overall
254 * After allocno assigning in the region, IRA modifies the hard
255 register and memory costs for the corresponding allocnos in
256 the subregions to reflect the cost of possible loads, stores,
257 or moves on the border of the region and its subregions.
258 When default regional allocation algorithm is used
259 (-fira-algorithm=mixed), IRA just propagates the assignment
260 for allocnos if the register pressure in the region for the
261 corresponding pressure class is less than number of available
262 hard registers for given pressure class.
264 o Spill/restore code moving. When IRA performs an allocation
265 by traversing regions in top-down order, it does not know what
266 happens below in the region tree. Therefore, sometimes IRA
267 misses opportunities to perform a better allocation. A simple
268 optimization tries to improve allocation in a region having
269 subregions and containing in another region. If the
270 corresponding allocnos in the subregion are spilled, it spills
271 the region allocno if it is profitable. The optimization
272 implements a simple iterative algorithm performing profitable
273 transformations while they are still possible. It is fast in
274 practice, so there is no real need for a better time complexity
277 o Code change. After coloring, two allocnos representing the
278 same pseudo-register outside and inside a region respectively
279 may be assigned to different locations (hard-registers or
280 memory). In this case IRA creates and uses a new
281 pseudo-register inside the region and adds code to move allocno
282 values on the region's borders. This is done during top-down
283 traversal of the regions (file ira-emit.c). In some
284 complicated cases IRA can create a new allocno to move allocno
285 values (e.g. when a swap of values stored in two hard-registers
286 is needed). At this stage, the new allocno is marked as
287 spilled. IRA still creates the pseudo-register and the moves
288 on the region borders even when both allocnos were assigned to
289 the same hard-register. If the reload pass spills a
290 pseudo-register for some reason, the effect will be smaller
291 because another allocno will still be in the hard-register. In
292 most cases, this is better then spilling both allocnos. If
293 reload does not change the allocation for the two
294 pseudo-registers, the trivial move will be removed by
295 post-reload optimizations. IRA does not generate moves for
296 allocnos assigned to the same hard register when the default
297 regional allocation algorithm is used and the register pressure
298 in the region for the corresponding pressure class is less than
299 number of available hard registers for given pressure class.
300 IRA also does some optimizations to remove redundant stores and
301 to reduce code duplication on the region borders.
303 o Flattening internal representation. After changing code, IRA
304 transforms its internal representation for several regions into
305 one region representation (file ira-build.c). This process is
306 called IR flattening. Such process is more complicated than IR
307 rebuilding would be, but is much faster.
309 o After IR flattening, IRA tries to assign hard registers to all
310 spilled allocnos. This is implemented by a simple and fast
311 priority coloring algorithm (see function
312 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
313 created during the code change pass can be assigned to hard
316 o At the end IRA calls the reload pass. The reload pass
317 communicates with IRA through several functions in file
318 ira-color.c to improve its decisions in
320 * sharing stack slots for the spilled pseudos based on IRA info
321 about pseudo-register conflicts.
323 * reassigning hard-registers to all spilled pseudos at the end
324 of each reload iteration.
326 * choosing a better hard-register to spill based on IRA info
327 about pseudo-register live ranges and the register pressure
328 in places where the pseudo-register lives.
330 IRA uses a lot of data representing the target processors. These
331 data are initialized in file ira.c.
333 If function has no loops (or the loops are ignored when
334 -fira-algorithm=CB is used), we have classic Chaitin-Briggs
335 coloring (only instead of separate pass of coalescing, we use hard
336 register preferencing). In such case, IRA works much faster
337 because many things are not made (like IR flattening, the
338 spill/restore optimization, and the code change).
340 Literature is worth to read for better understanding the code:
342 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
343 Graph Coloring Register Allocation.
345 o David Callahan, Brian Koblenz. Register allocation via
346 hierarchical graph coloring.
348 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
349 Coloring Register Allocation: A Study of the Chaitin-Briggs and
350 Callahan-Koblenz Algorithms.
352 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
353 Register Allocation Based on Graph Fusion.
355 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
356 Allocation for Irregular Architectures
358 o Vladimir Makarov. The Integrated Register Allocator for GCC.
360 o Vladimir Makarov. The top-down register allocator for irregular
361 register file architectures.
368 #include "coretypes.h"
374 #include "memmodel.h"
376 #include "insn-config.h"
380 #include "diagnostic-core.h"
382 #include "cfgbuild.h"
383 #include "cfgcleanup.h"
385 #include "tree-pass.h"
392 #include "rtl-iter.h"
393 #include "shrink-wrap.h"
394 #include "print-rtl.h"
396 struct target_ira default_target_ira
;
397 class target_ira_int default_target_ira_int
;
398 #if SWITCHABLE_TARGET
399 struct target_ira
*this_target_ira
= &default_target_ira
;
400 class target_ira_int
*this_target_ira_int
= &default_target_ira_int
;
403 /* A modified value of flag `-fira-verbose' used internally. */
404 int internal_flag_ira_verbose
;
406 /* Dump file of the allocator if it is not NULL. */
409 /* The number of elements in the following array. */
410 int ira_spilled_reg_stack_slots_num
;
412 /* The following array contains info about spilled pseudo-registers
413 stack slots used in current function so far. */
414 class ira_spilled_reg_stack_slot
*ira_spilled_reg_stack_slots
;
416 /* Correspondingly overall cost of the allocation, overall cost before
417 reload, cost of the allocnos assigned to hard-registers, cost of
418 the allocnos assigned to memory, cost of loads, stores and register
419 move insns generated for pseudo-register live range splitting (see
421 int64_t ira_overall_cost
, overall_cost_before
;
422 int64_t ira_reg_cost
, ira_mem_cost
;
423 int64_t ira_load_cost
, ira_store_cost
, ira_shuffle_cost
;
424 int ira_move_loops_num
, ira_additional_jumps_num
;
426 /* All registers that can be eliminated. */
428 HARD_REG_SET eliminable_regset
;
430 /* Value of max_reg_num () before IRA work start. This value helps
431 us to recognize a situation when new pseudos were created during
433 static int max_regno_before_ira
;
435 /* Temporary hard reg set used for a different calculation. */
436 static HARD_REG_SET temp_hard_regset
;
438 #define last_mode_for_init_move_cost \
439 (this_target_ira_int->x_last_mode_for_init_move_cost)
442 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
444 setup_reg_mode_hard_regset (void)
446 int i
, m
, hard_regno
;
448 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
449 for (hard_regno
= 0; hard_regno
< FIRST_PSEUDO_REGISTER
; hard_regno
++)
451 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset
[hard_regno
][m
]);
452 for (i
= hard_regno_nregs (hard_regno
, (machine_mode
) m
) - 1;
454 if (hard_regno
+ i
< FIRST_PSEUDO_REGISTER
)
455 SET_HARD_REG_BIT (ira_reg_mode_hard_regset
[hard_regno
][m
],
461 #define no_unit_alloc_regs \
462 (this_target_ira_int->x_no_unit_alloc_regs)
464 /* The function sets up the three arrays declared above. */
466 setup_class_hard_regs (void)
468 int cl
, i
, hard_regno
, n
;
469 HARD_REG_SET processed_hard_reg_set
;
471 ira_assert (SHRT_MAX
>= FIRST_PSEUDO_REGISTER
);
472 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
474 temp_hard_regset
= reg_class_contents
[cl
] & ~no_unit_alloc_regs
;
475 CLEAR_HARD_REG_SET (processed_hard_reg_set
);
476 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
478 ira_non_ordered_class_hard_regs
[cl
][i
] = -1;
479 ira_class_hard_reg_index
[cl
][i
] = -1;
481 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
483 #ifdef REG_ALLOC_ORDER
484 hard_regno
= reg_alloc_order
[i
];
488 if (TEST_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
))
490 SET_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
);
491 if (! TEST_HARD_REG_BIT (temp_hard_regset
, hard_regno
))
492 ira_class_hard_reg_index
[cl
][hard_regno
] = -1;
495 ira_class_hard_reg_index
[cl
][hard_regno
] = n
;
496 ira_class_hard_regs
[cl
][n
++] = hard_regno
;
499 ira_class_hard_regs_num
[cl
] = n
;
500 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
501 if (TEST_HARD_REG_BIT (temp_hard_regset
, i
))
502 ira_non_ordered_class_hard_regs
[cl
][n
++] = i
;
503 ira_assert (ira_class_hard_regs_num
[cl
] == n
);
507 /* Set up global variables defining info about hard registers for the
508 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
509 that we can use the hard frame pointer for the allocation. */
511 setup_alloc_regs (bool use_hard_frame_p
)
513 #ifdef ADJUST_REG_ALLOC_ORDER
514 ADJUST_REG_ALLOC_ORDER
;
516 no_unit_alloc_regs
= fixed_nonglobal_reg_set
;
517 if (! use_hard_frame_p
)
518 add_to_hard_reg_set (&no_unit_alloc_regs
, Pmode
,
519 HARD_FRAME_POINTER_REGNUM
);
520 setup_class_hard_regs ();
525 #define alloc_reg_class_subclasses \
526 (this_target_ira_int->x_alloc_reg_class_subclasses)
528 /* Initialize the table of subclasses of each reg class. */
530 setup_reg_subclasses (void)
533 HARD_REG_SET temp_hard_regset2
;
535 for (i
= 0; i
< N_REG_CLASSES
; i
++)
536 for (j
= 0; j
< N_REG_CLASSES
; j
++)
537 alloc_reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
539 for (i
= 0; i
< N_REG_CLASSES
; i
++)
541 if (i
== (int) NO_REGS
)
544 temp_hard_regset
= reg_class_contents
[i
] & ~no_unit_alloc_regs
;
545 if (hard_reg_set_empty_p (temp_hard_regset
))
547 for (j
= 0; j
< N_REG_CLASSES
; j
++)
552 temp_hard_regset2
= reg_class_contents
[j
] & ~no_unit_alloc_regs
;
553 if (! hard_reg_set_subset_p (temp_hard_regset
,
556 p
= &alloc_reg_class_subclasses
[j
][0];
557 while (*p
!= LIM_REG_CLASSES
) p
++;
558 *p
= (enum reg_class
) i
;
565 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
567 setup_class_subset_and_memory_move_costs (void)
569 int cl
, cl2
, mode
, cost
;
570 HARD_REG_SET temp_hard_regset2
;
572 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
573 ira_memory_move_cost
[mode
][NO_REGS
][0]
574 = ira_memory_move_cost
[mode
][NO_REGS
][1] = SHRT_MAX
;
575 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
577 if (cl
!= (int) NO_REGS
)
578 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
580 ira_max_memory_move_cost
[mode
][cl
][0]
581 = ira_memory_move_cost
[mode
][cl
][0]
582 = memory_move_cost ((machine_mode
) mode
,
583 (reg_class_t
) cl
, false);
584 ira_max_memory_move_cost
[mode
][cl
][1]
585 = ira_memory_move_cost
[mode
][cl
][1]
586 = memory_move_cost ((machine_mode
) mode
,
587 (reg_class_t
) cl
, true);
588 /* Costs for NO_REGS are used in cost calculation on the
589 1st pass when the preferred register classes are not
590 known yet. In this case we take the best scenario. */
591 if (ira_memory_move_cost
[mode
][NO_REGS
][0]
592 > ira_memory_move_cost
[mode
][cl
][0])
593 ira_max_memory_move_cost
[mode
][NO_REGS
][0]
594 = ira_memory_move_cost
[mode
][NO_REGS
][0]
595 = ira_memory_move_cost
[mode
][cl
][0];
596 if (ira_memory_move_cost
[mode
][NO_REGS
][1]
597 > ira_memory_move_cost
[mode
][cl
][1])
598 ira_max_memory_move_cost
[mode
][NO_REGS
][1]
599 = ira_memory_move_cost
[mode
][NO_REGS
][1]
600 = ira_memory_move_cost
[mode
][cl
][1];
603 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
604 for (cl2
= (int) N_REG_CLASSES
- 1; cl2
>= 0; cl2
--)
606 temp_hard_regset
= reg_class_contents
[cl
] & ~no_unit_alloc_regs
;
607 temp_hard_regset2
= reg_class_contents
[cl2
] & ~no_unit_alloc_regs
;
608 ira_class_subset_p
[cl
][cl2
]
609 = hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
);
610 if (! hard_reg_set_empty_p (temp_hard_regset2
)
611 && hard_reg_set_subset_p (reg_class_contents
[cl2
],
612 reg_class_contents
[cl
]))
613 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
615 cost
= ira_memory_move_cost
[mode
][cl2
][0];
616 if (cost
> ira_max_memory_move_cost
[mode
][cl
][0])
617 ira_max_memory_move_cost
[mode
][cl
][0] = cost
;
618 cost
= ira_memory_move_cost
[mode
][cl2
][1];
619 if (cost
> ira_max_memory_move_cost
[mode
][cl
][1])
620 ira_max_memory_move_cost
[mode
][cl
][1] = cost
;
623 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
624 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
626 ira_memory_move_cost
[mode
][cl
][0]
627 = ira_max_memory_move_cost
[mode
][cl
][0];
628 ira_memory_move_cost
[mode
][cl
][1]
629 = ira_max_memory_move_cost
[mode
][cl
][1];
631 setup_reg_subclasses ();
636 /* Define the following macro if allocation through malloc if
638 #define IRA_NO_OBSTACK
640 #ifndef IRA_NO_OBSTACK
641 /* Obstack used for storing all dynamic data (except bitmaps) of the
643 static struct obstack ira_obstack
;
646 /* Obstack used for storing all bitmaps of the IRA. */
647 static struct bitmap_obstack ira_bitmap_obstack
;
649 /* Allocate memory of size LEN for IRA data. */
651 ira_allocate (size_t len
)
655 #ifndef IRA_NO_OBSTACK
656 res
= obstack_alloc (&ira_obstack
, len
);
663 /* Free memory ADDR allocated for IRA data. */
665 ira_free (void *addr ATTRIBUTE_UNUSED
)
667 #ifndef IRA_NO_OBSTACK
675 /* Allocate and returns bitmap for IRA. */
677 ira_allocate_bitmap (void)
679 return BITMAP_ALLOC (&ira_bitmap_obstack
);
682 /* Free bitmap B allocated for IRA. */
684 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED
)
691 /* Output information about allocation of all allocnos (except for
692 caps) into file F. */
694 ira_print_disposition (FILE *f
)
700 fprintf (f
, "Disposition:");
701 max_regno
= max_reg_num ();
702 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
703 for (a
= ira_regno_allocno_map
[i
];
705 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
710 fprintf (f
, " %4d:r%-4d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
711 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
712 fprintf (f
, "b%-3d", bb
->index
);
714 fprintf (f
, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
715 if (ALLOCNO_HARD_REGNO (a
) >= 0)
716 fprintf (f
, " %3d", ALLOCNO_HARD_REGNO (a
));
723 /* Outputs information about allocation of all allocnos into
726 ira_debug_disposition (void)
728 ira_print_disposition (stderr
);
733 /* Set up ira_stack_reg_pressure_class which is the biggest pressure
734 register class containing stack registers or NO_REGS if there are
735 no stack registers. To find this class, we iterate through all
736 register pressure classes and choose the first register pressure
737 class containing all the stack registers and having the biggest
740 setup_stack_reg_pressure_class (void)
742 ira_stack_reg_pressure_class
= NO_REGS
;
747 HARD_REG_SET temp_hard_regset2
;
749 CLEAR_HARD_REG_SET (temp_hard_regset
);
750 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
751 SET_HARD_REG_BIT (temp_hard_regset
, i
);
753 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
755 cl
= ira_pressure_classes
[i
];
756 temp_hard_regset2
= temp_hard_regset
& reg_class_contents
[cl
];
757 size
= hard_reg_set_size (temp_hard_regset2
);
761 ira_stack_reg_pressure_class
= cl
;
768 /* Find pressure classes which are register classes for which we
769 calculate register pressure in IRA, register pressure sensitive
770 insn scheduling, and register pressure sensitive loop invariant
773 To make register pressure calculation easy, we always use
774 non-intersected register pressure classes. A move of hard
775 registers from one register pressure class is not more expensive
776 than load and store of the hard registers. Most likely an allocno
777 class will be a subset of a register pressure class and in many
778 cases a register pressure class. That makes usage of register
779 pressure classes a good approximation to find a high register
782 setup_pressure_classes (void)
784 int cost
, i
, n
, curr
;
786 enum reg_class pressure_classes
[N_REG_CLASSES
];
788 HARD_REG_SET temp_hard_regset2
;
791 if (targetm
.compute_pressure_classes
)
792 n
= targetm
.compute_pressure_classes (pressure_classes
);
796 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
798 if (ira_class_hard_regs_num
[cl
] == 0)
800 if (ira_class_hard_regs_num
[cl
] != 1
801 /* A register class without subclasses may contain a few
802 hard registers and movement between them is costly
803 (e.g. SPARC FPCC registers). We still should consider it
804 as a candidate for a pressure class. */
805 && alloc_reg_class_subclasses
[cl
][0] < cl
)
807 /* Check that the moves between any hard registers of the
808 current class are not more expensive for a legal mode
809 than load/store of the hard registers of the current
810 class. Such class is a potential candidate to be a
811 register pressure class. */
812 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
815 = (reg_class_contents
[cl
]
816 & ~(no_unit_alloc_regs
817 | ira_prohibited_class_mode_regs
[cl
][m
]));
818 if (hard_reg_set_empty_p (temp_hard_regset
))
820 ira_init_register_move_cost_if_necessary ((machine_mode
) m
);
821 cost
= ira_register_move_cost
[m
][cl
][cl
];
822 if (cost
<= ira_max_memory_move_cost
[m
][cl
][1]
823 || cost
<= ira_max_memory_move_cost
[m
][cl
][0])
826 if (m
>= NUM_MACHINE_MODES
)
831 temp_hard_regset
= reg_class_contents
[cl
] & ~no_unit_alloc_regs
;
832 /* Remove so far added pressure classes which are subset of the
833 current candidate class. Prefer GENERAL_REGS as a pressure
834 register class to another class containing the same
835 allocatable hard registers. We do this because machine
836 dependent cost hooks might give wrong costs for the latter
837 class but always give the right cost for the former class
839 for (i
= 0; i
< n
; i
++)
841 cl2
= pressure_classes
[i
];
842 temp_hard_regset2
= (reg_class_contents
[cl2
]
843 & ~no_unit_alloc_regs
);
844 if (hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
)
845 && (temp_hard_regset
!= temp_hard_regset2
846 || cl2
== (int) GENERAL_REGS
))
848 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
852 if (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
)
853 && (temp_hard_regset2
!= temp_hard_regset
854 || cl
== (int) GENERAL_REGS
))
856 if (temp_hard_regset2
== temp_hard_regset
)
858 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
860 /* If the current candidate is a subset of a so far added
861 pressure class, don't add it to the list of the pressure
864 pressure_classes
[curr
++] = (enum reg_class
) cl
;
868 #ifdef ENABLE_IRA_CHECKING
870 HARD_REG_SET ignore_hard_regs
;
872 /* Check pressure classes correctness: here we check that hard
873 registers from all register pressure classes contains all hard
874 registers available for the allocation. */
875 CLEAR_HARD_REG_SET (temp_hard_regset
);
876 CLEAR_HARD_REG_SET (temp_hard_regset2
);
877 ignore_hard_regs
= no_unit_alloc_regs
;
878 for (cl
= 0; cl
< LIM_REG_CLASSES
; cl
++)
880 /* For some targets (like MIPS with MD_REGS), there are some
881 classes with hard registers available for allocation but
882 not able to hold value of any mode. */
883 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
884 if (contains_reg_of_mode
[cl
][m
])
886 if (m
>= NUM_MACHINE_MODES
)
888 ignore_hard_regs
|= reg_class_contents
[cl
];
891 for (i
= 0; i
< n
; i
++)
892 if ((int) pressure_classes
[i
] == cl
)
894 temp_hard_regset2
|= reg_class_contents
[cl
];
896 temp_hard_regset
|= reg_class_contents
[cl
];
898 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
899 /* Some targets (like SPARC with ICC reg) have allocatable regs
900 for which no reg class is defined. */
901 if (REGNO_REG_CLASS (i
) == NO_REGS
)
902 SET_HARD_REG_BIT (ignore_hard_regs
, i
);
903 temp_hard_regset
&= ~ignore_hard_regs
;
904 temp_hard_regset2
&= ~ignore_hard_regs
;
905 ira_assert (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
));
908 ira_pressure_classes_num
= 0;
909 for (i
= 0; i
< n
; i
++)
911 cl
= (int) pressure_classes
[i
];
912 ira_reg_pressure_class_p
[cl
] = true;
913 ira_pressure_classes
[ira_pressure_classes_num
++] = (enum reg_class
) cl
;
915 setup_stack_reg_pressure_class ();
918 /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class
919 whose register move cost between any registers of the class is the
920 same as for all its subclasses. We use the data to speed up the
921 2nd pass of calculations of allocno costs. */
923 setup_uniform_class_p (void)
927 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
929 ira_uniform_class_p
[cl
] = false;
930 if (ira_class_hard_regs_num
[cl
] == 0)
932 /* We cannot use alloc_reg_class_subclasses here because move
933 cost hooks does not take into account that some registers are
934 unavailable for the subtarget. E.g. for i686, INT_SSE_REGS
935 is element of alloc_reg_class_subclasses for GENERAL_REGS
936 because SSE regs are unavailable. */
937 for (i
= 0; (cl2
= reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
; i
++)
939 if (ira_class_hard_regs_num
[cl2
] == 0)
941 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
942 if (contains_reg_of_mode
[cl
][m
] && contains_reg_of_mode
[cl2
][m
])
944 ira_init_register_move_cost_if_necessary ((machine_mode
) m
);
945 if (ira_register_move_cost
[m
][cl
][cl
]
946 != ira_register_move_cost
[m
][cl2
][cl2
])
949 if (m
< NUM_MACHINE_MODES
)
952 if (cl2
== LIM_REG_CLASSES
)
953 ira_uniform_class_p
[cl
] = true;
957 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
958 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
960 Target may have many subtargets and not all target hard registers can
961 be used for allocation, e.g. x86 port in 32-bit mode cannot use
962 hard registers introduced in x86-64 like r8-r15). Some classes
963 might have the same allocatable hard registers, e.g. INDEX_REGS
964 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
965 calculations efforts we introduce allocno classes which contain
966 unique non-empty sets of allocatable hard-registers.
968 Pseudo class cost calculation in ira-costs.c is very expensive.
969 Therefore we are trying to decrease number of classes involved in
970 such calculation. Register classes used in the cost calculation
971 are called important classes. They are allocno classes and other
972 non-empty classes whose allocatable hard register sets are inside
973 of an allocno class hard register set. From the first sight, it
974 looks like that they are just allocno classes. It is not true. In
975 example of x86-port in 32-bit mode, allocno classes will contain
976 GENERAL_REGS but not LEGACY_REGS (because allocatable hard
977 registers are the same for the both classes). The important
978 classes will contain GENERAL_REGS and LEGACY_REGS. It is done
979 because a machine description insn constraint may refers for
980 LEGACY_REGS and code in ira-costs.c is mostly base on investigation
981 of the insn constraints. */
983 setup_allocno_and_important_classes (void)
987 HARD_REG_SET temp_hard_regset2
;
988 static enum reg_class classes
[LIM_REG_CLASSES
+ 1];
991 /* Collect classes which contain unique sets of allocatable hard
992 registers. Prefer GENERAL_REGS to other classes containing the
993 same set of hard registers. */
994 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
996 temp_hard_regset
= reg_class_contents
[i
] & ~no_unit_alloc_regs
;
997 for (j
= 0; j
< n
; j
++)
1000 temp_hard_regset2
= reg_class_contents
[cl
] & ~no_unit_alloc_regs
;
1001 if (temp_hard_regset
== temp_hard_regset2
)
1004 if (j
>= n
|| targetm
.additional_allocno_class_p (i
))
1005 classes
[n
++] = (enum reg_class
) i
;
1006 else if (i
== GENERAL_REGS
)
1007 /* Prefer general regs. For i386 example, it means that
1008 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
1009 (all of them consists of the same available hard
1011 classes
[j
] = (enum reg_class
) i
;
1013 classes
[n
] = LIM_REG_CLASSES
;
1015 /* Set up classes which can be used for allocnos as classes
1016 containing non-empty unique sets of allocatable hard
1018 ira_allocno_classes_num
= 0;
1019 for (i
= 0; (cl
= classes
[i
]) != LIM_REG_CLASSES
; i
++)
1020 if (ira_class_hard_regs_num
[cl
] > 0)
1021 ira_allocno_classes
[ira_allocno_classes_num
++] = (enum reg_class
) cl
;
1022 ira_important_classes_num
= 0;
1023 /* Add non-allocno classes containing to non-empty set of
1024 allocatable hard regs. */
1025 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1026 if (ira_class_hard_regs_num
[cl
] > 0)
1028 temp_hard_regset
= reg_class_contents
[cl
] & ~no_unit_alloc_regs
;
1030 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1032 temp_hard_regset2
= (reg_class_contents
[ira_allocno_classes
[j
]]
1033 & ~no_unit_alloc_regs
);
1034 if ((enum reg_class
) cl
== ira_allocno_classes
[j
])
1036 else if (hard_reg_set_subset_p (temp_hard_regset
,
1040 if (set_p
&& j
>= ira_allocno_classes_num
)
1041 ira_important_classes
[ira_important_classes_num
++]
1042 = (enum reg_class
) cl
;
1044 /* Now add allocno classes to the important classes. */
1045 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1046 ira_important_classes
[ira_important_classes_num
++]
1047 = ira_allocno_classes
[j
];
1048 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1050 ira_reg_allocno_class_p
[cl
] = false;
1051 ira_reg_pressure_class_p
[cl
] = false;
1053 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1054 ira_reg_allocno_class_p
[ira_allocno_classes
[j
]] = true;
1055 setup_pressure_classes ();
1056 setup_uniform_class_p ();
1059 /* Setup translation in CLASS_TRANSLATE of all classes into a class
1060 given by array CLASSES of length CLASSES_NUM. The function is used
1061 make translation any reg class to an allocno class or to an
1062 pressure class. This translation is necessary for some
1063 calculations when we can use only allocno or pressure classes and
1064 such translation represents an approximate representation of all
1067 The translation in case when allocatable hard register set of a
1068 given class is subset of allocatable hard register set of a class
1069 in CLASSES is pretty simple. We use smallest classes from CLASSES
1070 containing a given class. If allocatable hard register set of a
1071 given class is not a subset of any corresponding set of a class
1072 from CLASSES, we use the cheapest (with load/store point of view)
1073 class from CLASSES whose set intersects with given class set. */
1075 setup_class_translate_array (enum reg_class
*class_translate
,
1076 int classes_num
, enum reg_class
*classes
)
1079 enum reg_class aclass
, best_class
, *cl_ptr
;
1080 int i
, cost
, min_cost
, best_cost
;
1082 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1083 class_translate
[cl
] = NO_REGS
;
1085 for (i
= 0; i
< classes_num
; i
++)
1087 aclass
= classes
[i
];
1088 for (cl_ptr
= &alloc_reg_class_subclasses
[aclass
][0];
1089 (cl
= *cl_ptr
) != LIM_REG_CLASSES
;
1091 if (class_translate
[cl
] == NO_REGS
)
1092 class_translate
[cl
] = aclass
;
1093 class_translate
[aclass
] = aclass
;
1095 /* For classes which are not fully covered by one of given classes
1096 (in other words covered by more one given class), use the
1098 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1100 if (cl
== NO_REGS
|| class_translate
[cl
] != NO_REGS
)
1102 best_class
= NO_REGS
;
1103 best_cost
= INT_MAX
;
1104 for (i
= 0; i
< classes_num
; i
++)
1106 aclass
= classes
[i
];
1107 temp_hard_regset
= (reg_class_contents
[aclass
]
1108 & reg_class_contents
[cl
]
1109 & ~no_unit_alloc_regs
);
1110 if (! hard_reg_set_empty_p (temp_hard_regset
))
1113 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1115 cost
= (ira_memory_move_cost
[mode
][aclass
][0]
1116 + ira_memory_move_cost
[mode
][aclass
][1]);
1117 if (min_cost
> cost
)
1120 if (best_class
== NO_REGS
|| best_cost
> min_cost
)
1122 best_class
= aclass
;
1123 best_cost
= min_cost
;
1127 class_translate
[cl
] = best_class
;
1131 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
1132 IRA_PRESSURE_CLASS_TRANSLATE. */
1134 setup_class_translate (void)
1136 setup_class_translate_array (ira_allocno_class_translate
,
1137 ira_allocno_classes_num
, ira_allocno_classes
);
1138 setup_class_translate_array (ira_pressure_class_translate
,
1139 ira_pressure_classes_num
, ira_pressure_classes
);
1142 /* Order numbers of allocno classes in original target allocno class
1143 array, -1 for non-allocno classes. */
1144 static int allocno_class_order
[N_REG_CLASSES
];
1146 /* The function used to sort the important classes. */
1148 comp_reg_classes_func (const void *v1p
, const void *v2p
)
1150 enum reg_class cl1
= *(const enum reg_class
*) v1p
;
1151 enum reg_class cl2
= *(const enum reg_class
*) v2p
;
1152 enum reg_class tcl1
, tcl2
;
1155 tcl1
= ira_allocno_class_translate
[cl1
];
1156 tcl2
= ira_allocno_class_translate
[cl2
];
1157 if (tcl1
!= NO_REGS
&& tcl2
!= NO_REGS
1158 && (diff
= allocno_class_order
[tcl1
] - allocno_class_order
[tcl2
]) != 0)
1160 return (int) cl1
- (int) cl2
;
1163 /* For correct work of function setup_reg_class_relation we need to
1164 reorder important classes according to the order of their allocno
1165 classes. It places important classes containing the same
1166 allocatable hard register set adjacent to each other and allocno
1167 class with the allocatable hard register set right after the other
1168 important classes with the same set.
1170 In example from comments of function
1171 setup_allocno_and_important_classes, it places LEGACY_REGS and
1172 GENERAL_REGS close to each other and GENERAL_REGS is after
1175 reorder_important_classes (void)
1179 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1180 allocno_class_order
[i
] = -1;
1181 for (i
= 0; i
< ira_allocno_classes_num
; i
++)
1182 allocno_class_order
[ira_allocno_classes
[i
]] = i
;
1183 qsort (ira_important_classes
, ira_important_classes_num
,
1184 sizeof (enum reg_class
), comp_reg_classes_func
);
1185 for (i
= 0; i
< ira_important_classes_num
; i
++)
1186 ira_important_class_nums
[ira_important_classes
[i
]] = i
;
1189 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
1190 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
1191 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
1192 please see corresponding comments in ira-int.h. */
1194 setup_reg_class_relations (void)
1196 int i
, cl1
, cl2
, cl3
;
1197 HARD_REG_SET intersection_set
, union_set
, temp_set2
;
1198 bool important_class_p
[N_REG_CLASSES
];
1200 memset (important_class_p
, 0, sizeof (important_class_p
));
1201 for (i
= 0; i
< ira_important_classes_num
; i
++)
1202 important_class_p
[ira_important_classes
[i
]] = true;
1203 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1205 ira_reg_class_super_classes
[cl1
][0] = LIM_REG_CLASSES
;
1206 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1208 ira_reg_classes_intersect_p
[cl1
][cl2
] = false;
1209 ira_reg_class_intersect
[cl1
][cl2
] = NO_REGS
;
1210 ira_reg_class_subset
[cl1
][cl2
] = NO_REGS
;
1211 temp_hard_regset
= reg_class_contents
[cl1
] & ~no_unit_alloc_regs
;
1212 temp_set2
= reg_class_contents
[cl2
] & ~no_unit_alloc_regs
;
1213 if (hard_reg_set_empty_p (temp_hard_regset
)
1214 && hard_reg_set_empty_p (temp_set2
))
1216 /* The both classes have no allocatable hard registers
1217 -- take all class hard registers into account and use
1218 reg_class_subunion and reg_class_superunion. */
1221 cl3
= reg_class_subclasses
[cl1
][i
];
1222 if (cl3
== LIM_REG_CLASSES
)
1224 if (reg_class_subset_p (ira_reg_class_intersect
[cl1
][cl2
],
1225 (enum reg_class
) cl3
))
1226 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1228 ira_reg_class_subunion
[cl1
][cl2
] = reg_class_subunion
[cl1
][cl2
];
1229 ira_reg_class_superunion
[cl1
][cl2
] = reg_class_superunion
[cl1
][cl2
];
1232 ira_reg_classes_intersect_p
[cl1
][cl2
]
1233 = hard_reg_set_intersect_p (temp_hard_regset
, temp_set2
);
1234 if (important_class_p
[cl1
] && important_class_p
[cl2
]
1235 && hard_reg_set_subset_p (temp_hard_regset
, temp_set2
))
1237 /* CL1 and CL2 are important classes and CL1 allocatable
1238 hard register set is inside of CL2 allocatable hard
1239 registers -- make CL1 a superset of CL2. */
1242 p
= &ira_reg_class_super_classes
[cl1
][0];
1243 while (*p
!= LIM_REG_CLASSES
)
1245 *p
++ = (enum reg_class
) cl2
;
1246 *p
= LIM_REG_CLASSES
;
1248 ira_reg_class_subunion
[cl1
][cl2
] = NO_REGS
;
1249 ira_reg_class_superunion
[cl1
][cl2
] = NO_REGS
;
1250 intersection_set
= (reg_class_contents
[cl1
]
1251 & reg_class_contents
[cl2
]
1252 & ~no_unit_alloc_regs
);
1253 union_set
= ((reg_class_contents
[cl1
] | reg_class_contents
[cl2
])
1254 & ~no_unit_alloc_regs
);
1255 for (cl3
= 0; cl3
< N_REG_CLASSES
; cl3
++)
1257 temp_hard_regset
= reg_class_contents
[cl3
] & ~no_unit_alloc_regs
;
1258 if (hard_reg_set_subset_p (temp_hard_regset
, intersection_set
))
1260 /* CL3 allocatable hard register set is inside of
1261 intersection of allocatable hard register sets
1263 if (important_class_p
[cl3
])
1266 = (reg_class_contents
1267 [ira_reg_class_intersect
[cl1
][cl2
]]);
1268 temp_set2
&= ~no_unit_alloc_regs
;
1269 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1270 /* If the allocatable hard register sets are
1271 the same, prefer GENERAL_REGS or the
1272 smallest class for debugging
1274 || (temp_hard_regset
== temp_set2
1275 && (cl3
== GENERAL_REGS
1276 || ((ira_reg_class_intersect
[cl1
][cl2
]
1278 && hard_reg_set_subset_p
1279 (reg_class_contents
[cl3
],
1282 ira_reg_class_intersect
[cl1
][cl2
]])))))
1283 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1286 = (reg_class_contents
[ira_reg_class_subset
[cl1
][cl2
]]
1287 & ~no_unit_alloc_regs
);
1288 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1289 /* Ignore unavailable hard registers and prefer
1290 smallest class for debugging purposes. */
1291 || (temp_hard_regset
== temp_set2
1292 && hard_reg_set_subset_p
1293 (reg_class_contents
[cl3
],
1295 [(int) ira_reg_class_subset
[cl1
][cl2
]])))
1296 ira_reg_class_subset
[cl1
][cl2
] = (enum reg_class
) cl3
;
1298 if (important_class_p
[cl3
]
1299 && hard_reg_set_subset_p (temp_hard_regset
, union_set
))
1301 /* CL3 allocatable hard register set is inside of
1302 union of allocatable hard register sets of CL1
1305 = (reg_class_contents
[ira_reg_class_subunion
[cl1
][cl2
]]
1306 & ~no_unit_alloc_regs
);
1307 if (ira_reg_class_subunion
[cl1
][cl2
] == NO_REGS
1308 || (hard_reg_set_subset_p (temp_set2
, temp_hard_regset
)
1310 && (temp_set2
!= temp_hard_regset
1311 || cl3
== GENERAL_REGS
1312 /* If the allocatable hard register sets are the
1313 same, prefer GENERAL_REGS or the smallest
1314 class for debugging purposes. */
1315 || (ira_reg_class_subunion
[cl1
][cl2
] != GENERAL_REGS
1316 && hard_reg_set_subset_p
1317 (reg_class_contents
[cl3
],
1319 [(int) ira_reg_class_subunion
[cl1
][cl2
]])))))
1320 ira_reg_class_subunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1322 if (hard_reg_set_subset_p (union_set
, temp_hard_regset
))
1324 /* CL3 allocatable hard register set contains union
1325 of allocatable hard register sets of CL1 and
1328 = (reg_class_contents
[ira_reg_class_superunion
[cl1
][cl2
]]
1329 & ~no_unit_alloc_regs
);
1330 if (ira_reg_class_superunion
[cl1
][cl2
] == NO_REGS
1331 || (hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1333 && (temp_set2
!= temp_hard_regset
1334 || cl3
== GENERAL_REGS
1335 /* If the allocatable hard register sets are the
1336 same, prefer GENERAL_REGS or the smallest
1337 class for debugging purposes. */
1338 || (ira_reg_class_superunion
[cl1
][cl2
] != GENERAL_REGS
1339 && hard_reg_set_subset_p
1340 (reg_class_contents
[cl3
],
1342 [(int) ira_reg_class_superunion
[cl1
][cl2
]])))))
1343 ira_reg_class_superunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1350 /* Output all uniform and important classes into file F. */
1352 print_uniform_and_important_classes (FILE *f
)
1356 fprintf (f
, "Uniform classes:\n");
1357 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1358 if (ira_uniform_class_p
[cl
])
1359 fprintf (f
, " %s", reg_class_names
[cl
]);
1360 fprintf (f
, "\nImportant classes:\n");
1361 for (i
= 0; i
< ira_important_classes_num
; i
++)
1362 fprintf (f
, " %s", reg_class_names
[ira_important_classes
[i
]]);
1366 /* Output all possible allocno or pressure classes and their
1367 translation map into file F. */
1369 print_translated_classes (FILE *f
, bool pressure_p
)
1371 int classes_num
= (pressure_p
1372 ? ira_pressure_classes_num
: ira_allocno_classes_num
);
1373 enum reg_class
*classes
= (pressure_p
1374 ? ira_pressure_classes
: ira_allocno_classes
);
1375 enum reg_class
*class_translate
= (pressure_p
1376 ? ira_pressure_class_translate
1377 : ira_allocno_class_translate
);
1380 fprintf (f
, "%s classes:\n", pressure_p
? "Pressure" : "Allocno");
1381 for (i
= 0; i
< classes_num
; i
++)
1382 fprintf (f
, " %s", reg_class_names
[classes
[i
]]);
1383 fprintf (f
, "\nClass translation:\n");
1384 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1385 fprintf (f
, " %s -> %s\n", reg_class_names
[i
],
1386 reg_class_names
[class_translate
[i
]]);
1389 /* Output all possible allocno and translation classes and the
1390 translation maps into stderr. */
1392 ira_debug_allocno_classes (void)
1394 print_uniform_and_important_classes (stderr
);
1395 print_translated_classes (stderr
, false);
1396 print_translated_classes (stderr
, true);
1399 /* Set up different arrays concerning class subsets, allocno and
1400 important classes. */
1402 find_reg_classes (void)
1404 setup_allocno_and_important_classes ();
1405 setup_class_translate ();
1406 reorder_important_classes ();
1407 setup_reg_class_relations ();
1412 /* Set up the array above. */
1414 setup_hard_regno_aclass (void)
1418 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1421 ira_hard_regno_allocno_class
[i
]
1422 = (TEST_HARD_REG_BIT (no_unit_alloc_regs
, i
)
1424 : ira_allocno_class_translate
[REGNO_REG_CLASS (i
)]);
1428 ira_hard_regno_allocno_class
[i
] = NO_REGS
;
1429 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1431 cl
= ira_allocno_classes
[j
];
1432 if (ira_class_hard_reg_index
[cl
][i
] >= 0)
1434 ira_hard_regno_allocno_class
[i
] = cl
;
1444 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
1446 setup_reg_class_nregs (void)
1450 for (m
= 0; m
< MAX_MACHINE_MODE
; m
++)
1452 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1453 ira_reg_class_max_nregs
[cl
][m
]
1454 = ira_reg_class_min_nregs
[cl
][m
]
1455 = targetm
.class_max_nregs ((reg_class_t
) cl
, (machine_mode
) m
);
1456 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1458 (cl2
= alloc_reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
;
1460 if (ira_reg_class_min_nregs
[cl2
][m
]
1461 < ira_reg_class_min_nregs
[cl
][m
])
1462 ira_reg_class_min_nregs
[cl
][m
] = ira_reg_class_min_nregs
[cl2
][m
];
1468 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON.
1469 This function is called once IRA_CLASS_HARD_REGS has been initialized. */
1471 setup_prohibited_class_mode_regs (void)
1473 int j
, k
, hard_regno
, cl
, last_hard_regno
, count
;
1475 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1477 temp_hard_regset
= reg_class_contents
[cl
] & ~no_unit_alloc_regs
;
1478 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1481 last_hard_regno
= -1;
1482 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs
[cl
][j
]);
1483 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1485 hard_regno
= ira_class_hard_regs
[cl
][k
];
1486 if (!targetm
.hard_regno_mode_ok (hard_regno
, (machine_mode
) j
))
1487 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1489 else if (in_hard_reg_set_p (temp_hard_regset
,
1490 (machine_mode
) j
, hard_regno
))
1492 last_hard_regno
= hard_regno
;
1496 ira_class_singleton
[cl
][j
] = (count
== 1 ? last_hard_regno
: -1);
1501 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
1502 spanning from one register pressure class to another one. It is
1503 called after defining the pressure classes. */
1505 clarify_prohibited_class_mode_regs (void)
1507 int j
, k
, hard_regno
, cl
, pclass
, nregs
;
1509 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1510 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1512 CLEAR_HARD_REG_SET (ira_useful_class_mode_regs
[cl
][j
]);
1513 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1515 hard_regno
= ira_class_hard_regs
[cl
][k
];
1516 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
], hard_regno
))
1518 nregs
= hard_regno_nregs (hard_regno
, (machine_mode
) j
);
1519 if (hard_regno
+ nregs
> FIRST_PSEUDO_REGISTER
)
1521 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1525 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1526 for (nregs
-- ;nregs
>= 0; nregs
--)
1527 if (((enum reg_class
) pclass
1528 != ira_pressure_class_translate
[REGNO_REG_CLASS
1529 (hard_regno
+ nregs
)]))
1531 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1535 if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1537 add_to_hard_reg_set (&ira_useful_class_mode_regs
[cl
][j
],
1538 (machine_mode
) j
, hard_regno
);
1543 /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST
1544 and IRA_MAY_MOVE_OUT_COST for MODE. */
1546 ira_init_register_move_cost (machine_mode mode
)
1548 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
1549 bool all_match
= true;
1550 unsigned int i
, cl1
, cl2
;
1551 HARD_REG_SET ok_regs
;
1553 ira_assert (ira_register_move_cost
[mode
] == NULL
1554 && ira_may_move_in_cost
[mode
] == NULL
1555 && ira_may_move_out_cost
[mode
] == NULL
);
1556 CLEAR_HARD_REG_SET (ok_regs
);
1557 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1558 if (targetm
.hard_regno_mode_ok (i
, mode
))
1559 SET_HARD_REG_BIT (ok_regs
, i
);
1561 /* Note that we might be asked about the move costs of modes that
1562 cannot be stored in any hard register, for example if an inline
1563 asm tries to create a register operand with an impossible mode.
1564 We therefore can't assert have_regs_of_mode[mode] here. */
1565 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1566 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1569 if (!hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[cl1
])
1570 || !hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[cl2
]))
1572 if ((ira_reg_class_max_nregs
[cl1
][mode
]
1573 > ira_class_hard_regs_num
[cl1
])
1574 || (ira_reg_class_max_nregs
[cl2
][mode
]
1575 > ira_class_hard_regs_num
[cl2
]))
1578 cost
= (ira_memory_move_cost
[mode
][cl1
][0]
1579 + ira_memory_move_cost
[mode
][cl2
][1]) * 2;
1583 cost
= register_move_cost (mode
, (enum reg_class
) cl1
,
1584 (enum reg_class
) cl2
);
1585 ira_assert (cost
< 65535);
1587 all_match
&= (last_move_cost
[cl1
][cl2
] == cost
);
1588 last_move_cost
[cl1
][cl2
] = cost
;
1590 if (all_match
&& last_mode_for_init_move_cost
!= -1)
1592 ira_register_move_cost
[mode
]
1593 = ira_register_move_cost
[last_mode_for_init_move_cost
];
1594 ira_may_move_in_cost
[mode
]
1595 = ira_may_move_in_cost
[last_mode_for_init_move_cost
];
1596 ira_may_move_out_cost
[mode
]
1597 = ira_may_move_out_cost
[last_mode_for_init_move_cost
];
1600 last_mode_for_init_move_cost
= mode
;
1601 ira_register_move_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1602 ira_may_move_in_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1603 ira_may_move_out_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1604 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1605 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1608 enum reg_class
*p1
, *p2
;
1610 if (last_move_cost
[cl1
][cl2
] == 65535)
1612 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1613 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1614 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1618 cost
= last_move_cost
[cl1
][cl2
];
1620 for (p2
= ®_class_subclasses
[cl2
][0];
1621 *p2
!= LIM_REG_CLASSES
; p2
++)
1622 if (ira_class_hard_regs_num
[*p2
] > 0
1623 && (ira_reg_class_max_nregs
[*p2
][mode
]
1624 <= ira_class_hard_regs_num
[*p2
]))
1625 cost
= MAX (cost
, ira_register_move_cost
[mode
][cl1
][*p2
]);
1627 for (p1
= ®_class_subclasses
[cl1
][0];
1628 *p1
!= LIM_REG_CLASSES
; p1
++)
1629 if (ira_class_hard_regs_num
[*p1
] > 0
1630 && (ira_reg_class_max_nregs
[*p1
][mode
]
1631 <= ira_class_hard_regs_num
[*p1
]))
1632 cost
= MAX (cost
, ira_register_move_cost
[mode
][*p1
][cl2
]);
1634 ira_assert (cost
<= 65535);
1635 ira_register_move_cost
[mode
][cl1
][cl2
] = cost
;
1637 if (ira_class_subset_p
[cl1
][cl2
])
1638 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 0;
1640 ira_may_move_in_cost
[mode
][cl1
][cl2
] = cost
;
1642 if (ira_class_subset_p
[cl2
][cl1
])
1643 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 0;
1645 ira_may_move_out_cost
[mode
][cl1
][cl2
] = cost
;
1652 /* This is called once during compiler work. It sets up
1653 different arrays whose values don't depend on the compiled
1656 ira_init_once (void)
1658 ira_init_costs_once ();
1661 ira_use_lra_p
= targetm
.lra_p ();
1664 /* Free ira_max_register_move_cost, ira_may_move_in_cost and
1665 ira_may_move_out_cost for each mode. */
1667 target_ira_int::free_register_move_costs (void)
1671 /* Reset move_cost and friends, making sure we only free shared
1672 table entries once. */
1673 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1674 if (x_ira_register_move_cost
[mode
])
1677 i
< mode
&& (x_ira_register_move_cost
[i
]
1678 != x_ira_register_move_cost
[mode
]);
1683 free (x_ira_register_move_cost
[mode
]);
1684 free (x_ira_may_move_in_cost
[mode
]);
1685 free (x_ira_may_move_out_cost
[mode
]);
1688 memset (x_ira_register_move_cost
, 0, sizeof x_ira_register_move_cost
);
1689 memset (x_ira_may_move_in_cost
, 0, sizeof x_ira_may_move_in_cost
);
1690 memset (x_ira_may_move_out_cost
, 0, sizeof x_ira_may_move_out_cost
);
1691 last_mode_for_init_move_cost
= -1;
1694 target_ira_int::~target_ira_int ()
1697 free_register_move_costs ();
1700 /* This is called every time when register related information is
1705 this_target_ira_int
->free_register_move_costs ();
1706 setup_reg_mode_hard_regset ();
1707 setup_alloc_regs (flag_omit_frame_pointer
!= 0);
1708 setup_class_subset_and_memory_move_costs ();
1709 setup_reg_class_nregs ();
1710 setup_prohibited_class_mode_regs ();
1711 find_reg_classes ();
1712 clarify_prohibited_class_mode_regs ();
1713 setup_hard_regno_aclass ();
1718 #define ira_prohibited_mode_move_regs_initialized_p \
1719 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p)
1721 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */
1723 setup_prohibited_mode_move_regs (void)
1726 rtx test_reg1
, test_reg2
, move_pat
;
1727 rtx_insn
*move_insn
;
1729 if (ira_prohibited_mode_move_regs_initialized_p
)
1731 ira_prohibited_mode_move_regs_initialized_p
= true;
1732 test_reg1
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
1733 test_reg2
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 2);
1734 move_pat
= gen_rtx_SET (test_reg1
, test_reg2
);
1735 move_insn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, move_pat
, 0, -1, 0);
1736 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1738 SET_HARD_REG_SET (ira_prohibited_mode_move_regs
[i
]);
1739 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1741 if (!targetm
.hard_regno_mode_ok (j
, (machine_mode
) i
))
1743 set_mode_and_regno (test_reg1
, (machine_mode
) i
, j
);
1744 set_mode_and_regno (test_reg2
, (machine_mode
) i
, j
);
1745 INSN_CODE (move_insn
) = -1;
1746 recog_memoized (move_insn
);
1747 if (INSN_CODE (move_insn
) < 0)
1749 extract_insn (move_insn
);
1750 /* We don't know whether the move will be in code that is optimized
1751 for size or speed, so consider all enabled alternatives. */
1752 if (! constrain_operands (1, get_enabled_alternatives (move_insn
)))
1754 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs
[i
], j
);
1761 /* Extract INSN and return the set of alternatives that we should consider.
1762 This excludes any alternatives whose constraints are obviously impossible
1763 to meet (e.g. because the constraint requires a constant and the operand
1764 is nonconstant). It also excludes alternatives that are bound to need
1765 a spill or reload, as long as we have other alternatives that match
1768 ira_setup_alts (rtx_insn
*insn
)
1773 int commutative
= -1;
1775 extract_insn (insn
);
1776 preprocess_constraints (insn
);
1777 alternative_mask preferred
= get_preferred_alternatives (insn
);
1778 alternative_mask alts
= 0;
1779 alternative_mask exact_alts
= 0;
1780 /* Check that the hard reg set is enough for holding all
1781 alternatives. It is hard to imagine the situation when the
1782 assertion is wrong. */
1783 ira_assert (recog_data
.n_alternatives
1784 <= (int) MAX (sizeof (HARD_REG_ELT_TYPE
) * CHAR_BIT
,
1785 FIRST_PSEUDO_REGISTER
));
1786 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1787 if (recog_data
.constraints
[nop
][0] == '%')
1792 for (curr_swapped
= false;; curr_swapped
= true)
1794 for (nalt
= 0; nalt
< recog_data
.n_alternatives
; nalt
++)
1796 if (!TEST_BIT (preferred
, nalt
) || TEST_BIT (exact_alts
, nalt
))
1799 const operand_alternative
*op_alt
1800 = &recog_op_alt
[nalt
* recog_data
.n_operands
];
1801 int this_reject
= 0;
1802 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1806 this_reject
+= op_alt
[nop
].reject
;
1808 rtx op
= recog_data
.operand
[nop
];
1809 p
= op_alt
[nop
].constraint
;
1810 if (*p
== 0 || *p
== ',')
1815 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
1826 /* The commutative modifier is handled above. */
1829 case '0': case '1': case '2': case '3': case '4':
1830 case '5': case '6': case '7': case '8': case '9':
1833 unsigned long dup
= strtoul (p
, &end
, 10);
1834 rtx other
= recog_data
.operand
[dup
];
1837 ? rtx_equal_p (other
, op
)
1838 : REG_P (op
) || SUBREG_P (op
))
1850 enum constraint_num cn
= lookup_constraint (p
);
1852 switch (get_constraint_type (cn
))
1855 if (reg_class_for_constraint (cn
) != NO_REGS
)
1857 if (REG_P (op
) || SUBREG_P (op
))
1864 if (CONST_INT_P (op
)
1865 && (insn_const_int_ok_for_constraint
1874 case CT_RELAXED_MEMORY
:
1877 case CT_SPECIAL_MEMORY
:
1879 mem
= extract_mem_from_operand (op
);
1886 if (constraint_satisfied_p (op
, cn
))
1893 while (p
+= len
, c
);
1896 /* We can make the alternative match by spilling a register
1897 to memory or loading something into a register. Count a
1898 cost of one reload (the equivalent of the '?' constraint). */
1904 if (nop
>= recog_data
.n_operands
)
1906 alts
|= ALTERNATIVE_BIT (nalt
);
1907 if (this_reject
== 0)
1908 exact_alts
|= ALTERNATIVE_BIT (nalt
);
1911 if (commutative
< 0)
1913 /* Swap forth and back to avoid changing recog_data. */
1914 std::swap (recog_data
.operand
[commutative
],
1915 recog_data
.operand
[commutative
+ 1]);
1919 return exact_alts
? exact_alts
: alts
;
1922 /* Return the number of the output non-early clobber operand which
1923 should be the same in any case as operand with number OP_NUM (or
1924 negative value if there is no such operand). ALTS is the mask
1925 of alternatives that we should consider. */
1927 ira_get_dup_out_num (int op_num
, alternative_mask alts
)
1929 int curr_alt
, c
, original
;
1930 bool ignore_p
, use_commut_op_p
;
1933 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
1935 /* We should find duplications only for input operands. */
1936 if (recog_data
.operand_type
[op_num
] != OP_IN
)
1938 str
= recog_data
.constraints
[op_num
];
1939 use_commut_op_p
= false;
1942 rtx op
= recog_data
.operand
[op_num
];
1944 for (curr_alt
= 0, ignore_p
= !TEST_BIT (alts
, curr_alt
),
1955 ignore_p
= !TEST_BIT (alts
, curr_alt
);
1957 else if (! ignore_p
)
1964 enum constraint_num cn
= lookup_constraint (str
);
1965 enum reg_class cl
= reg_class_for_constraint (cn
);
1967 && !targetm
.class_likely_spilled_p (cl
))
1969 if (constraint_satisfied_p (op
, cn
))
1974 case '0': case '1': case '2': case '3': case '4':
1975 case '5': case '6': case '7': case '8': case '9':
1978 int n
= (int) strtoul (str
, &end
, 10);
1980 if (original
!= -1 && original
!= n
)
1986 str
+= CONSTRAINT_LEN (c
, str
);
1990 if (recog_data
.operand_type
[original
] == OP_OUT
)
1993 if (use_commut_op_p
)
1995 use_commut_op_p
= true;
1996 if (recog_data
.constraints
[op_num
][0] == '%')
1997 str
= recog_data
.constraints
[op_num
+ 1];
1998 else if (op_num
> 0 && recog_data
.constraints
[op_num
- 1][0] == '%')
1999 str
= recog_data
.constraints
[op_num
- 1];
2008 /* Search forward to see if the source register of a copy insn dies
2009 before either it or the destination register is modified, but don't
2010 scan past the end of the basic block. If so, we can replace the
2011 source with the destination and let the source die in the copy
2014 This will reduce the number of registers live in that range and may
2015 enable the destination and the source coalescing, thus often saving
2016 one register in addition to a register-register copy. */
2019 decrease_live_ranges_number (void)
2023 rtx set
, src
, dest
, dest_death
, note
;
2027 if (! flag_expensive_optimizations
)
2031 fprintf (ira_dump_file
, "Starting decreasing number of live ranges...\n");
2033 FOR_EACH_BB_FN (bb
, cfun
)
2034 FOR_BB_INSNS (bb
, insn
)
2036 set
= single_set (insn
);
2039 src
= SET_SRC (set
);
2040 dest
= SET_DEST (set
);
2041 if (! REG_P (src
) || ! REG_P (dest
)
2042 || find_reg_note (insn
, REG_DEAD
, src
))
2044 sregno
= REGNO (src
);
2045 dregno
= REGNO (dest
);
2047 /* We don't want to mess with hard regs if register classes
2049 if (sregno
== dregno
2050 || (targetm
.small_register_classes_for_mode_p (GET_MODE (src
))
2051 && (sregno
< FIRST_PSEUDO_REGISTER
2052 || dregno
< FIRST_PSEUDO_REGISTER
))
2053 /* We don't see all updates to SP if they are in an
2054 auto-inc memory reference, so we must disallow this
2055 optimization on them. */
2056 || sregno
== STACK_POINTER_REGNUM
2057 || dregno
== STACK_POINTER_REGNUM
)
2060 dest_death
= NULL_RTX
;
2062 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
2066 if (BLOCK_FOR_INSN (p
) != bb
)
2069 if (reg_set_p (src
, p
) || reg_set_p (dest
, p
)
2070 /* If SRC is an asm-declared register, it must not be
2071 replaced in any asm. Unfortunately, the REG_EXPR
2072 tree for the asm variable may be absent in the SRC
2073 rtx, so we can't check the actual register
2074 declaration easily (the asm operand will have it,
2075 though). To avoid complicating the test for a rare
2076 case, we just don't perform register replacement
2077 for a hard reg mentioned in an asm. */
2078 || (sregno
< FIRST_PSEUDO_REGISTER
2079 && asm_noperands (PATTERN (p
)) >= 0
2080 && reg_overlap_mentioned_p (src
, PATTERN (p
)))
2081 /* Don't change hard registers used by a call. */
2082 || (CALL_P (p
) && sregno
< FIRST_PSEUDO_REGISTER
2083 && find_reg_fusage (p
, USE
, src
))
2084 /* Don't change a USE of a register. */
2085 || (GET_CODE (PATTERN (p
)) == USE
2086 && reg_overlap_mentioned_p (src
, XEXP (PATTERN (p
), 0))))
2089 /* See if all of SRC dies in P. This test is slightly
2090 more conservative than it needs to be. */
2091 if ((note
= find_regno_note (p
, REG_DEAD
, sregno
))
2092 && GET_MODE (XEXP (note
, 0)) == GET_MODE (src
))
2096 /* We can do the optimization. Scan forward from INSN
2097 again, replacing regs as we go. Set FAILED if a
2098 replacement can't be done. In that case, we can't
2099 move the death note for SRC. This should be
2102 /* Set to stop at next insn. */
2103 for (q
= next_real_insn (insn
);
2104 q
!= next_real_insn (p
);
2105 q
= next_real_insn (q
))
2107 if (reg_overlap_mentioned_p (src
, PATTERN (q
)))
2109 /* If SRC is a hard register, we might miss
2110 some overlapping registers with
2111 validate_replace_rtx, so we would have to
2112 undo it. We can't if DEST is present in
2113 the insn, so fail in that combination of
2115 if (sregno
< FIRST_PSEUDO_REGISTER
2116 && reg_mentioned_p (dest
, PATTERN (q
)))
2119 /* Attempt to replace all uses. */
2120 else if (!validate_replace_rtx (src
, dest
, q
))
2123 /* If this succeeded, but some part of the
2124 register is still present, undo the
2126 else if (sregno
< FIRST_PSEUDO_REGISTER
2127 && reg_overlap_mentioned_p (src
, PATTERN (q
)))
2129 validate_replace_rtx (dest
, src
, q
);
2134 /* If DEST dies here, remove the death note and
2135 save it for later. Make sure ALL of DEST dies
2136 here; again, this is overly conservative. */
2138 && (dest_death
= find_regno_note (q
, REG_DEAD
, dregno
)))
2140 if (GET_MODE (XEXP (dest_death
, 0)) == GET_MODE (dest
))
2141 remove_note (q
, dest_death
);
2152 /* Move death note of SRC from P to INSN. */
2153 remove_note (p
, note
);
2154 XEXP (note
, 1) = REG_NOTES (insn
);
2155 REG_NOTES (insn
) = note
;
2158 /* DEST is also dead if INSN has a REG_UNUSED note for
2162 = find_regno_note (insn
, REG_UNUSED
, dregno
)))
2164 PUT_REG_NOTE_KIND (dest_death
, REG_DEAD
);
2165 remove_note (insn
, dest_death
);
2168 /* Put death note of DEST on P if we saw it die. */
2171 XEXP (dest_death
, 1) = REG_NOTES (p
);
2172 REG_NOTES (p
) = dest_death
;
2177 /* If SRC is a hard register which is set or killed in
2178 some other way, we can't do this optimization. */
2179 else if (sregno
< FIRST_PSEUDO_REGISTER
&& dead_or_set_p (p
, src
))
2187 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */
2189 ira_bad_reload_regno_1 (int regno
, rtx x
)
2193 enum reg_class pref
;
2195 /* We only deal with pseudo regs. */
2196 if (! x
|| GET_CODE (x
) != REG
)
2199 x_regno
= REGNO (x
);
2200 if (x_regno
< FIRST_PSEUDO_REGISTER
)
2203 /* If the pseudo prefers REGNO explicitly, then do not consider
2204 REGNO a bad spill choice. */
2205 pref
= reg_preferred_class (x_regno
);
2206 if (reg_class_size
[pref
] == 1)
2207 return !TEST_HARD_REG_BIT (reg_class_contents
[pref
], regno
);
2209 /* If the pseudo conflicts with REGNO, then we consider REGNO a
2210 poor choice for a reload regno. */
2211 a
= ira_regno_allocno_map
[x_regno
];
2212 n
= ALLOCNO_NUM_OBJECTS (a
);
2213 for (i
= 0; i
< n
; i
++)
2215 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2216 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
))
2222 /* Return nonzero if REGNO is a particularly bad choice for reloading
2225 ira_bad_reload_regno (int regno
, rtx in
, rtx out
)
2227 return (ira_bad_reload_regno_1 (regno
, in
)
2228 || ira_bad_reload_regno_1 (regno
, out
));
2231 /* Add register clobbers from asm statements. */
2233 compute_regs_asm_clobbered (void)
2237 FOR_EACH_BB_FN (bb
, cfun
)
2240 FOR_BB_INSNS_REVERSE (bb
, insn
)
2244 if (NONDEBUG_INSN_P (insn
) && asm_noperands (PATTERN (insn
)) >= 0)
2245 FOR_EACH_INSN_DEF (def
, insn
)
2247 unsigned int dregno
= DF_REF_REGNO (def
);
2248 if (HARD_REGISTER_NUM_P (dregno
))
2249 add_to_hard_reg_set (&crtl
->asm_clobbers
,
2250 GET_MODE (DF_REF_REAL_REG (def
)),
2258 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and
2261 ira_setup_eliminable_regset (void)
2264 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2265 int fp_reg_count
= hard_regno_nregs (HARD_FRAME_POINTER_REGNUM
, Pmode
);
2267 /* Setup is_leaf as frame_pointer_required may use it. This function
2268 is called by sched_init before ira if scheduling is enabled. */
2269 crtl
->is_leaf
= leaf_function_p ();
2271 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore
2272 sp for alloca. So we can't eliminate the frame pointer in that
2273 case. At some point, we should improve this by emitting the
2274 sp-adjusting insns for this case. */
2275 frame_pointer_needed
2276 = (! flag_omit_frame_pointer
2277 || (cfun
->calls_alloca
&& EXIT_IGNORE_STACK
)
2278 /* We need the frame pointer to catch stack overflow exceptions if
2279 the stack pointer is moving (as for the alloca case just above). */
2280 || (STACK_CHECK_MOVING_SP
2283 && cfun
->can_throw_non_call_exceptions
)
2284 || crtl
->accesses_prior_frames
2285 || (SUPPORTS_STACK_ALIGNMENT
&& crtl
->stack_realign_needed
)
2286 || targetm
.frame_pointer_required ());
2288 /* The chance that FRAME_POINTER_NEEDED is changed from inspecting
2289 RTL is very small. So if we use frame pointer for RA and RTL
2290 actually prevents this, we will spill pseudos assigned to the
2291 frame pointer in LRA. */
2293 if (frame_pointer_needed
)
2294 for (i
= 0; i
< fp_reg_count
; i
++)
2295 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
+ i
, true);
2297 ira_no_alloc_regs
= no_unit_alloc_regs
;
2298 CLEAR_HARD_REG_SET (eliminable_regset
);
2300 compute_regs_asm_clobbered ();
2302 /* Build the regset of all eliminable registers and show we can't
2303 use those that we already know won't be eliminated. */
2304 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2307 = (! targetm
.can_eliminate (eliminables
[i
].from
, eliminables
[i
].to
)
2308 || (eliminables
[i
].to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
2310 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, eliminables
[i
].from
))
2312 SET_HARD_REG_BIT (eliminable_regset
, eliminables
[i
].from
);
2315 SET_HARD_REG_BIT (ira_no_alloc_regs
, eliminables
[i
].from
);
2317 else if (cannot_elim
)
2318 error ("%s cannot be used in %<asm%> here",
2319 reg_names
[eliminables
[i
].from
]);
2321 df_set_regs_ever_live (eliminables
[i
].from
, true);
2323 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
)
2325 for (i
= 0; i
< fp_reg_count
; i
++)
2326 if (global_regs
[HARD_FRAME_POINTER_REGNUM
+ i
])
2327 /* Nothing to do: the register is already treated as live
2328 where appropriate, and cannot be eliminated. */
2330 else if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
,
2331 HARD_FRAME_POINTER_REGNUM
+ i
))
2333 SET_HARD_REG_BIT (eliminable_regset
,
2334 HARD_FRAME_POINTER_REGNUM
+ i
);
2335 if (frame_pointer_needed
)
2336 SET_HARD_REG_BIT (ira_no_alloc_regs
,
2337 HARD_FRAME_POINTER_REGNUM
+ i
);
2339 else if (frame_pointer_needed
)
2340 error ("%s cannot be used in %<asm%> here",
2341 reg_names
[HARD_FRAME_POINTER_REGNUM
+ i
]);
2343 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
+ i
, true);
2349 /* Vector of substitutions of register numbers,
2350 used to map pseudo regs into hardware regs.
2351 This is set up as a result of register allocation.
2352 Element N is the hard reg assigned to pseudo reg N,
2353 or is -1 if no hard reg was assigned.
2354 If N is a hard reg number, element N is N. */
2355 short *reg_renumber
;
2357 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from
2358 the allocation found by IRA. */
2360 setup_reg_renumber (void)
2362 int regno
, hard_regno
;
2364 ira_allocno_iterator ai
;
2366 caller_save_needed
= 0;
2367 FOR_EACH_ALLOCNO (a
, ai
)
2369 if (ira_use_lra_p
&& ALLOCNO_CAP_MEMBER (a
) != NULL
)
2371 /* There are no caps at this point. */
2372 ira_assert (ALLOCNO_CAP_MEMBER (a
) == NULL
);
2373 if (! ALLOCNO_ASSIGNED_P (a
))
2374 /* It can happen if A is not referenced but partially anticipated
2375 somewhere in a region. */
2376 ALLOCNO_ASSIGNED_P (a
) = true;
2377 ira_free_allocno_updated_costs (a
);
2378 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2379 regno
= ALLOCNO_REGNO (a
);
2380 reg_renumber
[regno
] = (hard_regno
< 0 ? -1 : hard_regno
);
2381 if (hard_regno
>= 0)
2384 enum reg_class pclass
;
2387 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
2388 nwords
= ALLOCNO_NUM_OBJECTS (a
);
2389 for (i
= 0; i
< nwords
; i
++)
2391 obj
= ALLOCNO_OBJECT (a
, i
);
2392 OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
)
2393 |= ~reg_class_contents
[pclass
];
2395 if (ira_need_caller_save_p (a
, hard_regno
))
2397 ira_assert (!optimize
|| flag_caller_saves
2398 || (ALLOCNO_CALLS_CROSSED_NUM (a
)
2399 == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2400 || regno
>= ira_reg_equiv_len
2401 || ira_equiv_no_lvalue_p (regno
));
2402 caller_save_needed
= 1;
2408 /* Set up allocno assignment flags for further allocation
2411 setup_allocno_assignment_flags (void)
2415 ira_allocno_iterator ai
;
2417 FOR_EACH_ALLOCNO (a
, ai
)
2419 if (! ALLOCNO_ASSIGNED_P (a
))
2420 /* It can happen if A is not referenced but partially anticipated
2421 somewhere in a region. */
2422 ira_free_allocno_updated_costs (a
);
2423 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2424 /* Don't assign hard registers to allocnos which are destination
2425 of removed store at the end of loop. It has no sense to keep
2426 the same value in different hard registers. It is also
2427 impossible to assign hard registers correctly to such
2428 allocnos because the cost info and info about intersected
2429 calls are incorrect for them. */
2430 ALLOCNO_ASSIGNED_P (a
) = (hard_regno
>= 0
2431 || ALLOCNO_EMIT_DATA (a
)->mem_optimized_dest_p
2432 || (ALLOCNO_MEMORY_COST (a
)
2433 - ALLOCNO_CLASS_COST (a
)) < 0);
2436 || ira_hard_reg_in_set_p (hard_regno
, ALLOCNO_MODE (a
),
2437 reg_class_contents
[ALLOCNO_CLASS (a
)]));
2441 /* Evaluate overall allocation cost and the costs for using hard
2442 registers and memory for allocnos. */
2444 calculate_allocation_cost (void)
2446 int hard_regno
, cost
;
2448 ira_allocno_iterator ai
;
2450 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
2451 FOR_EACH_ALLOCNO (a
, ai
)
2453 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2454 ira_assert (hard_regno
< 0
2455 || (ira_hard_reg_in_set_p
2456 (hard_regno
, ALLOCNO_MODE (a
),
2457 reg_class_contents
[ALLOCNO_CLASS (a
)])));
2460 cost
= ALLOCNO_MEMORY_COST (a
);
2461 ira_mem_cost
+= cost
;
2463 else if (ALLOCNO_HARD_REG_COSTS (a
) != NULL
)
2465 cost
= (ALLOCNO_HARD_REG_COSTS (a
)
2466 [ira_class_hard_reg_index
2467 [ALLOCNO_CLASS (a
)][hard_regno
]]);
2468 ira_reg_cost
+= cost
;
2472 cost
= ALLOCNO_CLASS_COST (a
);
2473 ira_reg_cost
+= cost
;
2475 ira_overall_cost
+= cost
;
2478 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
2480 fprintf (ira_dump_file
,
2481 "+++Costs: overall %" PRId64
2487 ira_overall_cost
, ira_reg_cost
, ira_mem_cost
,
2488 ira_load_cost
, ira_store_cost
, ira_shuffle_cost
);
2489 fprintf (ira_dump_file
, "\n+++ move loops %d, new jumps %d\n",
2490 ira_move_loops_num
, ira_additional_jumps_num
);
2495 #ifdef ENABLE_IRA_CHECKING
2496 /* Check the correctness of the allocation. We do need this because
2497 of complicated code to transform more one region internal
2498 representation into one region representation. */
2500 check_allocation (void)
2503 int hard_regno
, nregs
, conflict_nregs
;
2504 ira_allocno_iterator ai
;
2506 FOR_EACH_ALLOCNO (a
, ai
)
2508 int n
= ALLOCNO_NUM_OBJECTS (a
);
2511 if (ALLOCNO_CAP_MEMBER (a
) != NULL
2512 || (hard_regno
= ALLOCNO_HARD_REGNO (a
)) < 0)
2514 nregs
= hard_regno_nregs (hard_regno
, ALLOCNO_MODE (a
));
2516 /* We allocated a single hard register. */
2519 /* We allocated multiple hard registers, and we will test
2520 conflicts in a granularity of single hard regs. */
2523 for (i
= 0; i
< n
; i
++)
2525 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2526 ira_object_t conflict_obj
;
2527 ira_object_conflict_iterator oci
;
2528 int this_regno
= hard_regno
;
2531 if (REG_WORDS_BIG_ENDIAN
)
2532 this_regno
+= n
- i
- 1;
2536 FOR_EACH_OBJECT_CONFLICT (obj
, conflict_obj
, oci
)
2538 ira_allocno_t conflict_a
= OBJECT_ALLOCNO (conflict_obj
);
2539 int conflict_hard_regno
= ALLOCNO_HARD_REGNO (conflict_a
);
2540 if (conflict_hard_regno
< 0)
2543 conflict_nregs
= hard_regno_nregs (conflict_hard_regno
,
2544 ALLOCNO_MODE (conflict_a
));
2546 if (ALLOCNO_NUM_OBJECTS (conflict_a
) > 1
2547 && conflict_nregs
== ALLOCNO_NUM_OBJECTS (conflict_a
))
2549 if (REG_WORDS_BIG_ENDIAN
)
2550 conflict_hard_regno
+= (ALLOCNO_NUM_OBJECTS (conflict_a
)
2551 - OBJECT_SUBWORD (conflict_obj
) - 1);
2553 conflict_hard_regno
+= OBJECT_SUBWORD (conflict_obj
);
2557 if ((conflict_hard_regno
<= this_regno
2558 && this_regno
< conflict_hard_regno
+ conflict_nregs
)
2559 || (this_regno
<= conflict_hard_regno
2560 && conflict_hard_regno
< this_regno
+ nregs
))
2562 fprintf (stderr
, "bad allocation for %d and %d\n",
2563 ALLOCNO_REGNO (a
), ALLOCNO_REGNO (conflict_a
));
2572 /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should
2573 be already calculated. */
2575 setup_reg_equiv_init (void)
2578 int max_regno
= max_reg_num ();
2580 for (i
= 0; i
< max_regno
; i
++)
2581 reg_equiv_init (i
) = ira_reg_equiv
[i
].init_insns
;
2584 /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS
2585 are insns which were generated for such movement. It is assumed
2586 that FROM_REGNO and TO_REGNO always have the same value at the
2587 point of any move containing such registers. This function is used
2588 to update equiv info for register shuffles on the region borders
2589 and for caller save/restore insns. */
2591 ira_update_equiv_info_by_shuffle_insn (int to_regno
, int from_regno
, rtx_insn
*insns
)
2596 if (! ira_reg_equiv
[from_regno
].defined_p
2597 && (! ira_reg_equiv
[to_regno
].defined_p
2598 || ((x
= ira_reg_equiv
[to_regno
].memory
) != NULL_RTX
2599 && ! MEM_READONLY_P (x
))))
2602 if (NEXT_INSN (insn
) != NULL_RTX
)
2604 if (! ira_reg_equiv
[to_regno
].defined_p
)
2606 ira_assert (ira_reg_equiv
[to_regno
].init_insns
== NULL_RTX
);
2609 ira_reg_equiv
[to_regno
].defined_p
= false;
2610 ira_reg_equiv
[to_regno
].memory
2611 = ira_reg_equiv
[to_regno
].constant
2612 = ira_reg_equiv
[to_regno
].invariant
2613 = ira_reg_equiv
[to_regno
].init_insns
= NULL
;
2614 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2615 fprintf (ira_dump_file
,
2616 " Invalidating equiv info for reg %d\n", to_regno
);
2619 /* It is possible that FROM_REGNO still has no equivalence because
2620 in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd
2621 insn was not processed yet. */
2622 if (ira_reg_equiv
[from_regno
].defined_p
)
2624 ira_reg_equiv
[to_regno
].defined_p
= true;
2625 if ((x
= ira_reg_equiv
[from_regno
].memory
) != NULL_RTX
)
2627 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
2628 && ira_reg_equiv
[from_regno
].constant
== NULL_RTX
);
2629 ira_assert (ira_reg_equiv
[to_regno
].memory
== NULL_RTX
2630 || rtx_equal_p (ira_reg_equiv
[to_regno
].memory
, x
));
2631 ira_reg_equiv
[to_regno
].memory
= x
;
2632 if (! MEM_READONLY_P (x
))
2633 /* We don't add the insn to insn init list because memory
2634 equivalence is just to say what memory is better to use
2635 when the pseudo is spilled. */
2638 else if ((x
= ira_reg_equiv
[from_regno
].constant
) != NULL_RTX
)
2640 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
);
2641 ira_assert (ira_reg_equiv
[to_regno
].constant
== NULL_RTX
2642 || rtx_equal_p (ira_reg_equiv
[to_regno
].constant
, x
));
2643 ira_reg_equiv
[to_regno
].constant
= x
;
2647 x
= ira_reg_equiv
[from_regno
].invariant
;
2648 ira_assert (x
!= NULL_RTX
);
2649 ira_assert (ira_reg_equiv
[to_regno
].invariant
== NULL_RTX
2650 || rtx_equal_p (ira_reg_equiv
[to_regno
].invariant
, x
));
2651 ira_reg_equiv
[to_regno
].invariant
= x
;
2653 if (find_reg_note (insn
, REG_EQUIV
, x
) == NULL_RTX
)
2655 note
= set_unique_reg_note (insn
, REG_EQUIV
, copy_rtx (x
));
2656 gcc_assert (note
!= NULL_RTX
);
2657 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2659 fprintf (ira_dump_file
,
2660 " Adding equiv note to insn %u for reg %d ",
2661 INSN_UID (insn
), to_regno
);
2662 dump_value_slim (ira_dump_file
, x
, 1);
2663 fprintf (ira_dump_file
, "\n");
2667 ira_reg_equiv
[to_regno
].init_insns
2668 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
2669 ira_reg_equiv
[to_regno
].init_insns
);
2670 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2671 fprintf (ira_dump_file
,
2672 " Adding equiv init move insn %u to reg %d\n",
2673 INSN_UID (insn
), to_regno
);
2676 /* Fix values of array REG_EQUIV_INIT after live range splitting done
2679 fix_reg_equiv_init (void)
2681 int max_regno
= max_reg_num ();
2682 int i
, new_regno
, max
;
2684 rtx_insn_list
*x
, *next
, *prev
;
2687 if (max_regno_before_ira
< max_regno
)
2689 max
= vec_safe_length (reg_equivs
);
2691 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; i
++)
2692 for (prev
= NULL
, x
= reg_equiv_init (i
);
2698 set
= single_set (insn
);
2699 ira_assert (set
!= NULL_RTX
2700 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))));
2701 if (REG_P (SET_DEST (set
))
2702 && ((int) REGNO (SET_DEST (set
)) == i
2703 || (int) ORIGINAL_REGNO (SET_DEST (set
)) == i
))
2704 new_regno
= REGNO (SET_DEST (set
));
2705 else if (REG_P (SET_SRC (set
))
2706 && ((int) REGNO (SET_SRC (set
)) == i
2707 || (int) ORIGINAL_REGNO (SET_SRC (set
)) == i
))
2708 new_regno
= REGNO (SET_SRC (set
));
2715 /* Remove the wrong list element. */
2716 if (prev
== NULL_RTX
)
2717 reg_equiv_init (i
) = next
;
2719 XEXP (prev
, 1) = next
;
2720 XEXP (x
, 1) = reg_equiv_init (new_regno
);
2721 reg_equiv_init (new_regno
) = x
;
2727 #ifdef ENABLE_IRA_CHECKING
2728 /* Print redundant memory-memory copies. */
2730 print_redundant_copies (void)
2734 ira_copy_t cp
, next_cp
;
2735 ira_allocno_iterator ai
;
2737 FOR_EACH_ALLOCNO (a
, ai
)
2739 if (ALLOCNO_CAP_MEMBER (a
) != NULL
)
2742 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2743 if (hard_regno
>= 0)
2745 for (cp
= ALLOCNO_COPIES (a
); cp
!= NULL
; cp
= next_cp
)
2747 next_cp
= cp
->next_first_allocno_copy
;
2750 next_cp
= cp
->next_second_allocno_copy
;
2751 if (internal_flag_ira_verbose
> 4 && ira_dump_file
!= NULL
2752 && cp
->insn
!= NULL_RTX
2753 && ALLOCNO_HARD_REGNO (cp
->first
) == hard_regno
)
2754 fprintf (ira_dump_file
,
2755 " Redundant move from %d(freq %d):%d\n",
2756 INSN_UID (cp
->insn
), cp
->freq
, hard_regno
);
2762 /* Setup preferred and alternative classes for new pseudo-registers
2763 created by IRA starting with START. */
2765 setup_preferred_alternate_classes_for_new_pseudos (int start
)
2768 int max_regno
= max_reg_num ();
2770 for (i
= start
; i
< max_regno
; i
++)
2772 old_regno
= ORIGINAL_REGNO (regno_reg_rtx
[i
]);
2773 ira_assert (i
!= old_regno
);
2774 setup_reg_classes (i
, reg_preferred_class (old_regno
),
2775 reg_alternate_class (old_regno
),
2776 reg_allocno_class (old_regno
));
2777 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
2778 fprintf (ira_dump_file
,
2779 " New r%d: setting preferred %s, alternative %s\n",
2780 i
, reg_class_names
[reg_preferred_class (old_regno
)],
2781 reg_class_names
[reg_alternate_class (old_regno
)]);
2786 /* The number of entries allocated in reg_info. */
2787 static int allocated_reg_info_size
;
2789 /* Regional allocation can create new pseudo-registers. This function
2790 expands some arrays for pseudo-registers. */
2792 expand_reg_info (void)
2795 int size
= max_reg_num ();
2798 for (i
= allocated_reg_info_size
; i
< size
; i
++)
2799 setup_reg_classes (i
, GENERAL_REGS
, ALL_REGS
, GENERAL_REGS
);
2800 setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size
);
2801 allocated_reg_info_size
= size
;
2804 /* Return TRUE if there is too high register pressure in the function.
2805 It is used to decide when stack slot sharing is worth to do. */
2807 too_high_register_pressure_p (void)
2810 enum reg_class pclass
;
2812 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
2814 pclass
= ira_pressure_classes
[i
];
2815 if (ira_loop_tree_root
->reg_pressure
[pclass
] > 10000)
2823 /* Indicate that hard register number FROM was eliminated and replaced with
2824 an offset from hard register number TO. The status of hard registers live
2825 at the start of a basic block is updated by replacing a use of FROM with
2829 mark_elimination (int from
, int to
)
2834 FOR_EACH_BB_FN (bb
, cfun
)
2837 if (bitmap_bit_p (r
, from
))
2839 bitmap_clear_bit (r
, from
);
2840 bitmap_set_bit (r
, to
);
2844 r
= DF_LIVE_IN (bb
);
2845 if (bitmap_bit_p (r
, from
))
2847 bitmap_clear_bit (r
, from
);
2848 bitmap_set_bit (r
, to
);
2855 /* The length of the following array. */
2856 int ira_reg_equiv_len
;
2858 /* Info about equiv. info for each register. */
2859 struct ira_reg_equiv_s
*ira_reg_equiv
;
2861 /* Expand ira_reg_equiv if necessary. */
2863 ira_expand_reg_equiv (void)
2865 int old
= ira_reg_equiv_len
;
2867 if (ira_reg_equiv_len
> max_reg_num ())
2869 ira_reg_equiv_len
= max_reg_num () * 3 / 2 + 1;
2871 = (struct ira_reg_equiv_s
*) xrealloc (ira_reg_equiv
,
2873 * sizeof (struct ira_reg_equiv_s
));
2874 gcc_assert (old
< ira_reg_equiv_len
);
2875 memset (ira_reg_equiv
+ old
, 0,
2876 sizeof (struct ira_reg_equiv_s
) * (ira_reg_equiv_len
- old
));
2880 init_reg_equiv (void)
2882 ira_reg_equiv_len
= 0;
2883 ira_reg_equiv
= NULL
;
2884 ira_expand_reg_equiv ();
2888 finish_reg_equiv (void)
2890 free (ira_reg_equiv
);
2897 /* Set when a REG_EQUIV note is found or created. Use to
2898 keep track of what memory accesses might be created later,
2903 /* The list of each instruction which initializes this register.
2905 NULL indicates we know nothing about this register's equivalence
2908 An INSN_LIST with a NULL insn indicates this pseudo is already
2909 known to not have a valid equivalence. */
2910 rtx_insn_list
*init_insns
;
2912 /* Loop depth is used to recognize equivalences which appear
2913 to be present within the same loop (or in an inner loop). */
2915 /* Nonzero if this had a preexisting REG_EQUIV note. */
2916 unsigned char is_arg_equivalence
: 1;
2917 /* Set when an attempt should be made to replace a register
2918 with the associated src_p entry. */
2919 unsigned char replace
: 1;
2920 /* Set if this register has no known equivalence. */
2921 unsigned char no_equiv
: 1;
2922 /* Set if this register is mentioned in a paradoxical subreg. */
2923 unsigned char pdx_subregs
: 1;
2926 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
2927 structure for that register. */
2928 static struct equivalence
*reg_equiv
;
2930 /* Used for communication between the following two functions. */
2931 struct equiv_mem_data
2933 /* A MEM that we wish to ensure remains unchanged. */
2936 /* Set true if EQUIV_MEM is modified. */
2937 bool equiv_mem_modified
;
2940 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
2941 Called via note_stores. */
2943 validate_equiv_mem_from_store (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
,
2946 struct equiv_mem_data
*info
= (struct equiv_mem_data
*) data
;
2949 && reg_overlap_mentioned_p (dest
, info
->equiv_mem
))
2951 && anti_dependence (info
->equiv_mem
, dest
)))
2952 info
->equiv_mem_modified
= true;
2955 enum valid_equiv
{ valid_none
, valid_combine
, valid_reload
};
2957 /* Verify that no store between START and the death of REG invalidates
2958 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
2959 by storing into an overlapping memory location, or with a non-const
2962 Return VALID_RELOAD if MEMREF remains valid for both reload and
2963 combine_and_move insns, VALID_COMBINE if only valid for
2964 combine_and_move_insns, and VALID_NONE otherwise. */
2965 static enum valid_equiv
2966 validate_equiv_mem (rtx_insn
*start
, rtx reg
, rtx memref
)
2970 struct equiv_mem_data info
= { memref
, false };
2971 enum valid_equiv ret
= valid_reload
;
2973 /* If the memory reference has side effects or is volatile, it isn't a
2974 valid equivalence. */
2975 if (side_effects_p (memref
))
2978 for (insn
= start
; insn
; insn
= NEXT_INSN (insn
))
2983 if (find_reg_note (insn
, REG_DEAD
, reg
))
2988 /* We can combine a reg def from one insn into a reg use in
2989 another over a call if the memory is readonly or the call
2990 const/pure. However, we can't set reg_equiv notes up for
2991 reload over any call. The problem is the equivalent form
2992 may reference a pseudo which gets assigned a call
2993 clobbered hard reg. When we later replace REG with its
2994 equivalent form, the value in the call-clobbered reg has
2995 been changed and all hell breaks loose. */
2996 ret
= valid_combine
;
2997 if (!MEM_READONLY_P (memref
)
2998 && !RTL_CONST_OR_PURE_CALL_P (insn
))
3002 note_stores (insn
, validate_equiv_mem_from_store
, &info
);
3003 if (info
.equiv_mem_modified
)
3006 /* If a register mentioned in MEMREF is modified via an
3007 auto-increment, we lose the equivalence. Do the same if one
3008 dies; although we could extend the life, it doesn't seem worth
3011 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3012 if ((REG_NOTE_KIND (note
) == REG_INC
3013 || REG_NOTE_KIND (note
) == REG_DEAD
)
3014 && REG_P (XEXP (note
, 0))
3015 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
3022 /* Returns zero if X is known to be invariant. */
3024 equiv_init_varies_p (rtx x
)
3026 RTX_CODE code
= GET_CODE (x
);
3033 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
3042 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
3045 if (MEM_VOLATILE_P (x
))
3054 fmt
= GET_RTX_FORMAT (code
);
3055 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3058 if (equiv_init_varies_p (XEXP (x
, i
)))
3061 else if (fmt
[i
] == 'E')
3064 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3065 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
3072 /* Returns nonzero if X (used to initialize register REGNO) is movable.
3073 X is only movable if the registers it uses have equivalent initializations
3074 which appear to be within the same loop (or in an inner loop) and movable
3075 or if they are not candidates for local_alloc and don't vary. */
3077 equiv_init_movable_p (rtx x
, int regno
)
3081 enum rtx_code code
= GET_CODE (x
);
3086 return equiv_init_movable_p (SET_SRC (x
), regno
);
3100 return ((reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
3101 && reg_equiv
[REGNO (x
)].replace
)
3102 || (REG_BASIC_BLOCK (REGNO (x
)) < NUM_FIXED_BLOCKS
3103 && ! rtx_varies_p (x
, 0)));
3105 case UNSPEC_VOLATILE
:
3109 if (MEM_VOLATILE_P (x
))
3118 fmt
= GET_RTX_FORMAT (code
);
3119 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3123 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
3127 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3128 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
3136 static bool memref_referenced_p (rtx memref
, rtx x
, bool read_p
);
3138 /* Auxiliary function for memref_referenced_p. Process setting X for
3141 process_set_for_memref_referenced_p (rtx memref
, rtx x
)
3143 /* If we are setting a MEM, it doesn't count (its address does), but any
3144 other SET_DEST that has a MEM in it is referencing the MEM. */
3147 if (memref_referenced_p (memref
, XEXP (x
, 0), true))
3150 else if (memref_referenced_p (memref
, x
, false))
3156 /* TRUE if X references a memory location (as a read if READ_P) that
3157 would be affected by a store to MEMREF. */
3159 memref_referenced_p (rtx memref
, rtx x
, bool read_p
)
3163 enum rtx_code code
= GET_CODE (x
);
3177 return (reg_equiv
[REGNO (x
)].replacement
3178 && memref_referenced_p (memref
,
3179 reg_equiv
[REGNO (x
)].replacement
, read_p
));
3182 /* Memory X might have another effective type than MEMREF. */
3183 if (read_p
|| true_dependence (memref
, VOIDmode
, x
))
3188 if (process_set_for_memref_referenced_p (memref
, SET_DEST (x
)))
3191 return memref_referenced_p (memref
, SET_SRC (x
), true);
3194 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3203 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3206 return memref_referenced_p (memref
, XEXP (x
, 0), true);
3210 /* op0 = op0 + op1 */
3211 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3214 if (memref_referenced_p (memref
, XEXP (x
, 0), true))
3217 return memref_referenced_p (memref
, XEXP (x
, 1), true);
3223 fmt
= GET_RTX_FORMAT (code
);
3224 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3228 if (memref_referenced_p (memref
, XEXP (x
, i
), read_p
))
3232 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3233 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
), read_p
))
3241 /* TRUE if some insn in the range (START, END] references a memory location
3242 that would be affected by a store to MEMREF.
3244 Callers should not call this routine if START is after END in the
3248 memref_used_between_p (rtx memref
, rtx_insn
*start
, rtx_insn
*end
)
3252 for (insn
= NEXT_INSN (start
);
3253 insn
&& insn
!= NEXT_INSN (end
);
3254 insn
= NEXT_INSN (insn
))
3256 if (!NONDEBUG_INSN_P (insn
))
3259 if (memref_referenced_p (memref
, PATTERN (insn
), false))
3262 /* Nonconst functions may access memory. */
3263 if (CALL_P (insn
) && (! RTL_CONST_CALL_P (insn
)))
3267 gcc_assert (insn
== NEXT_INSN (end
));
3271 /* Mark REG as having no known equivalence.
3272 Some instructions might have been processed before and furnished
3273 with REG_EQUIV notes for this register; these notes will have to be
3275 STORE is the piece of RTL that does the non-constant / conflicting
3276 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
3277 but needs to be there because this function is called from note_stores. */
3279 no_equiv (rtx reg
, const_rtx store ATTRIBUTE_UNUSED
,
3280 void *data ATTRIBUTE_UNUSED
)
3283 rtx_insn_list
*list
;
3287 regno
= REGNO (reg
);
3288 reg_equiv
[regno
].no_equiv
= 1;
3289 list
= reg_equiv
[regno
].init_insns
;
3290 if (list
&& list
->insn () == NULL
)
3292 reg_equiv
[regno
].init_insns
= gen_rtx_INSN_LIST (VOIDmode
, NULL_RTX
, NULL
);
3293 reg_equiv
[regno
].replacement
= NULL_RTX
;
3294 /* This doesn't matter for equivalences made for argument registers, we
3295 should keep their initialization insns. */
3296 if (reg_equiv
[regno
].is_arg_equivalence
)
3298 ira_reg_equiv
[regno
].defined_p
= false;
3299 ira_reg_equiv
[regno
].init_insns
= NULL
;
3300 for (; list
; list
= list
->next ())
3302 rtx_insn
*insn
= list
->insn ();
3303 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
3307 /* Check whether the SUBREG is a paradoxical subreg and set the result
3311 set_paradoxical_subreg (rtx_insn
*insn
)
3313 subrtx_iterator::array_type array
;
3314 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
3316 const_rtx subreg
= *iter
;
3317 if (GET_CODE (subreg
) == SUBREG
)
3319 const_rtx reg
= SUBREG_REG (subreg
);
3320 if (REG_P (reg
) && paradoxical_subreg_p (subreg
))
3321 reg_equiv
[REGNO (reg
)].pdx_subregs
= true;
3326 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the
3327 equivalent replacement. */
3330 adjust_cleared_regs (rtx loc
, const_rtx old_rtx ATTRIBUTE_UNUSED
, void *data
)
3334 bitmap cleared_regs
= (bitmap
) data
;
3335 if (bitmap_bit_p (cleared_regs
, REGNO (loc
)))
3336 return simplify_replace_fn_rtx (copy_rtx (*reg_equiv
[REGNO (loc
)].src_p
),
3337 NULL_RTX
, adjust_cleared_regs
, data
);
3342 /* Given register REGNO is set only once, return true if the defining
3343 insn dominates all uses. */
3346 def_dominates_uses (int regno
)
3348 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3350 struct df_insn_info
*def_info
= DF_REF_INSN_INFO (def
);
3351 /* If this is an artificial def (eh handler regs, hard frame pointer
3352 for non-local goto, regs defined on function entry) then def_info
3353 is NULL and the reg is always live before any use. We might
3354 reasonably return true in that case, but since the only call
3355 of this function is currently here in ira.c when we are looking
3356 at a defining insn we can't have an artificial def as that would
3357 bump DF_REG_DEF_COUNT. */
3358 gcc_assert (DF_REG_DEF_COUNT (regno
) == 1 && def_info
!= NULL
);
3360 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3361 basic_block def_bb
= BLOCK_FOR_INSN (def_insn
);
3363 for (df_ref use
= DF_REG_USE_CHAIN (regno
);
3365 use
= DF_REF_NEXT_REG (use
))
3367 struct df_insn_info
*use_info
= DF_REF_INSN_INFO (use
);
3368 /* Only check real uses, not artificial ones. */
3371 rtx_insn
*use_insn
= DF_REF_INSN (use
);
3372 if (!DEBUG_INSN_P (use_insn
))
3374 basic_block use_bb
= BLOCK_FOR_INSN (use_insn
);
3375 if (use_bb
!= def_bb
3376 ? !dominated_by_p (CDI_DOMINATORS
, use_bb
, def_bb
)
3377 : DF_INSN_INFO_LUID (use_info
) < DF_INSN_INFO_LUID (def_info
))
3385 /* Scan the instructions before update_equiv_regs. Record which registers
3386 are referenced as paradoxical subregs. Also check for cases in which
3387 the current function needs to save a register that one of its call
3388 instructions clobbers.
3390 These things are logically unrelated, but it's more efficient to do
3394 update_equiv_regs_prescan (void)
3398 function_abi_aggregator callee_abis
;
3400 FOR_EACH_BB_FN (bb
, cfun
)
3401 FOR_BB_INSNS (bb
, insn
)
3402 if (NONDEBUG_INSN_P (insn
))
3404 set_paradoxical_subreg (insn
);
3406 callee_abis
.note_callee_abi (insn_callee_abi (insn
));
3409 HARD_REG_SET extra_caller_saves
= callee_abis
.caller_save_regs (*crtl
->abi
);
3410 if (!hard_reg_set_empty_p (extra_caller_saves
))
3411 for (unsigned int regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; ++regno
)
3412 if (TEST_HARD_REG_BIT (extra_caller_saves
, regno
))
3413 df_set_regs_ever_live (regno
, true);
3416 /* Find registers that are equivalent to a single value throughout the
3417 compilation (either because they can be referenced in memory or are
3418 set once from a single constant). Lower their priority for a
3421 If such a register is only referenced once, try substituting its
3422 value into the using insn. If it succeeds, we can eliminate the
3423 register completely.
3425 Initialize init_insns in ira_reg_equiv array. */
3427 update_equiv_regs (void)
3432 /* Scan the insns and find which registers have equivalences. Do this
3433 in a separate scan of the insns because (due to -fcse-follow-jumps)
3434 a register can be set below its use. */
3435 bitmap setjmp_crosses
= regstat_get_setjmp_crosses ();
3436 FOR_EACH_BB_FN (bb
, cfun
)
3438 int loop_depth
= bb_loop_depth (bb
);
3440 for (insn
= BB_HEAD (bb
);
3441 insn
!= NEXT_INSN (BB_END (bb
));
3442 insn
= NEXT_INSN (insn
))
3449 if (! INSN_P (insn
))
3452 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3453 if (REG_NOTE_KIND (note
) == REG_INC
)
3454 no_equiv (XEXP (note
, 0), note
, NULL
);
3456 set
= single_set (insn
);
3458 /* If this insn contains more (or less) than a single SET,
3459 only mark all destinations as having no known equivalence. */
3461 || side_effects_p (SET_SRC (set
)))
3463 note_pattern_stores (PATTERN (insn
), no_equiv
, NULL
);
3466 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
3470 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
3472 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
3474 note_pattern_stores (part
, no_equiv
, NULL
);
3478 dest
= SET_DEST (set
);
3479 src
= SET_SRC (set
);
3481 /* See if this is setting up the equivalence between an argument
3482 register and its stack slot. */
3483 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3486 gcc_assert (REG_P (dest
));
3487 regno
= REGNO (dest
);
3489 /* Note that we don't want to clear init_insns in
3490 ira_reg_equiv even if there are multiple sets of this
3492 reg_equiv
[regno
].is_arg_equivalence
= 1;
3494 /* The insn result can have equivalence memory although
3495 the equivalence is not set up by the insn. We add
3496 this insn to init insns as it is a flag for now that
3497 regno has an equivalence. We will remove the insn
3498 from init insn list later. */
3499 if (rtx_equal_p (src
, XEXP (note
, 0)) || MEM_P (XEXP (note
, 0)))
3500 ira_reg_equiv
[regno
].init_insns
3501 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3502 ira_reg_equiv
[regno
].init_insns
);
3504 /* Continue normally in case this is a candidate for
3511 /* We only handle the case of a pseudo register being set
3512 once, or always to the same value. */
3513 /* ??? The mn10200 port breaks if we add equivalences for
3514 values that need an ADDRESS_REGS register and set them equivalent
3515 to a MEM of a pseudo. The actual problem is in the over-conservative
3516 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
3517 calculate_needs, but we traditionally work around this problem
3518 here by rejecting equivalences when the destination is in a register
3519 that's likely spilled. This is fragile, of course, since the
3520 preferred class of a pseudo depends on all instructions that set
3524 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
3525 || (reg_equiv
[regno
].init_insns
3526 && reg_equiv
[regno
].init_insns
->insn () == NULL
)
3527 || (targetm
.class_likely_spilled_p (reg_preferred_class (regno
))
3528 && MEM_P (src
) && ! reg_equiv
[regno
].is_arg_equivalence
))
3530 /* This might be setting a SUBREG of a pseudo, a pseudo that is
3531 also set somewhere else to a constant. */
3532 note_pattern_stores (set
, no_equiv
, NULL
);
3536 /* Don't set reg mentioned in a paradoxical subreg
3537 equivalent to a mem. */
3538 if (MEM_P (src
) && reg_equiv
[regno
].pdx_subregs
)
3540 note_pattern_stores (set
, no_equiv
, NULL
);
3544 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
3546 /* cse sometimes generates function invariants, but doesn't put a
3547 REG_EQUAL note on the insn. Since this note would be redundant,
3548 there's no point creating it earlier than here. */
3549 if (! note
&& ! rtx_varies_p (src
, 0))
3550 note
= set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
3552 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
3553 since it represents a function call. */
3554 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
3557 if (DF_REG_DEF_COUNT (regno
) != 1)
3559 bool equal_p
= true;
3560 rtx_insn_list
*list
;
3562 /* If we have already processed this pseudo and determined it
3563 cannot have an equivalence, then honor that decision. */
3564 if (reg_equiv
[regno
].no_equiv
)
3568 || rtx_varies_p (XEXP (note
, 0), 0)
3569 || (reg_equiv
[regno
].replacement
3570 && ! rtx_equal_p (XEXP (note
, 0),
3571 reg_equiv
[regno
].replacement
)))
3573 no_equiv (dest
, set
, NULL
);
3577 list
= reg_equiv
[regno
].init_insns
;
3578 for (; list
; list
= list
->next ())
3583 insn_tmp
= list
->insn ();
3584 note_tmp
= find_reg_note (insn_tmp
, REG_EQUAL
, NULL_RTX
);
3585 gcc_assert (note_tmp
);
3586 if (! rtx_equal_p (XEXP (note
, 0), XEXP (note_tmp
, 0)))
3595 no_equiv (dest
, set
, NULL
);
3600 /* Record this insn as initializing this register. */
3601 reg_equiv
[regno
].init_insns
3602 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
3604 /* If this register is known to be equal to a constant, record that
3605 it is always equivalent to the constant.
3606 Note that it is possible to have a register use before
3607 the def in loops (see gcc.c-torture/execute/pr79286.c)
3608 where the reg is undefined on first use. If the def insn
3609 won't trap we can use it as an equivalence, effectively
3610 choosing the "undefined" value for the reg to be the
3611 same as the value set by the def. */
3612 if (DF_REG_DEF_COUNT (regno
) == 1
3614 && !rtx_varies_p (XEXP (note
, 0), 0)
3615 && (!may_trap_or_fault_p (XEXP (note
, 0))
3616 || def_dominates_uses (regno
)))
3618 rtx note_value
= XEXP (note
, 0);
3619 remove_note (insn
, note
);
3620 set_unique_reg_note (insn
, REG_EQUIV
, note_value
);
3623 /* If this insn introduces a "constant" register, decrease the priority
3624 of that register. Record this insn if the register is only used once
3625 more and the equivalence value is the same as our source.
3627 The latter condition is checked for two reasons: First, it is an
3628 indication that it may be more efficient to actually emit the insn
3629 as written (if no registers are available, reload will substitute
3630 the equivalence). Secondly, it avoids problems with any registers
3631 dying in this insn whose death notes would be missed.
3633 If we don't have a REG_EQUIV note, see if this insn is loading
3634 a register used only in one basic block from a MEM. If so, and the
3635 MEM remains unchanged for the life of the register, add a REG_EQUIV
3637 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3639 rtx replacement
= NULL_RTX
;
3641 replacement
= XEXP (note
, 0);
3642 else if (REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3643 && MEM_P (SET_SRC (set
)))
3645 enum valid_equiv validity
;
3646 validity
= validate_equiv_mem (insn
, dest
, SET_SRC (set
));
3647 if (validity
!= valid_none
)
3649 replacement
= copy_rtx (SET_SRC (set
));
3650 if (validity
== valid_reload
)
3651 note
= set_unique_reg_note (insn
, REG_EQUIV
, replacement
);
3655 /* If we haven't done so, record for reload that this is an
3656 equivalencing insn. */
3657 if (note
&& !reg_equiv
[regno
].is_arg_equivalence
)
3658 ira_reg_equiv
[regno
].init_insns
3659 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3660 ira_reg_equiv
[regno
].init_insns
);
3664 reg_equiv
[regno
].replacement
= replacement
;
3665 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
3666 reg_equiv
[regno
].loop_depth
= (short) loop_depth
;
3668 /* Don't mess with things live during setjmp. */
3669 if (optimize
&& !bitmap_bit_p (setjmp_crosses
, regno
))
3671 /* If the register is referenced exactly twice, meaning it is
3672 set once and used once, indicate that the reference may be
3673 replaced by the equivalence we computed above. Do this
3674 even if the register is only used in one block so that
3675 dependencies can be handled where the last register is
3676 used in a different block (i.e. HIGH / LO_SUM sequences)
3677 and to reduce the number of registers alive across
3680 if (REG_N_REFS (regno
) == 2
3681 && (rtx_equal_p (replacement
, src
)
3682 || ! equiv_init_varies_p (src
))
3683 && NONJUMP_INSN_P (insn
)
3684 && equiv_init_movable_p (PATTERN (insn
), regno
))
3685 reg_equiv
[regno
].replace
= 1;
3692 /* For insns that set a MEM to the contents of a REG that is only used
3693 in a single basic block, see if the register is always equivalent
3694 to that memory location and if moving the store from INSN to the
3695 insn that sets REG is safe. If so, put a REG_EQUIV note on the
3696 initializing insn. */
3698 add_store_equivs (void)
3700 auto_bitmap seen_insns
;
3702 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3706 rtx_insn
*init_insn
;
3708 bitmap_set_bit (seen_insns
, INSN_UID (insn
));
3710 if (! INSN_P (insn
))
3713 set
= single_set (insn
);
3717 dest
= SET_DEST (set
);
3718 src
= SET_SRC (set
);
3720 /* Don't add a REG_EQUIV note if the insn already has one. The existing
3721 REG_EQUIV is likely more useful than the one we are adding. */
3722 if (MEM_P (dest
) && REG_P (src
)
3723 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
3724 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3725 && DF_REG_DEF_COUNT (regno
) == 1
3726 && ! reg_equiv
[regno
].pdx_subregs
3727 && reg_equiv
[regno
].init_insns
!= NULL
3728 && (init_insn
= reg_equiv
[regno
].init_insns
->insn ()) != 0
3729 && bitmap_bit_p (seen_insns
, INSN_UID (init_insn
))
3730 && ! find_reg_note (init_insn
, REG_EQUIV
, NULL_RTX
)
3731 && validate_equiv_mem (init_insn
, src
, dest
) == valid_reload
3732 && ! memref_used_between_p (dest
, init_insn
, insn
)
3733 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
3735 && set_unique_reg_note (init_insn
, REG_EQUIV
, copy_rtx (dest
)))
3737 /* This insn makes the equivalence, not the one initializing
3739 ira_reg_equiv
[regno
].init_insns
3740 = gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
);
3741 df_notes_rescan (init_insn
);
3744 "Adding REG_EQUIV to insn %d for source of insn %d\n",
3745 INSN_UID (init_insn
),
3751 /* Scan all regs killed in an insn to see if any of them are registers
3752 only used that once. If so, see if we can replace the reference
3753 with the equivalent form. If we can, delete the initializing
3754 reference and this register will go away. If we can't replace the
3755 reference, and the initializing reference is within the same loop
3756 (or in an inner loop), then move the register initialization just
3757 before the use, so that they are in the same basic block. */
3759 combine_and_move_insns (void)
3761 auto_bitmap cleared_regs
;
3762 int max
= max_reg_num ();
3764 for (int regno
= FIRST_PSEUDO_REGISTER
; regno
< max
; regno
++)
3766 if (!reg_equiv
[regno
].replace
)
3769 rtx_insn
*use_insn
= 0;
3770 for (df_ref use
= DF_REG_USE_CHAIN (regno
);
3772 use
= DF_REF_NEXT_REG (use
))
3773 if (DF_REF_INSN_INFO (use
))
3775 if (DEBUG_INSN_P (DF_REF_INSN (use
)))
3777 gcc_assert (!use_insn
);
3778 use_insn
= DF_REF_INSN (use
);
3780 gcc_assert (use_insn
);
3782 /* Don't substitute into jumps. indirect_jump_optimize does
3783 this for anything we are prepared to handle. */
3784 if (JUMP_P (use_insn
))
3787 /* Also don't substitute into a conditional trap insn -- it can become
3788 an unconditional trap, and that is a flow control insn. */
3789 if (GET_CODE (PATTERN (use_insn
)) == TRAP_IF
)
3792 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3793 gcc_assert (DF_REG_DEF_COUNT (regno
) == 1 && DF_REF_INSN_INFO (def
));
3794 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3796 /* We may not move instructions that can throw, since that
3797 changes basic block boundaries and we are not prepared to
3798 adjust the CFG to match. */
3799 if (can_throw_internal (def_insn
))
3802 /* Instructions with multiple sets can only be moved if DF analysis is
3803 performed for all of the registers set. See PR91052. */
3804 if (multiple_sets (def_insn
))
3807 basic_block use_bb
= BLOCK_FOR_INSN (use_insn
);
3808 basic_block def_bb
= BLOCK_FOR_INSN (def_insn
);
3809 if (bb_loop_depth (use_bb
) > bb_loop_depth (def_bb
))
3812 if (asm_noperands (PATTERN (def_insn
)) < 0
3813 && validate_replace_rtx (regno_reg_rtx
[regno
],
3814 *reg_equiv
[regno
].src_p
, use_insn
))
3817 /* Append the REG_DEAD notes from def_insn. */
3818 for (rtx
*p
= ®_NOTES (def_insn
); (link
= *p
) != 0; )
3820 if (REG_NOTE_KIND (XEXP (link
, 0)) == REG_DEAD
)
3822 *p
= XEXP (link
, 1);
3823 XEXP (link
, 1) = REG_NOTES (use_insn
);
3824 REG_NOTES (use_insn
) = link
;
3827 p
= &XEXP (link
, 1);
3830 remove_death (regno
, use_insn
);
3831 SET_REG_N_REFS (regno
, 0);
3832 REG_FREQ (regno
) = 0;
3834 FOR_EACH_INSN_USE (use
, def_insn
)
3836 unsigned int use_regno
= DF_REF_REGNO (use
);
3837 if (!HARD_REGISTER_NUM_P (use_regno
))
3838 reg_equiv
[use_regno
].replace
= 0;
3841 delete_insn (def_insn
);
3843 reg_equiv
[regno
].init_insns
= NULL
;
3844 ira_reg_equiv
[regno
].init_insns
= NULL
;
3845 bitmap_set_bit (cleared_regs
, regno
);
3848 /* Move the initialization of the register to just before
3849 USE_INSN. Update the flow information. */
3850 else if (prev_nondebug_insn (use_insn
) != def_insn
)
3854 new_insn
= emit_insn_before (PATTERN (def_insn
), use_insn
);
3855 REG_NOTES (new_insn
) = REG_NOTES (def_insn
);
3856 REG_NOTES (def_insn
) = 0;
3857 /* Rescan it to process the notes. */
3858 df_insn_rescan (new_insn
);
3860 /* Make sure this insn is recognized before reload begins,
3861 otherwise eliminate_regs_in_insn will die. */
3862 INSN_CODE (new_insn
) = INSN_CODE (def_insn
);
3864 delete_insn (def_insn
);
3866 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
3868 REG_BASIC_BLOCK (regno
) = use_bb
->index
;
3869 REG_N_CALLS_CROSSED (regno
) = 0;
3871 if (use_insn
== BB_HEAD (use_bb
))
3872 BB_HEAD (use_bb
) = new_insn
;
3874 /* We know regno dies in use_insn, but inside a loop
3875 REG_DEAD notes might be missing when def_insn was in
3876 another basic block. However, when we move def_insn into
3877 this bb we'll definitely get a REG_DEAD note and reload
3878 will see the death. It's possible that update_equiv_regs
3879 set up an equivalence referencing regno for a reg set by
3880 use_insn, when regno was seen as non-local. Now that
3881 regno is local to this block, and dies, such an
3882 equivalence is invalid. */
3883 if (find_reg_note (use_insn
, REG_EQUIV
, regno_reg_rtx
[regno
]))
3885 rtx set
= single_set (use_insn
);
3886 if (set
&& REG_P (SET_DEST (set
)))
3887 no_equiv (SET_DEST (set
), set
, NULL
);
3890 ira_reg_equiv
[regno
].init_insns
3891 = gen_rtx_INSN_LIST (VOIDmode
, new_insn
, NULL_RTX
);
3892 bitmap_set_bit (cleared_regs
, regno
);
3896 if (!bitmap_empty_p (cleared_regs
))
3900 FOR_EACH_BB_FN (bb
, cfun
)
3902 bitmap_and_compl_into (DF_LR_IN (bb
), cleared_regs
);
3903 bitmap_and_compl_into (DF_LR_OUT (bb
), cleared_regs
);
3906 bitmap_and_compl_into (DF_LIVE_IN (bb
), cleared_regs
);
3907 bitmap_and_compl_into (DF_LIVE_OUT (bb
), cleared_regs
);
3910 /* Last pass - adjust debug insns referencing cleared regs. */
3911 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3912 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3913 if (DEBUG_BIND_INSN_P (insn
))
3915 rtx old_loc
= INSN_VAR_LOCATION_LOC (insn
);
3916 INSN_VAR_LOCATION_LOC (insn
)
3917 = simplify_replace_fn_rtx (old_loc
, NULL_RTX
,
3918 adjust_cleared_regs
,
3919 (void *) cleared_regs
);
3920 if (old_loc
!= INSN_VAR_LOCATION_LOC (insn
))
3921 df_insn_rescan (insn
);
3926 /* A pass over indirect jumps, converting simple cases to direct jumps.
3927 Combine does this optimization too, but only within a basic block. */
3929 indirect_jump_optimize (void)
3932 bool rebuild_p
= false;
3934 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3936 rtx_insn
*insn
= BB_END (bb
);
3938 || find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
3941 rtx x
= pc_set (insn
);
3942 if (!x
|| !REG_P (SET_SRC (x
)))
3945 int regno
= REGNO (SET_SRC (x
));
3946 if (DF_REG_DEF_COUNT (regno
) == 1)
3948 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3949 if (!DF_REF_IS_ARTIFICIAL (def
))
3951 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3953 rtx set
= single_set (def_insn
);
3954 if (set
&& GET_CODE (SET_SRC (set
)) == LABEL_REF
)
3955 lab
= SET_SRC (set
);
3958 rtx eqnote
= find_reg_note (def_insn
, REG_EQUAL
, NULL_RTX
);
3959 if (eqnote
&& GET_CODE (XEXP (eqnote
, 0)) == LABEL_REF
)
3960 lab
= XEXP (eqnote
, 0);
3962 if (lab
&& validate_replace_rtx (SET_SRC (x
), lab
, insn
))
3970 timevar_push (TV_JUMP
);
3971 rebuild_jump_labels (get_insns ());
3972 if (purge_all_dead_edges ())
3973 delete_unreachable_blocks ();
3974 timevar_pop (TV_JUMP
);
3978 /* Set up fields memory, constant, and invariant from init_insns in
3979 the structures of array ira_reg_equiv. */
3981 setup_reg_equiv (void)
3984 rtx_insn_list
*elem
, *prev_elem
, *next_elem
;
3988 for (i
= FIRST_PSEUDO_REGISTER
; i
< ira_reg_equiv_len
; i
++)
3989 for (prev_elem
= NULL
, elem
= ira_reg_equiv
[i
].init_insns
;
3991 prev_elem
= elem
, elem
= next_elem
)
3993 next_elem
= elem
->next ();
3994 insn
= elem
->insn ();
3995 set
= single_set (insn
);
3997 /* Init insns can set up equivalence when the reg is a destination or
3998 a source (in this case the destination is memory). */
3999 if (set
!= 0 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))))
4001 if ((x
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL
)
4004 if (REG_P (SET_DEST (set
))
4005 && REGNO (SET_DEST (set
)) == (unsigned int) i
4006 && ! rtx_equal_p (SET_SRC (set
), x
) && MEM_P (x
))
4008 /* This insn reporting the equivalence but
4009 actually not setting it. Remove it from the
4011 if (prev_elem
== NULL
)
4012 ira_reg_equiv
[i
].init_insns
= next_elem
;
4014 XEXP (prev_elem
, 1) = next_elem
;
4018 else if (REG_P (SET_DEST (set
))
4019 && REGNO (SET_DEST (set
)) == (unsigned int) i
)
4023 gcc_assert (REG_P (SET_SRC (set
))
4024 && REGNO (SET_SRC (set
)) == (unsigned int) i
);
4027 if (! function_invariant_p (x
)
4029 /* A function invariant is often CONSTANT_P but may
4030 include a register. We promise to only pass
4031 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
4032 || (CONSTANT_P (x
) && LEGITIMATE_PIC_OPERAND_P (x
)))
4034 /* It can happen that a REG_EQUIV note contains a MEM
4035 that is not a legitimate memory operand. As later
4036 stages of reload assume that all addresses found in
4037 the lra_regno_equiv_* arrays were originally
4038 legitimate, we ignore such REG_EQUIV notes. */
4039 if (memory_operand (x
, VOIDmode
))
4041 ira_reg_equiv
[i
].defined_p
= true;
4042 ira_reg_equiv
[i
].memory
= x
;
4045 else if (function_invariant_p (x
))
4049 mode
= GET_MODE (SET_DEST (set
));
4050 if (GET_CODE (x
) == PLUS
4051 || x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4052 /* This is PLUS of frame pointer and a constant,
4054 ira_reg_equiv
[i
].invariant
= x
;
4055 else if (targetm
.legitimate_constant_p (mode
, x
))
4056 ira_reg_equiv
[i
].constant
= x
;
4059 ira_reg_equiv
[i
].memory
= force_const_mem (mode
, x
);
4060 if (ira_reg_equiv
[i
].memory
== NULL_RTX
)
4062 ira_reg_equiv
[i
].defined_p
= false;
4063 ira_reg_equiv
[i
].init_insns
= NULL
;
4067 ira_reg_equiv
[i
].defined_p
= true;
4072 ira_reg_equiv
[i
].defined_p
= false;
4073 ira_reg_equiv
[i
].init_insns
= NULL
;
4080 /* Print chain C to FILE. */
4082 print_insn_chain (FILE *file
, class insn_chain
*c
)
4084 fprintf (file
, "insn=%d, ", INSN_UID (c
->insn
));
4085 bitmap_print (file
, &c
->live_throughout
, "live_throughout: ", ", ");
4086 bitmap_print (file
, &c
->dead_or_set
, "dead_or_set: ", "\n");
4090 /* Print all reload_insn_chains to FILE. */
4092 print_insn_chains (FILE *file
)
4094 class insn_chain
*c
;
4095 for (c
= reload_insn_chain
; c
; c
= c
->next
)
4096 print_insn_chain (file
, c
);
4099 /* Return true if pseudo REGNO should be added to set live_throughout
4100 or dead_or_set of the insn chains for reload consideration. */
4102 pseudo_for_reload_consideration_p (int regno
)
4104 /* Consider spilled pseudos too for IRA because they still have a
4105 chance to get hard-registers in the reload when IRA is used. */
4106 return (reg_renumber
[regno
] >= 0 || ira_conflicts_p
);
4109 /* Return true if we can track the individual bytes of subreg X.
4110 When returning true, set *OUTER_SIZE to the number of bytes in
4111 X itself, *INNER_SIZE to the number of bytes in the inner register
4112 and *START to the offset of the first byte. */
4114 get_subreg_tracking_sizes (rtx x
, HOST_WIDE_INT
*outer_size
,
4115 HOST_WIDE_INT
*inner_size
, HOST_WIDE_INT
*start
)
4117 rtx reg
= regno_reg_rtx
[REGNO (SUBREG_REG (x
))];
4118 return (GET_MODE_SIZE (GET_MODE (x
)).is_constant (outer_size
)
4119 && GET_MODE_SIZE (GET_MODE (reg
)).is_constant (inner_size
)
4120 && SUBREG_BYTE (x
).is_constant (start
));
4123 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] for
4124 a register with SIZE bytes, making the register live if INIT_VALUE. */
4126 init_live_subregs (bool init_value
, sbitmap
*live_subregs
,
4127 bitmap live_subregs_used
, int allocnum
, int size
)
4129 gcc_assert (size
> 0);
4131 /* Been there, done that. */
4132 if (bitmap_bit_p (live_subregs_used
, allocnum
))
4135 /* Create a new one. */
4136 if (live_subregs
[allocnum
] == NULL
)
4137 live_subregs
[allocnum
] = sbitmap_alloc (size
);
4139 /* If the entire reg was live before blasting into subregs, we need
4140 to init all of the subregs to ones else init to 0. */
4142 bitmap_ones (live_subregs
[allocnum
]);
4144 bitmap_clear (live_subregs
[allocnum
]);
4146 bitmap_set_bit (live_subregs_used
, allocnum
);
4149 /* Walk the insns of the current function and build reload_insn_chain,
4150 and record register life information. */
4152 build_insn_chain (void)
4155 class insn_chain
**p
= &reload_insn_chain
;
4157 class insn_chain
*c
= NULL
;
4158 class insn_chain
*next
= NULL
;
4159 auto_bitmap live_relevant_regs
;
4160 auto_bitmap elim_regset
;
4161 /* live_subregs is a vector used to keep accurate information about
4162 which hardregs are live in multiword pseudos. live_subregs and
4163 live_subregs_used are indexed by pseudo number. The live_subreg
4164 entry for a particular pseudo is only used if the corresponding
4165 element is non zero in live_subregs_used. The sbitmap size of
4166 live_subreg[allocno] is number of bytes that the pseudo can
4168 sbitmap
*live_subregs
= XCNEWVEC (sbitmap
, max_regno
);
4169 auto_bitmap live_subregs_used
;
4171 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4172 if (TEST_HARD_REG_BIT (eliminable_regset
, i
))
4173 bitmap_set_bit (elim_regset
, i
);
4174 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
4179 CLEAR_REG_SET (live_relevant_regs
);
4180 bitmap_clear (live_subregs_used
);
4182 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
), 0, i
, bi
)
4184 if (i
>= FIRST_PSEUDO_REGISTER
)
4186 bitmap_set_bit (live_relevant_regs
, i
);
4189 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
),
4190 FIRST_PSEUDO_REGISTER
, i
, bi
)
4192 if (pseudo_for_reload_consideration_p (i
))
4193 bitmap_set_bit (live_relevant_regs
, i
);
4196 FOR_BB_INSNS_REVERSE (bb
, insn
)
4198 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4200 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4203 c
= new_insn_chain ();
4210 c
->block
= bb
->index
;
4212 if (NONDEBUG_INSN_P (insn
))
4213 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4215 unsigned int regno
= DF_REF_REGNO (def
);
4217 /* Ignore may clobbers because these are generated
4218 from calls. However, every other kind of def is
4219 added to dead_or_set. */
4220 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
4222 if (regno
< FIRST_PSEUDO_REGISTER
)
4224 if (!fixed_regs
[regno
])
4225 bitmap_set_bit (&c
->dead_or_set
, regno
);
4227 else if (pseudo_for_reload_consideration_p (regno
))
4228 bitmap_set_bit (&c
->dead_or_set
, regno
);
4231 if ((regno
< FIRST_PSEUDO_REGISTER
4232 || reg_renumber
[regno
] >= 0
4234 && (!DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
)))
4236 rtx reg
= DF_REF_REG (def
);
4237 HOST_WIDE_INT outer_size
, inner_size
, start
;
4239 /* We can usually track the liveness of individual
4240 bytes within a subreg. The only exceptions are
4241 subregs wrapped in ZERO_EXTRACTs and subregs whose
4242 size is not known; in those cases we need to be
4243 conservative and treat the definition as a partial
4244 definition of the full register rather than a full
4245 definition of a specific part of the register. */
4246 if (GET_CODE (reg
) == SUBREG
4247 && !DF_REF_FLAGS_IS_SET (def
, DF_REF_ZERO_EXTRACT
)
4248 && get_subreg_tracking_sizes (reg
, &outer_size
,
4249 &inner_size
, &start
))
4251 HOST_WIDE_INT last
= start
+ outer_size
;
4254 (bitmap_bit_p (live_relevant_regs
, regno
),
4255 live_subregs
, live_subregs_used
, regno
,
4258 if (!DF_REF_FLAGS_IS_SET
4259 (def
, DF_REF_STRICT_LOW_PART
))
4261 /* Expand the range to cover entire words.
4262 Bytes added here are "don't care". */
4264 = start
/ UNITS_PER_WORD
* UNITS_PER_WORD
;
4265 last
= ((last
+ UNITS_PER_WORD
- 1)
4266 / UNITS_PER_WORD
* UNITS_PER_WORD
);
4269 /* Ignore the paradoxical bits. */
4270 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4271 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4273 while (start
< last
)
4275 bitmap_clear_bit (live_subregs
[regno
], start
);
4279 if (bitmap_empty_p (live_subregs
[regno
]))
4281 bitmap_clear_bit (live_subregs_used
, regno
);
4282 bitmap_clear_bit (live_relevant_regs
, regno
);
4285 /* Set live_relevant_regs here because
4286 that bit has to be true to get us to
4287 look at the live_subregs fields. */
4288 bitmap_set_bit (live_relevant_regs
, regno
);
4292 /* DF_REF_PARTIAL is generated for
4293 subregs, STRICT_LOW_PART, and
4294 ZERO_EXTRACT. We handle the subreg
4295 case above so here we have to keep from
4296 modeling the def as a killing def. */
4297 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
))
4299 bitmap_clear_bit (live_subregs_used
, regno
);
4300 bitmap_clear_bit (live_relevant_regs
, regno
);
4306 bitmap_and_compl_into (live_relevant_regs
, elim_regset
);
4307 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4309 if (NONDEBUG_INSN_P (insn
))
4310 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4312 unsigned int regno
= DF_REF_REGNO (use
);
4313 rtx reg
= DF_REF_REG (use
);
4315 /* DF_REF_READ_WRITE on a use means that this use
4316 is fabricated from a def that is a partial set
4317 to a multiword reg. Here, we only model the
4318 subreg case that is not wrapped in ZERO_EXTRACT
4319 precisely so we do not need to look at the
4321 if (DF_REF_FLAGS_IS_SET (use
, DF_REF_READ_WRITE
)
4322 && !DF_REF_FLAGS_IS_SET (use
, DF_REF_ZERO_EXTRACT
)
4323 && DF_REF_FLAGS_IS_SET (use
, DF_REF_SUBREG
))
4326 /* Add the last use of each var to dead_or_set. */
4327 if (!bitmap_bit_p (live_relevant_regs
, regno
))
4329 if (regno
< FIRST_PSEUDO_REGISTER
)
4331 if (!fixed_regs
[regno
])
4332 bitmap_set_bit (&c
->dead_or_set
, regno
);
4334 else if (pseudo_for_reload_consideration_p (regno
))
4335 bitmap_set_bit (&c
->dead_or_set
, regno
);
4338 if (regno
< FIRST_PSEUDO_REGISTER
4339 || pseudo_for_reload_consideration_p (regno
))
4341 HOST_WIDE_INT outer_size
, inner_size
, start
;
4342 if (GET_CODE (reg
) == SUBREG
4343 && !DF_REF_FLAGS_IS_SET (use
,
4345 | DF_REF_ZERO_EXTRACT
)
4346 && get_subreg_tracking_sizes (reg
, &outer_size
,
4347 &inner_size
, &start
))
4349 HOST_WIDE_INT last
= start
+ outer_size
;
4352 (bitmap_bit_p (live_relevant_regs
, regno
),
4353 live_subregs
, live_subregs_used
, regno
,
4356 /* Ignore the paradoxical bits. */
4357 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4358 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4360 while (start
< last
)
4362 bitmap_set_bit (live_subregs
[regno
], start
);
4367 /* Resetting the live_subregs_used is
4368 effectively saying do not use the subregs
4369 because we are reading the whole
4371 bitmap_clear_bit (live_subregs_used
, regno
);
4372 bitmap_set_bit (live_relevant_regs
, regno
);
4378 /* FIXME!! The following code is a disaster. Reload needs to see the
4379 labels and jump tables that are just hanging out in between
4380 the basic blocks. See pr33676. */
4381 insn
= BB_HEAD (bb
);
4383 /* Skip over the barriers and cruft. */
4384 while (insn
&& (BARRIER_P (insn
) || NOTE_P (insn
)
4385 || BLOCK_FOR_INSN (insn
) == bb
))
4386 insn
= PREV_INSN (insn
);
4388 /* While we add anything except barriers and notes, the focus is
4389 to get the labels and jump tables into the
4390 reload_insn_chain. */
4393 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4395 if (BLOCK_FOR_INSN (insn
))
4398 c
= new_insn_chain ();
4404 /* The block makes no sense here, but it is what the old
4406 c
->block
= bb
->index
;
4408 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4410 insn
= PREV_INSN (insn
);
4414 reload_insn_chain
= c
;
4417 for (i
= 0; i
< (unsigned int) max_regno
; i
++)
4418 if (live_subregs
[i
] != NULL
)
4419 sbitmap_free (live_subregs
[i
]);
4420 free (live_subregs
);
4423 print_insn_chains (dump_file
);
4426 /* Examine the rtx found in *LOC, which is read or written to as determined
4427 by TYPE. Return false if we find a reason why an insn containing this
4428 rtx should not be moved (such as accesses to non-constant memory), true
4431 rtx_moveable_p (rtx
*loc
, enum op_type type
)
4437 enum rtx_code code
= GET_CODE (x
);
4447 return type
== OP_IN
;
4450 if (x
== frame_pointer_rtx
)
4452 if (HARD_REGISTER_P (x
))
4458 if (type
== OP_IN
&& MEM_READONLY_P (x
))
4459 return rtx_moveable_p (&XEXP (x
, 0), OP_IN
);
4463 return (rtx_moveable_p (&SET_SRC (x
), OP_IN
)
4464 && rtx_moveable_p (&SET_DEST (x
), OP_OUT
));
4466 case STRICT_LOW_PART
:
4467 return rtx_moveable_p (&XEXP (x
, 0), OP_OUT
);
4471 return (rtx_moveable_p (&XEXP (x
, 0), type
)
4472 && rtx_moveable_p (&XEXP (x
, 1), OP_IN
)
4473 && rtx_moveable_p (&XEXP (x
, 2), OP_IN
));
4476 return rtx_moveable_p (&SET_DEST (x
), OP_OUT
);
4478 case UNSPEC_VOLATILE
:
4479 /* It is a bad idea to consider insns with such rtl
4480 as moveable ones. The insn scheduler also considers them as barrier
4485 /* The same is true for volatile asm: it has unknown side effects, it
4486 cannot be moved at will. */
4487 if (MEM_VOLATILE_P (x
))
4494 fmt
= GET_RTX_FORMAT (code
);
4495 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4499 if (!rtx_moveable_p (&XEXP (x
, i
), type
))
4502 else if (fmt
[i
] == 'E')
4503 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4505 if (!rtx_moveable_p (&XVECEXP (x
, i
, j
), type
))
4512 /* A wrapper around dominated_by_p, which uses the information in UID_LUID
4513 to give dominance relationships between two insns I1 and I2. */
4515 insn_dominated_by_p (rtx i1
, rtx i2
, int *uid_luid
)
4517 basic_block bb1
= BLOCK_FOR_INSN (i1
);
4518 basic_block bb2
= BLOCK_FOR_INSN (i2
);
4521 return uid_luid
[INSN_UID (i2
)] < uid_luid
[INSN_UID (i1
)];
4522 return dominated_by_p (CDI_DOMINATORS
, bb1
, bb2
);
4525 /* Record the range of register numbers added by find_moveable_pseudos. */
4526 int first_moveable_pseudo
, last_moveable_pseudo
;
4528 /* These two vectors hold data for every register added by
4529 find_movable_pseudos, with index 0 holding data for the
4530 first_moveable_pseudo. */
4531 /* The original home register. */
4532 static vec
<rtx
> pseudo_replaced_reg
;
4534 /* Look for instances where we have an instruction that is known to increase
4535 register pressure, and whose result is not used immediately. If it is
4536 possible to move the instruction downwards to just before its first use,
4537 split its lifetime into two ranges. We create a new pseudo to compute the
4538 value, and emit a move instruction just before the first use. If, after
4539 register allocation, the new pseudo remains unallocated, the function
4540 move_unallocated_pseudos then deletes the move instruction and places
4541 the computation just before the first use.
4543 Such a move is safe and profitable if all the input registers remain live
4544 and unchanged between the original computation and its first use. In such
4545 a situation, the computation is known to increase register pressure, and
4546 moving it is known to at least not worsen it.
4548 We restrict moves to only those cases where a register remains unallocated,
4549 in order to avoid interfering too much with the instruction schedule. As
4550 an exception, we may move insns which only modify their input register
4551 (typically induction variables), as this increases the freedom for our
4552 intended transformation, and does not limit the second instruction
4556 find_moveable_pseudos (void)
4559 int max_regs
= max_reg_num ();
4560 int max_uid
= get_max_uid ();
4562 int *uid_luid
= XNEWVEC (int, max_uid
);
4563 rtx_insn
**closest_uses
= XNEWVEC (rtx_insn
*, max_regs
);
4564 /* A set of registers which are live but not modified throughout a block. */
4565 bitmap_head
*bb_transp_live
= XNEWVEC (bitmap_head
,
4566 last_basic_block_for_fn (cfun
));
4567 /* A set of registers which only exist in a given basic block. */
4568 bitmap_head
*bb_local
= XNEWVEC (bitmap_head
,
4569 last_basic_block_for_fn (cfun
));
4570 /* A set of registers which are set once, in an instruction that can be
4571 moved freely downwards, but are otherwise transparent to a block. */
4572 bitmap_head
*bb_moveable_reg_sets
= XNEWVEC (bitmap_head
,
4573 last_basic_block_for_fn (cfun
));
4574 auto_bitmap live
, used
, set
, interesting
, unusable_as_input
;
4577 first_moveable_pseudo
= max_regs
;
4578 pseudo_replaced_reg
.release ();
4579 pseudo_replaced_reg
.safe_grow_cleared (max_regs
, true);
4582 calculate_dominance_info (CDI_DOMINATORS
);
4585 FOR_EACH_BB_FN (bb
, cfun
)
4588 bitmap transp
= bb_transp_live
+ bb
->index
;
4589 bitmap moveable
= bb_moveable_reg_sets
+ bb
->index
;
4590 bitmap local
= bb_local
+ bb
->index
;
4592 bitmap_initialize (local
, 0);
4593 bitmap_initialize (transp
, 0);
4594 bitmap_initialize (moveable
, 0);
4595 bitmap_copy (live
, df_get_live_out (bb
));
4596 bitmap_and_into (live
, df_get_live_in (bb
));
4597 bitmap_copy (transp
, live
);
4598 bitmap_clear (moveable
);
4599 bitmap_clear (live
);
4600 bitmap_clear (used
);
4602 FOR_BB_INSNS (bb
, insn
)
4603 if (NONDEBUG_INSN_P (insn
))
4605 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4608 uid_luid
[INSN_UID (insn
)] = i
++;
4610 def
= df_single_def (insn_info
);
4611 use
= df_single_use (insn_info
);
4614 && DF_REF_REGNO (use
) == DF_REF_REGNO (def
)
4615 && !bitmap_bit_p (set
, DF_REF_REGNO (use
))
4616 && rtx_moveable_p (&PATTERN (insn
), OP_IN
))
4618 unsigned regno
= DF_REF_REGNO (use
);
4619 bitmap_set_bit (moveable
, regno
);
4620 bitmap_set_bit (set
, regno
);
4621 bitmap_set_bit (used
, regno
);
4622 bitmap_clear_bit (transp
, regno
);
4625 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4627 unsigned regno
= DF_REF_REGNO (use
);
4628 bitmap_set_bit (used
, regno
);
4629 if (bitmap_clear_bit (moveable
, regno
))
4630 bitmap_clear_bit (transp
, regno
);
4633 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4635 unsigned regno
= DF_REF_REGNO (def
);
4636 bitmap_set_bit (set
, regno
);
4637 bitmap_clear_bit (transp
, regno
);
4638 bitmap_clear_bit (moveable
, regno
);
4643 FOR_EACH_BB_FN (bb
, cfun
)
4645 bitmap local
= bb_local
+ bb
->index
;
4648 FOR_BB_INSNS (bb
, insn
)
4649 if (NONDEBUG_INSN_P (insn
))
4651 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4653 rtx closest_use
, note
;
4656 bool all_dominated
, all_local
;
4659 def
= df_single_def (insn_info
);
4660 /* There must be exactly one def in this insn. */
4661 if (!def
|| !single_set (insn
))
4663 /* This must be the only definition of the reg. We also limit
4664 which modes we deal with so that we can assume we can generate
4665 move instructions. */
4666 regno
= DF_REF_REGNO (def
);
4667 mode
= GET_MODE (DF_REF_REG (def
));
4668 if (DF_REG_DEF_COUNT (regno
) != 1
4669 || !DF_REF_INSN_INFO (def
)
4670 || HARD_REGISTER_NUM_P (regno
)
4671 || DF_REG_EQ_USE_COUNT (regno
) > 0
4672 || (!INTEGRAL_MODE_P (mode
)
4673 && !FLOAT_MODE_P (mode
)
4674 && !OPAQUE_MODE_P (mode
)))
4676 def_insn
= DF_REF_INSN (def
);
4678 for (note
= REG_NOTES (def_insn
); note
; note
= XEXP (note
, 1))
4679 if (REG_NOTE_KIND (note
) == REG_EQUIV
&& MEM_P (XEXP (note
, 0)))
4685 fprintf (dump_file
, "Ignoring reg %d, has equiv memory\n",
4687 bitmap_set_bit (unusable_as_input
, regno
);
4691 use
= DF_REG_USE_CHAIN (regno
);
4692 all_dominated
= true;
4694 closest_use
= NULL_RTX
;
4695 for (; use
; use
= DF_REF_NEXT_REG (use
))
4698 if (!DF_REF_INSN_INFO (use
))
4700 all_dominated
= false;
4704 insn
= DF_REF_INSN (use
);
4705 if (DEBUG_INSN_P (insn
))
4707 if (BLOCK_FOR_INSN (insn
) != BLOCK_FOR_INSN (def_insn
))
4709 if (!insn_dominated_by_p (insn
, def_insn
, uid_luid
))
4710 all_dominated
= false;
4711 if (closest_use
!= insn
&& closest_use
!= const0_rtx
)
4713 if (closest_use
== NULL_RTX
)
4715 else if (insn_dominated_by_p (closest_use
, insn
, uid_luid
))
4717 else if (!insn_dominated_by_p (insn
, closest_use
, uid_luid
))
4718 closest_use
= const0_rtx
;
4724 fprintf (dump_file
, "Reg %d not all uses dominated by set\n",
4729 bitmap_set_bit (local
, regno
);
4730 if (closest_use
== const0_rtx
|| closest_use
== NULL
4731 || next_nonnote_nondebug_insn (def_insn
) == closest_use
)
4734 fprintf (dump_file
, "Reg %d uninteresting%s\n", regno
,
4735 closest_use
== const0_rtx
|| closest_use
== NULL
4736 ? " (no unique first use)" : "");
4740 bitmap_set_bit (interesting
, regno
);
4741 /* If we get here, we know closest_use is a non-NULL insn
4742 (as opposed to const_0_rtx). */
4743 closest_uses
[regno
] = as_a
<rtx_insn
*> (closest_use
);
4745 if (dump_file
&& (all_local
|| all_dominated
))
4747 fprintf (dump_file
, "Reg %u:", regno
);
4749 fprintf (dump_file
, " local to bb %d", bb
->index
);
4751 fprintf (dump_file
, " def dominates all uses");
4752 if (closest_use
!= const0_rtx
)
4753 fprintf (dump_file
, " has unique first use");
4754 fputs ("\n", dump_file
);
4759 EXECUTE_IF_SET_IN_BITMAP (interesting
, 0, i
, bi
)
4761 df_ref def
= DF_REG_DEF_CHAIN (i
);
4762 rtx_insn
*def_insn
= DF_REF_INSN (def
);
4763 basic_block def_block
= BLOCK_FOR_INSN (def_insn
);
4764 bitmap def_bb_local
= bb_local
+ def_block
->index
;
4765 bitmap def_bb_moveable
= bb_moveable_reg_sets
+ def_block
->index
;
4766 bitmap def_bb_transp
= bb_transp_live
+ def_block
->index
;
4767 bool local_to_bb_p
= bitmap_bit_p (def_bb_local
, i
);
4768 rtx_insn
*use_insn
= closest_uses
[i
];
4771 bool all_transp
= true;
4773 if (!REG_P (DF_REF_REG (def
)))
4779 fprintf (dump_file
, "Reg %u not local to one basic block\n",
4783 if (reg_equiv_init (i
) != NULL_RTX
)
4786 fprintf (dump_file
, "Ignoring reg %u with equiv init insn\n",
4790 if (!rtx_moveable_p (&PATTERN (def_insn
), OP_IN
))
4793 fprintf (dump_file
, "Found def insn %d for %d to be not moveable\n",
4794 INSN_UID (def_insn
), i
);
4798 fprintf (dump_file
, "Examining insn %d, def for %d\n",
4799 INSN_UID (def_insn
), i
);
4800 FOR_EACH_INSN_USE (use
, def_insn
)
4802 unsigned regno
= DF_REF_REGNO (use
);
4803 if (bitmap_bit_p (unusable_as_input
, regno
))
4807 fprintf (dump_file
, " found unusable input reg %u.\n", regno
);
4810 if (!bitmap_bit_p (def_bb_transp
, regno
))
4812 if (bitmap_bit_p (def_bb_moveable
, regno
)
4813 && !control_flow_insn_p (use_insn
))
4815 if (modified_between_p (DF_REF_REG (use
), def_insn
, use_insn
))
4817 rtx_insn
*x
= NEXT_INSN (def_insn
);
4818 while (!modified_in_p (DF_REF_REG (use
), x
))
4820 gcc_assert (x
!= use_insn
);
4824 fprintf (dump_file
, " input reg %u modified but insn %d moveable\n",
4825 regno
, INSN_UID (x
));
4826 emit_insn_after (PATTERN (x
), use_insn
);
4827 set_insn_deleted (x
);
4832 fprintf (dump_file
, " input reg %u modified between def and use\n",
4843 if (!dbg_cnt (ira_move
))
4846 fprintf (dump_file
, " all ok%s\n", all_transp
? " and transp" : "");
4850 rtx def_reg
= DF_REF_REG (def
);
4851 rtx newreg
= ira_create_new_reg (def_reg
);
4852 if (validate_change (def_insn
, DF_REF_REAL_LOC (def
), newreg
, 0))
4854 unsigned nregno
= REGNO (newreg
);
4855 emit_insn_before (gen_move_insn (def_reg
, newreg
), use_insn
);
4857 pseudo_replaced_reg
[nregno
] = def_reg
;
4862 FOR_EACH_BB_FN (bb
, cfun
)
4864 bitmap_clear (bb_local
+ bb
->index
);
4865 bitmap_clear (bb_transp_live
+ bb
->index
);
4866 bitmap_clear (bb_moveable_reg_sets
+ bb
->index
);
4869 free (closest_uses
);
4871 free (bb_transp_live
);
4872 free (bb_moveable_reg_sets
);
4874 last_moveable_pseudo
= max_reg_num ();
4876 fix_reg_equiv_init ();
4878 regstat_free_n_sets_and_refs ();
4880 regstat_init_n_sets_and_refs ();
4881 regstat_compute_ri ();
4882 free_dominance_info (CDI_DOMINATORS
);
4885 /* If SET pattern SET is an assignment from a hard register to a pseudo which
4886 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return
4887 the destination. Otherwise return NULL. */
4890 interesting_dest_for_shprep_1 (rtx set
, basic_block call_dom
)
4892 rtx src
= SET_SRC (set
);
4893 rtx dest
= SET_DEST (set
);
4894 if (!REG_P (src
) || !HARD_REGISTER_P (src
)
4895 || !REG_P (dest
) || HARD_REGISTER_P (dest
)
4896 || (call_dom
&& !bitmap_bit_p (df_get_live_in (call_dom
), REGNO (dest
))))
4901 /* If insn is interesting for parameter range-splitting shrink-wrapping
4902 preparation, i.e. it is a single set from a hard register to a pseudo, which
4903 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a
4904 parallel statement with only one such statement, return the destination.
4905 Otherwise return NULL. */
4908 interesting_dest_for_shprep (rtx_insn
*insn
, basic_block call_dom
)
4912 rtx pat
= PATTERN (insn
);
4913 if (GET_CODE (pat
) == SET
)
4914 return interesting_dest_for_shprep_1 (pat
, call_dom
);
4916 if (GET_CODE (pat
) != PARALLEL
)
4919 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
4921 rtx sub
= XVECEXP (pat
, 0, i
);
4922 if (GET_CODE (sub
) == USE
|| GET_CODE (sub
) == CLOBBER
)
4924 if (GET_CODE (sub
) != SET
4925 || side_effects_p (sub
))
4927 rtx dest
= interesting_dest_for_shprep_1 (sub
, call_dom
);
4936 /* Split live ranges of pseudos that are loaded from hard registers in the
4937 first BB in a BB that dominates all non-sibling call if such a BB can be
4938 found and is not in a loop. Return true if the function has made any
4942 split_live_ranges_for_shrink_wrap (void)
4944 basic_block bb
, call_dom
= NULL
;
4945 basic_block first
= single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
4946 rtx_insn
*insn
, *last_interesting_insn
= NULL
;
4947 auto_bitmap need_new
, reachable
;
4948 vec
<basic_block
> queue
;
4950 if (!SHRINK_WRAPPING_ENABLED
)
4953 queue
.create (n_basic_blocks_for_fn (cfun
));
4955 FOR_EACH_BB_FN (bb
, cfun
)
4956 FOR_BB_INSNS (bb
, insn
)
4957 if (CALL_P (insn
) && !SIBLING_CALL_P (insn
))
4965 bitmap_set_bit (need_new
, bb
->index
);
4966 bitmap_set_bit (reachable
, bb
->index
);
4967 queue
.quick_push (bb
);
4971 if (queue
.is_empty ())
4977 while (!queue
.is_empty ())
4983 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
4984 if (e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
)
4985 && bitmap_set_bit (reachable
, e
->dest
->index
))
4986 queue
.quick_push (e
->dest
);
4990 FOR_BB_INSNS (first
, insn
)
4992 rtx dest
= interesting_dest_for_shprep (insn
, NULL
);
4996 if (DF_REG_DEF_COUNT (REGNO (dest
)) > 1)
4999 for (df_ref use
= DF_REG_USE_CHAIN (REGNO(dest
));
5001 use
= DF_REF_NEXT_REG (use
))
5003 int ubbi
= DF_REF_BB (use
)->index
;
5004 if (bitmap_bit_p (reachable
, ubbi
))
5005 bitmap_set_bit (need_new
, ubbi
);
5007 last_interesting_insn
= insn
;
5010 if (!last_interesting_insn
)
5013 call_dom
= nearest_common_dominator_for_set (CDI_DOMINATORS
, need_new
);
5014 if (call_dom
== first
)
5017 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
5018 while (bb_loop_depth (call_dom
) > 0)
5019 call_dom
= get_immediate_dominator (CDI_DOMINATORS
, call_dom
);
5020 loop_optimizer_finalize ();
5022 if (call_dom
== first
)
5025 calculate_dominance_info (CDI_POST_DOMINATORS
);
5026 if (dominated_by_p (CDI_POST_DOMINATORS
, first
, call_dom
))
5028 free_dominance_info (CDI_POST_DOMINATORS
);
5031 free_dominance_info (CDI_POST_DOMINATORS
);
5034 fprintf (dump_file
, "Will split live ranges of parameters at BB %i\n",
5038 FOR_BB_INSNS (first
, insn
)
5040 rtx dest
= interesting_dest_for_shprep (insn
, call_dom
);
5041 if (!dest
|| dest
== pic_offset_table_rtx
)
5044 bool need_newreg
= false;
5046 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
5048 rtx_insn
*uin
= DF_REF_INSN (use
);
5049 next
= DF_REF_NEXT_REG (use
);
5051 if (DEBUG_INSN_P (uin
))
5054 basic_block ubb
= BLOCK_FOR_INSN (uin
);
5056 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
5065 rtx newreg
= ira_create_new_reg (dest
);
5067 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
5069 rtx_insn
*uin
= DF_REF_INSN (use
);
5070 next
= DF_REF_NEXT_REG (use
);
5072 basic_block ubb
= BLOCK_FOR_INSN (uin
);
5074 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
5075 validate_change (uin
, DF_REF_REAL_LOC (use
), newreg
, true);
5078 rtx_insn
*new_move
= gen_move_insn (newreg
, dest
);
5079 emit_insn_after (new_move
, bb_note (call_dom
));
5082 fprintf (dump_file
, "Split live-range of register ");
5083 print_rtl_single (dump_file
, dest
);
5088 if (insn
== last_interesting_insn
)
5091 apply_change_group ();
5095 /* Perform the second half of the transformation started in
5096 find_moveable_pseudos. We look for instances where the newly introduced
5097 pseudo remains unallocated, and remove it by moving the definition to
5098 just before its use, replacing the move instruction generated by
5099 find_moveable_pseudos. */
5101 move_unallocated_pseudos (void)
5104 for (i
= first_moveable_pseudo
; i
< last_moveable_pseudo
; i
++)
5105 if (reg_renumber
[i
] < 0)
5107 int idx
= i
- first_moveable_pseudo
;
5108 rtx other_reg
= pseudo_replaced_reg
[idx
];
5109 /* The iterating range [first_moveable_pseudo, last_moveable_pseudo)
5110 covers every new pseudo created in find_moveable_pseudos,
5111 regardless of the validation with it is successful or not.
5112 So we need to skip the pseudos which were used in those failed
5113 validations to avoid unexpected DF info and consequent ICE.
5114 We only set pseudo_replaced_reg[] when the validation is successful
5115 in find_moveable_pseudos, it's enough to check it here. */
5118 rtx_insn
*def_insn
= DF_REF_INSN (DF_REG_DEF_CHAIN (i
));
5119 /* The use must follow all definitions of OTHER_REG, so we can
5120 insert the new definition immediately after any of them. */
5121 df_ref other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
));
5122 rtx_insn
*move_insn
= DF_REF_INSN (other_def
);
5123 rtx_insn
*newinsn
= emit_insn_after (PATTERN (def_insn
), move_insn
);
5128 fprintf (dump_file
, "moving def of %d (insn %d now) ",
5129 REGNO (other_reg
), INSN_UID (def_insn
));
5131 delete_insn (move_insn
);
5132 while ((other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
))))
5133 delete_insn (DF_REF_INSN (other_def
));
5134 delete_insn (def_insn
);
5136 set
= single_set (newinsn
);
5137 success
= validate_change (newinsn
, &SET_DEST (set
), other_reg
, 0);
5138 gcc_assert (success
);
5140 fprintf (dump_file
, " %d) rather than keep unallocated replacement %d\n",
5141 INSN_UID (newinsn
), i
);
5142 SET_REG_N_REFS (i
, 0);
5145 first_moveable_pseudo
= last_moveable_pseudo
= 0;
5150 /* Code dealing with scratches (changing them onto
5151 pseudos and restoring them from the pseudos).
5153 We change scratches into pseudos at the beginning of IRA to
5154 simplify dealing with them (conflicts, hard register assignments).
5156 If the pseudo denoting scratch was spilled it means that we do not
5157 need a hard register for it. Such pseudos are transformed back to
5158 scratches at the end of LRA. */
5160 /* Description of location of a former scratch operand. */
5163 rtx_insn
*insn
; /* Insn where the scratch was. */
5164 int nop
; /* Number of the operand which was a scratch. */
5165 unsigned regno
; /* regno gnerated instead of scratch */
5166 int icode
; /* Original icode from which scratch was removed. */
5169 typedef struct sloc
*sloc_t
;
5171 /* Locations of the former scratches. */
5172 static vec
<sloc_t
> scratches
;
5174 /* Bitmap of scratch regnos. */
5175 static bitmap_head scratch_bitmap
;
5177 /* Bitmap of scratch operands. */
5178 static bitmap_head scratch_operand_bitmap
;
5180 /* Return true if pseudo REGNO is made of SCRATCH. */
5182 ira_former_scratch_p (int regno
)
5184 return bitmap_bit_p (&scratch_bitmap
, regno
);
5187 /* Return true if the operand NOP of INSN is a former scratch. */
5189 ira_former_scratch_operand_p (rtx_insn
*insn
, int nop
)
5191 return bitmap_bit_p (&scratch_operand_bitmap
,
5192 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
) != 0;
5195 /* Register operand NOP in INSN as a former scratch. It will be
5196 changed to scratch back, if it is necessary, at the LRA end. */
5198 ira_register_new_scratch_op (rtx_insn
*insn
, int nop
, int icode
)
5200 rtx op
= *recog_data
.operand_loc
[nop
];
5201 sloc_t loc
= XNEW (struct sloc
);
5202 ira_assert (REG_P (op
));
5205 loc
->regno
= REGNO (op
);
5207 scratches
.safe_push (loc
);
5208 bitmap_set_bit (&scratch_bitmap
, REGNO (op
));
5209 bitmap_set_bit (&scratch_operand_bitmap
,
5210 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
);
5211 add_reg_note (insn
, REG_UNUSED
, op
);
5214 /* Return true if string STR contains constraint 'X'. */
5216 contains_X_constraint_p (const char *str
)
5222 str
+= CONSTRAINT_LEN (c
, str
);
5223 if (c
== 'X') return true;
5228 /* Change INSN's scratches into pseudos and save their location.
5229 Return true if we changed any scratch. */
5231 ira_remove_insn_scratches (rtx_insn
*insn
, bool all_p
, FILE *dump_file
,
5232 rtx (*get_reg
) (rtx original
))
5235 bool insn_changed_p
;
5238 extract_insn (insn
);
5239 insn_changed_p
= false;
5240 for (i
= 0; i
< recog_data
.n_operands
; i
++)
5242 loc
= recog_data
.operand_loc
[i
];
5243 if (GET_CODE (*loc
) == SCRATCH
&& GET_MODE (*loc
) != VOIDmode
)
5245 if (! all_p
&& contains_X_constraint_p (recog_data
.constraints
[i
]))
5247 insn_changed_p
= true;
5248 *loc
= reg
= get_reg (*loc
);
5249 ira_register_new_scratch_op (insn
, i
, INSN_CODE (insn
));
5250 if (ira_dump_file
!= NULL
)
5252 "Removing SCRATCH to p%u in insn #%u (nop %d)\n",
5253 REGNO (reg
), INSN_UID (insn
), i
);
5256 return insn_changed_p
;
5259 /* Return new register of the same mode as ORIGINAL. Used in
5260 remove_scratches. */
5262 get_scratch_reg (rtx original
)
5264 return gen_reg_rtx (GET_MODE (original
));
5267 /* Change scratches into pseudos and save their location. Return true
5268 if we changed any scratch. */
5270 remove_scratches (void)
5272 bool change_p
= false;
5276 scratches
.create (get_max_uid ());
5277 bitmap_initialize (&scratch_bitmap
, ®_obstack
);
5278 bitmap_initialize (&scratch_operand_bitmap
, ®_obstack
);
5279 FOR_EACH_BB_FN (bb
, cfun
)
5280 FOR_BB_INSNS (bb
, insn
)
5282 && ira_remove_insn_scratches (insn
, false, ira_dump_file
, get_scratch_reg
))
5284 /* Because we might use DF, we need to keep DF info up to date. */
5285 df_insn_rescan (insn
);
5291 /* Changes pseudos created by function remove_scratches onto scratches. */
5293 ira_restore_scratches (FILE *dump_file
)
5300 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
5302 /* Ignore already deleted insns. */
5303 if (NOTE_P (loc
->insn
)
5304 && NOTE_KIND (loc
->insn
) == NOTE_INSN_DELETED
)
5306 extract_insn (loc
->insn
);
5307 if (loc
->icode
!= INSN_CODE (loc
->insn
))
5309 /* The icode doesn't match, which means the insn has been modified
5310 (e.g. register elimination). The scratch cannot be restored. */
5313 op_loc
= recog_data
.operand_loc
[loc
->nop
];
5315 && ((regno
= REGNO (*op_loc
)) >= FIRST_PSEUDO_REGISTER
)
5316 && reg_renumber
[regno
] < 0)
5318 /* It should be only case when scratch register with chosen
5319 constraint 'X' did not get memory or hard register. */
5320 ira_assert (ira_former_scratch_p (regno
));
5321 *op_loc
= gen_rtx_SCRATCH (GET_MODE (*op_loc
));
5322 for (n
= 0; n
< recog_data
.n_dups
; n
++)
5323 *recog_data
.dup_loc
[n
]
5324 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[n
]];
5325 if (dump_file
!= NULL
)
5326 fprintf (dump_file
, "Restoring SCRATCH in insn #%u(nop %d)\n",
5327 INSN_UID (loc
->insn
), loc
->nop
);
5330 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
5332 scratches
.release ();
5333 bitmap_clear (&scratch_bitmap
);
5334 bitmap_clear (&scratch_operand_bitmap
);
5339 /* If the backend knows where to allocate pseudos for hard
5340 register initial values, register these allocations now. */
5342 allocate_initial_values (void)
5344 if (targetm
.allocate_initial_value
)
5349 for (i
= 0; HARD_REGISTER_NUM_P (i
); i
++)
5351 if (! initial_value_entry (i
, &hreg
, &preg
))
5354 x
= targetm
.allocate_initial_value (hreg
);
5355 regno
= REGNO (preg
);
5356 if (x
&& REG_N_SETS (regno
) <= 1)
5359 reg_equiv_memory_loc (regno
) = x
;
5365 gcc_assert (REG_P (x
));
5366 new_regno
= REGNO (x
);
5367 reg_renumber
[regno
] = new_regno
;
5368 /* Poke the regno right into regno_reg_rtx so that even
5369 fixed regs are accepted. */
5370 SET_REGNO (preg
, new_regno
);
5371 /* Update global register liveness information. */
5372 FOR_EACH_BB_FN (bb
, cfun
)
5374 if (REGNO_REG_SET_P (df_get_live_in (bb
), regno
))
5375 SET_REGNO_REG_SET (df_get_live_in (bb
), new_regno
);
5376 if (REGNO_REG_SET_P (df_get_live_out (bb
), regno
))
5377 SET_REGNO_REG_SET (df_get_live_out (bb
), new_regno
);
5383 gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER
,
5391 /* True when we use LRA instead of reload pass for the current
5395 /* True if we have allocno conflicts. It is false for non-optimized
5396 mode or when the conflict table is too big. */
5397 bool ira_conflicts_p
;
5399 /* Saved between IRA and reload. */
5400 static int saved_flag_ira_share_spill_slots
;
5402 /* This is the main entry of IRA. */
5407 int ira_max_point_before_emit
;
5408 bool saved_flag_caller_saves
= flag_caller_saves
;
5409 enum ira_region saved_flag_ira_region
= flag_ira_region
;
5413 bool output_jump_reload_p
= false;
5417 /* First put potential jump output reloads on the output edges
5418 as USE which will be removed at the end of LRA. The major
5419 goal is actually to create BBs for critical edges for LRA and
5420 populate them later by live info. In LRA it will be
5421 difficult to do this. */
5422 FOR_EACH_BB_FN (bb
, cfun
)
5424 rtx_insn
*end
= BB_END (bb
);
5428 for (int i
= 0; i
< recog_data
.n_operands
; i
++)
5429 if (recog_data
.operand_type
[i
] != OP_IN
)
5431 bool skip_p
= false;
5432 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
5433 if (EDGE_CRITICAL_P (e
)
5434 && e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
)
5435 && (e
->flags
& EDGE_ABNORMAL
))
5442 output_jump_reload_p
= true;
5443 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
5444 if (EDGE_CRITICAL_P (e
)
5445 && e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
))
5448 /* We need to put some no-op insn here. We can
5449 not put a note as commit_edges insertion will
5451 emit_insn (gen_rtx_USE (VOIDmode
, const1_rtx
));
5452 rtx_insn
*insns
= get_insns ();
5454 insert_insn_on_edge (insns
, e
);
5459 if (output_jump_reload_p
)
5460 commit_edge_insertions ();
5463 if (flag_ira_verbose
< 10)
5465 internal_flag_ira_verbose
= flag_ira_verbose
;
5470 internal_flag_ira_verbose
= flag_ira_verbose
- 10;
5471 ira_dump_file
= stderr
;
5476 /* Determine if the current function is a leaf before running IRA
5477 since this can impact optimizations done by the prologue and
5478 epilogue thus changing register elimination offsets.
5479 Other target callbacks may use crtl->is_leaf too, including
5480 SHRINK_WRAPPING_ENABLED, so initialize as early as possible. */
5481 crtl
->is_leaf
= leaf_function_p ();
5483 /* Perform target specific PIC register initialization. */
5484 targetm
.init_pic_reg ();
5486 ira_conflicts_p
= optimize
> 0;
5488 /* Determine the number of pseudos actually requiring coloring. */
5489 unsigned int num_used_regs
= 0;
5490 for (unsigned int i
= FIRST_PSEUDO_REGISTER
; i
< DF_REG_SIZE (df
); i
++)
5491 if (DF_REG_DEF_COUNT (i
) || DF_REG_USE_COUNT (i
))
5494 /* If there are too many pseudos and/or basic blocks (e.g. 10K
5495 pseudos and 10K blocks or 100K pseudos and 1K blocks), we will
5496 use simplified and faster algorithms in LRA. */
5499 && num_used_regs
>= (1U << 26) / last_basic_block_for_fn (cfun
);
5503 /* It permits to skip live range splitting in LRA. */
5504 flag_caller_saves
= false;
5505 /* There is no sense to do regional allocation when we use
5507 flag_ira_region
= IRA_REGION_ONE
;
5508 ira_conflicts_p
= false;
5511 #ifndef IRA_NO_OBSTACK
5512 gcc_obstack_init (&ira_obstack
);
5514 bitmap_obstack_initialize (&ira_bitmap_obstack
);
5516 /* LRA uses its own infrastructure to handle caller save registers. */
5517 if (flag_caller_saves
&& !ira_use_lra_p
)
5518 init_caller_save ();
5520 setup_prohibited_mode_move_regs ();
5521 decrease_live_ranges_number ();
5522 df_note_add_problem ();
5524 /* DF_LIVE can't be used in the register allocator, too many other
5525 parts of the compiler depend on using the "classic" liveness
5526 interpretation of the DF_LR problem. See PR38711.
5527 Remove the problem, so that we don't spend time updating it in
5528 any of the df_analyze() calls during IRA/LRA. */
5530 df_remove_problem (df_live
);
5531 gcc_checking_assert (df_live
== NULL
);
5534 df
->changeable_flags
|= DF_VERIFY_SCHEDULED
;
5539 if (ira_conflicts_p
)
5541 calculate_dominance_info (CDI_DOMINATORS
);
5543 if (split_live_ranges_for_shrink_wrap ())
5546 free_dominance_info (CDI_DOMINATORS
);
5549 df_clear_flags (DF_NO_INSN_RESCAN
);
5551 indirect_jump_optimize ();
5552 if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
5555 regstat_init_n_sets_and_refs ();
5556 regstat_compute_ri ();
5558 /* If we are not optimizing, then this is the only place before
5559 register allocation where dataflow is done. And that is needed
5560 to generate these warnings. */
5562 generate_setjmp_warnings ();
5564 /* update_equiv_regs can use reg classes of pseudos and they are set up in
5565 register pressure sensitive scheduling and loop invariant motion and in
5566 live range shrinking. This info can become obsolete if we add new pseudos
5567 since the last set up. Recalculate it again if the new pseudos were
5569 if (resize_reg_info () && (flag_sched_pressure
|| flag_live_range_shrinkage
5570 || flag_ira_loop_pressure
))
5571 ira_set_pseudo_classes (true, ira_dump_file
);
5573 init_alias_analysis ();
5574 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
5575 reg_equiv
= XCNEWVEC (struct equivalence
, max_reg_num ());
5576 update_equiv_regs_prescan ();
5577 update_equiv_regs ();
5579 /* Don't move insns if live range shrinkage or register
5580 pressure-sensitive scheduling were done because it will not
5581 improve allocation but likely worsen insn scheduling. */
5583 && !flag_live_range_shrinkage
5584 && !(flag_sched_pressure
&& flag_schedule_insns
))
5585 combine_and_move_insns ();
5587 /* Gather additional equivalences with memory. */
5589 add_store_equivs ();
5591 loop_optimizer_finalize ();
5592 free_dominance_info (CDI_DOMINATORS
);
5593 end_alias_analysis ();
5596 /* Once max_regno changes, we need to free and re-init/re-compute
5597 some data structures like regstat_n_sets_and_refs and reg_info_p. */
5598 auto regstat_recompute_for_max_regno
= []() {
5599 regstat_free_n_sets_and_refs ();
5601 regstat_init_n_sets_and_refs ();
5602 regstat_compute_ri ();
5605 int max_regno_before_rm
= max_reg_num ();
5606 if (ira_use_lra_p
&& remove_scratches ())
5608 ira_expand_reg_equiv ();
5609 /* For now remove_scatches is supposed to create pseudos when it
5610 succeeds, assert this happens all the time. Once it doesn't
5611 hold, we should guard the regstat recompute for the case
5612 max_regno changes. */
5613 gcc_assert (max_regno_before_rm
!= max_reg_num ());
5614 regstat_recompute_for_max_regno ();
5619 setup_reg_equiv_init ();
5621 allocated_reg_info_size
= max_reg_num ();
5623 /* It is not worth to do such improvement when we use a simple
5624 allocation because of -O0 usage or because the function is too
5626 if (ira_conflicts_p
)
5627 find_moveable_pseudos ();
5629 max_regno_before_ira
= max_reg_num ();
5630 ira_setup_eliminable_regset ();
5632 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
5633 ira_load_cost
= ira_store_cost
= ira_shuffle_cost
= 0;
5634 ira_move_loops_num
= ira_additional_jumps_num
= 0;
5636 ira_assert (current_loops
== NULL
);
5637 if (flag_ira_region
== IRA_REGION_ALL
|| flag_ira_region
== IRA_REGION_MIXED
)
5638 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
| LOOPS_HAVE_RECORDED_EXITS
);
5640 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5641 fprintf (ira_dump_file
, "Building IRA IR\n");
5642 loops_p
= ira_build ();
5644 ira_assert (ira_conflicts_p
|| !loops_p
);
5646 saved_flag_ira_share_spill_slots
= flag_ira_share_spill_slots
;
5647 if (too_high_register_pressure_p () || cfun
->calls_setjmp
)
5648 /* It is just wasting compiler's time to pack spilled pseudos into
5649 stack slots in this case -- prohibit it. We also do this if
5650 there is setjmp call because a variable not modified between
5651 setjmp and longjmp the compiler is required to preserve its
5652 value and sharing slots does not guarantee it. */
5653 flag_ira_share_spill_slots
= FALSE
;
5657 ira_max_point_before_emit
= ira_max_point
;
5659 ira_initiate_emit_data ();
5663 max_regno
= max_reg_num ();
5664 if (ira_conflicts_p
)
5668 if (! ira_use_lra_p
)
5669 ira_initiate_assign ();
5678 ira_allocno_iterator ai
;
5680 FOR_EACH_ALLOCNO (a
, ai
)
5682 int old_regno
= ALLOCNO_REGNO (a
);
5683 int new_regno
= REGNO (ALLOCNO_EMIT_DATA (a
)->reg
);
5685 ALLOCNO_REGNO (a
) = new_regno
;
5687 if (old_regno
!= new_regno
)
5688 setup_reg_classes (new_regno
, reg_preferred_class (old_regno
),
5689 reg_alternate_class (old_regno
),
5690 reg_allocno_class (old_regno
));
5695 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5696 fprintf (ira_dump_file
, "Flattening IR\n");
5697 ira_flattening (max_regno_before_ira
, ira_max_point_before_emit
);
5699 /* New insns were generated: add notes and recalculate live
5703 /* ??? Rebuild the loop tree, but why? Does the loop tree
5704 change if new insns were generated? Can that be handled
5705 by updating the loop tree incrementally? */
5706 loop_optimizer_finalize ();
5707 free_dominance_info (CDI_DOMINATORS
);
5708 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
5709 | LOOPS_HAVE_RECORDED_EXITS
);
5711 if (! ira_use_lra_p
)
5713 setup_allocno_assignment_flags ();
5714 ira_initiate_assign ();
5715 ira_reassign_conflict_allocnos (max_regno
);
5720 ira_finish_emit_data ();
5722 setup_reg_renumber ();
5724 calculate_allocation_cost ();
5726 #ifdef ENABLE_IRA_CHECKING
5727 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5728 /* Opposite to reload pass, LRA does not use any conflict info
5729 from IRA. We don't rebuild conflict info for LRA (through
5730 ira_flattening call) and cannot use the check here. We could
5731 rebuild this info for LRA in the check mode but there is a risk
5732 that code generated with the check and without it will be a bit
5733 different. Calling ira_flattening in any mode would be a
5734 wasting CPU time. So do not check the allocation for LRA. */
5735 check_allocation ();
5738 if (max_regno
!= max_regno_before_ira
)
5739 regstat_recompute_for_max_regno ();
5741 overall_cost_before
= ira_overall_cost
;
5742 if (! ira_conflicts_p
)
5746 fix_reg_equiv_init ();
5748 #ifdef ENABLE_IRA_CHECKING
5749 print_redundant_copies ();
5751 if (! ira_use_lra_p
)
5753 ira_spilled_reg_stack_slots_num
= 0;
5754 ira_spilled_reg_stack_slots
5755 = ((class ira_spilled_reg_stack_slot
*)
5756 ira_allocate (max_regno
5757 * sizeof (class ira_spilled_reg_stack_slot
)));
5758 memset ((void *)ira_spilled_reg_stack_slots
, 0,
5759 max_regno
* sizeof (class ira_spilled_reg_stack_slot
));
5762 allocate_initial_values ();
5764 /* See comment for find_moveable_pseudos call. */
5765 if (ira_conflicts_p
)
5766 move_unallocated_pseudos ();
5768 /* Restore original values. */
5771 flag_caller_saves
= saved_flag_caller_saves
;
5772 flag_ira_region
= saved_flag_ira_region
;
5776 /* Modify asm goto to avoid further trouble with this insn. We can
5777 not replace the insn by USE as in other asm insns as we still
5778 need to keep CFG consistency. */
5780 ira_nullify_asm_goto (rtx_insn
*insn
)
5782 ira_assert (JUMP_P (insn
) && INSN_CODE (insn
) < 0);
5783 rtx tmp
= extract_asm_operands (PATTERN (insn
));
5784 PATTERN (insn
) = gen_rtx_ASM_OPERANDS (VOIDmode
, ggc_strdup (""), "", 0,
5787 ASM_OPERANDS_LABEL_VEC (tmp
),
5788 ASM_OPERANDS_SOURCE_LOCATION(tmp
));
5796 unsigned pic_offset_table_regno
= INVALID_REGNUM
;
5798 if (flag_ira_verbose
< 10)
5799 ira_dump_file
= dump_file
;
5801 /* If pic_offset_table_rtx is a pseudo register, then keep it so
5802 after reload to avoid possible wrong usages of hard reg assigned
5804 if (pic_offset_table_rtx
5805 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
5806 pic_offset_table_regno
= REGNO (pic_offset_table_rtx
);
5808 timevar_push (TV_RELOAD
);
5811 if (current_loops
!= NULL
)
5813 loop_optimizer_finalize ();
5814 free_dominance_info (CDI_DOMINATORS
);
5816 FOR_ALL_BB_FN (bb
, cfun
)
5817 bb
->loop_father
= NULL
;
5818 current_loops
= NULL
;
5822 lra (ira_dump_file
);
5823 /* ???!!! Move it before lra () when we use ira_reg_equiv in
5825 vec_free (reg_equivs
);
5831 df_set_flags (DF_NO_INSN_RESCAN
);
5832 build_insn_chain ();
5834 need_dce
= reload (get_insns (), ira_conflicts_p
);
5837 timevar_pop (TV_RELOAD
);
5839 timevar_push (TV_IRA
);
5841 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5843 ira_free (ira_spilled_reg_stack_slots
);
5844 ira_finish_assign ();
5847 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
5848 && overall_cost_before
!= ira_overall_cost
)
5849 fprintf (ira_dump_file
, "+++Overall after reload %" PRId64
"\n",
5852 flag_ira_share_spill_slots
= saved_flag_ira_share_spill_slots
;
5854 if (! ira_use_lra_p
)
5857 if (current_loops
!= NULL
)
5859 loop_optimizer_finalize ();
5860 free_dominance_info (CDI_DOMINATORS
);
5862 FOR_ALL_BB_FN (bb
, cfun
)
5863 bb
->loop_father
= NULL
;
5864 current_loops
= NULL
;
5867 regstat_free_n_sets_and_refs ();
5871 cleanup_cfg (CLEANUP_EXPENSIVE
);
5873 finish_reg_equiv ();
5875 bitmap_obstack_release (&ira_bitmap_obstack
);
5876 #ifndef IRA_NO_OBSTACK
5877 obstack_free (&ira_obstack
, NULL
);
5880 /* The code after the reload has changed so much that at this point
5881 we might as well just rescan everything. Note that
5882 df_rescan_all_insns is not going to help here because it does not
5883 touch the artificial uses and defs. */
5884 df_finish_pass (true);
5885 df_scan_alloc (NULL
);
5890 df_live_add_problem ();
5891 df_live_set_all_dirty ();
5897 if (need_dce
&& optimize
)
5900 /* Diagnose uses of the hard frame pointer when it is used as a global
5901 register. Often we can get away with letting the user appropriate
5902 the frame pointer, but we should let them know when code generation
5903 makes that impossible. */
5904 if (global_regs
[HARD_FRAME_POINTER_REGNUM
] && frame_pointer_needed
)
5906 tree decl
= global_regs_decl
[HARD_FRAME_POINTER_REGNUM
];
5907 error_at (DECL_SOURCE_LOCATION (current_function_decl
),
5908 "frame pointer required, but reserved");
5909 inform (DECL_SOURCE_LOCATION (decl
), "for %qD", decl
);
5912 /* If we are doing generic stack checking, give a warning if this
5913 function's frame size is larger than we expect. */
5914 if (flag_stack_check
== GENERIC_STACK_CHECK
)
5916 poly_int64 size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
5918 for (int i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5919 if (df_regs_ever_live_p (i
)
5921 && !crtl
->abi
->clobbers_full_reg_p (i
))
5922 size
+= UNITS_PER_WORD
;
5924 if (constant_lower_bound (size
) > STACK_CHECK_MAX_FRAME_SIZE
)
5925 warning (0, "frame size too large for reliable stack checking");
5928 if (pic_offset_table_regno
!= INVALID_REGNUM
)
5929 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, pic_offset_table_regno
);
5931 timevar_pop (TV_IRA
);
5934 /* Run the integrated register allocator. */
5938 const pass_data pass_data_ira
=
5940 RTL_PASS
, /* type */
5942 OPTGROUP_NONE
, /* optinfo_flags */
5944 0, /* properties_required */
5945 0, /* properties_provided */
5946 0, /* properties_destroyed */
5947 0, /* todo_flags_start */
5948 TODO_do_not_ggc_collect
, /* todo_flags_finish */
5951 class pass_ira
: public rtl_opt_pass
5954 pass_ira (gcc::context
*ctxt
)
5955 : rtl_opt_pass (pass_data_ira
, ctxt
)
5958 /* opt_pass methods: */
5959 virtual bool gate (function
*)
5961 return !targetm
.no_register_allocation
;
5963 virtual unsigned int execute (function
*)
5969 }; // class pass_ira
5974 make_pass_ira (gcc::context
*ctxt
)
5976 return new pass_ira (ctxt
);
5981 const pass_data pass_data_reload
=
5983 RTL_PASS
, /* type */
5984 "reload", /* name */
5985 OPTGROUP_NONE
, /* optinfo_flags */
5986 TV_RELOAD
, /* tv_id */
5987 0, /* properties_required */
5988 0, /* properties_provided */
5989 0, /* properties_destroyed */
5990 0, /* todo_flags_start */
5991 0, /* todo_flags_finish */
5994 class pass_reload
: public rtl_opt_pass
5997 pass_reload (gcc::context
*ctxt
)
5998 : rtl_opt_pass (pass_data_reload
, ctxt
)
6001 /* opt_pass methods: */
6002 virtual bool gate (function
*)
6004 return !targetm
.no_register_allocation
;
6006 virtual unsigned int execute (function
*)
6012 }; // class pass_reload
6017 make_pass_reload (gcc::context
*ctxt
)
6019 return new pass_reload (ctxt
);