1 /* Integrated Register Allocator (IRA) entry point.
2 Copyright (C) 2006-2019 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* The integrated register allocator (IRA) is a
22 regional register allocator performing graph coloring on a top-down
23 traversal of nested regions. Graph coloring in a region is based
24 on Chaitin-Briggs algorithm. It is called integrated because
25 register coalescing, register live range splitting, and choosing a
26 better hard register are done on-the-fly during coloring. Register
27 coalescing and choosing a cheaper hard register is done by hard
28 register preferencing during hard register assigning. The live
29 range splitting is a byproduct of the regional register allocation.
31 Major IRA notions are:
33 o *Region* is a part of CFG where graph coloring based on
34 Chaitin-Briggs algorithm is done. IRA can work on any set of
35 nested CFG regions forming a tree. Currently the regions are
36 the entire function for the root region and natural loops for
37 the other regions. Therefore data structure representing a
38 region is called loop_tree_node.
40 o *Allocno class* is a register class used for allocation of
41 given allocno. It means that only hard register of given
42 register class can be assigned to given allocno. In reality,
43 even smaller subset of (*profitable*) hard registers can be
44 assigned. In rare cases, the subset can be even smaller
45 because our modification of Chaitin-Briggs algorithm requires
46 that sets of hard registers can be assigned to allocnos forms a
47 forest, i.e. the sets can be ordered in a way where any
48 previous set is not intersected with given set or is a superset
51 o *Pressure class* is a register class belonging to a set of
52 register classes containing all of the hard-registers available
53 for register allocation. The set of all pressure classes for a
54 target is defined in the corresponding machine-description file
55 according some criteria. Register pressure is calculated only
56 for pressure classes and it affects some IRA decisions as
57 forming allocation regions.
59 o *Allocno* represents the live range of a pseudo-register in a
60 region. Besides the obvious attributes like the corresponding
61 pseudo-register number, allocno class, conflicting allocnos and
62 conflicting hard-registers, there are a few allocno attributes
63 which are important for understanding the allocation algorithm:
65 - *Live ranges*. This is a list of ranges of *program points*
66 where the allocno lives. Program points represent places
67 where a pseudo can be born or become dead (there are
68 approximately two times more program points than the insns)
69 and they are represented by integers starting with 0. The
70 live ranges are used to find conflicts between allocnos.
71 They also play very important role for the transformation of
72 the IRA internal representation of several regions into a one
73 region representation. The later is used during the reload
74 pass work because each allocno represents all of the
75 corresponding pseudo-registers.
77 - *Hard-register costs*. This is a vector of size equal to the
78 number of available hard-registers of the allocno class. The
79 cost of a callee-clobbered hard-register for an allocno is
80 increased by the cost of save/restore code around the calls
81 through the given allocno's life. If the allocno is a move
82 instruction operand and another operand is a hard-register of
83 the allocno class, the cost of the hard-register is decreased
86 When an allocno is assigned, the hard-register with minimal
87 full cost is used. Initially, a hard-register's full cost is
88 the corresponding value from the hard-register's cost vector.
89 If the allocno is connected by a *copy* (see below) to
90 another allocno which has just received a hard-register, the
91 cost of the hard-register is decreased. Before choosing a
92 hard-register for an allocno, the allocno's current costs of
93 the hard-registers are modified by the conflict hard-register
94 costs of all of the conflicting allocnos which are not
97 - *Conflict hard-register costs*. This is a vector of the same
98 size as the hard-register costs vector. To permit an
99 unassigned allocno to get a better hard-register, IRA uses
100 this vector to calculate the final full cost of the
101 available hard-registers. Conflict hard-register costs of an
102 unassigned allocno are also changed with a change of the
103 hard-register cost of the allocno when a copy involving the
104 allocno is processed as described above. This is done to
105 show other unassigned allocnos that a given allocno prefers
106 some hard-registers in order to remove the move instruction
107 corresponding to the copy.
109 o *Cap*. If a pseudo-register does not live in a region but
110 lives in a nested region, IRA creates a special allocno called
111 a cap in the outer region. A region cap is also created for a
114 o *Copy*. Allocnos can be connected by copies. Copies are used
115 to modify hard-register costs for allocnos during coloring.
116 Such modifications reflects a preference to use the same
117 hard-register for the allocnos connected by copies. Usually
118 copies are created for move insns (in this case it results in
119 register coalescing). But IRA also creates copies for operands
120 of an insn which should be assigned to the same hard-register
121 due to constraints in the machine description (it usually
122 results in removing a move generated in reload to satisfy
123 the constraints) and copies referring to the allocno which is
124 the output operand of an instruction and the allocno which is
125 an input operand dying in the instruction (creation of such
126 copies results in less register shuffling). IRA *does not*
127 create copies between the same register allocnos from different
128 regions because we use another technique for propagating
129 hard-register preference on the borders of regions.
131 Allocnos (including caps) for the upper region in the region tree
132 *accumulate* information important for coloring from allocnos with
133 the same pseudo-register from nested regions. This includes
134 hard-register and memory costs, conflicts with hard-registers,
135 allocno conflicts, allocno copies and more. *Thus, attributes for
136 allocnos in a region have the same values as if the region had no
137 subregions*. It means that attributes for allocnos in the
138 outermost region corresponding to the function have the same values
139 as though the allocation used only one region which is the entire
140 function. It also means that we can look at IRA work as if the
141 first IRA did allocation for all function then it improved the
142 allocation for loops then their subloops and so on.
144 IRA major passes are:
146 o Building IRA internal representation which consists of the
149 * First, IRA builds regions and creates allocnos (file
150 ira-build.c) and initializes most of their attributes.
152 * Then IRA finds an allocno class for each allocno and
153 calculates its initial (non-accumulated) cost of memory and
154 each hard-register of its allocno class (file ira-cost.c).
156 * IRA creates live ranges of each allocno, calculates register
157 pressure for each pressure class in each region, sets up
158 conflict hard registers for each allocno and info about calls
159 the allocno lives through (file ira-lives.c).
161 * IRA removes low register pressure loops from the regions
162 mostly to speed IRA up (file ira-build.c).
164 * IRA propagates accumulated allocno info from lower region
165 allocnos to corresponding upper region allocnos (file
168 * IRA creates all caps (file ira-build.c).
170 * Having live-ranges of allocnos and their classes, IRA creates
171 conflicting allocnos for each allocno. Conflicting allocnos
172 are stored as a bit vector or array of pointers to the
173 conflicting allocnos whatever is more profitable (file
174 ira-conflicts.c). At this point IRA creates allocno copies.
176 o Coloring. Now IRA has all necessary info to start graph coloring
177 process. It is done in each region on top-down traverse of the
178 region tree (file ira-color.c). There are following subpasses:
180 * Finding profitable hard registers of corresponding allocno
181 class for each allocno. For example, only callee-saved hard
182 registers are frequently profitable for allocnos living
183 through colors. If the profitable hard register set of
184 allocno does not form a tree based on subset relation, we use
185 some approximation to form the tree. This approximation is
186 used to figure out trivial colorability of allocnos. The
187 approximation is a pretty rare case.
189 * Putting allocnos onto the coloring stack. IRA uses Briggs
190 optimistic coloring which is a major improvement over
191 Chaitin's coloring. Therefore IRA does not spill allocnos at
192 this point. There is some freedom in the order of putting
193 allocnos on the stack which can affect the final result of
194 the allocation. IRA uses some heuristics to improve the
195 order. The major one is to form *threads* from colorable
196 allocnos and push them on the stack by threads. Thread is a
197 set of non-conflicting colorable allocnos connected by
198 copies. The thread contains allocnos from the colorable
199 bucket or colorable allocnos already pushed onto the coloring
200 stack. Pushing thread allocnos one after another onto the
201 stack increases chances of removing copies when the allocnos
202 get the same hard reg.
204 We also use a modification of Chaitin-Briggs algorithm which
205 works for intersected register classes of allocnos. To
206 figure out trivial colorability of allocnos, the mentioned
207 above tree of hard register sets is used. To get an idea how
208 the algorithm works in i386 example, let us consider an
209 allocno to which any general hard register can be assigned.
210 If the allocno conflicts with eight allocnos to which only
211 EAX register can be assigned, given allocno is still
212 trivially colorable because all conflicting allocnos might be
213 assigned only to EAX and all other general hard registers are
216 To get an idea of the used trivial colorability criterion, it
217 is also useful to read article "Graph-Coloring Register
218 Allocation for Irregular Architectures" by Michael D. Smith
219 and Glen Holloway. Major difference between the article
220 approach and approach used in IRA is that Smith's approach
221 takes register classes only from machine description and IRA
222 calculate register classes from intermediate code too
223 (e.g. an explicit usage of hard registers in RTL code for
224 parameter passing can result in creation of additional
225 register classes which contain or exclude the hard
226 registers). That makes IRA approach useful for improving
227 coloring even for architectures with regular register files
228 and in fact some benchmarking shows the improvement for
229 regular class architectures is even bigger than for irregular
230 ones. Another difference is that Smith's approach chooses
231 intersection of classes of all insn operands in which a given
232 pseudo occurs. IRA can use bigger classes if it is still
233 more profitable than memory usage.
235 * Popping the allocnos from the stack and assigning them hard
236 registers. If IRA cannot assign a hard register to an
237 allocno and the allocno is coalesced, IRA undoes the
238 coalescing and puts the uncoalesced allocnos onto the stack in
239 the hope that some such allocnos will get a hard register
240 separately. If IRA fails to assign hard register or memory
241 is more profitable for it, IRA spills the allocno. IRA
242 assigns the allocno the hard-register with minimal full
243 allocation cost which reflects the cost of usage of the
244 hard-register for the allocno and cost of usage of the
245 hard-register for allocnos conflicting with given allocno.
247 * Chaitin-Briggs coloring assigns as many pseudos as possible
248 to hard registers. After coloring we try to improve
249 allocation with cost point of view. We improve the
250 allocation by spilling some allocnos and assigning the freed
251 hard registers to other allocnos if it decreases the overall
254 * After allocno assigning in the region, IRA modifies the hard
255 register and memory costs for the corresponding allocnos in
256 the subregions to reflect the cost of possible loads, stores,
257 or moves on the border of the region and its subregions.
258 When default regional allocation algorithm is used
259 (-fira-algorithm=mixed), IRA just propagates the assignment
260 for allocnos if the register pressure in the region for the
261 corresponding pressure class is less than number of available
262 hard registers for given pressure class.
264 o Spill/restore code moving. When IRA performs an allocation
265 by traversing regions in top-down order, it does not know what
266 happens below in the region tree. Therefore, sometimes IRA
267 misses opportunities to perform a better allocation. A simple
268 optimization tries to improve allocation in a region having
269 subregions and containing in another region. If the
270 corresponding allocnos in the subregion are spilled, it spills
271 the region allocno if it is profitable. The optimization
272 implements a simple iterative algorithm performing profitable
273 transformations while they are still possible. It is fast in
274 practice, so there is no real need for a better time complexity
277 o Code change. After coloring, two allocnos representing the
278 same pseudo-register outside and inside a region respectively
279 may be assigned to different locations (hard-registers or
280 memory). In this case IRA creates and uses a new
281 pseudo-register inside the region and adds code to move allocno
282 values on the region's borders. This is done during top-down
283 traversal of the regions (file ira-emit.c). In some
284 complicated cases IRA can create a new allocno to move allocno
285 values (e.g. when a swap of values stored in two hard-registers
286 is needed). At this stage, the new allocno is marked as
287 spilled. IRA still creates the pseudo-register and the moves
288 on the region borders even when both allocnos were assigned to
289 the same hard-register. If the reload pass spills a
290 pseudo-register for some reason, the effect will be smaller
291 because another allocno will still be in the hard-register. In
292 most cases, this is better then spilling both allocnos. If
293 reload does not change the allocation for the two
294 pseudo-registers, the trivial move will be removed by
295 post-reload optimizations. IRA does not generate moves for
296 allocnos assigned to the same hard register when the default
297 regional allocation algorithm is used and the register pressure
298 in the region for the corresponding pressure class is less than
299 number of available hard registers for given pressure class.
300 IRA also does some optimizations to remove redundant stores and
301 to reduce code duplication on the region borders.
303 o Flattening internal representation. After changing code, IRA
304 transforms its internal representation for several regions into
305 one region representation (file ira-build.c). This process is
306 called IR flattening. Such process is more complicated than IR
307 rebuilding would be, but is much faster.
309 o After IR flattening, IRA tries to assign hard registers to all
310 spilled allocnos. This is implemented by a simple and fast
311 priority coloring algorithm (see function
312 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
313 created during the code change pass can be assigned to hard
316 o At the end IRA calls the reload pass. The reload pass
317 communicates with IRA through several functions in file
318 ira-color.c to improve its decisions in
320 * sharing stack slots for the spilled pseudos based on IRA info
321 about pseudo-register conflicts.
323 * reassigning hard-registers to all spilled pseudos at the end
324 of each reload iteration.
326 * choosing a better hard-register to spill based on IRA info
327 about pseudo-register live ranges and the register pressure
328 in places where the pseudo-register lives.
330 IRA uses a lot of data representing the target processors. These
331 data are initialized in file ira.c.
333 If function has no loops (or the loops are ignored when
334 -fira-algorithm=CB is used), we have classic Chaitin-Briggs
335 coloring (only instead of separate pass of coalescing, we use hard
336 register preferencing). In such case, IRA works much faster
337 because many things are not made (like IR flattening, the
338 spill/restore optimization, and the code change).
340 Literature is worth to read for better understanding the code:
342 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
343 Graph Coloring Register Allocation.
345 o David Callahan, Brian Koblenz. Register allocation via
346 hierarchical graph coloring.
348 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
349 Coloring Register Allocation: A Study of the Chaitin-Briggs and
350 Callahan-Koblenz Algorithms.
352 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
353 Register Allocation Based on Graph Fusion.
355 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
356 Allocation for Irregular Architectures
358 o Vladimir Makarov. The Integrated Register Allocator for GCC.
360 o Vladimir Makarov. The top-down register allocator for irregular
361 register file architectures.
368 #include "coretypes.h"
374 #include "memmodel.h"
376 #include "insn-config.h"
380 #include "diagnostic-core.h"
382 #include "cfgbuild.h"
383 #include "cfgcleanup.h"
385 #include "tree-pass.h"
392 #include "rtl-iter.h"
393 #include "shrink-wrap.h"
394 #include "print-rtl.h"
396 struct target_ira default_target_ira
;
397 struct target_ira_int default_target_ira_int
;
398 #if SWITCHABLE_TARGET
399 struct target_ira
*this_target_ira
= &default_target_ira
;
400 struct target_ira_int
*this_target_ira_int
= &default_target_ira_int
;
403 /* A modified value of flag `-fira-verbose' used internally. */
404 int internal_flag_ira_verbose
;
406 /* Dump file of the allocator if it is not NULL. */
409 /* The number of elements in the following array. */
410 int ira_spilled_reg_stack_slots_num
;
412 /* The following array contains info about spilled pseudo-registers
413 stack slots used in current function so far. */
414 struct ira_spilled_reg_stack_slot
*ira_spilled_reg_stack_slots
;
416 /* Correspondingly overall cost of the allocation, overall cost before
417 reload, cost of the allocnos assigned to hard-registers, cost of
418 the allocnos assigned to memory, cost of loads, stores and register
419 move insns generated for pseudo-register live range splitting (see
421 int64_t ira_overall_cost
, overall_cost_before
;
422 int64_t ira_reg_cost
, ira_mem_cost
;
423 int64_t ira_load_cost
, ira_store_cost
, ira_shuffle_cost
;
424 int ira_move_loops_num
, ira_additional_jumps_num
;
426 /* All registers that can be eliminated. */
428 HARD_REG_SET eliminable_regset
;
430 /* Value of max_reg_num () before IRA work start. This value helps
431 us to recognize a situation when new pseudos were created during
433 static int max_regno_before_ira
;
435 /* Temporary hard reg set used for a different calculation. */
436 static HARD_REG_SET temp_hard_regset
;
438 #define last_mode_for_init_move_cost \
439 (this_target_ira_int->x_last_mode_for_init_move_cost)
442 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
444 setup_reg_mode_hard_regset (void)
446 int i
, m
, hard_regno
;
448 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
449 for (hard_regno
= 0; hard_regno
< FIRST_PSEUDO_REGISTER
; hard_regno
++)
451 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset
[hard_regno
][m
]);
452 for (i
= hard_regno_nregs (hard_regno
, (machine_mode
) m
) - 1;
454 if (hard_regno
+ i
< FIRST_PSEUDO_REGISTER
)
455 SET_HARD_REG_BIT (ira_reg_mode_hard_regset
[hard_regno
][m
],
461 #define no_unit_alloc_regs \
462 (this_target_ira_int->x_no_unit_alloc_regs)
464 /* The function sets up the three arrays declared above. */
466 setup_class_hard_regs (void)
468 int cl
, i
, hard_regno
, n
;
469 HARD_REG_SET processed_hard_reg_set
;
471 ira_assert (SHRT_MAX
>= FIRST_PSEUDO_REGISTER
);
472 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
474 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
475 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
476 CLEAR_HARD_REG_SET (processed_hard_reg_set
);
477 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
479 ira_non_ordered_class_hard_regs
[cl
][i
] = -1;
480 ira_class_hard_reg_index
[cl
][i
] = -1;
482 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
484 #ifdef REG_ALLOC_ORDER
485 hard_regno
= reg_alloc_order
[i
];
489 if (TEST_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
))
491 SET_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
);
492 if (! TEST_HARD_REG_BIT (temp_hard_regset
, hard_regno
))
493 ira_class_hard_reg_index
[cl
][hard_regno
] = -1;
496 ira_class_hard_reg_index
[cl
][hard_regno
] = n
;
497 ira_class_hard_regs
[cl
][n
++] = hard_regno
;
500 ira_class_hard_regs_num
[cl
] = n
;
501 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
502 if (TEST_HARD_REG_BIT (temp_hard_regset
, i
))
503 ira_non_ordered_class_hard_regs
[cl
][n
++] = i
;
504 ira_assert (ira_class_hard_regs_num
[cl
] == n
);
508 /* Set up global variables defining info about hard registers for the
509 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
510 that we can use the hard frame pointer for the allocation. */
512 setup_alloc_regs (bool use_hard_frame_p
)
514 #ifdef ADJUST_REG_ALLOC_ORDER
515 ADJUST_REG_ALLOC_ORDER
;
517 COPY_HARD_REG_SET (no_unit_alloc_regs
, fixed_nonglobal_reg_set
);
518 if (! use_hard_frame_p
)
519 SET_HARD_REG_BIT (no_unit_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
520 setup_class_hard_regs ();
525 #define alloc_reg_class_subclasses \
526 (this_target_ira_int->x_alloc_reg_class_subclasses)
528 /* Initialize the table of subclasses of each reg class. */
530 setup_reg_subclasses (void)
533 HARD_REG_SET temp_hard_regset2
;
535 for (i
= 0; i
< N_REG_CLASSES
; i
++)
536 for (j
= 0; j
< N_REG_CLASSES
; j
++)
537 alloc_reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
539 for (i
= 0; i
< N_REG_CLASSES
; i
++)
541 if (i
== (int) NO_REGS
)
544 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
545 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
546 if (hard_reg_set_empty_p (temp_hard_regset
))
548 for (j
= 0; j
< N_REG_CLASSES
; j
++)
553 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[j
]);
554 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
555 if (! hard_reg_set_subset_p (temp_hard_regset
,
558 p
= &alloc_reg_class_subclasses
[j
][0];
559 while (*p
!= LIM_REG_CLASSES
) p
++;
560 *p
= (enum reg_class
) i
;
567 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
569 setup_class_subset_and_memory_move_costs (void)
571 int cl
, cl2
, mode
, cost
;
572 HARD_REG_SET temp_hard_regset2
;
574 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
575 ira_memory_move_cost
[mode
][NO_REGS
][0]
576 = ira_memory_move_cost
[mode
][NO_REGS
][1] = SHRT_MAX
;
577 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
579 if (cl
!= (int) NO_REGS
)
580 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
582 ira_max_memory_move_cost
[mode
][cl
][0]
583 = ira_memory_move_cost
[mode
][cl
][0]
584 = memory_move_cost ((machine_mode
) mode
,
585 (reg_class_t
) cl
, false);
586 ira_max_memory_move_cost
[mode
][cl
][1]
587 = ira_memory_move_cost
[mode
][cl
][1]
588 = memory_move_cost ((machine_mode
) mode
,
589 (reg_class_t
) cl
, true);
590 /* Costs for NO_REGS are used in cost calculation on the
591 1st pass when the preferred register classes are not
592 known yet. In this case we take the best scenario. */
593 if (ira_memory_move_cost
[mode
][NO_REGS
][0]
594 > ira_memory_move_cost
[mode
][cl
][0])
595 ira_max_memory_move_cost
[mode
][NO_REGS
][0]
596 = ira_memory_move_cost
[mode
][NO_REGS
][0]
597 = ira_memory_move_cost
[mode
][cl
][0];
598 if (ira_memory_move_cost
[mode
][NO_REGS
][1]
599 > ira_memory_move_cost
[mode
][cl
][1])
600 ira_max_memory_move_cost
[mode
][NO_REGS
][1]
601 = ira_memory_move_cost
[mode
][NO_REGS
][1]
602 = ira_memory_move_cost
[mode
][cl
][1];
605 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
606 for (cl2
= (int) N_REG_CLASSES
- 1; cl2
>= 0; cl2
--)
608 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
609 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
610 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
611 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
612 ira_class_subset_p
[cl
][cl2
]
613 = hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
);
614 if (! hard_reg_set_empty_p (temp_hard_regset2
)
615 && hard_reg_set_subset_p (reg_class_contents
[cl2
],
616 reg_class_contents
[cl
]))
617 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
619 cost
= ira_memory_move_cost
[mode
][cl2
][0];
620 if (cost
> ira_max_memory_move_cost
[mode
][cl
][0])
621 ira_max_memory_move_cost
[mode
][cl
][0] = cost
;
622 cost
= ira_memory_move_cost
[mode
][cl2
][1];
623 if (cost
> ira_max_memory_move_cost
[mode
][cl
][1])
624 ira_max_memory_move_cost
[mode
][cl
][1] = cost
;
627 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
628 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
630 ira_memory_move_cost
[mode
][cl
][0]
631 = ira_max_memory_move_cost
[mode
][cl
][0];
632 ira_memory_move_cost
[mode
][cl
][1]
633 = ira_max_memory_move_cost
[mode
][cl
][1];
635 setup_reg_subclasses ();
640 /* Define the following macro if allocation through malloc if
642 #define IRA_NO_OBSTACK
644 #ifndef IRA_NO_OBSTACK
645 /* Obstack used for storing all dynamic data (except bitmaps) of the
647 static struct obstack ira_obstack
;
650 /* Obstack used for storing all bitmaps of the IRA. */
651 static struct bitmap_obstack ira_bitmap_obstack
;
653 /* Allocate memory of size LEN for IRA data. */
655 ira_allocate (size_t len
)
659 #ifndef IRA_NO_OBSTACK
660 res
= obstack_alloc (&ira_obstack
, len
);
667 /* Free memory ADDR allocated for IRA data. */
669 ira_free (void *addr ATTRIBUTE_UNUSED
)
671 #ifndef IRA_NO_OBSTACK
679 /* Allocate and returns bitmap for IRA. */
681 ira_allocate_bitmap (void)
683 return BITMAP_ALLOC (&ira_bitmap_obstack
);
686 /* Free bitmap B allocated for IRA. */
688 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED
)
695 /* Output information about allocation of all allocnos (except for
696 caps) into file F. */
698 ira_print_disposition (FILE *f
)
704 fprintf (f
, "Disposition:");
705 max_regno
= max_reg_num ();
706 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
707 for (a
= ira_regno_allocno_map
[i
];
709 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
714 fprintf (f
, " %4d:r%-4d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
715 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
716 fprintf (f
, "b%-3d", bb
->index
);
718 fprintf (f
, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
719 if (ALLOCNO_HARD_REGNO (a
) >= 0)
720 fprintf (f
, " %3d", ALLOCNO_HARD_REGNO (a
));
727 /* Outputs information about allocation of all allocnos into
730 ira_debug_disposition (void)
732 ira_print_disposition (stderr
);
737 /* Set up ira_stack_reg_pressure_class which is the biggest pressure
738 register class containing stack registers or NO_REGS if there are
739 no stack registers. To find this class, we iterate through all
740 register pressure classes and choose the first register pressure
741 class containing all the stack registers and having the biggest
744 setup_stack_reg_pressure_class (void)
746 ira_stack_reg_pressure_class
= NO_REGS
;
751 HARD_REG_SET temp_hard_regset2
;
753 CLEAR_HARD_REG_SET (temp_hard_regset
);
754 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
755 SET_HARD_REG_BIT (temp_hard_regset
, i
);
757 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
759 cl
= ira_pressure_classes
[i
];
760 COPY_HARD_REG_SET (temp_hard_regset2
, temp_hard_regset
);
761 AND_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
762 size
= hard_reg_set_size (temp_hard_regset2
);
766 ira_stack_reg_pressure_class
= cl
;
773 /* Find pressure classes which are register classes for which we
774 calculate register pressure in IRA, register pressure sensitive
775 insn scheduling, and register pressure sensitive loop invariant
778 To make register pressure calculation easy, we always use
779 non-intersected register pressure classes. A move of hard
780 registers from one register pressure class is not more expensive
781 than load and store of the hard registers. Most likely an allocno
782 class will be a subset of a register pressure class and in many
783 cases a register pressure class. That makes usage of register
784 pressure classes a good approximation to find a high register
787 setup_pressure_classes (void)
789 int cost
, i
, n
, curr
;
791 enum reg_class pressure_classes
[N_REG_CLASSES
];
793 HARD_REG_SET temp_hard_regset2
;
796 if (targetm
.compute_pressure_classes
)
797 n
= targetm
.compute_pressure_classes (pressure_classes
);
801 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
803 if (ira_class_hard_regs_num
[cl
] == 0)
805 if (ira_class_hard_regs_num
[cl
] != 1
806 /* A register class without subclasses may contain a few
807 hard registers and movement between them is costly
808 (e.g. SPARC FPCC registers). We still should consider it
809 as a candidate for a pressure class. */
810 && alloc_reg_class_subclasses
[cl
][0] < cl
)
812 /* Check that the moves between any hard registers of the
813 current class are not more expensive for a legal mode
814 than load/store of the hard registers of the current
815 class. Such class is a potential candidate to be a
816 register pressure class. */
817 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
819 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
820 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
821 AND_COMPL_HARD_REG_SET (temp_hard_regset
,
822 ira_prohibited_class_mode_regs
[cl
][m
]);
823 if (hard_reg_set_empty_p (temp_hard_regset
))
825 ira_init_register_move_cost_if_necessary ((machine_mode
) m
);
826 cost
= ira_register_move_cost
[m
][cl
][cl
];
827 if (cost
<= ira_max_memory_move_cost
[m
][cl
][1]
828 || cost
<= ira_max_memory_move_cost
[m
][cl
][0])
831 if (m
>= NUM_MACHINE_MODES
)
836 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
837 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
838 /* Remove so far added pressure classes which are subset of the
839 current candidate class. Prefer GENERAL_REGS as a pressure
840 register class to another class containing the same
841 allocatable hard registers. We do this because machine
842 dependent cost hooks might give wrong costs for the latter
843 class but always give the right cost for the former class
845 for (i
= 0; i
< n
; i
++)
847 cl2
= pressure_classes
[i
];
848 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl2
]);
849 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
850 if (hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
)
851 && (! hard_reg_set_equal_p (temp_hard_regset
,
853 || cl2
== (int) GENERAL_REGS
))
855 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
859 if (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
)
860 && (! hard_reg_set_equal_p (temp_hard_regset2
,
862 || cl
== (int) GENERAL_REGS
))
864 if (hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
))
866 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
868 /* If the current candidate is a subset of a so far added
869 pressure class, don't add it to the list of the pressure
872 pressure_classes
[curr
++] = (enum reg_class
) cl
;
876 #ifdef ENABLE_IRA_CHECKING
878 HARD_REG_SET ignore_hard_regs
;
880 /* Check pressure classes correctness: here we check that hard
881 registers from all register pressure classes contains all hard
882 registers available for the allocation. */
883 CLEAR_HARD_REG_SET (temp_hard_regset
);
884 CLEAR_HARD_REG_SET (temp_hard_regset2
);
885 COPY_HARD_REG_SET (ignore_hard_regs
, no_unit_alloc_regs
);
886 for (cl
= 0; cl
< LIM_REG_CLASSES
; cl
++)
888 /* For some targets (like MIPS with MD_REGS), there are some
889 classes with hard registers available for allocation but
890 not able to hold value of any mode. */
891 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
892 if (contains_reg_of_mode
[cl
][m
])
894 if (m
>= NUM_MACHINE_MODES
)
896 IOR_HARD_REG_SET (ignore_hard_regs
, reg_class_contents
[cl
]);
899 for (i
= 0; i
< n
; i
++)
900 if ((int) pressure_classes
[i
] == cl
)
902 IOR_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
904 IOR_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
906 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
907 /* Some targets (like SPARC with ICC reg) have allocatable regs
908 for which no reg class is defined. */
909 if (REGNO_REG_CLASS (i
) == NO_REGS
)
910 SET_HARD_REG_BIT (ignore_hard_regs
, i
);
911 AND_COMPL_HARD_REG_SET (temp_hard_regset
, ignore_hard_regs
);
912 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, ignore_hard_regs
);
913 ira_assert (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
));
916 ira_pressure_classes_num
= 0;
917 for (i
= 0; i
< n
; i
++)
919 cl
= (int) pressure_classes
[i
];
920 ira_reg_pressure_class_p
[cl
] = true;
921 ira_pressure_classes
[ira_pressure_classes_num
++] = (enum reg_class
) cl
;
923 setup_stack_reg_pressure_class ();
926 /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class
927 whose register move cost between any registers of the class is the
928 same as for all its subclasses. We use the data to speed up the
929 2nd pass of calculations of allocno costs. */
931 setup_uniform_class_p (void)
935 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
937 ira_uniform_class_p
[cl
] = false;
938 if (ira_class_hard_regs_num
[cl
] == 0)
940 /* We cannot use alloc_reg_class_subclasses here because move
941 cost hooks does not take into account that some registers are
942 unavailable for the subtarget. E.g. for i686, INT_SSE_REGS
943 is element of alloc_reg_class_subclasses for GENERAL_REGS
944 because SSE regs are unavailable. */
945 for (i
= 0; (cl2
= reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
; i
++)
947 if (ira_class_hard_regs_num
[cl2
] == 0)
949 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
950 if (contains_reg_of_mode
[cl
][m
] && contains_reg_of_mode
[cl2
][m
])
952 ira_init_register_move_cost_if_necessary ((machine_mode
) m
);
953 if (ira_register_move_cost
[m
][cl
][cl
]
954 != ira_register_move_cost
[m
][cl2
][cl2
])
957 if (m
< NUM_MACHINE_MODES
)
960 if (cl2
== LIM_REG_CLASSES
)
961 ira_uniform_class_p
[cl
] = true;
965 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
966 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
968 Target may have many subtargets and not all target hard registers can
969 be used for allocation, e.g. x86 port in 32-bit mode cannot use
970 hard registers introduced in x86-64 like r8-r15). Some classes
971 might have the same allocatable hard registers, e.g. INDEX_REGS
972 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
973 calculations efforts we introduce allocno classes which contain
974 unique non-empty sets of allocatable hard-registers.
976 Pseudo class cost calculation in ira-costs.c is very expensive.
977 Therefore we are trying to decrease number of classes involved in
978 such calculation. Register classes used in the cost calculation
979 are called important classes. They are allocno classes and other
980 non-empty classes whose allocatable hard register sets are inside
981 of an allocno class hard register set. From the first sight, it
982 looks like that they are just allocno classes. It is not true. In
983 example of x86-port in 32-bit mode, allocno classes will contain
984 GENERAL_REGS but not LEGACY_REGS (because allocatable hard
985 registers are the same for the both classes). The important
986 classes will contain GENERAL_REGS and LEGACY_REGS. It is done
987 because a machine description insn constraint may refers for
988 LEGACY_REGS and code in ira-costs.c is mostly base on investigation
989 of the insn constraints. */
991 setup_allocno_and_important_classes (void)
995 HARD_REG_SET temp_hard_regset2
;
996 static enum reg_class classes
[LIM_REG_CLASSES
+ 1];
999 /* Collect classes which contain unique sets of allocatable hard
1000 registers. Prefer GENERAL_REGS to other classes containing the
1001 same set of hard registers. */
1002 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
1004 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[i
]);
1005 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1006 for (j
= 0; j
< n
; j
++)
1009 COPY_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
1010 AND_COMPL_HARD_REG_SET (temp_hard_regset2
,
1011 no_unit_alloc_regs
);
1012 if (hard_reg_set_equal_p (temp_hard_regset
,
1016 if (j
>= n
|| targetm
.additional_allocno_class_p (i
))
1017 classes
[n
++] = (enum reg_class
) i
;
1018 else if (i
== GENERAL_REGS
)
1019 /* Prefer general regs. For i386 example, it means that
1020 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
1021 (all of them consists of the same available hard
1023 classes
[j
] = (enum reg_class
) i
;
1025 classes
[n
] = LIM_REG_CLASSES
;
1027 /* Set up classes which can be used for allocnos as classes
1028 containing non-empty unique sets of allocatable hard
1030 ira_allocno_classes_num
= 0;
1031 for (i
= 0; (cl
= classes
[i
]) != LIM_REG_CLASSES
; i
++)
1032 if (ira_class_hard_regs_num
[cl
] > 0)
1033 ira_allocno_classes
[ira_allocno_classes_num
++] = (enum reg_class
) cl
;
1034 ira_important_classes_num
= 0;
1035 /* Add non-allocno classes containing to non-empty set of
1036 allocatable hard regs. */
1037 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1038 if (ira_class_hard_regs_num
[cl
] > 0)
1040 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1041 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1043 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1045 COPY_HARD_REG_SET (temp_hard_regset2
,
1046 reg_class_contents
[ira_allocno_classes
[j
]]);
1047 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
1048 if ((enum reg_class
) cl
== ira_allocno_classes
[j
])
1050 else if (hard_reg_set_subset_p (temp_hard_regset
,
1054 if (set_p
&& j
>= ira_allocno_classes_num
)
1055 ira_important_classes
[ira_important_classes_num
++]
1056 = (enum reg_class
) cl
;
1058 /* Now add allocno classes to the important classes. */
1059 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1060 ira_important_classes
[ira_important_classes_num
++]
1061 = ira_allocno_classes
[j
];
1062 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1064 ira_reg_allocno_class_p
[cl
] = false;
1065 ira_reg_pressure_class_p
[cl
] = false;
1067 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1068 ira_reg_allocno_class_p
[ira_allocno_classes
[j
]] = true;
1069 setup_pressure_classes ();
1070 setup_uniform_class_p ();
1073 /* Setup translation in CLASS_TRANSLATE of all classes into a class
1074 given by array CLASSES of length CLASSES_NUM. The function is used
1075 make translation any reg class to an allocno class or to an
1076 pressure class. This translation is necessary for some
1077 calculations when we can use only allocno or pressure classes and
1078 such translation represents an approximate representation of all
1081 The translation in case when allocatable hard register set of a
1082 given class is subset of allocatable hard register set of a class
1083 in CLASSES is pretty simple. We use smallest classes from CLASSES
1084 containing a given class. If allocatable hard register set of a
1085 given class is not a subset of any corresponding set of a class
1086 from CLASSES, we use the cheapest (with load/store point of view)
1087 class from CLASSES whose set intersects with given class set. */
1089 setup_class_translate_array (enum reg_class
*class_translate
,
1090 int classes_num
, enum reg_class
*classes
)
1093 enum reg_class aclass
, best_class
, *cl_ptr
;
1094 int i
, cost
, min_cost
, best_cost
;
1096 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1097 class_translate
[cl
] = NO_REGS
;
1099 for (i
= 0; i
< classes_num
; i
++)
1101 aclass
= classes
[i
];
1102 for (cl_ptr
= &alloc_reg_class_subclasses
[aclass
][0];
1103 (cl
= *cl_ptr
) != LIM_REG_CLASSES
;
1105 if (class_translate
[cl
] == NO_REGS
)
1106 class_translate
[cl
] = aclass
;
1107 class_translate
[aclass
] = aclass
;
1109 /* For classes which are not fully covered by one of given classes
1110 (in other words covered by more one given class), use the
1112 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1114 if (cl
== NO_REGS
|| class_translate
[cl
] != NO_REGS
)
1116 best_class
= NO_REGS
;
1117 best_cost
= INT_MAX
;
1118 for (i
= 0; i
< classes_num
; i
++)
1120 aclass
= classes
[i
];
1121 COPY_HARD_REG_SET (temp_hard_regset
,
1122 reg_class_contents
[aclass
]);
1123 AND_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1124 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1125 if (! hard_reg_set_empty_p (temp_hard_regset
))
1128 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1130 cost
= (ira_memory_move_cost
[mode
][aclass
][0]
1131 + ira_memory_move_cost
[mode
][aclass
][1]);
1132 if (min_cost
> cost
)
1135 if (best_class
== NO_REGS
|| best_cost
> min_cost
)
1137 best_class
= aclass
;
1138 best_cost
= min_cost
;
1142 class_translate
[cl
] = best_class
;
1146 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
1147 IRA_PRESSURE_CLASS_TRANSLATE. */
1149 setup_class_translate (void)
1151 setup_class_translate_array (ira_allocno_class_translate
,
1152 ira_allocno_classes_num
, ira_allocno_classes
);
1153 setup_class_translate_array (ira_pressure_class_translate
,
1154 ira_pressure_classes_num
, ira_pressure_classes
);
1157 /* Order numbers of allocno classes in original target allocno class
1158 array, -1 for non-allocno classes. */
1159 static int allocno_class_order
[N_REG_CLASSES
];
1161 /* The function used to sort the important classes. */
1163 comp_reg_classes_func (const void *v1p
, const void *v2p
)
1165 enum reg_class cl1
= *(const enum reg_class
*) v1p
;
1166 enum reg_class cl2
= *(const enum reg_class
*) v2p
;
1167 enum reg_class tcl1
, tcl2
;
1170 tcl1
= ira_allocno_class_translate
[cl1
];
1171 tcl2
= ira_allocno_class_translate
[cl2
];
1172 if (tcl1
!= NO_REGS
&& tcl2
!= NO_REGS
1173 && (diff
= allocno_class_order
[tcl1
] - allocno_class_order
[tcl2
]) != 0)
1175 return (int) cl1
- (int) cl2
;
1178 /* For correct work of function setup_reg_class_relation we need to
1179 reorder important classes according to the order of their allocno
1180 classes. It places important classes containing the same
1181 allocatable hard register set adjacent to each other and allocno
1182 class with the allocatable hard register set right after the other
1183 important classes with the same set.
1185 In example from comments of function
1186 setup_allocno_and_important_classes, it places LEGACY_REGS and
1187 GENERAL_REGS close to each other and GENERAL_REGS is after
1190 reorder_important_classes (void)
1194 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1195 allocno_class_order
[i
] = -1;
1196 for (i
= 0; i
< ira_allocno_classes_num
; i
++)
1197 allocno_class_order
[ira_allocno_classes
[i
]] = i
;
1198 qsort (ira_important_classes
, ira_important_classes_num
,
1199 sizeof (enum reg_class
), comp_reg_classes_func
);
1200 for (i
= 0; i
< ira_important_classes_num
; i
++)
1201 ira_important_class_nums
[ira_important_classes
[i
]] = i
;
1204 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
1205 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
1206 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
1207 please see corresponding comments in ira-int.h. */
1209 setup_reg_class_relations (void)
1211 int i
, cl1
, cl2
, cl3
;
1212 HARD_REG_SET intersection_set
, union_set
, temp_set2
;
1213 bool important_class_p
[N_REG_CLASSES
];
1215 memset (important_class_p
, 0, sizeof (important_class_p
));
1216 for (i
= 0; i
< ira_important_classes_num
; i
++)
1217 important_class_p
[ira_important_classes
[i
]] = true;
1218 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1220 ira_reg_class_super_classes
[cl1
][0] = LIM_REG_CLASSES
;
1221 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1223 ira_reg_classes_intersect_p
[cl1
][cl2
] = false;
1224 ira_reg_class_intersect
[cl1
][cl2
] = NO_REGS
;
1225 ira_reg_class_subset
[cl1
][cl2
] = NO_REGS
;
1226 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl1
]);
1227 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1228 COPY_HARD_REG_SET (temp_set2
, reg_class_contents
[cl2
]);
1229 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1230 if (hard_reg_set_empty_p (temp_hard_regset
)
1231 && hard_reg_set_empty_p (temp_set2
))
1233 /* The both classes have no allocatable hard registers
1234 -- take all class hard registers into account and use
1235 reg_class_subunion and reg_class_superunion. */
1238 cl3
= reg_class_subclasses
[cl1
][i
];
1239 if (cl3
== LIM_REG_CLASSES
)
1241 if (reg_class_subset_p (ira_reg_class_intersect
[cl1
][cl2
],
1242 (enum reg_class
) cl3
))
1243 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1245 ira_reg_class_subunion
[cl1
][cl2
] = reg_class_subunion
[cl1
][cl2
];
1246 ira_reg_class_superunion
[cl1
][cl2
] = reg_class_superunion
[cl1
][cl2
];
1249 ira_reg_classes_intersect_p
[cl1
][cl2
]
1250 = hard_reg_set_intersect_p (temp_hard_regset
, temp_set2
);
1251 if (important_class_p
[cl1
] && important_class_p
[cl2
]
1252 && hard_reg_set_subset_p (temp_hard_regset
, temp_set2
))
1254 /* CL1 and CL2 are important classes and CL1 allocatable
1255 hard register set is inside of CL2 allocatable hard
1256 registers -- make CL1 a superset of CL2. */
1259 p
= &ira_reg_class_super_classes
[cl1
][0];
1260 while (*p
!= LIM_REG_CLASSES
)
1262 *p
++ = (enum reg_class
) cl2
;
1263 *p
= LIM_REG_CLASSES
;
1265 ira_reg_class_subunion
[cl1
][cl2
] = NO_REGS
;
1266 ira_reg_class_superunion
[cl1
][cl2
] = NO_REGS
;
1267 COPY_HARD_REG_SET (intersection_set
, reg_class_contents
[cl1
]);
1268 AND_HARD_REG_SET (intersection_set
, reg_class_contents
[cl2
]);
1269 AND_COMPL_HARD_REG_SET (intersection_set
, no_unit_alloc_regs
);
1270 COPY_HARD_REG_SET (union_set
, reg_class_contents
[cl1
]);
1271 IOR_HARD_REG_SET (union_set
, reg_class_contents
[cl2
]);
1272 AND_COMPL_HARD_REG_SET (union_set
, no_unit_alloc_regs
);
1273 for (cl3
= 0; cl3
< N_REG_CLASSES
; cl3
++)
1275 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl3
]);
1276 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1277 if (hard_reg_set_subset_p (temp_hard_regset
, intersection_set
))
1279 /* CL3 allocatable hard register set is inside of
1280 intersection of allocatable hard register sets
1282 if (important_class_p
[cl3
])
1287 [(int) ira_reg_class_intersect
[cl1
][cl2
]]);
1288 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1289 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1290 /* If the allocatable hard register sets are
1291 the same, prefer GENERAL_REGS or the
1292 smallest class for debugging
1294 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1295 && (cl3
== GENERAL_REGS
1296 || ((ira_reg_class_intersect
[cl1
][cl2
]
1298 && hard_reg_set_subset_p
1299 (reg_class_contents
[cl3
],
1302 ira_reg_class_intersect
[cl1
][cl2
]])))))
1303 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1307 reg_class_contents
[(int) ira_reg_class_subset
[cl1
][cl2
]]);
1308 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1309 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1310 /* Ignore unavailable hard registers and prefer
1311 smallest class for debugging purposes. */
1312 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1313 && hard_reg_set_subset_p
1314 (reg_class_contents
[cl3
],
1316 [(int) ira_reg_class_subset
[cl1
][cl2
]])))
1317 ira_reg_class_subset
[cl1
][cl2
] = (enum reg_class
) cl3
;
1319 if (important_class_p
[cl3
]
1320 && hard_reg_set_subset_p (temp_hard_regset
, union_set
))
1322 /* CL3 allocatable hard register set is inside of
1323 union of allocatable hard register sets of CL1
1327 reg_class_contents
[(int) ira_reg_class_subunion
[cl1
][cl2
]]);
1328 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1329 if (ira_reg_class_subunion
[cl1
][cl2
] == NO_REGS
1330 || (hard_reg_set_subset_p (temp_set2
, temp_hard_regset
)
1332 && (! hard_reg_set_equal_p (temp_set2
,
1334 || cl3
== GENERAL_REGS
1335 /* If the allocatable hard register sets are the
1336 same, prefer GENERAL_REGS or the smallest
1337 class for debugging purposes. */
1338 || (ira_reg_class_subunion
[cl1
][cl2
] != GENERAL_REGS
1339 && hard_reg_set_subset_p
1340 (reg_class_contents
[cl3
],
1342 [(int) ira_reg_class_subunion
[cl1
][cl2
]])))))
1343 ira_reg_class_subunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1345 if (hard_reg_set_subset_p (union_set
, temp_hard_regset
))
1347 /* CL3 allocatable hard register set contains union
1348 of allocatable hard register sets of CL1 and
1352 reg_class_contents
[(int) ira_reg_class_superunion
[cl1
][cl2
]]);
1353 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1354 if (ira_reg_class_superunion
[cl1
][cl2
] == NO_REGS
1355 || (hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1357 && (! hard_reg_set_equal_p (temp_set2
,
1359 || cl3
== GENERAL_REGS
1360 /* If the allocatable hard register sets are the
1361 same, prefer GENERAL_REGS or the smallest
1362 class for debugging purposes. */
1363 || (ira_reg_class_superunion
[cl1
][cl2
] != GENERAL_REGS
1364 && hard_reg_set_subset_p
1365 (reg_class_contents
[cl3
],
1367 [(int) ira_reg_class_superunion
[cl1
][cl2
]])))))
1368 ira_reg_class_superunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1375 /* Output all uniform and important classes into file F. */
1377 print_uniform_and_important_classes (FILE *f
)
1381 fprintf (f
, "Uniform classes:\n");
1382 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1383 if (ira_uniform_class_p
[cl
])
1384 fprintf (f
, " %s", reg_class_names
[cl
]);
1385 fprintf (f
, "\nImportant classes:\n");
1386 for (i
= 0; i
< ira_important_classes_num
; i
++)
1387 fprintf (f
, " %s", reg_class_names
[ira_important_classes
[i
]]);
1391 /* Output all possible allocno or pressure classes and their
1392 translation map into file F. */
1394 print_translated_classes (FILE *f
, bool pressure_p
)
1396 int classes_num
= (pressure_p
1397 ? ira_pressure_classes_num
: ira_allocno_classes_num
);
1398 enum reg_class
*classes
= (pressure_p
1399 ? ira_pressure_classes
: ira_allocno_classes
);
1400 enum reg_class
*class_translate
= (pressure_p
1401 ? ira_pressure_class_translate
1402 : ira_allocno_class_translate
);
1405 fprintf (f
, "%s classes:\n", pressure_p
? "Pressure" : "Allocno");
1406 for (i
= 0; i
< classes_num
; i
++)
1407 fprintf (f
, " %s", reg_class_names
[classes
[i
]]);
1408 fprintf (f
, "\nClass translation:\n");
1409 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1410 fprintf (f
, " %s -> %s\n", reg_class_names
[i
],
1411 reg_class_names
[class_translate
[i
]]);
1414 /* Output all possible allocno and translation classes and the
1415 translation maps into stderr. */
1417 ira_debug_allocno_classes (void)
1419 print_uniform_and_important_classes (stderr
);
1420 print_translated_classes (stderr
, false);
1421 print_translated_classes (stderr
, true);
1424 /* Set up different arrays concerning class subsets, allocno and
1425 important classes. */
1427 find_reg_classes (void)
1429 setup_allocno_and_important_classes ();
1430 setup_class_translate ();
1431 reorder_important_classes ();
1432 setup_reg_class_relations ();
1437 /* Set up the array above. */
1439 setup_hard_regno_aclass (void)
1443 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1446 ira_hard_regno_allocno_class
[i
]
1447 = (TEST_HARD_REG_BIT (no_unit_alloc_regs
, i
)
1449 : ira_allocno_class_translate
[REGNO_REG_CLASS (i
)]);
1453 ira_hard_regno_allocno_class
[i
] = NO_REGS
;
1454 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1456 cl
= ira_allocno_classes
[j
];
1457 if (ira_class_hard_reg_index
[cl
][i
] >= 0)
1459 ira_hard_regno_allocno_class
[i
] = cl
;
1469 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
1471 setup_reg_class_nregs (void)
1475 for (m
= 0; m
< MAX_MACHINE_MODE
; m
++)
1477 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1478 ira_reg_class_max_nregs
[cl
][m
]
1479 = ira_reg_class_min_nregs
[cl
][m
]
1480 = targetm
.class_max_nregs ((reg_class_t
) cl
, (machine_mode
) m
);
1481 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1483 (cl2
= alloc_reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
;
1485 if (ira_reg_class_min_nregs
[cl2
][m
]
1486 < ira_reg_class_min_nregs
[cl
][m
])
1487 ira_reg_class_min_nregs
[cl
][m
] = ira_reg_class_min_nregs
[cl2
][m
];
1493 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON.
1494 This function is called once IRA_CLASS_HARD_REGS has been initialized. */
1496 setup_prohibited_class_mode_regs (void)
1498 int j
, k
, hard_regno
, cl
, last_hard_regno
, count
;
1500 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1502 COPY_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
1503 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1504 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1507 last_hard_regno
= -1;
1508 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs
[cl
][j
]);
1509 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1511 hard_regno
= ira_class_hard_regs
[cl
][k
];
1512 if (!targetm
.hard_regno_mode_ok (hard_regno
, (machine_mode
) j
))
1513 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1515 else if (in_hard_reg_set_p (temp_hard_regset
,
1516 (machine_mode
) j
, hard_regno
))
1518 last_hard_regno
= hard_regno
;
1522 ira_class_singleton
[cl
][j
] = (count
== 1 ? last_hard_regno
: -1);
1527 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
1528 spanning from one register pressure class to another one. It is
1529 called after defining the pressure classes. */
1531 clarify_prohibited_class_mode_regs (void)
1533 int j
, k
, hard_regno
, cl
, pclass
, nregs
;
1535 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1536 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1538 CLEAR_HARD_REG_SET (ira_useful_class_mode_regs
[cl
][j
]);
1539 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1541 hard_regno
= ira_class_hard_regs
[cl
][k
];
1542 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
], hard_regno
))
1544 nregs
= hard_regno_nregs (hard_regno
, (machine_mode
) j
);
1545 if (hard_regno
+ nregs
> FIRST_PSEUDO_REGISTER
)
1547 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1551 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1552 for (nregs
-- ;nregs
>= 0; nregs
--)
1553 if (((enum reg_class
) pclass
1554 != ira_pressure_class_translate
[REGNO_REG_CLASS
1555 (hard_regno
+ nregs
)]))
1557 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1561 if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1563 add_to_hard_reg_set (&ira_useful_class_mode_regs
[cl
][j
],
1564 (machine_mode
) j
, hard_regno
);
1569 /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST
1570 and IRA_MAY_MOVE_OUT_COST for MODE. */
1572 ira_init_register_move_cost (machine_mode mode
)
1574 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
1575 bool all_match
= true;
1576 unsigned int i
, cl1
, cl2
;
1577 HARD_REG_SET ok_regs
;
1579 ira_assert (ira_register_move_cost
[mode
] == NULL
1580 && ira_may_move_in_cost
[mode
] == NULL
1581 && ira_may_move_out_cost
[mode
] == NULL
);
1582 CLEAR_HARD_REG_SET (ok_regs
);
1583 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1584 if (targetm
.hard_regno_mode_ok (i
, mode
))
1585 SET_HARD_REG_BIT (ok_regs
, i
);
1587 /* Note that we might be asked about the move costs of modes that
1588 cannot be stored in any hard register, for example if an inline
1589 asm tries to create a register operand with an impossible mode.
1590 We therefore can't assert have_regs_of_mode[mode] here. */
1591 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1592 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1595 if (!hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[cl1
])
1596 || !hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[cl2
]))
1598 if ((ira_reg_class_max_nregs
[cl1
][mode
]
1599 > ira_class_hard_regs_num
[cl1
])
1600 || (ira_reg_class_max_nregs
[cl2
][mode
]
1601 > ira_class_hard_regs_num
[cl2
]))
1604 cost
= (ira_memory_move_cost
[mode
][cl1
][0]
1605 + ira_memory_move_cost
[mode
][cl2
][1]) * 2;
1609 cost
= register_move_cost (mode
, (enum reg_class
) cl1
,
1610 (enum reg_class
) cl2
);
1611 ira_assert (cost
< 65535);
1613 all_match
&= (last_move_cost
[cl1
][cl2
] == cost
);
1614 last_move_cost
[cl1
][cl2
] = cost
;
1616 if (all_match
&& last_mode_for_init_move_cost
!= -1)
1618 ira_register_move_cost
[mode
]
1619 = ira_register_move_cost
[last_mode_for_init_move_cost
];
1620 ira_may_move_in_cost
[mode
]
1621 = ira_may_move_in_cost
[last_mode_for_init_move_cost
];
1622 ira_may_move_out_cost
[mode
]
1623 = ira_may_move_out_cost
[last_mode_for_init_move_cost
];
1626 last_mode_for_init_move_cost
= mode
;
1627 ira_register_move_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1628 ira_may_move_in_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1629 ira_may_move_out_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1630 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1631 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1634 enum reg_class
*p1
, *p2
;
1636 if (last_move_cost
[cl1
][cl2
] == 65535)
1638 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1639 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1640 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1644 cost
= last_move_cost
[cl1
][cl2
];
1646 for (p2
= ®_class_subclasses
[cl2
][0];
1647 *p2
!= LIM_REG_CLASSES
; p2
++)
1648 if (ira_class_hard_regs_num
[*p2
] > 0
1649 && (ira_reg_class_max_nregs
[*p2
][mode
]
1650 <= ira_class_hard_regs_num
[*p2
]))
1651 cost
= MAX (cost
, ira_register_move_cost
[mode
][cl1
][*p2
]);
1653 for (p1
= ®_class_subclasses
[cl1
][0];
1654 *p1
!= LIM_REG_CLASSES
; p1
++)
1655 if (ira_class_hard_regs_num
[*p1
] > 0
1656 && (ira_reg_class_max_nregs
[*p1
][mode
]
1657 <= ira_class_hard_regs_num
[*p1
]))
1658 cost
= MAX (cost
, ira_register_move_cost
[mode
][*p1
][cl2
]);
1660 ira_assert (cost
<= 65535);
1661 ira_register_move_cost
[mode
][cl1
][cl2
] = cost
;
1663 if (ira_class_subset_p
[cl1
][cl2
])
1664 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 0;
1666 ira_may_move_in_cost
[mode
][cl1
][cl2
] = cost
;
1668 if (ira_class_subset_p
[cl2
][cl1
])
1669 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 0;
1671 ira_may_move_out_cost
[mode
][cl1
][cl2
] = cost
;
1678 /* This is called once during compiler work. It sets up
1679 different arrays whose values don't depend on the compiled
1682 ira_init_once (void)
1684 ira_init_costs_once ();
1687 ira_use_lra_p
= targetm
.lra_p ();
1690 /* Free ira_max_register_move_cost, ira_may_move_in_cost and
1691 ira_may_move_out_cost for each mode. */
1693 target_ira_int::free_register_move_costs (void)
1697 /* Reset move_cost and friends, making sure we only free shared
1698 table entries once. */
1699 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1700 if (x_ira_register_move_cost
[mode
])
1703 i
< mode
&& (x_ira_register_move_cost
[i
]
1704 != x_ira_register_move_cost
[mode
]);
1709 free (x_ira_register_move_cost
[mode
]);
1710 free (x_ira_may_move_in_cost
[mode
]);
1711 free (x_ira_may_move_out_cost
[mode
]);
1714 memset (x_ira_register_move_cost
, 0, sizeof x_ira_register_move_cost
);
1715 memset (x_ira_may_move_in_cost
, 0, sizeof x_ira_may_move_in_cost
);
1716 memset (x_ira_may_move_out_cost
, 0, sizeof x_ira_may_move_out_cost
);
1717 last_mode_for_init_move_cost
= -1;
1720 target_ira_int::~target_ira_int ()
1723 free_register_move_costs ();
1726 /* This is called every time when register related information is
1731 this_target_ira_int
->free_register_move_costs ();
1732 setup_reg_mode_hard_regset ();
1733 setup_alloc_regs (flag_omit_frame_pointer
!= 0);
1734 setup_class_subset_and_memory_move_costs ();
1735 setup_reg_class_nregs ();
1736 setup_prohibited_class_mode_regs ();
1737 find_reg_classes ();
1738 clarify_prohibited_class_mode_regs ();
1739 setup_hard_regno_aclass ();
1744 #define ira_prohibited_mode_move_regs_initialized_p \
1745 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p)
1747 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */
1749 setup_prohibited_mode_move_regs (void)
1752 rtx test_reg1
, test_reg2
, move_pat
;
1753 rtx_insn
*move_insn
;
1755 if (ira_prohibited_mode_move_regs_initialized_p
)
1757 ira_prohibited_mode_move_regs_initialized_p
= true;
1758 test_reg1
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
1759 test_reg2
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 2);
1760 move_pat
= gen_rtx_SET (test_reg1
, test_reg2
);
1761 move_insn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, move_pat
, 0, -1, 0);
1762 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1764 SET_HARD_REG_SET (ira_prohibited_mode_move_regs
[i
]);
1765 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1767 if (!targetm
.hard_regno_mode_ok (j
, (machine_mode
) i
))
1769 set_mode_and_regno (test_reg1
, (machine_mode
) i
, j
);
1770 set_mode_and_regno (test_reg2
, (machine_mode
) i
, j
);
1771 INSN_CODE (move_insn
) = -1;
1772 recog_memoized (move_insn
);
1773 if (INSN_CODE (move_insn
) < 0)
1775 extract_insn (move_insn
);
1776 /* We don't know whether the move will be in code that is optimized
1777 for size or speed, so consider all enabled alternatives. */
1778 if (! constrain_operands (1, get_enabled_alternatives (move_insn
)))
1780 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs
[i
], j
);
1787 /* Extract INSN and return the set of alternatives that we should consider.
1788 This excludes any alternatives whose constraints are obviously impossible
1789 to meet (e.g. because the constraint requires a constant and the operand
1792 ira_setup_alts (rtx_insn
*insn
)
1794 /* MAP nalt * nop -> start of constraints for given operand and
1796 static vec
<const char *> insn_constraints
;
1800 int commutative
= -1;
1802 extract_insn (insn
);
1803 alternative_mask preferred
= get_preferred_alternatives (insn
);
1804 alternative_mask alts
= 0;
1805 insn_constraints
.release ();
1806 insn_constraints
.safe_grow_cleared (recog_data
.n_operands
1807 * recog_data
.n_alternatives
+ 1);
1808 /* Check that the hard reg set is enough for holding all
1809 alternatives. It is hard to imagine the situation when the
1810 assertion is wrong. */
1811 ira_assert (recog_data
.n_alternatives
1812 <= (int) MAX (sizeof (HARD_REG_ELT_TYPE
) * CHAR_BIT
,
1813 FIRST_PSEUDO_REGISTER
));
1814 for (curr_swapped
= false;; curr_swapped
= true)
1816 /* Calculate some data common for all alternatives to speed up the
1818 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1820 for (nalt
= 0, p
= recog_data
.constraints
[nop
];
1821 nalt
< recog_data
.n_alternatives
;
1824 insn_constraints
[nop
* recog_data
.n_alternatives
+ nalt
] = p
;
1825 while (*p
&& *p
!= ',')
1827 /* We only support one commutative marker, the first
1828 one. We already set commutative above. */
1829 if (*p
== '%' && commutative
< 0)
1837 for (nalt
= 0; nalt
< recog_data
.n_alternatives
; nalt
++)
1839 if (!TEST_BIT (preferred
, nalt
) || TEST_BIT (alts
, nalt
))
1842 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1846 rtx op
= recog_data
.operand
[nop
];
1847 p
= insn_constraints
[nop
* recog_data
.n_alternatives
+ nalt
];
1848 if (*p
== 0 || *p
== ',')
1852 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
1863 /* The commutative modifier is handled above. */
1866 case '0': case '1': case '2': case '3': case '4':
1867 case '5': case '6': case '7': case '8': case '9':
1877 enum constraint_num cn
= lookup_constraint (p
);
1878 switch (get_constraint_type (cn
))
1881 if (reg_class_for_constraint (cn
) != NO_REGS
)
1886 if (CONST_INT_P (op
)
1887 && (insn_const_int_ok_for_constraint
1894 case CT_SPECIAL_MEMORY
:
1898 if (constraint_satisfied_p (op
, cn
))
1905 while (p
+= len
, c
);
1910 if (nop
>= recog_data
.n_operands
)
1911 alts
|= ALTERNATIVE_BIT (nalt
);
1913 if (commutative
< 0)
1915 /* Swap forth and back to avoid changing recog_data. */
1916 std::swap (recog_data
.operand
[commutative
],
1917 recog_data
.operand
[commutative
+ 1]);
1924 /* Return the number of the output non-early clobber operand which
1925 should be the same in any case as operand with number OP_NUM (or
1926 negative value if there is no such operand). The function takes
1927 only really possible alternatives into consideration. */
1929 ira_get_dup_out_num (int op_num
, alternative_mask alts
)
1931 int curr_alt
, c
, original
, dup
;
1932 bool ignore_p
, use_commut_op_p
;
1935 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
1937 /* We should find duplications only for input operands. */
1938 if (recog_data
.operand_type
[op_num
] != OP_IN
)
1940 str
= recog_data
.constraints
[op_num
];
1941 use_commut_op_p
= false;
1944 rtx op
= recog_data
.operand
[op_num
];
1946 for (curr_alt
= 0, ignore_p
= !TEST_BIT (alts
, curr_alt
),
1957 ignore_p
= !TEST_BIT (alts
, curr_alt
);
1959 else if (! ignore_p
)
1966 enum constraint_num cn
= lookup_constraint (str
);
1967 enum reg_class cl
= reg_class_for_constraint (cn
);
1969 && !targetm
.class_likely_spilled_p (cl
))
1971 if (constraint_satisfied_p (op
, cn
))
1976 case '0': case '1': case '2': case '3': case '4':
1977 case '5': case '6': case '7': case '8': case '9':
1978 if (original
!= -1 && original
!= c
)
1983 str
+= CONSTRAINT_LEN (c
, str
);
1988 for (ignore_p
= false, str
= recog_data
.constraints
[original
- '0'];
1996 else if (*str
== '#')
1998 else if (! ignore_p
)
2001 dup
= original
- '0';
2002 /* It is better ignore an alternative with early clobber. */
2003 else if (*str
== '&')
2009 if (use_commut_op_p
)
2011 use_commut_op_p
= true;
2012 if (recog_data
.constraints
[op_num
][0] == '%')
2013 str
= recog_data
.constraints
[op_num
+ 1];
2014 else if (op_num
> 0 && recog_data
.constraints
[op_num
- 1][0] == '%')
2015 str
= recog_data
.constraints
[op_num
- 1];
2024 /* Search forward to see if the source register of a copy insn dies
2025 before either it or the destination register is modified, but don't
2026 scan past the end of the basic block. If so, we can replace the
2027 source with the destination and let the source die in the copy
2030 This will reduce the number of registers live in that range and may
2031 enable the destination and the source coalescing, thus often saving
2032 one register in addition to a register-register copy. */
2035 decrease_live_ranges_number (void)
2039 rtx set
, src
, dest
, dest_death
, note
;
2043 if (! flag_expensive_optimizations
)
2047 fprintf (ira_dump_file
, "Starting decreasing number of live ranges...\n");
2049 FOR_EACH_BB_FN (bb
, cfun
)
2050 FOR_BB_INSNS (bb
, insn
)
2052 set
= single_set (insn
);
2055 src
= SET_SRC (set
);
2056 dest
= SET_DEST (set
);
2057 if (! REG_P (src
) || ! REG_P (dest
)
2058 || find_reg_note (insn
, REG_DEAD
, src
))
2060 sregno
= REGNO (src
);
2061 dregno
= REGNO (dest
);
2063 /* We don't want to mess with hard regs if register classes
2065 if (sregno
== dregno
2066 || (targetm
.small_register_classes_for_mode_p (GET_MODE (src
))
2067 && (sregno
< FIRST_PSEUDO_REGISTER
2068 || dregno
< FIRST_PSEUDO_REGISTER
))
2069 /* We don't see all updates to SP if they are in an
2070 auto-inc memory reference, so we must disallow this
2071 optimization on them. */
2072 || sregno
== STACK_POINTER_REGNUM
2073 || dregno
== STACK_POINTER_REGNUM
)
2076 dest_death
= NULL_RTX
;
2078 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
2082 if (BLOCK_FOR_INSN (p
) != bb
)
2085 if (reg_set_p (src
, p
) || reg_set_p (dest
, p
)
2086 /* If SRC is an asm-declared register, it must not be
2087 replaced in any asm. Unfortunately, the REG_EXPR
2088 tree for the asm variable may be absent in the SRC
2089 rtx, so we can't check the actual register
2090 declaration easily (the asm operand will have it,
2091 though). To avoid complicating the test for a rare
2092 case, we just don't perform register replacement
2093 for a hard reg mentioned in an asm. */
2094 || (sregno
< FIRST_PSEUDO_REGISTER
2095 && asm_noperands (PATTERN (p
)) >= 0
2096 && reg_overlap_mentioned_p (src
, PATTERN (p
)))
2097 /* Don't change hard registers used by a call. */
2098 || (CALL_P (p
) && sregno
< FIRST_PSEUDO_REGISTER
2099 && find_reg_fusage (p
, USE
, src
))
2100 /* Don't change a USE of a register. */
2101 || (GET_CODE (PATTERN (p
)) == USE
2102 && reg_overlap_mentioned_p (src
, XEXP (PATTERN (p
), 0))))
2105 /* See if all of SRC dies in P. This test is slightly
2106 more conservative than it needs to be. */
2107 if ((note
= find_regno_note (p
, REG_DEAD
, sregno
))
2108 && GET_MODE (XEXP (note
, 0)) == GET_MODE (src
))
2112 /* We can do the optimization. Scan forward from INSN
2113 again, replacing regs as we go. Set FAILED if a
2114 replacement can't be done. In that case, we can't
2115 move the death note for SRC. This should be
2118 /* Set to stop at next insn. */
2119 for (q
= next_real_insn (insn
);
2120 q
!= next_real_insn (p
);
2121 q
= next_real_insn (q
))
2123 if (reg_overlap_mentioned_p (src
, PATTERN (q
)))
2125 /* If SRC is a hard register, we might miss
2126 some overlapping registers with
2127 validate_replace_rtx, so we would have to
2128 undo it. We can't if DEST is present in
2129 the insn, so fail in that combination of
2131 if (sregno
< FIRST_PSEUDO_REGISTER
2132 && reg_mentioned_p (dest
, PATTERN (q
)))
2135 /* Attempt to replace all uses. */
2136 else if (!validate_replace_rtx (src
, dest
, q
))
2139 /* If this succeeded, but some part of the
2140 register is still present, undo the
2142 else if (sregno
< FIRST_PSEUDO_REGISTER
2143 && reg_overlap_mentioned_p (src
, PATTERN (q
)))
2145 validate_replace_rtx (dest
, src
, q
);
2150 /* If DEST dies here, remove the death note and
2151 save it for later. Make sure ALL of DEST dies
2152 here; again, this is overly conservative. */
2154 && (dest_death
= find_regno_note (q
, REG_DEAD
, dregno
)))
2156 if (GET_MODE (XEXP (dest_death
, 0)) == GET_MODE (dest
))
2157 remove_note (q
, dest_death
);
2168 /* Move death note of SRC from P to INSN. */
2169 remove_note (p
, note
);
2170 XEXP (note
, 1) = REG_NOTES (insn
);
2171 REG_NOTES (insn
) = note
;
2174 /* DEST is also dead if INSN has a REG_UNUSED note for
2178 = find_regno_note (insn
, REG_UNUSED
, dregno
)))
2180 PUT_REG_NOTE_KIND (dest_death
, REG_DEAD
);
2181 remove_note (insn
, dest_death
);
2184 /* Put death note of DEST on P if we saw it die. */
2187 XEXP (dest_death
, 1) = REG_NOTES (p
);
2188 REG_NOTES (p
) = dest_death
;
2193 /* If SRC is a hard register which is set or killed in
2194 some other way, we can't do this optimization. */
2195 else if (sregno
< FIRST_PSEUDO_REGISTER
&& dead_or_set_p (p
, src
))
2203 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */
2205 ira_bad_reload_regno_1 (int regno
, rtx x
)
2209 enum reg_class pref
;
2211 /* We only deal with pseudo regs. */
2212 if (! x
|| GET_CODE (x
) != REG
)
2215 x_regno
= REGNO (x
);
2216 if (x_regno
< FIRST_PSEUDO_REGISTER
)
2219 /* If the pseudo prefers REGNO explicitly, then do not consider
2220 REGNO a bad spill choice. */
2221 pref
= reg_preferred_class (x_regno
);
2222 if (reg_class_size
[pref
] == 1)
2223 return !TEST_HARD_REG_BIT (reg_class_contents
[pref
], regno
);
2225 /* If the pseudo conflicts with REGNO, then we consider REGNO a
2226 poor choice for a reload regno. */
2227 a
= ira_regno_allocno_map
[x_regno
];
2228 n
= ALLOCNO_NUM_OBJECTS (a
);
2229 for (i
= 0; i
< n
; i
++)
2231 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2232 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
))
2238 /* Return nonzero if REGNO is a particularly bad choice for reloading
2241 ira_bad_reload_regno (int regno
, rtx in
, rtx out
)
2243 return (ira_bad_reload_regno_1 (regno
, in
)
2244 || ira_bad_reload_regno_1 (regno
, out
));
2247 /* Add register clobbers from asm statements. */
2249 compute_regs_asm_clobbered (void)
2253 FOR_EACH_BB_FN (bb
, cfun
)
2256 FOR_BB_INSNS_REVERSE (bb
, insn
)
2260 if (NONDEBUG_INSN_P (insn
) && asm_noperands (PATTERN (insn
)) >= 0)
2261 FOR_EACH_INSN_DEF (def
, insn
)
2263 unsigned int dregno
= DF_REF_REGNO (def
);
2264 if (HARD_REGISTER_NUM_P (dregno
))
2265 add_to_hard_reg_set (&crtl
->asm_clobbers
,
2266 GET_MODE (DF_REF_REAL_REG (def
)),
2274 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and
2277 ira_setup_eliminable_regset (void)
2280 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2282 /* Setup is_leaf as frame_pointer_required may use it. This function
2283 is called by sched_init before ira if scheduling is enabled. */
2284 crtl
->is_leaf
= leaf_function_p ();
2286 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore
2287 sp for alloca. So we can't eliminate the frame pointer in that
2288 case. At some point, we should improve this by emitting the
2289 sp-adjusting insns for this case. */
2290 frame_pointer_needed
2291 = (! flag_omit_frame_pointer
2292 || (cfun
->calls_alloca
&& EXIT_IGNORE_STACK
)
2293 /* We need the frame pointer to catch stack overflow exceptions if
2294 the stack pointer is moving (as for the alloca case just above). */
2295 || (STACK_CHECK_MOVING_SP
2298 && cfun
->can_throw_non_call_exceptions
)
2299 || crtl
->accesses_prior_frames
2300 || (SUPPORTS_STACK_ALIGNMENT
&& crtl
->stack_realign_needed
)
2301 || targetm
.frame_pointer_required ());
2303 /* The chance that FRAME_POINTER_NEEDED is changed from inspecting
2304 RTL is very small. So if we use frame pointer for RA and RTL
2305 actually prevents this, we will spill pseudos assigned to the
2306 frame pointer in LRA. */
2308 if (frame_pointer_needed
)
2309 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2311 COPY_HARD_REG_SET (ira_no_alloc_regs
, no_unit_alloc_regs
);
2312 CLEAR_HARD_REG_SET (eliminable_regset
);
2314 compute_regs_asm_clobbered ();
2316 /* Build the regset of all eliminable registers and show we can't
2317 use those that we already know won't be eliminated. */
2318 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2321 = (! targetm
.can_eliminate (eliminables
[i
].from
, eliminables
[i
].to
)
2322 || (eliminables
[i
].to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
2324 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, eliminables
[i
].from
))
2326 SET_HARD_REG_BIT (eliminable_regset
, eliminables
[i
].from
);
2329 SET_HARD_REG_BIT (ira_no_alloc_regs
, eliminables
[i
].from
);
2331 else if (cannot_elim
)
2332 error ("%s cannot be used in %<asm%> here",
2333 reg_names
[eliminables
[i
].from
]);
2335 df_set_regs_ever_live (eliminables
[i
].from
, true);
2337 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
)
2339 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
2341 SET_HARD_REG_BIT (eliminable_regset
, HARD_FRAME_POINTER_REGNUM
);
2342 if (frame_pointer_needed
)
2343 SET_HARD_REG_BIT (ira_no_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
2345 else if (frame_pointer_needed
)
2346 error ("%s cannot be used in %<asm%> here",
2347 reg_names
[HARD_FRAME_POINTER_REGNUM
]);
2349 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2355 /* Vector of substitutions of register numbers,
2356 used to map pseudo regs into hardware regs.
2357 This is set up as a result of register allocation.
2358 Element N is the hard reg assigned to pseudo reg N,
2359 or is -1 if no hard reg was assigned.
2360 If N is a hard reg number, element N is N. */
2361 short *reg_renumber
;
2363 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from
2364 the allocation found by IRA. */
2366 setup_reg_renumber (void)
2368 int regno
, hard_regno
;
2370 ira_allocno_iterator ai
;
2372 caller_save_needed
= 0;
2373 FOR_EACH_ALLOCNO (a
, ai
)
2375 if (ira_use_lra_p
&& ALLOCNO_CAP_MEMBER (a
) != NULL
)
2377 /* There are no caps at this point. */
2378 ira_assert (ALLOCNO_CAP_MEMBER (a
) == NULL
);
2379 if (! ALLOCNO_ASSIGNED_P (a
))
2380 /* It can happen if A is not referenced but partially anticipated
2381 somewhere in a region. */
2382 ALLOCNO_ASSIGNED_P (a
) = true;
2383 ira_free_allocno_updated_costs (a
);
2384 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2385 regno
= ALLOCNO_REGNO (a
);
2386 reg_renumber
[regno
] = (hard_regno
< 0 ? -1 : hard_regno
);
2387 if (hard_regno
>= 0)
2390 enum reg_class pclass
;
2393 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
2394 nwords
= ALLOCNO_NUM_OBJECTS (a
);
2395 for (i
= 0; i
< nwords
; i
++)
2397 obj
= ALLOCNO_OBJECT (a
, i
);
2398 IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
2399 reg_class_contents
[pclass
]);
2401 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0
2402 && ira_hard_reg_set_intersection_p (hard_regno
, ALLOCNO_MODE (a
),
2405 ira_assert (!optimize
|| flag_caller_saves
2406 || (ALLOCNO_CALLS_CROSSED_NUM (a
)
2407 == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2408 || regno
>= ira_reg_equiv_len
2409 || ira_equiv_no_lvalue_p (regno
));
2410 caller_save_needed
= 1;
2416 /* Set up allocno assignment flags for further allocation
2419 setup_allocno_assignment_flags (void)
2423 ira_allocno_iterator ai
;
2425 FOR_EACH_ALLOCNO (a
, ai
)
2427 if (! ALLOCNO_ASSIGNED_P (a
))
2428 /* It can happen if A is not referenced but partially anticipated
2429 somewhere in a region. */
2430 ira_free_allocno_updated_costs (a
);
2431 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2432 /* Don't assign hard registers to allocnos which are destination
2433 of removed store at the end of loop. It has no sense to keep
2434 the same value in different hard registers. It is also
2435 impossible to assign hard registers correctly to such
2436 allocnos because the cost info and info about intersected
2437 calls are incorrect for them. */
2438 ALLOCNO_ASSIGNED_P (a
) = (hard_regno
>= 0
2439 || ALLOCNO_EMIT_DATA (a
)->mem_optimized_dest_p
2440 || (ALLOCNO_MEMORY_COST (a
)
2441 - ALLOCNO_CLASS_COST (a
)) < 0);
2444 || ira_hard_reg_in_set_p (hard_regno
, ALLOCNO_MODE (a
),
2445 reg_class_contents
[ALLOCNO_CLASS (a
)]));
2449 /* Evaluate overall allocation cost and the costs for using hard
2450 registers and memory for allocnos. */
2452 calculate_allocation_cost (void)
2454 int hard_regno
, cost
;
2456 ira_allocno_iterator ai
;
2458 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
2459 FOR_EACH_ALLOCNO (a
, ai
)
2461 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2462 ira_assert (hard_regno
< 0
2463 || (ira_hard_reg_in_set_p
2464 (hard_regno
, ALLOCNO_MODE (a
),
2465 reg_class_contents
[ALLOCNO_CLASS (a
)])));
2468 cost
= ALLOCNO_MEMORY_COST (a
);
2469 ira_mem_cost
+= cost
;
2471 else if (ALLOCNO_HARD_REG_COSTS (a
) != NULL
)
2473 cost
= (ALLOCNO_HARD_REG_COSTS (a
)
2474 [ira_class_hard_reg_index
2475 [ALLOCNO_CLASS (a
)][hard_regno
]]);
2476 ira_reg_cost
+= cost
;
2480 cost
= ALLOCNO_CLASS_COST (a
);
2481 ira_reg_cost
+= cost
;
2483 ira_overall_cost
+= cost
;
2486 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
2488 fprintf (ira_dump_file
,
2489 "+++Costs: overall %" PRId64
2495 ira_overall_cost
, ira_reg_cost
, ira_mem_cost
,
2496 ira_load_cost
, ira_store_cost
, ira_shuffle_cost
);
2497 fprintf (ira_dump_file
, "\n+++ move loops %d, new jumps %d\n",
2498 ira_move_loops_num
, ira_additional_jumps_num
);
2503 #ifdef ENABLE_IRA_CHECKING
2504 /* Check the correctness of the allocation. We do need this because
2505 of complicated code to transform more one region internal
2506 representation into one region representation. */
2508 check_allocation (void)
2511 int hard_regno
, nregs
, conflict_nregs
;
2512 ira_allocno_iterator ai
;
2514 FOR_EACH_ALLOCNO (a
, ai
)
2516 int n
= ALLOCNO_NUM_OBJECTS (a
);
2519 if (ALLOCNO_CAP_MEMBER (a
) != NULL
2520 || (hard_regno
= ALLOCNO_HARD_REGNO (a
)) < 0)
2522 nregs
= hard_regno_nregs (hard_regno
, ALLOCNO_MODE (a
));
2524 /* We allocated a single hard register. */
2527 /* We allocated multiple hard registers, and we will test
2528 conflicts in a granularity of single hard regs. */
2531 for (i
= 0; i
< n
; i
++)
2533 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2534 ira_object_t conflict_obj
;
2535 ira_object_conflict_iterator oci
;
2536 int this_regno
= hard_regno
;
2539 if (REG_WORDS_BIG_ENDIAN
)
2540 this_regno
+= n
- i
- 1;
2544 FOR_EACH_OBJECT_CONFLICT (obj
, conflict_obj
, oci
)
2546 ira_allocno_t conflict_a
= OBJECT_ALLOCNO (conflict_obj
);
2547 int conflict_hard_regno
= ALLOCNO_HARD_REGNO (conflict_a
);
2548 if (conflict_hard_regno
< 0)
2551 conflict_nregs
= hard_regno_nregs (conflict_hard_regno
,
2552 ALLOCNO_MODE (conflict_a
));
2554 if (ALLOCNO_NUM_OBJECTS (conflict_a
) > 1
2555 && conflict_nregs
== ALLOCNO_NUM_OBJECTS (conflict_a
))
2557 if (REG_WORDS_BIG_ENDIAN
)
2558 conflict_hard_regno
+= (ALLOCNO_NUM_OBJECTS (conflict_a
)
2559 - OBJECT_SUBWORD (conflict_obj
) - 1);
2561 conflict_hard_regno
+= OBJECT_SUBWORD (conflict_obj
);
2565 if ((conflict_hard_regno
<= this_regno
2566 && this_regno
< conflict_hard_regno
+ conflict_nregs
)
2567 || (this_regno
<= conflict_hard_regno
2568 && conflict_hard_regno
< this_regno
+ nregs
))
2570 fprintf (stderr
, "bad allocation for %d and %d\n",
2571 ALLOCNO_REGNO (a
), ALLOCNO_REGNO (conflict_a
));
2580 /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should
2581 be already calculated. */
2583 setup_reg_equiv_init (void)
2586 int max_regno
= max_reg_num ();
2588 for (i
= 0; i
< max_regno
; i
++)
2589 reg_equiv_init (i
) = ira_reg_equiv
[i
].init_insns
;
2592 /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS
2593 are insns which were generated for such movement. It is assumed
2594 that FROM_REGNO and TO_REGNO always have the same value at the
2595 point of any move containing such registers. This function is used
2596 to update equiv info for register shuffles on the region borders
2597 and for caller save/restore insns. */
2599 ira_update_equiv_info_by_shuffle_insn (int to_regno
, int from_regno
, rtx_insn
*insns
)
2604 if (! ira_reg_equiv
[from_regno
].defined_p
2605 && (! ira_reg_equiv
[to_regno
].defined_p
2606 || ((x
= ira_reg_equiv
[to_regno
].memory
) != NULL_RTX
2607 && ! MEM_READONLY_P (x
))))
2610 if (NEXT_INSN (insn
) != NULL_RTX
)
2612 if (! ira_reg_equiv
[to_regno
].defined_p
)
2614 ira_assert (ira_reg_equiv
[to_regno
].init_insns
== NULL_RTX
);
2617 ira_reg_equiv
[to_regno
].defined_p
= false;
2618 ira_reg_equiv
[to_regno
].memory
2619 = ira_reg_equiv
[to_regno
].constant
2620 = ira_reg_equiv
[to_regno
].invariant
2621 = ira_reg_equiv
[to_regno
].init_insns
= NULL
;
2622 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2623 fprintf (ira_dump_file
,
2624 " Invalidating equiv info for reg %d\n", to_regno
);
2627 /* It is possible that FROM_REGNO still has no equivalence because
2628 in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd
2629 insn was not processed yet. */
2630 if (ira_reg_equiv
[from_regno
].defined_p
)
2632 ira_reg_equiv
[to_regno
].defined_p
= true;
2633 if ((x
= ira_reg_equiv
[from_regno
].memory
) != NULL_RTX
)
2635 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
2636 && ira_reg_equiv
[from_regno
].constant
== NULL_RTX
);
2637 ira_assert (ira_reg_equiv
[to_regno
].memory
== NULL_RTX
2638 || rtx_equal_p (ira_reg_equiv
[to_regno
].memory
, x
));
2639 ira_reg_equiv
[to_regno
].memory
= x
;
2640 if (! MEM_READONLY_P (x
))
2641 /* We don't add the insn to insn init list because memory
2642 equivalence is just to say what memory is better to use
2643 when the pseudo is spilled. */
2646 else if ((x
= ira_reg_equiv
[from_regno
].constant
) != NULL_RTX
)
2648 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
);
2649 ira_assert (ira_reg_equiv
[to_regno
].constant
== NULL_RTX
2650 || rtx_equal_p (ira_reg_equiv
[to_regno
].constant
, x
));
2651 ira_reg_equiv
[to_regno
].constant
= x
;
2655 x
= ira_reg_equiv
[from_regno
].invariant
;
2656 ira_assert (x
!= NULL_RTX
);
2657 ira_assert (ira_reg_equiv
[to_regno
].invariant
== NULL_RTX
2658 || rtx_equal_p (ira_reg_equiv
[to_regno
].invariant
, x
));
2659 ira_reg_equiv
[to_regno
].invariant
= x
;
2661 if (find_reg_note (insn
, REG_EQUIV
, x
) == NULL_RTX
)
2663 note
= set_unique_reg_note (insn
, REG_EQUIV
, copy_rtx (x
));
2664 gcc_assert (note
!= NULL_RTX
);
2665 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2667 fprintf (ira_dump_file
,
2668 " Adding equiv note to insn %u for reg %d ",
2669 INSN_UID (insn
), to_regno
);
2670 dump_value_slim (ira_dump_file
, x
, 1);
2671 fprintf (ira_dump_file
, "\n");
2675 ira_reg_equiv
[to_regno
].init_insns
2676 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
2677 ira_reg_equiv
[to_regno
].init_insns
);
2678 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2679 fprintf (ira_dump_file
,
2680 " Adding equiv init move insn %u to reg %d\n",
2681 INSN_UID (insn
), to_regno
);
2684 /* Fix values of array REG_EQUIV_INIT after live range splitting done
2687 fix_reg_equiv_init (void)
2689 int max_regno
= max_reg_num ();
2690 int i
, new_regno
, max
;
2692 rtx_insn_list
*x
, *next
, *prev
;
2695 if (max_regno_before_ira
< max_regno
)
2697 max
= vec_safe_length (reg_equivs
);
2699 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; i
++)
2700 for (prev
= NULL
, x
= reg_equiv_init (i
);
2706 set
= single_set (insn
);
2707 ira_assert (set
!= NULL_RTX
2708 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))));
2709 if (REG_P (SET_DEST (set
))
2710 && ((int) REGNO (SET_DEST (set
)) == i
2711 || (int) ORIGINAL_REGNO (SET_DEST (set
)) == i
))
2712 new_regno
= REGNO (SET_DEST (set
));
2713 else if (REG_P (SET_SRC (set
))
2714 && ((int) REGNO (SET_SRC (set
)) == i
2715 || (int) ORIGINAL_REGNO (SET_SRC (set
)) == i
))
2716 new_regno
= REGNO (SET_SRC (set
));
2723 /* Remove the wrong list element. */
2724 if (prev
== NULL_RTX
)
2725 reg_equiv_init (i
) = next
;
2727 XEXP (prev
, 1) = next
;
2728 XEXP (x
, 1) = reg_equiv_init (new_regno
);
2729 reg_equiv_init (new_regno
) = x
;
2735 #ifdef ENABLE_IRA_CHECKING
2736 /* Print redundant memory-memory copies. */
2738 print_redundant_copies (void)
2742 ira_copy_t cp
, next_cp
;
2743 ira_allocno_iterator ai
;
2745 FOR_EACH_ALLOCNO (a
, ai
)
2747 if (ALLOCNO_CAP_MEMBER (a
) != NULL
)
2750 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2751 if (hard_regno
>= 0)
2753 for (cp
= ALLOCNO_COPIES (a
); cp
!= NULL
; cp
= next_cp
)
2755 next_cp
= cp
->next_first_allocno_copy
;
2758 next_cp
= cp
->next_second_allocno_copy
;
2759 if (internal_flag_ira_verbose
> 4 && ira_dump_file
!= NULL
2760 && cp
->insn
!= NULL_RTX
2761 && ALLOCNO_HARD_REGNO (cp
->first
) == hard_regno
)
2762 fprintf (ira_dump_file
,
2763 " Redundant move from %d(freq %d):%d\n",
2764 INSN_UID (cp
->insn
), cp
->freq
, hard_regno
);
2770 /* Setup preferred and alternative classes for new pseudo-registers
2771 created by IRA starting with START. */
2773 setup_preferred_alternate_classes_for_new_pseudos (int start
)
2776 int max_regno
= max_reg_num ();
2778 for (i
= start
; i
< max_regno
; i
++)
2780 old_regno
= ORIGINAL_REGNO (regno_reg_rtx
[i
]);
2781 ira_assert (i
!= old_regno
);
2782 setup_reg_classes (i
, reg_preferred_class (old_regno
),
2783 reg_alternate_class (old_regno
),
2784 reg_allocno_class (old_regno
));
2785 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
2786 fprintf (ira_dump_file
,
2787 " New r%d: setting preferred %s, alternative %s\n",
2788 i
, reg_class_names
[reg_preferred_class (old_regno
)],
2789 reg_class_names
[reg_alternate_class (old_regno
)]);
2794 /* The number of entries allocated in reg_info. */
2795 static int allocated_reg_info_size
;
2797 /* Regional allocation can create new pseudo-registers. This function
2798 expands some arrays for pseudo-registers. */
2800 expand_reg_info (void)
2803 int size
= max_reg_num ();
2806 for (i
= allocated_reg_info_size
; i
< size
; i
++)
2807 setup_reg_classes (i
, GENERAL_REGS
, ALL_REGS
, GENERAL_REGS
);
2808 setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size
);
2809 allocated_reg_info_size
= size
;
2812 /* Return TRUE if there is too high register pressure in the function.
2813 It is used to decide when stack slot sharing is worth to do. */
2815 too_high_register_pressure_p (void)
2818 enum reg_class pclass
;
2820 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
2822 pclass
= ira_pressure_classes
[i
];
2823 if (ira_loop_tree_root
->reg_pressure
[pclass
] > 10000)
2831 /* Indicate that hard register number FROM was eliminated and replaced with
2832 an offset from hard register number TO. The status of hard registers live
2833 at the start of a basic block is updated by replacing a use of FROM with
2837 mark_elimination (int from
, int to
)
2842 FOR_EACH_BB_FN (bb
, cfun
)
2845 if (bitmap_bit_p (r
, from
))
2847 bitmap_clear_bit (r
, from
);
2848 bitmap_set_bit (r
, to
);
2852 r
= DF_LIVE_IN (bb
);
2853 if (bitmap_bit_p (r
, from
))
2855 bitmap_clear_bit (r
, from
);
2856 bitmap_set_bit (r
, to
);
2863 /* The length of the following array. */
2864 int ira_reg_equiv_len
;
2866 /* Info about equiv. info for each register. */
2867 struct ira_reg_equiv_s
*ira_reg_equiv
;
2869 /* Expand ira_reg_equiv if necessary. */
2871 ira_expand_reg_equiv (void)
2873 int old
= ira_reg_equiv_len
;
2875 if (ira_reg_equiv_len
> max_reg_num ())
2877 ira_reg_equiv_len
= max_reg_num () * 3 / 2 + 1;
2879 = (struct ira_reg_equiv_s
*) xrealloc (ira_reg_equiv
,
2881 * sizeof (struct ira_reg_equiv_s
));
2882 gcc_assert (old
< ira_reg_equiv_len
);
2883 memset (ira_reg_equiv
+ old
, 0,
2884 sizeof (struct ira_reg_equiv_s
) * (ira_reg_equiv_len
- old
));
2888 init_reg_equiv (void)
2890 ira_reg_equiv_len
= 0;
2891 ira_reg_equiv
= NULL
;
2892 ira_expand_reg_equiv ();
2896 finish_reg_equiv (void)
2898 free (ira_reg_equiv
);
2905 /* Set when a REG_EQUIV note is found or created. Use to
2906 keep track of what memory accesses might be created later,
2911 /* The list of each instruction which initializes this register.
2913 NULL indicates we know nothing about this register's equivalence
2916 An INSN_LIST with a NULL insn indicates this pseudo is already
2917 known to not have a valid equivalence. */
2918 rtx_insn_list
*init_insns
;
2920 /* Loop depth is used to recognize equivalences which appear
2921 to be present within the same loop (or in an inner loop). */
2923 /* Nonzero if this had a preexisting REG_EQUIV note. */
2924 unsigned char is_arg_equivalence
: 1;
2925 /* Set when an attempt should be made to replace a register
2926 with the associated src_p entry. */
2927 unsigned char replace
: 1;
2928 /* Set if this register has no known equivalence. */
2929 unsigned char no_equiv
: 1;
2930 /* Set if this register is mentioned in a paradoxical subreg. */
2931 unsigned char pdx_subregs
: 1;
2934 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
2935 structure for that register. */
2936 static struct equivalence
*reg_equiv
;
2938 /* Used for communication between the following two functions. */
2939 struct equiv_mem_data
2941 /* A MEM that we wish to ensure remains unchanged. */
2944 /* Set true if EQUIV_MEM is modified. */
2945 bool equiv_mem_modified
;
2948 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
2949 Called via note_stores. */
2951 validate_equiv_mem_from_store (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
,
2954 struct equiv_mem_data
*info
= (struct equiv_mem_data
*) data
;
2957 && reg_overlap_mentioned_p (dest
, info
->equiv_mem
))
2959 && anti_dependence (info
->equiv_mem
, dest
)))
2960 info
->equiv_mem_modified
= true;
2963 enum valid_equiv
{ valid_none
, valid_combine
, valid_reload
};
2965 /* Verify that no store between START and the death of REG invalidates
2966 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
2967 by storing into an overlapping memory location, or with a non-const
2970 Return VALID_RELOAD if MEMREF remains valid for both reload and
2971 combine_and_move insns, VALID_COMBINE if only valid for
2972 combine_and_move_insns, and VALID_NONE otherwise. */
2973 static enum valid_equiv
2974 validate_equiv_mem (rtx_insn
*start
, rtx reg
, rtx memref
)
2978 struct equiv_mem_data info
= { memref
, false };
2979 enum valid_equiv ret
= valid_reload
;
2981 /* If the memory reference has side effects or is volatile, it isn't a
2982 valid equivalence. */
2983 if (side_effects_p (memref
))
2986 for (insn
= start
; insn
; insn
= NEXT_INSN (insn
))
2991 if (find_reg_note (insn
, REG_DEAD
, reg
))
2996 /* We can combine a reg def from one insn into a reg use in
2997 another over a call if the memory is readonly or the call
2998 const/pure. However, we can't set reg_equiv notes up for
2999 reload over any call. The problem is the equivalent form
3000 may reference a pseudo which gets assigned a call
3001 clobbered hard reg. When we later replace REG with its
3002 equivalent form, the value in the call-clobbered reg has
3003 been changed and all hell breaks loose. */
3004 ret
= valid_combine
;
3005 if (!MEM_READONLY_P (memref
)
3006 && !RTL_CONST_OR_PURE_CALL_P (insn
))
3010 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, &info
);
3011 if (info
.equiv_mem_modified
)
3014 /* If a register mentioned in MEMREF is modified via an
3015 auto-increment, we lose the equivalence. Do the same if one
3016 dies; although we could extend the life, it doesn't seem worth
3019 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3020 if ((REG_NOTE_KIND (note
) == REG_INC
3021 || REG_NOTE_KIND (note
) == REG_DEAD
)
3022 && REG_P (XEXP (note
, 0))
3023 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
3030 /* Returns zero if X is known to be invariant. */
3032 equiv_init_varies_p (rtx x
)
3034 RTX_CODE code
= GET_CODE (x
);
3041 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
3050 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
3053 if (MEM_VOLATILE_P (x
))
3062 fmt
= GET_RTX_FORMAT (code
);
3063 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3066 if (equiv_init_varies_p (XEXP (x
, i
)))
3069 else if (fmt
[i
] == 'E')
3072 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3073 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
3080 /* Returns nonzero if X (used to initialize register REGNO) is movable.
3081 X is only movable if the registers it uses have equivalent initializations
3082 which appear to be within the same loop (or in an inner loop) and movable
3083 or if they are not candidates for local_alloc and don't vary. */
3085 equiv_init_movable_p (rtx x
, int regno
)
3089 enum rtx_code code
= GET_CODE (x
);
3094 return equiv_init_movable_p (SET_SRC (x
), regno
);
3110 return ((reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
3111 && reg_equiv
[REGNO (x
)].replace
)
3112 || (REG_BASIC_BLOCK (REGNO (x
)) < NUM_FIXED_BLOCKS
3113 && ! rtx_varies_p (x
, 0)));
3115 case UNSPEC_VOLATILE
:
3119 if (MEM_VOLATILE_P (x
))
3128 fmt
= GET_RTX_FORMAT (code
);
3129 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3133 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
3137 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3138 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
3146 static bool memref_referenced_p (rtx memref
, rtx x
, bool read_p
);
3148 /* Auxiliary function for memref_referenced_p. Process setting X for
3151 process_set_for_memref_referenced_p (rtx memref
, rtx x
)
3153 /* If we are setting a MEM, it doesn't count (its address does), but any
3154 other SET_DEST that has a MEM in it is referencing the MEM. */
3157 if (memref_referenced_p (memref
, XEXP (x
, 0), true))
3160 else if (memref_referenced_p (memref
, x
, false))
3166 /* TRUE if X references a memory location (as a read if READ_P) that
3167 would be affected by a store to MEMREF. */
3169 memref_referenced_p (rtx memref
, rtx x
, bool read_p
)
3173 enum rtx_code code
= GET_CODE (x
);
3188 return (reg_equiv
[REGNO (x
)].replacement
3189 && memref_referenced_p (memref
,
3190 reg_equiv
[REGNO (x
)].replacement
, read_p
));
3193 /* Memory X might have another effective type than MEMREF. */
3194 if (read_p
|| true_dependence (memref
, VOIDmode
, x
))
3199 if (process_set_for_memref_referenced_p (memref
, SET_DEST (x
)))
3202 return memref_referenced_p (memref
, SET_SRC (x
), true);
3206 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3215 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3218 return memref_referenced_p (memref
, XEXP (x
, 0), true);
3222 /* op0 = op0 + op1 */
3223 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3226 if (memref_referenced_p (memref
, XEXP (x
, 0), true))
3229 return memref_referenced_p (memref
, XEXP (x
, 1), true);
3235 fmt
= GET_RTX_FORMAT (code
);
3236 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3240 if (memref_referenced_p (memref
, XEXP (x
, i
), read_p
))
3244 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3245 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
), read_p
))
3253 /* TRUE if some insn in the range (START, END] references a memory location
3254 that would be affected by a store to MEMREF.
3256 Callers should not call this routine if START is after END in the
3260 memref_used_between_p (rtx memref
, rtx_insn
*start
, rtx_insn
*end
)
3264 for (insn
= NEXT_INSN (start
);
3265 insn
&& insn
!= NEXT_INSN (end
);
3266 insn
= NEXT_INSN (insn
))
3268 if (!NONDEBUG_INSN_P (insn
))
3271 if (memref_referenced_p (memref
, PATTERN (insn
), false))
3274 /* Nonconst functions may access memory. */
3275 if (CALL_P (insn
) && (! RTL_CONST_CALL_P (insn
)))
3279 gcc_assert (insn
== NEXT_INSN (end
));
3283 /* Mark REG as having no known equivalence.
3284 Some instructions might have been processed before and furnished
3285 with REG_EQUIV notes for this register; these notes will have to be
3287 STORE is the piece of RTL that does the non-constant / conflicting
3288 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
3289 but needs to be there because this function is called from note_stores. */
3291 no_equiv (rtx reg
, const_rtx store ATTRIBUTE_UNUSED
,
3292 void *data ATTRIBUTE_UNUSED
)
3295 rtx_insn_list
*list
;
3299 regno
= REGNO (reg
);
3300 reg_equiv
[regno
].no_equiv
= 1;
3301 list
= reg_equiv
[regno
].init_insns
;
3302 if (list
&& list
->insn () == NULL
)
3304 reg_equiv
[regno
].init_insns
= gen_rtx_INSN_LIST (VOIDmode
, NULL_RTX
, NULL
);
3305 reg_equiv
[regno
].replacement
= NULL_RTX
;
3306 /* This doesn't matter for equivalences made for argument registers, we
3307 should keep their initialization insns. */
3308 if (reg_equiv
[regno
].is_arg_equivalence
)
3310 ira_reg_equiv
[regno
].defined_p
= false;
3311 ira_reg_equiv
[regno
].init_insns
= NULL
;
3312 for (; list
; list
= list
->next ())
3314 rtx_insn
*insn
= list
->insn ();
3315 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
3319 /* Check whether the SUBREG is a paradoxical subreg and set the result
3323 set_paradoxical_subreg (rtx_insn
*insn
)
3325 subrtx_iterator::array_type array
;
3326 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
3328 const_rtx subreg
= *iter
;
3329 if (GET_CODE (subreg
) == SUBREG
)
3331 const_rtx reg
= SUBREG_REG (subreg
);
3332 if (REG_P (reg
) && paradoxical_subreg_p (subreg
))
3333 reg_equiv
[REGNO (reg
)].pdx_subregs
= true;
3338 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the
3339 equivalent replacement. */
3342 adjust_cleared_regs (rtx loc
, const_rtx old_rtx ATTRIBUTE_UNUSED
, void *data
)
3346 bitmap cleared_regs
= (bitmap
) data
;
3347 if (bitmap_bit_p (cleared_regs
, REGNO (loc
)))
3348 return simplify_replace_fn_rtx (copy_rtx (*reg_equiv
[REGNO (loc
)].src_p
),
3349 NULL_RTX
, adjust_cleared_regs
, data
);
3354 /* Given register REGNO is set only once, return true if the defining
3355 insn dominates all uses. */
3358 def_dominates_uses (int regno
)
3360 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3362 struct df_insn_info
*def_info
= DF_REF_INSN_INFO (def
);
3363 /* If this is an artificial def (eh handler regs, hard frame pointer
3364 for non-local goto, regs defined on function entry) then def_info
3365 is NULL and the reg is always live before any use. We might
3366 reasonably return true in that case, but since the only call
3367 of this function is currently here in ira.c when we are looking
3368 at a defining insn we can't have an artificial def as that would
3369 bump DF_REG_DEF_COUNT. */
3370 gcc_assert (DF_REG_DEF_COUNT (regno
) == 1 && def_info
!= NULL
);
3372 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3373 basic_block def_bb
= BLOCK_FOR_INSN (def_insn
);
3375 for (df_ref use
= DF_REG_USE_CHAIN (regno
);
3377 use
= DF_REF_NEXT_REG (use
))
3379 struct df_insn_info
*use_info
= DF_REF_INSN_INFO (use
);
3380 /* Only check real uses, not artificial ones. */
3383 rtx_insn
*use_insn
= DF_REF_INSN (use
);
3384 if (!DEBUG_INSN_P (use_insn
))
3386 basic_block use_bb
= BLOCK_FOR_INSN (use_insn
);
3387 if (use_bb
!= def_bb
3388 ? !dominated_by_p (CDI_DOMINATORS
, use_bb
, def_bb
)
3389 : DF_INSN_INFO_LUID (use_info
) < DF_INSN_INFO_LUID (def_info
))
3397 /* Find registers that are equivalent to a single value throughout the
3398 compilation (either because they can be referenced in memory or are
3399 set once from a single constant). Lower their priority for a
3402 If such a register is only referenced once, try substituting its
3403 value into the using insn. If it succeeds, we can eliminate the
3404 register completely.
3406 Initialize init_insns in ira_reg_equiv array. */
3408 update_equiv_regs (void)
3413 /* Scan insns and set pdx_subregs if the reg is used in a
3414 paradoxical subreg. Don't set such reg equivalent to a mem,
3415 because lra will not substitute such equiv memory in order to
3416 prevent access beyond allocated memory for paradoxical memory subreg. */
3417 FOR_EACH_BB_FN (bb
, cfun
)
3418 FOR_BB_INSNS (bb
, insn
)
3419 if (NONDEBUG_INSN_P (insn
))
3420 set_paradoxical_subreg (insn
);
3422 /* Scan the insns and find which registers have equivalences. Do this
3423 in a separate scan of the insns because (due to -fcse-follow-jumps)
3424 a register can be set below its use. */
3425 bitmap setjmp_crosses
= regstat_get_setjmp_crosses ();
3426 FOR_EACH_BB_FN (bb
, cfun
)
3428 int loop_depth
= bb_loop_depth (bb
);
3430 for (insn
= BB_HEAD (bb
);
3431 insn
!= NEXT_INSN (BB_END (bb
));
3432 insn
= NEXT_INSN (insn
))
3439 if (! INSN_P (insn
))
3442 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3443 if (REG_NOTE_KIND (note
) == REG_INC
)
3444 no_equiv (XEXP (note
, 0), note
, NULL
);
3446 set
= single_set (insn
);
3448 /* If this insn contains more (or less) than a single SET,
3449 only mark all destinations as having no known equivalence. */
3451 || side_effects_p (SET_SRC (set
)))
3453 note_stores (PATTERN (insn
), no_equiv
, NULL
);
3456 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
3460 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
3462 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
3464 note_stores (part
, no_equiv
, NULL
);
3468 dest
= SET_DEST (set
);
3469 src
= SET_SRC (set
);
3471 /* See if this is setting up the equivalence between an argument
3472 register and its stack slot. */
3473 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3476 gcc_assert (REG_P (dest
));
3477 regno
= REGNO (dest
);
3479 /* Note that we don't want to clear init_insns in
3480 ira_reg_equiv even if there are multiple sets of this
3482 reg_equiv
[regno
].is_arg_equivalence
= 1;
3484 /* The insn result can have equivalence memory although
3485 the equivalence is not set up by the insn. We add
3486 this insn to init insns as it is a flag for now that
3487 regno has an equivalence. We will remove the insn
3488 from init insn list later. */
3489 if (rtx_equal_p (src
, XEXP (note
, 0)) || MEM_P (XEXP (note
, 0)))
3490 ira_reg_equiv
[regno
].init_insns
3491 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3492 ira_reg_equiv
[regno
].init_insns
);
3494 /* Continue normally in case this is a candidate for
3501 /* We only handle the case of a pseudo register being set
3502 once, or always to the same value. */
3503 /* ??? The mn10200 port breaks if we add equivalences for
3504 values that need an ADDRESS_REGS register and set them equivalent
3505 to a MEM of a pseudo. The actual problem is in the over-conservative
3506 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
3507 calculate_needs, but we traditionally work around this problem
3508 here by rejecting equivalences when the destination is in a register
3509 that's likely spilled. This is fragile, of course, since the
3510 preferred class of a pseudo depends on all instructions that set
3514 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
3515 || (reg_equiv
[regno
].init_insns
3516 && reg_equiv
[regno
].init_insns
->insn () == NULL
)
3517 || (targetm
.class_likely_spilled_p (reg_preferred_class (regno
))
3518 && MEM_P (src
) && ! reg_equiv
[regno
].is_arg_equivalence
))
3520 /* This might be setting a SUBREG of a pseudo, a pseudo that is
3521 also set somewhere else to a constant. */
3522 note_stores (set
, no_equiv
, NULL
);
3526 /* Don't set reg mentioned in a paradoxical subreg
3527 equivalent to a mem. */
3528 if (MEM_P (src
) && reg_equiv
[regno
].pdx_subregs
)
3530 note_stores (set
, no_equiv
, NULL
);
3534 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
3536 /* cse sometimes generates function invariants, but doesn't put a
3537 REG_EQUAL note on the insn. Since this note would be redundant,
3538 there's no point creating it earlier than here. */
3539 if (! note
&& ! rtx_varies_p (src
, 0))
3540 note
= set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
3542 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
3543 since it represents a function call. */
3544 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
3547 if (DF_REG_DEF_COUNT (regno
) != 1)
3549 bool equal_p
= true;
3550 rtx_insn_list
*list
;
3552 /* If we have already processed this pseudo and determined it
3553 cannot have an equivalence, then honor that decision. */
3554 if (reg_equiv
[regno
].no_equiv
)
3558 || rtx_varies_p (XEXP (note
, 0), 0)
3559 || (reg_equiv
[regno
].replacement
3560 && ! rtx_equal_p (XEXP (note
, 0),
3561 reg_equiv
[regno
].replacement
)))
3563 no_equiv (dest
, set
, NULL
);
3567 list
= reg_equiv
[regno
].init_insns
;
3568 for (; list
; list
= list
->next ())
3573 insn_tmp
= list
->insn ();
3574 note_tmp
= find_reg_note (insn_tmp
, REG_EQUAL
, NULL_RTX
);
3575 gcc_assert (note_tmp
);
3576 if (! rtx_equal_p (XEXP (note
, 0), XEXP (note_tmp
, 0)))
3585 no_equiv (dest
, set
, NULL
);
3590 /* Record this insn as initializing this register. */
3591 reg_equiv
[regno
].init_insns
3592 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
3594 /* If this register is known to be equal to a constant, record that
3595 it is always equivalent to the constant.
3596 Note that it is possible to have a register use before
3597 the def in loops (see gcc.c-torture/execute/pr79286.c)
3598 where the reg is undefined on first use. If the def insn
3599 won't trap we can use it as an equivalence, effectively
3600 choosing the "undefined" value for the reg to be the
3601 same as the value set by the def. */
3602 if (DF_REG_DEF_COUNT (regno
) == 1
3604 && !rtx_varies_p (XEXP (note
, 0), 0)
3605 && (!may_trap_or_fault_p (XEXP (note
, 0))
3606 || def_dominates_uses (regno
)))
3608 rtx note_value
= XEXP (note
, 0);
3609 remove_note (insn
, note
);
3610 set_unique_reg_note (insn
, REG_EQUIV
, note_value
);
3613 /* If this insn introduces a "constant" register, decrease the priority
3614 of that register. Record this insn if the register is only used once
3615 more and the equivalence value is the same as our source.
3617 The latter condition is checked for two reasons: First, it is an
3618 indication that it may be more efficient to actually emit the insn
3619 as written (if no registers are available, reload will substitute
3620 the equivalence). Secondly, it avoids problems with any registers
3621 dying in this insn whose death notes would be missed.
3623 If we don't have a REG_EQUIV note, see if this insn is loading
3624 a register used only in one basic block from a MEM. If so, and the
3625 MEM remains unchanged for the life of the register, add a REG_EQUIV
3627 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3629 rtx replacement
= NULL_RTX
;
3631 replacement
= XEXP (note
, 0);
3632 else if (REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3633 && MEM_P (SET_SRC (set
)))
3635 enum valid_equiv validity
;
3636 validity
= validate_equiv_mem (insn
, dest
, SET_SRC (set
));
3637 if (validity
!= valid_none
)
3639 replacement
= copy_rtx (SET_SRC (set
));
3640 if (validity
== valid_reload
)
3641 note
= set_unique_reg_note (insn
, REG_EQUIV
, replacement
);
3645 /* If we haven't done so, record for reload that this is an
3646 equivalencing insn. */
3647 if (note
&& !reg_equiv
[regno
].is_arg_equivalence
)
3648 ira_reg_equiv
[regno
].init_insns
3649 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3650 ira_reg_equiv
[regno
].init_insns
);
3654 reg_equiv
[regno
].replacement
= replacement
;
3655 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
3656 reg_equiv
[regno
].loop_depth
= (short) loop_depth
;
3658 /* Don't mess with things live during setjmp. */
3659 if (optimize
&& !bitmap_bit_p (setjmp_crosses
, regno
))
3661 /* If the register is referenced exactly twice, meaning it is
3662 set once and used once, indicate that the reference may be
3663 replaced by the equivalence we computed above. Do this
3664 even if the register is only used in one block so that
3665 dependencies can be handled where the last register is
3666 used in a different block (i.e. HIGH / LO_SUM sequences)
3667 and to reduce the number of registers alive across
3670 if (REG_N_REFS (regno
) == 2
3671 && (rtx_equal_p (replacement
, src
)
3672 || ! equiv_init_varies_p (src
))
3673 && NONJUMP_INSN_P (insn
)
3674 && equiv_init_movable_p (PATTERN (insn
), regno
))
3675 reg_equiv
[regno
].replace
= 1;
3682 /* For insns that set a MEM to the contents of a REG that is only used
3683 in a single basic block, see if the register is always equivalent
3684 to that memory location and if moving the store from INSN to the
3685 insn that sets REG is safe. If so, put a REG_EQUIV note on the
3686 initializing insn. */
3688 add_store_equivs (void)
3690 auto_bitmap seen_insns
;
3692 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3696 rtx_insn
*init_insn
;
3698 bitmap_set_bit (seen_insns
, INSN_UID (insn
));
3700 if (! INSN_P (insn
))
3703 set
= single_set (insn
);
3707 dest
= SET_DEST (set
);
3708 src
= SET_SRC (set
);
3710 /* Don't add a REG_EQUIV note if the insn already has one. The existing
3711 REG_EQUIV is likely more useful than the one we are adding. */
3712 if (MEM_P (dest
) && REG_P (src
)
3713 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
3714 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3715 && DF_REG_DEF_COUNT (regno
) == 1
3716 && ! reg_equiv
[regno
].pdx_subregs
3717 && reg_equiv
[regno
].init_insns
!= NULL
3718 && (init_insn
= reg_equiv
[regno
].init_insns
->insn ()) != 0
3719 && bitmap_bit_p (seen_insns
, INSN_UID (init_insn
))
3720 && ! find_reg_note (init_insn
, REG_EQUIV
, NULL_RTX
)
3721 && validate_equiv_mem (init_insn
, src
, dest
) == valid_reload
3722 && ! memref_used_between_p (dest
, init_insn
, insn
)
3723 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
3725 && set_unique_reg_note (init_insn
, REG_EQUIV
, copy_rtx (dest
)))
3727 /* This insn makes the equivalence, not the one initializing
3729 ira_reg_equiv
[regno
].init_insns
3730 = gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
);
3731 df_notes_rescan (init_insn
);
3734 "Adding REG_EQUIV to insn %d for source of insn %d\n",
3735 INSN_UID (init_insn
),
3741 /* Scan all regs killed in an insn to see if any of them are registers
3742 only used that once. If so, see if we can replace the reference
3743 with the equivalent form. If we can, delete the initializing
3744 reference and this register will go away. If we can't replace the
3745 reference, and the initializing reference is within the same loop
3746 (or in an inner loop), then move the register initialization just
3747 before the use, so that they are in the same basic block. */
3749 combine_and_move_insns (void)
3751 auto_bitmap cleared_regs
;
3752 int max
= max_reg_num ();
3754 for (int regno
= FIRST_PSEUDO_REGISTER
; regno
< max
; regno
++)
3756 if (!reg_equiv
[regno
].replace
)
3759 rtx_insn
*use_insn
= 0;
3760 for (df_ref use
= DF_REG_USE_CHAIN (regno
);
3762 use
= DF_REF_NEXT_REG (use
))
3763 if (DF_REF_INSN_INFO (use
))
3765 if (DEBUG_INSN_P (DF_REF_INSN (use
)))
3767 gcc_assert (!use_insn
);
3768 use_insn
= DF_REF_INSN (use
);
3770 gcc_assert (use_insn
);
3772 /* Don't substitute into jumps. indirect_jump_optimize does
3773 this for anything we are prepared to handle. */
3774 if (JUMP_P (use_insn
))
3777 /* Also don't substitute into a conditional trap insn -- it can become
3778 an unconditional trap, and that is a flow control insn. */
3779 if (GET_CODE (PATTERN (use_insn
)) == TRAP_IF
)
3782 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3783 gcc_assert (DF_REG_DEF_COUNT (regno
) == 1 && DF_REF_INSN_INFO (def
));
3784 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3786 /* We may not move instructions that can throw, since that
3787 changes basic block boundaries and we are not prepared to
3788 adjust the CFG to match. */
3789 if (can_throw_internal (def_insn
))
3792 basic_block use_bb
= BLOCK_FOR_INSN (use_insn
);
3793 basic_block def_bb
= BLOCK_FOR_INSN (def_insn
);
3794 if (bb_loop_depth (use_bb
) > bb_loop_depth (def_bb
))
3797 if (asm_noperands (PATTERN (def_insn
)) < 0
3798 && validate_replace_rtx (regno_reg_rtx
[regno
],
3799 *reg_equiv
[regno
].src_p
, use_insn
))
3802 /* Append the REG_DEAD notes from def_insn. */
3803 for (rtx
*p
= ®_NOTES (def_insn
); (link
= *p
) != 0; )
3805 if (REG_NOTE_KIND (XEXP (link
, 0)) == REG_DEAD
)
3807 *p
= XEXP (link
, 1);
3808 XEXP (link
, 1) = REG_NOTES (use_insn
);
3809 REG_NOTES (use_insn
) = link
;
3812 p
= &XEXP (link
, 1);
3815 remove_death (regno
, use_insn
);
3816 SET_REG_N_REFS (regno
, 0);
3817 REG_FREQ (regno
) = 0;
3819 FOR_EACH_INSN_USE (use
, def_insn
)
3821 unsigned int use_regno
= DF_REF_REGNO (use
);
3822 if (!HARD_REGISTER_NUM_P (use_regno
))
3823 reg_equiv
[use_regno
].replace
= 0;
3826 delete_insn (def_insn
);
3828 reg_equiv
[regno
].init_insns
= NULL
;
3829 ira_reg_equiv
[regno
].init_insns
= NULL
;
3830 bitmap_set_bit (cleared_regs
, regno
);
3833 /* Move the initialization of the register to just before
3834 USE_INSN. Update the flow information. */
3835 else if (prev_nondebug_insn (use_insn
) != def_insn
)
3839 new_insn
= emit_insn_before (PATTERN (def_insn
), use_insn
);
3840 REG_NOTES (new_insn
) = REG_NOTES (def_insn
);
3841 REG_NOTES (def_insn
) = 0;
3842 /* Rescan it to process the notes. */
3843 df_insn_rescan (new_insn
);
3845 /* Make sure this insn is recognized before reload begins,
3846 otherwise eliminate_regs_in_insn will die. */
3847 INSN_CODE (new_insn
) = INSN_CODE (def_insn
);
3849 delete_insn (def_insn
);
3851 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
3853 REG_BASIC_BLOCK (regno
) = use_bb
->index
;
3854 REG_N_CALLS_CROSSED (regno
) = 0;
3856 if (use_insn
== BB_HEAD (use_bb
))
3857 BB_HEAD (use_bb
) = new_insn
;
3859 /* We know regno dies in use_insn, but inside a loop
3860 REG_DEAD notes might be missing when def_insn was in
3861 another basic block. However, when we move def_insn into
3862 this bb we'll definitely get a REG_DEAD note and reload
3863 will see the death. It's possible that update_equiv_regs
3864 set up an equivalence referencing regno for a reg set by
3865 use_insn, when regno was seen as non-local. Now that
3866 regno is local to this block, and dies, such an
3867 equivalence is invalid. */
3868 if (find_reg_note (use_insn
, REG_EQUIV
, regno_reg_rtx
[regno
]))
3870 rtx set
= single_set (use_insn
);
3871 if (set
&& REG_P (SET_DEST (set
)))
3872 no_equiv (SET_DEST (set
), set
, NULL
);
3875 ira_reg_equiv
[regno
].init_insns
3876 = gen_rtx_INSN_LIST (VOIDmode
, new_insn
, NULL_RTX
);
3877 bitmap_set_bit (cleared_regs
, regno
);
3881 if (!bitmap_empty_p (cleared_regs
))
3885 FOR_EACH_BB_FN (bb
, cfun
)
3887 bitmap_and_compl_into (DF_LR_IN (bb
), cleared_regs
);
3888 bitmap_and_compl_into (DF_LR_OUT (bb
), cleared_regs
);
3891 bitmap_and_compl_into (DF_LIVE_IN (bb
), cleared_regs
);
3892 bitmap_and_compl_into (DF_LIVE_OUT (bb
), cleared_regs
);
3895 /* Last pass - adjust debug insns referencing cleared regs. */
3896 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3897 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3898 if (DEBUG_BIND_INSN_P (insn
))
3900 rtx old_loc
= INSN_VAR_LOCATION_LOC (insn
);
3901 INSN_VAR_LOCATION_LOC (insn
)
3902 = simplify_replace_fn_rtx (old_loc
, NULL_RTX
,
3903 adjust_cleared_regs
,
3904 (void *) cleared_regs
);
3905 if (old_loc
!= INSN_VAR_LOCATION_LOC (insn
))
3906 df_insn_rescan (insn
);
3911 /* A pass over indirect jumps, converting simple cases to direct jumps.
3912 Combine does this optimization too, but only within a basic block. */
3914 indirect_jump_optimize (void)
3917 bool rebuild_p
= false;
3919 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3921 rtx_insn
*insn
= BB_END (bb
);
3923 || find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
3926 rtx x
= pc_set (insn
);
3927 if (!x
|| !REG_P (SET_SRC (x
)))
3930 int regno
= REGNO (SET_SRC (x
));
3931 if (DF_REG_DEF_COUNT (regno
) == 1)
3933 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3934 if (!DF_REF_IS_ARTIFICIAL (def
))
3936 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3938 rtx set
= single_set (def_insn
);
3939 if (set
&& GET_CODE (SET_SRC (set
)) == LABEL_REF
)
3940 lab
= SET_SRC (set
);
3943 rtx eqnote
= find_reg_note (def_insn
, REG_EQUAL
, NULL_RTX
);
3944 if (eqnote
&& GET_CODE (XEXP (eqnote
, 0)) == LABEL_REF
)
3945 lab
= XEXP (eqnote
, 0);
3947 if (lab
&& validate_replace_rtx (SET_SRC (x
), lab
, insn
))
3955 timevar_push (TV_JUMP
);
3956 rebuild_jump_labels (get_insns ());
3957 if (purge_all_dead_edges ())
3958 delete_unreachable_blocks ();
3959 timevar_pop (TV_JUMP
);
3963 /* Set up fields memory, constant, and invariant from init_insns in
3964 the structures of array ira_reg_equiv. */
3966 setup_reg_equiv (void)
3969 rtx_insn_list
*elem
, *prev_elem
, *next_elem
;
3973 for (i
= FIRST_PSEUDO_REGISTER
; i
< ira_reg_equiv_len
; i
++)
3974 for (prev_elem
= NULL
, elem
= ira_reg_equiv
[i
].init_insns
;
3976 prev_elem
= elem
, elem
= next_elem
)
3978 next_elem
= elem
->next ();
3979 insn
= elem
->insn ();
3980 set
= single_set (insn
);
3982 /* Init insns can set up equivalence when the reg is a destination or
3983 a source (in this case the destination is memory). */
3984 if (set
!= 0 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))))
3986 if ((x
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL
)
3989 if (REG_P (SET_DEST (set
))
3990 && REGNO (SET_DEST (set
)) == (unsigned int) i
3991 && ! rtx_equal_p (SET_SRC (set
), x
) && MEM_P (x
))
3993 /* This insn reporting the equivalence but
3994 actually not setting it. Remove it from the
3996 if (prev_elem
== NULL
)
3997 ira_reg_equiv
[i
].init_insns
= next_elem
;
3999 XEXP (prev_elem
, 1) = next_elem
;
4003 else if (REG_P (SET_DEST (set
))
4004 && REGNO (SET_DEST (set
)) == (unsigned int) i
)
4008 gcc_assert (REG_P (SET_SRC (set
))
4009 && REGNO (SET_SRC (set
)) == (unsigned int) i
);
4012 if (! function_invariant_p (x
)
4014 /* A function invariant is often CONSTANT_P but may
4015 include a register. We promise to only pass
4016 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
4017 || (CONSTANT_P (x
) && LEGITIMATE_PIC_OPERAND_P (x
)))
4019 /* It can happen that a REG_EQUIV note contains a MEM
4020 that is not a legitimate memory operand. As later
4021 stages of reload assume that all addresses found in
4022 the lra_regno_equiv_* arrays were originally
4023 legitimate, we ignore such REG_EQUIV notes. */
4024 if (memory_operand (x
, VOIDmode
))
4026 ira_reg_equiv
[i
].defined_p
= true;
4027 ira_reg_equiv
[i
].memory
= x
;
4030 else if (function_invariant_p (x
))
4034 mode
= GET_MODE (SET_DEST (set
));
4035 if (GET_CODE (x
) == PLUS
4036 || x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4037 /* This is PLUS of frame pointer and a constant,
4039 ira_reg_equiv
[i
].invariant
= x
;
4040 else if (targetm
.legitimate_constant_p (mode
, x
))
4041 ira_reg_equiv
[i
].constant
= x
;
4044 ira_reg_equiv
[i
].memory
= force_const_mem (mode
, x
);
4045 if (ira_reg_equiv
[i
].memory
== NULL_RTX
)
4047 ira_reg_equiv
[i
].defined_p
= false;
4048 ira_reg_equiv
[i
].init_insns
= NULL
;
4052 ira_reg_equiv
[i
].defined_p
= true;
4057 ira_reg_equiv
[i
].defined_p
= false;
4058 ira_reg_equiv
[i
].init_insns
= NULL
;
4065 /* Print chain C to FILE. */
4067 print_insn_chain (FILE *file
, struct insn_chain
*c
)
4069 fprintf (file
, "insn=%d, ", INSN_UID (c
->insn
));
4070 bitmap_print (file
, &c
->live_throughout
, "live_throughout: ", ", ");
4071 bitmap_print (file
, &c
->dead_or_set
, "dead_or_set: ", "\n");
4075 /* Print all reload_insn_chains to FILE. */
4077 print_insn_chains (FILE *file
)
4079 struct insn_chain
*c
;
4080 for (c
= reload_insn_chain
; c
; c
= c
->next
)
4081 print_insn_chain (file
, c
);
4084 /* Return true if pseudo REGNO should be added to set live_throughout
4085 or dead_or_set of the insn chains for reload consideration. */
4087 pseudo_for_reload_consideration_p (int regno
)
4089 /* Consider spilled pseudos too for IRA because they still have a
4090 chance to get hard-registers in the reload when IRA is used. */
4091 return (reg_renumber
[regno
] >= 0 || ira_conflicts_p
);
4094 /* Return true if we can track the individual bytes of subreg X.
4095 When returning true, set *OUTER_SIZE to the number of bytes in
4096 X itself, *INNER_SIZE to the number of bytes in the inner register
4097 and *START to the offset of the first byte. */
4099 get_subreg_tracking_sizes (rtx x
, HOST_WIDE_INT
*outer_size
,
4100 HOST_WIDE_INT
*inner_size
, HOST_WIDE_INT
*start
)
4102 rtx reg
= regno_reg_rtx
[REGNO (SUBREG_REG (x
))];
4103 return (GET_MODE_SIZE (GET_MODE (x
)).is_constant (outer_size
)
4104 && GET_MODE_SIZE (GET_MODE (reg
)).is_constant (inner_size
)
4105 && SUBREG_BYTE (x
).is_constant (start
));
4108 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] for
4109 a register with SIZE bytes, making the register live if INIT_VALUE. */
4111 init_live_subregs (bool init_value
, sbitmap
*live_subregs
,
4112 bitmap live_subregs_used
, int allocnum
, int size
)
4114 gcc_assert (size
> 0);
4116 /* Been there, done that. */
4117 if (bitmap_bit_p (live_subregs_used
, allocnum
))
4120 /* Create a new one. */
4121 if (live_subregs
[allocnum
] == NULL
)
4122 live_subregs
[allocnum
] = sbitmap_alloc (size
);
4124 /* If the entire reg was live before blasting into subregs, we need
4125 to init all of the subregs to ones else init to 0. */
4127 bitmap_ones (live_subregs
[allocnum
]);
4129 bitmap_clear (live_subregs
[allocnum
]);
4131 bitmap_set_bit (live_subregs_used
, allocnum
);
4134 /* Walk the insns of the current function and build reload_insn_chain,
4135 and record register life information. */
4137 build_insn_chain (void)
4140 struct insn_chain
**p
= &reload_insn_chain
;
4142 struct insn_chain
*c
= NULL
;
4143 struct insn_chain
*next
= NULL
;
4144 auto_bitmap live_relevant_regs
;
4145 auto_bitmap elim_regset
;
4146 /* live_subregs is a vector used to keep accurate information about
4147 which hardregs are live in multiword pseudos. live_subregs and
4148 live_subregs_used are indexed by pseudo number. The live_subreg
4149 entry for a particular pseudo is only used if the corresponding
4150 element is non zero in live_subregs_used. The sbitmap size of
4151 live_subreg[allocno] is number of bytes that the pseudo can
4153 sbitmap
*live_subregs
= XCNEWVEC (sbitmap
, max_regno
);
4154 auto_bitmap live_subregs_used
;
4156 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4157 if (TEST_HARD_REG_BIT (eliminable_regset
, i
))
4158 bitmap_set_bit (elim_regset
, i
);
4159 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
4164 CLEAR_REG_SET (live_relevant_regs
);
4165 bitmap_clear (live_subregs_used
);
4167 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
), 0, i
, bi
)
4169 if (i
>= FIRST_PSEUDO_REGISTER
)
4171 bitmap_set_bit (live_relevant_regs
, i
);
4174 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
),
4175 FIRST_PSEUDO_REGISTER
, i
, bi
)
4177 if (pseudo_for_reload_consideration_p (i
))
4178 bitmap_set_bit (live_relevant_regs
, i
);
4181 FOR_BB_INSNS_REVERSE (bb
, insn
)
4183 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4185 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4188 c
= new_insn_chain ();
4195 c
->block
= bb
->index
;
4197 if (NONDEBUG_INSN_P (insn
))
4198 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4200 unsigned int regno
= DF_REF_REGNO (def
);
4202 /* Ignore may clobbers because these are generated
4203 from calls. However, every other kind of def is
4204 added to dead_or_set. */
4205 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
4207 if (regno
< FIRST_PSEUDO_REGISTER
)
4209 if (!fixed_regs
[regno
])
4210 bitmap_set_bit (&c
->dead_or_set
, regno
);
4212 else if (pseudo_for_reload_consideration_p (regno
))
4213 bitmap_set_bit (&c
->dead_or_set
, regno
);
4216 if ((regno
< FIRST_PSEUDO_REGISTER
4217 || reg_renumber
[regno
] >= 0
4219 && (!DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
)))
4221 rtx reg
= DF_REF_REG (def
);
4222 HOST_WIDE_INT outer_size
, inner_size
, start
;
4224 /* We can usually track the liveness of individual
4225 bytes within a subreg. The only exceptions are
4226 subregs wrapped in ZERO_EXTRACTs and subregs whose
4227 size is not known; in those cases we need to be
4228 conservative and treat the definition as a partial
4229 definition of the full register rather than a full
4230 definition of a specific part of the register. */
4231 if (GET_CODE (reg
) == SUBREG
4232 && !DF_REF_FLAGS_IS_SET (def
, DF_REF_ZERO_EXTRACT
)
4233 && get_subreg_tracking_sizes (reg
, &outer_size
,
4234 &inner_size
, &start
))
4236 HOST_WIDE_INT last
= start
+ outer_size
;
4239 (bitmap_bit_p (live_relevant_regs
, regno
),
4240 live_subregs
, live_subregs_used
, regno
,
4243 if (!DF_REF_FLAGS_IS_SET
4244 (def
, DF_REF_STRICT_LOW_PART
))
4246 /* Expand the range to cover entire words.
4247 Bytes added here are "don't care". */
4249 = start
/ UNITS_PER_WORD
* UNITS_PER_WORD
;
4250 last
= ((last
+ UNITS_PER_WORD
- 1)
4251 / UNITS_PER_WORD
* UNITS_PER_WORD
);
4254 /* Ignore the paradoxical bits. */
4255 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4256 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4258 while (start
< last
)
4260 bitmap_clear_bit (live_subregs
[regno
], start
);
4264 if (bitmap_empty_p (live_subregs
[regno
]))
4266 bitmap_clear_bit (live_subregs_used
, regno
);
4267 bitmap_clear_bit (live_relevant_regs
, regno
);
4270 /* Set live_relevant_regs here because
4271 that bit has to be true to get us to
4272 look at the live_subregs fields. */
4273 bitmap_set_bit (live_relevant_regs
, regno
);
4277 /* DF_REF_PARTIAL is generated for
4278 subregs, STRICT_LOW_PART, and
4279 ZERO_EXTRACT. We handle the subreg
4280 case above so here we have to keep from
4281 modeling the def as a killing def. */
4282 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
))
4284 bitmap_clear_bit (live_subregs_used
, regno
);
4285 bitmap_clear_bit (live_relevant_regs
, regno
);
4291 bitmap_and_compl_into (live_relevant_regs
, elim_regset
);
4292 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4294 if (NONDEBUG_INSN_P (insn
))
4295 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4297 unsigned int regno
= DF_REF_REGNO (use
);
4298 rtx reg
= DF_REF_REG (use
);
4300 /* DF_REF_READ_WRITE on a use means that this use
4301 is fabricated from a def that is a partial set
4302 to a multiword reg. Here, we only model the
4303 subreg case that is not wrapped in ZERO_EXTRACT
4304 precisely so we do not need to look at the
4306 if (DF_REF_FLAGS_IS_SET (use
, DF_REF_READ_WRITE
)
4307 && !DF_REF_FLAGS_IS_SET (use
, DF_REF_ZERO_EXTRACT
)
4308 && DF_REF_FLAGS_IS_SET (use
, DF_REF_SUBREG
))
4311 /* Add the last use of each var to dead_or_set. */
4312 if (!bitmap_bit_p (live_relevant_regs
, regno
))
4314 if (regno
< FIRST_PSEUDO_REGISTER
)
4316 if (!fixed_regs
[regno
])
4317 bitmap_set_bit (&c
->dead_or_set
, regno
);
4319 else if (pseudo_for_reload_consideration_p (regno
))
4320 bitmap_set_bit (&c
->dead_or_set
, regno
);
4323 if (regno
< FIRST_PSEUDO_REGISTER
4324 || pseudo_for_reload_consideration_p (regno
))
4326 HOST_WIDE_INT outer_size
, inner_size
, start
;
4327 if (GET_CODE (reg
) == SUBREG
4328 && !DF_REF_FLAGS_IS_SET (use
,
4330 | DF_REF_ZERO_EXTRACT
)
4331 && get_subreg_tracking_sizes (reg
, &outer_size
,
4332 &inner_size
, &start
))
4334 HOST_WIDE_INT last
= start
+ outer_size
;
4337 (bitmap_bit_p (live_relevant_regs
, regno
),
4338 live_subregs
, live_subregs_used
, regno
,
4341 /* Ignore the paradoxical bits. */
4342 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4343 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4345 while (start
< last
)
4347 bitmap_set_bit (live_subregs
[regno
], start
);
4352 /* Resetting the live_subregs_used is
4353 effectively saying do not use the subregs
4354 because we are reading the whole
4356 bitmap_clear_bit (live_subregs_used
, regno
);
4357 bitmap_set_bit (live_relevant_regs
, regno
);
4363 /* FIXME!! The following code is a disaster. Reload needs to see the
4364 labels and jump tables that are just hanging out in between
4365 the basic blocks. See pr33676. */
4366 insn
= BB_HEAD (bb
);
4368 /* Skip over the barriers and cruft. */
4369 while (insn
&& (BARRIER_P (insn
) || NOTE_P (insn
)
4370 || BLOCK_FOR_INSN (insn
) == bb
))
4371 insn
= PREV_INSN (insn
);
4373 /* While we add anything except barriers and notes, the focus is
4374 to get the labels and jump tables into the
4375 reload_insn_chain. */
4378 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4380 if (BLOCK_FOR_INSN (insn
))
4383 c
= new_insn_chain ();
4389 /* The block makes no sense here, but it is what the old
4391 c
->block
= bb
->index
;
4393 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4395 insn
= PREV_INSN (insn
);
4399 reload_insn_chain
= c
;
4402 for (i
= 0; i
< (unsigned int) max_regno
; i
++)
4403 if (live_subregs
[i
] != NULL
)
4404 sbitmap_free (live_subregs
[i
]);
4405 free (live_subregs
);
4408 print_insn_chains (dump_file
);
4411 /* Examine the rtx found in *LOC, which is read or written to as determined
4412 by TYPE. Return false if we find a reason why an insn containing this
4413 rtx should not be moved (such as accesses to non-constant memory), true
4416 rtx_moveable_p (rtx
*loc
, enum op_type type
)
4422 enum rtx_code code
= GET_CODE (x
);
4432 return type
== OP_IN
;
4438 if (x
== frame_pointer_rtx
)
4440 if (HARD_REGISTER_P (x
))
4446 if (type
== OP_IN
&& MEM_READONLY_P (x
))
4447 return rtx_moveable_p (&XEXP (x
, 0), OP_IN
);
4451 return (rtx_moveable_p (&SET_SRC (x
), OP_IN
)
4452 && rtx_moveable_p (&SET_DEST (x
), OP_OUT
));
4454 case STRICT_LOW_PART
:
4455 return rtx_moveable_p (&XEXP (x
, 0), OP_OUT
);
4459 return (rtx_moveable_p (&XEXP (x
, 0), type
)
4460 && rtx_moveable_p (&XEXP (x
, 1), OP_IN
)
4461 && rtx_moveable_p (&XEXP (x
, 2), OP_IN
));
4465 return rtx_moveable_p (&SET_DEST (x
), OP_OUT
);
4467 case UNSPEC_VOLATILE
:
4468 /* It is a bad idea to consider insns with such rtl
4469 as moveable ones. The insn scheduler also considers them as barrier
4474 /* The same is true for volatile asm: it has unknown side effects, it
4475 cannot be moved at will. */
4476 if (MEM_VOLATILE_P (x
))
4483 fmt
= GET_RTX_FORMAT (code
);
4484 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4488 if (!rtx_moveable_p (&XEXP (x
, i
), type
))
4491 else if (fmt
[i
] == 'E')
4492 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4494 if (!rtx_moveable_p (&XVECEXP (x
, i
, j
), type
))
4501 /* A wrapper around dominated_by_p, which uses the information in UID_LUID
4502 to give dominance relationships between two insns I1 and I2. */
4504 insn_dominated_by_p (rtx i1
, rtx i2
, int *uid_luid
)
4506 basic_block bb1
= BLOCK_FOR_INSN (i1
);
4507 basic_block bb2
= BLOCK_FOR_INSN (i2
);
4510 return uid_luid
[INSN_UID (i2
)] < uid_luid
[INSN_UID (i1
)];
4511 return dominated_by_p (CDI_DOMINATORS
, bb1
, bb2
);
4514 /* Record the range of register numbers added by find_moveable_pseudos. */
4515 int first_moveable_pseudo
, last_moveable_pseudo
;
4517 /* These two vectors hold data for every register added by
4518 find_movable_pseudos, with index 0 holding data for the
4519 first_moveable_pseudo. */
4520 /* The original home register. */
4521 static vec
<rtx
> pseudo_replaced_reg
;
4523 /* Look for instances where we have an instruction that is known to increase
4524 register pressure, and whose result is not used immediately. If it is
4525 possible to move the instruction downwards to just before its first use,
4526 split its lifetime into two ranges. We create a new pseudo to compute the
4527 value, and emit a move instruction just before the first use. If, after
4528 register allocation, the new pseudo remains unallocated, the function
4529 move_unallocated_pseudos then deletes the move instruction and places
4530 the computation just before the first use.
4532 Such a move is safe and profitable if all the input registers remain live
4533 and unchanged between the original computation and its first use. In such
4534 a situation, the computation is known to increase register pressure, and
4535 moving it is known to at least not worsen it.
4537 We restrict moves to only those cases where a register remains unallocated,
4538 in order to avoid interfering too much with the instruction schedule. As
4539 an exception, we may move insns which only modify their input register
4540 (typically induction variables), as this increases the freedom for our
4541 intended transformation, and does not limit the second instruction
4545 find_moveable_pseudos (void)
4548 int max_regs
= max_reg_num ();
4549 int max_uid
= get_max_uid ();
4551 int *uid_luid
= XNEWVEC (int, max_uid
);
4552 rtx_insn
**closest_uses
= XNEWVEC (rtx_insn
*, max_regs
);
4553 /* A set of registers which are live but not modified throughout a block. */
4554 bitmap_head
*bb_transp_live
= XNEWVEC (bitmap_head
,
4555 last_basic_block_for_fn (cfun
));
4556 /* A set of registers which only exist in a given basic block. */
4557 bitmap_head
*bb_local
= XNEWVEC (bitmap_head
,
4558 last_basic_block_for_fn (cfun
));
4559 /* A set of registers which are set once, in an instruction that can be
4560 moved freely downwards, but are otherwise transparent to a block. */
4561 bitmap_head
*bb_moveable_reg_sets
= XNEWVEC (bitmap_head
,
4562 last_basic_block_for_fn (cfun
));
4563 auto_bitmap live
, used
, set
, interesting
, unusable_as_input
;
4566 first_moveable_pseudo
= max_regs
;
4567 pseudo_replaced_reg
.release ();
4568 pseudo_replaced_reg
.safe_grow_cleared (max_regs
);
4571 calculate_dominance_info (CDI_DOMINATORS
);
4574 FOR_EACH_BB_FN (bb
, cfun
)
4577 bitmap transp
= bb_transp_live
+ bb
->index
;
4578 bitmap moveable
= bb_moveable_reg_sets
+ bb
->index
;
4579 bitmap local
= bb_local
+ bb
->index
;
4581 bitmap_initialize (local
, 0);
4582 bitmap_initialize (transp
, 0);
4583 bitmap_initialize (moveable
, 0);
4584 bitmap_copy (live
, df_get_live_out (bb
));
4585 bitmap_and_into (live
, df_get_live_in (bb
));
4586 bitmap_copy (transp
, live
);
4587 bitmap_clear (moveable
);
4588 bitmap_clear (live
);
4589 bitmap_clear (used
);
4591 FOR_BB_INSNS (bb
, insn
)
4592 if (NONDEBUG_INSN_P (insn
))
4594 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4597 uid_luid
[INSN_UID (insn
)] = i
++;
4599 def
= df_single_def (insn_info
);
4600 use
= df_single_use (insn_info
);
4603 && DF_REF_REGNO (use
) == DF_REF_REGNO (def
)
4604 && !bitmap_bit_p (set
, DF_REF_REGNO (use
))
4605 && rtx_moveable_p (&PATTERN (insn
), OP_IN
))
4607 unsigned regno
= DF_REF_REGNO (use
);
4608 bitmap_set_bit (moveable
, regno
);
4609 bitmap_set_bit (set
, regno
);
4610 bitmap_set_bit (used
, regno
);
4611 bitmap_clear_bit (transp
, regno
);
4614 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4616 unsigned regno
= DF_REF_REGNO (use
);
4617 bitmap_set_bit (used
, regno
);
4618 if (bitmap_clear_bit (moveable
, regno
))
4619 bitmap_clear_bit (transp
, regno
);
4622 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4624 unsigned regno
= DF_REF_REGNO (def
);
4625 bitmap_set_bit (set
, regno
);
4626 bitmap_clear_bit (transp
, regno
);
4627 bitmap_clear_bit (moveable
, regno
);
4632 FOR_EACH_BB_FN (bb
, cfun
)
4634 bitmap local
= bb_local
+ bb
->index
;
4637 FOR_BB_INSNS (bb
, insn
)
4638 if (NONDEBUG_INSN_P (insn
))
4640 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4642 rtx closest_use
, note
;
4645 bool all_dominated
, all_local
;
4648 def
= df_single_def (insn_info
);
4649 /* There must be exactly one def in this insn. */
4650 if (!def
|| !single_set (insn
))
4652 /* This must be the only definition of the reg. We also limit
4653 which modes we deal with so that we can assume we can generate
4654 move instructions. */
4655 regno
= DF_REF_REGNO (def
);
4656 mode
= GET_MODE (DF_REF_REG (def
));
4657 if (DF_REG_DEF_COUNT (regno
) != 1
4658 || !DF_REF_INSN_INFO (def
)
4659 || HARD_REGISTER_NUM_P (regno
)
4660 || DF_REG_EQ_USE_COUNT (regno
) > 0
4661 || (!INTEGRAL_MODE_P (mode
) && !FLOAT_MODE_P (mode
)))
4663 def_insn
= DF_REF_INSN (def
);
4665 for (note
= REG_NOTES (def_insn
); note
; note
= XEXP (note
, 1))
4666 if (REG_NOTE_KIND (note
) == REG_EQUIV
&& MEM_P (XEXP (note
, 0)))
4672 fprintf (dump_file
, "Ignoring reg %d, has equiv memory\n",
4674 bitmap_set_bit (unusable_as_input
, regno
);
4678 use
= DF_REG_USE_CHAIN (regno
);
4679 all_dominated
= true;
4681 closest_use
= NULL_RTX
;
4682 for (; use
; use
= DF_REF_NEXT_REG (use
))
4685 if (!DF_REF_INSN_INFO (use
))
4687 all_dominated
= false;
4691 insn
= DF_REF_INSN (use
);
4692 if (DEBUG_INSN_P (insn
))
4694 if (BLOCK_FOR_INSN (insn
) != BLOCK_FOR_INSN (def_insn
))
4696 if (!insn_dominated_by_p (insn
, def_insn
, uid_luid
))
4697 all_dominated
= false;
4698 if (closest_use
!= insn
&& closest_use
!= const0_rtx
)
4700 if (closest_use
== NULL_RTX
)
4702 else if (insn_dominated_by_p (closest_use
, insn
, uid_luid
))
4704 else if (!insn_dominated_by_p (insn
, closest_use
, uid_luid
))
4705 closest_use
= const0_rtx
;
4711 fprintf (dump_file
, "Reg %d not all uses dominated by set\n",
4716 bitmap_set_bit (local
, regno
);
4717 if (closest_use
== const0_rtx
|| closest_use
== NULL
4718 || next_nonnote_nondebug_insn (def_insn
) == closest_use
)
4721 fprintf (dump_file
, "Reg %d uninteresting%s\n", regno
,
4722 closest_use
== const0_rtx
|| closest_use
== NULL
4723 ? " (no unique first use)" : "");
4726 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (closest_use
)))
4729 fprintf (dump_file
, "Reg %d: closest user uses cc0\n",
4734 bitmap_set_bit (interesting
, regno
);
4735 /* If we get here, we know closest_use is a non-NULL insn
4736 (as opposed to const_0_rtx). */
4737 closest_uses
[regno
] = as_a
<rtx_insn
*> (closest_use
);
4739 if (dump_file
&& (all_local
|| all_dominated
))
4741 fprintf (dump_file
, "Reg %u:", regno
);
4743 fprintf (dump_file
, " local to bb %d", bb
->index
);
4745 fprintf (dump_file
, " def dominates all uses");
4746 if (closest_use
!= const0_rtx
)
4747 fprintf (dump_file
, " has unique first use");
4748 fputs ("\n", dump_file
);
4753 EXECUTE_IF_SET_IN_BITMAP (interesting
, 0, i
, bi
)
4755 df_ref def
= DF_REG_DEF_CHAIN (i
);
4756 rtx_insn
*def_insn
= DF_REF_INSN (def
);
4757 basic_block def_block
= BLOCK_FOR_INSN (def_insn
);
4758 bitmap def_bb_local
= bb_local
+ def_block
->index
;
4759 bitmap def_bb_moveable
= bb_moveable_reg_sets
+ def_block
->index
;
4760 bitmap def_bb_transp
= bb_transp_live
+ def_block
->index
;
4761 bool local_to_bb_p
= bitmap_bit_p (def_bb_local
, i
);
4762 rtx_insn
*use_insn
= closest_uses
[i
];
4765 bool all_transp
= true;
4767 if (!REG_P (DF_REF_REG (def
)))
4773 fprintf (dump_file
, "Reg %u not local to one basic block\n",
4777 if (reg_equiv_init (i
) != NULL_RTX
)
4780 fprintf (dump_file
, "Ignoring reg %u with equiv init insn\n",
4784 if (!rtx_moveable_p (&PATTERN (def_insn
), OP_IN
))
4787 fprintf (dump_file
, "Found def insn %d for %d to be not moveable\n",
4788 INSN_UID (def_insn
), i
);
4792 fprintf (dump_file
, "Examining insn %d, def for %d\n",
4793 INSN_UID (def_insn
), i
);
4794 FOR_EACH_INSN_USE (use
, def_insn
)
4796 unsigned regno
= DF_REF_REGNO (use
);
4797 if (bitmap_bit_p (unusable_as_input
, regno
))
4801 fprintf (dump_file
, " found unusable input reg %u.\n", regno
);
4804 if (!bitmap_bit_p (def_bb_transp
, regno
))
4806 if (bitmap_bit_p (def_bb_moveable
, regno
)
4807 && !control_flow_insn_p (use_insn
)
4808 && (!HAVE_cc0
|| !sets_cc0_p (use_insn
)))
4810 if (modified_between_p (DF_REF_REG (use
), def_insn
, use_insn
))
4812 rtx_insn
*x
= NEXT_INSN (def_insn
);
4813 while (!modified_in_p (DF_REF_REG (use
), x
))
4815 gcc_assert (x
!= use_insn
);
4819 fprintf (dump_file
, " input reg %u modified but insn %d moveable\n",
4820 regno
, INSN_UID (x
));
4821 emit_insn_after (PATTERN (x
), use_insn
);
4822 set_insn_deleted (x
);
4827 fprintf (dump_file
, " input reg %u modified between def and use\n",
4838 if (!dbg_cnt (ira_move
))
4841 fprintf (dump_file
, " all ok%s\n", all_transp
? " and transp" : "");
4845 rtx def_reg
= DF_REF_REG (def
);
4846 rtx newreg
= ira_create_new_reg (def_reg
);
4847 if (validate_change (def_insn
, DF_REF_REAL_LOC (def
), newreg
, 0))
4849 unsigned nregno
= REGNO (newreg
);
4850 emit_insn_before (gen_move_insn (def_reg
, newreg
), use_insn
);
4852 pseudo_replaced_reg
[nregno
] = def_reg
;
4857 FOR_EACH_BB_FN (bb
, cfun
)
4859 bitmap_clear (bb_local
+ bb
->index
);
4860 bitmap_clear (bb_transp_live
+ bb
->index
);
4861 bitmap_clear (bb_moveable_reg_sets
+ bb
->index
);
4864 free (closest_uses
);
4866 free (bb_transp_live
);
4867 free (bb_moveable_reg_sets
);
4869 last_moveable_pseudo
= max_reg_num ();
4871 fix_reg_equiv_init ();
4873 regstat_free_n_sets_and_refs ();
4875 regstat_init_n_sets_and_refs ();
4876 regstat_compute_ri ();
4877 free_dominance_info (CDI_DOMINATORS
);
4880 /* If SET pattern SET is an assignment from a hard register to a pseudo which
4881 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return
4882 the destination. Otherwise return NULL. */
4885 interesting_dest_for_shprep_1 (rtx set
, basic_block call_dom
)
4887 rtx src
= SET_SRC (set
);
4888 rtx dest
= SET_DEST (set
);
4889 if (!REG_P (src
) || !HARD_REGISTER_P (src
)
4890 || !REG_P (dest
) || HARD_REGISTER_P (dest
)
4891 || (call_dom
&& !bitmap_bit_p (df_get_live_in (call_dom
), REGNO (dest
))))
4896 /* If insn is interesting for parameter range-splitting shrink-wrapping
4897 preparation, i.e. it is a single set from a hard register to a pseudo, which
4898 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a
4899 parallel statement with only one such statement, return the destination.
4900 Otherwise return NULL. */
4903 interesting_dest_for_shprep (rtx_insn
*insn
, basic_block call_dom
)
4907 rtx pat
= PATTERN (insn
);
4908 if (GET_CODE (pat
) == SET
)
4909 return interesting_dest_for_shprep_1 (pat
, call_dom
);
4911 if (GET_CODE (pat
) != PARALLEL
)
4914 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
4916 rtx sub
= XVECEXP (pat
, 0, i
);
4917 if (GET_CODE (sub
) == USE
4918 || GET_CODE (sub
) == CLOBBER
4919 || GET_CODE (sub
) == CLOBBER_HIGH
)
4921 if (GET_CODE (sub
) != SET
4922 || side_effects_p (sub
))
4924 rtx dest
= interesting_dest_for_shprep_1 (sub
, call_dom
);
4933 /* Split live ranges of pseudos that are loaded from hard registers in the
4934 first BB in a BB that dominates all non-sibling call if such a BB can be
4935 found and is not in a loop. Return true if the function has made any
4939 split_live_ranges_for_shrink_wrap (void)
4941 basic_block bb
, call_dom
= NULL
;
4942 basic_block first
= single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
4943 rtx_insn
*insn
, *last_interesting_insn
= NULL
;
4944 auto_bitmap need_new
, reachable
;
4945 vec
<basic_block
> queue
;
4947 if (!SHRINK_WRAPPING_ENABLED
)
4950 queue
.create (n_basic_blocks_for_fn (cfun
));
4952 FOR_EACH_BB_FN (bb
, cfun
)
4953 FOR_BB_INSNS (bb
, insn
)
4954 if (CALL_P (insn
) && !SIBLING_CALL_P (insn
))
4962 bitmap_set_bit (need_new
, bb
->index
);
4963 bitmap_set_bit (reachable
, bb
->index
);
4964 queue
.quick_push (bb
);
4968 if (queue
.is_empty ())
4974 while (!queue
.is_empty ())
4980 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
4981 if (e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
)
4982 && bitmap_set_bit (reachable
, e
->dest
->index
))
4983 queue
.quick_push (e
->dest
);
4987 FOR_BB_INSNS (first
, insn
)
4989 rtx dest
= interesting_dest_for_shprep (insn
, NULL
);
4993 if (DF_REG_DEF_COUNT (REGNO (dest
)) > 1)
4996 for (df_ref use
= DF_REG_USE_CHAIN (REGNO(dest
));
4998 use
= DF_REF_NEXT_REG (use
))
5000 int ubbi
= DF_REF_BB (use
)->index
;
5001 if (bitmap_bit_p (reachable
, ubbi
))
5002 bitmap_set_bit (need_new
, ubbi
);
5004 last_interesting_insn
= insn
;
5007 if (!last_interesting_insn
)
5010 call_dom
= nearest_common_dominator_for_set (CDI_DOMINATORS
, need_new
);
5011 if (call_dom
== first
)
5014 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
5015 while (bb_loop_depth (call_dom
) > 0)
5016 call_dom
= get_immediate_dominator (CDI_DOMINATORS
, call_dom
);
5017 loop_optimizer_finalize ();
5019 if (call_dom
== first
)
5022 calculate_dominance_info (CDI_POST_DOMINATORS
);
5023 if (dominated_by_p (CDI_POST_DOMINATORS
, first
, call_dom
))
5025 free_dominance_info (CDI_POST_DOMINATORS
);
5028 free_dominance_info (CDI_POST_DOMINATORS
);
5031 fprintf (dump_file
, "Will split live ranges of parameters at BB %i\n",
5035 FOR_BB_INSNS (first
, insn
)
5037 rtx dest
= interesting_dest_for_shprep (insn
, call_dom
);
5038 if (!dest
|| dest
== pic_offset_table_rtx
)
5041 bool need_newreg
= false;
5043 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
5045 rtx_insn
*uin
= DF_REF_INSN (use
);
5046 next
= DF_REF_NEXT_REG (use
);
5048 if (DEBUG_INSN_P (uin
))
5051 basic_block ubb
= BLOCK_FOR_INSN (uin
);
5053 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
5062 rtx newreg
= ira_create_new_reg (dest
);
5064 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
5066 rtx_insn
*uin
= DF_REF_INSN (use
);
5067 next
= DF_REF_NEXT_REG (use
);
5069 basic_block ubb
= BLOCK_FOR_INSN (uin
);
5071 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
5072 validate_change (uin
, DF_REF_REAL_LOC (use
), newreg
, true);
5075 rtx_insn
*new_move
= gen_move_insn (newreg
, dest
);
5076 emit_insn_after (new_move
, bb_note (call_dom
));
5079 fprintf (dump_file
, "Split live-range of register ");
5080 print_rtl_single (dump_file
, dest
);
5085 if (insn
== last_interesting_insn
)
5088 apply_change_group ();
5092 /* Perform the second half of the transformation started in
5093 find_moveable_pseudos. We look for instances where the newly introduced
5094 pseudo remains unallocated, and remove it by moving the definition to
5095 just before its use, replacing the move instruction generated by
5096 find_moveable_pseudos. */
5098 move_unallocated_pseudos (void)
5101 for (i
= first_moveable_pseudo
; i
< last_moveable_pseudo
; i
++)
5102 if (reg_renumber
[i
] < 0)
5104 int idx
= i
- first_moveable_pseudo
;
5105 rtx other_reg
= pseudo_replaced_reg
[idx
];
5106 rtx_insn
*def_insn
= DF_REF_INSN (DF_REG_DEF_CHAIN (i
));
5107 /* The use must follow all definitions of OTHER_REG, so we can
5108 insert the new definition immediately after any of them. */
5109 df_ref other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
));
5110 rtx_insn
*move_insn
= DF_REF_INSN (other_def
);
5111 rtx_insn
*newinsn
= emit_insn_after (PATTERN (def_insn
), move_insn
);
5116 fprintf (dump_file
, "moving def of %d (insn %d now) ",
5117 REGNO (other_reg
), INSN_UID (def_insn
));
5119 delete_insn (move_insn
);
5120 while ((other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
))))
5121 delete_insn (DF_REF_INSN (other_def
));
5122 delete_insn (def_insn
);
5124 set
= single_set (newinsn
);
5125 success
= validate_change (newinsn
, &SET_DEST (set
), other_reg
, 0);
5126 gcc_assert (success
);
5128 fprintf (dump_file
, " %d) rather than keep unallocated replacement %d\n",
5129 INSN_UID (newinsn
), i
);
5130 SET_REG_N_REFS (i
, 0);
5134 /* If the backend knows where to allocate pseudos for hard
5135 register initial values, register these allocations now. */
5137 allocate_initial_values (void)
5139 if (targetm
.allocate_initial_value
)
5144 for (i
= 0; HARD_REGISTER_NUM_P (i
); i
++)
5146 if (! initial_value_entry (i
, &hreg
, &preg
))
5149 x
= targetm
.allocate_initial_value (hreg
);
5150 regno
= REGNO (preg
);
5151 if (x
&& REG_N_SETS (regno
) <= 1)
5154 reg_equiv_memory_loc (regno
) = x
;
5160 gcc_assert (REG_P (x
));
5161 new_regno
= REGNO (x
);
5162 reg_renumber
[regno
] = new_regno
;
5163 /* Poke the regno right into regno_reg_rtx so that even
5164 fixed regs are accepted. */
5165 SET_REGNO (preg
, new_regno
);
5166 /* Update global register liveness information. */
5167 FOR_EACH_BB_FN (bb
, cfun
)
5169 if (REGNO_REG_SET_P (df_get_live_in (bb
), regno
))
5170 SET_REGNO_REG_SET (df_get_live_in (bb
), new_regno
);
5171 if (REGNO_REG_SET_P (df_get_live_out (bb
), regno
))
5172 SET_REGNO_REG_SET (df_get_live_out (bb
), new_regno
);
5178 gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER
,
5184 /* True when we use LRA instead of reload pass for the current
5188 /* True if we have allocno conflicts. It is false for non-optimized
5189 mode or when the conflict table is too big. */
5190 bool ira_conflicts_p
;
5192 /* Saved between IRA and reload. */
5193 static int saved_flag_ira_share_spill_slots
;
5195 /* This is the main entry of IRA. */
5200 int ira_max_point_before_emit
;
5201 bool saved_flag_caller_saves
= flag_caller_saves
;
5202 enum ira_region saved_flag_ira_region
= flag_ira_region
;
5204 int num_used_regs
= 0;
5208 /* Determine if the current function is a leaf before running IRA
5209 since this can impact optimizations done by the prologue and
5210 epilogue thus changing register elimination offsets.
5211 Other target callbacks may use crtl->is_leaf too, including
5212 SHRINK_WRAPPING_ENABLED, so initialize as early as possible. */
5213 crtl
->is_leaf
= leaf_function_p ();
5215 /* Perform target specific PIC register initialization. */
5216 targetm
.init_pic_reg ();
5218 ira_conflicts_p
= optimize
> 0;
5220 /* Determine the number of pseudos actually requiring coloring. */
5221 for (i
= FIRST_PSEUDO_REGISTER
; i
< DF_REG_SIZE (df
); i
++)
5222 num_used_regs
+= !!(DF_REG_USE_COUNT (i
) + DF_REG_DEF_COUNT (i
));
5224 /* If there are too many pseudos and/or basic blocks (e.g. 10K
5225 pseudos and 10K blocks or 100K pseudos and 1K blocks), we will
5226 use simplified and faster algorithms in LRA. */
5229 && num_used_regs
>= (1 << 26) / last_basic_block_for_fn (cfun
));
5233 /* It permits to skip live range splitting in LRA. */
5234 flag_caller_saves
= false;
5235 /* There is no sense to do regional allocation when we use
5237 flag_ira_region
= IRA_REGION_ONE
;
5238 ira_conflicts_p
= false;
5241 #ifndef IRA_NO_OBSTACK
5242 gcc_obstack_init (&ira_obstack
);
5244 bitmap_obstack_initialize (&ira_bitmap_obstack
);
5246 /* LRA uses its own infrastructure to handle caller save registers. */
5247 if (flag_caller_saves
&& !ira_use_lra_p
)
5248 init_caller_save ();
5250 if (flag_ira_verbose
< 10)
5252 internal_flag_ira_verbose
= flag_ira_verbose
;
5257 internal_flag_ira_verbose
= flag_ira_verbose
- 10;
5258 ira_dump_file
= stderr
;
5261 setup_prohibited_mode_move_regs ();
5262 decrease_live_ranges_number ();
5263 df_note_add_problem ();
5265 /* DF_LIVE can't be used in the register allocator, too many other
5266 parts of the compiler depend on using the "classic" liveness
5267 interpretation of the DF_LR problem. See PR38711.
5268 Remove the problem, so that we don't spend time updating it in
5269 any of the df_analyze() calls during IRA/LRA. */
5271 df_remove_problem (df_live
);
5272 gcc_checking_assert (df_live
== NULL
);
5275 df
->changeable_flags
|= DF_VERIFY_SCHEDULED
;
5280 if (ira_conflicts_p
)
5282 calculate_dominance_info (CDI_DOMINATORS
);
5284 if (split_live_ranges_for_shrink_wrap ())
5287 free_dominance_info (CDI_DOMINATORS
);
5290 df_clear_flags (DF_NO_INSN_RESCAN
);
5292 indirect_jump_optimize ();
5293 if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
5296 regstat_init_n_sets_and_refs ();
5297 regstat_compute_ri ();
5299 /* If we are not optimizing, then this is the only place before
5300 register allocation where dataflow is done. And that is needed
5301 to generate these warnings. */
5303 generate_setjmp_warnings ();
5305 if (resize_reg_info () && flag_ira_loop_pressure
)
5306 ira_set_pseudo_classes (true, ira_dump_file
);
5308 init_alias_analysis ();
5309 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
5310 reg_equiv
= XCNEWVEC (struct equivalence
, max_reg_num ());
5311 update_equiv_regs ();
5313 /* Don't move insns if live range shrinkage or register
5314 pressure-sensitive scheduling were done because it will not
5315 improve allocation but likely worsen insn scheduling. */
5317 && !flag_live_range_shrinkage
5318 && !(flag_sched_pressure
&& flag_schedule_insns
))
5319 combine_and_move_insns ();
5321 /* Gather additional equivalences with memory. */
5323 add_store_equivs ();
5325 loop_optimizer_finalize ();
5326 free_dominance_info (CDI_DOMINATORS
);
5327 end_alias_analysis ();
5332 setup_reg_equiv_init ();
5334 allocated_reg_info_size
= max_reg_num ();
5336 /* It is not worth to do such improvement when we use a simple
5337 allocation because of -O0 usage or because the function is too
5339 if (ira_conflicts_p
)
5340 find_moveable_pseudos ();
5342 max_regno_before_ira
= max_reg_num ();
5343 ira_setup_eliminable_regset ();
5345 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
5346 ira_load_cost
= ira_store_cost
= ira_shuffle_cost
= 0;
5347 ira_move_loops_num
= ira_additional_jumps_num
= 0;
5349 ira_assert (current_loops
== NULL
);
5350 if (flag_ira_region
== IRA_REGION_ALL
|| flag_ira_region
== IRA_REGION_MIXED
)
5351 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
| LOOPS_HAVE_RECORDED_EXITS
);
5353 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5354 fprintf (ira_dump_file
, "Building IRA IR\n");
5355 loops_p
= ira_build ();
5357 ira_assert (ira_conflicts_p
|| !loops_p
);
5359 saved_flag_ira_share_spill_slots
= flag_ira_share_spill_slots
;
5360 if (too_high_register_pressure_p () || cfun
->calls_setjmp
)
5361 /* It is just wasting compiler's time to pack spilled pseudos into
5362 stack slots in this case -- prohibit it. We also do this if
5363 there is setjmp call because a variable not modified between
5364 setjmp and longjmp the compiler is required to preserve its
5365 value and sharing slots does not guarantee it. */
5366 flag_ira_share_spill_slots
= FALSE
;
5370 ira_max_point_before_emit
= ira_max_point
;
5372 ira_initiate_emit_data ();
5376 max_regno
= max_reg_num ();
5377 if (ira_conflicts_p
)
5381 if (! ira_use_lra_p
)
5382 ira_initiate_assign ();
5391 ira_allocno_iterator ai
;
5393 FOR_EACH_ALLOCNO (a
, ai
)
5395 int old_regno
= ALLOCNO_REGNO (a
);
5396 int new_regno
= REGNO (ALLOCNO_EMIT_DATA (a
)->reg
);
5398 ALLOCNO_REGNO (a
) = new_regno
;
5400 if (old_regno
!= new_regno
)
5401 setup_reg_classes (new_regno
, reg_preferred_class (old_regno
),
5402 reg_alternate_class (old_regno
),
5403 reg_allocno_class (old_regno
));
5408 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5409 fprintf (ira_dump_file
, "Flattening IR\n");
5410 ira_flattening (max_regno_before_ira
, ira_max_point_before_emit
);
5412 /* New insns were generated: add notes and recalculate live
5416 /* ??? Rebuild the loop tree, but why? Does the loop tree
5417 change if new insns were generated? Can that be handled
5418 by updating the loop tree incrementally? */
5419 loop_optimizer_finalize ();
5420 free_dominance_info (CDI_DOMINATORS
);
5421 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
5422 | LOOPS_HAVE_RECORDED_EXITS
);
5424 if (! ira_use_lra_p
)
5426 setup_allocno_assignment_flags ();
5427 ira_initiate_assign ();
5428 ira_reassign_conflict_allocnos (max_regno
);
5433 ira_finish_emit_data ();
5435 setup_reg_renumber ();
5437 calculate_allocation_cost ();
5439 #ifdef ENABLE_IRA_CHECKING
5440 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5441 /* Opposite to reload pass, LRA does not use any conflict info
5442 from IRA. We don't rebuild conflict info for LRA (through
5443 ira_flattening call) and cannot use the check here. We could
5444 rebuild this info for LRA in the check mode but there is a risk
5445 that code generated with the check and without it will be a bit
5446 different. Calling ira_flattening in any mode would be a
5447 wasting CPU time. So do not check the allocation for LRA. */
5448 check_allocation ();
5451 if (max_regno
!= max_regno_before_ira
)
5453 regstat_free_n_sets_and_refs ();
5455 regstat_init_n_sets_and_refs ();
5456 regstat_compute_ri ();
5459 overall_cost_before
= ira_overall_cost
;
5460 if (! ira_conflicts_p
)
5464 fix_reg_equiv_init ();
5466 #ifdef ENABLE_IRA_CHECKING
5467 print_redundant_copies ();
5469 if (! ira_use_lra_p
)
5471 ira_spilled_reg_stack_slots_num
= 0;
5472 ira_spilled_reg_stack_slots
5473 = ((struct ira_spilled_reg_stack_slot
*)
5474 ira_allocate (max_regno
5475 * sizeof (struct ira_spilled_reg_stack_slot
)));
5476 memset ((void *)ira_spilled_reg_stack_slots
, 0,
5477 max_regno
* sizeof (struct ira_spilled_reg_stack_slot
));
5480 allocate_initial_values ();
5482 /* See comment for find_moveable_pseudos call. */
5483 if (ira_conflicts_p
)
5484 move_unallocated_pseudos ();
5486 /* Restore original values. */
5489 flag_caller_saves
= saved_flag_caller_saves
;
5490 flag_ira_region
= saved_flag_ira_region
;
5499 unsigned pic_offset_table_regno
= INVALID_REGNUM
;
5501 if (flag_ira_verbose
< 10)
5502 ira_dump_file
= dump_file
;
5504 /* If pic_offset_table_rtx is a pseudo register, then keep it so
5505 after reload to avoid possible wrong usages of hard reg assigned
5507 if (pic_offset_table_rtx
5508 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
5509 pic_offset_table_regno
= REGNO (pic_offset_table_rtx
);
5511 timevar_push (TV_RELOAD
);
5514 if (current_loops
!= NULL
)
5516 loop_optimizer_finalize ();
5517 free_dominance_info (CDI_DOMINATORS
);
5519 FOR_ALL_BB_FN (bb
, cfun
)
5520 bb
->loop_father
= NULL
;
5521 current_loops
= NULL
;
5525 lra (ira_dump_file
);
5526 /* ???!!! Move it before lra () when we use ira_reg_equiv in
5528 vec_free (reg_equivs
);
5534 df_set_flags (DF_NO_INSN_RESCAN
);
5535 build_insn_chain ();
5537 need_dce
= reload (get_insns (), ira_conflicts_p
);
5540 timevar_pop (TV_RELOAD
);
5542 timevar_push (TV_IRA
);
5544 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5546 ira_free (ira_spilled_reg_stack_slots
);
5547 ira_finish_assign ();
5550 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
5551 && overall_cost_before
!= ira_overall_cost
)
5552 fprintf (ira_dump_file
, "+++Overall after reload %" PRId64
"\n",
5555 flag_ira_share_spill_slots
= saved_flag_ira_share_spill_slots
;
5557 if (! ira_use_lra_p
)
5560 if (current_loops
!= NULL
)
5562 loop_optimizer_finalize ();
5563 free_dominance_info (CDI_DOMINATORS
);
5565 FOR_ALL_BB_FN (bb
, cfun
)
5566 bb
->loop_father
= NULL
;
5567 current_loops
= NULL
;
5570 regstat_free_n_sets_and_refs ();
5574 cleanup_cfg (CLEANUP_EXPENSIVE
);
5576 finish_reg_equiv ();
5578 bitmap_obstack_release (&ira_bitmap_obstack
);
5579 #ifndef IRA_NO_OBSTACK
5580 obstack_free (&ira_obstack
, NULL
);
5583 /* The code after the reload has changed so much that at this point
5584 we might as well just rescan everything. Note that
5585 df_rescan_all_insns is not going to help here because it does not
5586 touch the artificial uses and defs. */
5587 df_finish_pass (true);
5588 df_scan_alloc (NULL
);
5593 df_live_add_problem ();
5594 df_live_set_all_dirty ();
5600 if (need_dce
&& optimize
)
5603 /* Diagnose uses of the hard frame pointer when it is used as a global
5604 register. Often we can get away with letting the user appropriate
5605 the frame pointer, but we should let them know when code generation
5606 makes that impossible. */
5607 if (global_regs
[HARD_FRAME_POINTER_REGNUM
] && frame_pointer_needed
)
5609 tree decl
= global_regs_decl
[HARD_FRAME_POINTER_REGNUM
];
5610 error_at (DECL_SOURCE_LOCATION (current_function_decl
),
5611 "frame pointer required, but reserved");
5612 inform (DECL_SOURCE_LOCATION (decl
), "for %qD", decl
);
5615 /* If we are doing generic stack checking, give a warning if this
5616 function's frame size is larger than we expect. */
5617 if (flag_stack_check
== GENERIC_STACK_CHECK
)
5619 poly_int64 size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
5621 for (int i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5622 if (df_regs_ever_live_p (i
) && !fixed_regs
[i
] && call_used_regs
[i
])
5623 size
+= UNITS_PER_WORD
;
5625 if (constant_lower_bound (size
) > STACK_CHECK_MAX_FRAME_SIZE
)
5626 warning (0, "frame size too large for reliable stack checking");
5629 if (pic_offset_table_regno
!= INVALID_REGNUM
)
5630 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, pic_offset_table_regno
);
5632 timevar_pop (TV_IRA
);
5635 /* Run the integrated register allocator. */
5639 const pass_data pass_data_ira
=
5641 RTL_PASS
, /* type */
5643 OPTGROUP_NONE
, /* optinfo_flags */
5645 0, /* properties_required */
5646 0, /* properties_provided */
5647 0, /* properties_destroyed */
5648 0, /* todo_flags_start */
5649 TODO_do_not_ggc_collect
, /* todo_flags_finish */
5652 class pass_ira
: public rtl_opt_pass
5655 pass_ira (gcc::context
*ctxt
)
5656 : rtl_opt_pass (pass_data_ira
, ctxt
)
5659 /* opt_pass methods: */
5660 virtual bool gate (function
*)
5662 return !targetm
.no_register_allocation
;
5664 virtual unsigned int execute (function
*)
5670 }; // class pass_ira
5675 make_pass_ira (gcc::context
*ctxt
)
5677 return new pass_ira (ctxt
);
5682 const pass_data pass_data_reload
=
5684 RTL_PASS
, /* type */
5685 "reload", /* name */
5686 OPTGROUP_NONE
, /* optinfo_flags */
5687 TV_RELOAD
, /* tv_id */
5688 0, /* properties_required */
5689 0, /* properties_provided */
5690 0, /* properties_destroyed */
5691 0, /* todo_flags_start */
5692 0, /* todo_flags_finish */
5695 class pass_reload
: public rtl_opt_pass
5698 pass_reload (gcc::context
*ctxt
)
5699 : rtl_opt_pass (pass_data_reload
, ctxt
)
5702 /* opt_pass methods: */
5703 virtual bool gate (function
*)
5705 return !targetm
.no_register_allocation
;
5707 virtual unsigned int execute (function
*)
5713 }; // class pass_reload
5718 make_pass_reload (gcc::context
*ctxt
)
5720 return new pass_reload (ctxt
);