1 /* Integrated Register Allocator (IRA) entry point.
2 Copyright (C) 2006-2019 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 /* The integrated register allocator (IRA) is a
22 regional register allocator performing graph coloring on a top-down
23 traversal of nested regions. Graph coloring in a region is based
24 on Chaitin-Briggs algorithm. It is called integrated because
25 register coalescing, register live range splitting, and choosing a
26 better hard register are done on-the-fly during coloring. Register
27 coalescing and choosing a cheaper hard register is done by hard
28 register preferencing during hard register assigning. The live
29 range splitting is a byproduct of the regional register allocation.
31 Major IRA notions are:
33 o *Region* is a part of CFG where graph coloring based on
34 Chaitin-Briggs algorithm is done. IRA can work on any set of
35 nested CFG regions forming a tree. Currently the regions are
36 the entire function for the root region and natural loops for
37 the other regions. Therefore data structure representing a
38 region is called loop_tree_node.
40 o *Allocno class* is a register class used for allocation of
41 given allocno. It means that only hard register of given
42 register class can be assigned to given allocno. In reality,
43 even smaller subset of (*profitable*) hard registers can be
44 assigned. In rare cases, the subset can be even smaller
45 because our modification of Chaitin-Briggs algorithm requires
46 that sets of hard registers can be assigned to allocnos forms a
47 forest, i.e. the sets can be ordered in a way where any
48 previous set is not intersected with given set or is a superset
51 o *Pressure class* is a register class belonging to a set of
52 register classes containing all of the hard-registers available
53 for register allocation. The set of all pressure classes for a
54 target is defined in the corresponding machine-description file
55 according some criteria. Register pressure is calculated only
56 for pressure classes and it affects some IRA decisions as
57 forming allocation regions.
59 o *Allocno* represents the live range of a pseudo-register in a
60 region. Besides the obvious attributes like the corresponding
61 pseudo-register number, allocno class, conflicting allocnos and
62 conflicting hard-registers, there are a few allocno attributes
63 which are important for understanding the allocation algorithm:
65 - *Live ranges*. This is a list of ranges of *program points*
66 where the allocno lives. Program points represent places
67 where a pseudo can be born or become dead (there are
68 approximately two times more program points than the insns)
69 and they are represented by integers starting with 0. The
70 live ranges are used to find conflicts between allocnos.
71 They also play very important role for the transformation of
72 the IRA internal representation of several regions into a one
73 region representation. The later is used during the reload
74 pass work because each allocno represents all of the
75 corresponding pseudo-registers.
77 - *Hard-register costs*. This is a vector of size equal to the
78 number of available hard-registers of the allocno class. The
79 cost of a callee-clobbered hard-register for an allocno is
80 increased by the cost of save/restore code around the calls
81 through the given allocno's life. If the allocno is a move
82 instruction operand and another operand is a hard-register of
83 the allocno class, the cost of the hard-register is decreased
86 When an allocno is assigned, the hard-register with minimal
87 full cost is used. Initially, a hard-register's full cost is
88 the corresponding value from the hard-register's cost vector.
89 If the allocno is connected by a *copy* (see below) to
90 another allocno which has just received a hard-register, the
91 cost of the hard-register is decreased. Before choosing a
92 hard-register for an allocno, the allocno's current costs of
93 the hard-registers are modified by the conflict hard-register
94 costs of all of the conflicting allocnos which are not
97 - *Conflict hard-register costs*. This is a vector of the same
98 size as the hard-register costs vector. To permit an
99 unassigned allocno to get a better hard-register, IRA uses
100 this vector to calculate the final full cost of the
101 available hard-registers. Conflict hard-register costs of an
102 unassigned allocno are also changed with a change of the
103 hard-register cost of the allocno when a copy involving the
104 allocno is processed as described above. This is done to
105 show other unassigned allocnos that a given allocno prefers
106 some hard-registers in order to remove the move instruction
107 corresponding to the copy.
109 o *Cap*. If a pseudo-register does not live in a region but
110 lives in a nested region, IRA creates a special allocno called
111 a cap in the outer region. A region cap is also created for a
114 o *Copy*. Allocnos can be connected by copies. Copies are used
115 to modify hard-register costs for allocnos during coloring.
116 Such modifications reflects a preference to use the same
117 hard-register for the allocnos connected by copies. Usually
118 copies are created for move insns (in this case it results in
119 register coalescing). But IRA also creates copies for operands
120 of an insn which should be assigned to the same hard-register
121 due to constraints in the machine description (it usually
122 results in removing a move generated in reload to satisfy
123 the constraints) and copies referring to the allocno which is
124 the output operand of an instruction and the allocno which is
125 an input operand dying in the instruction (creation of such
126 copies results in less register shuffling). IRA *does not*
127 create copies between the same register allocnos from different
128 regions because we use another technique for propagating
129 hard-register preference on the borders of regions.
131 Allocnos (including caps) for the upper region in the region tree
132 *accumulate* information important for coloring from allocnos with
133 the same pseudo-register from nested regions. This includes
134 hard-register and memory costs, conflicts with hard-registers,
135 allocno conflicts, allocno copies and more. *Thus, attributes for
136 allocnos in a region have the same values as if the region had no
137 subregions*. It means that attributes for allocnos in the
138 outermost region corresponding to the function have the same values
139 as though the allocation used only one region which is the entire
140 function. It also means that we can look at IRA work as if the
141 first IRA did allocation for all function then it improved the
142 allocation for loops then their subloops and so on.
144 IRA major passes are:
146 o Building IRA internal representation which consists of the
149 * First, IRA builds regions and creates allocnos (file
150 ira-build.c) and initializes most of their attributes.
152 * Then IRA finds an allocno class for each allocno and
153 calculates its initial (non-accumulated) cost of memory and
154 each hard-register of its allocno class (file ira-cost.c).
156 * IRA creates live ranges of each allocno, calculates register
157 pressure for each pressure class in each region, sets up
158 conflict hard registers for each allocno and info about calls
159 the allocno lives through (file ira-lives.c).
161 * IRA removes low register pressure loops from the regions
162 mostly to speed IRA up (file ira-build.c).
164 * IRA propagates accumulated allocno info from lower region
165 allocnos to corresponding upper region allocnos (file
168 * IRA creates all caps (file ira-build.c).
170 * Having live-ranges of allocnos and their classes, IRA creates
171 conflicting allocnos for each allocno. Conflicting allocnos
172 are stored as a bit vector or array of pointers to the
173 conflicting allocnos whatever is more profitable (file
174 ira-conflicts.c). At this point IRA creates allocno copies.
176 o Coloring. Now IRA has all necessary info to start graph coloring
177 process. It is done in each region on top-down traverse of the
178 region tree (file ira-color.c). There are following subpasses:
180 * Finding profitable hard registers of corresponding allocno
181 class for each allocno. For example, only callee-saved hard
182 registers are frequently profitable for allocnos living
183 through colors. If the profitable hard register set of
184 allocno does not form a tree based on subset relation, we use
185 some approximation to form the tree. This approximation is
186 used to figure out trivial colorability of allocnos. The
187 approximation is a pretty rare case.
189 * Putting allocnos onto the coloring stack. IRA uses Briggs
190 optimistic coloring which is a major improvement over
191 Chaitin's coloring. Therefore IRA does not spill allocnos at
192 this point. There is some freedom in the order of putting
193 allocnos on the stack which can affect the final result of
194 the allocation. IRA uses some heuristics to improve the
195 order. The major one is to form *threads* from colorable
196 allocnos and push them on the stack by threads. Thread is a
197 set of non-conflicting colorable allocnos connected by
198 copies. The thread contains allocnos from the colorable
199 bucket or colorable allocnos already pushed onto the coloring
200 stack. Pushing thread allocnos one after another onto the
201 stack increases chances of removing copies when the allocnos
202 get the same hard reg.
204 We also use a modification of Chaitin-Briggs algorithm which
205 works for intersected register classes of allocnos. To
206 figure out trivial colorability of allocnos, the mentioned
207 above tree of hard register sets is used. To get an idea how
208 the algorithm works in i386 example, let us consider an
209 allocno to which any general hard register can be assigned.
210 If the allocno conflicts with eight allocnos to which only
211 EAX register can be assigned, given allocno is still
212 trivially colorable because all conflicting allocnos might be
213 assigned only to EAX and all other general hard registers are
216 To get an idea of the used trivial colorability criterion, it
217 is also useful to read article "Graph-Coloring Register
218 Allocation for Irregular Architectures" by Michael D. Smith
219 and Glen Holloway. Major difference between the article
220 approach and approach used in IRA is that Smith's approach
221 takes register classes only from machine description and IRA
222 calculate register classes from intermediate code too
223 (e.g. an explicit usage of hard registers in RTL code for
224 parameter passing can result in creation of additional
225 register classes which contain or exclude the hard
226 registers). That makes IRA approach useful for improving
227 coloring even for architectures with regular register files
228 and in fact some benchmarking shows the improvement for
229 regular class architectures is even bigger than for irregular
230 ones. Another difference is that Smith's approach chooses
231 intersection of classes of all insn operands in which a given
232 pseudo occurs. IRA can use bigger classes if it is still
233 more profitable than memory usage.
235 * Popping the allocnos from the stack and assigning them hard
236 registers. If IRA cannot assign a hard register to an
237 allocno and the allocno is coalesced, IRA undoes the
238 coalescing and puts the uncoalesced allocnos onto the stack in
239 the hope that some such allocnos will get a hard register
240 separately. If IRA fails to assign hard register or memory
241 is more profitable for it, IRA spills the allocno. IRA
242 assigns the allocno the hard-register with minimal full
243 allocation cost which reflects the cost of usage of the
244 hard-register for the allocno and cost of usage of the
245 hard-register for allocnos conflicting with given allocno.
247 * Chaitin-Briggs coloring assigns as many pseudos as possible
248 to hard registers. After coloring we try to improve
249 allocation with cost point of view. We improve the
250 allocation by spilling some allocnos and assigning the freed
251 hard registers to other allocnos if it decreases the overall
254 * After allocno assigning in the region, IRA modifies the hard
255 register and memory costs for the corresponding allocnos in
256 the subregions to reflect the cost of possible loads, stores,
257 or moves on the border of the region and its subregions.
258 When default regional allocation algorithm is used
259 (-fira-algorithm=mixed), IRA just propagates the assignment
260 for allocnos if the register pressure in the region for the
261 corresponding pressure class is less than number of available
262 hard registers for given pressure class.
264 o Spill/restore code moving. When IRA performs an allocation
265 by traversing regions in top-down order, it does not know what
266 happens below in the region tree. Therefore, sometimes IRA
267 misses opportunities to perform a better allocation. A simple
268 optimization tries to improve allocation in a region having
269 subregions and containing in another region. If the
270 corresponding allocnos in the subregion are spilled, it spills
271 the region allocno if it is profitable. The optimization
272 implements a simple iterative algorithm performing profitable
273 transformations while they are still possible. It is fast in
274 practice, so there is no real need for a better time complexity
277 o Code change. After coloring, two allocnos representing the
278 same pseudo-register outside and inside a region respectively
279 may be assigned to different locations (hard-registers or
280 memory). In this case IRA creates and uses a new
281 pseudo-register inside the region and adds code to move allocno
282 values on the region's borders. This is done during top-down
283 traversal of the regions (file ira-emit.c). In some
284 complicated cases IRA can create a new allocno to move allocno
285 values (e.g. when a swap of values stored in two hard-registers
286 is needed). At this stage, the new allocno is marked as
287 spilled. IRA still creates the pseudo-register and the moves
288 on the region borders even when both allocnos were assigned to
289 the same hard-register. If the reload pass spills a
290 pseudo-register for some reason, the effect will be smaller
291 because another allocno will still be in the hard-register. In
292 most cases, this is better then spilling both allocnos. If
293 reload does not change the allocation for the two
294 pseudo-registers, the trivial move will be removed by
295 post-reload optimizations. IRA does not generate moves for
296 allocnos assigned to the same hard register when the default
297 regional allocation algorithm is used and the register pressure
298 in the region for the corresponding pressure class is less than
299 number of available hard registers for given pressure class.
300 IRA also does some optimizations to remove redundant stores and
301 to reduce code duplication on the region borders.
303 o Flattening internal representation. After changing code, IRA
304 transforms its internal representation for several regions into
305 one region representation (file ira-build.c). This process is
306 called IR flattening. Such process is more complicated than IR
307 rebuilding would be, but is much faster.
309 o After IR flattening, IRA tries to assign hard registers to all
310 spilled allocnos. This is implemented by a simple and fast
311 priority coloring algorithm (see function
312 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos
313 created during the code change pass can be assigned to hard
316 o At the end IRA calls the reload pass. The reload pass
317 communicates with IRA through several functions in file
318 ira-color.c to improve its decisions in
320 * sharing stack slots for the spilled pseudos based on IRA info
321 about pseudo-register conflicts.
323 * reassigning hard-registers to all spilled pseudos at the end
324 of each reload iteration.
326 * choosing a better hard-register to spill based on IRA info
327 about pseudo-register live ranges and the register pressure
328 in places where the pseudo-register lives.
330 IRA uses a lot of data representing the target processors. These
331 data are initialized in file ira.c.
333 If function has no loops (or the loops are ignored when
334 -fira-algorithm=CB is used), we have classic Chaitin-Briggs
335 coloring (only instead of separate pass of coalescing, we use hard
336 register preferencing). In such case, IRA works much faster
337 because many things are not made (like IR flattening, the
338 spill/restore optimization, and the code change).
340 Literature is worth to read for better understanding the code:
342 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to
343 Graph Coloring Register Allocation.
345 o David Callahan, Brian Koblenz. Register allocation via
346 hierarchical graph coloring.
348 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph
349 Coloring Register Allocation: A Study of the Chaitin-Briggs and
350 Callahan-Koblenz Algorithms.
352 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global
353 Register Allocation Based on Graph Fusion.
355 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register
356 Allocation for Irregular Architectures
358 o Vladimir Makarov. The Integrated Register Allocator for GCC.
360 o Vladimir Makarov. The top-down register allocator for irregular
361 register file architectures.
368 #include "coretypes.h"
374 #include "memmodel.h"
376 #include "insn-config.h"
380 #include "diagnostic-core.h"
382 #include "cfgbuild.h"
383 #include "cfgcleanup.h"
385 #include "tree-pass.h"
392 #include "rtl-iter.h"
393 #include "shrink-wrap.h"
394 #include "print-rtl.h"
396 struct target_ira default_target_ira
;
397 class target_ira_int default_target_ira_int
;
398 #if SWITCHABLE_TARGET
399 struct target_ira
*this_target_ira
= &default_target_ira
;
400 class target_ira_int
*this_target_ira_int
= &default_target_ira_int
;
403 /* A modified value of flag `-fira-verbose' used internally. */
404 int internal_flag_ira_verbose
;
406 /* Dump file of the allocator if it is not NULL. */
409 /* The number of elements in the following array. */
410 int ira_spilled_reg_stack_slots_num
;
412 /* The following array contains info about spilled pseudo-registers
413 stack slots used in current function so far. */
414 class ira_spilled_reg_stack_slot
*ira_spilled_reg_stack_slots
;
416 /* Correspondingly overall cost of the allocation, overall cost before
417 reload, cost of the allocnos assigned to hard-registers, cost of
418 the allocnos assigned to memory, cost of loads, stores and register
419 move insns generated for pseudo-register live range splitting (see
421 int64_t ira_overall_cost
, overall_cost_before
;
422 int64_t ira_reg_cost
, ira_mem_cost
;
423 int64_t ira_load_cost
, ira_store_cost
, ira_shuffle_cost
;
424 int ira_move_loops_num
, ira_additional_jumps_num
;
426 /* All registers that can be eliminated. */
428 HARD_REG_SET eliminable_regset
;
430 /* Value of max_reg_num () before IRA work start. This value helps
431 us to recognize a situation when new pseudos were created during
433 static int max_regno_before_ira
;
435 /* Temporary hard reg set used for a different calculation. */
436 static HARD_REG_SET temp_hard_regset
;
438 #define last_mode_for_init_move_cost \
439 (this_target_ira_int->x_last_mode_for_init_move_cost)
442 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */
444 setup_reg_mode_hard_regset (void)
446 int i
, m
, hard_regno
;
448 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
449 for (hard_regno
= 0; hard_regno
< FIRST_PSEUDO_REGISTER
; hard_regno
++)
451 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset
[hard_regno
][m
]);
452 for (i
= hard_regno_nregs (hard_regno
, (machine_mode
) m
) - 1;
454 if (hard_regno
+ i
< FIRST_PSEUDO_REGISTER
)
455 SET_HARD_REG_BIT (ira_reg_mode_hard_regset
[hard_regno
][m
],
461 #define no_unit_alloc_regs \
462 (this_target_ira_int->x_no_unit_alloc_regs)
464 /* The function sets up the three arrays declared above. */
466 setup_class_hard_regs (void)
468 int cl
, i
, hard_regno
, n
;
469 HARD_REG_SET processed_hard_reg_set
;
471 ira_assert (SHRT_MAX
>= FIRST_PSEUDO_REGISTER
);
472 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
474 temp_hard_regset
= reg_class_contents
[cl
];
475 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
476 CLEAR_HARD_REG_SET (processed_hard_reg_set
);
477 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
479 ira_non_ordered_class_hard_regs
[cl
][i
] = -1;
480 ira_class_hard_reg_index
[cl
][i
] = -1;
482 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
484 #ifdef REG_ALLOC_ORDER
485 hard_regno
= reg_alloc_order
[i
];
489 if (TEST_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
))
491 SET_HARD_REG_BIT (processed_hard_reg_set
, hard_regno
);
492 if (! TEST_HARD_REG_BIT (temp_hard_regset
, hard_regno
))
493 ira_class_hard_reg_index
[cl
][hard_regno
] = -1;
496 ira_class_hard_reg_index
[cl
][hard_regno
] = n
;
497 ira_class_hard_regs
[cl
][n
++] = hard_regno
;
500 ira_class_hard_regs_num
[cl
] = n
;
501 for (n
= 0, i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
502 if (TEST_HARD_REG_BIT (temp_hard_regset
, i
))
503 ira_non_ordered_class_hard_regs
[cl
][n
++] = i
;
504 ira_assert (ira_class_hard_regs_num
[cl
] == n
);
508 /* Set up global variables defining info about hard registers for the
509 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means
510 that we can use the hard frame pointer for the allocation. */
512 setup_alloc_regs (bool use_hard_frame_p
)
514 #ifdef ADJUST_REG_ALLOC_ORDER
515 ADJUST_REG_ALLOC_ORDER
;
517 no_unit_alloc_regs
= fixed_nonglobal_reg_set
;
518 if (! use_hard_frame_p
)
519 SET_HARD_REG_BIT (no_unit_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
520 setup_class_hard_regs ();
525 #define alloc_reg_class_subclasses \
526 (this_target_ira_int->x_alloc_reg_class_subclasses)
528 /* Initialize the table of subclasses of each reg class. */
530 setup_reg_subclasses (void)
533 HARD_REG_SET temp_hard_regset2
;
535 for (i
= 0; i
< N_REG_CLASSES
; i
++)
536 for (j
= 0; j
< N_REG_CLASSES
; j
++)
537 alloc_reg_class_subclasses
[i
][j
] = LIM_REG_CLASSES
;
539 for (i
= 0; i
< N_REG_CLASSES
; i
++)
541 if (i
== (int) NO_REGS
)
544 temp_hard_regset
= reg_class_contents
[i
];
545 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
546 if (hard_reg_set_empty_p (temp_hard_regset
))
548 for (j
= 0; j
< N_REG_CLASSES
; j
++)
553 temp_hard_regset2
= reg_class_contents
[j
];
554 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
555 if (! hard_reg_set_subset_p (temp_hard_regset
,
558 p
= &alloc_reg_class_subclasses
[j
][0];
559 while (*p
!= LIM_REG_CLASSES
) p
++;
560 *p
= (enum reg_class
) i
;
567 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */
569 setup_class_subset_and_memory_move_costs (void)
571 int cl
, cl2
, mode
, cost
;
572 HARD_REG_SET temp_hard_regset2
;
574 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
575 ira_memory_move_cost
[mode
][NO_REGS
][0]
576 = ira_memory_move_cost
[mode
][NO_REGS
][1] = SHRT_MAX
;
577 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
579 if (cl
!= (int) NO_REGS
)
580 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
582 ira_max_memory_move_cost
[mode
][cl
][0]
583 = ira_memory_move_cost
[mode
][cl
][0]
584 = memory_move_cost ((machine_mode
) mode
,
585 (reg_class_t
) cl
, false);
586 ira_max_memory_move_cost
[mode
][cl
][1]
587 = ira_memory_move_cost
[mode
][cl
][1]
588 = memory_move_cost ((machine_mode
) mode
,
589 (reg_class_t
) cl
, true);
590 /* Costs for NO_REGS are used in cost calculation on the
591 1st pass when the preferred register classes are not
592 known yet. In this case we take the best scenario. */
593 if (ira_memory_move_cost
[mode
][NO_REGS
][0]
594 > ira_memory_move_cost
[mode
][cl
][0])
595 ira_max_memory_move_cost
[mode
][NO_REGS
][0]
596 = ira_memory_move_cost
[mode
][NO_REGS
][0]
597 = ira_memory_move_cost
[mode
][cl
][0];
598 if (ira_memory_move_cost
[mode
][NO_REGS
][1]
599 > ira_memory_move_cost
[mode
][cl
][1])
600 ira_max_memory_move_cost
[mode
][NO_REGS
][1]
601 = ira_memory_move_cost
[mode
][NO_REGS
][1]
602 = ira_memory_move_cost
[mode
][cl
][1];
605 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
606 for (cl2
= (int) N_REG_CLASSES
- 1; cl2
>= 0; cl2
--)
608 temp_hard_regset
= reg_class_contents
[cl
];
609 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
610 temp_hard_regset2
= reg_class_contents
[cl2
];
611 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
612 ira_class_subset_p
[cl
][cl2
]
613 = hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
);
614 if (! hard_reg_set_empty_p (temp_hard_regset2
)
615 && hard_reg_set_subset_p (reg_class_contents
[cl2
],
616 reg_class_contents
[cl
]))
617 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
619 cost
= ira_memory_move_cost
[mode
][cl2
][0];
620 if (cost
> ira_max_memory_move_cost
[mode
][cl
][0])
621 ira_max_memory_move_cost
[mode
][cl
][0] = cost
;
622 cost
= ira_memory_move_cost
[mode
][cl2
][1];
623 if (cost
> ira_max_memory_move_cost
[mode
][cl
][1])
624 ira_max_memory_move_cost
[mode
][cl
][1] = cost
;
627 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
628 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
630 ira_memory_move_cost
[mode
][cl
][0]
631 = ira_max_memory_move_cost
[mode
][cl
][0];
632 ira_memory_move_cost
[mode
][cl
][1]
633 = ira_max_memory_move_cost
[mode
][cl
][1];
635 setup_reg_subclasses ();
640 /* Define the following macro if allocation through malloc if
642 #define IRA_NO_OBSTACK
644 #ifndef IRA_NO_OBSTACK
645 /* Obstack used for storing all dynamic data (except bitmaps) of the
647 static struct obstack ira_obstack
;
650 /* Obstack used for storing all bitmaps of the IRA. */
651 static struct bitmap_obstack ira_bitmap_obstack
;
653 /* Allocate memory of size LEN for IRA data. */
655 ira_allocate (size_t len
)
659 #ifndef IRA_NO_OBSTACK
660 res
= obstack_alloc (&ira_obstack
, len
);
667 /* Free memory ADDR allocated for IRA data. */
669 ira_free (void *addr ATTRIBUTE_UNUSED
)
671 #ifndef IRA_NO_OBSTACK
679 /* Allocate and returns bitmap for IRA. */
681 ira_allocate_bitmap (void)
683 return BITMAP_ALLOC (&ira_bitmap_obstack
);
686 /* Free bitmap B allocated for IRA. */
688 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED
)
695 /* Output information about allocation of all allocnos (except for
696 caps) into file F. */
698 ira_print_disposition (FILE *f
)
704 fprintf (f
, "Disposition:");
705 max_regno
= max_reg_num ();
706 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
707 for (a
= ira_regno_allocno_map
[i
];
709 a
= ALLOCNO_NEXT_REGNO_ALLOCNO (a
))
714 fprintf (f
, " %4d:r%-4d", ALLOCNO_NUM (a
), ALLOCNO_REGNO (a
));
715 if ((bb
= ALLOCNO_LOOP_TREE_NODE (a
)->bb
) != NULL
)
716 fprintf (f
, "b%-3d", bb
->index
);
718 fprintf (f
, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a
)->loop_num
);
719 if (ALLOCNO_HARD_REGNO (a
) >= 0)
720 fprintf (f
, " %3d", ALLOCNO_HARD_REGNO (a
));
727 /* Outputs information about allocation of all allocnos into
730 ira_debug_disposition (void)
732 ira_print_disposition (stderr
);
737 /* Set up ira_stack_reg_pressure_class which is the biggest pressure
738 register class containing stack registers or NO_REGS if there are
739 no stack registers. To find this class, we iterate through all
740 register pressure classes and choose the first register pressure
741 class containing all the stack registers and having the biggest
744 setup_stack_reg_pressure_class (void)
746 ira_stack_reg_pressure_class
= NO_REGS
;
751 HARD_REG_SET temp_hard_regset2
;
753 CLEAR_HARD_REG_SET (temp_hard_regset
);
754 for (i
= FIRST_STACK_REG
; i
<= LAST_STACK_REG
; i
++)
755 SET_HARD_REG_BIT (temp_hard_regset
, i
);
757 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
759 cl
= ira_pressure_classes
[i
];
760 temp_hard_regset2
= temp_hard_regset
& reg_class_contents
[cl
];
761 size
= hard_reg_set_size (temp_hard_regset2
);
765 ira_stack_reg_pressure_class
= cl
;
772 /* Find pressure classes which are register classes for which we
773 calculate register pressure in IRA, register pressure sensitive
774 insn scheduling, and register pressure sensitive loop invariant
777 To make register pressure calculation easy, we always use
778 non-intersected register pressure classes. A move of hard
779 registers from one register pressure class is not more expensive
780 than load and store of the hard registers. Most likely an allocno
781 class will be a subset of a register pressure class and in many
782 cases a register pressure class. That makes usage of register
783 pressure classes a good approximation to find a high register
786 setup_pressure_classes (void)
788 int cost
, i
, n
, curr
;
790 enum reg_class pressure_classes
[N_REG_CLASSES
];
792 HARD_REG_SET temp_hard_regset2
;
795 if (targetm
.compute_pressure_classes
)
796 n
= targetm
.compute_pressure_classes (pressure_classes
);
800 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
802 if (ira_class_hard_regs_num
[cl
] == 0)
804 if (ira_class_hard_regs_num
[cl
] != 1
805 /* A register class without subclasses may contain a few
806 hard registers and movement between them is costly
807 (e.g. SPARC FPCC registers). We still should consider it
808 as a candidate for a pressure class. */
809 && alloc_reg_class_subclasses
[cl
][0] < cl
)
811 /* Check that the moves between any hard registers of the
812 current class are not more expensive for a legal mode
813 than load/store of the hard registers of the current
814 class. Such class is a potential candidate to be a
815 register pressure class. */
816 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
818 temp_hard_regset
= reg_class_contents
[cl
];
819 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
820 AND_COMPL_HARD_REG_SET (temp_hard_regset
,
821 ira_prohibited_class_mode_regs
[cl
][m
]);
822 if (hard_reg_set_empty_p (temp_hard_regset
))
824 ira_init_register_move_cost_if_necessary ((machine_mode
) m
);
825 cost
= ira_register_move_cost
[m
][cl
][cl
];
826 if (cost
<= ira_max_memory_move_cost
[m
][cl
][1]
827 || cost
<= ira_max_memory_move_cost
[m
][cl
][0])
830 if (m
>= NUM_MACHINE_MODES
)
835 temp_hard_regset
= reg_class_contents
[cl
];
836 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
837 /* Remove so far added pressure classes which are subset of the
838 current candidate class. Prefer GENERAL_REGS as a pressure
839 register class to another class containing the same
840 allocatable hard registers. We do this because machine
841 dependent cost hooks might give wrong costs for the latter
842 class but always give the right cost for the former class
844 for (i
= 0; i
< n
; i
++)
846 cl2
= pressure_classes
[i
];
847 temp_hard_regset2
= reg_class_contents
[cl2
];
848 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
849 if (hard_reg_set_subset_p (temp_hard_regset
, temp_hard_regset2
)
850 && (! hard_reg_set_equal_p (temp_hard_regset
,
852 || cl2
== (int) GENERAL_REGS
))
854 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
858 if (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
)
859 && (! hard_reg_set_equal_p (temp_hard_regset2
,
861 || cl
== (int) GENERAL_REGS
))
863 if (hard_reg_set_equal_p (temp_hard_regset2
, temp_hard_regset
))
865 pressure_classes
[curr
++] = (enum reg_class
) cl2
;
867 /* If the current candidate is a subset of a so far added
868 pressure class, don't add it to the list of the pressure
871 pressure_classes
[curr
++] = (enum reg_class
) cl
;
875 #ifdef ENABLE_IRA_CHECKING
877 HARD_REG_SET ignore_hard_regs
;
879 /* Check pressure classes correctness: here we check that hard
880 registers from all register pressure classes contains all hard
881 registers available for the allocation. */
882 CLEAR_HARD_REG_SET (temp_hard_regset
);
883 CLEAR_HARD_REG_SET (temp_hard_regset2
);
884 ignore_hard_regs
= no_unit_alloc_regs
;
885 for (cl
= 0; cl
< LIM_REG_CLASSES
; cl
++)
887 /* For some targets (like MIPS with MD_REGS), there are some
888 classes with hard registers available for allocation but
889 not able to hold value of any mode. */
890 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
891 if (contains_reg_of_mode
[cl
][m
])
893 if (m
>= NUM_MACHINE_MODES
)
895 IOR_HARD_REG_SET (ignore_hard_regs
, reg_class_contents
[cl
]);
898 for (i
= 0; i
< n
; i
++)
899 if ((int) pressure_classes
[i
] == cl
)
901 IOR_HARD_REG_SET (temp_hard_regset2
, reg_class_contents
[cl
]);
903 IOR_HARD_REG_SET (temp_hard_regset
, reg_class_contents
[cl
]);
905 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
906 /* Some targets (like SPARC with ICC reg) have allocatable regs
907 for which no reg class is defined. */
908 if (REGNO_REG_CLASS (i
) == NO_REGS
)
909 SET_HARD_REG_BIT (ignore_hard_regs
, i
);
910 AND_COMPL_HARD_REG_SET (temp_hard_regset
, ignore_hard_regs
);
911 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, ignore_hard_regs
);
912 ira_assert (hard_reg_set_subset_p (temp_hard_regset2
, temp_hard_regset
));
915 ira_pressure_classes_num
= 0;
916 for (i
= 0; i
< n
; i
++)
918 cl
= (int) pressure_classes
[i
];
919 ira_reg_pressure_class_p
[cl
] = true;
920 ira_pressure_classes
[ira_pressure_classes_num
++] = (enum reg_class
) cl
;
922 setup_stack_reg_pressure_class ();
925 /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class
926 whose register move cost between any registers of the class is the
927 same as for all its subclasses. We use the data to speed up the
928 2nd pass of calculations of allocno costs. */
930 setup_uniform_class_p (void)
934 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
936 ira_uniform_class_p
[cl
] = false;
937 if (ira_class_hard_regs_num
[cl
] == 0)
939 /* We cannot use alloc_reg_class_subclasses here because move
940 cost hooks does not take into account that some registers are
941 unavailable for the subtarget. E.g. for i686, INT_SSE_REGS
942 is element of alloc_reg_class_subclasses for GENERAL_REGS
943 because SSE regs are unavailable. */
944 for (i
= 0; (cl2
= reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
; i
++)
946 if (ira_class_hard_regs_num
[cl2
] == 0)
948 for (m
= 0; m
< NUM_MACHINE_MODES
; m
++)
949 if (contains_reg_of_mode
[cl
][m
] && contains_reg_of_mode
[cl2
][m
])
951 ira_init_register_move_cost_if_necessary ((machine_mode
) m
);
952 if (ira_register_move_cost
[m
][cl
][cl
]
953 != ira_register_move_cost
[m
][cl2
][cl2
])
956 if (m
< NUM_MACHINE_MODES
)
959 if (cl2
== LIM_REG_CLASSES
)
960 ira_uniform_class_p
[cl
] = true;
964 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM,
965 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM.
967 Target may have many subtargets and not all target hard registers can
968 be used for allocation, e.g. x86 port in 32-bit mode cannot use
969 hard registers introduced in x86-64 like r8-r15). Some classes
970 might have the same allocatable hard registers, e.g. INDEX_REGS
971 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different
972 calculations efforts we introduce allocno classes which contain
973 unique non-empty sets of allocatable hard-registers.
975 Pseudo class cost calculation in ira-costs.c is very expensive.
976 Therefore we are trying to decrease number of classes involved in
977 such calculation. Register classes used in the cost calculation
978 are called important classes. They are allocno classes and other
979 non-empty classes whose allocatable hard register sets are inside
980 of an allocno class hard register set. From the first sight, it
981 looks like that they are just allocno classes. It is not true. In
982 example of x86-port in 32-bit mode, allocno classes will contain
983 GENERAL_REGS but not LEGACY_REGS (because allocatable hard
984 registers are the same for the both classes). The important
985 classes will contain GENERAL_REGS and LEGACY_REGS. It is done
986 because a machine description insn constraint may refers for
987 LEGACY_REGS and code in ira-costs.c is mostly base on investigation
988 of the insn constraints. */
990 setup_allocno_and_important_classes (void)
994 HARD_REG_SET temp_hard_regset2
;
995 static enum reg_class classes
[LIM_REG_CLASSES
+ 1];
998 /* Collect classes which contain unique sets of allocatable hard
999 registers. Prefer GENERAL_REGS to other classes containing the
1000 same set of hard registers. */
1001 for (i
= 0; i
< LIM_REG_CLASSES
; i
++)
1003 temp_hard_regset
= reg_class_contents
[i
];
1004 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1005 for (j
= 0; j
< n
; j
++)
1008 temp_hard_regset2
= reg_class_contents
[cl
];
1009 AND_COMPL_HARD_REG_SET (temp_hard_regset2
,
1010 no_unit_alloc_regs
);
1011 if (hard_reg_set_equal_p (temp_hard_regset
,
1015 if (j
>= n
|| targetm
.additional_allocno_class_p (i
))
1016 classes
[n
++] = (enum reg_class
) i
;
1017 else if (i
== GENERAL_REGS
)
1018 /* Prefer general regs. For i386 example, it means that
1019 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS
1020 (all of them consists of the same available hard
1022 classes
[j
] = (enum reg_class
) i
;
1024 classes
[n
] = LIM_REG_CLASSES
;
1026 /* Set up classes which can be used for allocnos as classes
1027 containing non-empty unique sets of allocatable hard
1029 ira_allocno_classes_num
= 0;
1030 for (i
= 0; (cl
= classes
[i
]) != LIM_REG_CLASSES
; i
++)
1031 if (ira_class_hard_regs_num
[cl
] > 0)
1032 ira_allocno_classes
[ira_allocno_classes_num
++] = (enum reg_class
) cl
;
1033 ira_important_classes_num
= 0;
1034 /* Add non-allocno classes containing to non-empty set of
1035 allocatable hard regs. */
1036 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1037 if (ira_class_hard_regs_num
[cl
] > 0)
1039 temp_hard_regset
= reg_class_contents
[cl
];
1040 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1042 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1044 temp_hard_regset2
= reg_class_contents
[ira_allocno_classes
[j
]];
1045 AND_COMPL_HARD_REG_SET (temp_hard_regset2
, no_unit_alloc_regs
);
1046 if ((enum reg_class
) cl
== ira_allocno_classes
[j
])
1048 else if (hard_reg_set_subset_p (temp_hard_regset
,
1052 if (set_p
&& j
>= ira_allocno_classes_num
)
1053 ira_important_classes
[ira_important_classes_num
++]
1054 = (enum reg_class
) cl
;
1056 /* Now add allocno classes to the important classes. */
1057 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1058 ira_important_classes
[ira_important_classes_num
++]
1059 = ira_allocno_classes
[j
];
1060 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1062 ira_reg_allocno_class_p
[cl
] = false;
1063 ira_reg_pressure_class_p
[cl
] = false;
1065 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1066 ira_reg_allocno_class_p
[ira_allocno_classes
[j
]] = true;
1067 setup_pressure_classes ();
1068 setup_uniform_class_p ();
1071 /* Setup translation in CLASS_TRANSLATE of all classes into a class
1072 given by array CLASSES of length CLASSES_NUM. The function is used
1073 make translation any reg class to an allocno class or to an
1074 pressure class. This translation is necessary for some
1075 calculations when we can use only allocno or pressure classes and
1076 such translation represents an approximate representation of all
1079 The translation in case when allocatable hard register set of a
1080 given class is subset of allocatable hard register set of a class
1081 in CLASSES is pretty simple. We use smallest classes from CLASSES
1082 containing a given class. If allocatable hard register set of a
1083 given class is not a subset of any corresponding set of a class
1084 from CLASSES, we use the cheapest (with load/store point of view)
1085 class from CLASSES whose set intersects with given class set. */
1087 setup_class_translate_array (enum reg_class
*class_translate
,
1088 int classes_num
, enum reg_class
*classes
)
1091 enum reg_class aclass
, best_class
, *cl_ptr
;
1092 int i
, cost
, min_cost
, best_cost
;
1094 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1095 class_translate
[cl
] = NO_REGS
;
1097 for (i
= 0; i
< classes_num
; i
++)
1099 aclass
= classes
[i
];
1100 for (cl_ptr
= &alloc_reg_class_subclasses
[aclass
][0];
1101 (cl
= *cl_ptr
) != LIM_REG_CLASSES
;
1103 if (class_translate
[cl
] == NO_REGS
)
1104 class_translate
[cl
] = aclass
;
1105 class_translate
[aclass
] = aclass
;
1107 /* For classes which are not fully covered by one of given classes
1108 (in other words covered by more one given class), use the
1110 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1112 if (cl
== NO_REGS
|| class_translate
[cl
] != NO_REGS
)
1114 best_class
= NO_REGS
;
1115 best_cost
= INT_MAX
;
1116 for (i
= 0; i
< classes_num
; i
++)
1118 aclass
= classes
[i
];
1119 temp_hard_regset
= (reg_class_contents
[aclass
]
1120 & reg_class_contents
[cl
]);
1121 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1122 if (! hard_reg_set_empty_p (temp_hard_regset
))
1125 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1127 cost
= (ira_memory_move_cost
[mode
][aclass
][0]
1128 + ira_memory_move_cost
[mode
][aclass
][1]);
1129 if (min_cost
> cost
)
1132 if (best_class
== NO_REGS
|| best_cost
> min_cost
)
1134 best_class
= aclass
;
1135 best_cost
= min_cost
;
1139 class_translate
[cl
] = best_class
;
1143 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and
1144 IRA_PRESSURE_CLASS_TRANSLATE. */
1146 setup_class_translate (void)
1148 setup_class_translate_array (ira_allocno_class_translate
,
1149 ira_allocno_classes_num
, ira_allocno_classes
);
1150 setup_class_translate_array (ira_pressure_class_translate
,
1151 ira_pressure_classes_num
, ira_pressure_classes
);
1154 /* Order numbers of allocno classes in original target allocno class
1155 array, -1 for non-allocno classes. */
1156 static int allocno_class_order
[N_REG_CLASSES
];
1158 /* The function used to sort the important classes. */
1160 comp_reg_classes_func (const void *v1p
, const void *v2p
)
1162 enum reg_class cl1
= *(const enum reg_class
*) v1p
;
1163 enum reg_class cl2
= *(const enum reg_class
*) v2p
;
1164 enum reg_class tcl1
, tcl2
;
1167 tcl1
= ira_allocno_class_translate
[cl1
];
1168 tcl2
= ira_allocno_class_translate
[cl2
];
1169 if (tcl1
!= NO_REGS
&& tcl2
!= NO_REGS
1170 && (diff
= allocno_class_order
[tcl1
] - allocno_class_order
[tcl2
]) != 0)
1172 return (int) cl1
- (int) cl2
;
1175 /* For correct work of function setup_reg_class_relation we need to
1176 reorder important classes according to the order of their allocno
1177 classes. It places important classes containing the same
1178 allocatable hard register set adjacent to each other and allocno
1179 class with the allocatable hard register set right after the other
1180 important classes with the same set.
1182 In example from comments of function
1183 setup_allocno_and_important_classes, it places LEGACY_REGS and
1184 GENERAL_REGS close to each other and GENERAL_REGS is after
1187 reorder_important_classes (void)
1191 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1192 allocno_class_order
[i
] = -1;
1193 for (i
= 0; i
< ira_allocno_classes_num
; i
++)
1194 allocno_class_order
[ira_allocno_classes
[i
]] = i
;
1195 qsort (ira_important_classes
, ira_important_classes_num
,
1196 sizeof (enum reg_class
), comp_reg_classes_func
);
1197 for (i
= 0; i
< ira_important_classes_num
; i
++)
1198 ira_important_class_nums
[ira_important_classes
[i
]] = i
;
1201 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION,
1202 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and
1203 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations,
1204 please see corresponding comments in ira-int.h. */
1206 setup_reg_class_relations (void)
1208 int i
, cl1
, cl2
, cl3
;
1209 HARD_REG_SET intersection_set
, union_set
, temp_set2
;
1210 bool important_class_p
[N_REG_CLASSES
];
1212 memset (important_class_p
, 0, sizeof (important_class_p
));
1213 for (i
= 0; i
< ira_important_classes_num
; i
++)
1214 important_class_p
[ira_important_classes
[i
]] = true;
1215 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1217 ira_reg_class_super_classes
[cl1
][0] = LIM_REG_CLASSES
;
1218 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1220 ira_reg_classes_intersect_p
[cl1
][cl2
] = false;
1221 ira_reg_class_intersect
[cl1
][cl2
] = NO_REGS
;
1222 ira_reg_class_subset
[cl1
][cl2
] = NO_REGS
;
1223 temp_hard_regset
= reg_class_contents
[cl1
];
1224 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1225 temp_set2
= reg_class_contents
[cl2
];
1226 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1227 if (hard_reg_set_empty_p (temp_hard_regset
)
1228 && hard_reg_set_empty_p (temp_set2
))
1230 /* The both classes have no allocatable hard registers
1231 -- take all class hard registers into account and use
1232 reg_class_subunion and reg_class_superunion. */
1235 cl3
= reg_class_subclasses
[cl1
][i
];
1236 if (cl3
== LIM_REG_CLASSES
)
1238 if (reg_class_subset_p (ira_reg_class_intersect
[cl1
][cl2
],
1239 (enum reg_class
) cl3
))
1240 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1242 ira_reg_class_subunion
[cl1
][cl2
] = reg_class_subunion
[cl1
][cl2
];
1243 ira_reg_class_superunion
[cl1
][cl2
] = reg_class_superunion
[cl1
][cl2
];
1246 ira_reg_classes_intersect_p
[cl1
][cl2
]
1247 = hard_reg_set_intersect_p (temp_hard_regset
, temp_set2
);
1248 if (important_class_p
[cl1
] && important_class_p
[cl2
]
1249 && hard_reg_set_subset_p (temp_hard_regset
, temp_set2
))
1251 /* CL1 and CL2 are important classes and CL1 allocatable
1252 hard register set is inside of CL2 allocatable hard
1253 registers -- make CL1 a superset of CL2. */
1256 p
= &ira_reg_class_super_classes
[cl1
][0];
1257 while (*p
!= LIM_REG_CLASSES
)
1259 *p
++ = (enum reg_class
) cl2
;
1260 *p
= LIM_REG_CLASSES
;
1262 ira_reg_class_subunion
[cl1
][cl2
] = NO_REGS
;
1263 ira_reg_class_superunion
[cl1
][cl2
] = NO_REGS
;
1264 intersection_set
= (reg_class_contents
[cl1
]
1265 & reg_class_contents
[cl2
]);
1266 AND_COMPL_HARD_REG_SET (intersection_set
, no_unit_alloc_regs
);
1267 union_set
= reg_class_contents
[cl1
];
1268 IOR_HARD_REG_SET (union_set
, reg_class_contents
[cl2
]);
1269 AND_COMPL_HARD_REG_SET (union_set
, no_unit_alloc_regs
);
1270 for (cl3
= 0; cl3
< N_REG_CLASSES
; cl3
++)
1272 temp_hard_regset
= reg_class_contents
[cl3
];
1273 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1274 if (hard_reg_set_subset_p (temp_hard_regset
, intersection_set
))
1276 /* CL3 allocatable hard register set is inside of
1277 intersection of allocatable hard register sets
1279 if (important_class_p
[cl3
])
1282 = (reg_class_contents
1283 [ira_reg_class_intersect
[cl1
][cl2
]]);
1284 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1285 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1286 /* If the allocatable hard register sets are
1287 the same, prefer GENERAL_REGS or the
1288 smallest class for debugging
1290 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1291 && (cl3
== GENERAL_REGS
1292 || ((ira_reg_class_intersect
[cl1
][cl2
]
1294 && hard_reg_set_subset_p
1295 (reg_class_contents
[cl3
],
1298 ira_reg_class_intersect
[cl1
][cl2
]])))))
1299 ira_reg_class_intersect
[cl1
][cl2
] = (enum reg_class
) cl3
;
1302 = reg_class_contents
[ira_reg_class_subset
[cl1
][cl2
]];
1303 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1304 if (! hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1305 /* Ignore unavailable hard registers and prefer
1306 smallest class for debugging purposes. */
1307 || (hard_reg_set_equal_p (temp_hard_regset
, temp_set2
)
1308 && hard_reg_set_subset_p
1309 (reg_class_contents
[cl3
],
1311 [(int) ira_reg_class_subset
[cl1
][cl2
]])))
1312 ira_reg_class_subset
[cl1
][cl2
] = (enum reg_class
) cl3
;
1314 if (important_class_p
[cl3
]
1315 && hard_reg_set_subset_p (temp_hard_regset
, union_set
))
1317 /* CL3 allocatable hard register set is inside of
1318 union of allocatable hard register sets of CL1
1321 = reg_class_contents
[ira_reg_class_subunion
[cl1
][cl2
]];
1322 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1323 if (ira_reg_class_subunion
[cl1
][cl2
] == NO_REGS
1324 || (hard_reg_set_subset_p (temp_set2
, temp_hard_regset
)
1326 && (! hard_reg_set_equal_p (temp_set2
,
1328 || cl3
== GENERAL_REGS
1329 /* If the allocatable hard register sets are the
1330 same, prefer GENERAL_REGS or the smallest
1331 class for debugging purposes. */
1332 || (ira_reg_class_subunion
[cl1
][cl2
] != GENERAL_REGS
1333 && hard_reg_set_subset_p
1334 (reg_class_contents
[cl3
],
1336 [(int) ira_reg_class_subunion
[cl1
][cl2
]])))))
1337 ira_reg_class_subunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1339 if (hard_reg_set_subset_p (union_set
, temp_hard_regset
))
1341 /* CL3 allocatable hard register set contains union
1342 of allocatable hard register sets of CL1 and
1345 = reg_class_contents
[ira_reg_class_superunion
[cl1
][cl2
]];
1346 AND_COMPL_HARD_REG_SET (temp_set2
, no_unit_alloc_regs
);
1347 if (ira_reg_class_superunion
[cl1
][cl2
] == NO_REGS
1348 || (hard_reg_set_subset_p (temp_hard_regset
, temp_set2
)
1350 && (! hard_reg_set_equal_p (temp_set2
,
1352 || cl3
== GENERAL_REGS
1353 /* If the allocatable hard register sets are the
1354 same, prefer GENERAL_REGS or the smallest
1355 class for debugging purposes. */
1356 || (ira_reg_class_superunion
[cl1
][cl2
] != GENERAL_REGS
1357 && hard_reg_set_subset_p
1358 (reg_class_contents
[cl3
],
1360 [(int) ira_reg_class_superunion
[cl1
][cl2
]])))))
1361 ira_reg_class_superunion
[cl1
][cl2
] = (enum reg_class
) cl3
;
1368 /* Output all uniform and important classes into file F. */
1370 print_uniform_and_important_classes (FILE *f
)
1374 fprintf (f
, "Uniform classes:\n");
1375 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1376 if (ira_uniform_class_p
[cl
])
1377 fprintf (f
, " %s", reg_class_names
[cl
]);
1378 fprintf (f
, "\nImportant classes:\n");
1379 for (i
= 0; i
< ira_important_classes_num
; i
++)
1380 fprintf (f
, " %s", reg_class_names
[ira_important_classes
[i
]]);
1384 /* Output all possible allocno or pressure classes and their
1385 translation map into file F. */
1387 print_translated_classes (FILE *f
, bool pressure_p
)
1389 int classes_num
= (pressure_p
1390 ? ira_pressure_classes_num
: ira_allocno_classes_num
);
1391 enum reg_class
*classes
= (pressure_p
1392 ? ira_pressure_classes
: ira_allocno_classes
);
1393 enum reg_class
*class_translate
= (pressure_p
1394 ? ira_pressure_class_translate
1395 : ira_allocno_class_translate
);
1398 fprintf (f
, "%s classes:\n", pressure_p
? "Pressure" : "Allocno");
1399 for (i
= 0; i
< classes_num
; i
++)
1400 fprintf (f
, " %s", reg_class_names
[classes
[i
]]);
1401 fprintf (f
, "\nClass translation:\n");
1402 for (i
= 0; i
< N_REG_CLASSES
; i
++)
1403 fprintf (f
, " %s -> %s\n", reg_class_names
[i
],
1404 reg_class_names
[class_translate
[i
]]);
1407 /* Output all possible allocno and translation classes and the
1408 translation maps into stderr. */
1410 ira_debug_allocno_classes (void)
1412 print_uniform_and_important_classes (stderr
);
1413 print_translated_classes (stderr
, false);
1414 print_translated_classes (stderr
, true);
1417 /* Set up different arrays concerning class subsets, allocno and
1418 important classes. */
1420 find_reg_classes (void)
1422 setup_allocno_and_important_classes ();
1423 setup_class_translate ();
1424 reorder_important_classes ();
1425 setup_reg_class_relations ();
1430 /* Set up the array above. */
1432 setup_hard_regno_aclass (void)
1436 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1439 ira_hard_regno_allocno_class
[i
]
1440 = (TEST_HARD_REG_BIT (no_unit_alloc_regs
, i
)
1442 : ira_allocno_class_translate
[REGNO_REG_CLASS (i
)]);
1446 ira_hard_regno_allocno_class
[i
] = NO_REGS
;
1447 for (j
= 0; j
< ira_allocno_classes_num
; j
++)
1449 cl
= ira_allocno_classes
[j
];
1450 if (ira_class_hard_reg_index
[cl
][i
] >= 0)
1452 ira_hard_regno_allocno_class
[i
] = cl
;
1462 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */
1464 setup_reg_class_nregs (void)
1468 for (m
= 0; m
< MAX_MACHINE_MODE
; m
++)
1470 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1471 ira_reg_class_max_nregs
[cl
][m
]
1472 = ira_reg_class_min_nregs
[cl
][m
]
1473 = targetm
.class_max_nregs ((reg_class_t
) cl
, (machine_mode
) m
);
1474 for (cl
= 0; cl
< N_REG_CLASSES
; cl
++)
1476 (cl2
= alloc_reg_class_subclasses
[cl
][i
]) != LIM_REG_CLASSES
;
1478 if (ira_reg_class_min_nregs
[cl2
][m
]
1479 < ira_reg_class_min_nregs
[cl
][m
])
1480 ira_reg_class_min_nregs
[cl
][m
] = ira_reg_class_min_nregs
[cl2
][m
];
1486 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON.
1487 This function is called once IRA_CLASS_HARD_REGS has been initialized. */
1489 setup_prohibited_class_mode_regs (void)
1491 int j
, k
, hard_regno
, cl
, last_hard_regno
, count
;
1493 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1495 temp_hard_regset
= reg_class_contents
[cl
];
1496 AND_COMPL_HARD_REG_SET (temp_hard_regset
, no_unit_alloc_regs
);
1497 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1500 last_hard_regno
= -1;
1501 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs
[cl
][j
]);
1502 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1504 hard_regno
= ira_class_hard_regs
[cl
][k
];
1505 if (!targetm
.hard_regno_mode_ok (hard_regno
, (machine_mode
) j
))
1506 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1508 else if (in_hard_reg_set_p (temp_hard_regset
,
1509 (machine_mode
) j
, hard_regno
))
1511 last_hard_regno
= hard_regno
;
1515 ira_class_singleton
[cl
][j
] = (count
== 1 ? last_hard_regno
: -1);
1520 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers
1521 spanning from one register pressure class to another one. It is
1522 called after defining the pressure classes. */
1524 clarify_prohibited_class_mode_regs (void)
1526 int j
, k
, hard_regno
, cl
, pclass
, nregs
;
1528 for (cl
= (int) N_REG_CLASSES
- 1; cl
>= 0; cl
--)
1529 for (j
= 0; j
< NUM_MACHINE_MODES
; j
++)
1531 CLEAR_HARD_REG_SET (ira_useful_class_mode_regs
[cl
][j
]);
1532 for (k
= ira_class_hard_regs_num
[cl
] - 1; k
>= 0; k
--)
1534 hard_regno
= ira_class_hard_regs
[cl
][k
];
1535 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
], hard_regno
))
1537 nregs
= hard_regno_nregs (hard_regno
, (machine_mode
) j
);
1538 if (hard_regno
+ nregs
> FIRST_PSEUDO_REGISTER
)
1540 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1544 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
1545 for (nregs
-- ;nregs
>= 0; nregs
--)
1546 if (((enum reg_class
) pclass
1547 != ira_pressure_class_translate
[REGNO_REG_CLASS
1548 (hard_regno
+ nregs
)]))
1550 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1554 if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs
[cl
][j
],
1556 add_to_hard_reg_set (&ira_useful_class_mode_regs
[cl
][j
],
1557 (machine_mode
) j
, hard_regno
);
1562 /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST
1563 and IRA_MAY_MOVE_OUT_COST for MODE. */
1565 ira_init_register_move_cost (machine_mode mode
)
1567 static unsigned short last_move_cost
[N_REG_CLASSES
][N_REG_CLASSES
];
1568 bool all_match
= true;
1569 unsigned int i
, cl1
, cl2
;
1570 HARD_REG_SET ok_regs
;
1572 ira_assert (ira_register_move_cost
[mode
] == NULL
1573 && ira_may_move_in_cost
[mode
] == NULL
1574 && ira_may_move_out_cost
[mode
] == NULL
);
1575 CLEAR_HARD_REG_SET (ok_regs
);
1576 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1577 if (targetm
.hard_regno_mode_ok (i
, mode
))
1578 SET_HARD_REG_BIT (ok_regs
, i
);
1580 /* Note that we might be asked about the move costs of modes that
1581 cannot be stored in any hard register, for example if an inline
1582 asm tries to create a register operand with an impossible mode.
1583 We therefore can't assert have_regs_of_mode[mode] here. */
1584 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1585 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1588 if (!hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[cl1
])
1589 || !hard_reg_set_intersect_p (ok_regs
, reg_class_contents
[cl2
]))
1591 if ((ira_reg_class_max_nregs
[cl1
][mode
]
1592 > ira_class_hard_regs_num
[cl1
])
1593 || (ira_reg_class_max_nregs
[cl2
][mode
]
1594 > ira_class_hard_regs_num
[cl2
]))
1597 cost
= (ira_memory_move_cost
[mode
][cl1
][0]
1598 + ira_memory_move_cost
[mode
][cl2
][1]) * 2;
1602 cost
= register_move_cost (mode
, (enum reg_class
) cl1
,
1603 (enum reg_class
) cl2
);
1604 ira_assert (cost
< 65535);
1606 all_match
&= (last_move_cost
[cl1
][cl2
] == cost
);
1607 last_move_cost
[cl1
][cl2
] = cost
;
1609 if (all_match
&& last_mode_for_init_move_cost
!= -1)
1611 ira_register_move_cost
[mode
]
1612 = ira_register_move_cost
[last_mode_for_init_move_cost
];
1613 ira_may_move_in_cost
[mode
]
1614 = ira_may_move_in_cost
[last_mode_for_init_move_cost
];
1615 ira_may_move_out_cost
[mode
]
1616 = ira_may_move_out_cost
[last_mode_for_init_move_cost
];
1619 last_mode_for_init_move_cost
= mode
;
1620 ira_register_move_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1621 ira_may_move_in_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1622 ira_may_move_out_cost
[mode
] = XNEWVEC (move_table
, N_REG_CLASSES
);
1623 for (cl1
= 0; cl1
< N_REG_CLASSES
; cl1
++)
1624 for (cl2
= 0; cl2
< N_REG_CLASSES
; cl2
++)
1627 enum reg_class
*p1
, *p2
;
1629 if (last_move_cost
[cl1
][cl2
] == 65535)
1631 ira_register_move_cost
[mode
][cl1
][cl2
] = 65535;
1632 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 65535;
1633 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 65535;
1637 cost
= last_move_cost
[cl1
][cl2
];
1639 for (p2
= ®_class_subclasses
[cl2
][0];
1640 *p2
!= LIM_REG_CLASSES
; p2
++)
1641 if (ira_class_hard_regs_num
[*p2
] > 0
1642 && (ira_reg_class_max_nregs
[*p2
][mode
]
1643 <= ira_class_hard_regs_num
[*p2
]))
1644 cost
= MAX (cost
, ira_register_move_cost
[mode
][cl1
][*p2
]);
1646 for (p1
= ®_class_subclasses
[cl1
][0];
1647 *p1
!= LIM_REG_CLASSES
; p1
++)
1648 if (ira_class_hard_regs_num
[*p1
] > 0
1649 && (ira_reg_class_max_nregs
[*p1
][mode
]
1650 <= ira_class_hard_regs_num
[*p1
]))
1651 cost
= MAX (cost
, ira_register_move_cost
[mode
][*p1
][cl2
]);
1653 ira_assert (cost
<= 65535);
1654 ira_register_move_cost
[mode
][cl1
][cl2
] = cost
;
1656 if (ira_class_subset_p
[cl1
][cl2
])
1657 ira_may_move_in_cost
[mode
][cl1
][cl2
] = 0;
1659 ira_may_move_in_cost
[mode
][cl1
][cl2
] = cost
;
1661 if (ira_class_subset_p
[cl2
][cl1
])
1662 ira_may_move_out_cost
[mode
][cl1
][cl2
] = 0;
1664 ira_may_move_out_cost
[mode
][cl1
][cl2
] = cost
;
1671 /* This is called once during compiler work. It sets up
1672 different arrays whose values don't depend on the compiled
1675 ira_init_once (void)
1677 ira_init_costs_once ();
1680 ira_use_lra_p
= targetm
.lra_p ();
1683 /* Free ira_max_register_move_cost, ira_may_move_in_cost and
1684 ira_may_move_out_cost for each mode. */
1686 target_ira_int::free_register_move_costs (void)
1690 /* Reset move_cost and friends, making sure we only free shared
1691 table entries once. */
1692 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
1693 if (x_ira_register_move_cost
[mode
])
1696 i
< mode
&& (x_ira_register_move_cost
[i
]
1697 != x_ira_register_move_cost
[mode
]);
1702 free (x_ira_register_move_cost
[mode
]);
1703 free (x_ira_may_move_in_cost
[mode
]);
1704 free (x_ira_may_move_out_cost
[mode
]);
1707 memset (x_ira_register_move_cost
, 0, sizeof x_ira_register_move_cost
);
1708 memset (x_ira_may_move_in_cost
, 0, sizeof x_ira_may_move_in_cost
);
1709 memset (x_ira_may_move_out_cost
, 0, sizeof x_ira_may_move_out_cost
);
1710 last_mode_for_init_move_cost
= -1;
1713 target_ira_int::~target_ira_int ()
1716 free_register_move_costs ();
1719 /* This is called every time when register related information is
1724 this_target_ira_int
->free_register_move_costs ();
1725 setup_reg_mode_hard_regset ();
1726 setup_alloc_regs (flag_omit_frame_pointer
!= 0);
1727 setup_class_subset_and_memory_move_costs ();
1728 setup_reg_class_nregs ();
1729 setup_prohibited_class_mode_regs ();
1730 find_reg_classes ();
1731 clarify_prohibited_class_mode_regs ();
1732 setup_hard_regno_aclass ();
1737 #define ira_prohibited_mode_move_regs_initialized_p \
1738 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p)
1740 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */
1742 setup_prohibited_mode_move_regs (void)
1745 rtx test_reg1
, test_reg2
, move_pat
;
1746 rtx_insn
*move_insn
;
1748 if (ira_prohibited_mode_move_regs_initialized_p
)
1750 ira_prohibited_mode_move_regs_initialized_p
= true;
1751 test_reg1
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
1752 test_reg2
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 2);
1753 move_pat
= gen_rtx_SET (test_reg1
, test_reg2
);
1754 move_insn
= gen_rtx_INSN (VOIDmode
, 0, 0, 0, move_pat
, 0, -1, 0);
1755 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
1757 SET_HARD_REG_SET (ira_prohibited_mode_move_regs
[i
]);
1758 for (j
= 0; j
< FIRST_PSEUDO_REGISTER
; j
++)
1760 if (!targetm
.hard_regno_mode_ok (j
, (machine_mode
) i
))
1762 set_mode_and_regno (test_reg1
, (machine_mode
) i
, j
);
1763 set_mode_and_regno (test_reg2
, (machine_mode
) i
, j
);
1764 INSN_CODE (move_insn
) = -1;
1765 recog_memoized (move_insn
);
1766 if (INSN_CODE (move_insn
) < 0)
1768 extract_insn (move_insn
);
1769 /* We don't know whether the move will be in code that is optimized
1770 for size or speed, so consider all enabled alternatives. */
1771 if (! constrain_operands (1, get_enabled_alternatives (move_insn
)))
1773 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs
[i
], j
);
1780 /* Extract INSN and return the set of alternatives that we should consider.
1781 This excludes any alternatives whose constraints are obviously impossible
1782 to meet (e.g. because the constraint requires a constant and the operand
1783 is nonconstant). It also excludes alternatives that are bound to need
1784 a spill or reload, as long as we have other alternatives that match
1787 ira_setup_alts (rtx_insn
*insn
)
1792 int commutative
= -1;
1794 extract_insn (insn
);
1795 preprocess_constraints (insn
);
1796 alternative_mask preferred
= get_preferred_alternatives (insn
);
1797 alternative_mask alts
= 0;
1798 alternative_mask exact_alts
= 0;
1799 /* Check that the hard reg set is enough for holding all
1800 alternatives. It is hard to imagine the situation when the
1801 assertion is wrong. */
1802 ira_assert (recog_data
.n_alternatives
1803 <= (int) MAX (sizeof (HARD_REG_ELT_TYPE
) * CHAR_BIT
,
1804 FIRST_PSEUDO_REGISTER
));
1805 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1806 if (recog_data
.constraints
[nop
][0] == '%')
1811 for (curr_swapped
= false;; curr_swapped
= true)
1813 for (nalt
= 0; nalt
< recog_data
.n_alternatives
; nalt
++)
1815 if (!TEST_BIT (preferred
, nalt
) || TEST_BIT (exact_alts
, nalt
))
1818 const operand_alternative
*op_alt
1819 = &recog_op_alt
[nalt
* recog_data
.n_operands
];
1820 int this_reject
= 0;
1821 for (nop
= 0; nop
< recog_data
.n_operands
; nop
++)
1825 this_reject
+= op_alt
[nop
].reject
;
1827 rtx op
= recog_data
.operand
[nop
];
1828 p
= op_alt
[nop
].constraint
;
1829 if (*p
== 0 || *p
== ',')
1834 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
1845 /* The commutative modifier is handled above. */
1848 case '0': case '1': case '2': case '3': case '4':
1849 case '5': case '6': case '7': case '8': case '9':
1851 rtx other
= recog_data
.operand
[c
- '0'];
1853 ? rtx_equal_p (other
, op
)
1854 : REG_P (op
) || SUBREG_P (op
))
1866 enum constraint_num cn
= lookup_constraint (p
);
1867 switch (get_constraint_type (cn
))
1870 if (reg_class_for_constraint (cn
) != NO_REGS
)
1872 if (REG_P (op
) || SUBREG_P (op
))
1879 if (CONST_INT_P (op
)
1880 && (insn_const_int_ok_for_constraint
1889 case CT_SPECIAL_MEMORY
:
1896 if (constraint_satisfied_p (op
, cn
))
1903 while (p
+= len
, c
);
1906 /* We can make the alternative match by spilling a register
1907 to memory or loading something into a register. Count a
1908 cost of one reload (the equivalent of the '?' constraint). */
1914 if (nop
>= recog_data
.n_operands
)
1916 alts
|= ALTERNATIVE_BIT (nalt
);
1917 if (this_reject
== 0)
1918 exact_alts
|= ALTERNATIVE_BIT (nalt
);
1921 if (commutative
< 0)
1923 /* Swap forth and back to avoid changing recog_data. */
1924 std::swap (recog_data
.operand
[commutative
],
1925 recog_data
.operand
[commutative
+ 1]);
1929 return exact_alts
? exact_alts
: alts
;
1932 /* Return the number of the output non-early clobber operand which
1933 should be the same in any case as operand with number OP_NUM (or
1934 negative value if there is no such operand). ALTS is the mask
1935 of alternatives that we should consider. */
1937 ira_get_dup_out_num (int op_num
, alternative_mask alts
)
1939 int curr_alt
, c
, original
, dup
;
1940 bool ignore_p
, use_commut_op_p
;
1943 if (op_num
< 0 || recog_data
.n_alternatives
== 0)
1945 /* We should find duplications only for input operands. */
1946 if (recog_data
.operand_type
[op_num
] != OP_IN
)
1948 str
= recog_data
.constraints
[op_num
];
1949 use_commut_op_p
= false;
1952 rtx op
= recog_data
.operand
[op_num
];
1954 for (curr_alt
= 0, ignore_p
= !TEST_BIT (alts
, curr_alt
),
1965 ignore_p
= !TEST_BIT (alts
, curr_alt
);
1967 else if (! ignore_p
)
1974 enum constraint_num cn
= lookup_constraint (str
);
1975 enum reg_class cl
= reg_class_for_constraint (cn
);
1977 && !targetm
.class_likely_spilled_p (cl
))
1979 if (constraint_satisfied_p (op
, cn
))
1984 case '0': case '1': case '2': case '3': case '4':
1985 case '5': case '6': case '7': case '8': case '9':
1986 if (original
!= -1 && original
!= c
)
1991 str
+= CONSTRAINT_LEN (c
, str
);
1995 dup
= original
- '0';
1996 if (recog_data
.operand_type
[dup
] == OP_OUT
)
1999 if (use_commut_op_p
)
2001 use_commut_op_p
= true;
2002 if (recog_data
.constraints
[op_num
][0] == '%')
2003 str
= recog_data
.constraints
[op_num
+ 1];
2004 else if (op_num
> 0 && recog_data
.constraints
[op_num
- 1][0] == '%')
2005 str
= recog_data
.constraints
[op_num
- 1];
2014 /* Search forward to see if the source register of a copy insn dies
2015 before either it or the destination register is modified, but don't
2016 scan past the end of the basic block. If so, we can replace the
2017 source with the destination and let the source die in the copy
2020 This will reduce the number of registers live in that range and may
2021 enable the destination and the source coalescing, thus often saving
2022 one register in addition to a register-register copy. */
2025 decrease_live_ranges_number (void)
2029 rtx set
, src
, dest
, dest_death
, note
;
2033 if (! flag_expensive_optimizations
)
2037 fprintf (ira_dump_file
, "Starting decreasing number of live ranges...\n");
2039 FOR_EACH_BB_FN (bb
, cfun
)
2040 FOR_BB_INSNS (bb
, insn
)
2042 set
= single_set (insn
);
2045 src
= SET_SRC (set
);
2046 dest
= SET_DEST (set
);
2047 if (! REG_P (src
) || ! REG_P (dest
)
2048 || find_reg_note (insn
, REG_DEAD
, src
))
2050 sregno
= REGNO (src
);
2051 dregno
= REGNO (dest
);
2053 /* We don't want to mess with hard regs if register classes
2055 if (sregno
== dregno
2056 || (targetm
.small_register_classes_for_mode_p (GET_MODE (src
))
2057 && (sregno
< FIRST_PSEUDO_REGISTER
2058 || dregno
< FIRST_PSEUDO_REGISTER
))
2059 /* We don't see all updates to SP if they are in an
2060 auto-inc memory reference, so we must disallow this
2061 optimization on them. */
2062 || sregno
== STACK_POINTER_REGNUM
2063 || dregno
== STACK_POINTER_REGNUM
)
2066 dest_death
= NULL_RTX
;
2068 for (p
= NEXT_INSN (insn
); p
; p
= NEXT_INSN (p
))
2072 if (BLOCK_FOR_INSN (p
) != bb
)
2075 if (reg_set_p (src
, p
) || reg_set_p (dest
, p
)
2076 /* If SRC is an asm-declared register, it must not be
2077 replaced in any asm. Unfortunately, the REG_EXPR
2078 tree for the asm variable may be absent in the SRC
2079 rtx, so we can't check the actual register
2080 declaration easily (the asm operand will have it,
2081 though). To avoid complicating the test for a rare
2082 case, we just don't perform register replacement
2083 for a hard reg mentioned in an asm. */
2084 || (sregno
< FIRST_PSEUDO_REGISTER
2085 && asm_noperands (PATTERN (p
)) >= 0
2086 && reg_overlap_mentioned_p (src
, PATTERN (p
)))
2087 /* Don't change hard registers used by a call. */
2088 || (CALL_P (p
) && sregno
< FIRST_PSEUDO_REGISTER
2089 && find_reg_fusage (p
, USE
, src
))
2090 /* Don't change a USE of a register. */
2091 || (GET_CODE (PATTERN (p
)) == USE
2092 && reg_overlap_mentioned_p (src
, XEXP (PATTERN (p
), 0))))
2095 /* See if all of SRC dies in P. This test is slightly
2096 more conservative than it needs to be. */
2097 if ((note
= find_regno_note (p
, REG_DEAD
, sregno
))
2098 && GET_MODE (XEXP (note
, 0)) == GET_MODE (src
))
2102 /* We can do the optimization. Scan forward from INSN
2103 again, replacing regs as we go. Set FAILED if a
2104 replacement can't be done. In that case, we can't
2105 move the death note for SRC. This should be
2108 /* Set to stop at next insn. */
2109 for (q
= next_real_insn (insn
);
2110 q
!= next_real_insn (p
);
2111 q
= next_real_insn (q
))
2113 if (reg_overlap_mentioned_p (src
, PATTERN (q
)))
2115 /* If SRC is a hard register, we might miss
2116 some overlapping registers with
2117 validate_replace_rtx, so we would have to
2118 undo it. We can't if DEST is present in
2119 the insn, so fail in that combination of
2121 if (sregno
< FIRST_PSEUDO_REGISTER
2122 && reg_mentioned_p (dest
, PATTERN (q
)))
2125 /* Attempt to replace all uses. */
2126 else if (!validate_replace_rtx (src
, dest
, q
))
2129 /* If this succeeded, but some part of the
2130 register is still present, undo the
2132 else if (sregno
< FIRST_PSEUDO_REGISTER
2133 && reg_overlap_mentioned_p (src
, PATTERN (q
)))
2135 validate_replace_rtx (dest
, src
, q
);
2140 /* If DEST dies here, remove the death note and
2141 save it for later. Make sure ALL of DEST dies
2142 here; again, this is overly conservative. */
2144 && (dest_death
= find_regno_note (q
, REG_DEAD
, dregno
)))
2146 if (GET_MODE (XEXP (dest_death
, 0)) == GET_MODE (dest
))
2147 remove_note (q
, dest_death
);
2158 /* Move death note of SRC from P to INSN. */
2159 remove_note (p
, note
);
2160 XEXP (note
, 1) = REG_NOTES (insn
);
2161 REG_NOTES (insn
) = note
;
2164 /* DEST is also dead if INSN has a REG_UNUSED note for
2168 = find_regno_note (insn
, REG_UNUSED
, dregno
)))
2170 PUT_REG_NOTE_KIND (dest_death
, REG_DEAD
);
2171 remove_note (insn
, dest_death
);
2174 /* Put death note of DEST on P if we saw it die. */
2177 XEXP (dest_death
, 1) = REG_NOTES (p
);
2178 REG_NOTES (p
) = dest_death
;
2183 /* If SRC is a hard register which is set or killed in
2184 some other way, we can't do this optimization. */
2185 else if (sregno
< FIRST_PSEUDO_REGISTER
&& dead_or_set_p (p
, src
))
2193 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */
2195 ira_bad_reload_regno_1 (int regno
, rtx x
)
2199 enum reg_class pref
;
2201 /* We only deal with pseudo regs. */
2202 if (! x
|| GET_CODE (x
) != REG
)
2205 x_regno
= REGNO (x
);
2206 if (x_regno
< FIRST_PSEUDO_REGISTER
)
2209 /* If the pseudo prefers REGNO explicitly, then do not consider
2210 REGNO a bad spill choice. */
2211 pref
= reg_preferred_class (x_regno
);
2212 if (reg_class_size
[pref
] == 1)
2213 return !TEST_HARD_REG_BIT (reg_class_contents
[pref
], regno
);
2215 /* If the pseudo conflicts with REGNO, then we consider REGNO a
2216 poor choice for a reload regno. */
2217 a
= ira_regno_allocno_map
[x_regno
];
2218 n
= ALLOCNO_NUM_OBJECTS (a
);
2219 for (i
= 0; i
< n
; i
++)
2221 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2222 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
), regno
))
2228 /* Return nonzero if REGNO is a particularly bad choice for reloading
2231 ira_bad_reload_regno (int regno
, rtx in
, rtx out
)
2233 return (ira_bad_reload_regno_1 (regno
, in
)
2234 || ira_bad_reload_regno_1 (regno
, out
));
2237 /* Add register clobbers from asm statements. */
2239 compute_regs_asm_clobbered (void)
2243 FOR_EACH_BB_FN (bb
, cfun
)
2246 FOR_BB_INSNS_REVERSE (bb
, insn
)
2250 if (NONDEBUG_INSN_P (insn
) && asm_noperands (PATTERN (insn
)) >= 0)
2251 FOR_EACH_INSN_DEF (def
, insn
)
2253 unsigned int dregno
= DF_REF_REGNO (def
);
2254 if (HARD_REGISTER_NUM_P (dregno
))
2255 add_to_hard_reg_set (&crtl
->asm_clobbers
,
2256 GET_MODE (DF_REF_REAL_REG (def
)),
2264 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and
2267 ira_setup_eliminable_regset (void)
2270 static const struct {const int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2272 /* Setup is_leaf as frame_pointer_required may use it. This function
2273 is called by sched_init before ira if scheduling is enabled. */
2274 crtl
->is_leaf
= leaf_function_p ();
2276 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore
2277 sp for alloca. So we can't eliminate the frame pointer in that
2278 case. At some point, we should improve this by emitting the
2279 sp-adjusting insns for this case. */
2280 frame_pointer_needed
2281 = (! flag_omit_frame_pointer
2282 || (cfun
->calls_alloca
&& EXIT_IGNORE_STACK
)
2283 /* We need the frame pointer to catch stack overflow exceptions if
2284 the stack pointer is moving (as for the alloca case just above). */
2285 || (STACK_CHECK_MOVING_SP
2288 && cfun
->can_throw_non_call_exceptions
)
2289 || crtl
->accesses_prior_frames
2290 || (SUPPORTS_STACK_ALIGNMENT
&& crtl
->stack_realign_needed
)
2291 || targetm
.frame_pointer_required ());
2293 /* The chance that FRAME_POINTER_NEEDED is changed from inspecting
2294 RTL is very small. So if we use frame pointer for RA and RTL
2295 actually prevents this, we will spill pseudos assigned to the
2296 frame pointer in LRA. */
2298 if (frame_pointer_needed
)
2299 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2301 ira_no_alloc_regs
= no_unit_alloc_regs
;
2302 CLEAR_HARD_REG_SET (eliminable_regset
);
2304 compute_regs_asm_clobbered ();
2306 /* Build the regset of all eliminable registers and show we can't
2307 use those that we already know won't be eliminated. */
2308 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2311 = (! targetm
.can_eliminate (eliminables
[i
].from
, eliminables
[i
].to
)
2312 || (eliminables
[i
].to
== STACK_POINTER_REGNUM
&& frame_pointer_needed
));
2314 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, eliminables
[i
].from
))
2316 SET_HARD_REG_BIT (eliminable_regset
, eliminables
[i
].from
);
2319 SET_HARD_REG_BIT (ira_no_alloc_regs
, eliminables
[i
].from
);
2321 else if (cannot_elim
)
2322 error ("%s cannot be used in %<asm%> here",
2323 reg_names
[eliminables
[i
].from
]);
2325 df_set_regs_ever_live (eliminables
[i
].from
, true);
2327 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
)
2329 if (!TEST_HARD_REG_BIT (crtl
->asm_clobbers
, HARD_FRAME_POINTER_REGNUM
))
2331 SET_HARD_REG_BIT (eliminable_regset
, HARD_FRAME_POINTER_REGNUM
);
2332 if (frame_pointer_needed
)
2333 SET_HARD_REG_BIT (ira_no_alloc_regs
, HARD_FRAME_POINTER_REGNUM
);
2335 else if (frame_pointer_needed
)
2336 error ("%s cannot be used in %<asm%> here",
2337 reg_names
[HARD_FRAME_POINTER_REGNUM
]);
2339 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM
, true);
2345 /* Vector of substitutions of register numbers,
2346 used to map pseudo regs into hardware regs.
2347 This is set up as a result of register allocation.
2348 Element N is the hard reg assigned to pseudo reg N,
2349 or is -1 if no hard reg was assigned.
2350 If N is a hard reg number, element N is N. */
2351 short *reg_renumber
;
2353 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from
2354 the allocation found by IRA. */
2356 setup_reg_renumber (void)
2358 int regno
, hard_regno
;
2360 ira_allocno_iterator ai
;
2362 caller_save_needed
= 0;
2363 FOR_EACH_ALLOCNO (a
, ai
)
2365 if (ira_use_lra_p
&& ALLOCNO_CAP_MEMBER (a
) != NULL
)
2367 /* There are no caps at this point. */
2368 ira_assert (ALLOCNO_CAP_MEMBER (a
) == NULL
);
2369 if (! ALLOCNO_ASSIGNED_P (a
))
2370 /* It can happen if A is not referenced but partially anticipated
2371 somewhere in a region. */
2372 ALLOCNO_ASSIGNED_P (a
) = true;
2373 ira_free_allocno_updated_costs (a
);
2374 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2375 regno
= ALLOCNO_REGNO (a
);
2376 reg_renumber
[regno
] = (hard_regno
< 0 ? -1 : hard_regno
);
2377 if (hard_regno
>= 0)
2380 enum reg_class pclass
;
2383 pclass
= ira_pressure_class_translate
[REGNO_REG_CLASS (hard_regno
)];
2384 nwords
= ALLOCNO_NUM_OBJECTS (a
);
2385 for (i
= 0; i
< nwords
; i
++)
2387 obj
= ALLOCNO_OBJECT (a
, i
);
2388 IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj
),
2389 reg_class_contents
[pclass
]);
2391 if (ALLOCNO_CALLS_CROSSED_NUM (a
) != 0
2392 && ira_hard_reg_set_intersection_p (hard_regno
, ALLOCNO_MODE (a
),
2395 ira_assert (!optimize
|| flag_caller_saves
2396 || (ALLOCNO_CALLS_CROSSED_NUM (a
)
2397 == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a
))
2398 || regno
>= ira_reg_equiv_len
2399 || ira_equiv_no_lvalue_p (regno
));
2400 caller_save_needed
= 1;
2406 /* Set up allocno assignment flags for further allocation
2409 setup_allocno_assignment_flags (void)
2413 ira_allocno_iterator ai
;
2415 FOR_EACH_ALLOCNO (a
, ai
)
2417 if (! ALLOCNO_ASSIGNED_P (a
))
2418 /* It can happen if A is not referenced but partially anticipated
2419 somewhere in a region. */
2420 ira_free_allocno_updated_costs (a
);
2421 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2422 /* Don't assign hard registers to allocnos which are destination
2423 of removed store at the end of loop. It has no sense to keep
2424 the same value in different hard registers. It is also
2425 impossible to assign hard registers correctly to such
2426 allocnos because the cost info and info about intersected
2427 calls are incorrect for them. */
2428 ALLOCNO_ASSIGNED_P (a
) = (hard_regno
>= 0
2429 || ALLOCNO_EMIT_DATA (a
)->mem_optimized_dest_p
2430 || (ALLOCNO_MEMORY_COST (a
)
2431 - ALLOCNO_CLASS_COST (a
)) < 0);
2434 || ira_hard_reg_in_set_p (hard_regno
, ALLOCNO_MODE (a
),
2435 reg_class_contents
[ALLOCNO_CLASS (a
)]));
2439 /* Evaluate overall allocation cost and the costs for using hard
2440 registers and memory for allocnos. */
2442 calculate_allocation_cost (void)
2444 int hard_regno
, cost
;
2446 ira_allocno_iterator ai
;
2448 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
2449 FOR_EACH_ALLOCNO (a
, ai
)
2451 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2452 ira_assert (hard_regno
< 0
2453 || (ira_hard_reg_in_set_p
2454 (hard_regno
, ALLOCNO_MODE (a
),
2455 reg_class_contents
[ALLOCNO_CLASS (a
)])));
2458 cost
= ALLOCNO_MEMORY_COST (a
);
2459 ira_mem_cost
+= cost
;
2461 else if (ALLOCNO_HARD_REG_COSTS (a
) != NULL
)
2463 cost
= (ALLOCNO_HARD_REG_COSTS (a
)
2464 [ira_class_hard_reg_index
2465 [ALLOCNO_CLASS (a
)][hard_regno
]]);
2466 ira_reg_cost
+= cost
;
2470 cost
= ALLOCNO_CLASS_COST (a
);
2471 ira_reg_cost
+= cost
;
2473 ira_overall_cost
+= cost
;
2476 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
2478 fprintf (ira_dump_file
,
2479 "+++Costs: overall %" PRId64
2485 ira_overall_cost
, ira_reg_cost
, ira_mem_cost
,
2486 ira_load_cost
, ira_store_cost
, ira_shuffle_cost
);
2487 fprintf (ira_dump_file
, "\n+++ move loops %d, new jumps %d\n",
2488 ira_move_loops_num
, ira_additional_jumps_num
);
2493 #ifdef ENABLE_IRA_CHECKING
2494 /* Check the correctness of the allocation. We do need this because
2495 of complicated code to transform more one region internal
2496 representation into one region representation. */
2498 check_allocation (void)
2501 int hard_regno
, nregs
, conflict_nregs
;
2502 ira_allocno_iterator ai
;
2504 FOR_EACH_ALLOCNO (a
, ai
)
2506 int n
= ALLOCNO_NUM_OBJECTS (a
);
2509 if (ALLOCNO_CAP_MEMBER (a
) != NULL
2510 || (hard_regno
= ALLOCNO_HARD_REGNO (a
)) < 0)
2512 nregs
= hard_regno_nregs (hard_regno
, ALLOCNO_MODE (a
));
2514 /* We allocated a single hard register. */
2517 /* We allocated multiple hard registers, and we will test
2518 conflicts in a granularity of single hard regs. */
2521 for (i
= 0; i
< n
; i
++)
2523 ira_object_t obj
= ALLOCNO_OBJECT (a
, i
);
2524 ira_object_t conflict_obj
;
2525 ira_object_conflict_iterator oci
;
2526 int this_regno
= hard_regno
;
2529 if (REG_WORDS_BIG_ENDIAN
)
2530 this_regno
+= n
- i
- 1;
2534 FOR_EACH_OBJECT_CONFLICT (obj
, conflict_obj
, oci
)
2536 ira_allocno_t conflict_a
= OBJECT_ALLOCNO (conflict_obj
);
2537 int conflict_hard_regno
= ALLOCNO_HARD_REGNO (conflict_a
);
2538 if (conflict_hard_regno
< 0)
2541 conflict_nregs
= hard_regno_nregs (conflict_hard_regno
,
2542 ALLOCNO_MODE (conflict_a
));
2544 if (ALLOCNO_NUM_OBJECTS (conflict_a
) > 1
2545 && conflict_nregs
== ALLOCNO_NUM_OBJECTS (conflict_a
))
2547 if (REG_WORDS_BIG_ENDIAN
)
2548 conflict_hard_regno
+= (ALLOCNO_NUM_OBJECTS (conflict_a
)
2549 - OBJECT_SUBWORD (conflict_obj
) - 1);
2551 conflict_hard_regno
+= OBJECT_SUBWORD (conflict_obj
);
2555 if ((conflict_hard_regno
<= this_regno
2556 && this_regno
< conflict_hard_regno
+ conflict_nregs
)
2557 || (this_regno
<= conflict_hard_regno
2558 && conflict_hard_regno
< this_regno
+ nregs
))
2560 fprintf (stderr
, "bad allocation for %d and %d\n",
2561 ALLOCNO_REGNO (a
), ALLOCNO_REGNO (conflict_a
));
2570 /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should
2571 be already calculated. */
2573 setup_reg_equiv_init (void)
2576 int max_regno
= max_reg_num ();
2578 for (i
= 0; i
< max_regno
; i
++)
2579 reg_equiv_init (i
) = ira_reg_equiv
[i
].init_insns
;
2582 /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS
2583 are insns which were generated for such movement. It is assumed
2584 that FROM_REGNO and TO_REGNO always have the same value at the
2585 point of any move containing such registers. This function is used
2586 to update equiv info for register shuffles on the region borders
2587 and for caller save/restore insns. */
2589 ira_update_equiv_info_by_shuffle_insn (int to_regno
, int from_regno
, rtx_insn
*insns
)
2594 if (! ira_reg_equiv
[from_regno
].defined_p
2595 && (! ira_reg_equiv
[to_regno
].defined_p
2596 || ((x
= ira_reg_equiv
[to_regno
].memory
) != NULL_RTX
2597 && ! MEM_READONLY_P (x
))))
2600 if (NEXT_INSN (insn
) != NULL_RTX
)
2602 if (! ira_reg_equiv
[to_regno
].defined_p
)
2604 ira_assert (ira_reg_equiv
[to_regno
].init_insns
== NULL_RTX
);
2607 ira_reg_equiv
[to_regno
].defined_p
= false;
2608 ira_reg_equiv
[to_regno
].memory
2609 = ira_reg_equiv
[to_regno
].constant
2610 = ira_reg_equiv
[to_regno
].invariant
2611 = ira_reg_equiv
[to_regno
].init_insns
= NULL
;
2612 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2613 fprintf (ira_dump_file
,
2614 " Invalidating equiv info for reg %d\n", to_regno
);
2617 /* It is possible that FROM_REGNO still has no equivalence because
2618 in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd
2619 insn was not processed yet. */
2620 if (ira_reg_equiv
[from_regno
].defined_p
)
2622 ira_reg_equiv
[to_regno
].defined_p
= true;
2623 if ((x
= ira_reg_equiv
[from_regno
].memory
) != NULL_RTX
)
2625 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
2626 && ira_reg_equiv
[from_regno
].constant
== NULL_RTX
);
2627 ira_assert (ira_reg_equiv
[to_regno
].memory
== NULL_RTX
2628 || rtx_equal_p (ira_reg_equiv
[to_regno
].memory
, x
));
2629 ira_reg_equiv
[to_regno
].memory
= x
;
2630 if (! MEM_READONLY_P (x
))
2631 /* We don't add the insn to insn init list because memory
2632 equivalence is just to say what memory is better to use
2633 when the pseudo is spilled. */
2636 else if ((x
= ira_reg_equiv
[from_regno
].constant
) != NULL_RTX
)
2638 ira_assert (ira_reg_equiv
[from_regno
].invariant
== NULL_RTX
);
2639 ira_assert (ira_reg_equiv
[to_regno
].constant
== NULL_RTX
2640 || rtx_equal_p (ira_reg_equiv
[to_regno
].constant
, x
));
2641 ira_reg_equiv
[to_regno
].constant
= x
;
2645 x
= ira_reg_equiv
[from_regno
].invariant
;
2646 ira_assert (x
!= NULL_RTX
);
2647 ira_assert (ira_reg_equiv
[to_regno
].invariant
== NULL_RTX
2648 || rtx_equal_p (ira_reg_equiv
[to_regno
].invariant
, x
));
2649 ira_reg_equiv
[to_regno
].invariant
= x
;
2651 if (find_reg_note (insn
, REG_EQUIV
, x
) == NULL_RTX
)
2653 note
= set_unique_reg_note (insn
, REG_EQUIV
, copy_rtx (x
));
2654 gcc_assert (note
!= NULL_RTX
);
2655 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2657 fprintf (ira_dump_file
,
2658 " Adding equiv note to insn %u for reg %d ",
2659 INSN_UID (insn
), to_regno
);
2660 dump_value_slim (ira_dump_file
, x
, 1);
2661 fprintf (ira_dump_file
, "\n");
2665 ira_reg_equiv
[to_regno
].init_insns
2666 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
2667 ira_reg_equiv
[to_regno
].init_insns
);
2668 if (internal_flag_ira_verbose
> 3 && ira_dump_file
!= NULL
)
2669 fprintf (ira_dump_file
,
2670 " Adding equiv init move insn %u to reg %d\n",
2671 INSN_UID (insn
), to_regno
);
2674 /* Fix values of array REG_EQUIV_INIT after live range splitting done
2677 fix_reg_equiv_init (void)
2679 int max_regno
= max_reg_num ();
2680 int i
, new_regno
, max
;
2682 rtx_insn_list
*x
, *next
, *prev
;
2685 if (max_regno_before_ira
< max_regno
)
2687 max
= vec_safe_length (reg_equivs
);
2689 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; i
++)
2690 for (prev
= NULL
, x
= reg_equiv_init (i
);
2696 set
= single_set (insn
);
2697 ira_assert (set
!= NULL_RTX
2698 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))));
2699 if (REG_P (SET_DEST (set
))
2700 && ((int) REGNO (SET_DEST (set
)) == i
2701 || (int) ORIGINAL_REGNO (SET_DEST (set
)) == i
))
2702 new_regno
= REGNO (SET_DEST (set
));
2703 else if (REG_P (SET_SRC (set
))
2704 && ((int) REGNO (SET_SRC (set
)) == i
2705 || (int) ORIGINAL_REGNO (SET_SRC (set
)) == i
))
2706 new_regno
= REGNO (SET_SRC (set
));
2713 /* Remove the wrong list element. */
2714 if (prev
== NULL_RTX
)
2715 reg_equiv_init (i
) = next
;
2717 XEXP (prev
, 1) = next
;
2718 XEXP (x
, 1) = reg_equiv_init (new_regno
);
2719 reg_equiv_init (new_regno
) = x
;
2725 #ifdef ENABLE_IRA_CHECKING
2726 /* Print redundant memory-memory copies. */
2728 print_redundant_copies (void)
2732 ira_copy_t cp
, next_cp
;
2733 ira_allocno_iterator ai
;
2735 FOR_EACH_ALLOCNO (a
, ai
)
2737 if (ALLOCNO_CAP_MEMBER (a
) != NULL
)
2740 hard_regno
= ALLOCNO_HARD_REGNO (a
);
2741 if (hard_regno
>= 0)
2743 for (cp
= ALLOCNO_COPIES (a
); cp
!= NULL
; cp
= next_cp
)
2745 next_cp
= cp
->next_first_allocno_copy
;
2748 next_cp
= cp
->next_second_allocno_copy
;
2749 if (internal_flag_ira_verbose
> 4 && ira_dump_file
!= NULL
2750 && cp
->insn
!= NULL_RTX
2751 && ALLOCNO_HARD_REGNO (cp
->first
) == hard_regno
)
2752 fprintf (ira_dump_file
,
2753 " Redundant move from %d(freq %d):%d\n",
2754 INSN_UID (cp
->insn
), cp
->freq
, hard_regno
);
2760 /* Setup preferred and alternative classes for new pseudo-registers
2761 created by IRA starting with START. */
2763 setup_preferred_alternate_classes_for_new_pseudos (int start
)
2766 int max_regno
= max_reg_num ();
2768 for (i
= start
; i
< max_regno
; i
++)
2770 old_regno
= ORIGINAL_REGNO (regno_reg_rtx
[i
]);
2771 ira_assert (i
!= old_regno
);
2772 setup_reg_classes (i
, reg_preferred_class (old_regno
),
2773 reg_alternate_class (old_regno
),
2774 reg_allocno_class (old_regno
));
2775 if (internal_flag_ira_verbose
> 2 && ira_dump_file
!= NULL
)
2776 fprintf (ira_dump_file
,
2777 " New r%d: setting preferred %s, alternative %s\n",
2778 i
, reg_class_names
[reg_preferred_class (old_regno
)],
2779 reg_class_names
[reg_alternate_class (old_regno
)]);
2784 /* The number of entries allocated in reg_info. */
2785 static int allocated_reg_info_size
;
2787 /* Regional allocation can create new pseudo-registers. This function
2788 expands some arrays for pseudo-registers. */
2790 expand_reg_info (void)
2793 int size
= max_reg_num ();
2796 for (i
= allocated_reg_info_size
; i
< size
; i
++)
2797 setup_reg_classes (i
, GENERAL_REGS
, ALL_REGS
, GENERAL_REGS
);
2798 setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size
);
2799 allocated_reg_info_size
= size
;
2802 /* Return TRUE if there is too high register pressure in the function.
2803 It is used to decide when stack slot sharing is worth to do. */
2805 too_high_register_pressure_p (void)
2808 enum reg_class pclass
;
2810 for (i
= 0; i
< ira_pressure_classes_num
; i
++)
2812 pclass
= ira_pressure_classes
[i
];
2813 if (ira_loop_tree_root
->reg_pressure
[pclass
] > 10000)
2821 /* Indicate that hard register number FROM was eliminated and replaced with
2822 an offset from hard register number TO. The status of hard registers live
2823 at the start of a basic block is updated by replacing a use of FROM with
2827 mark_elimination (int from
, int to
)
2832 FOR_EACH_BB_FN (bb
, cfun
)
2835 if (bitmap_bit_p (r
, from
))
2837 bitmap_clear_bit (r
, from
);
2838 bitmap_set_bit (r
, to
);
2842 r
= DF_LIVE_IN (bb
);
2843 if (bitmap_bit_p (r
, from
))
2845 bitmap_clear_bit (r
, from
);
2846 bitmap_set_bit (r
, to
);
2853 /* The length of the following array. */
2854 int ira_reg_equiv_len
;
2856 /* Info about equiv. info for each register. */
2857 struct ira_reg_equiv_s
*ira_reg_equiv
;
2859 /* Expand ira_reg_equiv if necessary. */
2861 ira_expand_reg_equiv (void)
2863 int old
= ira_reg_equiv_len
;
2865 if (ira_reg_equiv_len
> max_reg_num ())
2867 ira_reg_equiv_len
= max_reg_num () * 3 / 2 + 1;
2869 = (struct ira_reg_equiv_s
*) xrealloc (ira_reg_equiv
,
2871 * sizeof (struct ira_reg_equiv_s
));
2872 gcc_assert (old
< ira_reg_equiv_len
);
2873 memset (ira_reg_equiv
+ old
, 0,
2874 sizeof (struct ira_reg_equiv_s
) * (ira_reg_equiv_len
- old
));
2878 init_reg_equiv (void)
2880 ira_reg_equiv_len
= 0;
2881 ira_reg_equiv
= NULL
;
2882 ira_expand_reg_equiv ();
2886 finish_reg_equiv (void)
2888 free (ira_reg_equiv
);
2895 /* Set when a REG_EQUIV note is found or created. Use to
2896 keep track of what memory accesses might be created later,
2901 /* The list of each instruction which initializes this register.
2903 NULL indicates we know nothing about this register's equivalence
2906 An INSN_LIST with a NULL insn indicates this pseudo is already
2907 known to not have a valid equivalence. */
2908 rtx_insn_list
*init_insns
;
2910 /* Loop depth is used to recognize equivalences which appear
2911 to be present within the same loop (or in an inner loop). */
2913 /* Nonzero if this had a preexisting REG_EQUIV note. */
2914 unsigned char is_arg_equivalence
: 1;
2915 /* Set when an attempt should be made to replace a register
2916 with the associated src_p entry. */
2917 unsigned char replace
: 1;
2918 /* Set if this register has no known equivalence. */
2919 unsigned char no_equiv
: 1;
2920 /* Set if this register is mentioned in a paradoxical subreg. */
2921 unsigned char pdx_subregs
: 1;
2924 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
2925 structure for that register. */
2926 static struct equivalence
*reg_equiv
;
2928 /* Used for communication between the following two functions. */
2929 struct equiv_mem_data
2931 /* A MEM that we wish to ensure remains unchanged. */
2934 /* Set true if EQUIV_MEM is modified. */
2935 bool equiv_mem_modified
;
2938 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
2939 Called via note_stores. */
2941 validate_equiv_mem_from_store (rtx dest
, const_rtx set ATTRIBUTE_UNUSED
,
2944 struct equiv_mem_data
*info
= (struct equiv_mem_data
*) data
;
2947 && reg_overlap_mentioned_p (dest
, info
->equiv_mem
))
2949 && anti_dependence (info
->equiv_mem
, dest
)))
2950 info
->equiv_mem_modified
= true;
2953 enum valid_equiv
{ valid_none
, valid_combine
, valid_reload
};
2955 /* Verify that no store between START and the death of REG invalidates
2956 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
2957 by storing into an overlapping memory location, or with a non-const
2960 Return VALID_RELOAD if MEMREF remains valid for both reload and
2961 combine_and_move insns, VALID_COMBINE if only valid for
2962 combine_and_move_insns, and VALID_NONE otherwise. */
2963 static enum valid_equiv
2964 validate_equiv_mem (rtx_insn
*start
, rtx reg
, rtx memref
)
2968 struct equiv_mem_data info
= { memref
, false };
2969 enum valid_equiv ret
= valid_reload
;
2971 /* If the memory reference has side effects or is volatile, it isn't a
2972 valid equivalence. */
2973 if (side_effects_p (memref
))
2976 for (insn
= start
; insn
; insn
= NEXT_INSN (insn
))
2981 if (find_reg_note (insn
, REG_DEAD
, reg
))
2986 /* We can combine a reg def from one insn into a reg use in
2987 another over a call if the memory is readonly or the call
2988 const/pure. However, we can't set reg_equiv notes up for
2989 reload over any call. The problem is the equivalent form
2990 may reference a pseudo which gets assigned a call
2991 clobbered hard reg. When we later replace REG with its
2992 equivalent form, the value in the call-clobbered reg has
2993 been changed and all hell breaks loose. */
2994 ret
= valid_combine
;
2995 if (!MEM_READONLY_P (memref
)
2996 && !RTL_CONST_OR_PURE_CALL_P (insn
))
3000 note_stores (insn
, validate_equiv_mem_from_store
, &info
);
3001 if (info
.equiv_mem_modified
)
3004 /* If a register mentioned in MEMREF is modified via an
3005 auto-increment, we lose the equivalence. Do the same if one
3006 dies; although we could extend the life, it doesn't seem worth
3009 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3010 if ((REG_NOTE_KIND (note
) == REG_INC
3011 || REG_NOTE_KIND (note
) == REG_DEAD
)
3012 && REG_P (XEXP (note
, 0))
3013 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
3020 /* Returns zero if X is known to be invariant. */
3022 equiv_init_varies_p (rtx x
)
3024 RTX_CODE code
= GET_CODE (x
);
3031 return !MEM_READONLY_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
3040 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
3043 if (MEM_VOLATILE_P (x
))
3052 fmt
= GET_RTX_FORMAT (code
);
3053 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3056 if (equiv_init_varies_p (XEXP (x
, i
)))
3059 else if (fmt
[i
] == 'E')
3062 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3063 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
3070 /* Returns nonzero if X (used to initialize register REGNO) is movable.
3071 X is only movable if the registers it uses have equivalent initializations
3072 which appear to be within the same loop (or in an inner loop) and movable
3073 or if they are not candidates for local_alloc and don't vary. */
3075 equiv_init_movable_p (rtx x
, int regno
)
3079 enum rtx_code code
= GET_CODE (x
);
3084 return equiv_init_movable_p (SET_SRC (x
), regno
);
3100 return ((reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
3101 && reg_equiv
[REGNO (x
)].replace
)
3102 || (REG_BASIC_BLOCK (REGNO (x
)) < NUM_FIXED_BLOCKS
3103 && ! rtx_varies_p (x
, 0)));
3105 case UNSPEC_VOLATILE
:
3109 if (MEM_VOLATILE_P (x
))
3118 fmt
= GET_RTX_FORMAT (code
);
3119 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3123 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
3127 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3128 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
3136 static bool memref_referenced_p (rtx memref
, rtx x
, bool read_p
);
3138 /* Auxiliary function for memref_referenced_p. Process setting X for
3141 process_set_for_memref_referenced_p (rtx memref
, rtx x
)
3143 /* If we are setting a MEM, it doesn't count (its address does), but any
3144 other SET_DEST that has a MEM in it is referencing the MEM. */
3147 if (memref_referenced_p (memref
, XEXP (x
, 0), true))
3150 else if (memref_referenced_p (memref
, x
, false))
3156 /* TRUE if X references a memory location (as a read if READ_P) that
3157 would be affected by a store to MEMREF. */
3159 memref_referenced_p (rtx memref
, rtx x
, bool read_p
)
3163 enum rtx_code code
= GET_CODE (x
);
3178 return (reg_equiv
[REGNO (x
)].replacement
3179 && memref_referenced_p (memref
,
3180 reg_equiv
[REGNO (x
)].replacement
, read_p
));
3183 /* Memory X might have another effective type than MEMREF. */
3184 if (read_p
|| true_dependence (memref
, VOIDmode
, x
))
3189 if (process_set_for_memref_referenced_p (memref
, SET_DEST (x
)))
3192 return memref_referenced_p (memref
, SET_SRC (x
), true);
3196 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3205 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3208 return memref_referenced_p (memref
, XEXP (x
, 0), true);
3212 /* op0 = op0 + op1 */
3213 if (process_set_for_memref_referenced_p (memref
, XEXP (x
, 0)))
3216 if (memref_referenced_p (memref
, XEXP (x
, 0), true))
3219 return memref_referenced_p (memref
, XEXP (x
, 1), true);
3225 fmt
= GET_RTX_FORMAT (code
);
3226 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3230 if (memref_referenced_p (memref
, XEXP (x
, i
), read_p
))
3234 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3235 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
), read_p
))
3243 /* TRUE if some insn in the range (START, END] references a memory location
3244 that would be affected by a store to MEMREF.
3246 Callers should not call this routine if START is after END in the
3250 memref_used_between_p (rtx memref
, rtx_insn
*start
, rtx_insn
*end
)
3254 for (insn
= NEXT_INSN (start
);
3255 insn
&& insn
!= NEXT_INSN (end
);
3256 insn
= NEXT_INSN (insn
))
3258 if (!NONDEBUG_INSN_P (insn
))
3261 if (memref_referenced_p (memref
, PATTERN (insn
), false))
3264 /* Nonconst functions may access memory. */
3265 if (CALL_P (insn
) && (! RTL_CONST_CALL_P (insn
)))
3269 gcc_assert (insn
== NEXT_INSN (end
));
3273 /* Mark REG as having no known equivalence.
3274 Some instructions might have been processed before and furnished
3275 with REG_EQUIV notes for this register; these notes will have to be
3277 STORE is the piece of RTL that does the non-constant / conflicting
3278 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
3279 but needs to be there because this function is called from note_stores. */
3281 no_equiv (rtx reg
, const_rtx store ATTRIBUTE_UNUSED
,
3282 void *data ATTRIBUTE_UNUSED
)
3285 rtx_insn_list
*list
;
3289 regno
= REGNO (reg
);
3290 reg_equiv
[regno
].no_equiv
= 1;
3291 list
= reg_equiv
[regno
].init_insns
;
3292 if (list
&& list
->insn () == NULL
)
3294 reg_equiv
[regno
].init_insns
= gen_rtx_INSN_LIST (VOIDmode
, NULL_RTX
, NULL
);
3295 reg_equiv
[regno
].replacement
= NULL_RTX
;
3296 /* This doesn't matter for equivalences made for argument registers, we
3297 should keep their initialization insns. */
3298 if (reg_equiv
[regno
].is_arg_equivalence
)
3300 ira_reg_equiv
[regno
].defined_p
= false;
3301 ira_reg_equiv
[regno
].init_insns
= NULL
;
3302 for (; list
; list
= list
->next ())
3304 rtx_insn
*insn
= list
->insn ();
3305 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
3309 /* Check whether the SUBREG is a paradoxical subreg and set the result
3313 set_paradoxical_subreg (rtx_insn
*insn
)
3315 subrtx_iterator::array_type array
;
3316 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
3318 const_rtx subreg
= *iter
;
3319 if (GET_CODE (subreg
) == SUBREG
)
3321 const_rtx reg
= SUBREG_REG (subreg
);
3322 if (REG_P (reg
) && paradoxical_subreg_p (subreg
))
3323 reg_equiv
[REGNO (reg
)].pdx_subregs
= true;
3328 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the
3329 equivalent replacement. */
3332 adjust_cleared_regs (rtx loc
, const_rtx old_rtx ATTRIBUTE_UNUSED
, void *data
)
3336 bitmap cleared_regs
= (bitmap
) data
;
3337 if (bitmap_bit_p (cleared_regs
, REGNO (loc
)))
3338 return simplify_replace_fn_rtx (copy_rtx (*reg_equiv
[REGNO (loc
)].src_p
),
3339 NULL_RTX
, adjust_cleared_regs
, data
);
3344 /* Given register REGNO is set only once, return true if the defining
3345 insn dominates all uses. */
3348 def_dominates_uses (int regno
)
3350 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3352 struct df_insn_info
*def_info
= DF_REF_INSN_INFO (def
);
3353 /* If this is an artificial def (eh handler regs, hard frame pointer
3354 for non-local goto, regs defined on function entry) then def_info
3355 is NULL and the reg is always live before any use. We might
3356 reasonably return true in that case, but since the only call
3357 of this function is currently here in ira.c when we are looking
3358 at a defining insn we can't have an artificial def as that would
3359 bump DF_REG_DEF_COUNT. */
3360 gcc_assert (DF_REG_DEF_COUNT (regno
) == 1 && def_info
!= NULL
);
3362 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3363 basic_block def_bb
= BLOCK_FOR_INSN (def_insn
);
3365 for (df_ref use
= DF_REG_USE_CHAIN (regno
);
3367 use
= DF_REF_NEXT_REG (use
))
3369 struct df_insn_info
*use_info
= DF_REF_INSN_INFO (use
);
3370 /* Only check real uses, not artificial ones. */
3373 rtx_insn
*use_insn
= DF_REF_INSN (use
);
3374 if (!DEBUG_INSN_P (use_insn
))
3376 basic_block use_bb
= BLOCK_FOR_INSN (use_insn
);
3377 if (use_bb
!= def_bb
3378 ? !dominated_by_p (CDI_DOMINATORS
, use_bb
, def_bb
)
3379 : DF_INSN_INFO_LUID (use_info
) < DF_INSN_INFO_LUID (def_info
))
3387 /* Find registers that are equivalent to a single value throughout the
3388 compilation (either because they can be referenced in memory or are
3389 set once from a single constant). Lower their priority for a
3392 If such a register is only referenced once, try substituting its
3393 value into the using insn. If it succeeds, we can eliminate the
3394 register completely.
3396 Initialize init_insns in ira_reg_equiv array. */
3398 update_equiv_regs (void)
3403 /* Scan insns and set pdx_subregs if the reg is used in a
3404 paradoxical subreg. Don't set such reg equivalent to a mem,
3405 because lra will not substitute such equiv memory in order to
3406 prevent access beyond allocated memory for paradoxical memory subreg. */
3407 FOR_EACH_BB_FN (bb
, cfun
)
3408 FOR_BB_INSNS (bb
, insn
)
3409 if (NONDEBUG_INSN_P (insn
))
3410 set_paradoxical_subreg (insn
);
3412 /* Scan the insns and find which registers have equivalences. Do this
3413 in a separate scan of the insns because (due to -fcse-follow-jumps)
3414 a register can be set below its use. */
3415 bitmap setjmp_crosses
= regstat_get_setjmp_crosses ();
3416 FOR_EACH_BB_FN (bb
, cfun
)
3418 int loop_depth
= bb_loop_depth (bb
);
3420 for (insn
= BB_HEAD (bb
);
3421 insn
!= NEXT_INSN (BB_END (bb
));
3422 insn
= NEXT_INSN (insn
))
3429 if (! INSN_P (insn
))
3432 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
3433 if (REG_NOTE_KIND (note
) == REG_INC
)
3434 no_equiv (XEXP (note
, 0), note
, NULL
);
3436 set
= single_set (insn
);
3438 /* If this insn contains more (or less) than a single SET,
3439 only mark all destinations as having no known equivalence. */
3441 || side_effects_p (SET_SRC (set
)))
3443 note_pattern_stores (PATTERN (insn
), no_equiv
, NULL
);
3446 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
3450 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
3452 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
3454 note_pattern_stores (part
, no_equiv
, NULL
);
3458 dest
= SET_DEST (set
);
3459 src
= SET_SRC (set
);
3461 /* See if this is setting up the equivalence between an argument
3462 register and its stack slot. */
3463 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3466 gcc_assert (REG_P (dest
));
3467 regno
= REGNO (dest
);
3469 /* Note that we don't want to clear init_insns in
3470 ira_reg_equiv even if there are multiple sets of this
3472 reg_equiv
[regno
].is_arg_equivalence
= 1;
3474 /* The insn result can have equivalence memory although
3475 the equivalence is not set up by the insn. We add
3476 this insn to init insns as it is a flag for now that
3477 regno has an equivalence. We will remove the insn
3478 from init insn list later. */
3479 if (rtx_equal_p (src
, XEXP (note
, 0)) || MEM_P (XEXP (note
, 0)))
3480 ira_reg_equiv
[regno
].init_insns
3481 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3482 ira_reg_equiv
[regno
].init_insns
);
3484 /* Continue normally in case this is a candidate for
3491 /* We only handle the case of a pseudo register being set
3492 once, or always to the same value. */
3493 /* ??? The mn10200 port breaks if we add equivalences for
3494 values that need an ADDRESS_REGS register and set them equivalent
3495 to a MEM of a pseudo. The actual problem is in the over-conservative
3496 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
3497 calculate_needs, but we traditionally work around this problem
3498 here by rejecting equivalences when the destination is in a register
3499 that's likely spilled. This is fragile, of course, since the
3500 preferred class of a pseudo depends on all instructions that set
3504 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
3505 || (reg_equiv
[regno
].init_insns
3506 && reg_equiv
[regno
].init_insns
->insn () == NULL
)
3507 || (targetm
.class_likely_spilled_p (reg_preferred_class (regno
))
3508 && MEM_P (src
) && ! reg_equiv
[regno
].is_arg_equivalence
))
3510 /* This might be setting a SUBREG of a pseudo, a pseudo that is
3511 also set somewhere else to a constant. */
3512 note_pattern_stores (set
, no_equiv
, NULL
);
3516 /* Don't set reg mentioned in a paradoxical subreg
3517 equivalent to a mem. */
3518 if (MEM_P (src
) && reg_equiv
[regno
].pdx_subregs
)
3520 note_pattern_stores (set
, no_equiv
, NULL
);
3524 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
3526 /* cse sometimes generates function invariants, but doesn't put a
3527 REG_EQUAL note on the insn. Since this note would be redundant,
3528 there's no point creating it earlier than here. */
3529 if (! note
&& ! rtx_varies_p (src
, 0))
3530 note
= set_unique_reg_note (insn
, REG_EQUAL
, copy_rtx (src
));
3532 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
3533 since it represents a function call. */
3534 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
3537 if (DF_REG_DEF_COUNT (regno
) != 1)
3539 bool equal_p
= true;
3540 rtx_insn_list
*list
;
3542 /* If we have already processed this pseudo and determined it
3543 cannot have an equivalence, then honor that decision. */
3544 if (reg_equiv
[regno
].no_equiv
)
3548 || rtx_varies_p (XEXP (note
, 0), 0)
3549 || (reg_equiv
[regno
].replacement
3550 && ! rtx_equal_p (XEXP (note
, 0),
3551 reg_equiv
[regno
].replacement
)))
3553 no_equiv (dest
, set
, NULL
);
3557 list
= reg_equiv
[regno
].init_insns
;
3558 for (; list
; list
= list
->next ())
3563 insn_tmp
= list
->insn ();
3564 note_tmp
= find_reg_note (insn_tmp
, REG_EQUAL
, NULL_RTX
);
3565 gcc_assert (note_tmp
);
3566 if (! rtx_equal_p (XEXP (note
, 0), XEXP (note_tmp
, 0)))
3575 no_equiv (dest
, set
, NULL
);
3580 /* Record this insn as initializing this register. */
3581 reg_equiv
[regno
].init_insns
3582 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
3584 /* If this register is known to be equal to a constant, record that
3585 it is always equivalent to the constant.
3586 Note that it is possible to have a register use before
3587 the def in loops (see gcc.c-torture/execute/pr79286.c)
3588 where the reg is undefined on first use. If the def insn
3589 won't trap we can use it as an equivalence, effectively
3590 choosing the "undefined" value for the reg to be the
3591 same as the value set by the def. */
3592 if (DF_REG_DEF_COUNT (regno
) == 1
3594 && !rtx_varies_p (XEXP (note
, 0), 0)
3595 && (!may_trap_or_fault_p (XEXP (note
, 0))
3596 || def_dominates_uses (regno
)))
3598 rtx note_value
= XEXP (note
, 0);
3599 remove_note (insn
, note
);
3600 set_unique_reg_note (insn
, REG_EQUIV
, note_value
);
3603 /* If this insn introduces a "constant" register, decrease the priority
3604 of that register. Record this insn if the register is only used once
3605 more and the equivalence value is the same as our source.
3607 The latter condition is checked for two reasons: First, it is an
3608 indication that it may be more efficient to actually emit the insn
3609 as written (if no registers are available, reload will substitute
3610 the equivalence). Secondly, it avoids problems with any registers
3611 dying in this insn whose death notes would be missed.
3613 If we don't have a REG_EQUIV note, see if this insn is loading
3614 a register used only in one basic block from a MEM. If so, and the
3615 MEM remains unchanged for the life of the register, add a REG_EQUIV
3617 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
3619 rtx replacement
= NULL_RTX
;
3621 replacement
= XEXP (note
, 0);
3622 else if (REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3623 && MEM_P (SET_SRC (set
)))
3625 enum valid_equiv validity
;
3626 validity
= validate_equiv_mem (insn
, dest
, SET_SRC (set
));
3627 if (validity
!= valid_none
)
3629 replacement
= copy_rtx (SET_SRC (set
));
3630 if (validity
== valid_reload
)
3631 note
= set_unique_reg_note (insn
, REG_EQUIV
, replacement
);
3635 /* If we haven't done so, record for reload that this is an
3636 equivalencing insn. */
3637 if (note
&& !reg_equiv
[regno
].is_arg_equivalence
)
3638 ira_reg_equiv
[regno
].init_insns
3639 = gen_rtx_INSN_LIST (VOIDmode
, insn
,
3640 ira_reg_equiv
[regno
].init_insns
);
3644 reg_equiv
[regno
].replacement
= replacement
;
3645 reg_equiv
[regno
].src_p
= &SET_SRC (set
);
3646 reg_equiv
[regno
].loop_depth
= (short) loop_depth
;
3648 /* Don't mess with things live during setjmp. */
3649 if (optimize
&& !bitmap_bit_p (setjmp_crosses
, regno
))
3651 /* If the register is referenced exactly twice, meaning it is
3652 set once and used once, indicate that the reference may be
3653 replaced by the equivalence we computed above. Do this
3654 even if the register is only used in one block so that
3655 dependencies can be handled where the last register is
3656 used in a different block (i.e. HIGH / LO_SUM sequences)
3657 and to reduce the number of registers alive across
3660 if (REG_N_REFS (regno
) == 2
3661 && (rtx_equal_p (replacement
, src
)
3662 || ! equiv_init_varies_p (src
))
3663 && NONJUMP_INSN_P (insn
)
3664 && equiv_init_movable_p (PATTERN (insn
), regno
))
3665 reg_equiv
[regno
].replace
= 1;
3672 /* For insns that set a MEM to the contents of a REG that is only used
3673 in a single basic block, see if the register is always equivalent
3674 to that memory location and if moving the store from INSN to the
3675 insn that sets REG is safe. If so, put a REG_EQUIV note on the
3676 initializing insn. */
3678 add_store_equivs (void)
3680 auto_bitmap seen_insns
;
3682 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3686 rtx_insn
*init_insn
;
3688 bitmap_set_bit (seen_insns
, INSN_UID (insn
));
3690 if (! INSN_P (insn
))
3693 set
= single_set (insn
);
3697 dest
= SET_DEST (set
);
3698 src
= SET_SRC (set
);
3700 /* Don't add a REG_EQUIV note if the insn already has one. The existing
3701 REG_EQUIV is likely more useful than the one we are adding. */
3702 if (MEM_P (dest
) && REG_P (src
)
3703 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
3704 && REG_BASIC_BLOCK (regno
) >= NUM_FIXED_BLOCKS
3705 && DF_REG_DEF_COUNT (regno
) == 1
3706 && ! reg_equiv
[regno
].pdx_subregs
3707 && reg_equiv
[regno
].init_insns
!= NULL
3708 && (init_insn
= reg_equiv
[regno
].init_insns
->insn ()) != 0
3709 && bitmap_bit_p (seen_insns
, INSN_UID (init_insn
))
3710 && ! find_reg_note (init_insn
, REG_EQUIV
, NULL_RTX
)
3711 && validate_equiv_mem (init_insn
, src
, dest
) == valid_reload
3712 && ! memref_used_between_p (dest
, init_insn
, insn
)
3713 /* Attaching a REG_EQUIV note will fail if INIT_INSN has
3715 && set_unique_reg_note (init_insn
, REG_EQUIV
, copy_rtx (dest
)))
3717 /* This insn makes the equivalence, not the one initializing
3719 ira_reg_equiv
[regno
].init_insns
3720 = gen_rtx_INSN_LIST (VOIDmode
, insn
, NULL_RTX
);
3721 df_notes_rescan (init_insn
);
3724 "Adding REG_EQUIV to insn %d for source of insn %d\n",
3725 INSN_UID (init_insn
),
3731 /* Scan all regs killed in an insn to see if any of them are registers
3732 only used that once. If so, see if we can replace the reference
3733 with the equivalent form. If we can, delete the initializing
3734 reference and this register will go away. If we can't replace the
3735 reference, and the initializing reference is within the same loop
3736 (or in an inner loop), then move the register initialization just
3737 before the use, so that they are in the same basic block. */
3739 combine_and_move_insns (void)
3741 auto_bitmap cleared_regs
;
3742 int max
= max_reg_num ();
3744 for (int regno
= FIRST_PSEUDO_REGISTER
; regno
< max
; regno
++)
3746 if (!reg_equiv
[regno
].replace
)
3749 rtx_insn
*use_insn
= 0;
3750 for (df_ref use
= DF_REG_USE_CHAIN (regno
);
3752 use
= DF_REF_NEXT_REG (use
))
3753 if (DF_REF_INSN_INFO (use
))
3755 if (DEBUG_INSN_P (DF_REF_INSN (use
)))
3757 gcc_assert (!use_insn
);
3758 use_insn
= DF_REF_INSN (use
);
3760 gcc_assert (use_insn
);
3762 /* Don't substitute into jumps. indirect_jump_optimize does
3763 this for anything we are prepared to handle. */
3764 if (JUMP_P (use_insn
))
3767 /* Also don't substitute into a conditional trap insn -- it can become
3768 an unconditional trap, and that is a flow control insn. */
3769 if (GET_CODE (PATTERN (use_insn
)) == TRAP_IF
)
3772 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3773 gcc_assert (DF_REG_DEF_COUNT (regno
) == 1 && DF_REF_INSN_INFO (def
));
3774 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3776 /* We may not move instructions that can throw, since that
3777 changes basic block boundaries and we are not prepared to
3778 adjust the CFG to match. */
3779 if (can_throw_internal (def_insn
))
3782 basic_block use_bb
= BLOCK_FOR_INSN (use_insn
);
3783 basic_block def_bb
= BLOCK_FOR_INSN (def_insn
);
3784 if (bb_loop_depth (use_bb
) > bb_loop_depth (def_bb
))
3787 if (asm_noperands (PATTERN (def_insn
)) < 0
3788 && validate_replace_rtx (regno_reg_rtx
[regno
],
3789 *reg_equiv
[regno
].src_p
, use_insn
))
3792 /* Append the REG_DEAD notes from def_insn. */
3793 for (rtx
*p
= ®_NOTES (def_insn
); (link
= *p
) != 0; )
3795 if (REG_NOTE_KIND (XEXP (link
, 0)) == REG_DEAD
)
3797 *p
= XEXP (link
, 1);
3798 XEXP (link
, 1) = REG_NOTES (use_insn
);
3799 REG_NOTES (use_insn
) = link
;
3802 p
= &XEXP (link
, 1);
3805 remove_death (regno
, use_insn
);
3806 SET_REG_N_REFS (regno
, 0);
3807 REG_FREQ (regno
) = 0;
3809 FOR_EACH_INSN_USE (use
, def_insn
)
3811 unsigned int use_regno
= DF_REF_REGNO (use
);
3812 if (!HARD_REGISTER_NUM_P (use_regno
))
3813 reg_equiv
[use_regno
].replace
= 0;
3816 delete_insn (def_insn
);
3818 reg_equiv
[regno
].init_insns
= NULL
;
3819 ira_reg_equiv
[regno
].init_insns
= NULL
;
3820 bitmap_set_bit (cleared_regs
, regno
);
3823 /* Move the initialization of the register to just before
3824 USE_INSN. Update the flow information. */
3825 else if (prev_nondebug_insn (use_insn
) != def_insn
)
3829 new_insn
= emit_insn_before (PATTERN (def_insn
), use_insn
);
3830 REG_NOTES (new_insn
) = REG_NOTES (def_insn
);
3831 REG_NOTES (def_insn
) = 0;
3832 /* Rescan it to process the notes. */
3833 df_insn_rescan (new_insn
);
3835 /* Make sure this insn is recognized before reload begins,
3836 otherwise eliminate_regs_in_insn will die. */
3837 INSN_CODE (new_insn
) = INSN_CODE (def_insn
);
3839 delete_insn (def_insn
);
3841 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
3843 REG_BASIC_BLOCK (regno
) = use_bb
->index
;
3844 REG_N_CALLS_CROSSED (regno
) = 0;
3846 if (use_insn
== BB_HEAD (use_bb
))
3847 BB_HEAD (use_bb
) = new_insn
;
3849 /* We know regno dies in use_insn, but inside a loop
3850 REG_DEAD notes might be missing when def_insn was in
3851 another basic block. However, when we move def_insn into
3852 this bb we'll definitely get a REG_DEAD note and reload
3853 will see the death. It's possible that update_equiv_regs
3854 set up an equivalence referencing regno for a reg set by
3855 use_insn, when regno was seen as non-local. Now that
3856 regno is local to this block, and dies, such an
3857 equivalence is invalid. */
3858 if (find_reg_note (use_insn
, REG_EQUIV
, regno_reg_rtx
[regno
]))
3860 rtx set
= single_set (use_insn
);
3861 if (set
&& REG_P (SET_DEST (set
)))
3862 no_equiv (SET_DEST (set
), set
, NULL
);
3865 ira_reg_equiv
[regno
].init_insns
3866 = gen_rtx_INSN_LIST (VOIDmode
, new_insn
, NULL_RTX
);
3867 bitmap_set_bit (cleared_regs
, regno
);
3871 if (!bitmap_empty_p (cleared_regs
))
3875 FOR_EACH_BB_FN (bb
, cfun
)
3877 bitmap_and_compl_into (DF_LR_IN (bb
), cleared_regs
);
3878 bitmap_and_compl_into (DF_LR_OUT (bb
), cleared_regs
);
3881 bitmap_and_compl_into (DF_LIVE_IN (bb
), cleared_regs
);
3882 bitmap_and_compl_into (DF_LIVE_OUT (bb
), cleared_regs
);
3885 /* Last pass - adjust debug insns referencing cleared regs. */
3886 if (MAY_HAVE_DEBUG_BIND_INSNS
)
3887 for (rtx_insn
*insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
3888 if (DEBUG_BIND_INSN_P (insn
))
3890 rtx old_loc
= INSN_VAR_LOCATION_LOC (insn
);
3891 INSN_VAR_LOCATION_LOC (insn
)
3892 = simplify_replace_fn_rtx (old_loc
, NULL_RTX
,
3893 adjust_cleared_regs
,
3894 (void *) cleared_regs
);
3895 if (old_loc
!= INSN_VAR_LOCATION_LOC (insn
))
3896 df_insn_rescan (insn
);
3901 /* A pass over indirect jumps, converting simple cases to direct jumps.
3902 Combine does this optimization too, but only within a basic block. */
3904 indirect_jump_optimize (void)
3907 bool rebuild_p
= false;
3909 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3911 rtx_insn
*insn
= BB_END (bb
);
3913 || find_reg_note (insn
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
3916 rtx x
= pc_set (insn
);
3917 if (!x
|| !REG_P (SET_SRC (x
)))
3920 int regno
= REGNO (SET_SRC (x
));
3921 if (DF_REG_DEF_COUNT (regno
) == 1)
3923 df_ref def
= DF_REG_DEF_CHAIN (regno
);
3924 if (!DF_REF_IS_ARTIFICIAL (def
))
3926 rtx_insn
*def_insn
= DF_REF_INSN (def
);
3928 rtx set
= single_set (def_insn
);
3929 if (set
&& GET_CODE (SET_SRC (set
)) == LABEL_REF
)
3930 lab
= SET_SRC (set
);
3933 rtx eqnote
= find_reg_note (def_insn
, REG_EQUAL
, NULL_RTX
);
3934 if (eqnote
&& GET_CODE (XEXP (eqnote
, 0)) == LABEL_REF
)
3935 lab
= XEXP (eqnote
, 0);
3937 if (lab
&& validate_replace_rtx (SET_SRC (x
), lab
, insn
))
3945 timevar_push (TV_JUMP
);
3946 rebuild_jump_labels (get_insns ());
3947 if (purge_all_dead_edges ())
3948 delete_unreachable_blocks ();
3949 timevar_pop (TV_JUMP
);
3953 /* Set up fields memory, constant, and invariant from init_insns in
3954 the structures of array ira_reg_equiv. */
3956 setup_reg_equiv (void)
3959 rtx_insn_list
*elem
, *prev_elem
, *next_elem
;
3963 for (i
= FIRST_PSEUDO_REGISTER
; i
< ira_reg_equiv_len
; i
++)
3964 for (prev_elem
= NULL
, elem
= ira_reg_equiv
[i
].init_insns
;
3966 prev_elem
= elem
, elem
= next_elem
)
3968 next_elem
= elem
->next ();
3969 insn
= elem
->insn ();
3970 set
= single_set (insn
);
3972 /* Init insns can set up equivalence when the reg is a destination or
3973 a source (in this case the destination is memory). */
3974 if (set
!= 0 && (REG_P (SET_DEST (set
)) || REG_P (SET_SRC (set
))))
3976 if ((x
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
)) != NULL
)
3979 if (REG_P (SET_DEST (set
))
3980 && REGNO (SET_DEST (set
)) == (unsigned int) i
3981 && ! rtx_equal_p (SET_SRC (set
), x
) && MEM_P (x
))
3983 /* This insn reporting the equivalence but
3984 actually not setting it. Remove it from the
3986 if (prev_elem
== NULL
)
3987 ira_reg_equiv
[i
].init_insns
= next_elem
;
3989 XEXP (prev_elem
, 1) = next_elem
;
3993 else if (REG_P (SET_DEST (set
))
3994 && REGNO (SET_DEST (set
)) == (unsigned int) i
)
3998 gcc_assert (REG_P (SET_SRC (set
))
3999 && REGNO (SET_SRC (set
)) == (unsigned int) i
);
4002 if (! function_invariant_p (x
)
4004 /* A function invariant is often CONSTANT_P but may
4005 include a register. We promise to only pass
4006 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
4007 || (CONSTANT_P (x
) && LEGITIMATE_PIC_OPERAND_P (x
)))
4009 /* It can happen that a REG_EQUIV note contains a MEM
4010 that is not a legitimate memory operand. As later
4011 stages of reload assume that all addresses found in
4012 the lra_regno_equiv_* arrays were originally
4013 legitimate, we ignore such REG_EQUIV notes. */
4014 if (memory_operand (x
, VOIDmode
))
4016 ira_reg_equiv
[i
].defined_p
= true;
4017 ira_reg_equiv
[i
].memory
= x
;
4020 else if (function_invariant_p (x
))
4024 mode
= GET_MODE (SET_DEST (set
));
4025 if (GET_CODE (x
) == PLUS
4026 || x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4027 /* This is PLUS of frame pointer and a constant,
4029 ira_reg_equiv
[i
].invariant
= x
;
4030 else if (targetm
.legitimate_constant_p (mode
, x
))
4031 ira_reg_equiv
[i
].constant
= x
;
4034 ira_reg_equiv
[i
].memory
= force_const_mem (mode
, x
);
4035 if (ira_reg_equiv
[i
].memory
== NULL_RTX
)
4037 ira_reg_equiv
[i
].defined_p
= false;
4038 ira_reg_equiv
[i
].init_insns
= NULL
;
4042 ira_reg_equiv
[i
].defined_p
= true;
4047 ira_reg_equiv
[i
].defined_p
= false;
4048 ira_reg_equiv
[i
].init_insns
= NULL
;
4055 /* Print chain C to FILE. */
4057 print_insn_chain (FILE *file
, class insn_chain
*c
)
4059 fprintf (file
, "insn=%d, ", INSN_UID (c
->insn
));
4060 bitmap_print (file
, &c
->live_throughout
, "live_throughout: ", ", ");
4061 bitmap_print (file
, &c
->dead_or_set
, "dead_or_set: ", "\n");
4065 /* Print all reload_insn_chains to FILE. */
4067 print_insn_chains (FILE *file
)
4069 class insn_chain
*c
;
4070 for (c
= reload_insn_chain
; c
; c
= c
->next
)
4071 print_insn_chain (file
, c
);
4074 /* Return true if pseudo REGNO should be added to set live_throughout
4075 or dead_or_set of the insn chains for reload consideration. */
4077 pseudo_for_reload_consideration_p (int regno
)
4079 /* Consider spilled pseudos too for IRA because they still have a
4080 chance to get hard-registers in the reload when IRA is used. */
4081 return (reg_renumber
[regno
] >= 0 || ira_conflicts_p
);
4084 /* Return true if we can track the individual bytes of subreg X.
4085 When returning true, set *OUTER_SIZE to the number of bytes in
4086 X itself, *INNER_SIZE to the number of bytes in the inner register
4087 and *START to the offset of the first byte. */
4089 get_subreg_tracking_sizes (rtx x
, HOST_WIDE_INT
*outer_size
,
4090 HOST_WIDE_INT
*inner_size
, HOST_WIDE_INT
*start
)
4092 rtx reg
= regno_reg_rtx
[REGNO (SUBREG_REG (x
))];
4093 return (GET_MODE_SIZE (GET_MODE (x
)).is_constant (outer_size
)
4094 && GET_MODE_SIZE (GET_MODE (reg
)).is_constant (inner_size
)
4095 && SUBREG_BYTE (x
).is_constant (start
));
4098 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] for
4099 a register with SIZE bytes, making the register live if INIT_VALUE. */
4101 init_live_subregs (bool init_value
, sbitmap
*live_subregs
,
4102 bitmap live_subregs_used
, int allocnum
, int size
)
4104 gcc_assert (size
> 0);
4106 /* Been there, done that. */
4107 if (bitmap_bit_p (live_subregs_used
, allocnum
))
4110 /* Create a new one. */
4111 if (live_subregs
[allocnum
] == NULL
)
4112 live_subregs
[allocnum
] = sbitmap_alloc (size
);
4114 /* If the entire reg was live before blasting into subregs, we need
4115 to init all of the subregs to ones else init to 0. */
4117 bitmap_ones (live_subregs
[allocnum
]);
4119 bitmap_clear (live_subregs
[allocnum
]);
4121 bitmap_set_bit (live_subregs_used
, allocnum
);
4124 /* Walk the insns of the current function and build reload_insn_chain,
4125 and record register life information. */
4127 build_insn_chain (void)
4130 class insn_chain
**p
= &reload_insn_chain
;
4132 class insn_chain
*c
= NULL
;
4133 class insn_chain
*next
= NULL
;
4134 auto_bitmap live_relevant_regs
;
4135 auto_bitmap elim_regset
;
4136 /* live_subregs is a vector used to keep accurate information about
4137 which hardregs are live in multiword pseudos. live_subregs and
4138 live_subregs_used are indexed by pseudo number. The live_subreg
4139 entry for a particular pseudo is only used if the corresponding
4140 element is non zero in live_subregs_used. The sbitmap size of
4141 live_subreg[allocno] is number of bytes that the pseudo can
4143 sbitmap
*live_subregs
= XCNEWVEC (sbitmap
, max_regno
);
4144 auto_bitmap live_subregs_used
;
4146 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4147 if (TEST_HARD_REG_BIT (eliminable_regset
, i
))
4148 bitmap_set_bit (elim_regset
, i
);
4149 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
4154 CLEAR_REG_SET (live_relevant_regs
);
4155 bitmap_clear (live_subregs_used
);
4157 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
), 0, i
, bi
)
4159 if (i
>= FIRST_PSEUDO_REGISTER
)
4161 bitmap_set_bit (live_relevant_regs
, i
);
4164 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb
),
4165 FIRST_PSEUDO_REGISTER
, i
, bi
)
4167 if (pseudo_for_reload_consideration_p (i
))
4168 bitmap_set_bit (live_relevant_regs
, i
);
4171 FOR_BB_INSNS_REVERSE (bb
, insn
)
4173 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4175 struct df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4178 c
= new_insn_chain ();
4185 c
->block
= bb
->index
;
4187 if (NONDEBUG_INSN_P (insn
))
4188 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4190 unsigned int regno
= DF_REF_REGNO (def
);
4192 /* Ignore may clobbers because these are generated
4193 from calls. However, every other kind of def is
4194 added to dead_or_set. */
4195 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_MAY_CLOBBER
))
4197 if (regno
< FIRST_PSEUDO_REGISTER
)
4199 if (!fixed_regs
[regno
])
4200 bitmap_set_bit (&c
->dead_or_set
, regno
);
4202 else if (pseudo_for_reload_consideration_p (regno
))
4203 bitmap_set_bit (&c
->dead_or_set
, regno
);
4206 if ((regno
< FIRST_PSEUDO_REGISTER
4207 || reg_renumber
[regno
] >= 0
4209 && (!DF_REF_FLAGS_IS_SET (def
, DF_REF_CONDITIONAL
)))
4211 rtx reg
= DF_REF_REG (def
);
4212 HOST_WIDE_INT outer_size
, inner_size
, start
;
4214 /* We can usually track the liveness of individual
4215 bytes within a subreg. The only exceptions are
4216 subregs wrapped in ZERO_EXTRACTs and subregs whose
4217 size is not known; in those cases we need to be
4218 conservative and treat the definition as a partial
4219 definition of the full register rather than a full
4220 definition of a specific part of the register. */
4221 if (GET_CODE (reg
) == SUBREG
4222 && !DF_REF_FLAGS_IS_SET (def
, DF_REF_ZERO_EXTRACT
)
4223 && get_subreg_tracking_sizes (reg
, &outer_size
,
4224 &inner_size
, &start
))
4226 HOST_WIDE_INT last
= start
+ outer_size
;
4229 (bitmap_bit_p (live_relevant_regs
, regno
),
4230 live_subregs
, live_subregs_used
, regno
,
4233 if (!DF_REF_FLAGS_IS_SET
4234 (def
, DF_REF_STRICT_LOW_PART
))
4236 /* Expand the range to cover entire words.
4237 Bytes added here are "don't care". */
4239 = start
/ UNITS_PER_WORD
* UNITS_PER_WORD
;
4240 last
= ((last
+ UNITS_PER_WORD
- 1)
4241 / UNITS_PER_WORD
* UNITS_PER_WORD
);
4244 /* Ignore the paradoxical bits. */
4245 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4246 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4248 while (start
< last
)
4250 bitmap_clear_bit (live_subregs
[regno
], start
);
4254 if (bitmap_empty_p (live_subregs
[regno
]))
4256 bitmap_clear_bit (live_subregs_used
, regno
);
4257 bitmap_clear_bit (live_relevant_regs
, regno
);
4260 /* Set live_relevant_regs here because
4261 that bit has to be true to get us to
4262 look at the live_subregs fields. */
4263 bitmap_set_bit (live_relevant_regs
, regno
);
4267 /* DF_REF_PARTIAL is generated for
4268 subregs, STRICT_LOW_PART, and
4269 ZERO_EXTRACT. We handle the subreg
4270 case above so here we have to keep from
4271 modeling the def as a killing def. */
4272 if (!DF_REF_FLAGS_IS_SET (def
, DF_REF_PARTIAL
))
4274 bitmap_clear_bit (live_subregs_used
, regno
);
4275 bitmap_clear_bit (live_relevant_regs
, regno
);
4281 bitmap_and_compl_into (live_relevant_regs
, elim_regset
);
4282 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4284 if (NONDEBUG_INSN_P (insn
))
4285 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4287 unsigned int regno
= DF_REF_REGNO (use
);
4288 rtx reg
= DF_REF_REG (use
);
4290 /* DF_REF_READ_WRITE on a use means that this use
4291 is fabricated from a def that is a partial set
4292 to a multiword reg. Here, we only model the
4293 subreg case that is not wrapped in ZERO_EXTRACT
4294 precisely so we do not need to look at the
4296 if (DF_REF_FLAGS_IS_SET (use
, DF_REF_READ_WRITE
)
4297 && !DF_REF_FLAGS_IS_SET (use
, DF_REF_ZERO_EXTRACT
)
4298 && DF_REF_FLAGS_IS_SET (use
, DF_REF_SUBREG
))
4301 /* Add the last use of each var to dead_or_set. */
4302 if (!bitmap_bit_p (live_relevant_regs
, regno
))
4304 if (regno
< FIRST_PSEUDO_REGISTER
)
4306 if (!fixed_regs
[regno
])
4307 bitmap_set_bit (&c
->dead_or_set
, regno
);
4309 else if (pseudo_for_reload_consideration_p (regno
))
4310 bitmap_set_bit (&c
->dead_or_set
, regno
);
4313 if (regno
< FIRST_PSEUDO_REGISTER
4314 || pseudo_for_reload_consideration_p (regno
))
4316 HOST_WIDE_INT outer_size
, inner_size
, start
;
4317 if (GET_CODE (reg
) == SUBREG
4318 && !DF_REF_FLAGS_IS_SET (use
,
4320 | DF_REF_ZERO_EXTRACT
)
4321 && get_subreg_tracking_sizes (reg
, &outer_size
,
4322 &inner_size
, &start
))
4324 HOST_WIDE_INT last
= start
+ outer_size
;
4327 (bitmap_bit_p (live_relevant_regs
, regno
),
4328 live_subregs
, live_subregs_used
, regno
,
4331 /* Ignore the paradoxical bits. */
4332 if (last
> SBITMAP_SIZE (live_subregs
[regno
]))
4333 last
= SBITMAP_SIZE (live_subregs
[regno
]);
4335 while (start
< last
)
4337 bitmap_set_bit (live_subregs
[regno
], start
);
4342 /* Resetting the live_subregs_used is
4343 effectively saying do not use the subregs
4344 because we are reading the whole
4346 bitmap_clear_bit (live_subregs_used
, regno
);
4347 bitmap_set_bit (live_relevant_regs
, regno
);
4353 /* FIXME!! The following code is a disaster. Reload needs to see the
4354 labels and jump tables that are just hanging out in between
4355 the basic blocks. See pr33676. */
4356 insn
= BB_HEAD (bb
);
4358 /* Skip over the barriers and cruft. */
4359 while (insn
&& (BARRIER_P (insn
) || NOTE_P (insn
)
4360 || BLOCK_FOR_INSN (insn
) == bb
))
4361 insn
= PREV_INSN (insn
);
4363 /* While we add anything except barriers and notes, the focus is
4364 to get the labels and jump tables into the
4365 reload_insn_chain. */
4368 if (!NOTE_P (insn
) && !BARRIER_P (insn
))
4370 if (BLOCK_FOR_INSN (insn
))
4373 c
= new_insn_chain ();
4379 /* The block makes no sense here, but it is what the old
4381 c
->block
= bb
->index
;
4383 bitmap_copy (&c
->live_throughout
, live_relevant_regs
);
4385 insn
= PREV_INSN (insn
);
4389 reload_insn_chain
= c
;
4392 for (i
= 0; i
< (unsigned int) max_regno
; i
++)
4393 if (live_subregs
[i
] != NULL
)
4394 sbitmap_free (live_subregs
[i
]);
4395 free (live_subregs
);
4398 print_insn_chains (dump_file
);
4401 /* Examine the rtx found in *LOC, which is read or written to as determined
4402 by TYPE. Return false if we find a reason why an insn containing this
4403 rtx should not be moved (such as accesses to non-constant memory), true
4406 rtx_moveable_p (rtx
*loc
, enum op_type type
)
4412 enum rtx_code code
= GET_CODE (x
);
4422 return type
== OP_IN
;
4428 if (x
== frame_pointer_rtx
)
4430 if (HARD_REGISTER_P (x
))
4436 if (type
== OP_IN
&& MEM_READONLY_P (x
))
4437 return rtx_moveable_p (&XEXP (x
, 0), OP_IN
);
4441 return (rtx_moveable_p (&SET_SRC (x
), OP_IN
)
4442 && rtx_moveable_p (&SET_DEST (x
), OP_OUT
));
4444 case STRICT_LOW_PART
:
4445 return rtx_moveable_p (&XEXP (x
, 0), OP_OUT
);
4449 return (rtx_moveable_p (&XEXP (x
, 0), type
)
4450 && rtx_moveable_p (&XEXP (x
, 1), OP_IN
)
4451 && rtx_moveable_p (&XEXP (x
, 2), OP_IN
));
4455 return rtx_moveable_p (&SET_DEST (x
), OP_OUT
);
4457 case UNSPEC_VOLATILE
:
4458 /* It is a bad idea to consider insns with such rtl
4459 as moveable ones. The insn scheduler also considers them as barrier
4464 /* The same is true for volatile asm: it has unknown side effects, it
4465 cannot be moved at will. */
4466 if (MEM_VOLATILE_P (x
))
4473 fmt
= GET_RTX_FORMAT (code
);
4474 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4478 if (!rtx_moveable_p (&XEXP (x
, i
), type
))
4481 else if (fmt
[i
] == 'E')
4482 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4484 if (!rtx_moveable_p (&XVECEXP (x
, i
, j
), type
))
4491 /* A wrapper around dominated_by_p, which uses the information in UID_LUID
4492 to give dominance relationships between two insns I1 and I2. */
4494 insn_dominated_by_p (rtx i1
, rtx i2
, int *uid_luid
)
4496 basic_block bb1
= BLOCK_FOR_INSN (i1
);
4497 basic_block bb2
= BLOCK_FOR_INSN (i2
);
4500 return uid_luid
[INSN_UID (i2
)] < uid_luid
[INSN_UID (i1
)];
4501 return dominated_by_p (CDI_DOMINATORS
, bb1
, bb2
);
4504 /* Record the range of register numbers added by find_moveable_pseudos. */
4505 int first_moveable_pseudo
, last_moveable_pseudo
;
4507 /* These two vectors hold data for every register added by
4508 find_movable_pseudos, with index 0 holding data for the
4509 first_moveable_pseudo. */
4510 /* The original home register. */
4511 static vec
<rtx
> pseudo_replaced_reg
;
4513 /* Look for instances where we have an instruction that is known to increase
4514 register pressure, and whose result is not used immediately. If it is
4515 possible to move the instruction downwards to just before its first use,
4516 split its lifetime into two ranges. We create a new pseudo to compute the
4517 value, and emit a move instruction just before the first use. If, after
4518 register allocation, the new pseudo remains unallocated, the function
4519 move_unallocated_pseudos then deletes the move instruction and places
4520 the computation just before the first use.
4522 Such a move is safe and profitable if all the input registers remain live
4523 and unchanged between the original computation and its first use. In such
4524 a situation, the computation is known to increase register pressure, and
4525 moving it is known to at least not worsen it.
4527 We restrict moves to only those cases where a register remains unallocated,
4528 in order to avoid interfering too much with the instruction schedule. As
4529 an exception, we may move insns which only modify their input register
4530 (typically induction variables), as this increases the freedom for our
4531 intended transformation, and does not limit the second instruction
4535 find_moveable_pseudos (void)
4538 int max_regs
= max_reg_num ();
4539 int max_uid
= get_max_uid ();
4541 int *uid_luid
= XNEWVEC (int, max_uid
);
4542 rtx_insn
**closest_uses
= XNEWVEC (rtx_insn
*, max_regs
);
4543 /* A set of registers which are live but not modified throughout a block. */
4544 bitmap_head
*bb_transp_live
= XNEWVEC (bitmap_head
,
4545 last_basic_block_for_fn (cfun
));
4546 /* A set of registers which only exist in a given basic block. */
4547 bitmap_head
*bb_local
= XNEWVEC (bitmap_head
,
4548 last_basic_block_for_fn (cfun
));
4549 /* A set of registers which are set once, in an instruction that can be
4550 moved freely downwards, but are otherwise transparent to a block. */
4551 bitmap_head
*bb_moveable_reg_sets
= XNEWVEC (bitmap_head
,
4552 last_basic_block_for_fn (cfun
));
4553 auto_bitmap live
, used
, set
, interesting
, unusable_as_input
;
4556 first_moveable_pseudo
= max_regs
;
4557 pseudo_replaced_reg
.release ();
4558 pseudo_replaced_reg
.safe_grow_cleared (max_regs
);
4561 calculate_dominance_info (CDI_DOMINATORS
);
4564 FOR_EACH_BB_FN (bb
, cfun
)
4567 bitmap transp
= bb_transp_live
+ bb
->index
;
4568 bitmap moveable
= bb_moveable_reg_sets
+ bb
->index
;
4569 bitmap local
= bb_local
+ bb
->index
;
4571 bitmap_initialize (local
, 0);
4572 bitmap_initialize (transp
, 0);
4573 bitmap_initialize (moveable
, 0);
4574 bitmap_copy (live
, df_get_live_out (bb
));
4575 bitmap_and_into (live
, df_get_live_in (bb
));
4576 bitmap_copy (transp
, live
);
4577 bitmap_clear (moveable
);
4578 bitmap_clear (live
);
4579 bitmap_clear (used
);
4581 FOR_BB_INSNS (bb
, insn
)
4582 if (NONDEBUG_INSN_P (insn
))
4584 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4587 uid_luid
[INSN_UID (insn
)] = i
++;
4589 def
= df_single_def (insn_info
);
4590 use
= df_single_use (insn_info
);
4593 && DF_REF_REGNO (use
) == DF_REF_REGNO (def
)
4594 && !bitmap_bit_p (set
, DF_REF_REGNO (use
))
4595 && rtx_moveable_p (&PATTERN (insn
), OP_IN
))
4597 unsigned regno
= DF_REF_REGNO (use
);
4598 bitmap_set_bit (moveable
, regno
);
4599 bitmap_set_bit (set
, regno
);
4600 bitmap_set_bit (used
, regno
);
4601 bitmap_clear_bit (transp
, regno
);
4604 FOR_EACH_INSN_INFO_USE (use
, insn_info
)
4606 unsigned regno
= DF_REF_REGNO (use
);
4607 bitmap_set_bit (used
, regno
);
4608 if (bitmap_clear_bit (moveable
, regno
))
4609 bitmap_clear_bit (transp
, regno
);
4612 FOR_EACH_INSN_INFO_DEF (def
, insn_info
)
4614 unsigned regno
= DF_REF_REGNO (def
);
4615 bitmap_set_bit (set
, regno
);
4616 bitmap_clear_bit (transp
, regno
);
4617 bitmap_clear_bit (moveable
, regno
);
4622 FOR_EACH_BB_FN (bb
, cfun
)
4624 bitmap local
= bb_local
+ bb
->index
;
4627 FOR_BB_INSNS (bb
, insn
)
4628 if (NONDEBUG_INSN_P (insn
))
4630 df_insn_info
*insn_info
= DF_INSN_INFO_GET (insn
);
4632 rtx closest_use
, note
;
4635 bool all_dominated
, all_local
;
4638 def
= df_single_def (insn_info
);
4639 /* There must be exactly one def in this insn. */
4640 if (!def
|| !single_set (insn
))
4642 /* This must be the only definition of the reg. We also limit
4643 which modes we deal with so that we can assume we can generate
4644 move instructions. */
4645 regno
= DF_REF_REGNO (def
);
4646 mode
= GET_MODE (DF_REF_REG (def
));
4647 if (DF_REG_DEF_COUNT (regno
) != 1
4648 || !DF_REF_INSN_INFO (def
)
4649 || HARD_REGISTER_NUM_P (regno
)
4650 || DF_REG_EQ_USE_COUNT (regno
) > 0
4651 || (!INTEGRAL_MODE_P (mode
) && !FLOAT_MODE_P (mode
)))
4653 def_insn
= DF_REF_INSN (def
);
4655 for (note
= REG_NOTES (def_insn
); note
; note
= XEXP (note
, 1))
4656 if (REG_NOTE_KIND (note
) == REG_EQUIV
&& MEM_P (XEXP (note
, 0)))
4662 fprintf (dump_file
, "Ignoring reg %d, has equiv memory\n",
4664 bitmap_set_bit (unusable_as_input
, regno
);
4668 use
= DF_REG_USE_CHAIN (regno
);
4669 all_dominated
= true;
4671 closest_use
= NULL_RTX
;
4672 for (; use
; use
= DF_REF_NEXT_REG (use
))
4675 if (!DF_REF_INSN_INFO (use
))
4677 all_dominated
= false;
4681 insn
= DF_REF_INSN (use
);
4682 if (DEBUG_INSN_P (insn
))
4684 if (BLOCK_FOR_INSN (insn
) != BLOCK_FOR_INSN (def_insn
))
4686 if (!insn_dominated_by_p (insn
, def_insn
, uid_luid
))
4687 all_dominated
= false;
4688 if (closest_use
!= insn
&& closest_use
!= const0_rtx
)
4690 if (closest_use
== NULL_RTX
)
4692 else if (insn_dominated_by_p (closest_use
, insn
, uid_luid
))
4694 else if (!insn_dominated_by_p (insn
, closest_use
, uid_luid
))
4695 closest_use
= const0_rtx
;
4701 fprintf (dump_file
, "Reg %d not all uses dominated by set\n",
4706 bitmap_set_bit (local
, regno
);
4707 if (closest_use
== const0_rtx
|| closest_use
== NULL
4708 || next_nonnote_nondebug_insn (def_insn
) == closest_use
)
4711 fprintf (dump_file
, "Reg %d uninteresting%s\n", regno
,
4712 closest_use
== const0_rtx
|| closest_use
== NULL
4713 ? " (no unique first use)" : "");
4716 if (HAVE_cc0
&& reg_referenced_p (cc0_rtx
, PATTERN (closest_use
)))
4719 fprintf (dump_file
, "Reg %d: closest user uses cc0\n",
4724 bitmap_set_bit (interesting
, regno
);
4725 /* If we get here, we know closest_use is a non-NULL insn
4726 (as opposed to const_0_rtx). */
4727 closest_uses
[regno
] = as_a
<rtx_insn
*> (closest_use
);
4729 if (dump_file
&& (all_local
|| all_dominated
))
4731 fprintf (dump_file
, "Reg %u:", regno
);
4733 fprintf (dump_file
, " local to bb %d", bb
->index
);
4735 fprintf (dump_file
, " def dominates all uses");
4736 if (closest_use
!= const0_rtx
)
4737 fprintf (dump_file
, " has unique first use");
4738 fputs ("\n", dump_file
);
4743 EXECUTE_IF_SET_IN_BITMAP (interesting
, 0, i
, bi
)
4745 df_ref def
= DF_REG_DEF_CHAIN (i
);
4746 rtx_insn
*def_insn
= DF_REF_INSN (def
);
4747 basic_block def_block
= BLOCK_FOR_INSN (def_insn
);
4748 bitmap def_bb_local
= bb_local
+ def_block
->index
;
4749 bitmap def_bb_moveable
= bb_moveable_reg_sets
+ def_block
->index
;
4750 bitmap def_bb_transp
= bb_transp_live
+ def_block
->index
;
4751 bool local_to_bb_p
= bitmap_bit_p (def_bb_local
, i
);
4752 rtx_insn
*use_insn
= closest_uses
[i
];
4755 bool all_transp
= true;
4757 if (!REG_P (DF_REF_REG (def
)))
4763 fprintf (dump_file
, "Reg %u not local to one basic block\n",
4767 if (reg_equiv_init (i
) != NULL_RTX
)
4770 fprintf (dump_file
, "Ignoring reg %u with equiv init insn\n",
4774 if (!rtx_moveable_p (&PATTERN (def_insn
), OP_IN
))
4777 fprintf (dump_file
, "Found def insn %d for %d to be not moveable\n",
4778 INSN_UID (def_insn
), i
);
4782 fprintf (dump_file
, "Examining insn %d, def for %d\n",
4783 INSN_UID (def_insn
), i
);
4784 FOR_EACH_INSN_USE (use
, def_insn
)
4786 unsigned regno
= DF_REF_REGNO (use
);
4787 if (bitmap_bit_p (unusable_as_input
, regno
))
4791 fprintf (dump_file
, " found unusable input reg %u.\n", regno
);
4794 if (!bitmap_bit_p (def_bb_transp
, regno
))
4796 if (bitmap_bit_p (def_bb_moveable
, regno
)
4797 && !control_flow_insn_p (use_insn
)
4798 && (!HAVE_cc0
|| !sets_cc0_p (use_insn
)))
4800 if (modified_between_p (DF_REF_REG (use
), def_insn
, use_insn
))
4802 rtx_insn
*x
= NEXT_INSN (def_insn
);
4803 while (!modified_in_p (DF_REF_REG (use
), x
))
4805 gcc_assert (x
!= use_insn
);
4809 fprintf (dump_file
, " input reg %u modified but insn %d moveable\n",
4810 regno
, INSN_UID (x
));
4811 emit_insn_after (PATTERN (x
), use_insn
);
4812 set_insn_deleted (x
);
4817 fprintf (dump_file
, " input reg %u modified between def and use\n",
4828 if (!dbg_cnt (ira_move
))
4831 fprintf (dump_file
, " all ok%s\n", all_transp
? " and transp" : "");
4835 rtx def_reg
= DF_REF_REG (def
);
4836 rtx newreg
= ira_create_new_reg (def_reg
);
4837 if (validate_change (def_insn
, DF_REF_REAL_LOC (def
), newreg
, 0))
4839 unsigned nregno
= REGNO (newreg
);
4840 emit_insn_before (gen_move_insn (def_reg
, newreg
), use_insn
);
4842 pseudo_replaced_reg
[nregno
] = def_reg
;
4847 FOR_EACH_BB_FN (bb
, cfun
)
4849 bitmap_clear (bb_local
+ bb
->index
);
4850 bitmap_clear (bb_transp_live
+ bb
->index
);
4851 bitmap_clear (bb_moveable_reg_sets
+ bb
->index
);
4854 free (closest_uses
);
4856 free (bb_transp_live
);
4857 free (bb_moveable_reg_sets
);
4859 last_moveable_pseudo
= max_reg_num ();
4861 fix_reg_equiv_init ();
4863 regstat_free_n_sets_and_refs ();
4865 regstat_init_n_sets_and_refs ();
4866 regstat_compute_ri ();
4867 free_dominance_info (CDI_DOMINATORS
);
4870 /* If SET pattern SET is an assignment from a hard register to a pseudo which
4871 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return
4872 the destination. Otherwise return NULL. */
4875 interesting_dest_for_shprep_1 (rtx set
, basic_block call_dom
)
4877 rtx src
= SET_SRC (set
);
4878 rtx dest
= SET_DEST (set
);
4879 if (!REG_P (src
) || !HARD_REGISTER_P (src
)
4880 || !REG_P (dest
) || HARD_REGISTER_P (dest
)
4881 || (call_dom
&& !bitmap_bit_p (df_get_live_in (call_dom
), REGNO (dest
))))
4886 /* If insn is interesting for parameter range-splitting shrink-wrapping
4887 preparation, i.e. it is a single set from a hard register to a pseudo, which
4888 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a
4889 parallel statement with only one such statement, return the destination.
4890 Otherwise return NULL. */
4893 interesting_dest_for_shprep (rtx_insn
*insn
, basic_block call_dom
)
4897 rtx pat
= PATTERN (insn
);
4898 if (GET_CODE (pat
) == SET
)
4899 return interesting_dest_for_shprep_1 (pat
, call_dom
);
4901 if (GET_CODE (pat
) != PARALLEL
)
4904 for (int i
= 0; i
< XVECLEN (pat
, 0); i
++)
4906 rtx sub
= XVECEXP (pat
, 0, i
);
4907 if (GET_CODE (sub
) == USE
4908 || GET_CODE (sub
) == CLOBBER
4909 || GET_CODE (sub
) == CLOBBER_HIGH
)
4911 if (GET_CODE (sub
) != SET
4912 || side_effects_p (sub
))
4914 rtx dest
= interesting_dest_for_shprep_1 (sub
, call_dom
);
4923 /* Split live ranges of pseudos that are loaded from hard registers in the
4924 first BB in a BB that dominates all non-sibling call if such a BB can be
4925 found and is not in a loop. Return true if the function has made any
4929 split_live_ranges_for_shrink_wrap (void)
4931 basic_block bb
, call_dom
= NULL
;
4932 basic_block first
= single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun
));
4933 rtx_insn
*insn
, *last_interesting_insn
= NULL
;
4934 auto_bitmap need_new
, reachable
;
4935 vec
<basic_block
> queue
;
4937 if (!SHRINK_WRAPPING_ENABLED
)
4940 queue
.create (n_basic_blocks_for_fn (cfun
));
4942 FOR_EACH_BB_FN (bb
, cfun
)
4943 FOR_BB_INSNS (bb
, insn
)
4944 if (CALL_P (insn
) && !SIBLING_CALL_P (insn
))
4952 bitmap_set_bit (need_new
, bb
->index
);
4953 bitmap_set_bit (reachable
, bb
->index
);
4954 queue
.quick_push (bb
);
4958 if (queue
.is_empty ())
4964 while (!queue
.is_empty ())
4970 FOR_EACH_EDGE (e
, ei
, bb
->succs
)
4971 if (e
->dest
!= EXIT_BLOCK_PTR_FOR_FN (cfun
)
4972 && bitmap_set_bit (reachable
, e
->dest
->index
))
4973 queue
.quick_push (e
->dest
);
4977 FOR_BB_INSNS (first
, insn
)
4979 rtx dest
= interesting_dest_for_shprep (insn
, NULL
);
4983 if (DF_REG_DEF_COUNT (REGNO (dest
)) > 1)
4986 for (df_ref use
= DF_REG_USE_CHAIN (REGNO(dest
));
4988 use
= DF_REF_NEXT_REG (use
))
4990 int ubbi
= DF_REF_BB (use
)->index
;
4991 if (bitmap_bit_p (reachable
, ubbi
))
4992 bitmap_set_bit (need_new
, ubbi
);
4994 last_interesting_insn
= insn
;
4997 if (!last_interesting_insn
)
5000 call_dom
= nearest_common_dominator_for_set (CDI_DOMINATORS
, need_new
);
5001 if (call_dom
== first
)
5004 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
5005 while (bb_loop_depth (call_dom
) > 0)
5006 call_dom
= get_immediate_dominator (CDI_DOMINATORS
, call_dom
);
5007 loop_optimizer_finalize ();
5009 if (call_dom
== first
)
5012 calculate_dominance_info (CDI_POST_DOMINATORS
);
5013 if (dominated_by_p (CDI_POST_DOMINATORS
, first
, call_dom
))
5015 free_dominance_info (CDI_POST_DOMINATORS
);
5018 free_dominance_info (CDI_POST_DOMINATORS
);
5021 fprintf (dump_file
, "Will split live ranges of parameters at BB %i\n",
5025 FOR_BB_INSNS (first
, insn
)
5027 rtx dest
= interesting_dest_for_shprep (insn
, call_dom
);
5028 if (!dest
|| dest
== pic_offset_table_rtx
)
5031 bool need_newreg
= false;
5033 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
5035 rtx_insn
*uin
= DF_REF_INSN (use
);
5036 next
= DF_REF_NEXT_REG (use
);
5038 if (DEBUG_INSN_P (uin
))
5041 basic_block ubb
= BLOCK_FOR_INSN (uin
);
5043 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
5052 rtx newreg
= ira_create_new_reg (dest
);
5054 for (use
= DF_REG_USE_CHAIN (REGNO (dest
)); use
; use
= next
)
5056 rtx_insn
*uin
= DF_REF_INSN (use
);
5057 next
= DF_REF_NEXT_REG (use
);
5059 basic_block ubb
= BLOCK_FOR_INSN (uin
);
5061 || dominated_by_p (CDI_DOMINATORS
, ubb
, call_dom
))
5062 validate_change (uin
, DF_REF_REAL_LOC (use
), newreg
, true);
5065 rtx_insn
*new_move
= gen_move_insn (newreg
, dest
);
5066 emit_insn_after (new_move
, bb_note (call_dom
));
5069 fprintf (dump_file
, "Split live-range of register ");
5070 print_rtl_single (dump_file
, dest
);
5075 if (insn
== last_interesting_insn
)
5078 apply_change_group ();
5082 /* Perform the second half of the transformation started in
5083 find_moveable_pseudos. We look for instances where the newly introduced
5084 pseudo remains unallocated, and remove it by moving the definition to
5085 just before its use, replacing the move instruction generated by
5086 find_moveable_pseudos. */
5088 move_unallocated_pseudos (void)
5091 for (i
= first_moveable_pseudo
; i
< last_moveable_pseudo
; i
++)
5092 if (reg_renumber
[i
] < 0)
5094 int idx
= i
- first_moveable_pseudo
;
5095 rtx other_reg
= pseudo_replaced_reg
[idx
];
5096 rtx_insn
*def_insn
= DF_REF_INSN (DF_REG_DEF_CHAIN (i
));
5097 /* The use must follow all definitions of OTHER_REG, so we can
5098 insert the new definition immediately after any of them. */
5099 df_ref other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
));
5100 rtx_insn
*move_insn
= DF_REF_INSN (other_def
);
5101 rtx_insn
*newinsn
= emit_insn_after (PATTERN (def_insn
), move_insn
);
5106 fprintf (dump_file
, "moving def of %d (insn %d now) ",
5107 REGNO (other_reg
), INSN_UID (def_insn
));
5109 delete_insn (move_insn
);
5110 while ((other_def
= DF_REG_DEF_CHAIN (REGNO (other_reg
))))
5111 delete_insn (DF_REF_INSN (other_def
));
5112 delete_insn (def_insn
);
5114 set
= single_set (newinsn
);
5115 success
= validate_change (newinsn
, &SET_DEST (set
), other_reg
, 0);
5116 gcc_assert (success
);
5118 fprintf (dump_file
, " %d) rather than keep unallocated replacement %d\n",
5119 INSN_UID (newinsn
), i
);
5120 SET_REG_N_REFS (i
, 0);
5124 /* If the backend knows where to allocate pseudos for hard
5125 register initial values, register these allocations now. */
5127 allocate_initial_values (void)
5129 if (targetm
.allocate_initial_value
)
5134 for (i
= 0; HARD_REGISTER_NUM_P (i
); i
++)
5136 if (! initial_value_entry (i
, &hreg
, &preg
))
5139 x
= targetm
.allocate_initial_value (hreg
);
5140 regno
= REGNO (preg
);
5141 if (x
&& REG_N_SETS (regno
) <= 1)
5144 reg_equiv_memory_loc (regno
) = x
;
5150 gcc_assert (REG_P (x
));
5151 new_regno
= REGNO (x
);
5152 reg_renumber
[regno
] = new_regno
;
5153 /* Poke the regno right into regno_reg_rtx so that even
5154 fixed regs are accepted. */
5155 SET_REGNO (preg
, new_regno
);
5156 /* Update global register liveness information. */
5157 FOR_EACH_BB_FN (bb
, cfun
)
5159 if (REGNO_REG_SET_P (df_get_live_in (bb
), regno
))
5160 SET_REGNO_REG_SET (df_get_live_in (bb
), new_regno
);
5161 if (REGNO_REG_SET_P (df_get_live_out (bb
), regno
))
5162 SET_REGNO_REG_SET (df_get_live_out (bb
), new_regno
);
5168 gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER
,
5174 /* True when we use LRA instead of reload pass for the current
5178 /* True if we have allocno conflicts. It is false for non-optimized
5179 mode or when the conflict table is too big. */
5180 bool ira_conflicts_p
;
5182 /* Saved between IRA and reload. */
5183 static int saved_flag_ira_share_spill_slots
;
5185 /* This is the main entry of IRA. */
5190 int ira_max_point_before_emit
;
5191 bool saved_flag_caller_saves
= flag_caller_saves
;
5192 enum ira_region saved_flag_ira_region
= flag_ira_region
;
5194 int num_used_regs
= 0;
5198 /* Determine if the current function is a leaf before running IRA
5199 since this can impact optimizations done by the prologue and
5200 epilogue thus changing register elimination offsets.
5201 Other target callbacks may use crtl->is_leaf too, including
5202 SHRINK_WRAPPING_ENABLED, so initialize as early as possible. */
5203 crtl
->is_leaf
= leaf_function_p ();
5205 /* Perform target specific PIC register initialization. */
5206 targetm
.init_pic_reg ();
5208 ira_conflicts_p
= optimize
> 0;
5210 /* Determine the number of pseudos actually requiring coloring. */
5211 for (i
= FIRST_PSEUDO_REGISTER
; i
< DF_REG_SIZE (df
); i
++)
5212 num_used_regs
+= !!(DF_REG_USE_COUNT (i
) + DF_REG_DEF_COUNT (i
));
5214 /* If there are too many pseudos and/or basic blocks (e.g. 10K
5215 pseudos and 10K blocks or 100K pseudos and 1K blocks), we will
5216 use simplified and faster algorithms in LRA. */
5219 && num_used_regs
>= (1 << 26) / last_basic_block_for_fn (cfun
));
5223 /* It permits to skip live range splitting in LRA. */
5224 flag_caller_saves
= false;
5225 /* There is no sense to do regional allocation when we use
5227 flag_ira_region
= IRA_REGION_ONE
;
5228 ira_conflicts_p
= false;
5231 #ifndef IRA_NO_OBSTACK
5232 gcc_obstack_init (&ira_obstack
);
5234 bitmap_obstack_initialize (&ira_bitmap_obstack
);
5236 /* LRA uses its own infrastructure to handle caller save registers. */
5237 if (flag_caller_saves
&& !ira_use_lra_p
)
5238 init_caller_save ();
5240 if (flag_ira_verbose
< 10)
5242 internal_flag_ira_verbose
= flag_ira_verbose
;
5247 internal_flag_ira_verbose
= flag_ira_verbose
- 10;
5248 ira_dump_file
= stderr
;
5251 setup_prohibited_mode_move_regs ();
5252 decrease_live_ranges_number ();
5253 df_note_add_problem ();
5255 /* DF_LIVE can't be used in the register allocator, too many other
5256 parts of the compiler depend on using the "classic" liveness
5257 interpretation of the DF_LR problem. See PR38711.
5258 Remove the problem, so that we don't spend time updating it in
5259 any of the df_analyze() calls during IRA/LRA. */
5261 df_remove_problem (df_live
);
5262 gcc_checking_assert (df_live
== NULL
);
5265 df
->changeable_flags
|= DF_VERIFY_SCHEDULED
;
5270 if (ira_conflicts_p
)
5272 calculate_dominance_info (CDI_DOMINATORS
);
5274 if (split_live_ranges_for_shrink_wrap ())
5277 free_dominance_info (CDI_DOMINATORS
);
5280 df_clear_flags (DF_NO_INSN_RESCAN
);
5282 indirect_jump_optimize ();
5283 if (delete_trivially_dead_insns (get_insns (), max_reg_num ()))
5286 regstat_init_n_sets_and_refs ();
5287 regstat_compute_ri ();
5289 /* If we are not optimizing, then this is the only place before
5290 register allocation where dataflow is done. And that is needed
5291 to generate these warnings. */
5293 generate_setjmp_warnings ();
5295 if (resize_reg_info () && flag_ira_loop_pressure
)
5296 ira_set_pseudo_classes (true, ira_dump_file
);
5298 init_alias_analysis ();
5299 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
5300 reg_equiv
= XCNEWVEC (struct equivalence
, max_reg_num ());
5301 update_equiv_regs ();
5303 /* Don't move insns if live range shrinkage or register
5304 pressure-sensitive scheduling were done because it will not
5305 improve allocation but likely worsen insn scheduling. */
5307 && !flag_live_range_shrinkage
5308 && !(flag_sched_pressure
&& flag_schedule_insns
))
5309 combine_and_move_insns ();
5311 /* Gather additional equivalences with memory. */
5313 add_store_equivs ();
5315 loop_optimizer_finalize ();
5316 free_dominance_info (CDI_DOMINATORS
);
5317 end_alias_analysis ();
5322 setup_reg_equiv_init ();
5324 allocated_reg_info_size
= max_reg_num ();
5326 /* It is not worth to do such improvement when we use a simple
5327 allocation because of -O0 usage or because the function is too
5329 if (ira_conflicts_p
)
5330 find_moveable_pseudos ();
5332 max_regno_before_ira
= max_reg_num ();
5333 ira_setup_eliminable_regset ();
5335 ira_overall_cost
= ira_reg_cost
= ira_mem_cost
= 0;
5336 ira_load_cost
= ira_store_cost
= ira_shuffle_cost
= 0;
5337 ira_move_loops_num
= ira_additional_jumps_num
= 0;
5339 ira_assert (current_loops
== NULL
);
5340 if (flag_ira_region
== IRA_REGION_ALL
|| flag_ira_region
== IRA_REGION_MIXED
)
5341 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
| LOOPS_HAVE_RECORDED_EXITS
);
5343 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5344 fprintf (ira_dump_file
, "Building IRA IR\n");
5345 loops_p
= ira_build ();
5347 ira_assert (ira_conflicts_p
|| !loops_p
);
5349 saved_flag_ira_share_spill_slots
= flag_ira_share_spill_slots
;
5350 if (too_high_register_pressure_p () || cfun
->calls_setjmp
)
5351 /* It is just wasting compiler's time to pack spilled pseudos into
5352 stack slots in this case -- prohibit it. We also do this if
5353 there is setjmp call because a variable not modified between
5354 setjmp and longjmp the compiler is required to preserve its
5355 value and sharing slots does not guarantee it. */
5356 flag_ira_share_spill_slots
= FALSE
;
5360 ira_max_point_before_emit
= ira_max_point
;
5362 ira_initiate_emit_data ();
5366 max_regno
= max_reg_num ();
5367 if (ira_conflicts_p
)
5371 if (! ira_use_lra_p
)
5372 ira_initiate_assign ();
5381 ira_allocno_iterator ai
;
5383 FOR_EACH_ALLOCNO (a
, ai
)
5385 int old_regno
= ALLOCNO_REGNO (a
);
5386 int new_regno
= REGNO (ALLOCNO_EMIT_DATA (a
)->reg
);
5388 ALLOCNO_REGNO (a
) = new_regno
;
5390 if (old_regno
!= new_regno
)
5391 setup_reg_classes (new_regno
, reg_preferred_class (old_regno
),
5392 reg_alternate_class (old_regno
),
5393 reg_allocno_class (old_regno
));
5398 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
)
5399 fprintf (ira_dump_file
, "Flattening IR\n");
5400 ira_flattening (max_regno_before_ira
, ira_max_point_before_emit
);
5402 /* New insns were generated: add notes and recalculate live
5406 /* ??? Rebuild the loop tree, but why? Does the loop tree
5407 change if new insns were generated? Can that be handled
5408 by updating the loop tree incrementally? */
5409 loop_optimizer_finalize ();
5410 free_dominance_info (CDI_DOMINATORS
);
5411 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
5412 | LOOPS_HAVE_RECORDED_EXITS
);
5414 if (! ira_use_lra_p
)
5416 setup_allocno_assignment_flags ();
5417 ira_initiate_assign ();
5418 ira_reassign_conflict_allocnos (max_regno
);
5423 ira_finish_emit_data ();
5425 setup_reg_renumber ();
5427 calculate_allocation_cost ();
5429 #ifdef ENABLE_IRA_CHECKING
5430 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5431 /* Opposite to reload pass, LRA does not use any conflict info
5432 from IRA. We don't rebuild conflict info for LRA (through
5433 ira_flattening call) and cannot use the check here. We could
5434 rebuild this info for LRA in the check mode but there is a risk
5435 that code generated with the check and without it will be a bit
5436 different. Calling ira_flattening in any mode would be a
5437 wasting CPU time. So do not check the allocation for LRA. */
5438 check_allocation ();
5441 if (max_regno
!= max_regno_before_ira
)
5443 regstat_free_n_sets_and_refs ();
5445 regstat_init_n_sets_and_refs ();
5446 regstat_compute_ri ();
5449 overall_cost_before
= ira_overall_cost
;
5450 if (! ira_conflicts_p
)
5454 fix_reg_equiv_init ();
5456 #ifdef ENABLE_IRA_CHECKING
5457 print_redundant_copies ();
5459 if (! ira_use_lra_p
)
5461 ira_spilled_reg_stack_slots_num
= 0;
5462 ira_spilled_reg_stack_slots
5463 = ((class ira_spilled_reg_stack_slot
*)
5464 ira_allocate (max_regno
5465 * sizeof (class ira_spilled_reg_stack_slot
)));
5466 memset ((void *)ira_spilled_reg_stack_slots
, 0,
5467 max_regno
* sizeof (class ira_spilled_reg_stack_slot
));
5470 allocate_initial_values ();
5472 /* See comment for find_moveable_pseudos call. */
5473 if (ira_conflicts_p
)
5474 move_unallocated_pseudos ();
5476 /* Restore original values. */
5479 flag_caller_saves
= saved_flag_caller_saves
;
5480 flag_ira_region
= saved_flag_ira_region
;
5489 unsigned pic_offset_table_regno
= INVALID_REGNUM
;
5491 if (flag_ira_verbose
< 10)
5492 ira_dump_file
= dump_file
;
5494 /* If pic_offset_table_rtx is a pseudo register, then keep it so
5495 after reload to avoid possible wrong usages of hard reg assigned
5497 if (pic_offset_table_rtx
5498 && REGNO (pic_offset_table_rtx
) >= FIRST_PSEUDO_REGISTER
)
5499 pic_offset_table_regno
= REGNO (pic_offset_table_rtx
);
5501 timevar_push (TV_RELOAD
);
5504 if (current_loops
!= NULL
)
5506 loop_optimizer_finalize ();
5507 free_dominance_info (CDI_DOMINATORS
);
5509 FOR_ALL_BB_FN (bb
, cfun
)
5510 bb
->loop_father
= NULL
;
5511 current_loops
= NULL
;
5515 lra (ira_dump_file
);
5516 /* ???!!! Move it before lra () when we use ira_reg_equiv in
5518 vec_free (reg_equivs
);
5524 df_set_flags (DF_NO_INSN_RESCAN
);
5525 build_insn_chain ();
5527 need_dce
= reload (get_insns (), ira_conflicts_p
);
5530 timevar_pop (TV_RELOAD
);
5532 timevar_push (TV_IRA
);
5534 if (ira_conflicts_p
&& ! ira_use_lra_p
)
5536 ira_free (ira_spilled_reg_stack_slots
);
5537 ira_finish_assign ();
5540 if (internal_flag_ira_verbose
> 0 && ira_dump_file
!= NULL
5541 && overall_cost_before
!= ira_overall_cost
)
5542 fprintf (ira_dump_file
, "+++Overall after reload %" PRId64
"\n",
5545 flag_ira_share_spill_slots
= saved_flag_ira_share_spill_slots
;
5547 if (! ira_use_lra_p
)
5550 if (current_loops
!= NULL
)
5552 loop_optimizer_finalize ();
5553 free_dominance_info (CDI_DOMINATORS
);
5555 FOR_ALL_BB_FN (bb
, cfun
)
5556 bb
->loop_father
= NULL
;
5557 current_loops
= NULL
;
5560 regstat_free_n_sets_and_refs ();
5564 cleanup_cfg (CLEANUP_EXPENSIVE
);
5566 finish_reg_equiv ();
5568 bitmap_obstack_release (&ira_bitmap_obstack
);
5569 #ifndef IRA_NO_OBSTACK
5570 obstack_free (&ira_obstack
, NULL
);
5573 /* The code after the reload has changed so much that at this point
5574 we might as well just rescan everything. Note that
5575 df_rescan_all_insns is not going to help here because it does not
5576 touch the artificial uses and defs. */
5577 df_finish_pass (true);
5578 df_scan_alloc (NULL
);
5583 df_live_add_problem ();
5584 df_live_set_all_dirty ();
5590 if (need_dce
&& optimize
)
5593 /* Diagnose uses of the hard frame pointer when it is used as a global
5594 register. Often we can get away with letting the user appropriate
5595 the frame pointer, but we should let them know when code generation
5596 makes that impossible. */
5597 if (global_regs
[HARD_FRAME_POINTER_REGNUM
] && frame_pointer_needed
)
5599 tree decl
= global_regs_decl
[HARD_FRAME_POINTER_REGNUM
];
5600 error_at (DECL_SOURCE_LOCATION (current_function_decl
),
5601 "frame pointer required, but reserved");
5602 inform (DECL_SOURCE_LOCATION (decl
), "for %qD", decl
);
5605 /* If we are doing generic stack checking, give a warning if this
5606 function's frame size is larger than we expect. */
5607 if (flag_stack_check
== GENERIC_STACK_CHECK
)
5609 poly_int64 size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
5611 for (int i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
5612 if (df_regs_ever_live_p (i
) && !fixed_regs
[i
] && call_used_regs
[i
])
5613 size
+= UNITS_PER_WORD
;
5615 if (constant_lower_bound (size
) > STACK_CHECK_MAX_FRAME_SIZE
)
5616 warning (0, "frame size too large for reliable stack checking");
5619 if (pic_offset_table_regno
!= INVALID_REGNUM
)
5620 pic_offset_table_rtx
= gen_rtx_REG (Pmode
, pic_offset_table_regno
);
5622 timevar_pop (TV_IRA
);
5625 /* Run the integrated register allocator. */
5629 const pass_data pass_data_ira
=
5631 RTL_PASS
, /* type */
5633 OPTGROUP_NONE
, /* optinfo_flags */
5635 0, /* properties_required */
5636 0, /* properties_provided */
5637 0, /* properties_destroyed */
5638 0, /* todo_flags_start */
5639 TODO_do_not_ggc_collect
, /* todo_flags_finish */
5642 class pass_ira
: public rtl_opt_pass
5645 pass_ira (gcc::context
*ctxt
)
5646 : rtl_opt_pass (pass_data_ira
, ctxt
)
5649 /* opt_pass methods: */
5650 virtual bool gate (function
*)
5652 return !targetm
.no_register_allocation
;
5654 virtual unsigned int execute (function
*)
5660 }; // class pass_ira
5665 make_pass_ira (gcc::context
*ctxt
)
5667 return new pass_ira (ctxt
);
5672 const pass_data pass_data_reload
=
5674 RTL_PASS
, /* type */
5675 "reload", /* name */
5676 OPTGROUP_NONE
, /* optinfo_flags */
5677 TV_RELOAD
, /* tv_id */
5678 0, /* properties_required */
5679 0, /* properties_provided */
5680 0, /* properties_destroyed */
5681 0, /* todo_flags_start */
5682 0, /* todo_flags_finish */
5685 class pass_reload
: public rtl_opt_pass
5688 pass_reload (gcc::context
*ctxt
)
5689 : rtl_opt_pass (pass_data_reload
, ctxt
)
5692 /* opt_pass methods: */
5693 virtual bool gate (function
*)
5695 return !targetm
.no_register_allocation
;
5697 virtual unsigned int execute (function
*)
5703 }; // class pass_reload
5708 make_pass_reload (gcc::context
*ctxt
)
5710 return new pass_reload (ctxt
);