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[thirdparty/gcc.git] / gcc / longlong.h
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991,92,94,95,96,97,98,99, 2000 Free Software Foundation, Inc.
3
4 This definition file is free software; you can redistribute it
5 and/or modify it under the terms of the GNU General Public
6 License as published by the Free Software Foundation; either
7 version 2, or (at your option) any later version.
8
9 This definition file is distributed in the hope that it will be
10 useful, but WITHOUT ANY WARRANTY; without even the implied
11 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 See the GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program; if not, write to the Free Software
16 Foundation, Inc., 59 Temple Place - Suite 330,
17 Boston, MA 02111-1307, USA. */
18
19 /* You have to define the following before including this file:
20
21 UWtype -- An unsigned type, default type for operations (typically a "word")
22 UHWtype -- An unsigned type, at least half the size of UWtype.
23 UDWtype -- An unsigned type, at least twice as large a UWtype
24 W_TYPE_SIZE -- size in bits of UWtype
25
26 UQItype -- Unsigned 8 bit type.
27 SItype, USItype -- Signed and unsigned 32 bit types.
28 DItype, UDItype -- Signed and unsigned 64 bit types.
29
30 On a 32 bit machine UWtype should typically be USItype;
31 on a 64 bit machine, UWtype should typically be UDItype.
32 */
33
34 #define __BITS4 (W_TYPE_SIZE / 4)
35 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
36 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
37 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
38
39 #ifndef W_TYPE_SIZE
40 #define W_TYPE_SIZE 32
41 #define UWtype USItype
42 #define UHWtype USItype
43 #define UDWtype UDItype
44 #endif
45
46 /* Define auxiliary asm macros.
47
48 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
49 UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
50 word product in HIGH_PROD and LOW_PROD.
51
52 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
53 UDWtype product. This is just a variant of umul_ppmm.
54
55 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
56 denominator) divides a UDWtype, composed by the UWtype integers
57 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
58 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
59 than DENOMINATOR for correct operation. If, in addition, the most
60 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
61 UDIV_NEEDS_NORMALIZATION is defined to 1.
62
63 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
64 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
65 is rounded towards 0.
66
67 5) count_leading_zeros(count, x) counts the number of zero-bits from the
68 msb to the first non-zero bit in the UWtype X. This is the number of
69 steps X needs to be shifted left to set the msb. Undefined for X == 0,
70 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
71
72 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
73 from the least significant end.
74
75 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
76 high_addend_2, low_addend_2) adds two UWtype integers, composed by
77 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
78 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
79 (i.e. carry out) is not stored anywhere, and is lost.
80
81 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
82 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
83 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
84 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
85 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
86 and is lost.
87
88 If any of these macros are left undefined for a particular CPU,
89 C macros are used. */
90
91 /* The CPUs come in alphabetical order below.
92
93 Please add support for more CPUs here, or improve the current support
94 for the CPUs below!
95 (E.g. WE32100, IBM360.) */
96
97 #if defined (__GNUC__) && !defined (NO_ASM)
98
99 /* We sometimes need to clobber "cc" with gcc2, but that would not be
100 understood by gcc1. Use cpp to avoid major code duplication. */
101 #if __GNUC__ < 2
102 #define __CLOBBER_CC
103 #define __AND_CLOBBER_CC
104 #else /* __GNUC__ >= 2 */
105 #define __CLOBBER_CC : "cc"
106 #define __AND_CLOBBER_CC , "cc"
107 #endif /* __GNUC__ < 2 */
108
109 #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
110 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
111 __asm__ ("add %1,%4,%5
112 addc %0,%2,%3" \
113 : "=r" ((USItype) (sh)), \
114 "=&r" ((USItype) (sl)) \
115 : "%r" ((USItype) (ah)), \
116 "rI" ((USItype) (bh)), \
117 "%r" ((USItype) (al)), \
118 "rI" ((USItype) (bl)))
119 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
120 __asm__ ("sub %1,%4,%5
121 subc %0,%2,%3" \
122 : "=r" ((USItype) (sh)), \
123 "=&r" ((USItype) (sl)) \
124 : "r" ((USItype) (ah)), \
125 "rI" ((USItype) (bh)), \
126 "r" ((USItype) (al)), \
127 "rI" ((USItype) (bl)))
128 #define umul_ppmm(xh, xl, m0, m1) \
129 do { \
130 USItype __m0 = (m0), __m1 = (m1); \
131 __asm__ ("multiplu %0,%1,%2" \
132 : "=r" ((USItype) (xl)) \
133 : "r" (__m0), \
134 "r" (__m1)); \
135 __asm__ ("multmu %0,%1,%2" \
136 : "=r" ((USItype) (xh)) \
137 : "r" (__m0), \
138 "r" (__m1)); \
139 } while (0)
140 #define udiv_qrnnd(q, r, n1, n0, d) \
141 __asm__ ("dividu %0,%3,%4" \
142 : "=r" ((USItype) (q)), \
143 "=q" ((USItype) (r)) \
144 : "1" ((USItype) (n1)), \
145 "r" ((USItype) (n0)), \
146 "r" ((USItype) (d)))
147 #define count_leading_zeros(count, x) \
148 __asm__ ("clz %0,%1" \
149 : "=r" ((USItype) (count)) \
150 : "r" ((USItype) (x)))
151 #define COUNT_LEADING_ZEROS_0 32
152 #endif /* __a29k__ */
153
154 #if defined (__alpha) && W_TYPE_SIZE == 64
155 #define umul_ppmm(ph, pl, m0, m1) \
156 do { \
157 UDItype __m0 = (m0), __m1 = (m1); \
158 __asm__ ("umulh %r1,%2,%0" \
159 : "=r" ((UDItype) ph) \
160 : "%rJ" (__m0), \
161 "rI" (__m1)); \
162 (pl) = __m0 * __m1; \
163 } while (0)
164 #define UMUL_TIME 46
165 #ifndef LONGLONG_STANDALONE
166 #define udiv_qrnnd(q, r, n1, n0, d) \
167 do { UDItype __r; \
168 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
169 (r) = __r; \
170 } while (0)
171 extern UDItype __udiv_qrnnd PARAMS ((UDItype *, UDItype, UDItype, UDItype));
172 #define UDIV_TIME 220
173 #endif /* LONGLONG_STANDALONE */
174 #endif /* __alpha */
175
176 #if defined (__arc__) && W_TYPE_SIZE == 32
177 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
178 __asm__ ("add.f %1, %4, %5
179 adc %0, %2, %3" \
180 : "=r" ((USItype) (sh)), \
181 "=&r" ((USItype) (sl)) \
182 : "%r" ((USItype) (ah)), \
183 "rIJ" ((USItype) (bh)), \
184 "%r" ((USItype) (al)), \
185 "rIJ" ((USItype) (bl)))
186 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
187 __asm__ ("sub.f %1, %4, %5
188 sbc %0, %2, %3" \
189 : "=r" ((USItype) (sh)), \
190 "=&r" ((USItype) (sl)) \
191 : "r" ((USItype) (ah)), \
192 "rIJ" ((USItype) (bh)), \
193 "r" ((USItype) (al)), \
194 "rIJ" ((USItype) (bl)))
195 /* Call libgcc1 routine. */
196 #define umul_ppmm(w1, w0, u, v) \
197 do { \
198 DWunion __w; \
199 __w.ll = __umulsidi3 (u, v); \
200 w1 = __w.s.high; \
201 w0 = __w.s.low; \
202 } while (0)
203 #define __umulsidi3 __umulsidi3
204 UDItype __umulsidi3 (USItype, USItype);
205 #endif
206
207 #if defined (__arm__) && W_TYPE_SIZE == 32
208 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
209 __asm__ ("adds %1, %4, %5
210 adc %0, %2, %3" \
211 : "=r" ((USItype) (sh)), \
212 "=&r" ((USItype) (sl)) \
213 : "%r" ((USItype) (ah)), \
214 "rI" ((USItype) (bh)), \
215 "%r" ((USItype) (al)), \
216 "rI" ((USItype) (bl)))
217 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
218 __asm__ ("subs %1, %4, %5
219 sbc %0, %2, %3" \
220 : "=r" ((USItype) (sh)), \
221 "=&r" ((USItype) (sl)) \
222 : "r" ((USItype) (ah)), \
223 "rI" ((USItype) (bh)), \
224 "r" ((USItype) (al)), \
225 "rI" ((USItype) (bl)))
226 #define umul_ppmm(xh, xl, a, b) \
227 {register USItype __t0, __t1, __t2; \
228 __asm__ ("%@ Inlined umul_ppmm
229 mov %2, %5, lsr #16
230 mov %0, %6, lsr #16
231 bic %3, %5, %2, lsl #16
232 bic %4, %6, %0, lsl #16
233 mul %1, %3, %4
234 mul %4, %2, %4
235 mul %3, %0, %3
236 mul %0, %2, %0
237 adds %3, %4, %3
238 addcs %0, %0, #65536
239 adds %1, %1, %3, lsl #16
240 adc %0, %0, %3, lsr #16" \
241 : "=&r" ((USItype) (xh)), \
242 "=r" ((USItype) (xl)), \
243 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
244 : "r" ((USItype) (a)), \
245 "r" ((USItype) (b)));}
246 #define UMUL_TIME 20
247 #define UDIV_TIME 100
248 #endif /* __arm__ */
249
250 #if defined (__clipper__) && W_TYPE_SIZE == 32
251 #define umul_ppmm(w1, w0, u, v) \
252 ({union {UDItype __ll; \
253 struct {USItype __l, __h;} __i; \
254 } __xx; \
255 __asm__ ("mulwux %2,%0" \
256 : "=r" (__xx.__ll) \
257 : "%0" ((USItype) (u)), \
258 "r" ((USItype) (v))); \
259 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
260 #define smul_ppmm(w1, w0, u, v) \
261 ({union {DItype __ll; \
262 struct {SItype __l, __h;} __i; \
263 } __xx; \
264 __asm__ ("mulwx %2,%0" \
265 : "=r" (__xx.__ll) \
266 : "%0" ((SItype) (u)), \
267 "r" ((SItype) (v))); \
268 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
269 #define __umulsidi3(u, v) \
270 ({UDItype __w; \
271 __asm__ ("mulwux %2,%0" \
272 : "=r" (__w) \
273 : "%0" ((USItype) (u)), \
274 "r" ((USItype) (v))); \
275 __w; })
276 #endif /* __clipper__ */
277
278 #if defined (__gmicro__) && W_TYPE_SIZE == 32
279 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
280 __asm__ ("add.w %5,%1
281 addx %3,%0" \
282 : "=g" ((USItype) (sh)), \
283 "=&g" ((USItype) (sl)) \
284 : "%0" ((USItype) (ah)), \
285 "g" ((USItype) (bh)), \
286 "%1" ((USItype) (al)), \
287 "g" ((USItype) (bl)))
288 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
289 __asm__ ("sub.w %5,%1
290 subx %3,%0" \
291 : "=g" ((USItype) (sh)), \
292 "=&g" ((USItype) (sl)) \
293 : "0" ((USItype) (ah)), \
294 "g" ((USItype) (bh)), \
295 "1" ((USItype) (al)), \
296 "g" ((USItype) (bl)))
297 #define umul_ppmm(ph, pl, m0, m1) \
298 __asm__ ("mulx %3,%0,%1" \
299 : "=g" ((USItype) (ph)), \
300 "=r" ((USItype) (pl)) \
301 : "%0" ((USItype) (m0)), \
302 "g" ((USItype) (m1)))
303 #define udiv_qrnnd(q, r, nh, nl, d) \
304 __asm__ ("divx %4,%0,%1" \
305 : "=g" ((USItype) (q)), \
306 "=r" ((USItype) (r)) \
307 : "1" ((USItype) (nh)), \
308 "0" ((USItype) (nl)), \
309 "g" ((USItype) (d)))
310 #define count_leading_zeros(count, x) \
311 __asm__ ("bsch/1 %1,%0" \
312 : "=g" (count) \
313 : "g" ((USItype) (x)), \
314 "0" ((USItype) 0))
315 #endif
316
317 #if defined (__hppa) && W_TYPE_SIZE == 32
318 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
319 __asm__ ("add %4,%5,%1
320 addc %2,%3,%0" \
321 : "=r" ((USItype) (sh)), \
322 "=&r" ((USItype) (sl)) \
323 : "%rM" ((USItype) (ah)), \
324 "rM" ((USItype) (bh)), \
325 "%rM" ((USItype) (al)), \
326 "rM" ((USItype) (bl)))
327 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
328 __asm__ ("sub %4,%5,%1
329 subb %2,%3,%0" \
330 : "=r" ((USItype) (sh)), \
331 "=&r" ((USItype) (sl)) \
332 : "rM" ((USItype) (ah)), \
333 "rM" ((USItype) (bh)), \
334 "rM" ((USItype) (al)), \
335 "rM" ((USItype) (bl)))
336 #if defined (_PA_RISC1_1)
337 #define umul_ppmm(w1, w0, u, v) \
338 do { \
339 union \
340 { \
341 UDItype __f; \
342 struct {USItype __w1, __w0;} __w1w0; \
343 } __t; \
344 __asm__ ("xmpyu %1,%2,%0" \
345 : "=x" (__t.__f) \
346 : "x" ((USItype) (u)), \
347 "x" ((USItype) (v))); \
348 (w1) = __t.__w1w0.__w1; \
349 (w0) = __t.__w1w0.__w0; \
350 } while (0)
351 #define UMUL_TIME 8
352 #else
353 #define UMUL_TIME 30
354 #endif
355 #define UDIV_TIME 40
356 #define count_leading_zeros(count, x) \
357 do { \
358 USItype __tmp; \
359 __asm__ ( \
360 "ldi 1,%0
361 extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
362 extru,tr %1,15,16,%1 ; No. Shift down, skip add.
363 ldo 16(%0),%0 ; Yes. Perform add.
364 extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
365 extru,tr %1,23,8,%1 ; No. Shift down, skip add.
366 ldo 8(%0),%0 ; Yes. Perform add.
367 extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
368 extru,tr %1,27,4,%1 ; No. Shift down, skip add.
369 ldo 4(%0),%0 ; Yes. Perform add.
370 extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
371 extru,tr %1,29,2,%1 ; No. Shift down, skip add.
372 ldo 2(%0),%0 ; Yes. Perform add.
373 extru %1,30,1,%1 ; Extract bit 1.
374 sub %0,%1,%0 ; Subtract it.
375 " : "=r" (count), "=r" (__tmp) : "1" (x)); \
376 } while (0)
377 #endif
378
379 #if (defined (__i370__) || defined (__mvs__)) && W_TYPE_SIZE == 32
380 #define umul_ppmm(xh, xl, m0, m1) \
381 do { \
382 union {UDItype __ll; \
383 struct {USItype __h, __l;} __i; \
384 } __xx; \
385 USItype __m0 = (m0), __m1 = (m1); \
386 __asm__ ("mr %0,%3" \
387 : "=r" (__xx.__i.__h), \
388 "=r" (__xx.__i.__l) \
389 : "%1" (__m0), \
390 "r" (__m1)); \
391 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
392 (xh) += ((((SItype) __m0 >> 31) & __m1) \
393 + (((SItype) __m1 >> 31) & __m0)); \
394 } while (0)
395 #define smul_ppmm(xh, xl, m0, m1) \
396 do { \
397 union {DItype __ll; \
398 struct {USItype __h, __l;} __i; \
399 } __xx; \
400 __asm__ ("mr %0,%3" \
401 : "=r" (__xx.__i.__h), \
402 "=r" (__xx.__i.__l) \
403 : "%1" (m0), \
404 "r" (m1)); \
405 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
406 } while (0)
407 #define sdiv_qrnnd(q, r, n1, n0, d) \
408 do { \
409 union {DItype __ll; \
410 struct {USItype __h, __l;} __i; \
411 } __xx; \
412 __xx.__i.__h = n1; __xx.__i.__l = n0; \
413 __asm__ ("dr %0,%2" \
414 : "=r" (__xx.__ll) \
415 : "0" (__xx.__ll), "r" (d)); \
416 (q) = __xx.__i.__l; (r) = __xx.__i.__h; \
417 } while (0)
418 #endif
419
420 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
421 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
422 __asm__ ("addl %5,%1
423 adcl %3,%0" \
424 : "=r" ((USItype) (sh)), \
425 "=&r" ((USItype) (sl)) \
426 : "%0" ((USItype) (ah)), \
427 "g" ((USItype) (bh)), \
428 "%1" ((USItype) (al)), \
429 "g" ((USItype) (bl)))
430 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
431 __asm__ ("subl %5,%1
432 sbbl %3,%0" \
433 : "=r" ((USItype) (sh)), \
434 "=&r" ((USItype) (sl)) \
435 : "0" ((USItype) (ah)), \
436 "g" ((USItype) (bh)), \
437 "1" ((USItype) (al)), \
438 "g" ((USItype) (bl)))
439 #define umul_ppmm(w1, w0, u, v) \
440 __asm__ ("mull %3" \
441 : "=a" ((USItype) (w0)), \
442 "=d" ((USItype) (w1)) \
443 : "%0" ((USItype) (u)), \
444 "rm" ((USItype) (v)))
445 #define udiv_qrnnd(q, r, n1, n0, dv) \
446 __asm__ ("divl %4" \
447 : "=a" ((USItype) (q)), \
448 "=d" ((USItype) (r)) \
449 : "0" ((USItype) (n0)), \
450 "1" ((USItype) (n1)), \
451 "rm" ((USItype) (dv)))
452 #define count_leading_zeros(count, x) \
453 do { \
454 USItype __cbtmp; \
455 __asm__ ("bsrl %1,%0" \
456 : "=r" (__cbtmp) : "rm" ((USItype) (x))); \
457 (count) = __cbtmp ^ 31; \
458 } while (0)
459 #define count_trailing_zeros(count, x) \
460 __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
461 #define UMUL_TIME 40
462 #define UDIV_TIME 40
463 #endif /* 80x86 */
464
465 #if defined (__i860__) && W_TYPE_SIZE == 32
466 #if 0
467 /* Make sure these patterns really improve the code before
468 switching them on. */
469 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
470 do { \
471 union \
472 { \
473 DItype __ll; \
474 struct {USItype __l, __h;} __i; \
475 } __a, __b, __s; \
476 __a.__i.__l = (al); \
477 __a.__i.__h = (ah); \
478 __b.__i.__l = (bl); \
479 __b.__i.__h = (bh); \
480 __asm__ ("fiadd.dd %1,%2,%0" \
481 : "=f" (__s.__ll) \
482 : "%f" (__a.__ll), "f" (__b.__ll)); \
483 (sh) = __s.__i.__h; \
484 (sl) = __s.__i.__l; \
485 } while (0)
486 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
487 do { \
488 union \
489 { \
490 DItype __ll; \
491 struct {USItype __l, __h;} __i; \
492 } __a, __b, __s; \
493 __a.__i.__l = (al); \
494 __a.__i.__h = (ah); \
495 __b.__i.__l = (bl); \
496 __b.__i.__h = (bh); \
497 __asm__ ("fisub.dd %1,%2,%0" \
498 : "=f" (__s.__ll) \
499 : "%f" (__a.__ll), "f" (__b.__ll)); \
500 (sh) = __s.__i.__h; \
501 (sl) = __s.__i.__l; \
502 } while (0)
503 #endif
504 #endif /* __i860__ */
505
506 #if defined (__i960__) && W_TYPE_SIZE == 32
507 #define umul_ppmm(w1, w0, u, v) \
508 ({union {UDItype __ll; \
509 struct {USItype __l, __h;} __i; \
510 } __xx; \
511 __asm__ ("emul %2,%1,%0" \
512 : "=d" (__xx.__ll) \
513 : "%dI" ((USItype) (u)), \
514 "dI" ((USItype) (v))); \
515 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
516 #define __umulsidi3(u, v) \
517 ({UDItype __w; \
518 __asm__ ("emul %2,%1,%0" \
519 : "=d" (__w) \
520 : "%dI" ((USItype) (u)), \
521 "dI" ((USItype) (v))); \
522 __w; })
523 #endif /* __i960__ */
524
525 #if defined (__M32R__) && W_TYPE_SIZE == 32
526 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
527 /* The cmp clears the condition bit. */ \
528 __asm__ ("cmp %0,%0
529 addx %%5,%1
530 addx %%3,%0" \
531 : "=r" ((USItype) (sh)), \
532 "=&r" ((USItype) (sl)) \
533 : "%0" ((USItype) (ah)), \
534 "r" ((USItype) (bh)), \
535 "%1" ((USItype) (al)), \
536 "r" ((USItype) (bl)) \
537 : "cbit")
538 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
539 /* The cmp clears the condition bit. */ \
540 __asm__ ("cmp %0,%0
541 subx %5,%1
542 subx %3,%0" \
543 : "=r" ((USItype) (sh)), \
544 "=&r" ((USItype) (sl)) \
545 : "0" ((USItype) (ah)), \
546 "r" ((USItype) (bh)), \
547 "1" ((USItype) (al)), \
548 "r" ((USItype) (bl)) \
549 : "cbit")
550 #endif /* __M32R__ */
551
552 #if defined (__mc68000__) && W_TYPE_SIZE == 32
553 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
554 __asm__ ("add%.l %5,%1
555 addx%.l %3,%0" \
556 : "=d" ((USItype) (sh)), \
557 "=&d" ((USItype) (sl)) \
558 : "%0" ((USItype) (ah)), \
559 "d" ((USItype) (bh)), \
560 "%1" ((USItype) (al)), \
561 "g" ((USItype) (bl)))
562 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
563 __asm__ ("sub%.l %5,%1
564 subx%.l %3,%0" \
565 : "=d" ((USItype) (sh)), \
566 "=&d" ((USItype) (sl)) \
567 : "0" ((USItype) (ah)), \
568 "d" ((USItype) (bh)), \
569 "1" ((USItype) (al)), \
570 "g" ((USItype) (bl)))
571
572 /* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r. */
573 #if defined (__mc68020__) || defined(mc68020) \
574 || defined(__mc68030__) || defined(mc68030) \
575 || defined(__mc68040__) || defined(mc68040) \
576 || defined(__mcpu32__) || defined(mcpu32) \
577 || defined(__NeXT__)
578 #define umul_ppmm(w1, w0, u, v) \
579 __asm__ ("mulu%.l %3,%1:%0" \
580 : "=d" ((USItype) (w0)), \
581 "=d" ((USItype) (w1)) \
582 : "%0" ((USItype) (u)), \
583 "dmi" ((USItype) (v)))
584 #define UMUL_TIME 45
585 #define udiv_qrnnd(q, r, n1, n0, d) \
586 __asm__ ("divu%.l %4,%1:%0" \
587 : "=d" ((USItype) (q)), \
588 "=d" ((USItype) (r)) \
589 : "0" ((USItype) (n0)), \
590 "1" ((USItype) (n1)), \
591 "dmi" ((USItype) (d)))
592 #define UDIV_TIME 90
593 #define sdiv_qrnnd(q, r, n1, n0, d) \
594 __asm__ ("divs%.l %4,%1:%0" \
595 : "=d" ((USItype) (q)), \
596 "=d" ((USItype) (r)) \
597 : "0" ((USItype) (n0)), \
598 "1" ((USItype) (n1)), \
599 "dmi" ((USItype) (d)))
600
601 #else /* not mc68020 */
602 #if !defined(__mcf5200__)
603 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
604 #define umul_ppmm(xh, xl, a, b) \
605 __asm__ ("| Inlined umul_ppmm
606 move%.l %2,%/d0
607 move%.l %3,%/d1
608 move%.l %/d0,%/d2
609 swap %/d0
610 move%.l %/d1,%/d3
611 swap %/d1
612 move%.w %/d2,%/d4
613 mulu %/d3,%/d4
614 mulu %/d1,%/d2
615 mulu %/d0,%/d3
616 mulu %/d0,%/d1
617 move%.l %/d4,%/d0
618 eor%.w %/d0,%/d0
619 swap %/d0
620 add%.l %/d0,%/d2
621 add%.l %/d3,%/d2
622 jcc 1f
623 add%.l %#65536,%/d1
624 1: swap %/d2
625 moveq %#0,%/d0
626 move%.w %/d2,%/d0
627 move%.w %/d4,%/d2
628 move%.l %/d2,%1
629 add%.l %/d1,%/d0
630 move%.l %/d0,%0" \
631 : "=g" ((USItype) (xh)), \
632 "=g" ((USItype) (xl)) \
633 : "g" ((USItype) (a)), \
634 "g" ((USItype) (b)) \
635 : "d0", "d1", "d2", "d3", "d4")
636 #define UMUL_TIME 100
637 #define UDIV_TIME 400
638 #endif /* not mcf5200 */
639 #endif /* not mc68020 */
640
641 /* The '020, '030, '040 and '060 have bitfield insns. */
642 #if defined (__mc68020__) || defined(mc68020) \
643 || defined(__mc68030__) || defined(mc68030) \
644 || defined(__mc68040__) || defined(mc68040) \
645 || defined(__mc68060__) || defined(mc68060) \
646 || defined(__NeXT__)
647 #define count_leading_zeros(count, x) \
648 __asm__ ("bfffo %1{%b2:%b2},%0" \
649 : "=d" ((USItype) (count)) \
650 : "od" ((USItype) (x)), "n" (0))
651 #endif
652 #endif /* mc68000 */
653
654 #if defined (__m88000__) && W_TYPE_SIZE == 32
655 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
656 __asm__ ("addu.co %1,%r4,%r5
657 addu.ci %0,%r2,%r3" \
658 : "=r" ((USItype) (sh)), \
659 "=&r" ((USItype) (sl)) \
660 : "%rJ" ((USItype) (ah)), \
661 "rJ" ((USItype) (bh)), \
662 "%rJ" ((USItype) (al)), \
663 "rJ" ((USItype) (bl)))
664 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
665 __asm__ ("subu.co %1,%r4,%r5
666 subu.ci %0,%r2,%r3" \
667 : "=r" ((USItype) (sh)), \
668 "=&r" ((USItype) (sl)) \
669 : "rJ" ((USItype) (ah)), \
670 "rJ" ((USItype) (bh)), \
671 "rJ" ((USItype) (al)), \
672 "rJ" ((USItype) (bl)))
673 #define count_leading_zeros(count, x) \
674 do { \
675 USItype __cbtmp; \
676 __asm__ ("ff1 %0,%1" \
677 : "=r" (__cbtmp) \
678 : "r" ((USItype) (x))); \
679 (count) = __cbtmp ^ 31; \
680 } while (0)
681 #define COUNT_LEADING_ZEROS_0 63 /* sic */
682 #if defined (__mc88110__)
683 #define umul_ppmm(wh, wl, u, v) \
684 do { \
685 union {UDItype __ll; \
686 struct {USItype __h, __l;} __i; \
687 } __xx; \
688 __asm__ ("mulu.d %0,%1,%2" \
689 : "=r" (__xx.__ll) \
690 : "r" ((USItype) (u)), \
691 "r" ((USItype) (v))); \
692 (wh) = __xx.__i.__h; \
693 (wl) = __xx.__i.__l; \
694 } while (0)
695 #define udiv_qrnnd(q, r, n1, n0, d) \
696 ({union {UDItype __ll; \
697 struct {USItype __h, __l;} __i; \
698 } __xx; \
699 USItype __q; \
700 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
701 __asm__ ("divu.d %0,%1,%2" \
702 : "=r" (__q) \
703 : "r" (__xx.__ll), \
704 "r" ((USItype) (d))); \
705 (r) = (n0) - __q * (d); (q) = __q; })
706 #define UMUL_TIME 5
707 #define UDIV_TIME 25
708 #else
709 #define UMUL_TIME 17
710 #define UDIV_TIME 150
711 #endif /* __mc88110__ */
712 #endif /* __m88000__ */
713
714 #if defined (__mips__) && W_TYPE_SIZE == 32
715 #define umul_ppmm(w1, w0, u, v) \
716 __asm__ ("multu %2,%3" \
717 : "=l" ((USItype) (w0)), \
718 "=h" ((USItype) (w1)) \
719 : "d" ((USItype) (u)), \
720 "d" ((USItype) (v)))
721 #define UMUL_TIME 10
722 #define UDIV_TIME 100
723 #endif /* __mips__ */
724
725 #if defined (__ns32000__) && W_TYPE_SIZE == 32
726 #define umul_ppmm(w1, w0, u, v) \
727 ({union {UDItype __ll; \
728 struct {USItype __l, __h;} __i; \
729 } __xx; \
730 __asm__ ("meid %2,%0" \
731 : "=g" (__xx.__ll) \
732 : "%0" ((USItype) (u)), \
733 "g" ((USItype) (v))); \
734 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
735 #define __umulsidi3(u, v) \
736 ({UDItype __w; \
737 __asm__ ("meid %2,%0" \
738 : "=g" (__w) \
739 : "%0" ((USItype) (u)), \
740 "g" ((USItype) (v))); \
741 __w; })
742 #define udiv_qrnnd(q, r, n1, n0, d) \
743 ({union {UDItype __ll; \
744 struct {USItype __l, __h;} __i; \
745 } __xx; \
746 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
747 __asm__ ("deid %2,%0" \
748 : "=g" (__xx.__ll) \
749 : "0" (__xx.__ll), \
750 "g" ((USItype) (d))); \
751 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
752 #define count_trailing_zeros(count,x) \
753 do {
754 __asm__ ("ffsd %2,%0" \
755 : "=r" ((USItype) (count)) \
756 : "0" ((USItype) 0), \
757 "r" ((USItype) (x))); \
758 } while (0)
759 #endif /* __ns32000__ */
760
761 #if (defined (_ARCH_PPC) || defined (_IBMR2))
762 #if W_TYPE_SIZE == 32
763 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
764 do { \
765 if (__builtin_constant_p (bh) && (bh) == 0) \
766 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
767 : "=r" ((USItype) (sh)), \
768 "=&r" ((USItype) (sl)) \
769 : "%r" ((USItype) (ah)), \
770 "%r" ((USItype) (al)), \
771 "rI" ((USItype) (bl))); \
772 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
773 __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
774 : "=r" ((USItype) (sh)), \
775 "=&r" ((USItype) (sl)) \
776 : "%r" ((USItype) (ah)), \
777 "%r" ((USItype) (al)), \
778 "rI" ((USItype) (bl))); \
779 else \
780 __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
781 : "=r" ((USItype) (sh)), \
782 "=&r" ((USItype) (sl)) \
783 : "%r" ((USItype) (ah)), \
784 "r" ((USItype) (bh)), \
785 "%r" ((USItype) (al)), \
786 "rI" ((USItype) (bl))); \
787 } while (0)
788 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
789 do { \
790 if (__builtin_constant_p (ah) && (ah) == 0) \
791 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
792 : "=r" ((USItype) (sh)), \
793 "=&r" ((USItype) (sl)) \
794 : "r" ((USItype) (bh)), \
795 "rI" ((USItype) (al)), \
796 "r" ((USItype) (bl))); \
797 else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
798 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
799 : "=r" ((USItype) (sh)), \
800 "=&r" ((USItype) (sl)) \
801 : "r" ((USItype) (bh)), \
802 "rI" ((USItype) (al)), \
803 "r" ((USItype) (bl))); \
804 else if (__builtin_constant_p (bh) && (bh) == 0) \
805 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
806 : "=r" ((USItype) (sh)), \
807 "=&r" ((USItype) (sl)) \
808 : "r" ((USItype) (ah)), \
809 "rI" ((USItype) (al)), \
810 "r" ((USItype) (bl))); \
811 else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
812 __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
813 : "=r" ((USItype) (sh)), \
814 "=&r" ((USItype) (sl)) \
815 : "r" ((USItype) (ah)), \
816 "rI" ((USItype) (al)), \
817 "r" ((USItype) (bl))); \
818 else \
819 __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
820 : "=r" ((USItype) (sh)), \
821 "=&r" ((USItype) (sl)) \
822 : "r" ((USItype) (ah)), \
823 "r" ((USItype) (bh)), \
824 "rI" ((USItype) (al)), \
825 "r" ((USItype) (bl))); \
826 } while (0)
827 #endif /* W_TYPE_SIZE */
828 #define count_leading_zeros(count, x) \
829 __asm__ ("{cntlz|cntlzw} %0,%1" \
830 : "=r" ((USItype) (count)) \
831 : "r" ((USItype) (x)))
832 #define COUNT_LEADING_ZEROS_0 32
833 #if defined (_ARCH_PPC)
834 #define umul_ppmm(ph, pl, m0, m1) \
835 do { \
836 USItype __m0 = (m0), __m1 = (m1); \
837 __asm__ ("mulhwu %0,%1,%2" \
838 : "=r" ((USItype) ph) \
839 : "%r" (__m0), \
840 "r" (__m1)); \
841 (pl) = __m0 * __m1; \
842 } while (0)
843 #define UMUL_TIME 15
844 #define smul_ppmm(ph, pl, m0, m1) \
845 do { \
846 SItype __m0 = (m0), __m1 = (m1); \
847 __asm__ ("mulhw %0,%1,%2" \
848 : "=r" ((SItype) ph) \
849 : "%r" (__m0), \
850 "r" (__m1)); \
851 (pl) = __m0 * __m1; \
852 } while (0)
853 #define SMUL_TIME 14
854 #define UDIV_TIME 120
855 #elif defined (_ARCH_POWER)
856 #define umul_ppmm(xh, xl, m0, m1) \
857 do { \
858 USItype __m0 = (m0), __m1 = (m1); \
859 __asm__ ("mul %0,%2,%3" \
860 : "=r" ((USItype) (xh)), \
861 "=q" ((USItype) (xl)) \
862 : "r" (__m0), \
863 "r" (__m1)); \
864 (xh) += ((((SItype) __m0 >> 31) & __m1) \
865 + (((SItype) __m1 >> 31) & __m0)); \
866 } while (0)
867 #define UMUL_TIME 8
868 #define smul_ppmm(xh, xl, m0, m1) \
869 __asm__ ("mul %0,%2,%3" \
870 : "=r" ((SItype) (xh)), \
871 "=q" ((SItype) (xl)) \
872 : "r" (m0), \
873 "r" (m1))
874 #define SMUL_TIME 4
875 #define sdiv_qrnnd(q, r, nh, nl, d) \
876 __asm__ ("div %0,%2,%4" \
877 : "=r" ((SItype) (q)), "=q" ((SItype) (r)) \
878 : "r" ((SItype) (nh)), "1" ((SItype) (nl)), "r" ((SItype) (d)))
879 #define UDIV_TIME 100
880 #endif
881 #endif /* Power architecture variants. */
882
883 #if defined (__pyr__) && W_TYPE_SIZE == 32
884 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
885 __asm__ ("addw %5,%1
886 addwc %3,%0" \
887 : "=r" ((USItype) (sh)), \
888 "=&r" ((USItype) (sl)) \
889 : "%0" ((USItype) (ah)), \
890 "g" ((USItype) (bh)), \
891 "%1" ((USItype) (al)), \
892 "g" ((USItype) (bl)))
893 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
894 __asm__ ("subw %5,%1
895 subwb %3,%0" \
896 : "=r" ((USItype) (sh)), \
897 "=&r" ((USItype) (sl)) \
898 : "0" ((USItype) (ah)), \
899 "g" ((USItype) (bh)), \
900 "1" ((USItype) (al)), \
901 "g" ((USItype) (bl)))
902 /* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP. */
903 #define umul_ppmm(w1, w0, u, v) \
904 ({union {UDItype __ll; \
905 struct {USItype __h, __l;} __i; \
906 } __xx; \
907 __asm__ ("movw %1,%R0
908 uemul %2,%0" \
909 : "=&r" (__xx.__ll) \
910 : "g" ((USItype) (u)), \
911 "g" ((USItype) (v))); \
912 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
913 #endif /* __pyr__ */
914
915 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
916 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
917 __asm__ ("a %1,%5
918 ae %0,%3" \
919 : "=r" ((USItype) (sh)), \
920 "=&r" ((USItype) (sl)) \
921 : "%0" ((USItype) (ah)), \
922 "r" ((USItype) (bh)), \
923 "%1" ((USItype) (al)), \
924 "r" ((USItype) (bl)))
925 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
926 __asm__ ("s %1,%5
927 se %0,%3" \
928 : "=r" ((USItype) (sh)), \
929 "=&r" ((USItype) (sl)) \
930 : "0" ((USItype) (ah)), \
931 "r" ((USItype) (bh)), \
932 "1" ((USItype) (al)), \
933 "r" ((USItype) (bl)))
934 #define umul_ppmm(ph, pl, m0, m1) \
935 do { \
936 USItype __m0 = (m0), __m1 = (m1); \
937 __asm__ ( \
938 "s r2,r2
939 mts r10,%2
940 m r2,%3
941 m r2,%3
942 m r2,%3
943 m r2,%3
944 m r2,%3
945 m r2,%3
946 m r2,%3
947 m r2,%3
948 m r2,%3
949 m r2,%3
950 m r2,%3
951 m r2,%3
952 m r2,%3
953 m r2,%3
954 m r2,%3
955 m r2,%3
956 cas %0,r2,r0
957 mfs r10,%1" \
958 : "=r" ((USItype) (ph)), \
959 "=r" ((USItype) (pl)) \
960 : "%r" (__m0), \
961 "r" (__m1) \
962 : "r2"); \
963 (ph) += ((((SItype) __m0 >> 31) & __m1) \
964 + (((SItype) __m1 >> 31) & __m0)); \
965 } while (0)
966 #define UMUL_TIME 20
967 #define UDIV_TIME 200
968 #define count_leading_zeros(count, x) \
969 do { \
970 if ((x) >= 0x10000) \
971 __asm__ ("clz %0,%1" \
972 : "=r" ((USItype) (count)) \
973 : "r" ((USItype) (x) >> 16)); \
974 else \
975 { \
976 __asm__ ("clz %0,%1" \
977 : "=r" ((USItype) (count)) \
978 : "r" ((USItype) (x))); \
979 (count) += 16; \
980 } \
981 } while (0)
982 #endif
983
984 #if defined (__sh2__) && W_TYPE_SIZE == 32
985 #define umul_ppmm(w1, w0, u, v) \
986 __asm__ ( \
987 "dmulu.l %2,%3
988 sts macl,%1
989 sts mach,%0" \
990 : "=r" ((USItype)(w1)), \
991 "=r" ((USItype)(w0)) \
992 : "r" ((USItype)(u)), \
993 "r" ((USItype)(v)) \
994 : "macl", "mach")
995 #define UMUL_TIME 5
996 #endif
997
998 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
999 && W_TYPE_SIZE == 32
1000 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1001 __asm__ ("addcc %r4,%5,%1
1002 addx %r2,%3,%0" \
1003 : "=r" ((USItype) (sh)), \
1004 "=&r" ((USItype) (sl)) \
1005 : "%rJ" ((USItype) (ah)), \
1006 "rI" ((USItype) (bh)), \
1007 "%rJ" ((USItype) (al)), \
1008 "rI" ((USItype) (bl)) \
1009 __CLOBBER_CC)
1010 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1011 __asm__ ("subcc %r4,%5,%1
1012 subx %r2,%3,%0" \
1013 : "=r" ((USItype) (sh)), \
1014 "=&r" ((USItype) (sl)) \
1015 : "rJ" ((USItype) (ah)), \
1016 "rI" ((USItype) (bh)), \
1017 "rJ" ((USItype) (al)), \
1018 "rI" ((USItype) (bl)) \
1019 __CLOBBER_CC)
1020 #if defined (__sparc_v8__)
1021 #define umul_ppmm(w1, w0, u, v) \
1022 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1023 : "=r" ((USItype) (w1)), \
1024 "=r" ((USItype) (w0)) \
1025 : "r" ((USItype) (u)), \
1026 "r" ((USItype) (v)))
1027 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1028 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
1029 : "=&r" ((USItype) (__q)), \
1030 "=&r" ((USItype) (__r)) \
1031 : "r" ((USItype) (__n1)), \
1032 "r" ((USItype) (__n0)), \
1033 "r" ((USItype) (__d)))
1034 #else
1035 #if defined (__sparclite__)
1036 /* This has hardware multiply but not divide. It also has two additional
1037 instructions scan (ffs from high bit) and divscc. */
1038 #define umul_ppmm(w1, w0, u, v) \
1039 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1040 : "=r" ((USItype) (w1)), \
1041 "=r" ((USItype) (w0)) \
1042 : "r" ((USItype) (u)), \
1043 "r" ((USItype) (v)))
1044 #define udiv_qrnnd(q, r, n1, n0, d) \
1045 __asm__ ("! Inlined udiv_qrnnd
1046 wr %%g0,%2,%%y ! Not a delayed write for sparclite
1047 tst %%g0
1048 divscc %3,%4,%%g1
1049 divscc %%g1,%4,%%g1
1050 divscc %%g1,%4,%%g1
1051 divscc %%g1,%4,%%g1
1052 divscc %%g1,%4,%%g1
1053 divscc %%g1,%4,%%g1
1054 divscc %%g1,%4,%%g1
1055 divscc %%g1,%4,%%g1
1056 divscc %%g1,%4,%%g1
1057 divscc %%g1,%4,%%g1
1058 divscc %%g1,%4,%%g1
1059 divscc %%g1,%4,%%g1
1060 divscc %%g1,%4,%%g1
1061 divscc %%g1,%4,%%g1
1062 divscc %%g1,%4,%%g1
1063 divscc %%g1,%4,%%g1
1064 divscc %%g1,%4,%%g1
1065 divscc %%g1,%4,%%g1
1066 divscc %%g1,%4,%%g1
1067 divscc %%g1,%4,%%g1
1068 divscc %%g1,%4,%%g1
1069 divscc %%g1,%4,%%g1
1070 divscc %%g1,%4,%%g1
1071 divscc %%g1,%4,%%g1
1072 divscc %%g1,%4,%%g1
1073 divscc %%g1,%4,%%g1
1074 divscc %%g1,%4,%%g1
1075 divscc %%g1,%4,%%g1
1076 divscc %%g1,%4,%%g1
1077 divscc %%g1,%4,%%g1
1078 divscc %%g1,%4,%%g1
1079 divscc %%g1,%4,%0
1080 rd %%y,%1
1081 bl,a 1f
1082 add %1,%4,%1
1083 1: ! End of inline udiv_qrnnd" \
1084 : "=r" ((USItype) (q)), \
1085 "=r" ((USItype) (r)) \
1086 : "r" ((USItype) (n1)), \
1087 "r" ((USItype) (n0)), \
1088 "rI" ((USItype) (d)) \
1089 : "g1" __AND_CLOBBER_CC)
1090 #define UDIV_TIME 37
1091 #define count_leading_zeros(count, x) \
1092 do { \
1093 __asm__ ("scan %1,1,%0" \
1094 : "=r" ((USItype) (count)) \
1095 : "r" ((USItype) (x))); \
1096 } while (0)
1097 /* Early sparclites return 63 for an argument of 0, but they warn that future
1098 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1099 undefined. */
1100 #else
1101 /* SPARC without integer multiplication and divide instructions.
1102 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1103 #define umul_ppmm(w1, w0, u, v) \
1104 __asm__ ("! Inlined umul_ppmm
1105 wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
1106 sra %3,31,%%o5 ! Don't move this insn
1107 and %2,%%o5,%%o5 ! Don't move this insn
1108 andcc %%g0,0,%%g1 ! Don't move this insn
1109 mulscc %%g1,%3,%%g1
1110 mulscc %%g1,%3,%%g1
1111 mulscc %%g1,%3,%%g1
1112 mulscc %%g1,%3,%%g1
1113 mulscc %%g1,%3,%%g1
1114 mulscc %%g1,%3,%%g1
1115 mulscc %%g1,%3,%%g1
1116 mulscc %%g1,%3,%%g1
1117 mulscc %%g1,%3,%%g1
1118 mulscc %%g1,%3,%%g1
1119 mulscc %%g1,%3,%%g1
1120 mulscc %%g1,%3,%%g1
1121 mulscc %%g1,%3,%%g1
1122 mulscc %%g1,%3,%%g1
1123 mulscc %%g1,%3,%%g1
1124 mulscc %%g1,%3,%%g1
1125 mulscc %%g1,%3,%%g1
1126 mulscc %%g1,%3,%%g1
1127 mulscc %%g1,%3,%%g1
1128 mulscc %%g1,%3,%%g1
1129 mulscc %%g1,%3,%%g1
1130 mulscc %%g1,%3,%%g1
1131 mulscc %%g1,%3,%%g1
1132 mulscc %%g1,%3,%%g1
1133 mulscc %%g1,%3,%%g1
1134 mulscc %%g1,%3,%%g1
1135 mulscc %%g1,%3,%%g1
1136 mulscc %%g1,%3,%%g1
1137 mulscc %%g1,%3,%%g1
1138 mulscc %%g1,%3,%%g1
1139 mulscc %%g1,%3,%%g1
1140 mulscc %%g1,%3,%%g1
1141 mulscc %%g1,0,%%g1
1142 add %%g1,%%o5,%0
1143 rd %%y,%1" \
1144 : "=r" ((USItype) (w1)), \
1145 "=r" ((USItype) (w0)) \
1146 : "%rI" ((USItype) (u)), \
1147 "r" ((USItype) (v)) \
1148 : "g1", "o5" __AND_CLOBBER_CC)
1149 #define UMUL_TIME 39 /* 39 instructions */
1150 /* It's quite necessary to add this much assembler for the sparc.
1151 The default udiv_qrnnd (in C) is more than 10 times slower! */
1152 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1153 __asm__ ("! Inlined udiv_qrnnd
1154 mov 32,%%g1
1155 subcc %1,%2,%%g0
1156 1: bcs 5f
1157 addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
1158 sub %1,%2,%1 ! this kills msb of n
1159 addx %1,%1,%1 ! so this can't give carry
1160 subcc %%g1,1,%%g1
1161 2: bne 1b
1162 subcc %1,%2,%%g0
1163 bcs 3f
1164 addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
1165 b 3f
1166 sub %1,%2,%1 ! this kills msb of n
1167 4: sub %1,%2,%1
1168 5: addxcc %1,%1,%1
1169 bcc 2b
1170 subcc %%g1,1,%%g1
1171 ! Got carry from n. Subtract next step to cancel this carry.
1172 bne 4b
1173 addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb
1174 sub %1,%2,%1
1175 3: xnor %0,0,%0
1176 ! End of inline udiv_qrnnd" \
1177 : "=&r" ((USItype) (__q)), \
1178 "=&r" ((USItype) (__r)) \
1179 : "r" ((USItype) (__d)), \
1180 "1" ((USItype) (__n1)), \
1181 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1182 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1183 #endif /* __sparclite__ */
1184 #endif /* __sparc_v8__ */
1185 #endif /* sparc32 */
1186
1187 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1188 && W_TYPE_SIZE == 64
1189 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1190 __asm__ ("addcc %r4,%5,%1
1191 add %r2,%3,%0
1192 bcs,a,pn %%xcc, 1f
1193 add %0, 1, %0
1194 1:" \
1195 : "=r" ((UDItype)(sh)), \
1196 "=&r" ((UDItype)(sl)) \
1197 : "%rJ" ((UDItype)(ah)), \
1198 "rI" ((UDItype)(bh)), \
1199 "%rJ" ((UDItype)(al)), \
1200 "rI" ((UDItype)(bl)) \
1201 __CLOBBER_CC)
1202
1203 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1204 __asm__ ("subcc %r4,%5,%1
1205 sub %r2,%3,%0
1206 bcs,a,pn %%xcc, 1f
1207 sub %0, 1, %0
1208 1:" \
1209 : "=r" ((UDItype)(sh)), \
1210 "=&r" ((UDItype)(sl)) \
1211 : "rJ" ((UDItype)(ah)), \
1212 "rI" ((UDItype)(bh)), \
1213 "rJ" ((UDItype)(al)), \
1214 "rI" ((UDItype)(bl)) \
1215 __CLOBBER_CC)
1216
1217 #define umul_ppmm(wh, wl, u, v) \
1218 do { \
1219 UDItype tmp1, tmp2, tmp3, tmp4; \
1220 __asm__ __volatile__ ( \
1221 "srl %7,0,%3
1222 mulx %3,%6,%1
1223 srlx %6,32,%2
1224 mulx %2,%3,%4
1225 sllx %4,32,%5
1226 srl %6,0,%3
1227 sub %1,%5,%5
1228 srlx %5,32,%5
1229 addcc %4,%5,%4
1230 srlx %7,32,%5
1231 mulx %3,%5,%3
1232 mulx %2,%5,%5
1233 sethi %%hi(0x80000000),%2
1234 addcc %4,%3,%4
1235 srlx %4,32,%4
1236 add %2,%2,%2
1237 movcc %%xcc,%%g0,%2
1238 addcc %5,%4,%5
1239 sllx %3,32,%3
1240 add %1,%3,%1
1241 add %5,%2,%0" \
1242 : "=r" ((UDItype)(wh)), \
1243 "=&r" ((UDItype)(wl)), \
1244 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1245 : "r" ((UDItype)(u)), \
1246 "r" ((UDItype)(v)) \
1247 __CLOBBER_CC); \
1248 } while (0)
1249 #define UMUL_TIME 96
1250 #define UDIV_TIME 230
1251 #endif /* sparc64 */
1252
1253 #if defined (__vax__) && W_TYPE_SIZE == 32
1254 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1255 __asm__ ("addl2 %5,%1
1256 adwc %3,%0" \
1257 : "=g" ((USItype) (sh)), \
1258 "=&g" ((USItype) (sl)) \
1259 : "%0" ((USItype) (ah)), \
1260 "g" ((USItype) (bh)), \
1261 "%1" ((USItype) (al)), \
1262 "g" ((USItype) (bl)))
1263 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1264 __asm__ ("subl2 %5,%1
1265 sbwc %3,%0" \
1266 : "=g" ((USItype) (sh)), \
1267 "=&g" ((USItype) (sl)) \
1268 : "0" ((USItype) (ah)), \
1269 "g" ((USItype) (bh)), \
1270 "1" ((USItype) (al)), \
1271 "g" ((USItype) (bl)))
1272 #define umul_ppmm(xh, xl, m0, m1) \
1273 do { \
1274 union { \
1275 UDItype __ll; \
1276 struct {USItype __l, __h;} __i; \
1277 } __xx; \
1278 USItype __m0 = (m0), __m1 = (m1); \
1279 __asm__ ("emul %1,%2,$0,%0" \
1280 : "=r" (__xx.__ll) \
1281 : "g" (__m0), \
1282 "g" (__m1)); \
1283 (xh) = __xx.__i.__h; \
1284 (xl) = __xx.__i.__l; \
1285 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1286 + (((SItype) __m1 >> 31) & __m0)); \
1287 } while (0)
1288 #define sdiv_qrnnd(q, r, n1, n0, d) \
1289 do { \
1290 union {DItype __ll; \
1291 struct {SItype __l, __h;} __i; \
1292 } __xx; \
1293 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1294 __asm__ ("ediv %3,%2,%0,%1" \
1295 : "=g" (q), "=g" (r) \
1296 : "g" (__xx.__ll), "g" (d)); \
1297 } while (0)
1298 #endif /* __vax__ */
1299
1300 #if defined (__z8000__) && W_TYPE_SIZE == 16
1301 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1302 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1303 : "=r" ((unsigned int)(sh)), \
1304 "=&r" ((unsigned int)(sl)) \
1305 : "%0" ((unsigned int)(ah)), \
1306 "r" ((unsigned int)(bh)), \
1307 "%1" ((unsigned int)(al)), \
1308 "rQR" ((unsigned int)(bl)))
1309 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1310 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1311 : "=r" ((unsigned int)(sh)), \
1312 "=&r" ((unsigned int)(sl)) \
1313 : "0" ((unsigned int)(ah)), \
1314 "r" ((unsigned int)(bh)), \
1315 "1" ((unsigned int)(al)), \
1316 "rQR" ((unsigned int)(bl)))
1317 #define umul_ppmm(xh, xl, m0, m1) \
1318 do { \
1319 union {long int __ll; \
1320 struct {unsigned int __h, __l;} __i; \
1321 } __xx; \
1322 unsigned int __m0 = (m0), __m1 = (m1); \
1323 __asm__ ("mult %S0,%H3" \
1324 : "=r" (__xx.__i.__h), \
1325 "=r" (__xx.__i.__l) \
1326 : "%1" (__m0), \
1327 "rQR" (__m1)); \
1328 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1329 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1330 + (((signed int) __m1 >> 15) & __m0)); \
1331 } while (0)
1332 #endif /* __z8000__ */
1333
1334 #endif /* __GNUC__ */
1335
1336 /* If this machine has no inline assembler, use C macros. */
1337
1338 #if !defined (add_ssaaaa)
1339 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1340 do { \
1341 UWtype __x; \
1342 __x = (al) + (bl); \
1343 (sh) = (ah) + (bh) + (__x < (al)); \
1344 (sl) = __x; \
1345 } while (0)
1346 #endif
1347
1348 #if !defined (sub_ddmmss)
1349 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1350 do { \
1351 UWtype __x; \
1352 __x = (al) - (bl); \
1353 (sh) = (ah) - (bh) - (__x > (al)); \
1354 (sl) = __x; \
1355 } while (0)
1356 #endif
1357
1358 #if !defined (umul_ppmm)
1359 #define umul_ppmm(w1, w0, u, v) \
1360 do { \
1361 UWtype __x0, __x1, __x2, __x3; \
1362 UHWtype __ul, __vl, __uh, __vh; \
1363 \
1364 __ul = __ll_lowpart (u); \
1365 __uh = __ll_highpart (u); \
1366 __vl = __ll_lowpart (v); \
1367 __vh = __ll_highpart (v); \
1368 \
1369 __x0 = (UWtype) __ul * __vl; \
1370 __x1 = (UWtype) __ul * __vh; \
1371 __x2 = (UWtype) __uh * __vl; \
1372 __x3 = (UWtype) __uh * __vh; \
1373 \
1374 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1375 __x1 += __x2; /* but this indeed can */ \
1376 if (__x1 < __x2) /* did we get it? */ \
1377 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1378 \
1379 (w1) = __x3 + __ll_highpart (__x1); \
1380 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1381 } while (0)
1382 #endif
1383
1384 #if !defined (__umulsidi3)
1385 #define __umulsidi3(u, v) \
1386 ({DWunion __w; \
1387 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1388 __w.ll; })
1389 #endif
1390
1391 /* Define this unconditionally, so it can be used for debugging. */
1392 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1393 do { \
1394 UWtype __d1, __d0, __q1, __q0; \
1395 UWtype __r1, __r0, __m; \
1396 __d1 = __ll_highpart (d); \
1397 __d0 = __ll_lowpart (d); \
1398 \
1399 __r1 = (n1) % __d1; \
1400 __q1 = (n1) / __d1; \
1401 __m = (UWtype) __q1 * __d0; \
1402 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1403 if (__r1 < __m) \
1404 { \
1405 __q1--, __r1 += (d); \
1406 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1407 if (__r1 < __m) \
1408 __q1--, __r1 += (d); \
1409 } \
1410 __r1 -= __m; \
1411 \
1412 __r0 = __r1 % __d1; \
1413 __q0 = __r1 / __d1; \
1414 __m = (UWtype) __q0 * __d0; \
1415 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1416 if (__r0 < __m) \
1417 { \
1418 __q0--, __r0 += (d); \
1419 if (__r0 >= (d)) \
1420 if (__r0 < __m) \
1421 __q0--, __r0 += (d); \
1422 } \
1423 __r0 -= __m; \
1424 \
1425 (q) = (UWtype) __q1 * __ll_B | __q0; \
1426 (r) = __r0; \
1427 } while (0)
1428
1429 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1430 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1431 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1432 #define udiv_qrnnd(q, r, nh, nl, d) \
1433 do { \
1434 USItype __r; \
1435 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1436 (r) = __r; \
1437 } while (0)
1438 #endif
1439
1440 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1441 #if !defined (udiv_qrnnd)
1442 #define UDIV_NEEDS_NORMALIZATION 1
1443 #define udiv_qrnnd __udiv_qrnnd_c
1444 #endif
1445
1446 #if !defined (count_leading_zeros)
1447 static const UQItype __clz_tab[];
1448 #define count_leading_zeros(count, x) \
1449 do { \
1450 UWtype __xr = (x); \
1451 UWtype __a; \
1452 \
1453 if (W_TYPE_SIZE <= 32) \
1454 { \
1455 __a = __xr < ((UWtype)1<<2*__BITS4) \
1456 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1457 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1458 } \
1459 else \
1460 { \
1461 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1462 if (((__xr >> __a) & 0xff) != 0) \
1463 break; \
1464 } \
1465 \
1466 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1467 } while (0)
1468 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1469 #endif
1470
1471 #if !defined (count_trailing_zeros)
1472 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1473 defined in asm, but if it is not, the C version above is good enough. */
1474 #define count_trailing_zeros(count, x) \
1475 do { \
1476 UWtype __ctz_x = (x); \
1477 UWtype __ctz_c; \
1478 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1479 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1480 } while (0)
1481 #endif
1482
1483 #ifndef UDIV_NEEDS_NORMALIZATION
1484 #define UDIV_NEEDS_NORMALIZATION 0
1485 #endif
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