1 /* Decompose multiword subregs.
2 Copyright (C) 2007-2017 Free Software Foundation, Inc.
3 Contributed by Richard Henderson <rth@redhat.com>
4 Ian Lance Taylor <iant@google.com>
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
33 #include "insn-config.h"
40 #include "tree-pass.h"
41 #include "lower-subreg.h"
46 /* Decompose multi-word pseudo-registers into individual
47 pseudo-registers when possible and profitable. This is possible
48 when all the uses of a multi-word register are via SUBREG, or are
49 copies of the register to another location. Breaking apart the
50 register permits more CSE and permits better register allocation.
51 This is profitable if the machine does not have move instructions
54 This pass only splits moves with modes that are wider than
55 word_mode and ASHIFTs, LSHIFTRTs, ASHIFTRTs and ZERO_EXTENDs with
56 integer modes that are twice the width of word_mode. The latter
57 could be generalized if there was a need to do this, but the trend in
58 architectures is to not need this.
60 There are two useful preprocessor defines for use by maintainers:
64 if you wish to see the actual cost estimates that are being used
65 for each mode wider than word mode and the cost estimates for zero
66 extension and the shifts. This can be useful when port maintainers
67 are tuning insn rtx costs.
69 #define FORCE_LOWERING 1
71 if you wish to test the pass with all the transformation forced on.
72 This can be useful for finding bugs in the transformations. */
75 #define FORCE_LOWERING 0
77 /* Bit N in this bitmap is set if regno N is used in a context in
78 which we can decompose it. */
79 static bitmap decomposable_context
;
81 /* Bit N in this bitmap is set if regno N is used in a context in
82 which it can not be decomposed. */
83 static bitmap non_decomposable_context
;
85 /* Bit N in this bitmap is set if regno N is used in a subreg
86 which changes the mode but not the size. This typically happens
87 when the register accessed as a floating-point value; we want to
88 avoid generating accesses to its subwords in integer modes. */
89 static bitmap subreg_context
;
91 /* Bit N in the bitmap in element M of this array is set if there is a
92 copy from reg M to reg N. */
93 static vec
<bitmap
> reg_copy_graph
;
95 struct target_lower_subreg default_target_lower_subreg
;
97 struct target_lower_subreg
*this_target_lower_subreg
98 = &default_target_lower_subreg
;
101 #define twice_word_mode \
102 this_target_lower_subreg->x_twice_word_mode
104 this_target_lower_subreg->x_choices
106 /* RTXes used while computing costs. */
108 /* Source and target registers. */
112 /* A twice_word_mode ZERO_EXTEND of SOURCE. */
115 /* A shift of SOURCE. */
118 /* A SET of TARGET. */
122 /* Return the cost of a CODE shift in mode MODE by OP1 bits, using the
123 rtxes in RTXES. SPEED_P selects between the speed and size cost. */
126 shift_cost (bool speed_p
, struct cost_rtxes
*rtxes
, enum rtx_code code
,
127 machine_mode mode
, int op1
)
129 PUT_CODE (rtxes
->shift
, code
);
130 PUT_MODE (rtxes
->shift
, mode
);
131 PUT_MODE (rtxes
->source
, mode
);
132 XEXP (rtxes
->shift
, 1) = GEN_INT (op1
);
133 return set_src_cost (rtxes
->shift
, mode
, speed_p
);
136 /* For each X in the range [0, BITS_PER_WORD), set SPLITTING[X]
137 to true if it is profitable to split a double-word CODE shift
138 of X + BITS_PER_WORD bits. SPEED_P says whether we are testing
139 for speed or size profitability.
141 Use the rtxes in RTXES to calculate costs. WORD_MOVE_ZERO_COST is
142 the cost of moving zero into a word-mode register. WORD_MOVE_COST
143 is the cost of moving between word registers. */
146 compute_splitting_shift (bool speed_p
, struct cost_rtxes
*rtxes
,
147 bool *splitting
, enum rtx_code code
,
148 int word_move_zero_cost
, int word_move_cost
)
150 int wide_cost
, narrow_cost
, upper_cost
, i
;
152 for (i
= 0; i
< BITS_PER_WORD
; i
++)
154 wide_cost
= shift_cost (speed_p
, rtxes
, code
, twice_word_mode
,
157 narrow_cost
= word_move_cost
;
159 narrow_cost
= shift_cost (speed_p
, rtxes
, code
, word_mode
, i
);
161 if (code
!= ASHIFTRT
)
162 upper_cost
= word_move_zero_cost
;
163 else if (i
== BITS_PER_WORD
- 1)
164 upper_cost
= word_move_cost
;
166 upper_cost
= shift_cost (speed_p
, rtxes
, code
, word_mode
,
170 fprintf (stderr
, "%s %s by %d: original cost %d, split cost %d + %d\n",
171 GET_MODE_NAME (twice_word_mode
), GET_RTX_NAME (code
),
172 i
+ BITS_PER_WORD
, wide_cost
, narrow_cost
, upper_cost
);
174 if (FORCE_LOWERING
|| wide_cost
>= narrow_cost
+ upper_cost
)
179 /* Compute what we should do when optimizing for speed or size; SPEED_P
180 selects which. Use RTXES for computing costs. */
183 compute_costs (bool speed_p
, struct cost_rtxes
*rtxes
)
186 int word_move_zero_cost
, word_move_cost
;
188 PUT_MODE (rtxes
->target
, word_mode
);
189 SET_SRC (rtxes
->set
) = CONST0_RTX (word_mode
);
190 word_move_zero_cost
= set_rtx_cost (rtxes
->set
, speed_p
);
192 SET_SRC (rtxes
->set
) = rtxes
->source
;
193 word_move_cost
= set_rtx_cost (rtxes
->set
, speed_p
);
196 fprintf (stderr
, "%s move: from zero cost %d, from reg cost %d\n",
197 GET_MODE_NAME (word_mode
), word_move_zero_cost
, word_move_cost
);
199 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
201 machine_mode mode
= (machine_mode
) i
;
202 int factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
207 PUT_MODE (rtxes
->target
, mode
);
208 PUT_MODE (rtxes
->source
, mode
);
209 mode_move_cost
= set_rtx_cost (rtxes
->set
, speed_p
);
212 fprintf (stderr
, "%s move: original cost %d, split cost %d * %d\n",
213 GET_MODE_NAME (mode
), mode_move_cost
,
214 word_move_cost
, factor
);
216 if (FORCE_LOWERING
|| mode_move_cost
>= word_move_cost
* factor
)
218 choices
[speed_p
].move_modes_to_split
[i
] = true;
219 choices
[speed_p
].something_to_do
= true;
224 /* For the moves and shifts, the only case that is checked is one
225 where the mode of the target is an integer mode twice the width
228 If it is not profitable to split a double word move then do not
229 even consider the shifts or the zero extension. */
230 if (choices
[speed_p
].move_modes_to_split
[(int) twice_word_mode
])
234 /* The only case here to check to see if moving the upper part with a
235 zero is cheaper than doing the zext itself. */
236 PUT_MODE (rtxes
->source
, word_mode
);
237 zext_cost
= set_src_cost (rtxes
->zext
, twice_word_mode
, speed_p
);
240 fprintf (stderr
, "%s %s: original cost %d, split cost %d + %d\n",
241 GET_MODE_NAME (twice_word_mode
), GET_RTX_NAME (ZERO_EXTEND
),
242 zext_cost
, word_move_cost
, word_move_zero_cost
);
244 if (FORCE_LOWERING
|| zext_cost
>= word_move_cost
+ word_move_zero_cost
)
245 choices
[speed_p
].splitting_zext
= true;
247 compute_splitting_shift (speed_p
, rtxes
,
248 choices
[speed_p
].splitting_ashift
, ASHIFT
,
249 word_move_zero_cost
, word_move_cost
);
250 compute_splitting_shift (speed_p
, rtxes
,
251 choices
[speed_p
].splitting_lshiftrt
, LSHIFTRT
,
252 word_move_zero_cost
, word_move_cost
);
253 compute_splitting_shift (speed_p
, rtxes
,
254 choices
[speed_p
].splitting_ashiftrt
, ASHIFTRT
,
255 word_move_zero_cost
, word_move_cost
);
259 /* Do one-per-target initialisation. This involves determining
260 which operations on the machine are profitable. If none are found,
261 then the pass just returns when called. */
264 init_lower_subreg (void)
266 struct cost_rtxes rtxes
;
268 memset (this_target_lower_subreg
, 0, sizeof (*this_target_lower_subreg
));
270 twice_word_mode
= GET_MODE_2XWIDER_MODE (word_mode
).require ();
272 rtxes
.target
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
273 rtxes
.source
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 2);
274 rtxes
.set
= gen_rtx_SET (rtxes
.target
, rtxes
.source
);
275 rtxes
.zext
= gen_rtx_ZERO_EXTEND (twice_word_mode
, rtxes
.source
);
276 rtxes
.shift
= gen_rtx_ASHIFT (twice_word_mode
, rtxes
.source
, const0_rtx
);
279 fprintf (stderr
, "\nSize costs\n==========\n\n");
280 compute_costs (false, &rtxes
);
283 fprintf (stderr
, "\nSpeed costs\n===========\n\n");
284 compute_costs (true, &rtxes
);
288 simple_move_operand (rtx x
)
290 if (GET_CODE (x
) == SUBREG
)
296 if (GET_CODE (x
) == LABEL_REF
297 || GET_CODE (x
) == SYMBOL_REF
298 || GET_CODE (x
) == HIGH
299 || GET_CODE (x
) == CONST
)
303 && (MEM_VOLATILE_P (x
)
304 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
))))
310 /* If INSN is a single set between two objects that we want to split,
311 return the single set. SPEED_P says whether we are optimizing
312 INSN for speed or size.
314 INSN should have been passed to recog and extract_insn before this
318 simple_move (rtx_insn
*insn
, bool speed_p
)
324 if (recog_data
.n_operands
!= 2)
327 set
= single_set (insn
);
332 if (x
!= recog_data
.operand
[0] && x
!= recog_data
.operand
[1])
334 if (!simple_move_operand (x
))
338 if (x
!= recog_data
.operand
[0] && x
!= recog_data
.operand
[1])
340 /* For the src we can handle ASM_OPERANDS, and it is beneficial for
341 things like x86 rdtsc which returns a DImode value. */
342 if (GET_CODE (x
) != ASM_OPERANDS
343 && !simple_move_operand (x
))
346 /* We try to decompose in integer modes, to avoid generating
347 inefficient code copying between integer and floating point
348 registers. That means that we can't decompose if this is a
349 non-integer mode for which there is no integer mode of the same
351 mode
= GET_MODE (SET_DEST (set
));
352 if (!SCALAR_INT_MODE_P (mode
)
353 && !int_mode_for_size (GET_MODE_BITSIZE (mode
), 0).exists ())
356 /* Reject PARTIAL_INT modes. They are used for processor specific
357 purposes and it's probably best not to tamper with them. */
358 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
361 if (!choices
[speed_p
].move_modes_to_split
[(int) mode
])
367 /* If SET is a copy from one multi-word pseudo-register to another,
368 record that in reg_copy_graph. Return whether it is such a
372 find_pseudo_copy (rtx set
)
374 rtx dest
= SET_DEST (set
);
375 rtx src
= SET_SRC (set
);
379 if (!REG_P (dest
) || !REG_P (src
))
384 if (HARD_REGISTER_NUM_P (rd
) || HARD_REGISTER_NUM_P (rs
))
387 b
= reg_copy_graph
[rs
];
390 b
= BITMAP_ALLOC (NULL
);
391 reg_copy_graph
[rs
] = b
;
394 bitmap_set_bit (b
, rd
);
399 /* Look through the registers in DECOMPOSABLE_CONTEXT. For each case
400 where they are copied to another register, add the register to
401 which they are copied to DECOMPOSABLE_CONTEXT. Use
402 NON_DECOMPOSABLE_CONTEXT to limit this--we don't bother to track
403 copies of registers which are in NON_DECOMPOSABLE_CONTEXT. */
406 propagate_pseudo_copies (void)
408 auto_bitmap queue
, propagate
;
410 bitmap_copy (queue
, decomposable_context
);
413 bitmap_iterator iter
;
416 bitmap_clear (propagate
);
418 EXECUTE_IF_SET_IN_BITMAP (queue
, 0, i
, iter
)
420 bitmap b
= reg_copy_graph
[i
];
422 bitmap_ior_and_compl_into (propagate
, b
, non_decomposable_context
);
425 bitmap_and_compl (queue
, propagate
, decomposable_context
);
426 bitmap_ior_into (decomposable_context
, propagate
);
428 while (!bitmap_empty_p (queue
));
431 /* A pointer to one of these values is passed to
432 find_decomposable_subregs. */
434 enum classify_move_insn
436 /* Not a simple move from one location to another. */
438 /* A simple move we want to decompose. */
439 DECOMPOSABLE_SIMPLE_MOVE
,
440 /* Any other simple move. */
444 /* If we find a SUBREG in *LOC which we could use to decompose a
445 pseudo-register, set a bit in DECOMPOSABLE_CONTEXT. If we find an
446 unadorned register which is not a simple pseudo-register copy,
447 DATA will point at the type of move, and we set a bit in
448 DECOMPOSABLE_CONTEXT or NON_DECOMPOSABLE_CONTEXT as appropriate. */
451 find_decomposable_subregs (rtx
*loc
, enum classify_move_insn
*pcmi
)
453 subrtx_var_iterator::array_type array
;
454 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
457 if (GET_CODE (x
) == SUBREG
)
459 rtx inner
= SUBREG_REG (x
);
460 unsigned int regno
, outer_size
, inner_size
, outer_words
, inner_words
;
465 regno
= REGNO (inner
);
466 if (HARD_REGISTER_NUM_P (regno
))
468 iter
.skip_subrtxes ();
472 outer_size
= GET_MODE_SIZE (GET_MODE (x
));
473 inner_size
= GET_MODE_SIZE (GET_MODE (inner
));
474 outer_words
= (outer_size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
475 inner_words
= (inner_size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
477 /* We only try to decompose single word subregs of multi-word
478 registers. When we find one, we return -1 to avoid iterating
479 over the inner register.
481 ??? This doesn't allow, e.g., DImode subregs of TImode values
482 on 32-bit targets. We would need to record the way the
483 pseudo-register was used, and only decompose if all the uses
484 were the same number and size of pieces. Hopefully this
485 doesn't happen much. */
487 if (outer_words
== 1 && inner_words
> 1)
489 bitmap_set_bit (decomposable_context
, regno
);
490 iter
.skip_subrtxes ();
494 /* If this is a cast from one mode to another, where the modes
495 have the same size, and they are not tieable, then mark this
496 register as non-decomposable. If we decompose it we are
497 likely to mess up whatever the backend is trying to do. */
499 && outer_size
== inner_size
500 && !targetm
.modes_tieable_p (GET_MODE (x
), GET_MODE (inner
)))
502 bitmap_set_bit (non_decomposable_context
, regno
);
503 bitmap_set_bit (subreg_context
, regno
);
504 iter
.skip_subrtxes ();
512 /* We will see an outer SUBREG before we see the inner REG, so
513 when we see a plain REG here it means a direct reference to
516 If this is not a simple copy from one location to another,
517 then we can not decompose this register. If this is a simple
518 copy we want to decompose, and the mode is right,
519 then we mark the register as decomposable.
520 Otherwise we don't say anything about this register --
521 it could be decomposed, but whether that would be
522 profitable depends upon how it is used elsewhere.
524 We only set bits in the bitmap for multi-word
525 pseudo-registers, since those are the only ones we care about
526 and it keeps the size of the bitmaps down. */
529 if (!HARD_REGISTER_NUM_P (regno
)
530 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
534 case NOT_SIMPLE_MOVE
:
535 bitmap_set_bit (non_decomposable_context
, regno
);
537 case DECOMPOSABLE_SIMPLE_MOVE
:
538 if (targetm
.modes_tieable_p (GET_MODE (x
), word_mode
))
539 bitmap_set_bit (decomposable_context
, regno
);
550 enum classify_move_insn cmi_mem
= NOT_SIMPLE_MOVE
;
552 /* Any registers used in a MEM do not participate in a
553 SIMPLE_MOVE or DECOMPOSABLE_SIMPLE_MOVE. Do our own recursion
554 here, and return -1 to block the parent's recursion. */
555 find_decomposable_subregs (&XEXP (x
, 0), &cmi_mem
);
556 iter
.skip_subrtxes ();
561 /* Decompose REGNO into word-sized components. We smash the REG node
562 in place. This ensures that (1) something goes wrong quickly if we
563 fail to make some replacement, and (2) the debug information inside
564 the symbol table is automatically kept up to date. */
567 decompose_register (unsigned int regno
)
570 unsigned int words
, i
;
573 reg
= regno_reg_rtx
[regno
];
575 regno_reg_rtx
[regno
] = NULL_RTX
;
577 words
= GET_MODE_SIZE (GET_MODE (reg
));
578 words
= (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
580 v
= rtvec_alloc (words
);
581 for (i
= 0; i
< words
; ++i
)
582 RTVEC_ELT (v
, i
) = gen_reg_rtx_offset (reg
, word_mode
, i
* UNITS_PER_WORD
);
584 PUT_CODE (reg
, CONCATN
);
589 fprintf (dump_file
, "; Splitting reg %u ->", regno
);
590 for (i
= 0; i
< words
; ++i
)
591 fprintf (dump_file
, " %u", REGNO (XVECEXP (reg
, 0, i
)));
592 fputc ('\n', dump_file
);
596 /* Get a SUBREG of a CONCATN. */
599 simplify_subreg_concatn (machine_mode outermode
, rtx op
,
602 unsigned int inner_size
;
603 machine_mode innermode
, partmode
;
605 unsigned int final_offset
;
607 gcc_assert (GET_CODE (op
) == CONCATN
);
608 gcc_assert (byte
% GET_MODE_SIZE (outermode
) == 0);
610 innermode
= GET_MODE (op
);
611 gcc_assert (byte
< GET_MODE_SIZE (innermode
));
612 if (GET_MODE_SIZE (outermode
) > GET_MODE_SIZE (innermode
))
615 inner_size
= GET_MODE_SIZE (innermode
) / XVECLEN (op
, 0);
616 part
= XVECEXP (op
, 0, byte
/ inner_size
);
617 partmode
= GET_MODE (part
);
619 /* VECTOR_CSTs in debug expressions are expanded into CONCATN instead of
620 regular CONST_VECTORs. They have vector or integer modes, depending
621 on the capabilities of the target. Cope with them. */
622 if (partmode
== VOIDmode
&& VECTOR_MODE_P (innermode
))
623 partmode
= GET_MODE_INNER (innermode
);
624 else if (partmode
== VOIDmode
)
626 enum mode_class mclass
= GET_MODE_CLASS (innermode
);
627 partmode
= mode_for_size (inner_size
* BITS_PER_UNIT
, mclass
, 0);
630 final_offset
= byte
% inner_size
;
631 if (final_offset
+ GET_MODE_SIZE (outermode
) > inner_size
)
634 return simplify_gen_subreg (outermode
, part
, partmode
, final_offset
);
637 /* Wrapper around simplify_gen_subreg which handles CONCATN. */
640 simplify_gen_subreg_concatn (machine_mode outermode
, rtx op
,
641 machine_mode innermode
, unsigned int byte
)
645 /* We have to handle generating a SUBREG of a SUBREG of a CONCATN.
646 If OP is a SUBREG of a CONCATN, then it must be a simple mode
647 change with the same size and offset 0, or it must extract a
648 part. We shouldn't see anything else here. */
649 if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == CONCATN
)
653 if ((GET_MODE_SIZE (GET_MODE (op
))
654 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
655 && SUBREG_BYTE (op
) == 0)
656 return simplify_gen_subreg_concatn (outermode
, SUBREG_REG (op
),
657 GET_MODE (SUBREG_REG (op
)), byte
);
659 op2
= simplify_subreg_concatn (GET_MODE (op
), SUBREG_REG (op
),
663 /* We don't handle paradoxical subregs here. */
664 gcc_assert (!paradoxical_subreg_p (outermode
, GET_MODE (op
)));
665 gcc_assert (!paradoxical_subreg_p (op
));
666 op2
= simplify_subreg_concatn (outermode
, SUBREG_REG (op
),
667 byte
+ SUBREG_BYTE (op
));
668 gcc_assert (op2
!= NULL_RTX
);
673 gcc_assert (op
!= NULL_RTX
);
674 gcc_assert (innermode
== GET_MODE (op
));
677 if (GET_CODE (op
) == CONCATN
)
678 return simplify_subreg_concatn (outermode
, op
, byte
);
680 ret
= simplify_gen_subreg (outermode
, op
, innermode
, byte
);
682 /* If we see an insn like (set (reg:DI) (subreg:DI (reg:SI) 0)) then
683 resolve_simple_move will ask for the high part of the paradoxical
684 subreg, which does not have a value. Just return a zero. */
686 && paradoxical_subreg_p (op
))
687 return CONST0_RTX (outermode
);
689 gcc_assert (ret
!= NULL_RTX
);
693 /* Return whether we should resolve X into the registers into which it
697 resolve_reg_p (rtx x
)
699 return GET_CODE (x
) == CONCATN
;
702 /* Return whether X is a SUBREG of a register which we need to
706 resolve_subreg_p (rtx x
)
708 if (GET_CODE (x
) != SUBREG
)
710 return resolve_reg_p (SUBREG_REG (x
));
713 /* Look for SUBREGs in *LOC which need to be decomposed. */
716 resolve_subreg_use (rtx
*loc
, rtx insn
)
718 subrtx_ptr_iterator::array_type array
;
719 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, NONCONST
)
723 if (resolve_subreg_p (x
))
725 x
= simplify_subreg_concatn (GET_MODE (x
), SUBREG_REG (x
),
728 /* It is possible for a note to contain a reference which we can
729 decompose. In this case, return 1 to the caller to indicate
730 that the note must be removed. */
737 validate_change (insn
, loc
, x
, 1);
738 iter
.skip_subrtxes ();
740 else if (resolve_reg_p (x
))
741 /* Return 1 to the caller to indicate that we found a direct
742 reference to a register which is being decomposed. This can
743 happen inside notes, multiword shift or zero-extend
751 /* Resolve any decomposed registers which appear in register notes on
755 resolve_reg_notes (rtx_insn
*insn
)
759 note
= find_reg_equal_equiv_note (insn
);
762 int old_count
= num_validated_changes ();
763 if (resolve_subreg_use (&XEXP (note
, 0), NULL_RTX
))
764 remove_note (insn
, note
);
766 if (old_count
!= num_validated_changes ())
767 df_notes_rescan (insn
);
770 pnote
= ®_NOTES (insn
);
771 while (*pnote
!= NULL_RTX
)
776 switch (REG_NOTE_KIND (note
))
780 if (resolve_reg_p (XEXP (note
, 0)))
789 *pnote
= XEXP (note
, 1);
791 pnote
= &XEXP (note
, 1);
795 /* Return whether X can be decomposed into subwords. */
798 can_decompose_p (rtx x
)
802 unsigned int regno
= REGNO (x
);
804 if (HARD_REGISTER_NUM_P (regno
))
806 unsigned int byte
, num_bytes
;
808 num_bytes
= GET_MODE_SIZE (GET_MODE (x
));
809 for (byte
= 0; byte
< num_bytes
; byte
+= UNITS_PER_WORD
)
810 if (simplify_subreg_regno (regno
, GET_MODE (x
), byte
, word_mode
) < 0)
815 return !bitmap_bit_p (subreg_context
, regno
);
821 /* Decompose the registers used in a simple move SET within INSN. If
822 we don't change anything, return INSN, otherwise return the start
823 of the sequence of moves. */
826 resolve_simple_move (rtx set
, rtx_insn
*insn
)
828 rtx src
, dest
, real_dest
;
830 machine_mode orig_mode
, dest_mode
;
835 dest
= SET_DEST (set
);
836 orig_mode
= GET_MODE (dest
);
838 words
= (GET_MODE_SIZE (orig_mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
839 gcc_assert (words
> 1);
843 /* We have to handle copying from a SUBREG of a decomposed reg where
844 the SUBREG is larger than word size. Rather than assume that we
845 can take a word_mode SUBREG of the destination, we copy to a new
846 register and then copy that to the destination. */
848 real_dest
= NULL_RTX
;
850 if (GET_CODE (src
) == SUBREG
851 && resolve_reg_p (SUBREG_REG (src
))
852 && (SUBREG_BYTE (src
) != 0
853 || (GET_MODE_SIZE (orig_mode
)
854 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))))
857 dest
= gen_reg_rtx (orig_mode
);
858 if (REG_P (real_dest
))
859 REG_ATTRS (dest
) = REG_ATTRS (real_dest
);
862 /* Similarly if we are copying to a SUBREG of a decomposed reg where
863 the SUBREG is larger than word size. */
865 if (GET_CODE (dest
) == SUBREG
866 && resolve_reg_p (SUBREG_REG (dest
))
867 && (SUBREG_BYTE (dest
) != 0
868 || (GET_MODE_SIZE (orig_mode
)
869 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
))))))
874 reg
= gen_reg_rtx (orig_mode
);
875 minsn
= emit_move_insn (reg
, src
);
876 smove
= single_set (minsn
);
877 gcc_assert (smove
!= NULL_RTX
);
878 resolve_simple_move (smove
, minsn
);
882 /* If we didn't have any big SUBREGS of decomposed registers, and
883 neither side of the move is a register we are decomposing, then
884 we don't have to do anything here. */
886 if (src
== SET_SRC (set
)
887 && dest
== SET_DEST (set
)
888 && !resolve_reg_p (src
)
889 && !resolve_subreg_p (src
)
890 && !resolve_reg_p (dest
)
891 && !resolve_subreg_p (dest
))
897 /* It's possible for the code to use a subreg of a decomposed
898 register while forming an address. We need to handle that before
899 passing the address to emit_move_insn. We pass NULL_RTX as the
900 insn parameter to resolve_subreg_use because we can not validate
902 if (MEM_P (src
) || MEM_P (dest
))
907 resolve_subreg_use (&XEXP (src
, 0), NULL_RTX
);
909 resolve_subreg_use (&XEXP (dest
, 0), NULL_RTX
);
910 acg
= apply_change_group ();
914 /* If SRC is a register which we can't decompose, or has side
915 effects, we need to move via a temporary register. */
917 if (!can_decompose_p (src
)
918 || side_effects_p (src
)
919 || GET_CODE (src
) == ASM_OPERANDS
)
923 reg
= gen_reg_rtx (orig_mode
);
927 rtx_insn
*move
= emit_move_insn (reg
, src
);
930 rtx note
= find_reg_note (insn
, REG_INC
, NULL_RTX
);
932 add_reg_note (move
, REG_INC
, XEXP (note
, 0));
936 emit_move_insn (reg
, src
);
941 /* If DEST is a register which we can't decompose, or has side
942 effects, we need to first move to a temporary register. We
943 handle the common case of pushing an operand directly. We also
944 go through a temporary register if it holds a floating point
945 value. This gives us better code on systems which can't move
946 data easily between integer and floating point registers. */
948 dest_mode
= orig_mode
;
949 pushing
= push_operand (dest
, dest_mode
);
950 if (!can_decompose_p (dest
)
951 || (side_effects_p (dest
) && !pushing
)
952 || (!SCALAR_INT_MODE_P (dest_mode
)
953 && !resolve_reg_p (dest
)
954 && !resolve_subreg_p (dest
)))
956 if (real_dest
== NULL_RTX
)
958 if (!SCALAR_INT_MODE_P (dest_mode
))
960 dest_mode
= mode_for_size (GET_MODE_SIZE (dest_mode
) * BITS_PER_UNIT
,
962 gcc_assert (dest_mode
!= BLKmode
);
964 dest
= gen_reg_rtx (dest_mode
);
965 if (REG_P (real_dest
))
966 REG_ATTRS (dest
) = REG_ATTRS (real_dest
);
971 unsigned int i
, j
, jinc
;
973 gcc_assert (GET_MODE_SIZE (orig_mode
) % UNITS_PER_WORD
== 0);
974 gcc_assert (GET_CODE (XEXP (dest
, 0)) != PRE_MODIFY
);
975 gcc_assert (GET_CODE (XEXP (dest
, 0)) != POST_MODIFY
);
977 if (WORDS_BIG_ENDIAN
== STACK_GROWS_DOWNWARD
)
988 for (i
= 0; i
< words
; ++i
, j
+= jinc
)
992 temp
= copy_rtx (XEXP (dest
, 0));
993 temp
= adjust_automodify_address_nv (dest
, word_mode
, temp
,
995 emit_move_insn (temp
,
996 simplify_gen_subreg_concatn (word_mode
, src
,
998 j
* UNITS_PER_WORD
));
1005 if (REG_P (dest
) && !HARD_REGISTER_NUM_P (REGNO (dest
)))
1006 emit_clobber (dest
);
1008 for (i
= 0; i
< words
; ++i
)
1009 emit_move_insn (simplify_gen_subreg_concatn (word_mode
, dest
,
1011 i
* UNITS_PER_WORD
),
1012 simplify_gen_subreg_concatn (word_mode
, src
,
1014 i
* UNITS_PER_WORD
));
1017 if (real_dest
!= NULL_RTX
)
1022 if (dest_mode
== orig_mode
)
1025 mdest
= simplify_gen_subreg (orig_mode
, dest
, GET_MODE (dest
), 0);
1026 minsn
= emit_move_insn (real_dest
, mdest
);
1028 if (AUTO_INC_DEC
&& MEM_P (real_dest
)
1029 && !(resolve_reg_p (real_dest
) || resolve_subreg_p (real_dest
)))
1031 rtx note
= find_reg_note (insn
, REG_INC
, NULL_RTX
);
1033 add_reg_note (minsn
, REG_INC
, XEXP (note
, 0));
1036 smove
= single_set (minsn
);
1037 gcc_assert (smove
!= NULL_RTX
);
1039 resolve_simple_move (smove
, minsn
);
1042 insns
= get_insns ();
1045 copy_reg_eh_region_note_forward (insn
, insns
, NULL_RTX
);
1047 emit_insn_before (insns
, insn
);
1049 /* If we get here via self-recursion, then INSN is not yet in the insns
1050 chain and delete_insn will fail. We only want to remove INSN from the
1051 current sequence. See PR56738. */
1052 if (in_sequence_p ())
1060 /* Change a CLOBBER of a decomposed register into a CLOBBER of the
1061 component registers. Return whether we changed something. */
1064 resolve_clobber (rtx pat
, rtx_insn
*insn
)
1067 machine_mode orig_mode
;
1068 unsigned int words
, i
;
1071 reg
= XEXP (pat
, 0);
1072 if (!resolve_reg_p (reg
) && !resolve_subreg_p (reg
))
1075 orig_mode
= GET_MODE (reg
);
1076 words
= GET_MODE_SIZE (orig_mode
);
1077 words
= (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1079 ret
= validate_change (NULL_RTX
, &XEXP (pat
, 0),
1080 simplify_gen_subreg_concatn (word_mode
, reg
,
1083 df_insn_rescan (insn
);
1084 gcc_assert (ret
!= 0);
1086 for (i
= words
- 1; i
> 0; --i
)
1090 x
= simplify_gen_subreg_concatn (word_mode
, reg
, orig_mode
,
1091 i
* UNITS_PER_WORD
);
1092 x
= gen_rtx_CLOBBER (VOIDmode
, x
);
1093 emit_insn_after (x
, insn
);
1096 resolve_reg_notes (insn
);
1101 /* A USE of a decomposed register is no longer meaningful. Return
1102 whether we changed something. */
1105 resolve_use (rtx pat
, rtx_insn
*insn
)
1107 if (resolve_reg_p (XEXP (pat
, 0)) || resolve_subreg_p (XEXP (pat
, 0)))
1113 resolve_reg_notes (insn
);
1118 /* A VAR_LOCATION can be simplified. */
1121 resolve_debug (rtx_insn
*insn
)
1123 subrtx_ptr_iterator::array_type array
;
1124 FOR_EACH_SUBRTX_PTR (iter
, array
, &PATTERN (insn
), NONCONST
)
1128 if (resolve_subreg_p (x
))
1130 x
= simplify_subreg_concatn (GET_MODE (x
), SUBREG_REG (x
),
1136 x
= copy_rtx (*loc
);
1138 if (resolve_reg_p (x
))
1139 *loc
= copy_rtx (x
);
1142 df_insn_rescan (insn
);
1144 resolve_reg_notes (insn
);
1147 /* Check if INSN is a decomposable multiword-shift or zero-extend and
1148 set the decomposable_context bitmap accordingly. SPEED_P is true
1149 if we are optimizing INSN for speed rather than size. Return true
1150 if INSN is decomposable. */
1153 find_decomposable_shift_zext (rtx_insn
*insn
, bool speed_p
)
1159 set
= single_set (insn
);
1164 if (GET_CODE (op
) != ASHIFT
1165 && GET_CODE (op
) != LSHIFTRT
1166 && GET_CODE (op
) != ASHIFTRT
1167 && GET_CODE (op
) != ZERO_EXTEND
)
1170 op_operand
= XEXP (op
, 0);
1171 if (!REG_P (SET_DEST (set
)) || !REG_P (op_operand
)
1172 || HARD_REGISTER_NUM_P (REGNO (SET_DEST (set
)))
1173 || HARD_REGISTER_NUM_P (REGNO (op_operand
))
1174 || GET_MODE (op
) != twice_word_mode
)
1177 if (GET_CODE (op
) == ZERO_EXTEND
)
1179 if (GET_MODE (op_operand
) != word_mode
1180 || !choices
[speed_p
].splitting_zext
)
1183 else /* left or right shift */
1185 bool *splitting
= (GET_CODE (op
) == ASHIFT
1186 ? choices
[speed_p
].splitting_ashift
1187 : GET_CODE (op
) == ASHIFTRT
1188 ? choices
[speed_p
].splitting_ashiftrt
1189 : choices
[speed_p
].splitting_lshiftrt
);
1190 if (!CONST_INT_P (XEXP (op
, 1))
1191 || !IN_RANGE (INTVAL (XEXP (op
, 1)), BITS_PER_WORD
,
1192 2 * BITS_PER_WORD
- 1)
1193 || !splitting
[INTVAL (XEXP (op
, 1)) - BITS_PER_WORD
])
1196 bitmap_set_bit (decomposable_context
, REGNO (op_operand
));
1199 bitmap_set_bit (decomposable_context
, REGNO (SET_DEST (set
)));
1204 /* Decompose a more than word wide shift (in INSN) of a multiword
1205 pseudo or a multiword zero-extend of a wordmode pseudo into a move
1206 and 'set to zero' insn. Return a pointer to the new insn when a
1207 replacement was done. */
1210 resolve_shift_zext (rtx_insn
*insn
)
1216 rtx src_reg
, dest_reg
, dest_upper
, upper_src
= NULL_RTX
;
1217 int src_reg_num
, dest_reg_num
, offset1
, offset2
, src_offset
;
1218 scalar_int_mode inner_mode
;
1220 set
= single_set (insn
);
1225 if (GET_CODE (op
) != ASHIFT
1226 && GET_CODE (op
) != LSHIFTRT
1227 && GET_CODE (op
) != ASHIFTRT
1228 && GET_CODE (op
) != ZERO_EXTEND
)
1231 op_operand
= XEXP (op
, 0);
1232 if (!is_a
<scalar_int_mode
> (GET_MODE (op_operand
), &inner_mode
))
1235 /* We can tear this operation apart only if the regs were already
1237 if (!resolve_reg_p (SET_DEST (set
)) && !resolve_reg_p (op_operand
))
1240 /* src_reg_num is the number of the word mode register which we
1241 are operating on. For a left shift and a zero_extend on little
1242 endian machines this is register 0. */
1243 src_reg_num
= (GET_CODE (op
) == LSHIFTRT
|| GET_CODE (op
) == ASHIFTRT
)
1246 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
1247 src_reg_num
= 1 - src_reg_num
;
1249 if (GET_CODE (op
) == ZERO_EXTEND
)
1250 dest_reg_num
= WORDS_BIG_ENDIAN
? 1 : 0;
1252 dest_reg_num
= 1 - src_reg_num
;
1254 offset1
= UNITS_PER_WORD
* dest_reg_num
;
1255 offset2
= UNITS_PER_WORD
* (1 - dest_reg_num
);
1256 src_offset
= UNITS_PER_WORD
* src_reg_num
;
1260 dest_reg
= simplify_gen_subreg_concatn (word_mode
, SET_DEST (set
),
1261 GET_MODE (SET_DEST (set
)),
1263 dest_upper
= simplify_gen_subreg_concatn (word_mode
, SET_DEST (set
),
1264 GET_MODE (SET_DEST (set
)),
1266 src_reg
= simplify_gen_subreg_concatn (word_mode
, op_operand
,
1267 GET_MODE (op_operand
),
1269 if (GET_CODE (op
) == ASHIFTRT
1270 && INTVAL (XEXP (op
, 1)) != 2 * BITS_PER_WORD
- 1)
1271 upper_src
= expand_shift (RSHIFT_EXPR
, word_mode
, copy_rtx (src_reg
),
1272 BITS_PER_WORD
- 1, NULL_RTX
, 0);
1274 if (GET_CODE (op
) != ZERO_EXTEND
)
1276 int shift_count
= INTVAL (XEXP (op
, 1));
1277 if (shift_count
> BITS_PER_WORD
)
1278 src_reg
= expand_shift (GET_CODE (op
) == ASHIFT
?
1279 LSHIFT_EXPR
: RSHIFT_EXPR
,
1281 shift_count
- BITS_PER_WORD
,
1282 dest_reg
, GET_CODE (op
) != ASHIFTRT
);
1285 if (dest_reg
!= src_reg
)
1286 emit_move_insn (dest_reg
, src_reg
);
1287 if (GET_CODE (op
) != ASHIFTRT
)
1288 emit_move_insn (dest_upper
, CONST0_RTX (word_mode
));
1289 else if (INTVAL (XEXP (op
, 1)) == 2 * BITS_PER_WORD
- 1)
1290 emit_move_insn (dest_upper
, copy_rtx (src_reg
));
1292 emit_move_insn (dest_upper
, upper_src
);
1293 insns
= get_insns ();
1297 emit_insn_before (insns
, insn
);
1302 fprintf (dump_file
, "; Replacing insn: %d with insns: ", INSN_UID (insn
));
1303 for (in
= insns
; in
!= insn
; in
= NEXT_INSN (in
))
1304 fprintf (dump_file
, "%d ", INSN_UID (in
));
1305 fprintf (dump_file
, "\n");
1312 /* Print to dump_file a description of what we're doing with shift code CODE.
1313 SPLITTING[X] is true if we are splitting shifts by X + BITS_PER_WORD. */
1316 dump_shift_choices (enum rtx_code code
, bool *splitting
)
1322 " Splitting mode %s for %s lowering with shift amounts = ",
1323 GET_MODE_NAME (twice_word_mode
), GET_RTX_NAME (code
));
1325 for (i
= 0; i
< BITS_PER_WORD
; i
++)
1328 fprintf (dump_file
, "%s%d", sep
, i
+ BITS_PER_WORD
);
1331 fprintf (dump_file
, "\n");
1334 /* Print to dump_file a description of what we're doing when optimizing
1335 for speed or size; SPEED_P says which. DESCRIPTION is a description
1336 of the SPEED_P choice. */
1339 dump_choices (bool speed_p
, const char *description
)
1343 fprintf (dump_file
, "Choices when optimizing for %s:\n", description
);
1345 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
1346 if (GET_MODE_SIZE ((machine_mode
) i
) > UNITS_PER_WORD
)
1347 fprintf (dump_file
, " %s mode %s for copy lowering.\n",
1348 choices
[speed_p
].move_modes_to_split
[i
]
1351 GET_MODE_NAME ((machine_mode
) i
));
1353 fprintf (dump_file
, " %s mode %s for zero_extend lowering.\n",
1354 choices
[speed_p
].splitting_zext
? "Splitting" : "Skipping",
1355 GET_MODE_NAME (twice_word_mode
));
1357 dump_shift_choices (ASHIFT
, choices
[speed_p
].splitting_ashift
);
1358 dump_shift_choices (LSHIFTRT
, choices
[speed_p
].splitting_lshiftrt
);
1359 dump_shift_choices (ASHIFTRT
, choices
[speed_p
].splitting_ashiftrt
);
1360 fprintf (dump_file
, "\n");
1363 /* Look for registers which are always accessed via word-sized SUBREGs
1364 or -if DECOMPOSE_COPIES is true- via copies. Decompose these
1365 registers into several word-sized pseudo-registers. */
1368 decompose_multiword_subregs (bool decompose_copies
)
1376 dump_choices (false, "size");
1377 dump_choices (true, "speed");
1380 /* Check if this target even has any modes to consider lowering. */
1381 if (!choices
[false].something_to_do
&& !choices
[true].something_to_do
)
1384 fprintf (dump_file
, "Nothing to do!\n");
1388 max
= max_reg_num ();
1390 /* First see if there are any multi-word pseudo-registers. If there
1391 aren't, there is nothing we can do. This should speed up this
1392 pass in the normal case, since it should be faster than scanning
1396 bool useful_modes_seen
= false;
1398 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; ++i
)
1399 if (regno_reg_rtx
[i
] != NULL
)
1401 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
1402 if (choices
[false].move_modes_to_split
[(int) mode
]
1403 || choices
[true].move_modes_to_split
[(int) mode
])
1405 useful_modes_seen
= true;
1410 if (!useful_modes_seen
)
1413 fprintf (dump_file
, "Nothing to lower in this function.\n");
1420 df_set_flags (DF_DEFER_INSN_RESCAN
);
1424 /* FIXME: It may be possible to change this code to look for each
1425 multi-word pseudo-register and to find each insn which sets or
1426 uses that register. That should be faster than scanning all the
1429 decomposable_context
= BITMAP_ALLOC (NULL
);
1430 non_decomposable_context
= BITMAP_ALLOC (NULL
);
1431 subreg_context
= BITMAP_ALLOC (NULL
);
1433 reg_copy_graph
.create (max
);
1434 reg_copy_graph
.safe_grow_cleared (max
);
1435 memset (reg_copy_graph
.address (), 0, sizeof (bitmap
) * max
);
1437 speed_p
= optimize_function_for_speed_p (cfun
);
1438 FOR_EACH_BB_FN (bb
, cfun
)
1442 FOR_BB_INSNS (bb
, insn
)
1445 enum classify_move_insn cmi
;
1449 || GET_CODE (PATTERN (insn
)) == CLOBBER
1450 || GET_CODE (PATTERN (insn
)) == USE
)
1453 recog_memoized (insn
);
1455 if (find_decomposable_shift_zext (insn
, speed_p
))
1458 extract_insn (insn
);
1460 set
= simple_move (insn
, speed_p
);
1463 cmi
= NOT_SIMPLE_MOVE
;
1466 /* We mark pseudo-to-pseudo copies as decomposable during the
1467 second pass only. The first pass is so early that there is
1468 good chance such moves will be optimized away completely by
1469 subsequent optimizations anyway.
1471 However, we call find_pseudo_copy even during the first pass
1472 so as to properly set up the reg_copy_graph. */
1473 if (find_pseudo_copy (set
))
1474 cmi
= decompose_copies
? DECOMPOSABLE_SIMPLE_MOVE
: SIMPLE_MOVE
;
1479 n
= recog_data
.n_operands
;
1480 for (i
= 0; i
< n
; ++i
)
1482 find_decomposable_subregs (&recog_data
.operand
[i
], &cmi
);
1484 /* We handle ASM_OPERANDS as a special case to support
1485 things like x86 rdtsc which returns a DImode value.
1486 We can decompose the output, which will certainly be
1487 operand 0, but not the inputs. */
1489 if (cmi
== SIMPLE_MOVE
1490 && GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1492 gcc_assert (i
== 0);
1493 cmi
= NOT_SIMPLE_MOVE
;
1499 bitmap_and_compl_into (decomposable_context
, non_decomposable_context
);
1500 if (!bitmap_empty_p (decomposable_context
))
1503 sbitmap_iterator sbi
;
1504 bitmap_iterator iter
;
1507 propagate_pseudo_copies ();
1509 auto_sbitmap
sub_blocks (last_basic_block_for_fn (cfun
));
1510 bitmap_clear (sub_blocks
);
1512 EXECUTE_IF_SET_IN_BITMAP (decomposable_context
, 0, regno
, iter
)
1513 decompose_register (regno
);
1515 FOR_EACH_BB_FN (bb
, cfun
)
1519 FOR_BB_INSNS (bb
, insn
)
1526 pat
= PATTERN (insn
);
1527 if (GET_CODE (pat
) == CLOBBER
)
1528 resolve_clobber (pat
, insn
);
1529 else if (GET_CODE (pat
) == USE
)
1530 resolve_use (pat
, insn
);
1531 else if (DEBUG_INSN_P (insn
))
1532 resolve_debug (insn
);
1538 recog_memoized (insn
);
1539 extract_insn (insn
);
1541 set
= simple_move (insn
, speed_p
);
1544 rtx_insn
*orig_insn
= insn
;
1545 bool cfi
= control_flow_insn_p (insn
);
1547 /* We can end up splitting loads to multi-word pseudos
1548 into separate loads to machine word size pseudos.
1549 When this happens, we first had one load that can
1550 throw, and after resolve_simple_move we'll have a
1551 bunch of loads (at least two). All those loads may
1552 trap if we can have non-call exceptions, so they
1553 all will end the current basic block. We split the
1554 block after the outer loop over all insns, but we
1555 make sure here that we will be able to split the
1556 basic block and still produce the correct control
1557 flow graph for it. */
1559 || (cfun
->can_throw_non_call_exceptions
1560 && can_throw_internal (insn
)));
1562 insn
= resolve_simple_move (set
, insn
);
1563 if (insn
!= orig_insn
)
1565 recog_memoized (insn
);
1566 extract_insn (insn
);
1569 bitmap_set_bit (sub_blocks
, bb
->index
);
1574 rtx_insn
*decomposed_shift
;
1576 decomposed_shift
= resolve_shift_zext (insn
);
1577 if (decomposed_shift
!= NULL_RTX
)
1579 insn
= decomposed_shift
;
1580 recog_memoized (insn
);
1581 extract_insn (insn
);
1585 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
1586 resolve_subreg_use (recog_data
.operand_loc
[i
], insn
);
1588 resolve_reg_notes (insn
);
1590 if (num_validated_changes () > 0)
1592 for (i
= recog_data
.n_dups
- 1; i
>= 0; --i
)
1594 rtx
*pl
= recog_data
.dup_loc
[i
];
1595 int dup_num
= recog_data
.dup_num
[i
];
1596 rtx
*px
= recog_data
.operand_loc
[dup_num
];
1598 validate_unshare_change (insn
, pl
, *px
, 1);
1601 i
= apply_change_group ();
1608 /* If we had insns to split that caused control flow insns in the middle
1609 of a basic block, split those blocks now. Note that we only handle
1610 the case where splitting a load has caused multiple possibly trapping
1612 EXECUTE_IF_SET_IN_BITMAP (sub_blocks
, 0, i
, sbi
)
1614 rtx_insn
*insn
, *end
;
1617 bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
1618 insn
= BB_HEAD (bb
);
1623 if (control_flow_insn_p (insn
))
1625 /* Split the block after insn. There will be a fallthru
1626 edge, which is OK so we keep it. We have to create the
1627 exception edges ourselves. */
1628 fallthru
= split_block (bb
, insn
);
1629 rtl_make_eh_edge (NULL
, bb
, BB_END (bb
));
1630 bb
= fallthru
->dest
;
1631 insn
= BB_HEAD (bb
);
1634 insn
= NEXT_INSN (insn
);
1643 FOR_EACH_VEC_ELT (reg_copy_graph
, i
, b
)
1648 reg_copy_graph
.release ();
1650 BITMAP_FREE (decomposable_context
);
1651 BITMAP_FREE (non_decomposable_context
);
1652 BITMAP_FREE (subreg_context
);
1655 /* Implement first lower subreg pass. */
1659 const pass_data pass_data_lower_subreg
=
1661 RTL_PASS
, /* type */
1662 "subreg1", /* name */
1663 OPTGROUP_NONE
, /* optinfo_flags */
1664 TV_LOWER_SUBREG
, /* tv_id */
1665 0, /* properties_required */
1666 0, /* properties_provided */
1667 0, /* properties_destroyed */
1668 0, /* todo_flags_start */
1669 0, /* todo_flags_finish */
1672 class pass_lower_subreg
: public rtl_opt_pass
1675 pass_lower_subreg (gcc::context
*ctxt
)
1676 : rtl_opt_pass (pass_data_lower_subreg
, ctxt
)
1679 /* opt_pass methods: */
1680 virtual bool gate (function
*) { return flag_split_wide_types
!= 0; }
1681 virtual unsigned int execute (function
*)
1683 decompose_multiword_subregs (false);
1687 }; // class pass_lower_subreg
1692 make_pass_lower_subreg (gcc::context
*ctxt
)
1694 return new pass_lower_subreg (ctxt
);
1697 /* Implement second lower subreg pass. */
1701 const pass_data pass_data_lower_subreg2
=
1703 RTL_PASS
, /* type */
1704 "subreg2", /* name */
1705 OPTGROUP_NONE
, /* optinfo_flags */
1706 TV_LOWER_SUBREG
, /* tv_id */
1707 0, /* properties_required */
1708 0, /* properties_provided */
1709 0, /* properties_destroyed */
1710 0, /* todo_flags_start */
1711 TODO_df_finish
, /* todo_flags_finish */
1714 class pass_lower_subreg2
: public rtl_opt_pass
1717 pass_lower_subreg2 (gcc::context
*ctxt
)
1718 : rtl_opt_pass (pass_data_lower_subreg2
, ctxt
)
1721 /* opt_pass methods: */
1722 virtual bool gate (function
*) { return flag_split_wide_types
!= 0; }
1723 virtual unsigned int execute (function
*)
1725 decompose_multiword_subregs (true);
1729 }; // class pass_lower_subreg2
1734 make_pass_lower_subreg2 (gcc::context
*ctxt
)
1736 return new pass_lower_subreg2 (ctxt
);