1 /* Decompose multiword subregs.
2 Copyright (C) 2007-2015 Free Software Foundation, Inc.
3 Contributed by Richard Henderson <rth@redhat.com>
4 Ian Lance Taylor <iant@google.com>
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
33 #include "insn-config.h"
49 #include "tree-pass.h"
50 #include "lower-subreg.h"
54 /* Decompose multi-word pseudo-registers into individual
55 pseudo-registers when possible and profitable. This is possible
56 when all the uses of a multi-word register are via SUBREG, or are
57 copies of the register to another location. Breaking apart the
58 register permits more CSE and permits better register allocation.
59 This is profitable if the machine does not have move instructions
62 This pass only splits moves with modes that are wider than
63 word_mode and ASHIFTs, LSHIFTRTs, ASHIFTRTs and ZERO_EXTENDs with
64 integer modes that are twice the width of word_mode. The latter
65 could be generalized if there was a need to do this, but the trend in
66 architectures is to not need this.
68 There are two useful preprocessor defines for use by maintainers:
72 if you wish to see the actual cost estimates that are being used
73 for each mode wider than word mode and the cost estimates for zero
74 extension and the shifts. This can be useful when port maintainers
75 are tuning insn rtx costs.
77 #define FORCE_LOWERING 1
79 if you wish to test the pass with all the transformation forced on.
80 This can be useful for finding bugs in the transformations. */
83 #define FORCE_LOWERING 0
85 /* Bit N in this bitmap is set if regno N is used in a context in
86 which we can decompose it. */
87 static bitmap decomposable_context
;
89 /* Bit N in this bitmap is set if regno N is used in a context in
90 which it can not be decomposed. */
91 static bitmap non_decomposable_context
;
93 /* Bit N in this bitmap is set if regno N is used in a subreg
94 which changes the mode but not the size. This typically happens
95 when the register accessed as a floating-point value; we want to
96 avoid generating accesses to its subwords in integer modes. */
97 static bitmap subreg_context
;
99 /* Bit N in the bitmap in element M of this array is set if there is a
100 copy from reg M to reg N. */
101 static vec
<bitmap
> reg_copy_graph
;
103 struct target_lower_subreg default_target_lower_subreg
;
104 #if SWITCHABLE_TARGET
105 struct target_lower_subreg
*this_target_lower_subreg
106 = &default_target_lower_subreg
;
109 #define twice_word_mode \
110 this_target_lower_subreg->x_twice_word_mode
112 this_target_lower_subreg->x_choices
114 /* RTXes used while computing costs. */
116 /* Source and target registers. */
120 /* A twice_word_mode ZERO_EXTEND of SOURCE. */
123 /* A shift of SOURCE. */
126 /* A SET of TARGET. */
130 /* Return the cost of a CODE shift in mode MODE by OP1 bits, using the
131 rtxes in RTXES. SPEED_P selects between the speed and size cost. */
134 shift_cost (bool speed_p
, struct cost_rtxes
*rtxes
, enum rtx_code code
,
135 machine_mode mode
, int op1
)
137 PUT_CODE (rtxes
->shift
, code
);
138 PUT_MODE (rtxes
->shift
, mode
);
139 PUT_MODE (rtxes
->source
, mode
);
140 XEXP (rtxes
->shift
, 1) = GEN_INT (op1
);
141 return set_src_cost (rtxes
->shift
, mode
, speed_p
);
144 /* For each X in the range [0, BITS_PER_WORD), set SPLITTING[X]
145 to true if it is profitable to split a double-word CODE shift
146 of X + BITS_PER_WORD bits. SPEED_P says whether we are testing
147 for speed or size profitability.
149 Use the rtxes in RTXES to calculate costs. WORD_MOVE_ZERO_COST is
150 the cost of moving zero into a word-mode register. WORD_MOVE_COST
151 is the cost of moving between word registers. */
154 compute_splitting_shift (bool speed_p
, struct cost_rtxes
*rtxes
,
155 bool *splitting
, enum rtx_code code
,
156 int word_move_zero_cost
, int word_move_cost
)
158 int wide_cost
, narrow_cost
, upper_cost
, i
;
160 for (i
= 0; i
< BITS_PER_WORD
; i
++)
162 wide_cost
= shift_cost (speed_p
, rtxes
, code
, twice_word_mode
,
165 narrow_cost
= word_move_cost
;
167 narrow_cost
= shift_cost (speed_p
, rtxes
, code
, word_mode
, i
);
169 if (code
!= ASHIFTRT
)
170 upper_cost
= word_move_zero_cost
;
171 else if (i
== BITS_PER_WORD
- 1)
172 upper_cost
= word_move_cost
;
174 upper_cost
= shift_cost (speed_p
, rtxes
, code
, word_mode
,
178 fprintf (stderr
, "%s %s by %d: original cost %d, split cost %d + %d\n",
179 GET_MODE_NAME (twice_word_mode
), GET_RTX_NAME (code
),
180 i
+ BITS_PER_WORD
, wide_cost
, narrow_cost
, upper_cost
);
182 if (FORCE_LOWERING
|| wide_cost
>= narrow_cost
+ upper_cost
)
187 /* Compute what we should do when optimizing for speed or size; SPEED_P
188 selects which. Use RTXES for computing costs. */
191 compute_costs (bool speed_p
, struct cost_rtxes
*rtxes
)
194 int word_move_zero_cost
, word_move_cost
;
196 PUT_MODE (rtxes
->target
, word_mode
);
197 SET_SRC (rtxes
->set
) = CONST0_RTX (word_mode
);
198 word_move_zero_cost
= set_rtx_cost (rtxes
->set
, speed_p
);
200 SET_SRC (rtxes
->set
) = rtxes
->source
;
201 word_move_cost
= set_rtx_cost (rtxes
->set
, speed_p
);
204 fprintf (stderr
, "%s move: from zero cost %d, from reg cost %d\n",
205 GET_MODE_NAME (word_mode
), word_move_zero_cost
, word_move_cost
);
207 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
209 machine_mode mode
= (machine_mode
) i
;
210 int factor
= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
215 PUT_MODE (rtxes
->target
, mode
);
216 PUT_MODE (rtxes
->source
, mode
);
217 mode_move_cost
= set_rtx_cost (rtxes
->set
, speed_p
);
220 fprintf (stderr
, "%s move: original cost %d, split cost %d * %d\n",
221 GET_MODE_NAME (mode
), mode_move_cost
,
222 word_move_cost
, factor
);
224 if (FORCE_LOWERING
|| mode_move_cost
>= word_move_cost
* factor
)
226 choices
[speed_p
].move_modes_to_split
[i
] = true;
227 choices
[speed_p
].something_to_do
= true;
232 /* For the moves and shifts, the only case that is checked is one
233 where the mode of the target is an integer mode twice the width
236 If it is not profitable to split a double word move then do not
237 even consider the shifts or the zero extension. */
238 if (choices
[speed_p
].move_modes_to_split
[(int) twice_word_mode
])
242 /* The only case here to check to see if moving the upper part with a
243 zero is cheaper than doing the zext itself. */
244 PUT_MODE (rtxes
->source
, word_mode
);
245 zext_cost
= set_src_cost (rtxes
->zext
, twice_word_mode
, speed_p
);
248 fprintf (stderr
, "%s %s: original cost %d, split cost %d + %d\n",
249 GET_MODE_NAME (twice_word_mode
), GET_RTX_NAME (ZERO_EXTEND
),
250 zext_cost
, word_move_cost
, word_move_zero_cost
);
252 if (FORCE_LOWERING
|| zext_cost
>= word_move_cost
+ word_move_zero_cost
)
253 choices
[speed_p
].splitting_zext
= true;
255 compute_splitting_shift (speed_p
, rtxes
,
256 choices
[speed_p
].splitting_ashift
, ASHIFT
,
257 word_move_zero_cost
, word_move_cost
);
258 compute_splitting_shift (speed_p
, rtxes
,
259 choices
[speed_p
].splitting_lshiftrt
, LSHIFTRT
,
260 word_move_zero_cost
, word_move_cost
);
261 compute_splitting_shift (speed_p
, rtxes
,
262 choices
[speed_p
].splitting_ashiftrt
, ASHIFTRT
,
263 word_move_zero_cost
, word_move_cost
);
267 /* Do one-per-target initialisation. This involves determining
268 which operations on the machine are profitable. If none are found,
269 then the pass just returns when called. */
272 init_lower_subreg (void)
274 struct cost_rtxes rtxes
;
276 memset (this_target_lower_subreg
, 0, sizeof (*this_target_lower_subreg
));
278 twice_word_mode
= GET_MODE_2XWIDER_MODE (word_mode
);
280 rtxes
.target
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
281 rtxes
.source
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 2);
282 rtxes
.set
= gen_rtx_SET (rtxes
.target
, rtxes
.source
);
283 rtxes
.zext
= gen_rtx_ZERO_EXTEND (twice_word_mode
, rtxes
.source
);
284 rtxes
.shift
= gen_rtx_ASHIFT (twice_word_mode
, rtxes
.source
, const0_rtx
);
287 fprintf (stderr
, "\nSize costs\n==========\n\n");
288 compute_costs (false, &rtxes
);
291 fprintf (stderr
, "\nSpeed costs\n===========\n\n");
292 compute_costs (true, &rtxes
);
296 simple_move_operand (rtx x
)
298 if (GET_CODE (x
) == SUBREG
)
304 if (GET_CODE (x
) == LABEL_REF
305 || GET_CODE (x
) == SYMBOL_REF
306 || GET_CODE (x
) == HIGH
307 || GET_CODE (x
) == CONST
)
311 && (MEM_VOLATILE_P (x
)
312 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
))))
318 /* If INSN is a single set between two objects that we want to split,
319 return the single set. SPEED_P says whether we are optimizing
320 INSN for speed or size.
322 INSN should have been passed to recog and extract_insn before this
326 simple_move (rtx_insn
*insn
, bool speed_p
)
332 if (recog_data
.n_operands
!= 2)
335 set
= single_set (insn
);
340 if (x
!= recog_data
.operand
[0] && x
!= recog_data
.operand
[1])
342 if (!simple_move_operand (x
))
346 if (x
!= recog_data
.operand
[0] && x
!= recog_data
.operand
[1])
348 /* For the src we can handle ASM_OPERANDS, and it is beneficial for
349 things like x86 rdtsc which returns a DImode value. */
350 if (GET_CODE (x
) != ASM_OPERANDS
351 && !simple_move_operand (x
))
354 /* We try to decompose in integer modes, to avoid generating
355 inefficient code copying between integer and floating point
356 registers. That means that we can't decompose if this is a
357 non-integer mode for which there is no integer mode of the same
359 mode
= GET_MODE (SET_DEST (set
));
360 if (!SCALAR_INT_MODE_P (mode
)
361 && (mode_for_size (GET_MODE_SIZE (mode
) * BITS_PER_UNIT
, MODE_INT
, 0)
365 /* Reject PARTIAL_INT modes. They are used for processor specific
366 purposes and it's probably best not to tamper with them. */
367 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
370 if (!choices
[speed_p
].move_modes_to_split
[(int) mode
])
376 /* If SET is a copy from one multi-word pseudo-register to another,
377 record that in reg_copy_graph. Return whether it is such a
381 find_pseudo_copy (rtx set
)
383 rtx dest
= SET_DEST (set
);
384 rtx src
= SET_SRC (set
);
388 if (!REG_P (dest
) || !REG_P (src
))
393 if (HARD_REGISTER_NUM_P (rd
) || HARD_REGISTER_NUM_P (rs
))
396 b
= reg_copy_graph
[rs
];
399 b
= BITMAP_ALLOC (NULL
);
400 reg_copy_graph
[rs
] = b
;
403 bitmap_set_bit (b
, rd
);
408 /* Look through the registers in DECOMPOSABLE_CONTEXT. For each case
409 where they are copied to another register, add the register to
410 which they are copied to DECOMPOSABLE_CONTEXT. Use
411 NON_DECOMPOSABLE_CONTEXT to limit this--we don't bother to track
412 copies of registers which are in NON_DECOMPOSABLE_CONTEXT. */
415 propagate_pseudo_copies (void)
417 bitmap queue
, propagate
;
419 queue
= BITMAP_ALLOC (NULL
);
420 propagate
= BITMAP_ALLOC (NULL
);
422 bitmap_copy (queue
, decomposable_context
);
425 bitmap_iterator iter
;
428 bitmap_clear (propagate
);
430 EXECUTE_IF_SET_IN_BITMAP (queue
, 0, i
, iter
)
432 bitmap b
= reg_copy_graph
[i
];
434 bitmap_ior_and_compl_into (propagate
, b
, non_decomposable_context
);
437 bitmap_and_compl (queue
, propagate
, decomposable_context
);
438 bitmap_ior_into (decomposable_context
, propagate
);
440 while (!bitmap_empty_p (queue
));
443 BITMAP_FREE (propagate
);
446 /* A pointer to one of these values is passed to
447 find_decomposable_subregs. */
449 enum classify_move_insn
451 /* Not a simple move from one location to another. */
453 /* A simple move we want to decompose. */
454 DECOMPOSABLE_SIMPLE_MOVE
,
455 /* Any other simple move. */
459 /* If we find a SUBREG in *LOC which we could use to decompose a
460 pseudo-register, set a bit in DECOMPOSABLE_CONTEXT. If we find an
461 unadorned register which is not a simple pseudo-register copy,
462 DATA will point at the type of move, and we set a bit in
463 DECOMPOSABLE_CONTEXT or NON_DECOMPOSABLE_CONTEXT as appropriate. */
466 find_decomposable_subregs (rtx
*loc
, enum classify_move_insn
*pcmi
)
468 subrtx_var_iterator::array_type array
;
469 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
472 if (GET_CODE (x
) == SUBREG
)
474 rtx inner
= SUBREG_REG (x
);
475 unsigned int regno
, outer_size
, inner_size
, outer_words
, inner_words
;
480 regno
= REGNO (inner
);
481 if (HARD_REGISTER_NUM_P (regno
))
483 iter
.skip_subrtxes ();
487 outer_size
= GET_MODE_SIZE (GET_MODE (x
));
488 inner_size
= GET_MODE_SIZE (GET_MODE (inner
));
489 outer_words
= (outer_size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
490 inner_words
= (inner_size
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
492 /* We only try to decompose single word subregs of multi-word
493 registers. When we find one, we return -1 to avoid iterating
494 over the inner register.
496 ??? This doesn't allow, e.g., DImode subregs of TImode values
497 on 32-bit targets. We would need to record the way the
498 pseudo-register was used, and only decompose if all the uses
499 were the same number and size of pieces. Hopefully this
500 doesn't happen much. */
502 if (outer_words
== 1 && inner_words
> 1)
504 bitmap_set_bit (decomposable_context
, regno
);
505 iter
.skip_subrtxes ();
509 /* If this is a cast from one mode to another, where the modes
510 have the same size, and they are not tieable, then mark this
511 register as non-decomposable. If we decompose it we are
512 likely to mess up whatever the backend is trying to do. */
514 && outer_size
== inner_size
515 && !MODES_TIEABLE_P (GET_MODE (x
), GET_MODE (inner
)))
517 bitmap_set_bit (non_decomposable_context
, regno
);
518 bitmap_set_bit (subreg_context
, regno
);
519 iter
.skip_subrtxes ();
527 /* We will see an outer SUBREG before we see the inner REG, so
528 when we see a plain REG here it means a direct reference to
531 If this is not a simple copy from one location to another,
532 then we can not decompose this register. If this is a simple
533 copy we want to decompose, and the mode is right,
534 then we mark the register as decomposable.
535 Otherwise we don't say anything about this register --
536 it could be decomposed, but whether that would be
537 profitable depends upon how it is used elsewhere.
539 We only set bits in the bitmap for multi-word
540 pseudo-registers, since those are the only ones we care about
541 and it keeps the size of the bitmaps down. */
544 if (!HARD_REGISTER_NUM_P (regno
)
545 && GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
549 case NOT_SIMPLE_MOVE
:
550 bitmap_set_bit (non_decomposable_context
, regno
);
552 case DECOMPOSABLE_SIMPLE_MOVE
:
553 if (MODES_TIEABLE_P (GET_MODE (x
), word_mode
))
554 bitmap_set_bit (decomposable_context
, regno
);
565 enum classify_move_insn cmi_mem
= NOT_SIMPLE_MOVE
;
567 /* Any registers used in a MEM do not participate in a
568 SIMPLE_MOVE or DECOMPOSABLE_SIMPLE_MOVE. Do our own recursion
569 here, and return -1 to block the parent's recursion. */
570 find_decomposable_subregs (&XEXP (x
, 0), &cmi_mem
);
571 iter
.skip_subrtxes ();
576 /* Decompose REGNO into word-sized components. We smash the REG node
577 in place. This ensures that (1) something goes wrong quickly if we
578 fail to make some replacement, and (2) the debug information inside
579 the symbol table is automatically kept up to date. */
582 decompose_register (unsigned int regno
)
585 unsigned int words
, i
;
588 reg
= regno_reg_rtx
[regno
];
590 regno_reg_rtx
[regno
] = NULL_RTX
;
592 words
= GET_MODE_SIZE (GET_MODE (reg
));
593 words
= (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
595 v
= rtvec_alloc (words
);
596 for (i
= 0; i
< words
; ++i
)
597 RTVEC_ELT (v
, i
) = gen_reg_rtx_offset (reg
, word_mode
, i
* UNITS_PER_WORD
);
599 PUT_CODE (reg
, CONCATN
);
604 fprintf (dump_file
, "; Splitting reg %u ->", regno
);
605 for (i
= 0; i
< words
; ++i
)
606 fprintf (dump_file
, " %u", REGNO (XVECEXP (reg
, 0, i
)));
607 fputc ('\n', dump_file
);
611 /* Get a SUBREG of a CONCATN. */
614 simplify_subreg_concatn (machine_mode outermode
, rtx op
,
617 unsigned int inner_size
;
618 machine_mode innermode
, partmode
;
620 unsigned int final_offset
;
622 gcc_assert (GET_CODE (op
) == CONCATN
);
623 gcc_assert (byte
% GET_MODE_SIZE (outermode
) == 0);
625 innermode
= GET_MODE (op
);
626 gcc_assert (byte
< GET_MODE_SIZE (innermode
));
627 gcc_assert (GET_MODE_SIZE (outermode
) <= GET_MODE_SIZE (innermode
));
629 inner_size
= GET_MODE_SIZE (innermode
) / XVECLEN (op
, 0);
630 part
= XVECEXP (op
, 0, byte
/ inner_size
);
631 partmode
= GET_MODE (part
);
633 /* VECTOR_CSTs in debug expressions are expanded into CONCATN instead of
634 regular CONST_VECTORs. They have vector or integer modes, depending
635 on the capabilities of the target. Cope with them. */
636 if (partmode
== VOIDmode
&& VECTOR_MODE_P (innermode
))
637 partmode
= GET_MODE_INNER (innermode
);
638 else if (partmode
== VOIDmode
)
640 enum mode_class mclass
= GET_MODE_CLASS (innermode
);
641 partmode
= mode_for_size (inner_size
* BITS_PER_UNIT
, mclass
, 0);
644 final_offset
= byte
% inner_size
;
645 if (final_offset
+ GET_MODE_SIZE (outermode
) > inner_size
)
648 return simplify_gen_subreg (outermode
, part
, partmode
, final_offset
);
651 /* Wrapper around simplify_gen_subreg which handles CONCATN. */
654 simplify_gen_subreg_concatn (machine_mode outermode
, rtx op
,
655 machine_mode innermode
, unsigned int byte
)
659 /* We have to handle generating a SUBREG of a SUBREG of a CONCATN.
660 If OP is a SUBREG of a CONCATN, then it must be a simple mode
661 change with the same size and offset 0, or it must extract a
662 part. We shouldn't see anything else here. */
663 if (GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == CONCATN
)
667 if ((GET_MODE_SIZE (GET_MODE (op
))
668 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
669 && SUBREG_BYTE (op
) == 0)
670 return simplify_gen_subreg_concatn (outermode
, SUBREG_REG (op
),
671 GET_MODE (SUBREG_REG (op
)), byte
);
673 op2
= simplify_subreg_concatn (GET_MODE (op
), SUBREG_REG (op
),
677 /* We don't handle paradoxical subregs here. */
678 gcc_assert (GET_MODE_SIZE (outermode
)
679 <= GET_MODE_SIZE (GET_MODE (op
)));
680 gcc_assert (GET_MODE_SIZE (GET_MODE (op
))
681 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))));
682 op2
= simplify_subreg_concatn (outermode
, SUBREG_REG (op
),
683 byte
+ SUBREG_BYTE (op
));
684 gcc_assert (op2
!= NULL_RTX
);
689 gcc_assert (op
!= NULL_RTX
);
690 gcc_assert (innermode
== GET_MODE (op
));
693 if (GET_CODE (op
) == CONCATN
)
694 return simplify_subreg_concatn (outermode
, op
, byte
);
696 ret
= simplify_gen_subreg (outermode
, op
, innermode
, byte
);
698 /* If we see an insn like (set (reg:DI) (subreg:DI (reg:SI) 0)) then
699 resolve_simple_move will ask for the high part of the paradoxical
700 subreg, which does not have a value. Just return a zero. */
702 && GET_CODE (op
) == SUBREG
703 && SUBREG_BYTE (op
) == 0
704 && (GET_MODE_SIZE (innermode
)
705 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
)))))
706 return CONST0_RTX (outermode
);
708 gcc_assert (ret
!= NULL_RTX
);
712 /* Return whether we should resolve X into the registers into which it
716 resolve_reg_p (rtx x
)
718 return GET_CODE (x
) == CONCATN
;
721 /* Return whether X is a SUBREG of a register which we need to
725 resolve_subreg_p (rtx x
)
727 if (GET_CODE (x
) != SUBREG
)
729 return resolve_reg_p (SUBREG_REG (x
));
732 /* Look for SUBREGs in *LOC which need to be decomposed. */
735 resolve_subreg_use (rtx
*loc
, rtx insn
)
737 subrtx_ptr_iterator::array_type array
;
738 FOR_EACH_SUBRTX_PTR (iter
, array
, loc
, NONCONST
)
742 if (resolve_subreg_p (x
))
744 x
= simplify_subreg_concatn (GET_MODE (x
), SUBREG_REG (x
),
747 /* It is possible for a note to contain a reference which we can
748 decompose. In this case, return 1 to the caller to indicate
749 that the note must be removed. */
756 validate_change (insn
, loc
, x
, 1);
757 iter
.skip_subrtxes ();
759 else if (resolve_reg_p (x
))
760 /* Return 1 to the caller to indicate that we found a direct
761 reference to a register which is being decomposed. This can
762 happen inside notes, multiword shift or zero-extend
770 /* Resolve any decomposed registers which appear in register notes on
774 resolve_reg_notes (rtx_insn
*insn
)
778 note
= find_reg_equal_equiv_note (insn
);
781 int old_count
= num_validated_changes ();
782 if (resolve_subreg_use (&XEXP (note
, 0), NULL_RTX
))
783 remove_note (insn
, note
);
785 if (old_count
!= num_validated_changes ())
786 df_notes_rescan (insn
);
789 pnote
= ®_NOTES (insn
);
790 while (*pnote
!= NULL_RTX
)
795 switch (REG_NOTE_KIND (note
))
799 if (resolve_reg_p (XEXP (note
, 0)))
808 *pnote
= XEXP (note
, 1);
810 pnote
= &XEXP (note
, 1);
814 /* Return whether X can be decomposed into subwords. */
817 can_decompose_p (rtx x
)
821 unsigned int regno
= REGNO (x
);
823 if (HARD_REGISTER_NUM_P (regno
))
825 unsigned int byte
, num_bytes
;
827 num_bytes
= GET_MODE_SIZE (GET_MODE (x
));
828 for (byte
= 0; byte
< num_bytes
; byte
+= UNITS_PER_WORD
)
829 if (simplify_subreg_regno (regno
, GET_MODE (x
), byte
, word_mode
) < 0)
834 return !bitmap_bit_p (subreg_context
, regno
);
840 /* Decompose the registers used in a simple move SET within INSN. If
841 we don't change anything, return INSN, otherwise return the start
842 of the sequence of moves. */
845 resolve_simple_move (rtx set
, rtx_insn
*insn
)
847 rtx src
, dest
, real_dest
;
849 machine_mode orig_mode
, dest_mode
;
854 dest
= SET_DEST (set
);
855 orig_mode
= GET_MODE (dest
);
857 words
= (GET_MODE_SIZE (orig_mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
858 gcc_assert (words
> 1);
862 /* We have to handle copying from a SUBREG of a decomposed reg where
863 the SUBREG is larger than word size. Rather than assume that we
864 can take a word_mode SUBREG of the destination, we copy to a new
865 register and then copy that to the destination. */
867 real_dest
= NULL_RTX
;
869 if (GET_CODE (src
) == SUBREG
870 && resolve_reg_p (SUBREG_REG (src
))
871 && (SUBREG_BYTE (src
) != 0
872 || (GET_MODE_SIZE (orig_mode
)
873 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))))
876 dest
= gen_reg_rtx (orig_mode
);
877 if (REG_P (real_dest
))
878 REG_ATTRS (dest
) = REG_ATTRS (real_dest
);
881 /* Similarly if we are copying to a SUBREG of a decomposed reg where
882 the SUBREG is larger than word size. */
884 if (GET_CODE (dest
) == SUBREG
885 && resolve_reg_p (SUBREG_REG (dest
))
886 && (SUBREG_BYTE (dest
) != 0
887 || (GET_MODE_SIZE (orig_mode
)
888 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
))))))
893 reg
= gen_reg_rtx (orig_mode
);
894 minsn
= emit_move_insn (reg
, src
);
895 smove
= single_set (minsn
);
896 gcc_assert (smove
!= NULL_RTX
);
897 resolve_simple_move (smove
, minsn
);
901 /* If we didn't have any big SUBREGS of decomposed registers, and
902 neither side of the move is a register we are decomposing, then
903 we don't have to do anything here. */
905 if (src
== SET_SRC (set
)
906 && dest
== SET_DEST (set
)
907 && !resolve_reg_p (src
)
908 && !resolve_subreg_p (src
)
909 && !resolve_reg_p (dest
)
910 && !resolve_subreg_p (dest
))
916 /* It's possible for the code to use a subreg of a decomposed
917 register while forming an address. We need to handle that before
918 passing the address to emit_move_insn. We pass NULL_RTX as the
919 insn parameter to resolve_subreg_use because we can not validate
921 if (MEM_P (src
) || MEM_P (dest
))
926 resolve_subreg_use (&XEXP (src
, 0), NULL_RTX
);
928 resolve_subreg_use (&XEXP (dest
, 0), NULL_RTX
);
929 acg
= apply_change_group ();
933 /* If SRC is a register which we can't decompose, or has side
934 effects, we need to move via a temporary register. */
936 if (!can_decompose_p (src
)
937 || side_effects_p (src
)
938 || GET_CODE (src
) == ASM_OPERANDS
)
942 reg
= gen_reg_rtx (orig_mode
);
946 rtx move
= emit_move_insn (reg
, src
);
949 rtx note
= find_reg_note (insn
, REG_INC
, NULL_RTX
);
951 add_reg_note (move
, REG_INC
, XEXP (note
, 0));
955 emit_move_insn (reg
, src
);
960 /* If DEST is a register which we can't decompose, or has side
961 effects, we need to first move to a temporary register. We
962 handle the common case of pushing an operand directly. We also
963 go through a temporary register if it holds a floating point
964 value. This gives us better code on systems which can't move
965 data easily between integer and floating point registers. */
967 dest_mode
= orig_mode
;
968 pushing
= push_operand (dest
, dest_mode
);
969 if (!can_decompose_p (dest
)
970 || (side_effects_p (dest
) && !pushing
)
971 || (!SCALAR_INT_MODE_P (dest_mode
)
972 && !resolve_reg_p (dest
)
973 && !resolve_subreg_p (dest
)))
975 if (real_dest
== NULL_RTX
)
977 if (!SCALAR_INT_MODE_P (dest_mode
))
979 dest_mode
= mode_for_size (GET_MODE_SIZE (dest_mode
) * BITS_PER_UNIT
,
981 gcc_assert (dest_mode
!= BLKmode
);
983 dest
= gen_reg_rtx (dest_mode
);
984 if (REG_P (real_dest
))
985 REG_ATTRS (dest
) = REG_ATTRS (real_dest
);
990 unsigned int i
, j
, jinc
;
992 gcc_assert (GET_MODE_SIZE (orig_mode
) % UNITS_PER_WORD
== 0);
993 gcc_assert (GET_CODE (XEXP (dest
, 0)) != PRE_MODIFY
);
994 gcc_assert (GET_CODE (XEXP (dest
, 0)) != POST_MODIFY
);
996 if (WORDS_BIG_ENDIAN
== STACK_GROWS_DOWNWARD
)
1007 for (i
= 0; i
< words
; ++i
, j
+= jinc
)
1011 temp
= copy_rtx (XEXP (dest
, 0));
1012 temp
= adjust_automodify_address_nv (dest
, word_mode
, temp
,
1013 j
* UNITS_PER_WORD
);
1014 emit_move_insn (temp
,
1015 simplify_gen_subreg_concatn (word_mode
, src
,
1017 j
* UNITS_PER_WORD
));
1024 if (REG_P (dest
) && !HARD_REGISTER_NUM_P (REGNO (dest
)))
1025 emit_clobber (dest
);
1027 for (i
= 0; i
< words
; ++i
)
1028 emit_move_insn (simplify_gen_subreg_concatn (word_mode
, dest
,
1030 i
* UNITS_PER_WORD
),
1031 simplify_gen_subreg_concatn (word_mode
, src
,
1033 i
* UNITS_PER_WORD
));
1036 if (real_dest
!= NULL_RTX
)
1041 if (dest_mode
== orig_mode
)
1044 mdest
= simplify_gen_subreg (orig_mode
, dest
, GET_MODE (dest
), 0);
1045 minsn
= emit_move_insn (real_dest
, mdest
);
1047 if (AUTO_INC_DEC
&& MEM_P (real_dest
)
1048 && !(resolve_reg_p (real_dest
) || resolve_subreg_p (real_dest
)))
1050 rtx note
= find_reg_note (insn
, REG_INC
, NULL_RTX
);
1052 add_reg_note (minsn
, REG_INC
, XEXP (note
, 0));
1055 smove
= single_set (minsn
);
1056 gcc_assert (smove
!= NULL_RTX
);
1058 resolve_simple_move (smove
, minsn
);
1061 insns
= get_insns ();
1064 copy_reg_eh_region_note_forward (insn
, insns
, NULL_RTX
);
1066 emit_insn_before (insns
, insn
);
1068 /* If we get here via self-recursion, then INSN is not yet in the insns
1069 chain and delete_insn will fail. We only want to remove INSN from the
1070 current sequence. See PR56738. */
1071 if (in_sequence_p ())
1079 /* Change a CLOBBER of a decomposed register into a CLOBBER of the
1080 component registers. Return whether we changed something. */
1083 resolve_clobber (rtx pat
, rtx_insn
*insn
)
1086 machine_mode orig_mode
;
1087 unsigned int words
, i
;
1090 reg
= XEXP (pat
, 0);
1091 if (!resolve_reg_p (reg
) && !resolve_subreg_p (reg
))
1094 orig_mode
= GET_MODE (reg
);
1095 words
= GET_MODE_SIZE (orig_mode
);
1096 words
= (words
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
1098 ret
= validate_change (NULL_RTX
, &XEXP (pat
, 0),
1099 simplify_gen_subreg_concatn (word_mode
, reg
,
1102 df_insn_rescan (insn
);
1103 gcc_assert (ret
!= 0);
1105 for (i
= words
- 1; i
> 0; --i
)
1109 x
= simplify_gen_subreg_concatn (word_mode
, reg
, orig_mode
,
1110 i
* UNITS_PER_WORD
);
1111 x
= gen_rtx_CLOBBER (VOIDmode
, x
);
1112 emit_insn_after (x
, insn
);
1115 resolve_reg_notes (insn
);
1120 /* A USE of a decomposed register is no longer meaningful. Return
1121 whether we changed something. */
1124 resolve_use (rtx pat
, rtx_insn
*insn
)
1126 if (resolve_reg_p (XEXP (pat
, 0)) || resolve_subreg_p (XEXP (pat
, 0)))
1132 resolve_reg_notes (insn
);
1137 /* A VAR_LOCATION can be simplified. */
1140 resolve_debug (rtx_insn
*insn
)
1142 subrtx_ptr_iterator::array_type array
;
1143 FOR_EACH_SUBRTX_PTR (iter
, array
, &PATTERN (insn
), NONCONST
)
1147 if (resolve_subreg_p (x
))
1149 x
= simplify_subreg_concatn (GET_MODE (x
), SUBREG_REG (x
),
1155 x
= copy_rtx (*loc
);
1157 if (resolve_reg_p (x
))
1158 *loc
= copy_rtx (x
);
1161 df_insn_rescan (insn
);
1163 resolve_reg_notes (insn
);
1166 /* Check if INSN is a decomposable multiword-shift or zero-extend and
1167 set the decomposable_context bitmap accordingly. SPEED_P is true
1168 if we are optimizing INSN for speed rather than size. Return true
1169 if INSN is decomposable. */
1172 find_decomposable_shift_zext (rtx_insn
*insn
, bool speed_p
)
1178 set
= single_set (insn
);
1183 if (GET_CODE (op
) != ASHIFT
1184 && GET_CODE (op
) != LSHIFTRT
1185 && GET_CODE (op
) != ASHIFTRT
1186 && GET_CODE (op
) != ZERO_EXTEND
)
1189 op_operand
= XEXP (op
, 0);
1190 if (!REG_P (SET_DEST (set
)) || !REG_P (op_operand
)
1191 || HARD_REGISTER_NUM_P (REGNO (SET_DEST (set
)))
1192 || HARD_REGISTER_NUM_P (REGNO (op_operand
))
1193 || GET_MODE (op
) != twice_word_mode
)
1196 if (GET_CODE (op
) == ZERO_EXTEND
)
1198 if (GET_MODE (op_operand
) != word_mode
1199 || !choices
[speed_p
].splitting_zext
)
1202 else /* left or right shift */
1204 bool *splitting
= (GET_CODE (op
) == ASHIFT
1205 ? choices
[speed_p
].splitting_ashift
1206 : GET_CODE (op
) == ASHIFTRT
1207 ? choices
[speed_p
].splitting_ashiftrt
1208 : choices
[speed_p
].splitting_lshiftrt
);
1209 if (!CONST_INT_P (XEXP (op
, 1))
1210 || !IN_RANGE (INTVAL (XEXP (op
, 1)), BITS_PER_WORD
,
1211 2 * BITS_PER_WORD
- 1)
1212 || !splitting
[INTVAL (XEXP (op
, 1)) - BITS_PER_WORD
])
1215 bitmap_set_bit (decomposable_context
, REGNO (op_operand
));
1218 bitmap_set_bit (decomposable_context
, REGNO (SET_DEST (set
)));
1223 /* Decompose a more than word wide shift (in INSN) of a multiword
1224 pseudo or a multiword zero-extend of a wordmode pseudo into a move
1225 and 'set to zero' insn. Return a pointer to the new insn when a
1226 replacement was done. */
1229 resolve_shift_zext (rtx_insn
*insn
)
1235 rtx src_reg
, dest_reg
, dest_upper
, upper_src
= NULL_RTX
;
1236 int src_reg_num
, dest_reg_num
, offset1
, offset2
, src_offset
;
1238 set
= single_set (insn
);
1243 if (GET_CODE (op
) != ASHIFT
1244 && GET_CODE (op
) != LSHIFTRT
1245 && GET_CODE (op
) != ASHIFTRT
1246 && GET_CODE (op
) != ZERO_EXTEND
)
1249 op_operand
= XEXP (op
, 0);
1251 /* We can tear this operation apart only if the regs were already
1253 if (!resolve_reg_p (SET_DEST (set
)) && !resolve_reg_p (op_operand
))
1256 /* src_reg_num is the number of the word mode register which we
1257 are operating on. For a left shift and a zero_extend on little
1258 endian machines this is register 0. */
1259 src_reg_num
= (GET_CODE (op
) == LSHIFTRT
|| GET_CODE (op
) == ASHIFTRT
)
1262 if (WORDS_BIG_ENDIAN
1263 && GET_MODE_SIZE (GET_MODE (op_operand
)) > UNITS_PER_WORD
)
1264 src_reg_num
= 1 - src_reg_num
;
1266 if (GET_CODE (op
) == ZERO_EXTEND
)
1267 dest_reg_num
= WORDS_BIG_ENDIAN
? 1 : 0;
1269 dest_reg_num
= 1 - src_reg_num
;
1271 offset1
= UNITS_PER_WORD
* dest_reg_num
;
1272 offset2
= UNITS_PER_WORD
* (1 - dest_reg_num
);
1273 src_offset
= UNITS_PER_WORD
* src_reg_num
;
1277 dest_reg
= simplify_gen_subreg_concatn (word_mode
, SET_DEST (set
),
1278 GET_MODE (SET_DEST (set
)),
1280 dest_upper
= simplify_gen_subreg_concatn (word_mode
, SET_DEST (set
),
1281 GET_MODE (SET_DEST (set
)),
1283 src_reg
= simplify_gen_subreg_concatn (word_mode
, op_operand
,
1284 GET_MODE (op_operand
),
1286 if (GET_CODE (op
) == ASHIFTRT
1287 && INTVAL (XEXP (op
, 1)) != 2 * BITS_PER_WORD
- 1)
1288 upper_src
= expand_shift (RSHIFT_EXPR
, word_mode
, copy_rtx (src_reg
),
1289 BITS_PER_WORD
- 1, NULL_RTX
, 0);
1291 if (GET_CODE (op
) != ZERO_EXTEND
)
1293 int shift_count
= INTVAL (XEXP (op
, 1));
1294 if (shift_count
> BITS_PER_WORD
)
1295 src_reg
= expand_shift (GET_CODE (op
) == ASHIFT
?
1296 LSHIFT_EXPR
: RSHIFT_EXPR
,
1298 shift_count
- BITS_PER_WORD
,
1299 dest_reg
, GET_CODE (op
) != ASHIFTRT
);
1302 if (dest_reg
!= src_reg
)
1303 emit_move_insn (dest_reg
, src_reg
);
1304 if (GET_CODE (op
) != ASHIFTRT
)
1305 emit_move_insn (dest_upper
, CONST0_RTX (word_mode
));
1306 else if (INTVAL (XEXP (op
, 1)) == 2 * BITS_PER_WORD
- 1)
1307 emit_move_insn (dest_upper
, copy_rtx (src_reg
));
1309 emit_move_insn (dest_upper
, upper_src
);
1310 insns
= get_insns ();
1314 emit_insn_before (insns
, insn
);
1319 fprintf (dump_file
, "; Replacing insn: %d with insns: ", INSN_UID (insn
));
1320 for (in
= insns
; in
!= insn
; in
= NEXT_INSN (in
))
1321 fprintf (dump_file
, "%d ", INSN_UID (in
));
1322 fprintf (dump_file
, "\n");
1329 /* Print to dump_file a description of what we're doing with shift code CODE.
1330 SPLITTING[X] is true if we are splitting shifts by X + BITS_PER_WORD. */
1333 dump_shift_choices (enum rtx_code code
, bool *splitting
)
1339 " Splitting mode %s for %s lowering with shift amounts = ",
1340 GET_MODE_NAME (twice_word_mode
), GET_RTX_NAME (code
));
1342 for (i
= 0; i
< BITS_PER_WORD
; i
++)
1345 fprintf (dump_file
, "%s%d", sep
, i
+ BITS_PER_WORD
);
1348 fprintf (dump_file
, "\n");
1351 /* Print to dump_file a description of what we're doing when optimizing
1352 for speed or size; SPEED_P says which. DESCRIPTION is a description
1353 of the SPEED_P choice. */
1356 dump_choices (bool speed_p
, const char *description
)
1360 fprintf (dump_file
, "Choices when optimizing for %s:\n", description
);
1362 for (i
= 0; i
< MAX_MACHINE_MODE
; i
++)
1363 if (GET_MODE_SIZE ((machine_mode
) i
) > UNITS_PER_WORD
)
1364 fprintf (dump_file
, " %s mode %s for copy lowering.\n",
1365 choices
[speed_p
].move_modes_to_split
[i
]
1368 GET_MODE_NAME ((machine_mode
) i
));
1370 fprintf (dump_file
, " %s mode %s for zero_extend lowering.\n",
1371 choices
[speed_p
].splitting_zext
? "Splitting" : "Skipping",
1372 GET_MODE_NAME (twice_word_mode
));
1374 dump_shift_choices (ASHIFT
, choices
[speed_p
].splitting_ashift
);
1375 dump_shift_choices (LSHIFTRT
, choices
[speed_p
].splitting_lshiftrt
);
1376 dump_shift_choices (ASHIFTRT
, choices
[speed_p
].splitting_ashiftrt
);
1377 fprintf (dump_file
, "\n");
1380 /* Look for registers which are always accessed via word-sized SUBREGs
1381 or -if DECOMPOSE_COPIES is true- via copies. Decompose these
1382 registers into several word-sized pseudo-registers. */
1385 decompose_multiword_subregs (bool decompose_copies
)
1393 dump_choices (false, "size");
1394 dump_choices (true, "speed");
1397 /* Check if this target even has any modes to consider lowering. */
1398 if (!choices
[false].something_to_do
&& !choices
[true].something_to_do
)
1401 fprintf (dump_file
, "Nothing to do!\n");
1405 max
= max_reg_num ();
1407 /* First see if there are any multi-word pseudo-registers. If there
1408 aren't, there is nothing we can do. This should speed up this
1409 pass in the normal case, since it should be faster than scanning
1413 bool useful_modes_seen
= false;
1415 for (i
= FIRST_PSEUDO_REGISTER
; i
< max
; ++i
)
1416 if (regno_reg_rtx
[i
] != NULL
)
1418 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
1419 if (choices
[false].move_modes_to_split
[(int) mode
]
1420 || choices
[true].move_modes_to_split
[(int) mode
])
1422 useful_modes_seen
= true;
1427 if (!useful_modes_seen
)
1430 fprintf (dump_file
, "Nothing to lower in this function.\n");
1437 df_set_flags (DF_DEFER_INSN_RESCAN
);
1441 /* FIXME: It may be possible to change this code to look for each
1442 multi-word pseudo-register and to find each insn which sets or
1443 uses that register. That should be faster than scanning all the
1446 decomposable_context
= BITMAP_ALLOC (NULL
);
1447 non_decomposable_context
= BITMAP_ALLOC (NULL
);
1448 subreg_context
= BITMAP_ALLOC (NULL
);
1450 reg_copy_graph
.create (max
);
1451 reg_copy_graph
.safe_grow_cleared (max
);
1452 memset (reg_copy_graph
.address (), 0, sizeof (bitmap
) * max
);
1454 speed_p
= optimize_function_for_speed_p (cfun
);
1455 FOR_EACH_BB_FN (bb
, cfun
)
1459 FOR_BB_INSNS (bb
, insn
)
1462 enum classify_move_insn cmi
;
1466 || GET_CODE (PATTERN (insn
)) == CLOBBER
1467 || GET_CODE (PATTERN (insn
)) == USE
)
1470 recog_memoized (insn
);
1472 if (find_decomposable_shift_zext (insn
, speed_p
))
1475 extract_insn (insn
);
1477 set
= simple_move (insn
, speed_p
);
1480 cmi
= NOT_SIMPLE_MOVE
;
1483 /* We mark pseudo-to-pseudo copies as decomposable during the
1484 second pass only. The first pass is so early that there is
1485 good chance such moves will be optimized away completely by
1486 subsequent optimizations anyway.
1488 However, we call find_pseudo_copy even during the first pass
1489 so as to properly set up the reg_copy_graph. */
1490 if (find_pseudo_copy (set
))
1491 cmi
= decompose_copies
? DECOMPOSABLE_SIMPLE_MOVE
: SIMPLE_MOVE
;
1496 n
= recog_data
.n_operands
;
1497 for (i
= 0; i
< n
; ++i
)
1499 find_decomposable_subregs (&recog_data
.operand
[i
], &cmi
);
1501 /* We handle ASM_OPERANDS as a special case to support
1502 things like x86 rdtsc which returns a DImode value.
1503 We can decompose the output, which will certainly be
1504 operand 0, but not the inputs. */
1506 if (cmi
== SIMPLE_MOVE
1507 && GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1509 gcc_assert (i
== 0);
1510 cmi
= NOT_SIMPLE_MOVE
;
1516 bitmap_and_compl_into (decomposable_context
, non_decomposable_context
);
1517 if (!bitmap_empty_p (decomposable_context
))
1521 sbitmap_iterator sbi
;
1522 bitmap_iterator iter
;
1525 propagate_pseudo_copies ();
1527 sub_blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
1528 bitmap_clear (sub_blocks
);
1530 EXECUTE_IF_SET_IN_BITMAP (decomposable_context
, 0, regno
, iter
)
1531 decompose_register (regno
);
1533 FOR_EACH_BB_FN (bb
, cfun
)
1537 FOR_BB_INSNS (bb
, insn
)
1544 pat
= PATTERN (insn
);
1545 if (GET_CODE (pat
) == CLOBBER
)
1546 resolve_clobber (pat
, insn
);
1547 else if (GET_CODE (pat
) == USE
)
1548 resolve_use (pat
, insn
);
1549 else if (DEBUG_INSN_P (insn
))
1550 resolve_debug (insn
);
1556 recog_memoized (insn
);
1557 extract_insn (insn
);
1559 set
= simple_move (insn
, speed_p
);
1562 rtx_insn
*orig_insn
= insn
;
1563 bool cfi
= control_flow_insn_p (insn
);
1565 /* We can end up splitting loads to multi-word pseudos
1566 into separate loads to machine word size pseudos.
1567 When this happens, we first had one load that can
1568 throw, and after resolve_simple_move we'll have a
1569 bunch of loads (at least two). All those loads may
1570 trap if we can have non-call exceptions, so they
1571 all will end the current basic block. We split the
1572 block after the outer loop over all insns, but we
1573 make sure here that we will be able to split the
1574 basic block and still produce the correct control
1575 flow graph for it. */
1577 || (cfun
->can_throw_non_call_exceptions
1578 && can_throw_internal (insn
)));
1580 insn
= resolve_simple_move (set
, insn
);
1581 if (insn
!= orig_insn
)
1583 recog_memoized (insn
);
1584 extract_insn (insn
);
1587 bitmap_set_bit (sub_blocks
, bb
->index
);
1592 rtx_insn
*decomposed_shift
;
1594 decomposed_shift
= resolve_shift_zext (insn
);
1595 if (decomposed_shift
!= NULL_RTX
)
1597 insn
= decomposed_shift
;
1598 recog_memoized (insn
);
1599 extract_insn (insn
);
1603 for (i
= recog_data
.n_operands
- 1; i
>= 0; --i
)
1604 resolve_subreg_use (recog_data
.operand_loc
[i
], insn
);
1606 resolve_reg_notes (insn
);
1608 if (num_validated_changes () > 0)
1610 for (i
= recog_data
.n_dups
- 1; i
>= 0; --i
)
1612 rtx
*pl
= recog_data
.dup_loc
[i
];
1613 int dup_num
= recog_data
.dup_num
[i
];
1614 rtx
*px
= recog_data
.operand_loc
[dup_num
];
1616 validate_unshare_change (insn
, pl
, *px
, 1);
1619 i
= apply_change_group ();
1626 /* If we had insns to split that caused control flow insns in the middle
1627 of a basic block, split those blocks now. Note that we only handle
1628 the case where splitting a load has caused multiple possibly trapping
1630 EXECUTE_IF_SET_IN_BITMAP (sub_blocks
, 0, i
, sbi
)
1632 rtx_insn
*insn
, *end
;
1635 bb
= BASIC_BLOCK_FOR_FN (cfun
, i
);
1636 insn
= BB_HEAD (bb
);
1641 if (control_flow_insn_p (insn
))
1643 /* Split the block after insn. There will be a fallthru
1644 edge, which is OK so we keep it. We have to create the
1645 exception edges ourselves. */
1646 fallthru
= split_block (bb
, insn
);
1647 rtl_make_eh_edge (NULL
, bb
, BB_END (bb
));
1648 bb
= fallthru
->dest
;
1649 insn
= BB_HEAD (bb
);
1652 insn
= NEXT_INSN (insn
);
1656 sbitmap_free (sub_blocks
);
1663 FOR_EACH_VEC_ELT (reg_copy_graph
, i
, b
)
1668 reg_copy_graph
.release ();
1670 BITMAP_FREE (decomposable_context
);
1671 BITMAP_FREE (non_decomposable_context
);
1672 BITMAP_FREE (subreg_context
);
1675 /* Implement first lower subreg pass. */
1679 const pass_data pass_data_lower_subreg
=
1681 RTL_PASS
, /* type */
1682 "subreg1", /* name */
1683 OPTGROUP_NONE
, /* optinfo_flags */
1684 TV_LOWER_SUBREG
, /* tv_id */
1685 0, /* properties_required */
1686 0, /* properties_provided */
1687 0, /* properties_destroyed */
1688 0, /* todo_flags_start */
1689 0, /* todo_flags_finish */
1692 class pass_lower_subreg
: public rtl_opt_pass
1695 pass_lower_subreg (gcc::context
*ctxt
)
1696 : rtl_opt_pass (pass_data_lower_subreg
, ctxt
)
1699 /* opt_pass methods: */
1700 virtual bool gate (function
*) { return flag_split_wide_types
!= 0; }
1701 virtual unsigned int execute (function
*)
1703 decompose_multiword_subregs (false);
1707 }; // class pass_lower_subreg
1712 make_pass_lower_subreg (gcc::context
*ctxt
)
1714 return new pass_lower_subreg (ctxt
);
1717 /* Implement second lower subreg pass. */
1721 const pass_data pass_data_lower_subreg2
=
1723 RTL_PASS
, /* type */
1724 "subreg2", /* name */
1725 OPTGROUP_NONE
, /* optinfo_flags */
1726 TV_LOWER_SUBREG
, /* tv_id */
1727 0, /* properties_required */
1728 0, /* properties_provided */
1729 0, /* properties_destroyed */
1730 0, /* todo_flags_start */
1731 TODO_df_finish
, /* todo_flags_finish */
1734 class pass_lower_subreg2
: public rtl_opt_pass
1737 pass_lower_subreg2 (gcc::context
*ctxt
)
1738 : rtl_opt_pass (pass_data_lower_subreg2
, ctxt
)
1741 /* opt_pass methods: */
1742 virtual bool gate (function
*) { return flag_split_wide_types
!= 0; }
1743 virtual unsigned int execute (function
*)
1745 decompose_multiword_subregs (true);
1749 }; // class pass_lower_subreg2
1754 make_pass_lower_subreg2 (gcc::context
*ctxt
)
1756 return new pass_lower_subreg2 (ctxt
);