1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010, 2011, 2012
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This file contains code for 3 passes: constraint pass,
24 inheritance/split pass, and pass for undoing failed inheritance and
27 The major goal of constraint pass is to transform RTL to satisfy
28 insn and address constraints by:
29 o choosing insn alternatives;
30 o generating *reload insns* (or reloads in brief) and *reload
31 pseudos* which will get necessary hard registers later;
32 o substituting pseudos with equivalent values and removing the
33 instructions that initialized those pseudos.
35 The constraint pass has biggest and most complicated code in LRA.
36 There are a lot of important details like:
37 o reuse of input reload pseudos to simplify reload pseudo
39 o some heuristics to choose insn alternative to improve the
43 The pass is mimicking former reload pass in alternative choosing
44 because the reload pass is oriented to current machine description
45 model. It might be changed if the machine description model is
48 There is special code for preventing all LRA and this pass cycling
51 On the first iteration of the pass we process every instruction and
52 choose an alternative for each one. On subsequent iterations we try
53 to avoid reprocessing instructions if we can be sure that the old
54 choice is still valid.
56 The inheritance/spilt pass is to transform code to achieve
57 ineheritance and live range splitting. It is done on backward
60 The inheritance optimization goal is to reuse values in hard
61 registers. There is analogous optimization in old reload pass. The
62 inheritance is achieved by following transformation:
64 reload_p1 <- p reload_p1 <- p
65 ... new_p <- reload_p1
67 reload_p2 <- p reload_p2 <- new_p
69 where p is spilled and not changed between the insns. Reload_p1 is
70 also called *original pseudo* and new_p is called *inheritance
73 The subsequent assignment pass will try to assign the same (or
74 another if it is not possible) hard register to new_p as to
75 reload_p1 or reload_p2.
77 If the assignment pass fails to assign a hard register to new_p,
78 this file will undo the inheritance and restore the original code.
79 This is because implementing the above sequence with a spilled
80 new_p would make the code much worse. The inheritance is done in
81 EBB scope. The above is just a simplified example to get an idea
82 of the inheritance as the inheritance is also done for non-reload
85 Splitting (transformation) is also done in EBB scope on the same
86 pass as the inheritance:
88 r <- ... or ... <- r r <- ... or ... <- r
89 ... s <- r (new insn -- save)
91 ... r <- s (new insn -- restore)
94 The *split pseudo* s is assigned to the hard register of the
95 original pseudo or hard register r.
98 o In EBBs with high register pressure for global pseudos (living
99 in at least 2 BBs) and assigned to hard registers when there
100 are more one reloads needing the hard registers;
101 o for pseudos needing save/restore code around calls.
103 If the split pseudo still has the same hard register as the
104 original pseudo after the subsequent assignment pass or the
105 original pseudo was split, the opposite transformation is done on
106 the same pass for undoing inheritance. */
112 #include "coretypes.h"
114 #include "hard-reg-set.h"
118 #include "insn-config.h"
119 #include "insn-codes.h"
122 #include "addresses.h"
124 #include "function.h"
126 #include "basic-block.h"
131 #include "rtl-error.h"
134 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
135 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 static int bb_reload_num
;
139 /* The current insn being processed and corresponding its data (basic
140 block, the insn data, the insn static data, and the mode of each
142 static rtx curr_insn
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* Return hard regno of REGNO or if it is was not assigned to a hard
156 register, use a hard register from its allocno class. */
158 get_try_hard_regno (int regno
)
161 enum reg_class rclass
;
163 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
164 hard_regno
= lra_get_regno_hard_regno (regno
);
167 rclass
= lra_get_allocno_class (regno
);
168 if (rclass
== NO_REGS
)
170 return ira_class_hard_regs
[rclass
][0];
173 /* Return final hard regno (plus offset) which will be after
174 elimination. We do this for matching constraints because the final
175 hard regno could have a different class. */
177 get_final_hard_regno (int hard_regno
, int offset
)
181 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
182 return hard_regno
+ offset
;
185 /* Return hard regno of X after removing subreg and making
186 elimination. If X is not a register or subreg of register, return
187 -1. For pseudo use its assignment. */
189 get_hard_regno (rtx x
)
192 int offset
, hard_regno
;
195 if (GET_CODE (x
) == SUBREG
)
196 reg
= SUBREG_REG (x
);
199 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
200 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
204 if (GET_CODE (x
) == SUBREG
)
205 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
206 SUBREG_BYTE (x
), GET_MODE (x
));
207 return get_final_hard_regno (hard_regno
, offset
);
210 /* If REGNO is a hard register or has been allocated a hard register,
211 return the class of that register. If REGNO is a reload pseudo
212 created by the current constraints pass, return its allocno class.
213 Return NO_REGS otherwise. */
214 static enum reg_class
215 get_reg_class (int regno
)
219 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
220 hard_regno
= lra_get_regno_hard_regno (regno
);
223 hard_regno
= get_final_hard_regno (hard_regno
, 0);
224 return REGNO_REG_CLASS (hard_regno
);
226 if (regno
>= new_regno_start
)
227 return lra_get_allocno_class (regno
);
231 /* Return true if REG satisfies (or will satisfy) reg class constraint
232 CL. Use elimination first if REG is a hard register. If REG is a
233 reload pseudo created by this constraints pass, assume that it will
234 be allocated a hard register from its allocno class, but allow that
235 class to be narrowed to CL if it is currently a superset of CL.
237 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
238 REGNO (reg), or NO_REGS if no change in its class was needed. */
240 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
242 enum reg_class rclass
, common_class
;
243 enum machine_mode reg_mode
;
244 int class_size
, hard_regno
, nregs
, i
, j
;
245 int regno
= REGNO (reg
);
247 if (new_class
!= NULL
)
248 *new_class
= NO_REGS
;
249 if (regno
< FIRST_PSEUDO_REGISTER
)
252 rtx
*final_loc
= &final_reg
;
254 lra_eliminate_reg_if_possible (final_loc
);
255 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
257 reg_mode
= GET_MODE (reg
);
258 rclass
= get_reg_class (regno
);
259 if (regno
< new_regno_start
260 /* Do not allow the constraints for reload instructions to
261 influence the classes of new pseudos. These reloads are
262 typically moves that have many alternatives, and restricting
263 reload pseudos for one alternative may lead to situations
264 where other reload pseudos are no longer allocatable. */
265 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
266 /* When we don't know what class will be used finally for reload
267 pseudos, we use ALL_REGS. */
268 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
269 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
270 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
271 lra_no_alloc_regs
)));
274 common_class
= ira_reg_class_subset
[rclass
][cl
];
275 if (new_class
!= NULL
)
276 *new_class
= common_class
;
277 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
280 /* Check that there are enough allocatable regs. */
281 class_size
= ira_class_hard_regs_num
[common_class
];
282 for (i
= 0; i
< class_size
; i
++)
284 hard_regno
= ira_class_hard_regs
[common_class
][i
];
285 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
288 for (j
= 0; j
< nregs
; j
++)
289 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
))
298 /* Return true if REGNO satisfies a memory constraint. */
302 return get_reg_class (regno
) == NO_REGS
;
305 /* If we have decided to substitute X with another value, return that
306 value, otherwise return X. */
308 get_equiv_substitution (rtx x
)
313 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
314 || ! ira_reg_equiv
[regno
].defined_p
315 || ! ira_reg_equiv
[regno
].profitable_p
316 || lra_get_regno_hard_regno (regno
) >= 0)
318 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
320 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
322 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
327 /* Set up curr_operand_mode. */
329 init_curr_operand_mode (void)
331 int nop
= curr_static_id
->n_operands
;
332 for (int i
= 0; i
< nop
; i
++)
334 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
335 if (mode
== VOIDmode
)
337 /* The .md mode for address operands is the mode of the
338 addressed value rather than the mode of the address itself. */
339 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
342 mode
= curr_static_id
->operand
[i
].mode
;
344 curr_operand_mode
[i
] = mode
;
350 /* The page contains code to reuse input reloads. */
352 /* Structure describes input reload of the current insns. */
355 /* Reloaded value. */
357 /* Reload pseudo used. */
361 /* The number of elements in the following array. */
362 static int curr_insn_input_reloads_num
;
363 /* Array containing info about input reloads. It is used to find the
364 same input reload and reuse the reload pseudo in this case. */
365 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
367 /* Initiate data concerning reuse of input reloads for the current
370 init_curr_insn_input_reloads (void)
372 curr_insn_input_reloads_num
= 0;
375 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
376 using TITLE. Output a new line if NL_P. */
378 change_class (int regno
, enum reg_class new_class
,
379 const char *title
, bool nl_p
)
381 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
382 if (lra_dump_file
!= NULL
)
383 fprintf (lra_dump_file
, "%s to class %s for r%d",
384 title
, reg_class_names
[new_class
], regno
);
385 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
386 if (lra_dump_file
!= NULL
&& nl_p
)
387 fprintf (lra_dump_file
, "\n");
390 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
391 created input reload pseudo (only if TYPE is not OP_OUT). The
392 result pseudo is returned through RESULT_REG. Return TRUE if we
393 created a new pseudo, FALSE if we reused the already created input
394 reload pseudo. Use TITLE to describe new registers for debug
397 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
398 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
401 enum reg_class new_class
;
406 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
409 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
410 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
411 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
413 lra_assert (! side_effects_p (original
));
414 *result_reg
= curr_insn_input_reloads
[i
].reg
;
415 regno
= REGNO (*result_reg
);
416 if (lra_dump_file
!= NULL
)
418 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
419 print_value_slim (lra_dump_file
, original
, 1);
421 if (rclass
!= new_class
)
422 change_class (regno
, new_class
, ", change", false);
423 if (lra_dump_file
!= NULL
)
424 fprintf (lra_dump_file
, "\n");
427 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
428 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
429 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
430 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
436 /* The page contains code to extract memory address parts. */
438 /* Info about base and index regs of an address. In some rare cases,
439 base/index register can be actually memory. In this case we will
443 /* NULL if there is no a base register. */
445 /* Second location of {post/pre}_modify, NULL otherwise. */
447 /* NULL if there is no an index register. */
449 /* Location of index reg * scale or index_reg_loc otherwise. */
451 /* NULL if there is no a displacement. */
453 /* Defined if base_reg_loc is not NULL. */
454 enum rtx_code base_outer_code
, index_code
;
455 /* True if the base register is modified in the address, for
456 example, in PRE_INC. */
460 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
462 ok_for_index_p_nonstrict (rtx reg
)
464 unsigned regno
= REGNO (reg
);
466 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
469 /* A version of regno_ok_for_base_p for use here, when all pseudos
470 should count as OK. Arguments as for regno_ok_for_base_p. */
472 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
473 enum rtx_code outer_code
, enum rtx_code index_code
)
475 unsigned regno
= REGNO (reg
);
477 if (regno
>= FIRST_PSEUDO_REGISTER
)
479 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
482 /* Process address part in space AS (or all address if TOP_P) with
483 location *LOC to extract address characteristics.
485 If CONTEXT_P is false, we are looking at the base part of an
486 address, otherwise we are looking at the index part.
488 MODE is the mode of the memory reference; OUTER_CODE and INDEX_CODE
489 give the context that the rtx appears in; MODIFY_P if *LOC is
492 extract_loc_address_regs (bool top_p
, enum machine_mode mode
, addr_space_t as
,
493 rtx
*loc
, bool context_p
, enum rtx_code outer_code
,
494 enum rtx_code index_code
,
495 bool modify_p
, struct address
*ad
)
498 enum rtx_code code
= GET_CODE (x
);
520 /* When we have an address that is a sum, we must determine
521 whether registers are "base" or "index" regs. If there is a
522 sum of two registers, we must choose one to be the
525 rtx
*arg0_loc
= &XEXP (x
, 0);
526 rtx
*arg1_loc
= &XEXP (x
, 1);
528 rtx arg0
= *arg0_loc
;
529 rtx arg1
= *arg1_loc
;
530 enum rtx_code code0
= GET_CODE (arg0
);
531 enum rtx_code code1
= GET_CODE (arg1
);
533 /* Look inside subregs. */
536 arg0_loc
= &SUBREG_REG (arg0
);
538 code0
= GET_CODE (arg0
);
542 arg1_loc
= &SUBREG_REG (arg1
);
544 code1
= GET_CODE (arg1
);
547 if (CONSTANT_P (arg0
)
548 || code1
== PLUS
|| code1
== MULT
|| code1
== ASHIFT
)
554 code0
= GET_CODE (arg0
);
556 code1
= GET_CODE (arg1
);
558 /* If this machine only allows one register per address, it
559 must be in the first operand. */
560 if (MAX_REGS_PER_ADDRESS
== 1 || code
== LO_SUM
)
562 lra_assert (ad
->disp_loc
== NULL
);
563 ad
->disp_loc
= arg1_loc
;
564 extract_loc_address_regs (false, mode
, as
, arg0_loc
, false, code
,
565 code1
, modify_p
, ad
);
567 /* Base + disp addressing */
568 else if (code0
!= PLUS
&& code0
!= MULT
&& code0
!= ASHIFT
569 && CONSTANT_P (arg1
))
571 lra_assert (ad
->disp_loc
== NULL
);
572 ad
->disp_loc
= arg1_loc
;
573 extract_loc_address_regs (false, mode
, as
, arg0_loc
, false, PLUS
,
574 code1
, modify_p
, ad
);
576 /* If index and base registers are the same on this machine,
577 just record registers in any non-constant operands. We
578 assume here, as well as in the tests below, that all
579 addresses are in canonical form. */
580 else if (INDEX_REG_CLASS
581 == base_reg_class (VOIDmode
, as
, PLUS
, SCRATCH
)
582 && code0
!= PLUS
&& code0
!= MULT
&& code0
!= ASHIFT
)
584 extract_loc_address_regs (false, mode
, as
, arg0_loc
, false, PLUS
,
585 code1
, modify_p
, ad
);
586 lra_assert (! CONSTANT_P (arg1
));
587 extract_loc_address_regs (false, mode
, as
, arg1_loc
, true, PLUS
,
588 code0
, modify_p
, ad
);
590 /* It might be [base + ]index * scale + disp. */
591 else if (CONSTANT_P (arg1
))
593 lra_assert (ad
->disp_loc
== NULL
);
594 ad
->disp_loc
= arg1_loc
;
595 extract_loc_address_regs (false, mode
, as
, arg0_loc
, context_p
,
596 PLUS
, code0
, modify_p
, ad
);
598 /* If both operands are registers but one is already a hard
599 register of index or reg-base class, give the other the
600 class that the hard register is not. */
601 else if (code0
== REG
&& code1
== REG
602 && REGNO (arg0
) < FIRST_PSEUDO_REGISTER
604 = ok_for_base_p_nonstrict (arg0
, mode
, as
, PLUS
, REG
))
605 || ok_for_index_p_nonstrict (arg0
)))
607 extract_loc_address_regs (false, mode
, as
, arg0_loc
, ! base_ok_p
,
608 PLUS
, REG
, modify_p
, ad
);
609 extract_loc_address_regs (false, mode
, as
, arg1_loc
, base_ok_p
,
610 PLUS
, REG
, modify_p
, ad
);
612 else if (code0
== REG
&& code1
== REG
613 && REGNO (arg1
) < FIRST_PSEUDO_REGISTER
615 = ok_for_base_p_nonstrict (arg1
, mode
, as
, PLUS
, REG
))
616 || ok_for_index_p_nonstrict (arg1
)))
618 extract_loc_address_regs (false, mode
, as
, arg0_loc
, base_ok_p
,
619 PLUS
, REG
, modify_p
, ad
);
620 extract_loc_address_regs (false, mode
, as
, arg1_loc
, ! base_ok_p
,
621 PLUS
, REG
, modify_p
, ad
);
623 /* Otherwise, count equal chances that each might be a base or
624 index register. This case should be rare. */
627 extract_loc_address_regs (false, mode
, as
, arg0_loc
, false, PLUS
,
628 code1
, modify_p
, ad
);
629 extract_loc_address_regs (false, mode
, as
, arg1_loc
,
630 ad
->base_reg_loc
!= NULL
, PLUS
,
631 code0
, modify_p
, ad
);
639 rtx
*arg0_loc
= &XEXP (x
, 0);
640 enum rtx_code code0
= GET_CODE (*arg0_loc
);
642 if (code0
== CONST_INT
)
643 arg0_loc
= &XEXP (x
, 1);
644 extract_loc_address_regs (false, mode
, as
, arg0_loc
, true,
645 outer_code
, code
, modify_p
, ad
);
646 lra_assert (ad
->index_loc
== NULL
);
653 extract_loc_address_regs (false, mode
, as
, &XEXP (x
, 0), false,
654 code
, GET_CODE (XEXP (XEXP (x
, 1), 1)),
656 lra_assert (rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)));
657 ad
->base_reg_loc2
= &XEXP (XEXP (x
, 1), 0);
658 if (REG_P (XEXP (XEXP (x
, 1), 1)))
659 extract_loc_address_regs (false, mode
, as
, &XEXP (XEXP (x
, 1), 1),
660 true, code
, REG
, modify_p
, ad
);
667 extract_loc_address_regs (false, mode
, as
, &XEXP (x
, 0), false, code
,
671 /* We process memory as a register. That means we flatten
672 addresses. In other words, the final code will never
673 contains memory in an address even if the target supports
674 such addresses (it is too rare these days). Memory also can
675 occur in address as a result some previous transformations
676 like equivalence substitution. */
681 lra_assert (ad
->index_reg_loc
== NULL
);
682 ad
->index_reg_loc
= loc
;
686 lra_assert (ad
->base_reg_loc
== NULL
);
687 ad
->base_reg_loc
= loc
;
688 ad
->base_outer_code
= outer_code
;
689 ad
->index_code
= index_code
;
690 ad
->base_modify_p
= modify_p
;
695 const char *fmt
= GET_RTX_FORMAT (code
);
698 if (GET_RTX_LENGTH (code
) != 1
699 || fmt
[0] != 'e' || GET_CODE (XEXP (x
, 0)) != UNSPEC
)
701 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
703 extract_loc_address_regs (false, mode
, as
, &XEXP (x
, i
),
704 context_p
, code
, SCRATCH
,
708 /* fall through for case UNARY_OP (UNSPEC ...) */
712 if (ad
->disp_loc
== NULL
)
714 else if (ad
->base_reg_loc
== NULL
)
716 ad
->base_reg_loc
= loc
;
717 ad
->base_outer_code
= outer_code
;
718 ad
->index_code
= index_code
;
719 ad
->base_modify_p
= modify_p
;
723 lra_assert (ad
->index_reg_loc
== NULL
);
724 ad
->index_reg_loc
= loc
;
732 /* Describe address *LOC in AD. There are two cases:
733 - *LOC is the address in a (mem ...). In this case OUTER_CODE is MEM
734 and AS is the mem's address space.
735 - *LOC is matched to an address constraint such as 'p'. In this case
736 OUTER_CODE is ADDRESS and AS is ADDR_SPACE_GENERIC. */
738 extract_address_regs (enum machine_mode mem_mode
, addr_space_t as
,
739 rtx
*loc
, enum rtx_code outer_code
, struct address
*ad
)
741 ad
->base_reg_loc
= ad
->base_reg_loc2
742 = ad
->index_reg_loc
= ad
->index_loc
= ad
->disp_loc
= NULL
;
743 ad
->base_outer_code
= SCRATCH
;
744 ad
->index_code
= SCRATCH
;
745 ad
->base_modify_p
= false;
746 extract_loc_address_regs (true, mem_mode
, as
, loc
, false, outer_code
,
748 if (ad
->index_loc
== NULL
)
750 ad
->index_loc
= ad
->index_reg_loc
;
755 /* The page contains major code to choose the current insn alternative
756 and generate reloads for it. */
758 /* Return the offset from REGNO of the least significant register
761 This function is used to tell whether two registers satisfy
762 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
764 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
765 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
767 lra_constraint_offset (int regno
, enum machine_mode mode
)
769 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
770 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
771 && SCALAR_INT_MODE_P (mode
))
772 return hard_regno_nregs
[regno
][mode
] - 1;
776 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
777 if they are the same hard reg, and has special hacks for
778 auto-increment and auto-decrement. This is specifically intended for
779 process_alt_operands to use in determining whether two operands
780 match. X is the operand whose number is the lower of the two.
782 It is supposed that X is the output operand and Y is the input
783 operand. Y_HARD_REGNO is the final hard regno of register Y or
784 register in subreg Y as we know it now. Otherwise, it is a
787 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
790 RTX_CODE code
= GET_CODE (x
);
795 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
796 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
800 i
= get_hard_regno (x
);
804 if ((j
= y_hard_regno
) < 0)
807 i
+= lra_constraint_offset (i
, GET_MODE (x
));
808 j
+= lra_constraint_offset (j
, GET_MODE (y
));
813 /* If two operands must match, because they are really a single
814 operand of an assembler insn, then two post-increments are invalid
815 because the assembler insn would increment only once. On the
816 other hand, a post-increment matches ordinary indexing if the
817 post-increment is the output operand. */
818 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
819 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
821 /* Two pre-increments are invalid because the assembler insn would
822 increment only once. On the other hand, a pre-increment matches
823 ordinary indexing if the pre-increment is the input operand. */
824 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
825 || GET_CODE (y
) == PRE_MODIFY
)
826 return operands_match_p (x
, XEXP (y
, 0), -1);
830 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
831 && x
== SUBREG_REG (y
))
833 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
834 && SUBREG_REG (x
) == y
)
837 /* Now we have disposed of all the cases in which different rtx
839 if (code
!= GET_CODE (y
))
842 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
843 if (GET_MODE (x
) != GET_MODE (y
))
852 return XEXP (x
, 0) == XEXP (y
, 0);
854 return XSTR (x
, 0) == XSTR (y
, 0);
860 /* Compare the elements. If any pair of corresponding elements fail
861 to match, return false for the whole things. */
863 fmt
= GET_RTX_FORMAT (code
);
864 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
870 if (XWINT (x
, i
) != XWINT (y
, i
))
875 if (XINT (x
, i
) != XINT (y
, i
))
880 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
889 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
891 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
893 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
899 /* It is believed that rtx's at this level will never
900 contain anything but integers and other rtx's, except for
901 within LABEL_REFs and SYMBOL_REFs. */
909 /* True if X is a constant that can be forced into the constant pool.
910 MODE is the mode of the operand, or VOIDmode if not known. */
911 #define CONST_POOL_OK_P(MODE, X) \
912 ((MODE) != VOIDmode \
914 && GET_CODE (X) != HIGH \
915 && !targetm.cannot_force_const_mem (MODE, X))
917 /* True if C is a non-empty register class that has too few registers
918 to be safely used as a reload target class. */
919 #define SMALL_REGISTER_CLASS_P(C) \
920 (reg_class_size [(C)] == 1 \
921 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
923 /* If REG is a reload pseudo, try to make its class satisfying CL. */
925 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
927 enum reg_class rclass
;
929 /* Do not make more accurate class from reloads generated. They are
930 mostly moves with a lot of constraints. Making more accurate
931 class may results in very narrow class and impossibility of find
932 registers for several reloads of one insn. */
933 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
935 if (GET_CODE (reg
) == SUBREG
)
936 reg
= SUBREG_REG (reg
);
937 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
939 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
940 change_class (REGNO (reg
), rclass
, " Change", true);
943 /* Generate reloads for matching OUT and INS (array of input operand
944 numbers with end marker -1) with reg class GOAL_CLASS. Add input
945 and output reloads correspondingly to the lists *BEFORE and
948 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
949 rtx
*before
, rtx
*after
)
952 rtx new_in_reg
, new_out_reg
, reg
;
953 enum machine_mode inmode
, outmode
;
954 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
955 rtx out_rtx
= *curr_id
->operand_loc
[out
];
957 outmode
= curr_operand_mode
[out
];
958 inmode
= curr_operand_mode
[ins
[0]];
959 push_to_sequence (*before
);
960 if (inmode
!= outmode
)
962 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
965 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
967 if (SCALAR_INT_MODE_P (inmode
))
968 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
970 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
975 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
977 if (SCALAR_INT_MODE_P (outmode
))
978 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
980 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
981 /* NEW_IN_REG is non-paradoxical subreg. We don't want
982 NEW_OUT_REG living above. We add clobber clause for
984 emit_clobber (new_out_reg
);
989 /* Pseudos have values -- see comments for lra_reg_info.
990 Different pseudos with the same value do not conflict even if
991 they live in the same place. When we create a pseudo we
992 assign value of original pseudo (if any) from which we
993 created the new pseudo. If we create the pseudo from the
994 input pseudo, the new pseudo will no conflict with the input
995 pseudo which is wrong when the input pseudo lives after the
996 insn and as the new pseudo value is changed by the insn
997 output. Therefore we create the new pseudo from the output.
999 We cannot reuse the current output register because we might
1000 have a situation like "a <- a op b", where the constraints
1001 force the second input operand ("b") to match the output
1002 operand ("a"). "b" must then be copied into a new register
1003 so that it doesn't clobber the current value of "a". */
1005 new_in_reg
= new_out_reg
1006 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
1009 /* In and out operand can be got from transformations before
1010 processing insn constraints. One example of such transformations
1011 is subreg reloading (see function simplify_operand_subreg). The
1012 new pseudos created by the transformations might have inaccurate
1013 class (ALL_REGS) and we should make their classes more
1015 narrow_reload_pseudo_class (in_rtx
, goal_class
);
1016 narrow_reload_pseudo_class (out_rtx
, goal_class
);
1017 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
1018 *before
= get_insns ();
1020 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
1023 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
1024 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
1025 *curr_id
->operand_loc
[in
] = new_in_reg
;
1027 lra_update_dups (curr_id
, ins
);
1028 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
1031 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
1033 *after
= get_insns ();
1036 *curr_id
->operand_loc
[out
] = new_out_reg
;
1037 lra_update_dup (curr_id
, out
);
1040 /* Return register class which is union of all reg classes in insn
1041 constraint alternative string starting with P. */
1042 static enum reg_class
1043 reg_class_from_constraints (const char *p
)
1046 enum reg_class op_class
= NO_REGS
;
1049 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1056 op_class
= (reg_class_subunion
1057 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1058 ADDRESS
, SCRATCH
)]);
1063 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
1067 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1069 #ifdef EXTRA_CONSTRAINT_STR
1070 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1072 = (reg_class_subunion
1073 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1074 ADDRESS
, SCRATCH
)]);
1080 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
1083 while ((p
+= len
), c
);
1087 /* If OP is a register, return the class of the register as per
1088 get_reg_class, otherwise return NO_REGS. */
1089 static inline enum reg_class
1090 get_op_class (rtx op
)
1092 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
1095 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
1096 otherwise. If modes of MEM_PSEUDO and VAL are different, use
1097 SUBREG for VAL to make them equal. */
1099 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
1101 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
1102 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
1103 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
1106 ? gen_move_insn (mem_pseudo
, val
)
1107 : gen_move_insn (val
, mem_pseudo
));
1110 /* Process a special case insn (register move), return true if we
1111 don't need to process it anymore. Return that RTL was changed
1112 through CHANGE_P and macro SECONDARY_MEMORY_NEEDED says to use
1113 secondary memory through SEC_MEM_P. */
1115 check_and_process_move (bool *change_p
, bool *sec_mem_p
)
1118 rtx set
, dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
1119 enum reg_class dclass
, sclass
, secondary_class
;
1120 enum machine_mode sreg_mode
;
1121 secondary_reload_info sri
;
1123 *sec_mem_p
= *change_p
= false;
1124 if ((set
= single_set (curr_insn
)) == NULL
)
1126 dreg
= dest
= SET_DEST (set
);
1127 sreg
= src
= SET_SRC (set
);
1128 /* Quick check on the right move insn which does not need
1130 if ((dclass
= get_op_class (dest
)) != NO_REGS
1131 && (sclass
= get_op_class (src
)) != NO_REGS
1132 /* The backend guarantees that register moves of cost 2 never
1134 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2)
1136 if (GET_CODE (dest
) == SUBREG
)
1137 dreg
= SUBREG_REG (dest
);
1138 if (GET_CODE (src
) == SUBREG
)
1139 sreg
= SUBREG_REG (src
);
1140 if (! REG_P (dreg
) || ! REG_P (sreg
))
1142 sclass
= dclass
= NO_REGS
;
1143 dreg
= get_equiv_substitution (dreg
);
1145 dclass
= get_reg_class (REGNO (dreg
));
1146 if (dclass
== ALL_REGS
)
1147 /* ALL_REGS is used for new pseudos created by transformations
1148 like reload of SUBREG_REG (see function
1149 simplify_operand_subreg). We don't know their class yet. We
1150 should figure out the class from processing the insn
1151 constraints not in this fast path function. Even if ALL_REGS
1152 were a right class for the pseudo, secondary_... hooks usually
1153 are not define for ALL_REGS. */
1155 sreg_mode
= GET_MODE (sreg
);
1157 sreg
= get_equiv_substitution (sreg
);
1159 sclass
= get_reg_class (REGNO (sreg
));
1160 if (sclass
== ALL_REGS
)
1161 /* See comments above. */
1163 #ifdef SECONDARY_MEMORY_NEEDED
1164 if (dclass
!= NO_REGS
&& sclass
!= NO_REGS
1165 && SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
)))
1171 sri
.prev_sri
= NULL
;
1172 sri
.icode
= CODE_FOR_nothing
;
1174 secondary_class
= NO_REGS
;
1175 /* Set up hard register for a reload pseudo for hook
1176 secondary_reload because some targets just ignore unassigned
1177 pseudos in the hook. */
1178 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
1180 dregno
= REGNO (dreg
);
1181 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
1185 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
1187 sregno
= REGNO (sreg
);
1188 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
1192 if (sclass
!= NO_REGS
)
1194 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
1195 (reg_class_t
) sclass
,
1196 GET_MODE (src
), &sri
);
1197 if (sclass
== NO_REGS
1198 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
1199 && dclass
!= NO_REGS
))
1201 #if ENABLE_ASSERT_CHECKING
1202 enum reg_class old_sclass
= secondary_class
;
1203 secondary_reload_info old_sri
= sri
;
1206 sri
.prev_sri
= NULL
;
1207 sri
.icode
= CODE_FOR_nothing
;
1210 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
1211 (reg_class_t
) dclass
,
1213 /* Check the target hook consistency. */
1215 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1216 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
1217 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
1220 reg_renumber
[sregno
] = -1;
1222 reg_renumber
[dregno
] = -1;
1223 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
1227 if (secondary_class
!= NO_REGS
)
1228 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1232 if (old_sreg
!= sreg
)
1233 sreg
= copy_rtx (sreg
);
1234 if (sri
.icode
== CODE_FOR_nothing
)
1235 lra_emit_move (new_reg
, sreg
);
1238 enum reg_class scratch_class
;
1240 scratch_class
= (reg_class_from_constraints
1241 (insn_data
[sri
.icode
].operand
[2].constraint
));
1242 scratch_reg
= (lra_create_new_reg_with_unique_value
1243 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1244 scratch_class
, "scratch"));
1245 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1246 sreg
, scratch_reg
));
1248 before
= get_insns ();
1250 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1251 if (new_reg
!= NULL_RTX
)
1253 if (GET_CODE (src
) == SUBREG
)
1254 SUBREG_REG (src
) = new_reg
;
1256 SET_SRC (set
) = new_reg
;
1260 if (lra_dump_file
!= NULL
)
1262 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1263 debug_rtl_slim (lra_dump_file
, curr_insn
, curr_insn
, -1, 0);
1265 lra_set_insn_deleted (curr_insn
);
1271 /* The following data describe the result of process_alt_operands.
1272 The data are used in curr_insn_transform to generate reloads. */
1274 /* The chosen reg classes which should be used for the corresponding
1276 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1277 /* True if the operand should be the same as another operand and that
1278 other operand does not need a reload. */
1279 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1280 /* True if the operand does not need a reload. */
1281 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1282 /* True if the operand can be offsetable memory. */
1283 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1284 /* The number of an operand to which given operand can be matched to. */
1285 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1286 /* The number of elements in the following array. */
1287 static int goal_alt_dont_inherit_ops_num
;
1288 /* Numbers of operands whose reload pseudos should not be inherited. */
1289 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1290 /* True if the insn commutative operands should be swapped. */
1291 static bool goal_alt_swapped
;
1292 /* The chosen insn alternative. */
1293 static int goal_alt_number
;
1295 /* The following five variables are used to choose the best insn
1296 alternative. They reflect final characteristics of the best
1299 /* Number of necessary reloads and overall cost reflecting the
1300 previous value and other unpleasantness of the best alternative. */
1301 static int best_losers
, best_overall
;
1302 /* Number of small register classes used for operands of the best
1304 static int best_small_class_operands_num
;
1305 /* Overall number hard registers used for reloads. For example, on
1306 some targets we need 2 general registers to reload DFmode and only
1307 one floating point register. */
1308 static int best_reload_nregs
;
1309 /* Overall number reflecting distances of previous reloading the same
1310 value. The distances are counted from the current BB start. It is
1311 used to improve inheritance chances. */
1312 static int best_reload_sum
;
1314 /* True if the current insn should have no correspondingly input or
1316 static bool no_input_reloads_p
, no_output_reloads_p
;
1318 /* True if we swapped the commutative operands in the current
1320 static int curr_swapped
;
1322 /* Arrange for address element *LOC to be a register of class CL.
1323 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1324 automodified value; handle that case by adding the required output
1325 reloads to list AFTER. Return true if the RTL was changed. */
1327 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1330 enum reg_class rclass
, new_class
;
1333 enum machine_mode mode
;
1334 bool before_p
= false;
1336 mode
= GET_MODE (reg
);
1339 /* Always reload memory in an address even if the target supports
1341 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1346 regno
= REGNO (reg
);
1347 rclass
= get_reg_class (regno
);
1348 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1350 if (lra_dump_file
!= NULL
)
1352 fprintf (lra_dump_file
,
1353 "Changing pseudo %d in address of insn %u on equiv ",
1354 REGNO (reg
), INSN_UID (curr_insn
));
1355 print_value_slim (lra_dump_file
, *loc
, 1);
1356 fprintf (lra_dump_file
, "\n");
1358 *loc
= copy_rtx (*loc
);
1360 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1363 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1364 mode
, reg
, cl
, "address", &new_reg
))
1367 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1369 change_class (regno
, new_class
, " Change", true);
1377 push_to_sequence (*before
);
1378 lra_emit_move (new_reg
, reg
);
1379 *before
= get_insns ();
1386 lra_emit_move (reg
, new_reg
);
1388 *after
= get_insns ();
1394 #ifndef SLOW_UNALIGNED_ACCESS
1395 #define SLOW_UNALIGNED_ACCESS(mode, align) 0
1398 /* Make reloads for subreg in operand NOP with internal subreg mode
1399 REG_MODE, add new reloads for further processing. Return true if
1400 any reload was generated. */
1402 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1406 enum machine_mode mode
;
1408 rtx operand
= *curr_id
->operand_loc
[nop
];
1410 before
= after
= NULL_RTX
;
1412 if (GET_CODE (operand
) != SUBREG
)
1415 mode
= GET_MODE (operand
);
1416 reg
= SUBREG_REG (operand
);
1417 /* If we change address for paradoxical subreg of memory, the
1418 address might violate the necessary alignment or the access might
1419 be slow. So take this into consideration. */
1421 && ((! STRICT_ALIGNMENT
1422 && ! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
)))
1423 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1424 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1426 alter_subreg (curr_id
->operand_loc
[nop
], false);
1429 /* Put constant into memory when we have mixed modes. It generates
1430 a better code in most cases as it does not need a secondary
1431 reload memory. It also prevents LRA looping when LRA is using
1432 secondary reload memory again and again. */
1433 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1434 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1436 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1437 alter_subreg (curr_id
->operand_loc
[nop
], false);
1440 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1441 if there may be a problem accessing OPERAND in the outer
1444 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1445 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1446 /* Don't reload paradoxical subregs because we could be looping
1447 having repeatedly final regno out of hard regs range. */
1448 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1449 >= hard_regno_nregs
[hard_regno
][mode
])
1450 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1451 SUBREG_BYTE (operand
), mode
) < 0)
1452 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1454 enum op_type type
= curr_static_id
->operand
[nop
].type
;
1455 /* The class will be defined later in curr_insn_transform. */
1456 enum reg_class rclass
1457 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1459 new_reg
= lra_create_new_reg_with_unique_value (reg_mode
, reg
, rclass
,
1461 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (new_reg
));
1463 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
))
1465 push_to_sequence (before
);
1466 lra_emit_move (new_reg
, reg
);
1467 before
= get_insns ();
1473 lra_emit_move (reg
, new_reg
);
1475 after
= get_insns ();
1478 SUBREG_REG (operand
) = new_reg
;
1479 lra_process_new_insns (curr_insn
, before
, after
,
1480 "Inserting subreg reload");
1486 /* Return TRUE if X refers for a hard register from SET. */
1488 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1490 int i
, j
, x_hard_regno
;
1491 enum machine_mode mode
;
1497 code
= GET_CODE (x
);
1498 mode
= GET_MODE (x
);
1502 code
= GET_CODE (x
);
1503 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1504 mode
= GET_MODE (x
);
1509 x_hard_regno
= get_hard_regno (x
);
1510 return (x_hard_regno
>= 0
1511 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1516 enum machine_mode mode
= GET_MODE (x
);
1517 rtx
*addr_loc
= &XEXP (x
, 0);
1519 extract_address_regs (mode
, MEM_ADDR_SPACE (x
), addr_loc
, MEM
, &ad
);
1520 if (ad
.base_reg_loc
!= NULL
)
1522 if (uses_hard_regs_p (*ad
.base_reg_loc
, set
))
1525 if (ad
.index_reg_loc
!= NULL
)
1527 if (uses_hard_regs_p (*ad
.index_reg_loc
, set
))
1531 fmt
= GET_RTX_FORMAT (code
);
1532 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1536 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1539 else if (fmt
[i
] == 'E')
1541 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1542 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1549 /* Return true if OP is a spilled pseudo. */
1551 spilled_pseudo_p (rtx op
)
1554 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1557 /* Return true if X is a general constant. */
1559 general_constant_p (rtx x
)
1561 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1564 /* Cost factor for each additional reload and maximal cost bound for
1565 insn reloads. One might ask about such strange numbers. Their
1566 values occurred historically from former reload pass. */
1567 #define LOSER_COST_FACTOR 6
1568 #define MAX_OVERALL_COST_BOUND 600
1570 /* Major function to choose the current insn alternative and what
1571 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1572 negative we should consider only this alternative. Return false if
1573 we can not choose the alternative or find how to reload the
1576 process_alt_operands (int only_alternative
)
1579 int nop
, small_class_operands_num
, overall
, nalt
;
1580 int n_alternatives
= curr_static_id
->n_alternatives
;
1581 int n_operands
= curr_static_id
->n_operands
;
1582 /* LOSERS counts the operands that don't fit this alternative and
1583 would require loading. */
1585 /* REJECT is a count of how undesirable this alternative says it is
1586 if any reloading is required. If the alternative matches exactly
1587 then REJECT is ignored, but otherwise it gets this much counted
1588 against it in addition to the reloading needed. */
1590 /* The number of elements in the following array. */
1591 int early_clobbered_regs_num
;
1592 /* Numbers of operands which are early clobber registers. */
1593 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1594 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1595 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1596 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1597 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1598 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1599 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1600 /* The number of elements in the following array. */
1601 int curr_alt_dont_inherit_ops_num
;
1602 /* Numbers of operands whose reload pseudos should not be inherited. */
1603 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1605 /* The register when the operand is a subreg of register, otherwise the
1607 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1608 /* The register if the operand is a register or subreg of register,
1610 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1611 int hard_regno
[MAX_RECOG_OPERANDS
];
1612 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1613 int reload_nregs
, reload_sum
;
1617 /* Calculate some data common for all alternatives to speed up the
1619 for (nop
= 0; nop
< n_operands
; nop
++)
1621 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1622 /* The real hard regno of the operand after the allocation. */
1623 hard_regno
[nop
] = get_hard_regno (op
);
1625 operand_reg
[nop
] = op
;
1626 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1627 if (GET_CODE (operand_reg
[nop
]) == SUBREG
)
1629 operand_reg
[nop
] = SUBREG_REG (operand_reg
[nop
]);
1630 if (GET_MODE_SIZE (biggest_mode
[nop
])
1631 < GET_MODE_SIZE (GET_MODE (operand_reg
[nop
])))
1632 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1634 if (REG_P (operand_reg
[nop
]))
1635 no_subreg_reg_operand
[nop
] = operand_reg
[nop
];
1637 operand_reg
[nop
] = NULL_RTX
;
1640 /* The constraints are made of several alternatives. Each operand's
1641 constraint looks like foo,bar,... with commas separating the
1642 alternatives. The first alternatives for all operands go
1643 together, the second alternatives go together, etc.
1645 First loop over alternatives. */
1646 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1648 /* Loop over operands for one constraint alternative. */
1649 #ifdef HAVE_ATTR_enabled
1650 if (curr_id
->alternative_enabled_p
!= NULL
1651 && ! curr_id
->alternative_enabled_p
[nalt
])
1655 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1658 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1659 for (nop
= 0; nop
< n_operands
; nop
++)
1660 reject
+= (curr_static_id
1661 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1662 early_clobbered_regs_num
= 0;
1664 for (nop
= 0; nop
< n_operands
; nop
++)
1668 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1669 bool win
, did_match
, offmemok
, early_clobber_p
;
1670 /* false => this operand can be reloaded somehow for this
1673 /* true => this operand can be reloaded if the alternative
1676 /* True if a constant forced into memory would be OK for
1679 enum reg_class this_alternative
, this_costly_alternative
;
1680 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1681 bool this_alternative_match_win
, this_alternative_win
;
1682 bool this_alternative_offmemok
;
1683 enum machine_mode mode
;
1685 opalt_num
= nalt
* n_operands
+ nop
;
1686 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1688 /* Fast track for no constraints at all. */
1689 curr_alt
[nop
] = NO_REGS
;
1690 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1691 curr_alt_win
[nop
] = true;
1692 curr_alt_match_win
[nop
] = false;
1693 curr_alt_offmemok
[nop
] = false;
1694 curr_alt_matches
[nop
] = -1;
1698 op
= no_subreg_reg_operand
[nop
];
1699 mode
= curr_operand_mode
[nop
];
1701 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1704 early_clobber_p
= false;
1705 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1707 this_costly_alternative
= this_alternative
= NO_REGS
;
1708 /* We update set of possible hard regs besides its class
1709 because reg class might be inaccurate. For example,
1710 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1711 is translated in HI_REGS because classes are merged by
1712 pairs and there is no accurate intermediate class. */
1713 CLEAR_HARD_REG_SET (this_alternative_set
);
1714 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1715 this_alternative_win
= false;
1716 this_alternative_match_win
= false;
1717 this_alternative_offmemok
= false;
1718 this_alternative_matches
= -1;
1720 /* An empty constraint should be excluded by the fast
1722 lra_assert (*p
!= 0 && *p
!= ',');
1724 /* Scan this alternative's specs for this operand; set WIN
1725 if the operand fits any letter in this alternative.
1726 Otherwise, clear BADOP if this operand could fit some
1727 letter after reloads, or set WINREG if this operand could
1728 fit after reloads provided the constraint allows some
1733 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1742 case '=': case '+': case '?': case '*': case '!':
1743 case ' ': case '\t':
1747 /* We only support one commutative marker, the first
1748 one. We already set commutative above. */
1752 early_clobber_p
= true;
1756 /* Ignore rest of this alternative. */
1760 case '0': case '1': case '2': case '3': case '4':
1761 case '5': case '6': case '7': case '8': case '9':
1766 m
= strtoul (p
, &end
, 10);
1769 lra_assert (nop
> m
);
1771 this_alternative_matches
= m
;
1772 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1773 /* We are supposed to match a previous operand.
1774 If we do, we win if that one did. If we do
1775 not, count both of the operands as losers.
1776 (This is too conservative, since most of the
1777 time only a single reload insn will be needed
1778 to make the two operands win. As a result,
1779 this alternative may be rejected when it is
1780 actually desirable.) */
1782 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1783 *curr_id
->operand_loc
[m
], m_hregno
))
1785 /* We should reject matching of an early
1786 clobber operand if the matching operand is
1787 not dying in the insn. */
1788 if (! curr_static_id
->operand
[m
].early_clobber
1789 || operand_reg
[nop
] == NULL_RTX
1790 || (find_regno_note (curr_insn
, REG_DEAD
,
1791 REGNO (operand_reg
[nop
]))
1797 /* If we are matching a non-offsettable
1798 address where an offsettable address was
1799 expected, then we must reject this
1800 combination, because we can't reload
1802 if (curr_alt_offmemok
[m
]
1803 && MEM_P (*curr_id
->operand_loc
[m
])
1804 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1810 /* Operands don't match. Both operands must
1811 allow a reload register, otherwise we
1812 cannot make them match. */
1813 if (curr_alt
[m
] == NO_REGS
)
1815 /* Retroactively mark the operand we had to
1816 match as a loser, if it wasn't already and
1817 it wasn't matched to a register constraint
1818 (e.g it might be matched by memory). */
1820 && (operand_reg
[m
] == NULL_RTX
1821 || hard_regno
[m
] < 0))
1825 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1826 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1829 /* We prefer no matching alternatives because
1830 it gives more freedom in RA. */
1831 if (operand_reg
[nop
] == NULL_RTX
1832 || (find_regno_note (curr_insn
, REG_DEAD
,
1833 REGNO (operand_reg
[nop
]))
1837 /* If we have to reload this operand and some
1838 previous operand also had to match the same
1839 thing as this operand, we don't know how to do
1841 if (!match_p
|| !curr_alt_win
[m
])
1843 for (i
= 0; i
< nop
; i
++)
1844 if (curr_alt_matches
[i
] == m
)
1852 /* This can be fixed with reloads if the operand
1853 we are supposed to match can be fixed with
1856 this_alternative
= curr_alt
[m
];
1857 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1862 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1864 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1865 IOR_HARD_REG_SET (this_alternative_set
,
1866 reg_class_contents
[cl
]);
1869 this_costly_alternative
1870 = reg_class_subunion
[this_costly_alternative
][cl
];
1871 IOR_HARD_REG_SET (this_costly_alternative_set
,
1872 reg_class_contents
[cl
]);
1878 case TARGET_MEM_CONSTRAINT
:
1879 if (MEM_P (op
) || spilled_pseudo_p (op
))
1881 if (CONST_POOL_OK_P (mode
, op
))
1888 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1889 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1895 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1896 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1900 /* Memory op whose address is not offsettable. */
1903 && ! offsettable_nonstrict_memref_p (op
))
1907 /* Memory operand whose address is offsettable. */
1910 && offsettable_nonstrict_memref_p (op
))
1911 || spilled_pseudo_p (op
))
1913 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
))
1921 if (GET_CODE (op
) == CONST_DOUBLE
1922 || (GET_CODE (op
) == CONST_VECTOR
1923 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1929 if (GET_CODE (op
) == CONST_DOUBLE
1930 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1935 if (CONST_INT_P (op
)
1936 || (GET_CODE (op
) == CONST_DOUBLE
&& mode
== VOIDmode
))
1939 if (general_constant_p (op
))
1944 if (CONST_INT_P (op
)
1945 || (GET_CODE (op
) == CONST_DOUBLE
&& mode
== VOIDmode
))
1957 if (CONST_INT_P (op
)
1958 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1963 /* This constraint should be excluded by the fast
1970 || general_constant_p (op
)
1971 || spilled_pseudo_p (op
))
1973 /* Drop through into 'r' case. */
1977 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1978 IOR_HARD_REG_SET (this_alternative_set
,
1979 reg_class_contents
[GENERAL_REGS
]);
1982 this_costly_alternative
1983 = (reg_class_subunion
1984 [this_costly_alternative
][GENERAL_REGS
]);
1985 IOR_HARD_REG_SET (this_costly_alternative_set
,
1986 reg_class_contents
[GENERAL_REGS
]);
1991 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1993 #ifdef EXTRA_CONSTRAINT_STR
1994 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1996 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1998 else if (spilled_pseudo_p (op
))
2001 /* If we didn't already win, we can reload
2002 constants via force_const_mem, and other
2003 MEMs by reloading the address like for
2005 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
))
2011 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
2013 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2016 /* If we didn't already win, we can reload
2017 the address into a base register. */
2018 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2021 = reg_class_subunion
[this_alternative
][cl
];
2022 IOR_HARD_REG_SET (this_alternative_set
,
2023 reg_class_contents
[cl
]);
2026 this_costly_alternative
2027 = (reg_class_subunion
2028 [this_costly_alternative
][cl
]);
2029 IOR_HARD_REG_SET (this_costly_alternative_set
,
2030 reg_class_contents
[cl
]);
2036 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
2042 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
2043 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
2044 IOR_HARD_REG_SET (this_alternative_set
,
2045 reg_class_contents
[cl
]);
2048 this_costly_alternative
2049 = reg_class_subunion
[this_costly_alternative
][cl
];
2050 IOR_HARD_REG_SET (this_costly_alternative_set
,
2051 reg_class_contents
[cl
]);
2054 if (mode
== BLKmode
)
2059 if (hard_regno
[nop
] >= 0
2060 && in_hard_reg_set_p (this_alternative_set
,
2061 mode
, hard_regno
[nop
]))
2063 else if (hard_regno
[nop
] < 0
2064 && in_class_p (op
, this_alternative
, NULL
))
2069 if (c
!= ' ' && c
!= '\t')
2070 costly_p
= c
== '*';
2072 while ((p
+= len
), c
);
2074 /* Record which operands fit this alternative. */
2077 this_alternative_win
= true;
2078 if (operand_reg
[nop
] != NULL_RTX
)
2080 if (hard_regno
[nop
] >= 0)
2082 if (in_hard_reg_set_p (this_costly_alternative_set
,
2083 mode
, hard_regno
[nop
]))
2088 /* Prefer won reg to spilled pseudo under other equal
2091 if (in_class_p (operand_reg
[nop
],
2092 this_costly_alternative
, NULL
))
2095 /* We simulate the behaviour of old reload here.
2096 Although scratches need hard registers and it
2097 might result in spilling other pseudos, no reload
2098 insns are generated for the scratches. So it
2099 might cost something but probably less than old
2100 reload pass believes. */
2101 if (lra_former_scratch_p (REGNO (operand_reg
[nop
])))
2102 reject
+= LOSER_COST_FACTOR
;
2106 this_alternative_match_win
= true;
2109 int const_to_mem
= 0;
2113 = (this_alternative
== NO_REGS
2114 || (hard_reg_set_subset_p
2115 (reg_class_contents
[this_alternative
],
2116 lra_no_alloc_regs
)));
2117 /* If this operand accepts a register, and if the
2118 register class has at least one allocatable register,
2119 then this operand can be reloaded. */
2120 if (winreg
&& !no_regs_p
)
2126 this_alternative_offmemok
= offmemok
;
2127 if (this_costly_alternative
!= NO_REGS
)
2129 /* If the operand is dying, has a matching constraint,
2130 and satisfies constraints of the matched operand
2131 which failed to satisfy the own constraints, we do
2132 not need to generate a reload insn for this
2134 if (!(this_alternative_matches
>= 0
2135 && !curr_alt_win
[this_alternative_matches
]
2137 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2138 && (hard_regno
[nop
] >= 0
2139 ? in_hard_reg_set_p (this_alternative_set
,
2140 mode
, hard_regno
[nop
])
2141 : in_class_p (op
, this_alternative
, NULL
))))
2143 if (operand_reg
[nop
] != NULL_RTX
2144 /* Output operands and matched input operands are
2145 not inherited. The following conditions do not
2146 exactly describe the previous statement but they
2147 are pretty close. */
2148 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2149 && (this_alternative_matches
< 0
2150 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2152 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2156 if (last_reload
> bb_reload_num
)
2157 reload_sum
+= last_reload
- bb_reload_num
;
2159 /* If this is a constant that is reloaded into the
2160 desired class by copying it to memory first, count
2161 that as another reload. This is consistent with
2162 other code and is required to avoid choosing another
2163 alternative when the constant is moved into memory.
2164 Note that the test here is precisely the same as in
2165 the code below that calls force_const_mem. */
2166 if (CONST_POOL_OK_P (mode
, op
)
2167 && ((targetm
.preferred_reload_class
2168 (op
, this_alternative
) == NO_REGS
)
2169 || no_input_reloads_p
))
2176 /* Alternative loses if it requires a type of reload not
2177 permitted for this insn. We can always reload
2178 objects with a REG_UNUSED note. */
2179 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2180 && no_output_reloads_p
2181 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2182 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2183 && no_input_reloads_p
&& ! const_to_mem
))
2186 /* If we can't reload this value at all, reject this
2187 alternative. Note that we could also lose due to
2188 LIMIT_RELOAD_CLASS, but we don't check that here. */
2189 if (! CONSTANT_P (op
) && ! no_regs_p
)
2191 if (targetm
.preferred_reload_class
2192 (op
, this_alternative
) == NO_REGS
)
2193 reject
= MAX_OVERALL_COST_BOUND
;
2195 if (curr_static_id
->operand
[nop
].type
== OP_OUT
2196 && (targetm
.preferred_output_reload_class
2197 (op
, this_alternative
) == NO_REGS
))
2198 reject
= MAX_OVERALL_COST_BOUND
;
2201 if (! ((const_to_mem
&& constmemok
)
2202 || (MEM_P (op
) && offmemok
)))
2204 /* We prefer to reload pseudos over reloading other
2205 things, since such reloads may be able to be
2206 eliminated later. So bump REJECT in other cases.
2207 Don't do this in the case where we are forcing a
2208 constant into memory and it will then win since
2209 we don't want to have a different alternative
2211 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2216 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2219 /* Input reloads can be inherited more often than output
2220 reloads can be removed, so penalize output
2222 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2226 if (early_clobber_p
)
2228 /* ??? We check early clobbers after processing all operands
2229 (see loop below) and there we update the costs more.
2230 Should we update the cost (may be approximately) here
2231 because of early clobber register reloads or it is a rare
2232 or non-important thing to be worth to do it. */
2233 overall
= losers
* LOSER_COST_FACTOR
+ reject
;
2234 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2237 curr_alt
[nop
] = this_alternative
;
2238 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2239 curr_alt_win
[nop
] = this_alternative_win
;
2240 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2241 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2242 curr_alt_matches
[nop
] = this_alternative_matches
;
2244 if (this_alternative_matches
>= 0
2245 && !did_match
&& !this_alternative_win
)
2246 curr_alt_win
[this_alternative_matches
] = false;
2248 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2249 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2252 curr_alt_dont_inherit_ops_num
= 0;
2253 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2255 int i
, j
, clobbered_hard_regno
;
2256 HARD_REG_SET temp_set
;
2258 i
= early_clobbered_nops
[nop
];
2259 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2260 || hard_regno
[i
] < 0)
2262 clobbered_hard_regno
= hard_regno
[i
];
2263 CLEAR_HARD_REG_SET (temp_set
);
2264 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2265 for (j
= 0; j
< n_operands
; j
++)
2267 /* We don't want process insides of match_operator and
2268 match_parallel because otherwise we would process
2269 their operands once again generating a wrong
2271 || curr_static_id
->operand
[j
].is_operator
)
2273 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2274 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2276 else if (uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2278 if (j
>= n_operands
)
2280 /* We need to reload early clobbered register. */
2281 for (j
= 0; j
< n_operands
; j
++)
2282 if (curr_alt_matches
[j
] == i
)
2284 curr_alt_match_win
[j
] = false;
2286 overall
+= LOSER_COST_FACTOR
;
2288 if (! curr_alt_match_win
[i
])
2289 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2292 /* Remember pseudos used for match reloads are never
2294 lra_assert (curr_alt_matches
[i
] >= 0);
2295 curr_alt_win
[curr_alt_matches
[i
]] = false;
2297 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2299 overall
+= LOSER_COST_FACTOR
;
2301 small_class_operands_num
= 0;
2302 for (nop
= 0; nop
< n_operands
; nop
++)
2303 small_class_operands_num
2304 += SMALL_REGISTER_CLASS_P (curr_alt
[nop
]) ? 1 : 0;
2306 /* If this alternative can be made to work by reloading, and it
2307 needs less reloading than the others checked so far, record
2308 it as the chosen goal for reloading. */
2309 if ((best_losers
!= 0 && losers
== 0)
2310 || (((best_losers
== 0 && losers
== 0)
2311 || (best_losers
!= 0 && losers
!= 0))
2312 && (best_overall
> overall
2313 || (best_overall
== overall
2314 /* If the cost of the reloads is the same,
2315 prefer alternative which requires minimal
2316 number of small register classes for the
2317 operands. This improves chances of reloads
2318 for insn requiring small register
2320 && (small_class_operands_num
2321 < best_small_class_operands_num
2322 || (small_class_operands_num
2323 == best_small_class_operands_num
2324 && (reload_nregs
< best_reload_nregs
2325 || (reload_nregs
== best_reload_nregs
2326 && best_reload_sum
< reload_sum
))))))))
2328 for (nop
= 0; nop
< n_operands
; nop
++)
2330 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2331 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2332 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2333 goal_alt
[nop
] = curr_alt
[nop
];
2334 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2336 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2337 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2338 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2339 goal_alt_swapped
= curr_swapped
;
2340 best_overall
= overall
;
2341 best_losers
= losers
;
2342 best_small_class_operands_num
= small_class_operands_num
;
2343 best_reload_nregs
= reload_nregs
;
2344 best_reload_sum
= reload_sum
;
2345 goal_alt_number
= nalt
;
2348 /* Everything is satisfied. Do not process alternatives
2357 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2358 space AS, and check that each pseudo has the proper kind of hard
2361 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2362 rtx addr
, addr_space_t as
)
2364 #ifdef GO_IF_LEGITIMATE_ADDRESS
2365 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2366 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2372 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2376 /* Make reload base reg + disp from address AD in space AS of memory
2377 with MODE into a new pseudo. Return the new pseudo. */
2379 base_plus_disp_to_reg (enum machine_mode mode
, addr_space_t as
,
2385 lra_assert (ad
->base_reg_loc
!= NULL
&& ad
->disp_loc
!= NULL
);
2386 cl
= base_reg_class (mode
, as
, ad
->base_outer_code
, ad
->index_code
);
2387 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "base + disp");
2388 lra_emit_add (new_reg
, *ad
->base_reg_loc
, *ad
->disp_loc
);
2392 /* Make substitution in address AD in space AS with location ADDR_LOC.
2393 Update AD and ADDR_LOC if it is necessary. Return true if a
2394 substitution was made. */
2396 equiv_address_substitution (struct address
*ad
, rtx
*addr_loc
,
2397 enum machine_mode mode
, addr_space_t as
,
2400 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
;
2401 HOST_WIDE_INT disp
, scale
;
2404 if (ad
->base_reg_loc
== NULL
)
2405 base_reg
= new_base_reg
= NULL_RTX
;
2408 base_reg
= *ad
->base_reg_loc
;
2409 new_base_reg
= get_equiv_substitution (base_reg
);
2411 if (ad
->index_reg_loc
== NULL
)
2412 index_reg
= new_index_reg
= NULL_RTX
;
2415 index_reg
= *ad
->index_reg_loc
;
2416 new_index_reg
= get_equiv_substitution (index_reg
);
2418 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2422 if (lra_dump_file
!= NULL
)
2424 fprintf (lra_dump_file
, "Changing address in insn %d ",
2425 INSN_UID (curr_insn
));
2426 print_value_slim (lra_dump_file
, *addr_loc
, 1);
2428 if (base_reg
!= new_base_reg
)
2430 if (REG_P (new_base_reg
))
2432 *ad
->base_reg_loc
= new_base_reg
;
2435 else if (GET_CODE (new_base_reg
) == PLUS
2436 && REG_P (XEXP (new_base_reg
, 0))
2437 && CONST_INT_P (XEXP (new_base_reg
, 1)))
2439 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2440 *ad
->base_reg_loc
= XEXP (new_base_reg
, 0);
2443 if (ad
->base_reg_loc2
!= NULL
)
2444 *ad
->base_reg_loc2
= *ad
->base_reg_loc
;
2447 if (ad
->index_loc
!= NULL
&& GET_CODE (*ad
->index_loc
) == MULT
)
2449 lra_assert (CONST_INT_P (XEXP (*ad
->index_loc
, 1)));
2450 scale
= INTVAL (XEXP (*ad
->index_loc
, 1));
2452 if (index_reg
!= new_index_reg
)
2454 if (REG_P (new_index_reg
))
2456 *ad
->index_reg_loc
= new_index_reg
;
2459 else if (GET_CODE (new_index_reg
) == PLUS
2460 && REG_P (XEXP (new_index_reg
, 0))
2461 && CONST_INT_P (XEXP (new_index_reg
, 1)))
2463 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2464 *ad
->index_reg_loc
= XEXP (new_index_reg
, 0);
2470 if (ad
->disp_loc
!= NULL
)
2471 *ad
->disp_loc
= plus_constant (Pmode
, *ad
->disp_loc
, disp
);
2474 *addr_loc
= gen_rtx_PLUS (Pmode
, *addr_loc
, GEN_INT (disp
));
2475 extract_address_regs (mode
, as
, addr_loc
, code
, ad
);
2479 if (lra_dump_file
!= NULL
)
2482 fprintf (lra_dump_file
, " -- no change\n");
2485 fprintf (lra_dump_file
, " on equiv ");
2486 print_value_slim (lra_dump_file
, *addr_loc
, 1);
2487 fprintf (lra_dump_file
, "\n");
2493 /* Major function to make reloads for address in operand NOP. Add to
2494 reloads to the list *BEFORE and *AFTER. We might need to add
2495 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2496 address. Return true for any RTL change. */
2498 process_address (int nop
, rtx
*before
, rtx
*after
)
2501 enum machine_mode mode
;
2502 rtx new_reg
, *addr_loc
, saved_index_reg
, saved_base_reg
;
2505 rtx op
= *curr_id
->operand_loc
[nop
];
2506 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2510 if (constraint
[0] == 'p'
2511 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2514 addr_loc
= curr_id
->operand_loc
[nop
];
2515 as
= ADDR_SPACE_GENERIC
;
2518 else if (MEM_P (op
))
2520 mode
= GET_MODE (op
);
2521 addr_loc
= &XEXP (op
, 0);
2522 as
= MEM_ADDR_SPACE (op
);
2525 else if (GET_CODE (op
) == SUBREG
2526 && MEM_P (SUBREG_REG (op
)))
2528 mode
= GET_MODE (SUBREG_REG (op
));
2529 addr_loc
= &XEXP (SUBREG_REG (op
), 0);
2530 as
= MEM_ADDR_SPACE (SUBREG_REG (op
));
2535 if (GET_CODE (*addr_loc
) == AND
)
2536 addr_loc
= &XEXP (*addr_loc
, 0);
2537 extract_address_regs (mode
, as
, addr_loc
, code
, &ad
);
2538 change_p
= equiv_address_substitution (&ad
, addr_loc
, mode
, as
, code
);
2539 if (ad
.base_reg_loc
!= NULL
2540 && (process_addr_reg
2541 (ad
.base_reg_loc
, before
,
2542 (ad
.base_modify_p
&& REG_P (*ad
.base_reg_loc
)
2543 && find_regno_note (curr_insn
, REG_DEAD
,
2544 REGNO (*ad
.base_reg_loc
)) == NULL_RTX
2546 base_reg_class (mode
, as
, ad
.base_outer_code
, ad
.index_code
))))
2549 if (ad
.base_reg_loc2
!= NULL
)
2550 *ad
.base_reg_loc2
= *ad
.base_reg_loc
;
2552 if (ad
.index_reg_loc
!= NULL
2553 && process_addr_reg (ad
.index_reg_loc
, before
, NULL
, INDEX_REG_CLASS
))
2556 /* The address was valid before LRA. We only change its form if the
2557 address has a displacement, so if it has no displacement it must
2559 if (ad
.disp_loc
== NULL
)
2562 /* See whether the address is still valid. Some ports do not check
2563 displacements for eliminable registers, so we replace them
2564 temporarily with the elimination target. */
2565 saved_base_reg
= saved_index_reg
= NULL_RTX
;
2566 if (ad
.base_reg_loc
!= NULL
)
2568 saved_base_reg
= *ad
.base_reg_loc
;
2569 lra_eliminate_reg_if_possible (ad
.base_reg_loc
);
2570 if (ad
.base_reg_loc2
!= NULL
)
2571 *ad
.base_reg_loc2
= *ad
.base_reg_loc
;
2573 if (ad
.index_reg_loc
!= NULL
)
2575 saved_index_reg
= *ad
.index_reg_loc
;
2576 lra_eliminate_reg_if_possible (ad
.index_reg_loc
);
2578 /* Some ports do not check displacements for virtual registers -- so
2579 we substitute them temporarily by real registers. */
2580 ok_p
= valid_address_p (mode
, *addr_loc
, as
);
2581 if (saved_base_reg
!= NULL_RTX
)
2583 *ad
.base_reg_loc
= saved_base_reg
;
2584 if (ad
.base_reg_loc2
!= NULL
)
2585 *ad
.base_reg_loc2
= saved_base_reg
;
2587 if (saved_index_reg
!= NULL_RTX
)
2588 *ad
.index_reg_loc
= saved_index_reg
;
2593 /* Addresses were legitimate before LRA. So if the address has
2594 two registers than it can have two of them. We should also
2595 not worry about scale for the same reason. */
2596 push_to_sequence (*before
);
2597 if (ad
.base_reg_loc
== NULL
)
2599 if (ad
.index_reg_loc
== NULL
)
2602 enum reg_class cl
= base_reg_class (mode
, as
, SCRATCH
, SCRATCH
);
2604 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2608 rtx last
= get_last_insn ();
2610 /* disp => lo_sum (new_base, disp) */
2611 insn
= emit_insn (gen_rtx_SET
2613 gen_rtx_HIGH (Pmode
, copy_rtx (*ad
.disp_loc
))));
2614 code
= recog_memoized (insn
);
2617 rtx save
= *ad
.disp_loc
;
2619 *ad
.disp_loc
= gen_rtx_LO_SUM (Pmode
, new_reg
, *ad
.disp_loc
);
2620 if (! valid_address_p (mode
, *ad
.disp_loc
, as
))
2622 *ad
.disp_loc
= save
;
2627 delete_insns_since (last
);
2632 /* disp => new_base */
2633 lra_emit_move (new_reg
, *ad
.disp_loc
);
2634 *ad
.disp_loc
= new_reg
;
2639 /* index * scale + disp => new base + index * scale */
2640 enum reg_class cl
= base_reg_class (mode
, as
, SCRATCH
, SCRATCH
);
2642 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2643 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2644 lra_assert (GET_CODE (*addr_loc
) == PLUS
);
2645 lra_emit_move (new_reg
, *ad
.disp_loc
);
2646 if (CONSTANT_P (XEXP (*addr_loc
, 1)))
2647 XEXP (*addr_loc
, 1) = XEXP (*addr_loc
, 0);
2648 XEXP (*addr_loc
, 0) = new_reg
;
2651 else if (ad
.index_reg_loc
== NULL
)
2653 /* base + disp => new base */
2654 /* Another option would be to reload the displacement into an
2655 index register. However, postreload has code to optimize
2656 address reloads that have the same base and different
2657 displacements, so reloading into an index register would
2658 not necessarily be a win. */
2659 new_reg
= base_plus_disp_to_reg (mode
, as
, &ad
);
2660 *addr_loc
= new_reg
;
2664 /* base + scale * index + disp => new base + scale * index */
2665 new_reg
= base_plus_disp_to_reg (mode
, as
, &ad
);
2666 *addr_loc
= gen_rtx_PLUS (Pmode
, new_reg
, *ad
.index_loc
);
2668 *before
= get_insns ();
2673 /* Emit insns to reload VALUE into a new register. VALUE is an
2674 auto-increment or auto-decrement RTX whose operand is a register or
2675 memory location; so reloading involves incrementing that location.
2676 IN is either identical to VALUE, or some cheaper place to reload
2677 value being incremented/decremented from.
2679 INC_AMOUNT is the number to increment or decrement by (always
2680 positive and ignored for POST_MODIFY/PRE_MODIFY).
2682 Return pseudo containing the result. */
2684 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2686 /* REG or MEM to be copied and incremented. */
2687 rtx incloc
= XEXP (value
, 0);
2688 /* Nonzero if increment after copying. */
2689 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2690 || GET_CODE (value
) == POST_MODIFY
);
2695 rtx real_in
= in
== value
? incloc
: in
;
2699 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2701 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2702 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2703 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2704 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2705 inc
= XEXP (XEXP (value
, 1), 1);
2709 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2710 inc_amount
= -inc_amount
;
2712 inc
= GEN_INT (inc_amount
);
2715 if (! post
&& REG_P (incloc
))
2718 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2721 if (real_in
!= result
)
2723 /* First copy the location to the result register. */
2724 lra_assert (REG_P (result
));
2725 emit_insn (gen_move_insn (result
, real_in
));
2728 /* We suppose that there are insns to add/sub with the constant
2729 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2730 old reload worked with this assumption. If the assumption
2731 becomes wrong, we should use approach in function
2732 base_plus_disp_to_reg. */
2735 /* See if we can directly increment INCLOC. */
2736 last
= get_last_insn ();
2737 add_insn
= emit_insn (plus_p
2738 ? gen_add2_insn (incloc
, inc
)
2739 : gen_sub2_insn (incloc
, inc
));
2741 code
= recog_memoized (add_insn
);
2744 if (! post
&& result
!= incloc
)
2745 emit_insn (gen_move_insn (result
, incloc
));
2748 delete_insns_since (last
);
2751 /* If couldn't do the increment directly, must increment in RESULT.
2752 The way we do this depends on whether this is pre- or
2753 post-increment. For pre-increment, copy INCLOC to the reload
2754 register, increment it there, then save back. */
2757 if (real_in
!= result
)
2758 emit_insn (gen_move_insn (result
, real_in
));
2760 emit_insn (gen_add2_insn (result
, inc
));
2762 emit_insn (gen_sub2_insn (result
, inc
));
2763 if (result
!= incloc
)
2764 emit_insn (gen_move_insn (incloc
, result
));
2770 Because this might be a jump insn or a compare, and because
2771 RESULT may not be available after the insn in an input
2772 reload, we must do the incrementing before the insn being
2775 We have already copied IN to RESULT. Increment the copy in
2776 RESULT, save that back, then decrement RESULT so it has
2777 the original value. */
2779 emit_insn (gen_add2_insn (result
, inc
));
2781 emit_insn (gen_sub2_insn (result
, inc
));
2782 emit_insn (gen_move_insn (incloc
, result
));
2783 /* Restore non-modified value for the result. We prefer this
2784 way because it does not require an additional hard
2788 if (CONST_INT_P (inc
))
2789 emit_insn (gen_add2_insn (result
, GEN_INT (-INTVAL (inc
))));
2791 emit_insn (gen_sub2_insn (result
, inc
));
2794 emit_insn (gen_add2_insn (result
, inc
));
2799 /* Swap operands NOP and NOP + 1. */
2801 swap_operands (int nop
)
2803 enum machine_mode mode
= curr_operand_mode
[nop
];
2804 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2805 curr_operand_mode
[nop
+ 1] = mode
;
2806 rtx x
= *curr_id
->operand_loc
[nop
];
2807 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2808 *curr_id
->operand_loc
[nop
+ 1] = x
;
2809 /* Swap the duplicates too. */
2810 lra_update_dup (curr_id
, nop
);
2811 lra_update_dup (curr_id
, nop
+ 1);
2814 /* Main entry point of the constraint code: search the body of the
2815 current insn to choose the best alternative. It is mimicking insn
2816 alternative cost calculation model of former reload pass. That is
2817 because machine descriptions were written to use this model. This
2818 model can be changed in future. Make commutative operand exchange
2821 Return true if some RTL changes happened during function call. */
2823 curr_insn_transform (void)
2829 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2832 /* Flag that the insn has been changed through a transformation. */
2835 #ifdef SECONDARY_MEMORY_NEEDED
2838 int max_regno_before
;
2839 int reused_alternative_num
;
2841 no_input_reloads_p
= no_output_reloads_p
= false;
2842 goal_alt_number
= -1;
2844 if (check_and_process_move (&change_p
, &sec_mem_p
))
2847 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
2848 reloads; neither are insns that SET cc0. Insns that use CC0 are
2849 not allowed to have any input reloads. */
2850 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
2851 no_output_reloads_p
= true;
2854 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
2855 no_input_reloads_p
= true;
2856 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
2857 no_output_reloads_p
= true;
2860 n_operands
= curr_static_id
->n_operands
;
2861 n_alternatives
= curr_static_id
->n_alternatives
;
2863 /* Just return "no reloads" if insn has no operands with
2865 if (n_operands
== 0 || n_alternatives
== 0)
2868 max_regno_before
= max_reg_num ();
2870 for (i
= 0; i
< n_operands
; i
++)
2872 goal_alt_matched
[i
][0] = -1;
2873 goal_alt_matches
[i
] = -1;
2876 commutative
= curr_static_id
->commutative
;
2878 /* Now see what we need for pseudos that didn't get hard regs or got
2879 the wrong kind of hard reg. For this, we must consider all the
2880 operands together against the register constraints. */
2882 best_losers
= best_overall
= MAX_RECOG_OPERANDS
* 2 + MAX_OVERALL_COST_BOUND
;
2883 best_small_class_operands_num
= best_reload_sum
= 0;
2885 curr_swapped
= false;
2886 goal_alt_swapped
= false;
2888 /* Make equivalence substitution and memory subreg elimination
2889 before address processing because an address legitimacy can
2890 depend on memory mode. */
2891 for (i
= 0; i
< n_operands
; i
++)
2893 rtx op
= *curr_id
->operand_loc
[i
];
2894 rtx subst
, old
= op
;
2895 bool op_change_p
= false;
2897 if (GET_CODE (old
) == SUBREG
)
2898 old
= SUBREG_REG (old
);
2899 subst
= get_equiv_substitution (old
);
2902 subst
= copy_rtx (subst
);
2903 lra_assert (REG_P (old
));
2904 if (GET_CODE (op
) == SUBREG
)
2905 SUBREG_REG (op
) = subst
;
2907 *curr_id
->operand_loc
[i
] = subst
;
2908 if (lra_dump_file
!= NULL
)
2910 fprintf (lra_dump_file
,
2911 "Changing pseudo %d in operand %i of insn %u on equiv ",
2912 REGNO (old
), i
, INSN_UID (curr_insn
));
2913 print_value_slim (lra_dump_file
, subst
, 1);
2914 fprintf (lra_dump_file
, "\n");
2916 op_change_p
= change_p
= true;
2918 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
2921 lra_update_dup (curr_id
, i
);
2925 /* Reload address registers and displacements. We do it before
2926 finding an alternative because of memory constraints. */
2927 before
= after
= NULL_RTX
;
2928 for (i
= 0; i
< n_operands
; i
++)
2929 if (! curr_static_id
->operand
[i
].is_operator
2930 && process_address (i
, &before
, &after
))
2933 lra_update_dup (curr_id
, i
);
2937 /* If we've changed the instruction then any alternative that
2938 we chose previously may no longer be valid. */
2939 lra_set_used_insn_alternative (curr_insn
, -1);
2943 reused_alternative_num
= curr_id
->used_insn_alternative
;
2944 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
2945 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
2946 reused_alternative_num
, INSN_UID (curr_insn
));
2948 if (process_alt_operands (reused_alternative_num
))
2951 /* If insn is commutative (it's safe to exchange a certain pair of
2952 operands) then we need to try each alternative twice, the second
2953 time matching those two operands as if we had exchanged them. To
2954 do this, really exchange them in operands.
2956 If we have just tried the alternatives the second time, return
2957 operands to normal and drop through. */
2959 if (reused_alternative_num
< 0 && commutative
>= 0)
2961 curr_swapped
= !curr_swapped
;
2964 swap_operands (commutative
);
2968 swap_operands (commutative
);
2971 /* The operands don't meet the constraints. goal_alt describes the
2972 alternative that we could reach by reloading the fewest operands.
2973 Reload so as to fit it. */
2975 if (! alt_p
&& ! sec_mem_p
)
2977 /* No alternative works with reloads?? */
2978 if (INSN_CODE (curr_insn
) >= 0)
2979 fatal_insn ("unable to generate reloads for:", curr_insn
);
2980 error_for_asm (curr_insn
,
2981 "inconsistent operand constraints in an %<asm%>");
2982 /* Avoid further trouble with this insn. */
2983 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
2984 lra_invalidate_insn_data (curr_insn
);
2988 /* If the best alternative is with operands 1 and 2 swapped, swap
2989 them. Update the operand numbers of any reloads already
2992 if (goal_alt_swapped
)
2994 if (lra_dump_file
!= NULL
)
2995 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
2996 INSN_UID (curr_insn
));
2998 /* Swap the duplicates too. */
2999 swap_operands (commutative
);
3003 #ifdef SECONDARY_MEMORY_NEEDED
3004 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3005 too conservatively. So we use the secondary memory only if there
3006 is no any alternative without reloads. */
3007 use_sec_mem_p
= false;
3009 use_sec_mem_p
= true;
3012 for (i
= 0; i
< n_operands
; i
++)
3013 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3015 use_sec_mem_p
= i
< n_operands
;
3020 rtx new_reg
, set
, src
, dest
;
3021 enum machine_mode sec_mode
;
3023 lra_assert (sec_mem_p
);
3024 set
= single_set (curr_insn
);
3025 lra_assert (set
!= NULL_RTX
&& ! side_effects_p (set
));
3026 dest
= SET_DEST (set
);
3027 src
= SET_SRC (set
);
3028 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3029 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
));
3031 sec_mode
= GET_MODE (src
);
3033 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3034 NO_REGS
, "secondary");
3035 /* If the mode is changed, it should be wider. */
3036 lra_assert (GET_MODE_SIZE (GET_MODE (new_reg
))
3037 >= GET_MODE_SIZE (GET_MODE (src
)));
3038 after
= emit_spill_move (false, new_reg
, dest
);
3039 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3040 "Inserting the sec. move");
3041 before
= emit_spill_move (true, new_reg
, src
);
3042 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3043 lra_set_insn_deleted (curr_insn
);
3048 lra_assert (goal_alt_number
>= 0);
3049 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3051 if (lra_dump_file
!= NULL
)
3055 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3056 goal_alt_number
, INSN_UID (curr_insn
));
3057 for (i
= 0; i
< n_operands
; i
++)
3059 p
= (curr_static_id
->operand_alternative
3060 [goal_alt_number
* n_operands
+ i
].constraint
);
3063 fprintf (lra_dump_file
, " (%d) ", i
);
3064 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3065 fputc (*p
, lra_dump_file
);
3067 fprintf (lra_dump_file
, "\n");
3070 /* Right now, for any pair of operands I and J that are required to
3071 match, with J < I, goal_alt_matches[I] is J. Add I to
3072 goal_alt_matched[J]. */
3074 for (i
= 0; i
< n_operands
; i
++)
3075 if ((j
= goal_alt_matches
[i
]) >= 0)
3077 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3079 /* We allow matching one output operand and several input
3082 || (curr_static_id
->operand
[j
].type
== OP_OUT
3083 && curr_static_id
->operand
[i
].type
== OP_IN
3084 && (curr_static_id
->operand
3085 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3086 goal_alt_matched
[j
][k
] = i
;
3087 goal_alt_matched
[j
][k
+ 1] = -1;
3090 for (i
= 0; i
< n_operands
; i
++)
3091 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3093 /* Any constants that aren't allowed and can't be reloaded into
3094 registers are here changed into memory references. */
3095 for (i
= 0; i
< n_operands
; i
++)
3096 if (goal_alt_win
[i
])
3099 enum reg_class new_class
;
3100 rtx reg
= *curr_id
->operand_loc
[i
];
3102 if (GET_CODE (reg
) == SUBREG
)
3103 reg
= SUBREG_REG (reg
);
3105 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3107 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3109 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3112 change_class (regno
, new_class
, " Change", true);
3118 const char *constraint
;
3120 rtx op
= *curr_id
->operand_loc
[i
];
3121 rtx subreg
= NULL_RTX
;
3122 enum machine_mode mode
= curr_operand_mode
[i
];
3124 if (GET_CODE (op
) == SUBREG
)
3127 op
= SUBREG_REG (op
);
3128 mode
= GET_MODE (op
);
3131 if (CONST_POOL_OK_P (mode
, op
)
3132 && ((targetm
.preferred_reload_class
3133 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3134 || no_input_reloads_p
))
3136 rtx tem
= force_const_mem (mode
, op
);
3139 if (subreg
!= NULL_RTX
)
3140 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3142 *curr_id
->operand_loc
[i
] = tem
;
3143 lra_update_dup (curr_id
, i
);
3144 process_address (i
, &before
, &after
);
3146 /* If the alternative accepts constant pool refs directly
3147 there will be no reload needed at all. */
3148 if (subreg
!= NULL_RTX
)
3150 /* Skip alternatives before the one requested. */
3151 constraint
= (curr_static_id
->operand_alternative
3152 [goal_alt_number
* n_operands
+ i
].constraint
);
3154 (c
= *constraint
) && c
!= ',' && c
!= '#';
3155 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3157 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3159 #ifdef EXTRA_CONSTRAINT_STR
3160 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3161 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3165 if (c
== '\0' || c
== ',' || c
== '#')
3168 goal_alt_win
[i
] = true;
3172 for (i
= 0; i
< n_operands
; i
++)
3175 rtx op
= *curr_id
->operand_loc
[i
];
3177 if (goal_alt_win
[i
])
3179 if (goal_alt
[i
] == NO_REGS
3181 /* When we assign NO_REGS it means that we will not
3182 assign a hard register to the scratch pseudo by
3183 assigment pass and the scratch pseudo will be
3184 spilled. Spilled scratch pseudos are transformed
3185 back to scratches at the LRA end. */
3186 && lra_former_scratch_operand_p (curr_insn
, i
))
3187 change_class (REGNO (op
), NO_REGS
, " Change", true);
3191 /* Operands that match previous ones have already been handled. */
3192 if (goal_alt_matches
[i
] >= 0)
3195 /* We should not have an operand with a non-offsettable address
3196 appearing where an offsettable address will do. It also may
3197 be a case when the address should be special in other words
3198 not a general one (e.g. it needs no index reg). */
3199 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3201 enum reg_class rclass
;
3202 rtx
*loc
= &XEXP (op
, 0);
3203 enum rtx_code code
= GET_CODE (*loc
);
3205 push_to_sequence (before
);
3206 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3208 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3209 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3210 /* This value does not matter for MODIFY. */
3211 GET_MODE_SIZE (GET_MODE (op
)));
3212 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3213 "offsetable address", &new_reg
))
3214 lra_emit_move (new_reg
, *loc
);
3215 before
= get_insns ();
3218 lra_update_dup (curr_id
, i
);
3220 else if (goal_alt_matched
[i
][0] == -1)
3222 enum machine_mode mode
;
3224 int hard_regno
, byte
;
3225 enum op_type type
= curr_static_id
->operand
[i
].type
;
3227 loc
= curr_id
->operand_loc
[i
];
3228 mode
= curr_operand_mode
[i
];
3229 if (GET_CODE (*loc
) == SUBREG
)
3231 reg
= SUBREG_REG (*loc
);
3232 byte
= SUBREG_BYTE (*loc
);
3234 /* Strict_low_part requires reload the register not
3235 the sub-register. */
3236 && (curr_static_id
->operand
[i
].strict_low
3237 || (GET_MODE_SIZE (mode
)
3238 <= GET_MODE_SIZE (GET_MODE (reg
))
3240 = get_try_hard_regno (REGNO (reg
))) >= 0
3241 && (simplify_subreg_regno
3243 GET_MODE (reg
), byte
, mode
) < 0)
3244 && (goal_alt
[i
] == NO_REGS
3245 || (simplify_subreg_regno
3246 (ira_class_hard_regs
[goal_alt
[i
]][0],
3247 GET_MODE (reg
), byte
, mode
) >= 0)))))
3249 loc
= &SUBREG_REG (*loc
);
3250 mode
= GET_MODE (*loc
);
3254 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3257 push_to_sequence (before
);
3258 lra_emit_move (new_reg
, old
);
3259 before
= get_insns ();
3264 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3267 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3269 after
= get_insns ();
3273 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3274 if (goal_alt_dont_inherit_ops
[j
] == i
)
3276 lra_set_regno_unique_value (REGNO (new_reg
));
3279 lra_update_dup (curr_id
, i
);
3281 else if (curr_static_id
->operand
[i
].type
== OP_IN
3282 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3289 match_reload (goal_alt_matched
[i
][0], arr
,
3290 goal_alt
[i
], &before
, &after
);
3292 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3293 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3295 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3297 /* We must generate code in any case when function
3298 process_alt_operands decides that it is possible. */
3301 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3302 || max_regno_before
!= max_reg_num ())
3306 lra_update_operator_dups (curr_id
);
3307 /* Something changes -- process the insn. */
3308 lra_update_insn_regno_info (curr_insn
);
3310 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3314 /* Return true if X is in LIST. */
3316 in_list_p (rtx x
, rtx list
)
3318 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3319 if (XEXP (list
, 0) == x
)
3324 /* Return true if X contains an allocatable hard register (if
3325 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3327 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3333 code
= GET_CODE (x
);
3336 int regno
= REGNO (x
);
3337 HARD_REG_SET alloc_regs
;
3341 if (regno
>= FIRST_PSEUDO_REGISTER
)
3342 regno
= lra_get_regno_hard_regno (regno
);
3345 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3346 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3350 if (regno
< FIRST_PSEUDO_REGISTER
)
3354 return lra_get_regno_hard_regno (regno
) < 0;
3357 fmt
= GET_RTX_FORMAT (code
);
3358 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3362 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3365 else if (fmt
[i
] == 'E')
3367 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3368 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3375 /* Process all regs in debug location *LOC and change them on
3376 equivalent substitution. Return true if any change was done. */
3378 debug_loc_equivalence_change_p (rtx
*loc
)
3380 rtx subst
, reg
, x
= *loc
;
3381 bool result
= false;
3382 enum rtx_code code
= GET_CODE (x
);
3388 reg
= SUBREG_REG (x
);
3389 if ((subst
= get_equiv_substitution (reg
)) != reg
3390 && GET_MODE (subst
) == VOIDmode
)
3392 /* We cannot reload debug location. Simplify subreg here
3393 while we know the inner mode. */
3394 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3395 GET_MODE (reg
), SUBREG_BYTE (x
));
3399 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3405 /* Scan all the operand sub-expressions. */
3406 fmt
= GET_RTX_FORMAT (code
);
3407 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3410 result
= debug_loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3411 else if (fmt
[i
] == 'E')
3412 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3414 = debug_loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3419 /* Maximum allowed number of constraint pass iterations after the last
3420 spill pass. It is for preventing LRA cycling in a bug case. */
3421 #define MAX_CONSTRAINT_ITERATION_NUMBER 15
3423 /* Maximum number of generated reload insns per an insn. It is for
3424 preventing this pass cycling in a bug case. */
3425 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3427 /* The current iteration number of this LRA pass. */
3428 int lra_constraint_iter
;
3430 /* The current iteration number of this LRA pass after the last spill
3432 int lra_constraint_iter_after_spill
;
3434 /* True if we substituted equiv which needs checking register
3435 allocation correctness because the equivalent value contains
3436 allocatable hard registers or when we restore multi-register
3438 bool lra_risky_transformations_p
;
3440 /* Return true if REGNO is referenced in more than one block. */
3442 multi_block_pseudo_p (int regno
)
3444 basic_block bb
= NULL
;
3448 if (regno
< FIRST_PSEUDO_REGISTER
)
3451 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3453 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3454 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3459 /* Return true if X contains a pseudo dying in INSN. */
3461 dead_pseudo_p (rtx x
, rtx insn
)
3468 return (insn
!= NULL_RTX
3469 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3470 code
= GET_CODE (x
);
3471 fmt
= GET_RTX_FORMAT (code
);
3472 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3476 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3479 else if (fmt
[i
] == 'E')
3481 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3482 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3489 /* Return true if INSN contains a dying pseudo in INSN right hand
3492 insn_rhs_dead_pseudo_p (rtx insn
)
3494 rtx set
= single_set (insn
);
3496 gcc_assert (set
!= NULL
);
3497 return dead_pseudo_p (SET_SRC (set
), insn
);
3500 /* Return true if any init insn of REGNO contains a dying pseudo in
3501 insn right hand side. */
3503 init_insn_rhs_dead_pseudo_p (int regno
)
3505 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3510 return insn_rhs_dead_pseudo_p (insns
);
3511 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3512 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3517 /* Entry function of LRA constraint pass. Return true if the
3518 constraint pass did change the code. */
3520 lra_constraints (bool first_p
)
3523 int i
, hard_regno
, new_insns_num
;
3524 unsigned int min_len
, new_min_len
;
3525 rtx set
, x
, dest_reg
;
3526 basic_block last_bb
;
3528 lra_constraint_iter
++;
3529 if (lra_dump_file
!= NULL
)
3530 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3531 lra_constraint_iter
);
3532 lra_constraint_iter_after_spill
++;
3533 if (lra_constraint_iter_after_spill
> MAX_CONSTRAINT_ITERATION_NUMBER
)
3535 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3536 MAX_CONSTRAINT_ITERATION_NUMBER
);
3538 lra_risky_transformations_p
= false;
3539 new_insn_uid_start
= get_max_uid ();
3540 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3541 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3542 if (lra_reg_info
[i
].nrefs
!= 0)
3544 ira_reg_equiv
[i
].profitable_p
= true;
3545 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3547 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3549 for (j
= 0; j
< nregs
; j
++)
3550 df_set_regs_ever_live (hard_regno
+ j
, true);
3552 else if ((x
= get_equiv_substitution (regno_reg_rtx
[i
])) != NULL_RTX
)
3554 bool pseudo_p
= contains_reg_p (x
, false, false);
3557 /* We don't use DF for compilation speed sake. So it is
3558 problematic to update live info when we use an
3559 equivalence containing pseudos in more than one BB. */
3560 if ((pseudo_p
&& multi_block_pseudo_p (i
))
3561 /* If it is not a reverse equivalence, we check that a
3562 pseudo in rhs of the init insn is not dying in the
3563 insn. Otherwise, the live info at the beginning of
3564 the corresponding BB might be wrong after we
3565 removed the insn. When the equiv can be a
3566 constant, the right hand side of the init insn can
3568 || (! ((insn
= ira_reg_equiv
[i
].init_insns
) != NULL_RTX
3570 && (set
= single_set (insn
)) != NULL_RTX
3571 && REG_P (SET_DEST (set
))
3572 && (int) REGNO (SET_DEST (set
)) == i
)
3573 && init_insn_rhs_dead_pseudo_p (i
)))
3574 ira_reg_equiv
[i
].defined_p
= false;
3575 else if (! first_p
&& pseudo_p
)
3576 /* After RTL transformation, we can not guarantee that
3577 pseudo in the substitution was not reloaded which
3578 might make equivalence invalid. For example, in
3585 the memory address register was reloaded before the
3587 ira_reg_equiv
[i
].defined_p
= false;
3588 if (contains_reg_p (x
, false, true))
3589 ira_reg_equiv
[i
].profitable_p
= false;
3592 lra_eliminate (false);
3593 min_len
= lra_insn_stack_length ();
3597 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3599 curr_insn
= lra_pop_insn ();
3601 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3602 if (curr_bb
!= last_bb
)
3605 bb_reload_num
= lra_curr_reload_num
;
3607 if (min_len
> new_min_len
)
3609 min_len
= new_min_len
;
3612 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3614 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3615 MAX_RELOAD_INSNS_NUMBER
);
3617 if (DEBUG_INSN_P (curr_insn
))
3619 /* We need to check equivalence in debug insn and change
3620 pseudo to the equivalent value if necessary. */
3621 curr_id
= lra_get_insn_recog_data (curr_insn
);
3622 if (debug_loc_equivalence_change_p (curr_id
->operand_loc
[0]))
3625 else if (INSN_P (curr_insn
))
3627 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3629 dest_reg
= SET_DEST (set
);
3630 /* The equivalence pseudo could be set up as SUBREG in a
3631 case when it is a call restore insn in a mode
3632 different from the pseudo mode. */
3633 if (GET_CODE (dest_reg
) == SUBREG
)
3634 dest_reg
= SUBREG_REG (dest_reg
);
3635 if ((REG_P (dest_reg
)
3636 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3637 /* Remove insns which set up a pseudo whose value
3638 can not be changed. Such insns might be not in
3639 init_insns because we don't update equiv data
3640 during insn transformations.
3642 As an example, let suppose that a pseudo got
3643 hard register and on the 1st pass was not
3644 changed to equivalent constant. We generate an
3645 additional insn setting up the pseudo because of
3646 secondary memory movement. Then the pseudo is
3647 spilled and we use the equiv constant. In this
3648 case we should remove the additional insn and
3649 this insn is not init_insns list. */
3650 && (! MEM_P (x
) || MEM_READONLY_P (x
)
3651 || in_list_p (curr_insn
,
3653 [REGNO (dest_reg
)].init_insns
)))
3654 || (((x
= get_equiv_substitution (SET_SRC (set
)))
3656 && in_list_p (curr_insn
,
3658 [REGNO (SET_SRC (set
))].init_insns
)))
3660 /* This is equiv init insn of pseudo which did not get a
3661 hard register -- remove the insn. */
3662 if (lra_dump_file
!= NULL
)
3664 fprintf (lra_dump_file
,
3665 " Removing equiv init insn %i (freq=%d)\n",
3666 INSN_UID (curr_insn
),
3667 BLOCK_FOR_INSN (curr_insn
)->frequency
);
3668 debug_rtl_slim (lra_dump_file
,
3669 curr_insn
, curr_insn
, -1, 0);
3671 if (contains_reg_p (x
, true, false))
3672 lra_risky_transformations_p
= true;
3673 lra_set_insn_deleted (curr_insn
);
3677 curr_id
= lra_get_insn_recog_data (curr_insn
);
3678 curr_static_id
= curr_id
->insn_static_data
;
3679 init_curr_insn_input_reloads ();
3680 init_curr_operand_mode ();
3681 if (curr_insn_transform ())
3685 /* If we used a new hard regno, changed_p should be true because the
3686 hard reg is assigned to a new pseudo. */
3687 #ifdef ENABLE_CHECKING
3690 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3691 if (lra_reg_info
[i
].nrefs
!= 0
3692 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3694 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3696 for (j
= 0; j
< nregs
; j
++)
3697 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
3704 /* Initiate the LRA constraint pass. It is done once per
3707 lra_constraints_init (void)
3711 /* Finalize the LRA constraint pass. It is done once per
3714 lra_constraints_finish (void)
3720 /* This page contains code to do inheritance/split
3723 /* Number of reloads passed so far in current EBB. */
3724 static int reloads_num
;
3726 /* Number of calls passed so far in current EBB. */
3727 static int calls_num
;
3729 /* Current reload pseudo check for validity of elements in
3731 static int curr_usage_insns_check
;
3733 /* Info about last usage of registers in EBB to do inheritance/split
3734 transformation. Inheritance transformation is done from a spilled
3735 pseudo and split transformations from a hard register or a pseudo
3736 assigned to a hard register. */
3739 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
3740 value INSNS is valid. The insns is chain of optional debug insns
3741 and a finishing non-debug insn using the corresponding reg. */
3743 /* Value of global reloads_num at the last insn in INSNS. */
3745 /* Value of global reloads_nums at the last insn in INSNS. */
3747 /* It can be true only for splitting. And it means that the restore
3748 insn should be put after insn given by the following member. */
3750 /* Next insns in the current EBB which use the original reg and the
3751 original reg value is not changed between the current insn and
3752 the next insns. In order words, e.g. for inheritance, if we need
3753 to use the original reg value again in the next insns we can try
3754 to use the value in a hard register from a reload insn of the
3759 /* Map: regno -> corresponding pseudo usage insns. */
3760 static struct usage_insns
*usage_insns
;
3763 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
3765 usage_insns
[regno
].check
= curr_usage_insns_check
;
3766 usage_insns
[regno
].insns
= insn
;
3767 usage_insns
[regno
].reloads_num
= reloads_num
;
3768 usage_insns
[regno
].calls_num
= calls_num
;
3769 usage_insns
[regno
].after_p
= after_p
;
3772 /* The function is used to form list REGNO usages which consists of
3773 optional debug insns finished by a non-debug insn using REGNO.
3774 RELOADS_NUM is current number of reload insns processed so far. */
3776 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
3778 rtx next_usage_insns
;
3780 if (usage_insns
[regno
].check
== curr_usage_insns_check
3781 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
3782 && DEBUG_INSN_P (insn
))
3784 /* Check that we did not add the debug insn yet. */
3785 if (next_usage_insns
!= insn
3786 && (GET_CODE (next_usage_insns
) != INSN_LIST
3787 || XEXP (next_usage_insns
, 0) != insn
))
3788 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
3791 else if (NONDEBUG_INSN_P (insn
))
3792 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
3794 usage_insns
[regno
].check
= 0;
3797 /* Replace all references to register OLD_REGNO in *LOC with pseudo
3798 register NEW_REG. Return true if any change was made. */
3800 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
3803 bool result
= false;
3811 code
= GET_CODE (x
);
3812 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
3814 enum machine_mode mode
= GET_MODE (*loc
);
3815 enum machine_mode inner_mode
= GET_MODE (new_reg
);
3817 if (mode
!= inner_mode
)
3819 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
3820 || ! SCALAR_INT_MODE_P (inner_mode
))
3821 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
3823 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
3829 /* Scan all the operand sub-expressions. */
3830 fmt
= GET_RTX_FORMAT (code
);
3831 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3835 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
3838 else if (fmt
[i
] == 'E')
3840 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3841 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
3848 /* Registers involved in inheritance/split in the current EBB
3849 (inheritance/split pseudos and original registers). */
3850 static bitmap_head check_only_regs
;
3852 /* Do inheritance transformations for insn INSN, which defines (if
3853 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
3854 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
3855 form as the "insns" field of usage_insns. Return true if we
3856 succeed in such transformation.
3858 The transformations look like:
3861 ... p <- i (new insn)
3863 <- ... p ... <- ... i ...
3865 ... i <- p (new insn)
3866 <- ... p ... <- ... i ...
3868 <- ... p ... <- ... i ...
3869 where p is a spilled original pseudo and i is a new inheritance pseudo.
3872 The inheritance pseudo has the smallest class of two classes CL and
3873 class of ORIGINAL REGNO. */
3875 inherit_reload_reg (bool def_p
, int original_regno
,
3876 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
3878 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
3879 rtx original_reg
= regno_reg_rtx
[original_regno
];
3880 rtx new_reg
, new_insns
, usage_insn
;
3882 lra_assert (! usage_insns
[original_regno
].after_p
);
3883 if (lra_dump_file
!= NULL
)
3884 fprintf (lra_dump_file
,
3885 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
3886 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
3888 if (lra_dump_file
!= NULL
)
3890 fprintf (lra_dump_file
,
3891 " Rejecting inheritance for %d "
3892 "because of disjoint classes %s and %s\n",
3893 original_regno
, reg_class_names
[cl
],
3894 reg_class_names
[rclass
]);
3895 fprintf (lra_dump_file
,
3896 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3900 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
3901 /* We don't use a subset of two classes because it can be
3902 NO_REGS. This transformation is still profitable in most
3903 cases even if the classes are not intersected as register
3904 move is probably cheaper than a memory load. */
3905 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
3907 if (lra_dump_file
!= NULL
)
3908 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
3909 reg_class_names
[cl
], reg_class_names
[rclass
]);
3913 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
3914 rclass
, "inheritance");
3917 emit_move_insn (original_reg
, new_reg
);
3919 emit_move_insn (new_reg
, original_reg
);
3920 new_insns
= get_insns ();
3922 if (NEXT_INSN (new_insns
) != NULL_RTX
)
3924 if (lra_dump_file
!= NULL
)
3926 fprintf (lra_dump_file
,
3927 " Rejecting inheritance %d->%d "
3928 "as it results in 2 or more insns:\n",
3929 original_regno
, REGNO (new_reg
));
3930 debug_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
3931 fprintf (lra_dump_file
,
3932 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3936 substitute_pseudo (&insn
, original_regno
, new_reg
);
3937 lra_update_insn_regno_info (insn
);
3939 /* We now have a new usage insn for original regno. */
3940 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
3941 if (lra_dump_file
!= NULL
)
3942 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
3943 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
3944 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
3945 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
3946 bitmap_set_bit (&check_only_regs
, original_regno
);
3947 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
3949 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
3950 "Add original<-inheritance");
3952 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
3953 "Add inheritance<-original");
3954 while (next_usage_insns
!= NULL_RTX
)
3956 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
3958 usage_insn
= next_usage_insns
;
3959 lra_assert (NONDEBUG_INSN_P (usage_insn
));
3960 next_usage_insns
= NULL
;
3964 usage_insn
= XEXP (next_usage_insns
, 0);
3965 lra_assert (DEBUG_INSN_P (usage_insn
));
3966 next_usage_insns
= XEXP (next_usage_insns
, 1);
3968 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
3969 lra_update_insn_regno_info (usage_insn
);
3970 if (lra_dump_file
!= NULL
)
3972 fprintf (lra_dump_file
,
3973 " Inheritance reuse change %d->%d (bb%d):\n",
3974 original_regno
, REGNO (new_reg
),
3975 BLOCK_FOR_INSN (usage_insn
)->index
);
3976 debug_rtl_slim (lra_dump_file
, usage_insn
, usage_insn
,
3980 if (lra_dump_file
!= NULL
)
3981 fprintf (lra_dump_file
,
3982 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3986 /* Return true if we need a caller save/restore for pseudo REGNO which
3987 was assigned to a hard register. */
3989 need_for_call_save_p (int regno
)
3991 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
3992 return (usage_insns
[regno
].calls_num
< calls_num
3993 && (overlaps_hard_reg_set_p
3995 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])));
3998 /* Global registers occuring in the current EBB. */
3999 static bitmap_head ebb_global_regs
;
4001 /* Return true if we need a split for hard register REGNO or pseudo
4002 REGNO which was assigned to a hard register.
4003 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4004 used for reloads since the EBB end. It is an approximation of the
4005 used hard registers in the split range. The exact value would
4006 require expensive calculations. If we were aggressive with
4007 splitting because of the approximation, the split pseudo will save
4008 the same hard register assignment and will be removed in the undo
4009 pass. We still need the approximation because too aggressive
4010 splitting would result in too inaccurate cost calculation in the
4011 assignment pass because of too many generated moves which will be
4012 probably removed in the undo pass. */
4014 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4016 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4018 lra_assert (hard_regno
>= 0);
4019 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4020 /* Don't split eliminable hard registers, otherwise we can
4021 split hard registers like hard frame pointer, which
4022 lives on BB start/end according to DF-infrastructure,
4023 when there is a pseudo assigned to the register and
4024 living in the same BB. */
4025 && (regno
>= FIRST_PSEUDO_REGISTER
4026 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4027 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4028 /* We need at least 2 reloads to make pseudo splitting
4029 profitable. We should provide hard regno splitting in
4030 any case to solve 1st insn scheduling problem when
4031 moving hard register definition up might result in
4032 impossibility to find hard register for reload pseudo of
4033 small register class. */
4034 && (usage_insns
[regno
].reloads_num
4035 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4036 && (regno
< FIRST_PSEUDO_REGISTER
4037 /* For short living pseudos, spilling + inheritance can
4038 be considered a substitution for splitting.
4039 Therefore we do not splitting for local pseudos. It
4040 decreases also aggressiveness of splitting. The
4041 minimal number of references is chosen taking into
4042 account that for 2 references splitting has no sense
4043 as we can just spill the pseudo. */
4044 || (regno
>= FIRST_PSEUDO_REGISTER
4045 && lra_reg_info
[regno
].nrefs
> 3
4046 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4047 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4050 /* Return class for the split pseudo created from original pseudo with
4051 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4052 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4053 results in no secondary memory movements. */
4054 static enum reg_class
4055 choose_split_class (enum reg_class allocno_class
,
4056 int hard_regno ATTRIBUTE_UNUSED
,
4057 enum machine_mode mode ATTRIBUTE_UNUSED
)
4059 #ifndef SECONDARY_MEMORY_NEEDED
4060 return allocno_class
;
4063 enum reg_class cl
, best_cl
= NO_REGS
;
4064 enum reg_class hard_reg_class
= REGNO_REG_CLASS (hard_regno
);
4066 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4067 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4068 return allocno_class
;
4070 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4072 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4073 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4074 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4075 && (best_cl
== NO_REGS
4076 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4082 /* Do split transformations for insn INSN, which defines or uses
4083 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4084 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4085 "insns" field of usage_insns.
4087 The transformations look like:
4090 ... s <- p (new insn -- save)
4092 ... p <- s (new insn -- restore)
4093 <- ... p ... <- ... p ...
4095 <- ... p ... <- ... p ...
4096 ... s <- p (new insn -- save)
4098 ... p <- s (new insn -- restore)
4099 <- ... p ... <- ... p ...
4101 where p is an original pseudo got a hard register or a hard
4102 register and s is a new split pseudo. The save is put before INSN
4103 if BEFORE_P is true. Return true if we succeed in such
4106 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4108 enum reg_class rclass
;
4111 rtx new_reg
, save
, restore
, usage_insn
;
4115 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4117 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4118 hard_regno
= original_regno
;
4119 call_save_p
= false;
4123 hard_regno
= reg_renumber
[original_regno
];
4124 rclass
= lra_get_allocno_class (original_regno
);
4125 original_reg
= regno_reg_rtx
[original_regno
];
4126 call_save_p
= need_for_call_save_p (original_regno
);
4128 original_reg
= regno_reg_rtx
[original_regno
];
4129 lra_assert (hard_regno
>= 0);
4130 if (lra_dump_file
!= NULL
)
4131 fprintf (lra_dump_file
,
4132 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4135 enum machine_mode sec_mode
;
4137 #ifdef SECONDARY_MEMORY_NEEDED_MODE
4138 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (original_reg
));
4140 sec_mode
= GET_MODE (original_reg
);
4142 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
4147 rclass
= choose_split_class (rclass
, hard_regno
,
4148 GET_MODE (original_reg
));
4149 if (rclass
== NO_REGS
)
4151 if (lra_dump_file
!= NULL
)
4153 fprintf (lra_dump_file
,
4154 " Rejecting split of %d(%s): "
4155 "no good reg class for %d(%s)\n",
4157 reg_class_names
[lra_get_allocno_class (original_regno
)],
4159 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4162 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4166 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4168 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4170 save
= emit_spill_move (true, new_reg
, original_reg
);
4171 if (NEXT_INSN (save
) != NULL_RTX
)
4173 lra_assert (! call_save_p
);
4174 if (lra_dump_file
!= NULL
)
4178 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4179 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4180 debug_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4181 fprintf (lra_dump_file
,
4182 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4186 restore
= emit_spill_move (false, new_reg
, original_reg
);
4187 if (NEXT_INSN (restore
) != NULL_RTX
)
4189 lra_assert (! call_save_p
);
4190 if (lra_dump_file
!= NULL
)
4192 fprintf (lra_dump_file
,
4193 " Rejecting split %d->%d "
4194 "resulting in > 2 %s restore insns:\n",
4195 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4196 debug_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4197 fprintf (lra_dump_file
,
4198 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4202 after_p
= usage_insns
[original_regno
].after_p
;
4203 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4204 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4205 bitmap_set_bit (&check_only_regs
, original_regno
);
4206 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4209 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4211 usage_insn
= next_usage_insns
;
4214 usage_insn
= XEXP (next_usage_insns
, 0);
4215 lra_assert (DEBUG_INSN_P (usage_insn
));
4216 next_usage_insns
= XEXP (next_usage_insns
, 1);
4217 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4218 lra_update_insn_regno_info (usage_insn
);
4219 if (lra_dump_file
!= NULL
)
4221 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4222 original_regno
, REGNO (new_reg
));
4223 debug_rtl_slim (lra_dump_file
, usage_insn
, usage_insn
,
4227 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4228 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4229 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4230 after_p
? restore
: NULL_RTX
,
4232 ? "Add reg<-save" : "Add reg<-split");
4233 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4234 before_p
? NULL_RTX
: save
,
4236 ? "Add save<-reg" : "Add split<-reg");
4237 if (lra_dump_file
!= NULL
)
4238 fprintf (lra_dump_file
,
4239 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4243 /* Recognize that we need a split transformation for insn INSN, which
4244 defines or uses REGNO in its insn biggest MODE (we use it only if
4245 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4246 hard registers which might be used for reloads since the EBB end.
4247 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4248 uid before starting INSN processing. Return true if we succeed in
4249 such transformation. */
4251 split_if_necessary (int regno
, enum machine_mode mode
,
4252 HARD_REG_SET potential_reload_hard_regs
,
4253 bool before_p
, rtx insn
, int max_uid
)
4257 rtx next_usage_insns
;
4259 if (regno
< FIRST_PSEUDO_REGISTER
)
4260 nregs
= hard_regno_nregs
[regno
][mode
];
4261 for (i
= 0; i
< nregs
; i
++)
4262 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4263 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4264 /* To avoid processing the register twice or more. */
4265 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4266 && INSN_UID (next_usage_insns
) < max_uid
)
4267 || (GET_CODE (next_usage_insns
) == INSN_LIST
4268 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4269 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4270 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4275 /* Check only registers living at the current program point in the
4277 static bitmap_head live_regs
;
4279 /* Update live info in EBB given by its HEAD and TAIL insns after
4280 inheritance/split transformation. The function removes dead moves
4283 update_ebb_live_info (rtx head
, rtx tail
)
4290 basic_block last_bb
, prev_bb
, curr_bb
;
4292 struct lra_insn_reg
*reg
;
4296 last_bb
= BLOCK_FOR_INSN (tail
);
4298 for (curr_insn
= tail
;
4299 curr_insn
!= PREV_INSN (head
);
4300 curr_insn
= prev_insn
)
4302 prev_insn
= PREV_INSN (curr_insn
);
4303 if (! INSN_P (curr_insn
))
4305 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4306 if (curr_bb
!= prev_bb
)
4308 if (prev_bb
!= NULL
)
4310 /* Update df_get_live_in (prev_bb): */
4311 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4312 if (bitmap_bit_p (&live_regs
, j
))
4313 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4315 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4317 if (curr_bb
!= last_bb
)
4319 /* Update df_get_live_out (curr_bb): */
4320 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4322 live_p
= bitmap_bit_p (&live_regs
, j
);
4324 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4325 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4331 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4333 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4337 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4339 if (DEBUG_INSN_P (curr_insn
))
4341 curr_id
= lra_get_insn_recog_data (curr_insn
);
4343 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4344 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4345 && bitmap_bit_p (&check_only_regs
, regno
)
4346 && ! bitmap_bit_p (&live_regs
, regno
))
4348 /* See which defined values die here. */
4349 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4350 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4351 bitmap_clear_bit (&live_regs
, reg
->regno
);
4352 /* Mark each used value as live. */
4353 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4354 if (reg
->type
== OP_IN
4355 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4356 bitmap_set_bit (&live_regs
, reg
->regno
);
4357 /* It is quite important to remove dead move insns because it
4358 means removing dead store. We don't need to process them for
4362 if (lra_dump_file
!= NULL
)
4364 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4365 debug_rtl_slim (lra_dump_file
, curr_insn
, curr_insn
, -1, 0);
4367 lra_set_insn_deleted (curr_insn
);
4372 /* The structure describes info to do an inheritance for the current
4373 insn. We need to collect such info first before doing the
4374 transformations because the transformations change the insn
4375 internal representation. */
4378 /* Original regno. */
4380 /* Subsequent insns which can inherit original reg value. */
4384 /* Array containing all info for doing inheritance from the current
4386 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4388 /* Number elements in the previous array. */
4389 static int to_inherit_num
;
4391 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4392 structure to_inherit. */
4394 add_to_inherit (int regno
, rtx insns
)
4398 for (i
= 0; i
< to_inherit_num
; i
++)
4399 if (to_inherit
[i
].regno
== regno
)
4401 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4402 to_inherit
[to_inherit_num
].regno
= regno
;
4403 to_inherit
[to_inherit_num
++].insns
= insns
;
4406 /* Return the last non-debug insn in basic block BB, or the block begin
4409 get_last_insertion_point (basic_block bb
)
4413 FOR_BB_INSNS_REVERSE (bb
, insn
)
4414 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4419 /* Set up RES by registers living on edges FROM except the edge (FROM,
4420 TO) or by registers set up in a jump insn in BB FROM. */
4422 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4425 struct lra_insn_reg
*reg
;
4429 lra_assert (to
!= NULL
);
4431 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4433 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4434 last
= get_last_insertion_point (from
);
4435 if (! JUMP_P (last
))
4437 curr_id
= lra_get_insn_recog_data (last
);
4438 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4439 if (reg
->type
!= OP_IN
)
4440 bitmap_set_bit (res
, reg
->regno
);
4443 /* Used as a temporary results of some bitmap calculations. */
4444 static bitmap_head temp_bitmap
;
4446 /* Do inheritance/split transformations in EBB starting with HEAD and
4447 finishing on TAIL. We process EBB insns in the reverse order.
4448 Return true if we did any inheritance/split transformation in the
4451 We should avoid excessive splitting which results in worse code
4452 because of inaccurate cost calculations for spilling new split
4453 pseudos in such case. To achieve this we do splitting only if
4454 register pressure is high in given basic block and there are reload
4455 pseudos requiring hard registers. We could do more register
4456 pressure calculations at any given program point to avoid necessary
4457 splitting even more but it is to expensive and the current approach
4458 works well enough. */
4460 inherit_in_ebb (rtx head
, rtx tail
)
4462 int i
, src_regno
, dst_regno
, nregs
;
4463 bool change_p
, succ_p
;
4464 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4466 struct lra_insn_reg
*reg
;
4467 basic_block last_processed_bb
, curr_bb
= NULL
;
4468 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4472 bool head_p
, after_p
;
4475 curr_usage_insns_check
++;
4476 reloads_num
= calls_num
= 0;
4477 bitmap_clear (&check_only_regs
);
4478 last_processed_bb
= NULL
;
4479 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4480 CLEAR_HARD_REG_SET (live_hard_regs
);
4481 /* We don't process new insns generated in the loop. */
4482 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4484 prev_insn
= PREV_INSN (curr_insn
);
4485 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4486 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4487 if (last_processed_bb
!= curr_bb
)
4489 /* We are at the end of BB. Add qualified living
4490 pseudos for potential splitting. */
4491 to_process
= df_get_live_out (curr_bb
);
4492 if (last_processed_bb
!= NULL
)
4494 /* We are somewhere in the middle of EBB. */
4495 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4497 to_process
= &temp_bitmap
;
4499 last_processed_bb
= curr_bb
;
4500 last_insn
= get_last_insertion_point (curr_bb
);
4501 after_p
= (! JUMP_P (last_insn
)
4502 && (! CALL_P (last_insn
)
4503 || (find_reg_note (last_insn
,
4504 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4505 && ! SIBLING_CALL_P (last_insn
))));
4506 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4507 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4508 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4509 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4510 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4512 if ((int) j
>= lra_constraint_new_regno_start
)
4514 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4516 if (j
< FIRST_PSEUDO_REGISTER
)
4517 SET_HARD_REG_BIT (live_hard_regs
, j
);
4519 add_to_hard_reg_set (&live_hard_regs
,
4520 PSEUDO_REGNO_MODE (j
),
4522 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4526 src_regno
= dst_regno
= -1;
4527 if (NONDEBUG_INSN_P (curr_insn
)
4528 && (set
= single_set (curr_insn
)) != NULL_RTX
4529 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4531 src_regno
= REGNO (SET_SRC (set
));
4532 dst_regno
= REGNO (SET_DEST (set
));
4534 if (src_regno
< lra_constraint_new_regno_start
4535 && src_regno
>= FIRST_PSEUDO_REGISTER
4536 && reg_renumber
[src_regno
] < 0
4537 && dst_regno
>= lra_constraint_new_regno_start
4538 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4540 /* 'reload_pseudo <- original_pseudo'. */
4543 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4544 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4545 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4546 curr_insn
, next_usage_insns
);
4550 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4551 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4552 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4553 reg_class_contents
[cl
]);
4555 else if (src_regno
>= lra_constraint_new_regno_start
4556 && dst_regno
< lra_constraint_new_regno_start
4557 && dst_regno
>= FIRST_PSEUDO_REGISTER
4558 && reg_renumber
[dst_regno
] < 0
4559 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
4560 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4561 && (next_usage_insns
4562 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4565 /* 'original_pseudo <- reload_pseudo'. */
4566 if (! JUMP_P (curr_insn
)
4567 && inherit_reload_reg (true, dst_regno
, cl
,
4568 curr_insn
, next_usage_insns
))
4571 usage_insns
[dst_regno
].check
= 0;
4572 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4573 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4574 reg_class_contents
[cl
]);
4576 else if (INSN_P (curr_insn
))
4578 int max_uid
= get_max_uid ();
4580 curr_id
= lra_get_insn_recog_data (curr_insn
);
4582 /* Process insn definitions. */
4583 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4584 if (reg
->type
!= OP_IN
4585 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4587 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
4588 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
4589 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4590 && (next_usage_insns
4591 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4593 struct lra_insn_reg
*r
;
4595 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
4596 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
4598 /* Don't do inheritance if the pseudo is also
4599 used in the insn. */
4601 /* We can not do inheritance right now
4602 because the current insn reg info (chain
4603 regs) can change after that. */
4604 add_to_inherit (dst_regno
, next_usage_insns
);
4606 /* We can not process one reg twice here because of
4607 usage_insns invalidation. */
4608 if ((dst_regno
< FIRST_PSEUDO_REGISTER
4609 || reg_renumber
[dst_regno
] >= 0)
4610 && ! reg
->subreg_p
&& reg
->type
== OP_OUT
)
4614 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
4615 potential_reload_hard_regs
,
4616 false, curr_insn
, max_uid
))
4618 CLEAR_HARD_REG_SET (s
);
4619 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
4620 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
4622 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
4623 reg_renumber
[dst_regno
]);
4624 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
4626 /* We should invalidate potential inheritance or
4627 splitting for the current insn usages to the next
4628 usage insns (see code below) as the output pseudo
4630 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
4631 && reg_renumber
[dst_regno
] < 0)
4632 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
4633 && (dst_regno
< FIRST_PSEUDO_REGISTER
4634 || reg_renumber
[dst_regno
] >= 0)))
4637 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
4638 usage_insns
[dst_regno
].check
= 0;
4641 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
4642 for (i
= 0; i
< nregs
; i
++)
4643 usage_insns
[dst_regno
+ i
].check
= 0;
4647 if (! JUMP_P (curr_insn
))
4648 for (i
= 0; i
< to_inherit_num
; i
++)
4649 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
4650 ALL_REGS
, curr_insn
,
4651 to_inherit
[i
].insns
))
4653 if (CALL_P (curr_insn
))
4655 rtx cheap
, pat
, dest
, restore
;
4656 int regno
, hard_regno
;
4659 if ((cheap
= find_reg_note (curr_insn
,
4660 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
4661 && ((cheap
= XEXP (cheap
, 0)), true)
4662 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
4663 && (hard_regno
= reg_renumber
[regno
]) >= 0
4664 /* If there are pending saves/restores, the
4665 optimization is not worth. */
4666 && usage_insns
[regno
].calls_num
== calls_num
- 1
4667 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
4669 /* Restore the pseudo from the call result as
4670 REG_RETURNED note says that the pseudo value is
4671 in the call result and the pseudo is an argument
4673 pat
= PATTERN (curr_insn
);
4674 if (GET_CODE (pat
) == PARALLEL
)
4675 pat
= XVECEXP (pat
, 0, 0);
4676 dest
= SET_DEST (pat
);
4678 emit_move_insn (cheap
, copy_rtx (dest
));
4679 restore
= get_insns ();
4681 lra_process_new_insns (curr_insn
, NULL
, restore
,
4682 "Inserting call parameter restore");
4683 /* We don't need to save/restore of the pseudo from
4685 usage_insns
[regno
].calls_num
= calls_num
;
4686 bitmap_set_bit (&check_only_regs
, regno
);
4690 /* Process insn usages. */
4691 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4692 if ((reg
->type
!= OP_OUT
4693 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
4694 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4696 if (src_regno
>= FIRST_PSEUDO_REGISTER
4697 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
4699 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4700 && (next_usage_insns
4701 = usage_insns
[src_regno
].insns
) != NULL_RTX
4702 && NONDEBUG_INSN_P (curr_insn
))
4703 add_to_inherit (src_regno
, next_usage_insns
);
4706 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
4708 else if (src_regno
< FIRST_PSEUDO_REGISTER
4709 || reg_renumber
[src_regno
] >= 0)
4712 rtx use_insn
= curr_insn
;
4714 before_p
= (JUMP_P (curr_insn
)
4715 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
4716 if (NONDEBUG_INSN_P (curr_insn
)
4717 && split_if_necessary (src_regno
, reg
->biggest_mode
,
4718 potential_reload_hard_regs
,
4719 before_p
, curr_insn
, max_uid
))
4722 lra_risky_transformations_p
= true;
4725 usage_insns
[src_regno
].check
= 0;
4727 use_insn
= PREV_INSN (curr_insn
);
4729 if (NONDEBUG_INSN_P (curr_insn
))
4731 if (src_regno
< FIRST_PSEUDO_REGISTER
)
4732 add_to_hard_reg_set (&live_hard_regs
,
4733 reg
->biggest_mode
, src_regno
);
4735 add_to_hard_reg_set (&live_hard_regs
,
4736 PSEUDO_REGNO_MODE (src_regno
),
4737 reg_renumber
[src_regno
]);
4739 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
4742 for (i
= 0; i
< to_inherit_num
; i
++)
4744 src_regno
= to_inherit
[i
].regno
;
4745 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
4746 curr_insn
, to_inherit
[i
].insns
))
4749 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4752 /* We reached the start of the current basic block. */
4753 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
4754 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
4756 /* We reached the beginning of the current block -- do
4757 rest of spliting in the current BB. */
4758 to_process
= df_get_live_in (curr_bb
);
4759 if (BLOCK_FOR_INSN (head
) != curr_bb
)
4761 /* We are somewhere in the middle of EBB. */
4762 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
4763 curr_bb
, &temp_bitmap
);
4764 to_process
= &temp_bitmap
;
4767 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4769 if ((int) j
>= lra_constraint_new_regno_start
)
4771 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4772 && usage_insns
[j
].check
== curr_usage_insns_check
4773 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
4775 if (need_for_split_p (potential_reload_hard_regs
, j
))
4777 if (lra_dump_file
!= NULL
&& head_p
)
4779 fprintf (lra_dump_file
,
4780 " ----------------------------------\n");
4783 if (split_reg (false, j
, bb_note (curr_bb
),
4787 usage_insns
[j
].check
= 0;
4795 /* This value affects EBB forming. If probability of edge from EBB to
4796 a BB is not greater than the following value, we don't add the BB
4798 #define EBB_PROBABILITY_CUTOFF (REG_BR_PROB_BASE / 2)
4800 /* Current number of inheritance/split iteration. */
4801 int lra_inheritance_iter
;
4803 /* Entry function for inheritance/split pass. */
4805 lra_inheritance (void)
4808 basic_block bb
, start_bb
;
4811 timevar_push (TV_LRA_INHERITANCE
);
4812 lra_inheritance_iter
++;
4813 if (lra_dump_file
!= NULL
)
4814 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
4815 lra_inheritance_iter
);
4816 curr_usage_insns_check
= 0;
4817 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
4818 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
4819 usage_insns
[i
].check
= 0;
4820 bitmap_initialize (&check_only_regs
, ®_obstack
);
4821 bitmap_initialize (&live_regs
, ®_obstack
);
4822 bitmap_initialize (&temp_bitmap
, ®_obstack
);
4823 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
4827 if (lra_dump_file
!= NULL
)
4828 fprintf (lra_dump_file
, "EBB");
4829 /* Form a EBB starting with BB. */
4830 bitmap_clear (&ebb_global_regs
);
4831 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
4834 if (lra_dump_file
!= NULL
)
4835 fprintf (lra_dump_file
, " %d", bb
->index
);
4836 if (bb
->next_bb
== EXIT_BLOCK_PTR
|| LABEL_P (BB_HEAD (bb
->next_bb
)))
4838 e
= find_fallthru_edge (bb
->succs
);
4841 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
4845 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
4846 if (lra_dump_file
!= NULL
)
4847 fprintf (lra_dump_file
, "\n");
4848 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
4849 /* Remember that the EBB head and tail can change in
4851 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
4853 bitmap_clear (&ebb_global_regs
);
4854 bitmap_clear (&temp_bitmap
);
4855 bitmap_clear (&live_regs
);
4856 bitmap_clear (&check_only_regs
);
4859 timevar_pop (TV_LRA_INHERITANCE
);
4864 /* This page contains code to undo failed inheritance/split
4867 /* Current number of iteration undoing inheritance/split. */
4868 int lra_undo_inheritance_iter
;
4870 /* Fix BB live info LIVE after removing pseudos created on pass doing
4871 inheritance/split which are REMOVED_PSEUDOS. */
4873 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
4878 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
4879 if (bitmap_clear_bit (live
, regno
))
4880 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
4883 /* Return regno of the (subreg of) REG. Otherwise, return a negative
4888 if (GET_CODE (reg
) == SUBREG
)
4889 reg
= SUBREG_REG (reg
);
4895 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
4896 return true if we did any change. The undo transformations for
4897 inheritance looks like
4901 p <- i, i <- p, and i <- i3
4902 where p is original pseudo from which inheritance pseudo i was
4903 created, i and i3 are removed inheritance pseudos, i2 is another
4904 not removed inheritance pseudo. All split pseudos or other
4905 occurrences of removed inheritance pseudos are changed on the
4906 corresponding original pseudos.
4908 The function also schedules insns changed and created during
4909 inheritance/split pass for processing by the subsequent constraint
4912 remove_inheritance_pseudos (bitmap remove_pseudos
)
4915 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
4916 rtx set
, prev_set
, prev_insn
;
4917 bool change_p
, done_p
;
4919 change_p
= ! bitmap_empty_p (remove_pseudos
);
4920 /* We can not finish the function right away if CHANGE_P is true
4921 because we need to marks insns affected by previous
4922 inheritance/split pass for processing by the subsequent
4926 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
4927 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
4928 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
4930 if (! INSN_P (curr_insn
))
4933 sregno
= dregno
= -1;
4934 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
4935 && (set
= single_set (curr_insn
)) != NULL_RTX
)
4937 dregno
= get_regno (SET_DEST (set
));
4938 sregno
= get_regno (SET_SRC (set
));
4941 if (sregno
>= 0 && dregno
>= 0)
4943 if ((bitmap_bit_p (remove_pseudos
, sregno
)
4944 && (lra_reg_info
[sregno
].restore_regno
== dregno
4945 || (bitmap_bit_p (remove_pseudos
, dregno
)
4946 && (lra_reg_info
[sregno
].restore_regno
4947 == lra_reg_info
[dregno
].restore_regno
))))
4948 || (bitmap_bit_p (remove_pseudos
, dregno
)
4949 && lra_reg_info
[dregno
].restore_regno
== sregno
))
4950 /* One of the following cases:
4951 original <- removed inheritance pseudo
4952 removed inherit pseudo <- another removed inherit pseudo
4953 removed inherit pseudo <- original pseudo
4955 removed_split_pseudo <- original_reg
4956 original_reg <- removed_split_pseudo */
4958 if (lra_dump_file
!= NULL
)
4960 fprintf (lra_dump_file
, " Removing %s:\n",
4961 bitmap_bit_p (&lra_split_regs
, sregno
)
4962 || bitmap_bit_p (&lra_split_regs
, dregno
)
4963 ? "split" : "inheritance");
4964 debug_rtl_slim (lra_dump_file
,
4965 curr_insn
, curr_insn
, -1, 0);
4967 lra_set_insn_deleted (curr_insn
);
4970 else if (bitmap_bit_p (remove_pseudos
, sregno
)
4971 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
4973 /* Search the following pattern:
4974 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
4975 original_pseudo <- inherit_or_split_pseudo1
4976 where the 2nd insn is the current insn and
4977 inherit_or_split_pseudo2 is not removed. If it is found,
4978 change the current insn onto:
4979 original_pseudo <- inherit_or_split_pseudo2. */
4980 for (prev_insn
= PREV_INSN (curr_insn
);
4981 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
4982 prev_insn
= PREV_INSN (prev_insn
))
4984 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
4985 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
4986 /* There should be no subregs in insn we are
4987 searching because only the original reg might
4988 be in subreg when we changed the mode of
4989 load/store for splitting. */
4990 && REG_P (SET_DEST (prev_set
))
4991 && REG_P (SET_SRC (prev_set
))
4992 && (int) REGNO (SET_DEST (prev_set
)) == sregno
4993 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
4994 >= FIRST_PSEUDO_REGISTER
)
4995 /* As we consider chain of inheritance or
4996 splitting described in above comment we should
4997 check that sregno and prev_sregno were
4998 inheritance/split pseudos created from the
4999 same original regno. */
5000 && (lra_reg_info
[sregno
].restore_regno
5001 == lra_reg_info
[prev_sregno
].restore_regno
)
5002 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5004 lra_assert (GET_MODE (SET_SRC (prev_set
))
5005 == GET_MODE (regno_reg_rtx
[sregno
]));
5006 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5007 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5009 SET_SRC (set
) = SET_SRC (prev_set
);
5010 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5011 lra_set_used_insn_alternative_by_uid
5012 (INSN_UID (curr_insn
), -1);
5014 if (lra_dump_file
!= NULL
)
5016 fprintf (lra_dump_file
, " Change reload insn:\n");
5017 debug_rtl_slim (lra_dump_file
,
5018 curr_insn
, curr_insn
, -1, 0);
5025 struct lra_insn_reg
*reg
;
5026 bool restored_regs_p
= false;
5027 bool kept_regs_p
= false;
5029 curr_id
= lra_get_insn_recog_data (curr_insn
);
5030 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5033 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5034 if (restore_regno
>= 0)
5036 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5038 substitute_pseudo (&curr_insn
, regno
,
5039 regno_reg_rtx
[restore_regno
]);
5040 restored_regs_p
= true;
5046 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5048 /* The instruction has changed since the previous
5049 constraints pass. */
5050 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5051 lra_set_used_insn_alternative_by_uid
5052 (INSN_UID (curr_insn
), -1);
5054 else if (restored_regs_p
)
5055 /* The instruction has been restored to the form that
5056 it had during the previous constraints pass. */
5057 lra_update_insn_regno_info (curr_insn
);
5058 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5060 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5061 debug_rtl_slim (lra_dump_file
, curr_insn
, curr_insn
, -1, 0);
5069 /* Entry function for undoing inheritance/split transformation. Return true
5070 if we did any RTL change in this pass. */
5072 lra_undo_inheritance (void)
5075 int restore_regno
, hard_regno
;
5076 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5077 bitmap_head remove_pseudos
;
5081 lra_undo_inheritance_iter
++;
5082 if (lra_dump_file
!= NULL
)
5083 fprintf (lra_dump_file
,
5084 "\n********** Undoing inheritance #%d: **********\n\n",
5085 lra_undo_inheritance_iter
);
5086 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5087 n_inherit
= n_all_inherit
= 0;
5088 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5089 if (lra_reg_info
[regno
].restore_regno
>= 0)
5092 if (reg_renumber
[regno
] < 0)
5093 bitmap_set_bit (&remove_pseudos
, regno
);
5097 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5098 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5099 n_inherit
, n_all_inherit
,
5100 (double) n_inherit
/ n_all_inherit
* 100);
5101 n_split
= n_all_split
= 0;
5102 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5103 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5106 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5107 ? reg_renumber
[restore_regno
] : restore_regno
);
5108 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5109 bitmap_set_bit (&remove_pseudos
, regno
);
5113 if (lra_dump_file
!= NULL
)
5114 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5115 regno
, restore_regno
);
5118 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5119 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5120 n_split
, n_all_split
,
5121 (double) n_split
/ n_all_split
* 100);
5122 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5123 bitmap_clear (&remove_pseudos
);
5124 /* Clear restore_regnos. */
5125 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5126 lra_reg_info
[regno
].restore_regno
= -1;
5127 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5128 lra_reg_info
[regno
].restore_regno
= -1;