1 /* Expand the basic unary and binary arithmetic operations, for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "diagnostic-core.h"
27 /* Include insn-config.h before expr.h so that HAVE_conditional_move
28 is properly defined. */
29 #include "insn-config.h"
34 #include "tree-hasher.h"
35 #include "stor-layout.h"
36 #include "stringpool.h"
40 #include "hard-reg-set.h"
50 #include "insn-codes.h"
56 #include "dominance.h"
58 #include "basic-block.h"
61 struct target_optabs default_target_optabs
;
62 struct target_libfuncs default_target_libfuncs
;
63 struct target_optabs
*this_fn_optabs
= &default_target_optabs
;
65 struct target_optabs
*this_target_optabs
= &default_target_optabs
;
66 struct target_libfuncs
*this_target_libfuncs
= &default_target_libfuncs
;
69 #define libfunc_hash \
70 (this_target_libfuncs->x_libfunc_hash)
72 static void prepare_float_lib_cmp (rtx
, rtx
, enum rtx_code
, rtx
*,
74 static rtx
expand_unop_direct (machine_mode
, optab
, rtx
, rtx
, int);
75 static void emit_libcall_block_1 (rtx_insn
*, rtx
, rtx
, rtx
, bool);
77 /* Debug facility for use in GDB. */
78 void debug_optab_libfuncs (void);
80 /* Prefixes for the current version of decimal floating point (BID vs. DPD) */
81 #if ENABLE_DECIMAL_BID_FORMAT
82 #define DECIMAL_PREFIX "bid_"
84 #define DECIMAL_PREFIX "dpd_"
87 /* Used for libfunc_hash. */
90 libfunc_hasher::hash (libfunc_entry
*e
)
92 return ((e
->mode1
+ e
->mode2
* NUM_MACHINE_MODES
) ^ e
->op
);
95 /* Used for libfunc_hash. */
98 libfunc_hasher::equal (libfunc_entry
*e1
, libfunc_entry
*e2
)
100 return e1
->op
== e2
->op
&& e1
->mode1
== e2
->mode1
&& e1
->mode2
== e2
->mode2
;
103 /* Return libfunc corresponding operation defined by OPTAB converting
104 from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL
105 if no libfunc is available. */
107 convert_optab_libfunc (convert_optab optab
, machine_mode mode1
,
110 struct libfunc_entry e
;
111 struct libfunc_entry
**slot
;
113 /* ??? This ought to be an assert, but not all of the places
114 that we expand optabs know about the optabs that got moved
116 if (!(optab
>= FIRST_CONV_OPTAB
&& optab
<= LAST_CONVLIB_OPTAB
))
122 slot
= libfunc_hash
->find_slot (&e
, NO_INSERT
);
125 const struct convert_optab_libcall_d
*d
126 = &convlib_def
[optab
- FIRST_CONV_OPTAB
];
128 if (d
->libcall_gen
== NULL
)
131 d
->libcall_gen (optab
, d
->libcall_basename
, mode1
, mode2
);
132 slot
= libfunc_hash
->find_slot (&e
, NO_INSERT
);
136 return (*slot
)->libfunc
;
139 /* Return libfunc corresponding operation defined by OPTAB in MODE.
140 Trigger lazy initialization if needed, return NULL if no libfunc is
143 optab_libfunc (optab optab
, machine_mode mode
)
145 struct libfunc_entry e
;
146 struct libfunc_entry
**slot
;
148 /* ??? This ought to be an assert, but not all of the places
149 that we expand optabs know about the optabs that got moved
151 if (!(optab
>= FIRST_NORM_OPTAB
&& optab
<= LAST_NORMLIB_OPTAB
))
157 slot
= libfunc_hash
->find_slot (&e
, NO_INSERT
);
160 const struct optab_libcall_d
*d
161 = &normlib_def
[optab
- FIRST_NORM_OPTAB
];
163 if (d
->libcall_gen
== NULL
)
166 d
->libcall_gen (optab
, d
->libcall_basename
, d
->libcall_suffix
, mode
);
167 slot
= libfunc_hash
->find_slot (&e
, NO_INSERT
);
171 return (*slot
)->libfunc
;
175 /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to
176 the result of operation CODE applied to OP0 (and OP1 if it is a binary
179 If the last insn does not set TARGET, don't do anything, but return 1.
181 If the last insn or a previous insn sets TARGET and TARGET is one of OP0
182 or OP1, don't add the REG_EQUAL note but return 0. Our caller can then
183 try again, ensuring that TARGET is not one of the operands. */
186 add_equal_note (rtx_insn
*insns
, rtx target
, enum rtx_code code
, rtx op0
, rtx op1
)
192 gcc_assert (insns
&& INSN_P (insns
) && NEXT_INSN (insns
));
194 if (GET_RTX_CLASS (code
) != RTX_COMM_ARITH
195 && GET_RTX_CLASS (code
) != RTX_BIN_ARITH
196 && GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
197 && GET_RTX_CLASS (code
) != RTX_COMPARE
198 && GET_RTX_CLASS (code
) != RTX_UNARY
)
201 if (GET_CODE (target
) == ZERO_EXTRACT
)
204 for (last_insn
= insns
;
205 NEXT_INSN (last_insn
) != NULL_RTX
;
206 last_insn
= NEXT_INSN (last_insn
))
209 /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing
210 a value changing in the insn, so the note would be invalid for CSE. */
211 if (reg_overlap_mentioned_p (target
, op0
)
212 || (op1
&& reg_overlap_mentioned_p (target
, op1
)))
215 && (rtx_equal_p (target
, op0
)
216 || (op1
&& rtx_equal_p (target
, op1
))))
218 /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note
219 over expanding it as temp = MEM op X, MEM = temp. If the target
220 supports MEM = MEM op X instructions, it is sometimes too hard
221 to reconstruct that form later, especially if X is also a memory,
222 and due to multiple occurrences of addresses the address might
223 be forced into register unnecessarily.
224 Note that not emitting the REG_EQUIV note might inhibit
225 CSE in some cases. */
226 set
= single_set (last_insn
);
228 && GET_CODE (SET_SRC (set
)) == code
229 && MEM_P (SET_DEST (set
))
230 && (rtx_equal_p (SET_DEST (set
), XEXP (SET_SRC (set
), 0))
231 || (op1
&& rtx_equal_p (SET_DEST (set
),
232 XEXP (SET_SRC (set
), 1)))))
238 set
= set_for_reg_notes (last_insn
);
242 if (! rtx_equal_p (SET_DEST (set
), target
)
243 /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */
244 && (GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
245 || ! rtx_equal_p (XEXP (SET_DEST (set
), 0), target
)))
248 if (GET_RTX_CLASS (code
) == RTX_UNARY
)
258 if (GET_MODE (op0
) != VOIDmode
&& GET_MODE (target
) != GET_MODE (op0
))
260 note
= gen_rtx_fmt_e (code
, GET_MODE (op0
), copy_rtx (op0
));
261 if (GET_MODE_SIZE (GET_MODE (op0
))
262 > GET_MODE_SIZE (GET_MODE (target
)))
263 note
= simplify_gen_unary (TRUNCATE
, GET_MODE (target
),
264 note
, GET_MODE (op0
));
266 note
= simplify_gen_unary (ZERO_EXTEND
, GET_MODE (target
),
267 note
, GET_MODE (op0
));
272 note
= gen_rtx_fmt_e (code
, GET_MODE (target
), copy_rtx (op0
));
276 note
= gen_rtx_fmt_ee (code
, GET_MODE (target
), copy_rtx (op0
), copy_rtx (op1
));
278 set_unique_reg_note (last_insn
, REG_EQUAL
, note
);
283 /* Given two input operands, OP0 and OP1, determine what the correct from_mode
284 for a widening operation would be. In most cases this would be OP0, but if
285 that's a constant it'll be VOIDmode, which isn't useful. */
288 widened_mode (machine_mode to_mode
, rtx op0
, rtx op1
)
290 machine_mode m0
= GET_MODE (op0
);
291 machine_mode m1
= GET_MODE (op1
);
294 if (m0
== VOIDmode
&& m1
== VOIDmode
)
296 else if (m0
== VOIDmode
|| GET_MODE_SIZE (m0
) < GET_MODE_SIZE (m1
))
301 if (GET_MODE_SIZE (result
) > GET_MODE_SIZE (to_mode
))
307 /* Like optab_handler, but for widening_operations that have a
308 TO_MODE and a FROM_MODE. */
311 widening_optab_handler (optab op
, machine_mode to_mode
,
312 machine_mode from_mode
)
314 unsigned scode
= (op
<< 16) | to_mode
;
315 if (to_mode
!= from_mode
&& from_mode
!= VOIDmode
)
317 /* ??? Why does find_widening_optab_handler_and_mode attempt to
318 widen things that can't be widened? E.g. add_optab... */
319 if (op
> LAST_CONV_OPTAB
)
320 return CODE_FOR_nothing
;
321 scode
|= from_mode
<< 8;
323 return raw_optab_handler (scode
);
326 /* Find a widening optab even if it doesn't widen as much as we want.
327 E.g. if from_mode is HImode, and to_mode is DImode, and there is no
328 direct HI->SI insn, then return SI->DI, if that exists.
329 If PERMIT_NON_WIDENING is non-zero then this can be used with
330 non-widening optabs also. */
333 find_widening_optab_handler_and_mode (optab op
, machine_mode to_mode
,
334 machine_mode from_mode
,
335 int permit_non_widening
,
336 machine_mode
*found_mode
)
338 for (; (permit_non_widening
|| from_mode
!= to_mode
)
339 && GET_MODE_SIZE (from_mode
) <= GET_MODE_SIZE (to_mode
)
340 && from_mode
!= VOIDmode
;
341 from_mode
= GET_MODE_WIDER_MODE (from_mode
))
343 enum insn_code handler
= widening_optab_handler (op
, to_mode
,
346 if (handler
!= CODE_FOR_nothing
)
349 *found_mode
= from_mode
;
354 return CODE_FOR_nothing
;
357 /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP
358 says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need
359 not actually do a sign-extend or zero-extend, but can leave the
360 higher-order bits of the result rtx undefined, for example, in the case
361 of logical operations, but not right shifts. */
364 widen_operand (rtx op
, machine_mode mode
, machine_mode oldmode
,
365 int unsignedp
, int no_extend
)
369 /* If we don't have to extend and this is a constant, return it. */
370 if (no_extend
&& GET_MODE (op
) == VOIDmode
)
373 /* If we must extend do so. If OP is a SUBREG for a promoted object, also
374 extend since it will be more efficient to do so unless the signedness of
375 a promoted object differs from our extension. */
377 || (GET_CODE (op
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (op
)
378 && SUBREG_CHECK_PROMOTED_SIGN (op
, unsignedp
)))
379 return convert_modes (mode
, oldmode
, op
, unsignedp
);
381 /* If MODE is no wider than a single word, we return a lowpart or paradoxical
383 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
384 return gen_lowpart (mode
, force_reg (GET_MODE (op
), op
));
386 /* Otherwise, get an object of MODE, clobber it, and set the low-order
389 result
= gen_reg_rtx (mode
);
390 emit_clobber (result
);
391 emit_move_insn (gen_lowpart (GET_MODE (op
), result
), op
);
395 /* Return the optab used for computing the operation given by the tree code,
396 CODE and the tree EXP. This function is not always usable (for example, it
397 cannot give complete results for multiplication or division) but probably
398 ought to be relied on more widely throughout the expander. */
400 optab_for_tree_code (enum tree_code code
, const_tree type
,
401 enum optab_subtype subtype
)
413 return one_cmpl_optab
;
418 case MULT_HIGHPART_EXPR
:
419 return TYPE_UNSIGNED (type
) ? umul_highpart_optab
: smul_highpart_optab
;
425 return TYPE_UNSIGNED (type
) ? umod_optab
: smod_optab
;
433 if (TYPE_SATURATING (type
))
434 return TYPE_UNSIGNED (type
) ? usdiv_optab
: ssdiv_optab
;
435 return TYPE_UNSIGNED (type
) ? udiv_optab
: sdiv_optab
;
438 if (TREE_CODE (type
) == VECTOR_TYPE
)
440 if (subtype
== optab_vector
)
441 return TYPE_SATURATING (type
) ? unknown_optab
: vashl_optab
;
443 gcc_assert (subtype
== optab_scalar
);
445 if (TYPE_SATURATING (type
))
446 return TYPE_UNSIGNED (type
) ? usashl_optab
: ssashl_optab
;
450 if (TREE_CODE (type
) == VECTOR_TYPE
)
452 if (subtype
== optab_vector
)
453 return TYPE_UNSIGNED (type
) ? vlshr_optab
: vashr_optab
;
455 gcc_assert (subtype
== optab_scalar
);
457 return TYPE_UNSIGNED (type
) ? lshr_optab
: ashr_optab
;
460 if (TREE_CODE (type
) == VECTOR_TYPE
)
462 if (subtype
== optab_vector
)
465 gcc_assert (subtype
== optab_scalar
);
470 if (TREE_CODE (type
) == VECTOR_TYPE
)
472 if (subtype
== optab_vector
)
475 gcc_assert (subtype
== optab_scalar
);
480 return TYPE_UNSIGNED (type
) ? umax_optab
: smax_optab
;
483 return TYPE_UNSIGNED (type
) ? umin_optab
: smin_optab
;
485 case REALIGN_LOAD_EXPR
:
486 return vec_realign_load_optab
;
489 return TYPE_UNSIGNED (type
) ? usum_widen_optab
: ssum_widen_optab
;
492 return TYPE_UNSIGNED (type
) ? udot_prod_optab
: sdot_prod_optab
;
495 return TYPE_UNSIGNED (type
) ? usad_optab
: ssad_optab
;
497 case WIDEN_MULT_PLUS_EXPR
:
498 return (TYPE_UNSIGNED (type
)
499 ? (TYPE_SATURATING (type
)
500 ? usmadd_widen_optab
: umadd_widen_optab
)
501 : (TYPE_SATURATING (type
)
502 ? ssmadd_widen_optab
: smadd_widen_optab
));
504 case WIDEN_MULT_MINUS_EXPR
:
505 return (TYPE_UNSIGNED (type
)
506 ? (TYPE_SATURATING (type
)
507 ? usmsub_widen_optab
: umsub_widen_optab
)
508 : (TYPE_SATURATING (type
)
509 ? ssmsub_widen_optab
: smsub_widen_optab
));
515 return TYPE_UNSIGNED (type
)
516 ? reduc_umax_scal_optab
: reduc_smax_scal_optab
;
519 return TYPE_UNSIGNED (type
)
520 ? reduc_umin_scal_optab
: reduc_smin_scal_optab
;
522 case REDUC_PLUS_EXPR
:
523 return reduc_plus_scal_optab
;
525 case VEC_WIDEN_MULT_HI_EXPR
:
526 return TYPE_UNSIGNED (type
) ?
527 vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
529 case VEC_WIDEN_MULT_LO_EXPR
:
530 return TYPE_UNSIGNED (type
) ?
531 vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
533 case VEC_WIDEN_MULT_EVEN_EXPR
:
534 return TYPE_UNSIGNED (type
) ?
535 vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
537 case VEC_WIDEN_MULT_ODD_EXPR
:
538 return TYPE_UNSIGNED (type
) ?
539 vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
541 case VEC_WIDEN_LSHIFT_HI_EXPR
:
542 return TYPE_UNSIGNED (type
) ?
543 vec_widen_ushiftl_hi_optab
: vec_widen_sshiftl_hi_optab
;
545 case VEC_WIDEN_LSHIFT_LO_EXPR
:
546 return TYPE_UNSIGNED (type
) ?
547 vec_widen_ushiftl_lo_optab
: vec_widen_sshiftl_lo_optab
;
549 case VEC_UNPACK_HI_EXPR
:
550 return TYPE_UNSIGNED (type
) ?
551 vec_unpacku_hi_optab
: vec_unpacks_hi_optab
;
553 case VEC_UNPACK_LO_EXPR
:
554 return TYPE_UNSIGNED (type
) ?
555 vec_unpacku_lo_optab
: vec_unpacks_lo_optab
;
557 case VEC_UNPACK_FLOAT_HI_EXPR
:
558 /* The signedness is determined from input operand. */
559 return TYPE_UNSIGNED (type
) ?
560 vec_unpacku_float_hi_optab
: vec_unpacks_float_hi_optab
;
562 case VEC_UNPACK_FLOAT_LO_EXPR
:
563 /* The signedness is determined from input operand. */
564 return TYPE_UNSIGNED (type
) ?
565 vec_unpacku_float_lo_optab
: vec_unpacks_float_lo_optab
;
567 case VEC_PACK_TRUNC_EXPR
:
568 return vec_pack_trunc_optab
;
570 case VEC_PACK_SAT_EXPR
:
571 return TYPE_UNSIGNED (type
) ? vec_pack_usat_optab
: vec_pack_ssat_optab
;
573 case VEC_PACK_FIX_TRUNC_EXPR
:
574 /* The signedness is determined from output operand. */
575 return TYPE_UNSIGNED (type
) ?
576 vec_pack_ufix_trunc_optab
: vec_pack_sfix_trunc_optab
;
582 trapv
= INTEGRAL_TYPE_P (type
) && TYPE_OVERFLOW_TRAPS (type
);
585 case POINTER_PLUS_EXPR
:
587 if (TYPE_SATURATING (type
))
588 return TYPE_UNSIGNED (type
) ? usadd_optab
: ssadd_optab
;
589 return trapv
? addv_optab
: add_optab
;
592 if (TYPE_SATURATING (type
))
593 return TYPE_UNSIGNED (type
) ? ussub_optab
: sssub_optab
;
594 return trapv
? subv_optab
: sub_optab
;
597 if (TYPE_SATURATING (type
))
598 return TYPE_UNSIGNED (type
) ? usmul_optab
: ssmul_optab
;
599 return trapv
? smulv_optab
: smul_optab
;
602 if (TYPE_SATURATING (type
))
603 return TYPE_UNSIGNED (type
) ? usneg_optab
: ssneg_optab
;
604 return trapv
? negv_optab
: neg_optab
;
607 return trapv
? absv_optab
: abs_optab
;
610 return unknown_optab
;
614 /* Given optab UNOPTAB that reduces a vector to a scalar, find instead the old
615 optab that produces a vector with the reduction result in one element,
616 for a tree with type TYPE. */
619 scalar_reduc_to_vector (optab unoptab
, const_tree type
)
623 case reduc_plus_scal_optab
:
624 return TYPE_UNSIGNED (type
) ? reduc_uplus_optab
: reduc_splus_optab
;
626 case reduc_smin_scal_optab
: return reduc_smin_optab
;
627 case reduc_umin_scal_optab
: return reduc_umin_optab
;
628 case reduc_smax_scal_optab
: return reduc_smax_optab
;
629 case reduc_umax_scal_optab
: return reduc_umax_optab
;
630 default: return unknown_optab
;
634 /* Expand vector widening operations.
636 There are two different classes of operations handled here:
637 1) Operations whose result is wider than all the arguments to the operation.
638 Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR
639 In this case OP0 and optionally OP1 would be initialized,
640 but WIDE_OP wouldn't (not relevant for this case).
641 2) Operations whose result is of the same size as the last argument to the
642 operation, but wider than all the other arguments to the operation.
643 Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR.
644 In the case WIDE_OP, OP0 and optionally OP1 would be initialized.
646 E.g, when called to expand the following operations, this is how
647 the arguments will be initialized:
649 widening-sum 2 oprnd0 - oprnd1
650 widening-dot-product 3 oprnd0 oprnd1 oprnd2
651 widening-mult 2 oprnd0 oprnd1 -
652 type-promotion (vec-unpack) 1 oprnd0 - - */
655 expand_widen_pattern_expr (sepops ops
, rtx op0
, rtx op1
, rtx wide_op
,
656 rtx target
, int unsignedp
)
658 struct expand_operand eops
[4];
659 tree oprnd0
, oprnd1
, oprnd2
;
660 machine_mode wmode
= VOIDmode
, tmode0
, tmode1
= VOIDmode
;
661 optab widen_pattern_optab
;
662 enum insn_code icode
;
663 int nops
= TREE_CODE_LENGTH (ops
->code
);
667 tmode0
= TYPE_MODE (TREE_TYPE (oprnd0
));
668 widen_pattern_optab
=
669 optab_for_tree_code (ops
->code
, TREE_TYPE (oprnd0
), optab_default
);
670 if (ops
->code
== WIDEN_MULT_PLUS_EXPR
671 || ops
->code
== WIDEN_MULT_MINUS_EXPR
)
672 icode
= find_widening_optab_handler (widen_pattern_optab
,
673 TYPE_MODE (TREE_TYPE (ops
->op2
)),
676 icode
= optab_handler (widen_pattern_optab
, tmode0
);
677 gcc_assert (icode
!= CODE_FOR_nothing
);
682 tmode1
= TYPE_MODE (TREE_TYPE (oprnd1
));
685 /* The last operand is of a wider mode than the rest of the operands. */
690 gcc_assert (tmode1
== tmode0
);
693 wmode
= TYPE_MODE (TREE_TYPE (oprnd2
));
697 create_output_operand (&eops
[op
++], target
, TYPE_MODE (ops
->type
));
698 create_convert_operand_from (&eops
[op
++], op0
, tmode0
, unsignedp
);
700 create_convert_operand_from (&eops
[op
++], op1
, tmode1
, unsignedp
);
702 create_convert_operand_from (&eops
[op
++], wide_op
, wmode
, unsignedp
);
703 expand_insn (icode
, op
, eops
);
704 return eops
[0].value
;
707 /* Generate code to perform an operation specified by TERNARY_OPTAB
708 on operands OP0, OP1 and OP2, with result having machine-mode MODE.
710 UNSIGNEDP is for the case where we have to widen the operands
711 to perform the operation. It says to use zero-extension.
713 If TARGET is nonzero, the value
714 is generated there, if it is convenient to do so.
715 In all cases an rtx is returned for the locus of the value;
716 this may or may not be TARGET. */
719 expand_ternary_op (machine_mode mode
, optab ternary_optab
, rtx op0
,
720 rtx op1
, rtx op2
, rtx target
, int unsignedp
)
722 struct expand_operand ops
[4];
723 enum insn_code icode
= optab_handler (ternary_optab
, mode
);
725 gcc_assert (optab_handler (ternary_optab
, mode
) != CODE_FOR_nothing
);
727 create_output_operand (&ops
[0], target
, mode
);
728 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
729 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
730 create_convert_operand_from (&ops
[3], op2
, mode
, unsignedp
);
731 expand_insn (icode
, 4, ops
);
736 /* Like expand_binop, but return a constant rtx if the result can be
737 calculated at compile time. The arguments and return value are
738 otherwise the same as for expand_binop. */
741 simplify_expand_binop (machine_mode mode
, optab binoptab
,
742 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
743 enum optab_methods methods
)
745 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
747 rtx x
= simplify_binary_operation (optab_to_code (binoptab
),
753 return expand_binop (mode
, binoptab
, op0
, op1
, target
, unsignedp
, methods
);
756 /* Like simplify_expand_binop, but always put the result in TARGET.
757 Return true if the expansion succeeded. */
760 force_expand_binop (machine_mode mode
, optab binoptab
,
761 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
762 enum optab_methods methods
)
764 rtx x
= simplify_expand_binop (mode
, binoptab
, op0
, op1
,
765 target
, unsignedp
, methods
);
769 emit_move_insn (target
, x
);
773 /* Create a new vector value in VMODE with all elements set to OP. The
774 mode of OP must be the element mode of VMODE. If OP is a constant,
775 then the return value will be a constant. */
778 expand_vector_broadcast (machine_mode vmode
, rtx op
)
780 enum insn_code icode
;
785 gcc_checking_assert (VECTOR_MODE_P (vmode
));
787 n
= GET_MODE_NUNITS (vmode
);
788 vec
= rtvec_alloc (n
);
789 for (i
= 0; i
< n
; ++i
)
790 RTVEC_ELT (vec
, i
) = op
;
793 return gen_rtx_CONST_VECTOR (vmode
, vec
);
795 /* ??? If the target doesn't have a vec_init, then we have no easy way
796 of performing this operation. Most of this sort of generic support
797 is hidden away in the vector lowering support in gimple. */
798 icode
= optab_handler (vec_init_optab
, vmode
);
799 if (icode
== CODE_FOR_nothing
)
802 ret
= gen_reg_rtx (vmode
);
803 emit_insn (GEN_FCN (icode
) (ret
, gen_rtx_PARALLEL (vmode
, vec
)));
808 /* This subroutine of expand_doubleword_shift handles the cases in which
809 the effective shift value is >= BITS_PER_WORD. The arguments and return
810 value are the same as for the parent routine, except that SUPERWORD_OP1
811 is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET.
812 INTO_TARGET may be null if the caller has decided to calculate it. */
815 expand_superword_shift (optab binoptab
, rtx outof_input
, rtx superword_op1
,
816 rtx outof_target
, rtx into_target
,
817 int unsignedp
, enum optab_methods methods
)
819 if (into_target
!= 0)
820 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, superword_op1
,
821 into_target
, unsignedp
, methods
))
824 if (outof_target
!= 0)
826 /* For a signed right shift, we must fill OUTOF_TARGET with copies
827 of the sign bit, otherwise we must fill it with zeros. */
828 if (binoptab
!= ashr_optab
)
829 emit_move_insn (outof_target
, CONST0_RTX (word_mode
));
831 if (!force_expand_binop (word_mode
, binoptab
,
832 outof_input
, GEN_INT (BITS_PER_WORD
- 1),
833 outof_target
, unsignedp
, methods
))
839 /* This subroutine of expand_doubleword_shift handles the cases in which
840 the effective shift value is < BITS_PER_WORD. The arguments and return
841 value are the same as for the parent routine. */
844 expand_subword_shift (machine_mode op1_mode
, optab binoptab
,
845 rtx outof_input
, rtx into_input
, rtx op1
,
846 rtx outof_target
, rtx into_target
,
847 int unsignedp
, enum optab_methods methods
,
848 unsigned HOST_WIDE_INT shift_mask
)
850 optab reverse_unsigned_shift
, unsigned_shift
;
853 reverse_unsigned_shift
= (binoptab
== ashl_optab
? lshr_optab
: ashl_optab
);
854 unsigned_shift
= (binoptab
== ashl_optab
? ashl_optab
: lshr_optab
);
856 /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT.
857 We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in
858 the opposite direction to BINOPTAB. */
859 if (CONSTANT_P (op1
) || shift_mask
>= BITS_PER_WORD
)
861 carries
= outof_input
;
862 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
,
863 op1_mode
), op1_mode
);
864 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
869 /* We must avoid shifting by BITS_PER_WORD bits since that is either
870 the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or
871 has unknown behavior. Do a single shift first, then shift by the
872 remainder. It's OK to use ~OP1 as the remainder if shift counts
873 are truncated to the mode size. */
874 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
875 outof_input
, const1_rtx
, 0, unsignedp
, methods
);
876 if (shift_mask
== BITS_PER_WORD
- 1)
878 tmp
= immed_wide_int_const
879 (wi::minus_one (GET_MODE_PRECISION (op1_mode
)), op1_mode
);
880 tmp
= simplify_expand_binop (op1_mode
, xor_optab
, op1
, tmp
,
885 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
- 1,
886 op1_mode
), op1_mode
);
887 tmp
= simplify_expand_binop (op1_mode
, sub_optab
, tmp
, op1
,
891 if (tmp
== 0 || carries
== 0)
893 carries
= expand_binop (word_mode
, reverse_unsigned_shift
,
894 carries
, tmp
, 0, unsignedp
, methods
);
898 /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT
899 so the result can go directly into INTO_TARGET if convenient. */
900 tmp
= expand_binop (word_mode
, unsigned_shift
, into_input
, op1
,
901 into_target
, unsignedp
, methods
);
905 /* Now OR in the bits carried over from OUTOF_INPUT. */
906 if (!force_expand_binop (word_mode
, ior_optab
, tmp
, carries
,
907 into_target
, unsignedp
, methods
))
910 /* Use a standard word_mode shift for the out-of half. */
911 if (outof_target
!= 0)
912 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
913 outof_target
, unsignedp
, methods
))
920 /* Try implementing expand_doubleword_shift using conditional moves.
921 The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true,
922 otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1
923 are the shift counts to use in the former and latter case. All other
924 arguments are the same as the parent routine. */
927 expand_doubleword_shift_condmove (machine_mode op1_mode
, optab binoptab
,
928 enum rtx_code cmp_code
, rtx cmp1
, rtx cmp2
,
929 rtx outof_input
, rtx into_input
,
930 rtx subword_op1
, rtx superword_op1
,
931 rtx outof_target
, rtx into_target
,
932 int unsignedp
, enum optab_methods methods
,
933 unsigned HOST_WIDE_INT shift_mask
)
935 rtx outof_superword
, into_superword
;
937 /* Put the superword version of the output into OUTOF_SUPERWORD and
939 outof_superword
= outof_target
!= 0 ? gen_reg_rtx (word_mode
) : 0;
940 if (outof_target
!= 0 && subword_op1
== superword_op1
)
942 /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in
943 OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */
944 into_superword
= outof_target
;
945 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
946 outof_superword
, 0, unsignedp
, methods
))
951 into_superword
= gen_reg_rtx (word_mode
);
952 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
953 outof_superword
, into_superword
,
958 /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */
959 if (!expand_subword_shift (op1_mode
, binoptab
,
960 outof_input
, into_input
, subword_op1
,
961 outof_target
, into_target
,
962 unsignedp
, methods
, shift_mask
))
965 /* Select between them. Do the INTO half first because INTO_SUPERWORD
966 might be the current value of OUTOF_TARGET. */
967 if (!emit_conditional_move (into_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
968 into_target
, into_superword
, word_mode
, false))
971 if (outof_target
!= 0)
972 if (!emit_conditional_move (outof_target
, cmp_code
, cmp1
, cmp2
, op1_mode
,
973 outof_target
, outof_superword
,
980 /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts.
981 OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first
982 input operand; the shift moves bits in the direction OUTOF_INPUT->
983 INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words
984 of the target. OP1 is the shift count and OP1_MODE is its mode.
985 If OP1 is constant, it will have been truncated as appropriate
986 and is known to be nonzero.
988 If SHIFT_MASK is zero, the result of word shifts is undefined when the
989 shift count is outside the range [0, BITS_PER_WORD). This routine must
990 avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2).
992 If SHIFT_MASK is nonzero, all word-mode shift counts are effectively
993 masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will
994 fill with zeros or sign bits as appropriate.
996 If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize
997 a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1.
998 Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED.
999 In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2)
1002 BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function
1003 may not use INTO_INPUT after modifying INTO_TARGET, and similarly for
1004 OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent
1005 function wants to calculate it itself.
1007 Return true if the shift could be successfully synthesized. */
1010 expand_doubleword_shift (machine_mode op1_mode
, optab binoptab
,
1011 rtx outof_input
, rtx into_input
, rtx op1
,
1012 rtx outof_target
, rtx into_target
,
1013 int unsignedp
, enum optab_methods methods
,
1014 unsigned HOST_WIDE_INT shift_mask
)
1016 rtx superword_op1
, tmp
, cmp1
, cmp2
;
1017 enum rtx_code cmp_code
;
1019 /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will
1020 fill the result with sign or zero bits as appropriate. If so, the value
1021 of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call
1022 this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT
1023 and INTO_INPUT), then emit code to set up OUTOF_TARGET.
1025 This isn't worthwhile for constant shifts since the optimizers will
1026 cope better with in-range shift counts. */
1027 if (shift_mask
>= BITS_PER_WORD
1028 && outof_target
!= 0
1029 && !CONSTANT_P (op1
))
1031 if (!expand_doubleword_shift (op1_mode
, binoptab
,
1032 outof_input
, into_input
, op1
,
1034 unsignedp
, methods
, shift_mask
))
1036 if (!force_expand_binop (word_mode
, binoptab
, outof_input
, op1
,
1037 outof_target
, unsignedp
, methods
))
1042 /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2)
1043 is true when the effective shift value is less than BITS_PER_WORD.
1044 Set SUPERWORD_OP1 to the shift count that should be used to shift
1045 OUTOF_INPUT into INTO_TARGET when the condition is false. */
1046 tmp
= immed_wide_int_const (wi::shwi (BITS_PER_WORD
, op1_mode
), op1_mode
);
1047 if (!CONSTANT_P (op1
) && shift_mask
== BITS_PER_WORD
- 1)
1049 /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1
1050 is a subword shift count. */
1051 cmp1
= simplify_expand_binop (op1_mode
, and_optab
, op1
, tmp
,
1053 cmp2
= CONST0_RTX (op1_mode
);
1055 superword_op1
= op1
;
1059 /* Set CMP1 to OP1 - BITS_PER_WORD. */
1060 cmp1
= simplify_expand_binop (op1_mode
, sub_optab
, op1
, tmp
,
1062 cmp2
= CONST0_RTX (op1_mode
);
1064 superword_op1
= cmp1
;
1069 /* If we can compute the condition at compile time, pick the
1070 appropriate subroutine. */
1071 tmp
= simplify_relational_operation (cmp_code
, SImode
, op1_mode
, cmp1
, cmp2
);
1072 if (tmp
!= 0 && CONST_INT_P (tmp
))
1074 if (tmp
== const0_rtx
)
1075 return expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1076 outof_target
, into_target
,
1077 unsignedp
, methods
);
1079 return expand_subword_shift (op1_mode
, binoptab
,
1080 outof_input
, into_input
, op1
,
1081 outof_target
, into_target
,
1082 unsignedp
, methods
, shift_mask
);
1085 /* Try using conditional moves to generate straight-line code. */
1086 if (HAVE_conditional_move
)
1088 rtx_insn
*start
= get_last_insn ();
1089 if (expand_doubleword_shift_condmove (op1_mode
, binoptab
,
1090 cmp_code
, cmp1
, cmp2
,
1091 outof_input
, into_input
,
1093 outof_target
, into_target
,
1094 unsignedp
, methods
, shift_mask
))
1096 delete_insns_since (start
);
1099 /* As a last resort, use branches to select the correct alternative. */
1100 rtx_code_label
*subword_label
= gen_label_rtx ();
1101 rtx_code_label
*done_label
= gen_label_rtx ();
1104 do_compare_rtx_and_jump (cmp1
, cmp2
, cmp_code
, false, op1_mode
,
1105 0, 0, subword_label
, -1);
1108 if (!expand_superword_shift (binoptab
, outof_input
, superword_op1
,
1109 outof_target
, into_target
,
1110 unsignedp
, methods
))
1113 emit_jump_insn (gen_jump (done_label
));
1115 emit_label (subword_label
);
1117 if (!expand_subword_shift (op1_mode
, binoptab
,
1118 outof_input
, into_input
, op1
,
1119 outof_target
, into_target
,
1120 unsignedp
, methods
, shift_mask
))
1123 emit_label (done_label
);
1127 /* Subroutine of expand_binop. Perform a double word multiplication of
1128 operands OP0 and OP1 both of mode MODE, which is exactly twice as wide
1129 as the target's word_mode. This function return NULL_RTX if anything
1130 goes wrong, in which case it may have already emitted instructions
1131 which need to be deleted.
1133 If we want to multiply two two-word values and have normal and widening
1134 multiplies of single-word values, we can do this with three smaller
1137 The multiplication proceeds as follows:
1138 _______________________
1139 [__op0_high_|__op0_low__]
1140 _______________________
1141 * [__op1_high_|__op1_low__]
1142 _______________________________________________
1143 _______________________
1144 (1) [__op0_low__*__op1_low__]
1145 _______________________
1146 (2a) [__op0_low__*__op1_high_]
1147 _______________________
1148 (2b) [__op0_high_*__op1_low__]
1149 _______________________
1150 (3) [__op0_high_*__op1_high_]
1153 This gives a 4-word result. Since we are only interested in the
1154 lower 2 words, partial result (3) and the upper words of (2a) and
1155 (2b) don't need to be calculated. Hence (2a) and (2b) can be
1156 calculated using non-widening multiplication.
1158 (1), however, needs to be calculated with an unsigned widening
1159 multiplication. If this operation is not directly supported we
1160 try using a signed widening multiplication and adjust the result.
1161 This adjustment works as follows:
1163 If both operands are positive then no adjustment is needed.
1165 If the operands have different signs, for example op0_low < 0 and
1166 op1_low >= 0, the instruction treats the most significant bit of
1167 op0_low as a sign bit instead of a bit with significance
1168 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low
1169 with 2**BITS_PER_WORD - op0_low, and two's complements the
1170 result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to
1173 Similarly, if both operands are negative, we need to add
1174 (op0_low + op1_low) * 2**BITS_PER_WORD.
1176 We use a trick to adjust quickly. We logically shift op0_low right
1177 (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to
1178 op0_high (op1_high) before it is used to calculate 2b (2a). If no
1179 logical shift exists, we do an arithmetic right shift and subtract
1183 expand_doubleword_mult (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
1184 bool umulp
, enum optab_methods methods
)
1186 int low
= (WORDS_BIG_ENDIAN
? 1 : 0);
1187 int high
= (WORDS_BIG_ENDIAN
? 0 : 1);
1188 rtx wordm1
= umulp
? NULL_RTX
: GEN_INT (BITS_PER_WORD
- 1);
1189 rtx product
, adjust
, product_high
, temp
;
1191 rtx op0_high
= operand_subword_force (op0
, high
, mode
);
1192 rtx op0_low
= operand_subword_force (op0
, low
, mode
);
1193 rtx op1_high
= operand_subword_force (op1
, high
, mode
);
1194 rtx op1_low
= operand_subword_force (op1
, low
, mode
);
1196 /* If we're using an unsigned multiply to directly compute the product
1197 of the low-order words of the operands and perform any required
1198 adjustments of the operands, we begin by trying two more multiplications
1199 and then computing the appropriate sum.
1201 We have checked above that the required addition is provided.
1202 Full-word addition will normally always succeed, especially if
1203 it is provided at all, so we don't worry about its failure. The
1204 multiplication may well fail, however, so we do handle that. */
1208 /* ??? This could be done with emit_store_flag where available. */
1209 temp
= expand_binop (word_mode
, lshr_optab
, op0_low
, wordm1
,
1210 NULL_RTX
, 1, methods
);
1212 op0_high
= expand_binop (word_mode
, add_optab
, op0_high
, temp
,
1213 NULL_RTX
, 0, OPTAB_DIRECT
);
1216 temp
= expand_binop (word_mode
, ashr_optab
, op0_low
, wordm1
,
1217 NULL_RTX
, 0, methods
);
1220 op0_high
= expand_binop (word_mode
, sub_optab
, op0_high
, temp
,
1221 NULL_RTX
, 0, OPTAB_DIRECT
);
1228 adjust
= expand_binop (word_mode
, smul_optab
, op0_high
, op1_low
,
1229 NULL_RTX
, 0, OPTAB_DIRECT
);
1233 /* OP0_HIGH should now be dead. */
1237 /* ??? This could be done with emit_store_flag where available. */
1238 temp
= expand_binop (word_mode
, lshr_optab
, op1_low
, wordm1
,
1239 NULL_RTX
, 1, methods
);
1241 op1_high
= expand_binop (word_mode
, add_optab
, op1_high
, temp
,
1242 NULL_RTX
, 0, OPTAB_DIRECT
);
1245 temp
= expand_binop (word_mode
, ashr_optab
, op1_low
, wordm1
,
1246 NULL_RTX
, 0, methods
);
1249 op1_high
= expand_binop (word_mode
, sub_optab
, op1_high
, temp
,
1250 NULL_RTX
, 0, OPTAB_DIRECT
);
1257 temp
= expand_binop (word_mode
, smul_optab
, op1_high
, op0_low
,
1258 NULL_RTX
, 0, OPTAB_DIRECT
);
1262 /* OP1_HIGH should now be dead. */
1264 adjust
= expand_binop (word_mode
, add_optab
, adjust
, temp
,
1265 NULL_RTX
, 0, OPTAB_DIRECT
);
1267 if (target
&& !REG_P (target
))
1271 product
= expand_binop (mode
, umul_widen_optab
, op0_low
, op1_low
,
1272 target
, 1, OPTAB_DIRECT
);
1274 product
= expand_binop (mode
, smul_widen_optab
, op0_low
, op1_low
,
1275 target
, 1, OPTAB_DIRECT
);
1280 product_high
= operand_subword (product
, high
, 1, mode
);
1281 adjust
= expand_binop (word_mode
, add_optab
, product_high
, adjust
,
1282 NULL_RTX
, 0, OPTAB_DIRECT
);
1283 emit_move_insn (product_high
, adjust
);
1287 /* Wrapper around expand_binop which takes an rtx code to specify
1288 the operation to perform, not an optab pointer. All other
1289 arguments are the same. */
1291 expand_simple_binop (machine_mode mode
, enum rtx_code code
, rtx op0
,
1292 rtx op1
, rtx target
, int unsignedp
,
1293 enum optab_methods methods
)
1295 optab binop
= code_to_optab (code
);
1298 return expand_binop (mode
, binop
, op0
, op1
, target
, unsignedp
, methods
);
1301 /* Return whether OP0 and OP1 should be swapped when expanding a commutative
1302 binop. Order them according to commutative_operand_precedence and, if
1303 possible, try to put TARGET or a pseudo first. */
1305 swap_commutative_operands_with_target (rtx target
, rtx op0
, rtx op1
)
1307 int op0_prec
= commutative_operand_precedence (op0
);
1308 int op1_prec
= commutative_operand_precedence (op1
);
1310 if (op0_prec
< op1_prec
)
1313 if (op0_prec
> op1_prec
)
1316 /* With equal precedence, both orders are ok, but it is better if the
1317 first operand is TARGET, or if both TARGET and OP0 are pseudos. */
1318 if (target
== 0 || REG_P (target
))
1319 return (REG_P (op1
) && !REG_P (op0
)) || target
== op1
;
1321 return rtx_equal_p (op1
, target
);
1324 /* Return true if BINOPTAB implements a shift operation. */
1327 shift_optab_p (optab binoptab
)
1329 switch (optab_to_code (binoptab
))
1345 /* Return true if BINOPTAB implements a commutative binary operation. */
1348 commutative_optab_p (optab binoptab
)
1350 return (GET_RTX_CLASS (optab_to_code (binoptab
)) == RTX_COMM_ARITH
1351 || binoptab
== smul_widen_optab
1352 || binoptab
== umul_widen_optab
1353 || binoptab
== smul_highpart_optab
1354 || binoptab
== umul_highpart_optab
);
1357 /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're
1358 optimizing, and if the operand is a constant that costs more than
1359 1 instruction, force the constant into a register and return that
1360 register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */
1363 avoid_expensive_constant (machine_mode mode
, optab binoptab
,
1364 int opn
, rtx x
, bool unsignedp
)
1366 bool speed
= optimize_insn_for_speed_p ();
1368 if (mode
!= VOIDmode
1371 && (rtx_cost (x
, optab_to_code (binoptab
), opn
, speed
)
1372 > set_src_cost (x
, speed
)))
1374 if (CONST_INT_P (x
))
1376 HOST_WIDE_INT intval
= trunc_int_for_mode (INTVAL (x
), mode
);
1377 if (intval
!= INTVAL (x
))
1378 x
= GEN_INT (intval
);
1381 x
= convert_modes (mode
, VOIDmode
, x
, unsignedp
);
1382 x
= force_reg (mode
, x
);
1387 /* Helper function for expand_binop: handle the case where there
1388 is an insn that directly implements the indicated operation.
1389 Returns null if this is not possible. */
1391 expand_binop_directly (machine_mode mode
, optab binoptab
,
1393 rtx target
, int unsignedp
, enum optab_methods methods
,
1396 machine_mode from_mode
= widened_mode (mode
, op0
, op1
);
1397 enum insn_code icode
= find_widening_optab_handler (binoptab
, mode
,
1399 machine_mode xmode0
= insn_data
[(int) icode
].operand
[1].mode
;
1400 machine_mode xmode1
= insn_data
[(int) icode
].operand
[2].mode
;
1401 machine_mode mode0
, mode1
, tmp_mode
;
1402 struct expand_operand ops
[3];
1405 rtx xop0
= op0
, xop1
= op1
;
1407 /* If it is a commutative operator and the modes would match
1408 if we would swap the operands, we can save the conversions. */
1409 commutative_p
= commutative_optab_p (binoptab
);
1411 && GET_MODE (xop0
) != xmode0
&& GET_MODE (xop1
) != xmode1
1412 && GET_MODE (xop0
) == xmode1
&& GET_MODE (xop1
) == xmode1
)
1413 std::swap (xop0
, xop1
);
1415 /* If we are optimizing, force expensive constants into a register. */
1416 xop0
= avoid_expensive_constant (xmode0
, binoptab
, 0, xop0
, unsignedp
);
1417 if (!shift_optab_p (binoptab
))
1418 xop1
= avoid_expensive_constant (xmode1
, binoptab
, 1, xop1
, unsignedp
);
1420 /* In case the insn wants input operands in modes different from
1421 those of the actual operands, convert the operands. It would
1422 seem that we don't need to convert CONST_INTs, but we do, so
1423 that they're properly zero-extended, sign-extended or truncated
1426 mode0
= GET_MODE (xop0
) != VOIDmode
? GET_MODE (xop0
) : mode
;
1427 if (xmode0
!= VOIDmode
&& xmode0
!= mode0
)
1429 xop0
= convert_modes (xmode0
, mode0
, xop0
, unsignedp
);
1433 mode1
= GET_MODE (xop1
) != VOIDmode
? GET_MODE (xop1
) : mode
;
1434 if (xmode1
!= VOIDmode
&& xmode1
!= mode1
)
1436 xop1
= convert_modes (xmode1
, mode1
, xop1
, unsignedp
);
1440 /* If operation is commutative,
1441 try to make the first operand a register.
1442 Even better, try to make it the same as the target.
1443 Also try to make the last operand a constant. */
1445 && swap_commutative_operands_with_target (target
, xop0
, xop1
))
1446 std::swap (xop0
, xop1
);
1448 /* Now, if insn's predicates don't allow our operands, put them into
1451 if (binoptab
== vec_pack_trunc_optab
1452 || binoptab
== vec_pack_usat_optab
1453 || binoptab
== vec_pack_ssat_optab
1454 || binoptab
== vec_pack_ufix_trunc_optab
1455 || binoptab
== vec_pack_sfix_trunc_optab
)
1457 /* The mode of the result is different then the mode of the
1459 tmp_mode
= insn_data
[(int) icode
].operand
[0].mode
;
1460 if (GET_MODE_NUNITS (tmp_mode
) != 2 * GET_MODE_NUNITS (mode
))
1462 delete_insns_since (last
);
1469 create_output_operand (&ops
[0], target
, tmp_mode
);
1470 create_input_operand (&ops
[1], xop0
, mode0
);
1471 create_input_operand (&ops
[2], xop1
, mode1
);
1472 pat
= maybe_gen_insn (icode
, 3, ops
);
1475 /* If PAT is composed of more than one insn, try to add an appropriate
1476 REG_EQUAL note to it. If we can't because TEMP conflicts with an
1477 operand, call expand_binop again, this time without a target. */
1478 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
1479 && ! add_equal_note (pat
, ops
[0].value
,
1480 optab_to_code (binoptab
),
1481 ops
[1].value
, ops
[2].value
))
1483 delete_insns_since (last
);
1484 return expand_binop (mode
, binoptab
, op0
, op1
, NULL_RTX
,
1485 unsignedp
, methods
);
1489 return ops
[0].value
;
1491 delete_insns_since (last
);
1495 /* Generate code to perform an operation specified by BINOPTAB
1496 on operands OP0 and OP1, with result having machine-mode MODE.
1498 UNSIGNEDP is for the case where we have to widen the operands
1499 to perform the operation. It says to use zero-extension.
1501 If TARGET is nonzero, the value
1502 is generated there, if it is convenient to do so.
1503 In all cases an rtx is returned for the locus of the value;
1504 this may or may not be TARGET. */
1507 expand_binop (machine_mode mode
, optab binoptab
, rtx op0
, rtx op1
,
1508 rtx target
, int unsignedp
, enum optab_methods methods
)
1510 enum optab_methods next_methods
1511 = (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
1512 ? OPTAB_WIDEN
: methods
);
1513 enum mode_class mclass
;
1514 machine_mode wider_mode
;
1517 rtx_insn
*entry_last
= get_last_insn ();
1520 mclass
= GET_MODE_CLASS (mode
);
1522 /* If subtracting an integer constant, convert this into an addition of
1523 the negated constant. */
1525 if (binoptab
== sub_optab
&& CONST_INT_P (op1
))
1527 op1
= negate_rtx (mode
, op1
);
1528 binoptab
= add_optab
;
1531 /* Record where to delete back to if we backtrack. */
1532 last
= get_last_insn ();
1534 /* If we can do it with a three-operand insn, do so. */
1536 if (methods
!= OPTAB_MUST_WIDEN
1537 && find_widening_optab_handler (binoptab
, mode
,
1538 widened_mode (mode
, op0
, op1
), 1)
1539 != CODE_FOR_nothing
)
1541 temp
= expand_binop_directly (mode
, binoptab
, op0
, op1
, target
,
1542 unsignedp
, methods
, last
);
1547 /* If we were trying to rotate, and that didn't work, try rotating
1548 the other direction before falling back to shifts and bitwise-or. */
1549 if (((binoptab
== rotl_optab
1550 && optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
1551 || (binoptab
== rotr_optab
1552 && optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
))
1553 && mclass
== MODE_INT
)
1555 optab otheroptab
= (binoptab
== rotl_optab
? rotr_optab
: rotl_optab
);
1557 unsigned int bits
= GET_MODE_PRECISION (mode
);
1559 if (CONST_INT_P (op1
))
1560 newop1
= GEN_INT (bits
- INTVAL (op1
));
1561 else if (targetm
.shift_truncation_mask (mode
) == bits
- 1)
1562 newop1
= negate_rtx (GET_MODE (op1
), op1
);
1564 newop1
= expand_binop (GET_MODE (op1
), sub_optab
,
1565 gen_int_mode (bits
, GET_MODE (op1
)), op1
,
1566 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1568 temp
= expand_binop_directly (mode
, otheroptab
, op0
, newop1
,
1569 target
, unsignedp
, methods
, last
);
1574 /* If this is a multiply, see if we can do a widening operation that
1575 takes operands of this mode and makes a wider mode. */
1577 if (binoptab
== smul_optab
1578 && GET_MODE_2XWIDER_MODE (mode
) != VOIDmode
1579 && (widening_optab_handler ((unsignedp
? umul_widen_optab
1580 : smul_widen_optab
),
1581 GET_MODE_2XWIDER_MODE (mode
), mode
)
1582 != CODE_FOR_nothing
))
1584 temp
= expand_binop (GET_MODE_2XWIDER_MODE (mode
),
1585 unsignedp
? umul_widen_optab
: smul_widen_optab
,
1586 op0
, op1
, NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
1590 if (GET_MODE_CLASS (mode
) == MODE_INT
1591 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (temp
)))
1592 return gen_lowpart (mode
, temp
);
1594 return convert_to_mode (mode
, temp
, unsignedp
);
1598 /* If this is a vector shift by a scalar, see if we can do a vector
1599 shift by a vector. If so, broadcast the scalar into a vector. */
1600 if (mclass
== MODE_VECTOR_INT
)
1602 optab otheroptab
= unknown_optab
;
1604 if (binoptab
== ashl_optab
)
1605 otheroptab
= vashl_optab
;
1606 else if (binoptab
== ashr_optab
)
1607 otheroptab
= vashr_optab
;
1608 else if (binoptab
== lshr_optab
)
1609 otheroptab
= vlshr_optab
;
1610 else if (binoptab
== rotl_optab
)
1611 otheroptab
= vrotl_optab
;
1612 else if (binoptab
== rotr_optab
)
1613 otheroptab
= vrotr_optab
;
1615 if (otheroptab
&& optab_handler (otheroptab
, mode
) != CODE_FOR_nothing
)
1617 rtx vop1
= expand_vector_broadcast (mode
, op1
);
1620 temp
= expand_binop_directly (mode
, otheroptab
, op0
, vop1
,
1621 target
, unsignedp
, methods
, last
);
1628 /* Look for a wider mode of the same class for which we think we
1629 can open-code the operation. Check for a widening multiply at the
1630 wider mode as well. */
1632 if (CLASS_HAS_WIDER_MODES_P (mclass
)
1633 && methods
!= OPTAB_DIRECT
&& methods
!= OPTAB_LIB
)
1634 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
1635 wider_mode
!= VOIDmode
;
1636 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
1638 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
1639 || (binoptab
== smul_optab
1640 && GET_MODE_WIDER_MODE (wider_mode
) != VOIDmode
1641 && (find_widening_optab_handler ((unsignedp
1643 : smul_widen_optab
),
1644 GET_MODE_WIDER_MODE (wider_mode
),
1646 != CODE_FOR_nothing
)))
1648 rtx xop0
= op0
, xop1
= op1
;
1651 /* For certain integer operations, we need not actually extend
1652 the narrow operands, as long as we will truncate
1653 the results to the same narrowness. */
1655 if ((binoptab
== ior_optab
|| binoptab
== and_optab
1656 || binoptab
== xor_optab
1657 || binoptab
== add_optab
|| binoptab
== sub_optab
1658 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
1659 && mclass
== MODE_INT
)
1662 xop0
= avoid_expensive_constant (mode
, binoptab
, 0,
1664 if (binoptab
!= ashl_optab
)
1665 xop1
= avoid_expensive_constant (mode
, binoptab
, 1,
1669 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
, no_extend
);
1671 /* The second operand of a shift must always be extended. */
1672 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
1673 no_extend
&& binoptab
!= ashl_optab
);
1675 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
1676 unsignedp
, OPTAB_DIRECT
);
1679 if (mclass
!= MODE_INT
1680 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
1683 target
= gen_reg_rtx (mode
);
1684 convert_move (target
, temp
, 0);
1688 return gen_lowpart (mode
, temp
);
1691 delete_insns_since (last
);
1695 /* If operation is commutative,
1696 try to make the first operand a register.
1697 Even better, try to make it the same as the target.
1698 Also try to make the last operand a constant. */
1699 if (commutative_optab_p (binoptab
)
1700 && swap_commutative_operands_with_target (target
, op0
, op1
))
1701 std::swap (op0
, op1
);
1703 /* These can be done a word at a time. */
1704 if ((binoptab
== and_optab
|| binoptab
== ior_optab
|| binoptab
== xor_optab
)
1705 && mclass
== MODE_INT
1706 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
1707 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1712 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1713 won't be accurate, so use a new target. */
1717 || !valid_multiword_target_p (target
))
1718 target
= gen_reg_rtx (mode
);
1722 /* Do the actual arithmetic. */
1723 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
1725 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
1726 rtx x
= expand_binop (word_mode
, binoptab
,
1727 operand_subword_force (op0
, i
, mode
),
1728 operand_subword_force (op1
, i
, mode
),
1729 target_piece
, unsignedp
, next_methods
);
1734 if (target_piece
!= x
)
1735 emit_move_insn (target_piece
, x
);
1738 insns
= get_insns ();
1741 if (i
== GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
)
1748 /* Synthesize double word shifts from single word shifts. */
1749 if ((binoptab
== lshr_optab
|| binoptab
== ashl_optab
1750 || binoptab
== ashr_optab
)
1751 && mclass
== MODE_INT
1752 && (CONST_INT_P (op1
) || optimize_insn_for_speed_p ())
1753 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
1754 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
)
1755 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
1756 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1757 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1759 unsigned HOST_WIDE_INT shift_mask
, double_shift_mask
;
1760 machine_mode op1_mode
;
1762 double_shift_mask
= targetm
.shift_truncation_mask (mode
);
1763 shift_mask
= targetm
.shift_truncation_mask (word_mode
);
1764 op1_mode
= GET_MODE (op1
) != VOIDmode
? GET_MODE (op1
) : word_mode
;
1766 /* Apply the truncation to constant shifts. */
1767 if (double_shift_mask
> 0 && CONST_INT_P (op1
))
1768 op1
= GEN_INT (INTVAL (op1
) & double_shift_mask
);
1770 if (op1
== CONST0_RTX (op1_mode
))
1773 /* Make sure that this is a combination that expand_doubleword_shift
1774 can handle. See the comments there for details. */
1775 if (double_shift_mask
== 0
1776 || (shift_mask
== BITS_PER_WORD
- 1
1777 && double_shift_mask
== BITS_PER_WORD
* 2 - 1))
1780 rtx into_target
, outof_target
;
1781 rtx into_input
, outof_input
;
1782 int left_shift
, outof_word
;
1784 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1785 won't be accurate, so use a new target. */
1789 || !valid_multiword_target_p (target
))
1790 target
= gen_reg_rtx (mode
);
1794 /* OUTOF_* is the word we are shifting bits away from, and
1795 INTO_* is the word that we are shifting bits towards, thus
1796 they differ depending on the direction of the shift and
1797 WORDS_BIG_ENDIAN. */
1799 left_shift
= binoptab
== ashl_optab
;
1800 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1802 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1803 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1805 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1806 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1808 if (expand_doubleword_shift (op1_mode
, binoptab
,
1809 outof_input
, into_input
, op1
,
1810 outof_target
, into_target
,
1811 unsignedp
, next_methods
, shift_mask
))
1813 insns
= get_insns ();
1823 /* Synthesize double word rotates from single word shifts. */
1824 if ((binoptab
== rotl_optab
|| binoptab
== rotr_optab
)
1825 && mclass
== MODE_INT
1826 && CONST_INT_P (op1
)
1827 && GET_MODE_PRECISION (mode
) == 2 * BITS_PER_WORD
1828 && optab_handler (ashl_optab
, word_mode
) != CODE_FOR_nothing
1829 && optab_handler (lshr_optab
, word_mode
) != CODE_FOR_nothing
)
1832 rtx into_target
, outof_target
;
1833 rtx into_input
, outof_input
;
1835 int shift_count
, left_shift
, outof_word
;
1837 /* If TARGET is the same as one of the operands, the REG_EQUAL note
1838 won't be accurate, so use a new target. Do this also if target is not
1839 a REG, first because having a register instead may open optimization
1840 opportunities, and second because if target and op0 happen to be MEMs
1841 designating the same location, we would risk clobbering it too early
1842 in the code sequence we generate below. */
1847 || !valid_multiword_target_p (target
))
1848 target
= gen_reg_rtx (mode
);
1852 shift_count
= INTVAL (op1
);
1854 /* OUTOF_* is the word we are shifting bits away from, and
1855 INTO_* is the word that we are shifting bits towards, thus
1856 they differ depending on the direction of the shift and
1857 WORDS_BIG_ENDIAN. */
1859 left_shift
= (binoptab
== rotl_optab
);
1860 outof_word
= left_shift
^ ! WORDS_BIG_ENDIAN
;
1862 outof_target
= operand_subword (target
, outof_word
, 1, mode
);
1863 into_target
= operand_subword (target
, 1 - outof_word
, 1, mode
);
1865 outof_input
= operand_subword_force (op0
, outof_word
, mode
);
1866 into_input
= operand_subword_force (op0
, 1 - outof_word
, mode
);
1868 if (shift_count
== BITS_PER_WORD
)
1870 /* This is just a word swap. */
1871 emit_move_insn (outof_target
, into_input
);
1872 emit_move_insn (into_target
, outof_input
);
1877 rtx into_temp1
, into_temp2
, outof_temp1
, outof_temp2
;
1878 rtx first_shift_count
, second_shift_count
;
1879 optab reverse_unsigned_shift
, unsigned_shift
;
1881 reverse_unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1882 ? lshr_optab
: ashl_optab
);
1884 unsigned_shift
= (left_shift
^ (shift_count
< BITS_PER_WORD
)
1885 ? ashl_optab
: lshr_optab
);
1887 if (shift_count
> BITS_PER_WORD
)
1889 first_shift_count
= GEN_INT (shift_count
- BITS_PER_WORD
);
1890 second_shift_count
= GEN_INT (2 * BITS_PER_WORD
- shift_count
);
1894 first_shift_count
= GEN_INT (BITS_PER_WORD
- shift_count
);
1895 second_shift_count
= GEN_INT (shift_count
);
1898 into_temp1
= expand_binop (word_mode
, unsigned_shift
,
1899 outof_input
, first_shift_count
,
1900 NULL_RTX
, unsignedp
, next_methods
);
1901 into_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1902 into_input
, second_shift_count
,
1903 NULL_RTX
, unsignedp
, next_methods
);
1905 if (into_temp1
!= 0 && into_temp2
!= 0)
1906 inter
= expand_binop (word_mode
, ior_optab
, into_temp1
, into_temp2
,
1907 into_target
, unsignedp
, next_methods
);
1911 if (inter
!= 0 && inter
!= into_target
)
1912 emit_move_insn (into_target
, inter
);
1914 outof_temp1
= expand_binop (word_mode
, unsigned_shift
,
1915 into_input
, first_shift_count
,
1916 NULL_RTX
, unsignedp
, next_methods
);
1917 outof_temp2
= expand_binop (word_mode
, reverse_unsigned_shift
,
1918 outof_input
, second_shift_count
,
1919 NULL_RTX
, unsignedp
, next_methods
);
1921 if (inter
!= 0 && outof_temp1
!= 0 && outof_temp2
!= 0)
1922 inter
= expand_binop (word_mode
, ior_optab
,
1923 outof_temp1
, outof_temp2
,
1924 outof_target
, unsignedp
, next_methods
);
1926 if (inter
!= 0 && inter
!= outof_target
)
1927 emit_move_insn (outof_target
, inter
);
1930 insns
= get_insns ();
1940 /* These can be done a word at a time by propagating carries. */
1941 if ((binoptab
== add_optab
|| binoptab
== sub_optab
)
1942 && mclass
== MODE_INT
1943 && GET_MODE_SIZE (mode
) >= 2 * UNITS_PER_WORD
1944 && optab_handler (binoptab
, word_mode
) != CODE_FOR_nothing
)
1947 optab otheroptab
= binoptab
== add_optab
? sub_optab
: add_optab
;
1948 const unsigned int nwords
= GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
;
1949 rtx carry_in
= NULL_RTX
, carry_out
= NULL_RTX
;
1950 rtx xop0
, xop1
, xtarget
;
1952 /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG
1953 value is one of those, use it. Otherwise, use 1 since it is the
1954 one easiest to get. */
1955 #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1
1956 int normalizep
= STORE_FLAG_VALUE
;
1961 /* Prepare the operands. */
1962 xop0
= force_reg (mode
, op0
);
1963 xop1
= force_reg (mode
, op1
);
1965 xtarget
= gen_reg_rtx (mode
);
1967 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1970 /* Indicate for flow that the entire target reg is being set. */
1972 emit_clobber (xtarget
);
1974 /* Do the actual arithmetic. */
1975 for (i
= 0; i
< nwords
; i
++)
1977 int index
= (WORDS_BIG_ENDIAN
? nwords
- i
- 1 : i
);
1978 rtx target_piece
= operand_subword (xtarget
, index
, 1, mode
);
1979 rtx op0_piece
= operand_subword_force (xop0
, index
, mode
);
1980 rtx op1_piece
= operand_subword_force (xop1
, index
, mode
);
1983 /* Main add/subtract of the input operands. */
1984 x
= expand_binop (word_mode
, binoptab
,
1985 op0_piece
, op1_piece
,
1986 target_piece
, unsignedp
, next_methods
);
1992 /* Store carry from main add/subtract. */
1993 carry_out
= gen_reg_rtx (word_mode
);
1994 carry_out
= emit_store_flag_force (carry_out
,
1995 (binoptab
== add_optab
1998 word_mode
, 1, normalizep
);
2005 /* Add/subtract previous carry to main result. */
2006 newx
= expand_binop (word_mode
,
2007 normalizep
== 1 ? binoptab
: otheroptab
,
2009 NULL_RTX
, 1, next_methods
);
2013 /* Get out carry from adding/subtracting carry in. */
2014 rtx carry_tmp
= gen_reg_rtx (word_mode
);
2015 carry_tmp
= emit_store_flag_force (carry_tmp
,
2016 (binoptab
== add_optab
2019 word_mode
, 1, normalizep
);
2021 /* Logical-ior the two poss. carry together. */
2022 carry_out
= expand_binop (word_mode
, ior_optab
,
2023 carry_out
, carry_tmp
,
2024 carry_out
, 0, next_methods
);
2028 emit_move_insn (target_piece
, newx
);
2032 if (x
!= target_piece
)
2033 emit_move_insn (target_piece
, x
);
2036 carry_in
= carry_out
;
2039 if (i
== GET_MODE_BITSIZE (mode
) / (unsigned) BITS_PER_WORD
)
2041 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
2042 || ! rtx_equal_p (target
, xtarget
))
2044 rtx_insn
*temp
= emit_move_insn (target
, xtarget
);
2046 set_dst_reg_note (temp
, REG_EQUAL
,
2047 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2048 mode
, copy_rtx (xop0
),
2059 delete_insns_since (last
);
2062 /* Attempt to synthesize double word multiplies using a sequence of word
2063 mode multiplications. We first attempt to generate a sequence using a
2064 more efficient unsigned widening multiply, and if that fails we then
2065 try using a signed widening multiply. */
2067 if (binoptab
== smul_optab
2068 && mclass
== MODE_INT
2069 && GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
2070 && optab_handler (smul_optab
, word_mode
) != CODE_FOR_nothing
2071 && optab_handler (add_optab
, word_mode
) != CODE_FOR_nothing
)
2073 rtx product
= NULL_RTX
;
2074 if (widening_optab_handler (umul_widen_optab
, mode
, word_mode
)
2075 != CODE_FOR_nothing
)
2077 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2080 delete_insns_since (last
);
2083 if (product
== NULL_RTX
2084 && widening_optab_handler (smul_widen_optab
, mode
, word_mode
)
2085 != CODE_FOR_nothing
)
2087 product
= expand_doubleword_mult (mode
, op0
, op1
, target
,
2090 delete_insns_since (last
);
2093 if (product
!= NULL_RTX
)
2095 if (optab_handler (mov_optab
, mode
) != CODE_FOR_nothing
)
2097 temp
= emit_move_insn (target
? target
: product
, product
);
2098 set_dst_reg_note (temp
,
2100 gen_rtx_fmt_ee (MULT
, mode
,
2103 target
? target
: product
);
2109 /* It can't be open-coded in this mode.
2110 Use a library call if one is available and caller says that's ok. */
2112 libfunc
= optab_libfunc (binoptab
, mode
);
2114 && (methods
== OPTAB_LIB
|| methods
== OPTAB_LIB_WIDEN
))
2118 machine_mode op1_mode
= mode
;
2123 if (shift_optab_p (binoptab
))
2125 op1_mode
= targetm
.libgcc_shift_count_mode ();
2126 /* Specify unsigned here,
2127 since negative shift counts are meaningless. */
2128 op1x
= convert_to_mode (op1_mode
, op1
, 1);
2131 if (GET_MODE (op0
) != VOIDmode
2132 && GET_MODE (op0
) != mode
)
2133 op0
= convert_to_mode (mode
, op0
, unsignedp
);
2135 /* Pass 1 for NO_QUEUE so we don't lose any increments
2136 if the libcall is cse'd or moved. */
2137 value
= emit_library_call_value (libfunc
,
2138 NULL_RTX
, LCT_CONST
, mode
, 2,
2139 op0
, mode
, op1x
, op1_mode
);
2141 insns
= get_insns ();
2144 target
= gen_reg_rtx (mode
);
2145 emit_libcall_block_1 (insns
, target
, value
,
2146 gen_rtx_fmt_ee (optab_to_code (binoptab
),
2148 trapv_binoptab_p (binoptab
));
2153 delete_insns_since (last
);
2155 /* It can't be done in this mode. Can we do it in a wider mode? */
2157 if (! (methods
== OPTAB_WIDEN
|| methods
== OPTAB_LIB_WIDEN
2158 || methods
== OPTAB_MUST_WIDEN
))
2160 /* Caller says, don't even try. */
2161 delete_insns_since (entry_last
);
2165 /* Compute the value of METHODS to pass to recursive calls.
2166 Don't allow widening to be tried recursively. */
2168 methods
= (methods
== OPTAB_LIB_WIDEN
? OPTAB_LIB
: OPTAB_DIRECT
);
2170 /* Look for a wider mode of the same class for which it appears we can do
2173 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2175 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2176 wider_mode
!= VOIDmode
;
2177 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2179 if (find_widening_optab_handler (binoptab
, wider_mode
, mode
, 1)
2181 || (methods
== OPTAB_LIB
2182 && optab_libfunc (binoptab
, wider_mode
)))
2184 rtx xop0
= op0
, xop1
= op1
;
2187 /* For certain integer operations, we need not actually extend
2188 the narrow operands, as long as we will truncate
2189 the results to the same narrowness. */
2191 if ((binoptab
== ior_optab
|| binoptab
== and_optab
2192 || binoptab
== xor_optab
2193 || binoptab
== add_optab
|| binoptab
== sub_optab
2194 || binoptab
== smul_optab
|| binoptab
== ashl_optab
)
2195 && mclass
== MODE_INT
)
2198 xop0
= widen_operand (xop0
, wider_mode
, mode
,
2199 unsignedp
, no_extend
);
2201 /* The second operand of a shift must always be extended. */
2202 xop1
= widen_operand (xop1
, wider_mode
, mode
, unsignedp
,
2203 no_extend
&& binoptab
!= ashl_optab
);
2205 temp
= expand_binop (wider_mode
, binoptab
, xop0
, xop1
, NULL_RTX
,
2206 unsignedp
, methods
);
2209 if (mclass
!= MODE_INT
2210 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
2213 target
= gen_reg_rtx (mode
);
2214 convert_move (target
, temp
, 0);
2218 return gen_lowpart (mode
, temp
);
2221 delete_insns_since (last
);
2226 delete_insns_since (entry_last
);
2230 /* Expand a binary operator which has both signed and unsigned forms.
2231 UOPTAB is the optab for unsigned operations, and SOPTAB is for
2234 If we widen unsigned operands, we may use a signed wider operation instead
2235 of an unsigned wider operation, since the result would be the same. */
2238 sign_expand_binop (machine_mode mode
, optab uoptab
, optab soptab
,
2239 rtx op0
, rtx op1
, rtx target
, int unsignedp
,
2240 enum optab_methods methods
)
2243 optab direct_optab
= unsignedp
? uoptab
: soptab
;
2246 /* Do it without widening, if possible. */
2247 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2248 unsignedp
, OPTAB_DIRECT
);
2249 if (temp
|| methods
== OPTAB_DIRECT
)
2252 /* Try widening to a signed int. Disable any direct use of any
2253 signed insn in the current mode. */
2254 save_enable
= swap_optab_enable (soptab
, mode
, false);
2256 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2257 unsignedp
, OPTAB_WIDEN
);
2259 /* For unsigned operands, try widening to an unsigned int. */
2260 if (!temp
&& unsignedp
)
2261 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2262 unsignedp
, OPTAB_WIDEN
);
2263 if (temp
|| methods
== OPTAB_WIDEN
)
2266 /* Use the right width libcall if that exists. */
2267 temp
= expand_binop (mode
, direct_optab
, op0
, op1
, target
,
2268 unsignedp
, OPTAB_LIB
);
2269 if (temp
|| methods
== OPTAB_LIB
)
2272 /* Must widen and use a libcall, use either signed or unsigned. */
2273 temp
= expand_binop (mode
, soptab
, op0
, op1
, target
,
2274 unsignedp
, methods
);
2275 if (!temp
&& unsignedp
)
2276 temp
= expand_binop (mode
, uoptab
, op0
, op1
, target
,
2277 unsignedp
, methods
);
2280 /* Undo the fiddling above. */
2282 swap_optab_enable (soptab
, mode
, true);
2286 /* Generate code to perform an operation specified by UNOPPTAB
2287 on operand OP0, with two results to TARG0 and TARG1.
2288 We assume that the order of the operands for the instruction
2289 is TARG0, TARG1, OP0.
2291 Either TARG0 or TARG1 may be zero, but what that means is that
2292 the result is not actually wanted. We will generate it into
2293 a dummy pseudo-reg and discard it. They may not both be zero.
2295 Returns 1 if this operation can be performed; 0 if not. */
2298 expand_twoval_unop (optab unoptab
, rtx op0
, rtx targ0
, rtx targ1
,
2301 machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2302 enum mode_class mclass
;
2303 machine_mode wider_mode
;
2304 rtx_insn
*entry_last
= get_last_insn ();
2307 mclass
= GET_MODE_CLASS (mode
);
2310 targ0
= gen_reg_rtx (mode
);
2312 targ1
= gen_reg_rtx (mode
);
2314 /* Record where to go back to if we fail. */
2315 last
= get_last_insn ();
2317 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2319 struct expand_operand ops
[3];
2320 enum insn_code icode
= optab_handler (unoptab
, mode
);
2322 create_fixed_operand (&ops
[0], targ0
);
2323 create_fixed_operand (&ops
[1], targ1
);
2324 create_convert_operand_from (&ops
[2], op0
, mode
, unsignedp
);
2325 if (maybe_expand_insn (icode
, 3, ops
))
2329 /* It can't be done in this mode. Can we do it in a wider mode? */
2331 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2333 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2334 wider_mode
!= VOIDmode
;
2335 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2337 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2339 rtx t0
= gen_reg_rtx (wider_mode
);
2340 rtx t1
= gen_reg_rtx (wider_mode
);
2341 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2343 if (expand_twoval_unop (unoptab
, cop0
, t0
, t1
, unsignedp
))
2345 convert_move (targ0
, t0
, unsignedp
);
2346 convert_move (targ1
, t1
, unsignedp
);
2350 delete_insns_since (last
);
2355 delete_insns_since (entry_last
);
2359 /* Generate code to perform an operation specified by BINOPTAB
2360 on operands OP0 and OP1, with two results to TARG1 and TARG2.
2361 We assume that the order of the operands for the instruction
2362 is TARG0, OP0, OP1, TARG1, which would fit a pattern like
2363 [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))].
2365 Either TARG0 or TARG1 may be zero, but what that means is that
2366 the result is not actually wanted. We will generate it into
2367 a dummy pseudo-reg and discard it. They may not both be zero.
2369 Returns 1 if this operation can be performed; 0 if not. */
2372 expand_twoval_binop (optab binoptab
, rtx op0
, rtx op1
, rtx targ0
, rtx targ1
,
2375 machine_mode mode
= GET_MODE (targ0
? targ0
: targ1
);
2376 enum mode_class mclass
;
2377 machine_mode wider_mode
;
2378 rtx_insn
*entry_last
= get_last_insn ();
2381 mclass
= GET_MODE_CLASS (mode
);
2384 targ0
= gen_reg_rtx (mode
);
2386 targ1
= gen_reg_rtx (mode
);
2388 /* Record where to go back to if we fail. */
2389 last
= get_last_insn ();
2391 if (optab_handler (binoptab
, mode
) != CODE_FOR_nothing
)
2393 struct expand_operand ops
[4];
2394 enum insn_code icode
= optab_handler (binoptab
, mode
);
2395 machine_mode mode0
= insn_data
[icode
].operand
[1].mode
;
2396 machine_mode mode1
= insn_data
[icode
].operand
[2].mode
;
2397 rtx xop0
= op0
, xop1
= op1
;
2399 /* If we are optimizing, force expensive constants into a register. */
2400 xop0
= avoid_expensive_constant (mode0
, binoptab
, 0, xop0
, unsignedp
);
2401 xop1
= avoid_expensive_constant (mode1
, binoptab
, 1, xop1
, unsignedp
);
2403 create_fixed_operand (&ops
[0], targ0
);
2404 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2405 create_convert_operand_from (&ops
[2], op1
, mode
, unsignedp
);
2406 create_fixed_operand (&ops
[3], targ1
);
2407 if (maybe_expand_insn (icode
, 4, ops
))
2409 delete_insns_since (last
);
2412 /* It can't be done in this mode. Can we do it in a wider mode? */
2414 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2416 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2417 wider_mode
!= VOIDmode
;
2418 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2420 if (optab_handler (binoptab
, wider_mode
) != CODE_FOR_nothing
)
2422 rtx t0
= gen_reg_rtx (wider_mode
);
2423 rtx t1
= gen_reg_rtx (wider_mode
);
2424 rtx cop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
2425 rtx cop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
2427 if (expand_twoval_binop (binoptab
, cop0
, cop1
,
2430 convert_move (targ0
, t0
, unsignedp
);
2431 convert_move (targ1
, t1
, unsignedp
);
2435 delete_insns_since (last
);
2440 delete_insns_since (entry_last
);
2444 /* Expand the two-valued library call indicated by BINOPTAB, but
2445 preserve only one of the values. If TARG0 is non-NULL, the first
2446 value is placed into TARG0; otherwise the second value is placed
2447 into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The
2448 value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1).
2449 This routine assumes that the value returned by the library call is
2450 as if the return value was of an integral mode twice as wide as the
2451 mode of OP0. Returns 1 if the call was successful. */
2454 expand_twoval_binop_libfunc (optab binoptab
, rtx op0
, rtx op1
,
2455 rtx targ0
, rtx targ1
, enum rtx_code code
)
2458 machine_mode libval_mode
;
2463 /* Exactly one of TARG0 or TARG1 should be non-NULL. */
2464 gcc_assert (!targ0
!= !targ1
);
2466 mode
= GET_MODE (op0
);
2467 libfunc
= optab_libfunc (binoptab
, mode
);
2471 /* The value returned by the library function will have twice as
2472 many bits as the nominal MODE. */
2473 libval_mode
= smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode
),
2476 libval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
2480 /* Get the part of VAL containing the value that we want. */
2481 libval
= simplify_gen_subreg (mode
, libval
, libval_mode
,
2482 targ0
? 0 : GET_MODE_SIZE (mode
));
2483 insns
= get_insns ();
2485 /* Move the into the desired location. */
2486 emit_libcall_block (insns
, targ0
? targ0
: targ1
, libval
,
2487 gen_rtx_fmt_ee (code
, mode
, op0
, op1
));
2493 /* Wrapper around expand_unop which takes an rtx code to specify
2494 the operation to perform, not an optab pointer. All other
2495 arguments are the same. */
2497 expand_simple_unop (machine_mode mode
, enum rtx_code code
, rtx op0
,
2498 rtx target
, int unsignedp
)
2500 optab unop
= code_to_optab (code
);
2503 return expand_unop (mode
, unop
, op0
, target
, unsignedp
);
2509 (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)).
2511 A similar operation can be used for clrsb. UNOPTAB says which operation
2512 we are trying to expand. */
2514 widen_leading (machine_mode mode
, rtx op0
, rtx target
, optab unoptab
)
2516 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2517 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2519 machine_mode wider_mode
;
2520 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2521 wider_mode
!= VOIDmode
;
2522 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2524 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
2529 last
= get_last_insn ();
2532 target
= gen_reg_rtx (mode
);
2533 xop0
= widen_operand (op0
, wider_mode
, mode
,
2534 unoptab
!= clrsb_optab
, false);
2535 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
2536 unoptab
!= clrsb_optab
);
2539 (wider_mode
, sub_optab
, temp
,
2540 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
2541 - GET_MODE_PRECISION (mode
),
2543 target
, true, OPTAB_DIRECT
);
2545 delete_insns_since (last
);
2554 /* Try calculating clz of a double-word quantity as two clz's of word-sized
2555 quantities, choosing which based on whether the high word is nonzero. */
2557 expand_doubleword_clz (machine_mode mode
, rtx op0
, rtx target
)
2559 rtx xop0
= force_reg (mode
, op0
);
2560 rtx subhi
= gen_highpart (word_mode
, xop0
);
2561 rtx sublo
= gen_lowpart (word_mode
, xop0
);
2562 rtx_code_label
*hi0_label
= gen_label_rtx ();
2563 rtx_code_label
*after_label
= gen_label_rtx ();
2567 /* If we were not given a target, use a word_mode register, not a
2568 'mode' register. The result will fit, and nobody is expecting
2569 anything bigger (the return type of __builtin_clz* is int). */
2571 target
= gen_reg_rtx (word_mode
);
2573 /* In any case, write to a word_mode scratch in both branches of the
2574 conditional, so we can ensure there is a single move insn setting
2575 'target' to tag a REG_EQUAL note on. */
2576 result
= gen_reg_rtx (word_mode
);
2580 /* If the high word is not equal to zero,
2581 then clz of the full value is clz of the high word. */
2582 emit_cmp_and_jump_insns (subhi
, CONST0_RTX (word_mode
), EQ
, 0,
2583 word_mode
, true, hi0_label
);
2585 temp
= expand_unop_direct (word_mode
, clz_optab
, subhi
, result
, true);
2590 convert_move (result
, temp
, true);
2592 emit_jump_insn (gen_jump (after_label
));
2595 /* Else clz of the full value is clz of the low word plus the number
2596 of bits in the high word. */
2597 emit_label (hi0_label
);
2599 temp
= expand_unop_direct (word_mode
, clz_optab
, sublo
, 0, true);
2602 temp
= expand_binop (word_mode
, add_optab
, temp
,
2603 gen_int_mode (GET_MODE_BITSIZE (word_mode
), word_mode
),
2604 result
, true, OPTAB_DIRECT
);
2608 convert_move (result
, temp
, true);
2610 emit_label (after_label
);
2611 convert_move (target
, result
, true);
2616 add_equal_note (seq
, target
, CLZ
, xop0
, 0);
2628 (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */
2630 widen_bswap (machine_mode mode
, rtx op0
, rtx target
)
2632 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2633 machine_mode wider_mode
;
2637 if (!CLASS_HAS_WIDER_MODES_P (mclass
))
2640 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
2641 wider_mode
!= VOIDmode
;
2642 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2643 if (optab_handler (bswap_optab
, wider_mode
) != CODE_FOR_nothing
)
2648 last
= get_last_insn ();
2650 x
= widen_operand (op0
, wider_mode
, mode
, true, true);
2651 x
= expand_unop (wider_mode
, bswap_optab
, x
, NULL_RTX
, true);
2653 gcc_assert (GET_MODE_PRECISION (wider_mode
) == GET_MODE_BITSIZE (wider_mode
)
2654 && GET_MODE_PRECISION (mode
) == GET_MODE_BITSIZE (mode
));
2656 x
= expand_shift (RSHIFT_EXPR
, wider_mode
, x
,
2657 GET_MODE_BITSIZE (wider_mode
)
2658 - GET_MODE_BITSIZE (mode
),
2664 target
= gen_reg_rtx (mode
);
2665 emit_move_insn (target
, gen_lowpart (mode
, x
));
2668 delete_insns_since (last
);
2673 /* Try calculating bswap as two bswaps of two word-sized operands. */
2676 expand_doubleword_bswap (machine_mode mode
, rtx op
, rtx target
)
2680 t1
= expand_unop (word_mode
, bswap_optab
,
2681 operand_subword_force (op
, 0, mode
), NULL_RTX
, true);
2682 t0
= expand_unop (word_mode
, bswap_optab
,
2683 operand_subword_force (op
, 1, mode
), NULL_RTX
, true);
2685 if (target
== 0 || !valid_multiword_target_p (target
))
2686 target
= gen_reg_rtx (mode
);
2688 emit_clobber (target
);
2689 emit_move_insn (operand_subword (target
, 0, 1, mode
), t0
);
2690 emit_move_insn (operand_subword (target
, 1, 1, mode
), t1
);
2695 /* Try calculating (parity x) as (and (popcount x) 1), where
2696 popcount can also be done in a wider mode. */
2698 expand_parity (machine_mode mode
, rtx op0
, rtx target
)
2700 enum mode_class mclass
= GET_MODE_CLASS (mode
);
2701 if (CLASS_HAS_WIDER_MODES_P (mclass
))
2703 machine_mode wider_mode
;
2704 for (wider_mode
= mode
; wider_mode
!= VOIDmode
;
2705 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
2707 if (optab_handler (popcount_optab
, wider_mode
) != CODE_FOR_nothing
)
2712 last
= get_last_insn ();
2715 target
= gen_reg_rtx (mode
);
2716 xop0
= widen_operand (op0
, wider_mode
, mode
, true, false);
2717 temp
= expand_unop (wider_mode
, popcount_optab
, xop0
, NULL_RTX
,
2720 temp
= expand_binop (wider_mode
, and_optab
, temp
, const1_rtx
,
2721 target
, true, OPTAB_DIRECT
);
2723 delete_insns_since (last
);
2732 /* Try calculating ctz(x) as K - clz(x & -x) ,
2733 where K is GET_MODE_PRECISION(mode) - 1.
2735 Both __builtin_ctz and __builtin_clz are undefined at zero, so we
2736 don't have to worry about what the hardware does in that case. (If
2737 the clz instruction produces the usual value at 0, which is K, the
2738 result of this code sequence will be -1; expand_ffs, below, relies
2739 on this. It might be nice to have it be K instead, for consistency
2740 with the (very few) processors that provide a ctz with a defined
2741 value, but that would take one more instruction, and it would be
2742 less convenient for expand_ffs anyway. */
2745 expand_ctz (machine_mode mode
, rtx op0
, rtx target
)
2750 if (optab_handler (clz_optab
, mode
) == CODE_FOR_nothing
)
2755 temp
= expand_unop_direct (mode
, neg_optab
, op0
, NULL_RTX
, true);
2757 temp
= expand_binop (mode
, and_optab
, op0
, temp
, NULL_RTX
,
2758 true, OPTAB_DIRECT
);
2760 temp
= expand_unop_direct (mode
, clz_optab
, temp
, NULL_RTX
, true);
2762 temp
= expand_binop (mode
, sub_optab
,
2763 gen_int_mode (GET_MODE_PRECISION (mode
) - 1, mode
),
2765 true, OPTAB_DIRECT
);
2775 add_equal_note (seq
, temp
, CTZ
, op0
, 0);
2781 /* Try calculating ffs(x) using ctz(x) if we have that instruction, or
2782 else with the sequence used by expand_clz.
2784 The ffs builtin promises to return zero for a zero value and ctz/clz
2785 may have an undefined value in that case. If they do not give us a
2786 convenient value, we have to generate a test and branch. */
2788 expand_ffs (machine_mode mode
, rtx op0
, rtx target
)
2790 HOST_WIDE_INT val
= 0;
2791 bool defined_at_zero
= false;
2795 if (optab_handler (ctz_optab
, mode
) != CODE_FOR_nothing
)
2799 temp
= expand_unop_direct (mode
, ctz_optab
, op0
, 0, true);
2803 defined_at_zero
= (CTZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2);
2805 else if (optab_handler (clz_optab
, mode
) != CODE_FOR_nothing
)
2808 temp
= expand_ctz (mode
, op0
, 0);
2812 if (CLZ_DEFINED_VALUE_AT_ZERO (mode
, val
) == 2)
2814 defined_at_zero
= true;
2815 val
= (GET_MODE_PRECISION (mode
) - 1) - val
;
2821 if (defined_at_zero
&& val
== -1)
2822 /* No correction needed at zero. */;
2825 /* We don't try to do anything clever with the situation found
2826 on some processors (eg Alpha) where ctz(0:mode) ==
2827 bitsize(mode). If someone can think of a way to send N to -1
2828 and leave alone all values in the range 0..N-1 (where N is a
2829 power of two), cheaper than this test-and-branch, please add it.
2831 The test-and-branch is done after the operation itself, in case
2832 the operation sets condition codes that can be recycled for this.
2833 (This is true on i386, for instance.) */
2835 rtx_code_label
*nonzero_label
= gen_label_rtx ();
2836 emit_cmp_and_jump_insns (op0
, CONST0_RTX (mode
), NE
, 0,
2837 mode
, true, nonzero_label
);
2839 convert_move (temp
, GEN_INT (-1), false);
2840 emit_label (nonzero_label
);
2843 /* temp now has a value in the range -1..bitsize-1. ffs is supposed
2844 to produce a value in the range 0..bitsize. */
2845 temp
= expand_binop (mode
, add_optab
, temp
, gen_int_mode (1, mode
),
2846 target
, false, OPTAB_DIRECT
);
2853 add_equal_note (seq
, temp
, FFS
, op0
, 0);
2862 /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain
2863 conditions, VAL may already be a SUBREG against which we cannot generate
2864 a further SUBREG. In this case, we expect forcing the value into a
2865 register will work around the situation. */
2868 lowpart_subreg_maybe_copy (machine_mode omode
, rtx val
,
2872 ret
= lowpart_subreg (omode
, val
, imode
);
2875 val
= force_reg (imode
, val
);
2876 ret
= lowpart_subreg (omode
, val
, imode
);
2877 gcc_assert (ret
!= NULL
);
2882 /* Expand a floating point absolute value or negation operation via a
2883 logical operation on the sign bit. */
2886 expand_absneg_bit (enum rtx_code code
, machine_mode mode
,
2887 rtx op0
, rtx target
)
2889 const struct real_format
*fmt
;
2890 int bitpos
, word
, nwords
, i
;
2895 /* The format has to have a simple sign bit. */
2896 fmt
= REAL_MODE_FORMAT (mode
);
2900 bitpos
= fmt
->signbit_rw
;
2904 /* Don't create negative zeros if the format doesn't support them. */
2905 if (code
== NEG
&& !fmt
->has_signed_zero
)
2908 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
2910 imode
= int_mode_for_mode (mode
);
2911 if (imode
== BLKmode
)
2920 if (FLOAT_WORDS_BIG_ENDIAN
)
2921 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
2923 word
= bitpos
/ BITS_PER_WORD
;
2924 bitpos
= bitpos
% BITS_PER_WORD
;
2925 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
2928 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
2934 || (nwords
> 1 && !valid_multiword_target_p (target
)))
2935 target
= gen_reg_rtx (mode
);
2941 for (i
= 0; i
< nwords
; ++i
)
2943 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
2944 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
2948 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2950 immed_wide_int_const (mask
, imode
),
2951 targ_piece
, 1, OPTAB_LIB_WIDEN
);
2952 if (temp
!= targ_piece
)
2953 emit_move_insn (targ_piece
, temp
);
2956 emit_move_insn (targ_piece
, op0_piece
);
2959 insns
= get_insns ();
2966 temp
= expand_binop (imode
, code
== ABS
? and_optab
: xor_optab
,
2967 gen_lowpart (imode
, op0
),
2968 immed_wide_int_const (mask
, imode
),
2969 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
2970 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
2972 set_dst_reg_note (get_last_insn (), REG_EQUAL
,
2973 gen_rtx_fmt_e (code
, mode
, copy_rtx (op0
)),
2980 /* As expand_unop, but will fail rather than attempt the operation in a
2981 different mode or with a libcall. */
2983 expand_unop_direct (machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
2986 if (optab_handler (unoptab
, mode
) != CODE_FOR_nothing
)
2988 struct expand_operand ops
[2];
2989 enum insn_code icode
= optab_handler (unoptab
, mode
);
2990 rtx_insn
*last
= get_last_insn ();
2993 create_output_operand (&ops
[0], target
, mode
);
2994 create_convert_operand_from (&ops
[1], op0
, mode
, unsignedp
);
2995 pat
= maybe_gen_insn (icode
, 2, ops
);
2998 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
2999 && ! add_equal_note (pat
, ops
[0].value
,
3000 optab_to_code (unoptab
),
3001 ops
[1].value
, NULL_RTX
))
3003 delete_insns_since (last
);
3004 return expand_unop (mode
, unoptab
, op0
, NULL_RTX
, unsignedp
);
3009 return ops
[0].value
;
3015 /* Generate code to perform an operation specified by UNOPTAB
3016 on operand OP0, with result having machine-mode MODE.
3018 UNSIGNEDP is for the case where we have to widen the operands
3019 to perform the operation. It says to use zero-extension.
3021 If TARGET is nonzero, the value
3022 is generated there, if it is convenient to do so.
3023 In all cases an rtx is returned for the locus of the value;
3024 this may or may not be TARGET. */
3027 expand_unop (machine_mode mode
, optab unoptab
, rtx op0
, rtx target
,
3030 enum mode_class mclass
= GET_MODE_CLASS (mode
);
3031 machine_mode wider_mode
;
3035 temp
= expand_unop_direct (mode
, unoptab
, op0
, target
, unsignedp
);
3039 /* It can't be done in this mode. Can we open-code it in a wider mode? */
3041 /* Widening (or narrowing) clz needs special treatment. */
3042 if (unoptab
== clz_optab
)
3044 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3048 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3049 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3051 temp
= expand_doubleword_clz (mode
, op0
, target
);
3059 if (unoptab
== clrsb_optab
)
3061 temp
= widen_leading (mode
, op0
, target
, unoptab
);
3067 /* Widening (or narrowing) bswap needs special treatment. */
3068 if (unoptab
== bswap_optab
)
3070 /* HImode is special because in this mode BSWAP is equivalent to ROTATE
3071 or ROTATERT. First try these directly; if this fails, then try the
3072 obvious pair of shifts with allowed widening, as this will probably
3073 be always more efficient than the other fallback methods. */
3079 if (optab_handler (rotl_optab
, mode
) != CODE_FOR_nothing
)
3081 temp
= expand_binop (mode
, rotl_optab
, op0
, GEN_INT (8), target
,
3082 unsignedp
, OPTAB_DIRECT
);
3087 if (optab_handler (rotr_optab
, mode
) != CODE_FOR_nothing
)
3089 temp
= expand_binop (mode
, rotr_optab
, op0
, GEN_INT (8), target
,
3090 unsignedp
, OPTAB_DIRECT
);
3095 last
= get_last_insn ();
3097 temp1
= expand_binop (mode
, ashl_optab
, op0
, GEN_INT (8), NULL_RTX
,
3098 unsignedp
, OPTAB_WIDEN
);
3099 temp2
= expand_binop (mode
, lshr_optab
, op0
, GEN_INT (8), NULL_RTX
,
3100 unsignedp
, OPTAB_WIDEN
);
3103 temp
= expand_binop (mode
, ior_optab
, temp1
, temp2
, target
,
3104 unsignedp
, OPTAB_WIDEN
);
3109 delete_insns_since (last
);
3112 temp
= widen_bswap (mode
, op0
, target
);
3116 if (GET_MODE_SIZE (mode
) == 2 * UNITS_PER_WORD
3117 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3119 temp
= expand_doubleword_bswap (mode
, op0
, target
);
3127 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3128 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3129 wider_mode
!= VOIDmode
;
3130 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3132 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
)
3135 rtx_insn
*last
= get_last_insn ();
3137 /* For certain operations, we need not actually extend
3138 the narrow operand, as long as we will truncate the
3139 results to the same narrowness. */
3141 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3142 (unoptab
== neg_optab
3143 || unoptab
== one_cmpl_optab
)
3144 && mclass
== MODE_INT
);
3146 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3151 if (mclass
!= MODE_INT
3152 || !TRULY_NOOP_TRUNCATION_MODES_P (mode
, wider_mode
))
3155 target
= gen_reg_rtx (mode
);
3156 convert_move (target
, temp
, 0);
3160 return gen_lowpart (mode
, temp
);
3163 delete_insns_since (last
);
3167 /* These can be done a word at a time. */
3168 if (unoptab
== one_cmpl_optab
3169 && mclass
== MODE_INT
3170 && GET_MODE_SIZE (mode
) > UNITS_PER_WORD
3171 && optab_handler (unoptab
, word_mode
) != CODE_FOR_nothing
)
3176 if (target
== 0 || target
== op0
|| !valid_multiword_target_p (target
))
3177 target
= gen_reg_rtx (mode
);
3181 /* Do the actual arithmetic. */
3182 for (i
= 0; i
< GET_MODE_BITSIZE (mode
) / BITS_PER_WORD
; i
++)
3184 rtx target_piece
= operand_subword (target
, i
, 1, mode
);
3185 rtx x
= expand_unop (word_mode
, unoptab
,
3186 operand_subword_force (op0
, i
, mode
),
3187 target_piece
, unsignedp
);
3189 if (target_piece
!= x
)
3190 emit_move_insn (target_piece
, x
);
3193 insns
= get_insns ();
3200 if (optab_to_code (unoptab
) == NEG
)
3202 /* Try negating floating point values by flipping the sign bit. */
3203 if (SCALAR_FLOAT_MODE_P (mode
))
3205 temp
= expand_absneg_bit (NEG
, mode
, op0
, target
);
3210 /* If there is no negation pattern, and we have no negative zero,
3211 try subtracting from zero. */
3212 if (!HONOR_SIGNED_ZEROS (mode
))
3214 temp
= expand_binop (mode
, (unoptab
== negv_optab
3215 ? subv_optab
: sub_optab
),
3216 CONST0_RTX (mode
), op0
, target
,
3217 unsignedp
, OPTAB_DIRECT
);
3223 /* Try calculating parity (x) as popcount (x) % 2. */
3224 if (unoptab
== parity_optab
)
3226 temp
= expand_parity (mode
, op0
, target
);
3231 /* Try implementing ffs (x) in terms of clz (x). */
3232 if (unoptab
== ffs_optab
)
3234 temp
= expand_ffs (mode
, op0
, target
);
3239 /* Try implementing ctz (x) in terms of clz (x). */
3240 if (unoptab
== ctz_optab
)
3242 temp
= expand_ctz (mode
, op0
, target
);
3248 /* Now try a library call in this mode. */
3249 libfunc
= optab_libfunc (unoptab
, mode
);
3255 machine_mode outmode
= mode
;
3257 /* All of these functions return small values. Thus we choose to
3258 have them return something that isn't a double-word. */
3259 if (unoptab
== ffs_optab
|| unoptab
== clz_optab
|| unoptab
== ctz_optab
3260 || unoptab
== clrsb_optab
|| unoptab
== popcount_optab
3261 || unoptab
== parity_optab
)
3263 = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node
),
3264 optab_libfunc (unoptab
, mode
)));
3268 /* Pass 1 for NO_QUEUE so we don't lose any increments
3269 if the libcall is cse'd or moved. */
3270 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, outmode
,
3272 insns
= get_insns ();
3275 target
= gen_reg_rtx (outmode
);
3276 eq_value
= gen_rtx_fmt_e (optab_to_code (unoptab
), mode
, op0
);
3277 if (GET_MODE_SIZE (outmode
) < GET_MODE_SIZE (mode
))
3278 eq_value
= simplify_gen_unary (TRUNCATE
, outmode
, eq_value
, mode
);
3279 else if (GET_MODE_SIZE (outmode
) > GET_MODE_SIZE (mode
))
3280 eq_value
= simplify_gen_unary (ZERO_EXTEND
, outmode
, eq_value
, mode
);
3281 emit_libcall_block_1 (insns
, target
, value
, eq_value
,
3282 trapv_unoptab_p (unoptab
));
3287 /* It can't be done in this mode. Can we do it in a wider mode? */
3289 if (CLASS_HAS_WIDER_MODES_P (mclass
))
3291 for (wider_mode
= GET_MODE_WIDER_MODE (mode
);
3292 wider_mode
!= VOIDmode
;
3293 wider_mode
= GET_MODE_WIDER_MODE (wider_mode
))
3295 if (optab_handler (unoptab
, wider_mode
) != CODE_FOR_nothing
3296 || optab_libfunc (unoptab
, wider_mode
))
3299 rtx_insn
*last
= get_last_insn ();
3301 /* For certain operations, we need not actually extend
3302 the narrow operand, as long as we will truncate the
3303 results to the same narrowness. */
3304 xop0
= widen_operand (xop0
, wider_mode
, mode
, unsignedp
,
3305 (unoptab
== neg_optab
3306 || unoptab
== one_cmpl_optab
3307 || unoptab
== bswap_optab
)
3308 && mclass
== MODE_INT
);
3310 temp
= expand_unop (wider_mode
, unoptab
, xop0
, NULL_RTX
,
3313 /* If we are generating clz using wider mode, adjust the
3314 result. Similarly for clrsb. */
3315 if ((unoptab
== clz_optab
|| unoptab
== clrsb_optab
)
3318 (wider_mode
, sub_optab
, temp
,
3319 gen_int_mode (GET_MODE_PRECISION (wider_mode
)
3320 - GET_MODE_PRECISION (mode
),
3322 target
, true, OPTAB_DIRECT
);
3324 /* Likewise for bswap. */
3325 if (unoptab
== bswap_optab
&& temp
!= 0)
3327 gcc_assert (GET_MODE_PRECISION (wider_mode
)
3328 == GET_MODE_BITSIZE (wider_mode
)
3329 && GET_MODE_PRECISION (mode
)
3330 == GET_MODE_BITSIZE (mode
));
3332 temp
= expand_shift (RSHIFT_EXPR
, wider_mode
, temp
,
3333 GET_MODE_BITSIZE (wider_mode
)
3334 - GET_MODE_BITSIZE (mode
),
3340 if (mclass
!= MODE_INT
)
3343 target
= gen_reg_rtx (mode
);
3344 convert_move (target
, temp
, 0);
3348 return gen_lowpart (mode
, temp
);
3351 delete_insns_since (last
);
3356 /* One final attempt at implementing negation via subtraction,
3357 this time allowing widening of the operand. */
3358 if (optab_to_code (unoptab
) == NEG
&& !HONOR_SIGNED_ZEROS (mode
))
3361 temp
= expand_binop (mode
,
3362 unoptab
== negv_optab
? subv_optab
: sub_optab
,
3363 CONST0_RTX (mode
), op0
,
3364 target
, unsignedp
, OPTAB_LIB_WIDEN
);
3372 /* Emit code to compute the absolute value of OP0, with result to
3373 TARGET if convenient. (TARGET may be 0.) The return value says
3374 where the result actually is to be found.
3376 MODE is the mode of the operand; the mode of the result is
3377 different but can be deduced from MODE.
3382 expand_abs_nojump (machine_mode mode
, rtx op0
, rtx target
,
3383 int result_unsignedp
)
3387 if (GET_MODE_CLASS (mode
) != MODE_INT
3389 result_unsignedp
= 1;
3391 /* First try to do it with a special abs instruction. */
3392 temp
= expand_unop (mode
, result_unsignedp
? abs_optab
: absv_optab
,
3397 /* For floating point modes, try clearing the sign bit. */
3398 if (SCALAR_FLOAT_MODE_P (mode
))
3400 temp
= expand_absneg_bit (ABS
, mode
, op0
, target
);
3405 /* If we have a MAX insn, we can do this as MAX (x, -x). */
3406 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
3407 && !HONOR_SIGNED_ZEROS (mode
))
3409 rtx_insn
*last
= get_last_insn ();
3411 temp
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3414 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3420 delete_insns_since (last
);
3423 /* If this machine has expensive jumps, we can do integer absolute
3424 value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)),
3425 where W is the width of MODE. */
3427 if (GET_MODE_CLASS (mode
) == MODE_INT
3428 && BRANCH_COST (optimize_insn_for_speed_p (),
3431 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3432 GET_MODE_PRECISION (mode
) - 1,
3435 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3438 temp
= expand_binop (mode
, result_unsignedp
? sub_optab
: subv_optab
,
3439 temp
, extended
, target
, 0, OPTAB_LIB_WIDEN
);
3449 expand_abs (machine_mode mode
, rtx op0
, rtx target
,
3450 int result_unsignedp
, int safe
)
3453 rtx_code_label
*op1
;
3455 if (GET_MODE_CLASS (mode
) != MODE_INT
3457 result_unsignedp
= 1;
3459 temp
= expand_abs_nojump (mode
, op0
, target
, result_unsignedp
);
3463 /* If that does not win, use conditional jump and negate. */
3465 /* It is safe to use the target if it is the same
3466 as the source if this is also a pseudo register */
3467 if (op0
== target
&& REG_P (op0
)
3468 && REGNO (op0
) >= FIRST_PSEUDO_REGISTER
)
3471 op1
= gen_label_rtx ();
3472 if (target
== 0 || ! safe
3473 || GET_MODE (target
) != mode
3474 || (MEM_P (target
) && MEM_VOLATILE_P (target
))
3476 && REGNO (target
) < FIRST_PSEUDO_REGISTER
))
3477 target
= gen_reg_rtx (mode
);
3479 emit_move_insn (target
, op0
);
3482 do_compare_rtx_and_jump (target
, CONST0_RTX (mode
), GE
, 0, mode
,
3483 NULL_RTX
, NULL
, op1
, -1);
3485 op0
= expand_unop (mode
, result_unsignedp
? neg_optab
: negv_optab
,
3488 emit_move_insn (target
, op0
);
3494 /* Emit code to compute the one's complement absolute value of OP0
3495 (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient.
3496 (TARGET may be NULL_RTX.) The return value says where the result
3497 actually is to be found.
3499 MODE is the mode of the operand; the mode of the result is
3500 different but can be deduced from MODE. */
3503 expand_one_cmpl_abs_nojump (machine_mode mode
, rtx op0
, rtx target
)
3507 /* Not applicable for floating point modes. */
3508 if (FLOAT_MODE_P (mode
))
3511 /* If we have a MAX insn, we can do this as MAX (x, ~x). */
3512 if (optab_handler (smax_optab
, mode
) != CODE_FOR_nothing
)
3514 rtx_insn
*last
= get_last_insn ();
3516 temp
= expand_unop (mode
, one_cmpl_optab
, op0
, NULL_RTX
, 0);
3518 temp
= expand_binop (mode
, smax_optab
, op0
, temp
, target
, 0,
3524 delete_insns_since (last
);
3527 /* If this machine has expensive jumps, we can do one's complement
3528 absolute value of X as (((signed) x >> (W-1)) ^ x). */
3530 if (GET_MODE_CLASS (mode
) == MODE_INT
3531 && BRANCH_COST (optimize_insn_for_speed_p (),
3534 rtx extended
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3535 GET_MODE_PRECISION (mode
) - 1,
3538 temp
= expand_binop (mode
, xor_optab
, extended
, op0
, target
, 0,
3548 /* A subroutine of expand_copysign, perform the copysign operation using the
3549 abs and neg primitives advertised to exist on the target. The assumption
3550 is that we have a split register file, and leaving op0 in fp registers,
3551 and not playing with subregs so much, will help the register allocator. */
3554 expand_copysign_absneg (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3555 int bitpos
, bool op0_is_abs
)
3558 enum insn_code icode
;
3560 rtx_code_label
*label
;
3565 /* Check if the back end provides an insn that handles signbit for the
3567 icode
= optab_handler (signbit_optab
, mode
);
3568 if (icode
!= CODE_FOR_nothing
)
3570 imode
= insn_data
[(int) icode
].operand
[0].mode
;
3571 sign
= gen_reg_rtx (imode
);
3572 emit_unop_insn (icode
, sign
, op1
, UNKNOWN
);
3576 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3578 imode
= int_mode_for_mode (mode
);
3579 if (imode
== BLKmode
)
3581 op1
= gen_lowpart (imode
, op1
);
3588 if (FLOAT_WORDS_BIG_ENDIAN
)
3589 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3591 word
= bitpos
/ BITS_PER_WORD
;
3592 bitpos
= bitpos
% BITS_PER_WORD
;
3593 op1
= operand_subword_force (op1
, word
, mode
);
3596 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3597 sign
= expand_binop (imode
, and_optab
, op1
,
3598 immed_wide_int_const (mask
, imode
),
3599 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3604 op0
= expand_unop (mode
, abs_optab
, op0
, target
, 0);
3611 if (target
== NULL_RTX
)
3612 target
= copy_to_reg (op0
);
3614 emit_move_insn (target
, op0
);
3617 label
= gen_label_rtx ();
3618 emit_cmp_and_jump_insns (sign
, const0_rtx
, EQ
, NULL_RTX
, imode
, 1, label
);
3620 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3621 op0
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
3623 op0
= expand_unop (mode
, neg_optab
, op0
, target
, 0);
3625 emit_move_insn (target
, op0
);
3633 /* A subroutine of expand_copysign, perform the entire copysign operation
3634 with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS
3635 is true if op0 is known to have its sign bit clear. */
3638 expand_copysign_bit (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3639 int bitpos
, bool op0_is_abs
)
3642 int word
, nwords
, i
;
3646 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
)
3648 imode
= int_mode_for_mode (mode
);
3649 if (imode
== BLKmode
)
3658 if (FLOAT_WORDS_BIG_ENDIAN
)
3659 word
= (GET_MODE_BITSIZE (mode
) - bitpos
) / BITS_PER_WORD
;
3661 word
= bitpos
/ BITS_PER_WORD
;
3662 bitpos
= bitpos
% BITS_PER_WORD
;
3663 nwords
= (GET_MODE_BITSIZE (mode
) + BITS_PER_WORD
- 1) / BITS_PER_WORD
;
3666 wide_int mask
= wi::set_bit_in_zero (bitpos
, GET_MODE_PRECISION (imode
));
3671 || (nwords
> 1 && !valid_multiword_target_p (target
)))
3672 target
= gen_reg_rtx (mode
);
3678 for (i
= 0; i
< nwords
; ++i
)
3680 rtx targ_piece
= operand_subword (target
, i
, 1, mode
);
3681 rtx op0_piece
= operand_subword_force (op0
, i
, mode
);
3687 = expand_binop (imode
, and_optab
, op0_piece
,
3688 immed_wide_int_const (~mask
, imode
),
3689 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3690 op1
= expand_binop (imode
, and_optab
,
3691 operand_subword_force (op1
, i
, mode
),
3692 immed_wide_int_const (mask
, imode
),
3693 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3695 temp
= expand_binop (imode
, ior_optab
, op0_piece
, op1
,
3696 targ_piece
, 1, OPTAB_LIB_WIDEN
);
3697 if (temp
!= targ_piece
)
3698 emit_move_insn (targ_piece
, temp
);
3701 emit_move_insn (targ_piece
, op0_piece
);
3704 insns
= get_insns ();
3711 op1
= expand_binop (imode
, and_optab
, gen_lowpart (imode
, op1
),
3712 immed_wide_int_const (mask
, imode
),
3713 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3715 op0
= gen_lowpart (imode
, op0
);
3717 op0
= expand_binop (imode
, and_optab
, op0
,
3718 immed_wide_int_const (~mask
, imode
),
3719 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3721 temp
= expand_binop (imode
, ior_optab
, op0
, op1
,
3722 gen_lowpart (imode
, target
), 1, OPTAB_LIB_WIDEN
);
3723 target
= lowpart_subreg_maybe_copy (mode
, temp
, imode
);
3729 /* Expand the C99 copysign operation. OP0 and OP1 must be the same
3730 scalar floating point mode. Return NULL if we do not know how to
3731 expand the operation inline. */
3734 expand_copysign (rtx op0
, rtx op1
, rtx target
)
3736 machine_mode mode
= GET_MODE (op0
);
3737 const struct real_format
*fmt
;
3741 gcc_assert (SCALAR_FLOAT_MODE_P (mode
));
3742 gcc_assert (GET_MODE (op1
) == mode
);
3744 /* First try to do it with a special instruction. */
3745 temp
= expand_binop (mode
, copysign_optab
, op0
, op1
,
3746 target
, 0, OPTAB_DIRECT
);
3750 fmt
= REAL_MODE_FORMAT (mode
);
3751 if (fmt
== NULL
|| !fmt
->has_signed_zero
)
3755 if (CONST_DOUBLE_AS_FLOAT_P (op0
))
3757 if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0
)))
3758 op0
= simplify_unary_operation (ABS
, mode
, op0
, mode
);
3762 if (fmt
->signbit_ro
>= 0
3763 && (CONST_DOUBLE_AS_FLOAT_P (op0
)
3764 || (optab_handler (neg_optab
, mode
) != CODE_FOR_nothing
3765 && optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)))
3767 temp
= expand_copysign_absneg (mode
, op0
, op1
, target
,
3768 fmt
->signbit_ro
, op0_is_abs
);
3773 if (fmt
->signbit_rw
< 0)
3775 return expand_copysign_bit (mode
, op0
, op1
, target
,
3776 fmt
->signbit_rw
, op0_is_abs
);
3779 /* Generate an instruction whose insn-code is INSN_CODE,
3780 with two operands: an output TARGET and an input OP0.
3781 TARGET *must* be nonzero, and the output is always stored there.
3782 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3783 the value that is stored into TARGET.
3785 Return false if expansion failed. */
3788 maybe_emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
,
3791 struct expand_operand ops
[2];
3794 create_output_operand (&ops
[0], target
, GET_MODE (target
));
3795 create_input_operand (&ops
[1], op0
, GET_MODE (op0
));
3796 pat
= maybe_gen_insn (icode
, 2, ops
);
3800 if (INSN_P (pat
) && NEXT_INSN (pat
) != NULL_RTX
3802 add_equal_note (pat
, ops
[0].value
, code
, ops
[1].value
, NULL_RTX
);
3806 if (ops
[0].value
!= target
)
3807 emit_move_insn (target
, ops
[0].value
);
3810 /* Generate an instruction whose insn-code is INSN_CODE,
3811 with two operands: an output TARGET and an input OP0.
3812 TARGET *must* be nonzero, and the output is always stored there.
3813 CODE is an rtx code such that (CODE OP0) is an rtx that describes
3814 the value that is stored into TARGET. */
3817 emit_unop_insn (enum insn_code icode
, rtx target
, rtx op0
, enum rtx_code code
)
3819 bool ok
= maybe_emit_unop_insn (icode
, target
, op0
, code
);
3823 struct no_conflict_data
3826 rtx_insn
*first
, *insn
;
3830 /* Called via note_stores by emit_libcall_block. Set P->must_stay if
3831 the currently examined clobber / store has to stay in the list of
3832 insns that constitute the actual libcall block. */
3834 no_conflict_move_test (rtx dest
, const_rtx set
, void *p0
)
3836 struct no_conflict_data
*p
= (struct no_conflict_data
*) p0
;
3838 /* If this inns directly contributes to setting the target, it must stay. */
3839 if (reg_overlap_mentioned_p (p
->target
, dest
))
3840 p
->must_stay
= true;
3841 /* If we haven't committed to keeping any other insns in the list yet,
3842 there is nothing more to check. */
3843 else if (p
->insn
== p
->first
)
3845 /* If this insn sets / clobbers a register that feeds one of the insns
3846 already in the list, this insn has to stay too. */
3847 else if (reg_overlap_mentioned_p (dest
, PATTERN (p
->first
))
3848 || (CALL_P (p
->first
) && (find_reg_fusage (p
->first
, USE
, dest
)))
3849 || reg_used_between_p (dest
, p
->first
, p
->insn
)
3850 /* Likewise if this insn depends on a register set by a previous
3851 insn in the list, or if it sets a result (presumably a hard
3852 register) that is set or clobbered by a previous insn.
3853 N.B. the modified_*_p (SET_DEST...) tests applied to a MEM
3854 SET_DEST perform the former check on the address, and the latter
3855 check on the MEM. */
3856 || (GET_CODE (set
) == SET
3857 && (modified_in_p (SET_SRC (set
), p
->first
)
3858 || modified_in_p (SET_DEST (set
), p
->first
)
3859 || modified_between_p (SET_SRC (set
), p
->first
, p
->insn
)
3860 || modified_between_p (SET_DEST (set
), p
->first
, p
->insn
))))
3861 p
->must_stay
= true;
3865 /* Emit code to make a call to a constant function or a library call.
3867 INSNS is a list containing all insns emitted in the call.
3868 These insns leave the result in RESULT. Our block is to copy RESULT
3869 to TARGET, which is logically equivalent to EQUIV.
3871 We first emit any insns that set a pseudo on the assumption that these are
3872 loading constants into registers; doing so allows them to be safely cse'ed
3873 between blocks. Then we emit all the other insns in the block, followed by
3874 an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL
3875 note with an operand of EQUIV. */
3878 emit_libcall_block_1 (rtx_insn
*insns
, rtx target
, rtx result
, rtx equiv
,
3879 bool equiv_may_trap
)
3881 rtx final_dest
= target
;
3882 rtx_insn
*next
, *last
, *insn
;
3884 /* If this is a reg with REG_USERVAR_P set, then it could possibly turn
3885 into a MEM later. Protect the libcall block from this change. */
3886 if (! REG_P (target
) || REG_USERVAR_P (target
))
3887 target
= gen_reg_rtx (GET_MODE (target
));
3889 /* If we're using non-call exceptions, a libcall corresponding to an
3890 operation that may trap may also trap. */
3891 /* ??? See the comment in front of make_reg_eh_region_note. */
3892 if (cfun
->can_throw_non_call_exceptions
3893 && (equiv_may_trap
|| may_trap_p (equiv
)))
3895 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3898 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
3901 int lp_nr
= INTVAL (XEXP (note
, 0));
3902 if (lp_nr
== 0 || lp_nr
== INT_MIN
)
3903 remove_note (insn
, note
);
3909 /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION
3910 reg note to indicate that this call cannot throw or execute a nonlocal
3911 goto (unless there is already a REG_EH_REGION note, in which case
3913 for (insn
= insns
; insn
; insn
= NEXT_INSN (insn
))
3915 make_reg_eh_region_note_nothrow_nononlocal (insn
);
3918 /* First emit all insns that set pseudos. Remove them from the list as
3919 we go. Avoid insns that set pseudos which were referenced in previous
3920 insns. These can be generated by move_by_pieces, for example,
3921 to update an address. Similarly, avoid insns that reference things
3922 set in previous insns. */
3924 for (insn
= insns
; insn
; insn
= next
)
3926 rtx set
= single_set (insn
);
3928 next
= NEXT_INSN (insn
);
3930 if (set
!= 0 && REG_P (SET_DEST (set
))
3931 && REGNO (SET_DEST (set
)) >= FIRST_PSEUDO_REGISTER
)
3933 struct no_conflict_data data
;
3935 data
.target
= const0_rtx
;
3939 note_stores (PATTERN (insn
), no_conflict_move_test
, &data
);
3940 if (! data
.must_stay
)
3942 if (PREV_INSN (insn
))
3943 SET_NEXT_INSN (PREV_INSN (insn
)) = next
;
3948 SET_PREV_INSN (next
) = PREV_INSN (insn
);
3954 /* Some ports use a loop to copy large arguments onto the stack.
3955 Don't move anything outside such a loop. */
3960 /* Write the remaining insns followed by the final copy. */
3961 for (insn
= insns
; insn
; insn
= next
)
3963 next
= NEXT_INSN (insn
);
3968 last
= emit_move_insn (target
, result
);
3969 set_dst_reg_note (last
, REG_EQUAL
, copy_rtx (equiv
), target
);
3971 if (final_dest
!= target
)
3972 emit_move_insn (final_dest
, target
);
3976 emit_libcall_block (rtx insns
, rtx target
, rtx result
, rtx equiv
)
3978 emit_libcall_block_1 (safe_as_a
<rtx_insn
*> (insns
),
3979 target
, result
, equiv
, false);
3982 /* Nonzero if we can perform a comparison of mode MODE straightforwardly.
3983 PURPOSE describes how this comparison will be used. CODE is the rtx
3984 comparison code we will be using.
3986 ??? Actually, CODE is slightly weaker than that. A target is still
3987 required to implement all of the normal bcc operations, but not
3988 required to implement all (or any) of the unordered bcc operations. */
3991 can_compare_p (enum rtx_code code
, machine_mode mode
,
3992 enum can_compare_purpose purpose
)
3995 test
= gen_rtx_fmt_ee (code
, mode
, const0_rtx
, const0_rtx
);
3998 enum insn_code icode
;
4000 if (purpose
== ccp_jump
4001 && (icode
= optab_handler (cbranch_optab
, mode
)) != CODE_FOR_nothing
4002 && insn_operand_matches (icode
, 0, test
))
4004 if (purpose
== ccp_store_flag
4005 && (icode
= optab_handler (cstore_optab
, mode
)) != CODE_FOR_nothing
4006 && insn_operand_matches (icode
, 1, test
))
4008 if (purpose
== ccp_cmov
4009 && optab_handler (cmov_optab
, mode
) != CODE_FOR_nothing
)
4012 mode
= GET_MODE_WIDER_MODE (mode
);
4013 PUT_MODE (test
, mode
);
4015 while (mode
!= VOIDmode
);
4020 /* This function is called when we are going to emit a compare instruction that
4021 compares the values found in *PX and *PY, using the rtl operator COMPARISON.
4023 *PMODE is the mode of the inputs (in case they are const_int).
4024 *PUNSIGNEDP nonzero says that the operands are unsigned;
4025 this matters if they need to be widened (as given by METHODS).
4027 If they have mode BLKmode, then SIZE specifies the size of both operands.
4029 This function performs all the setup necessary so that the caller only has
4030 to emit a single comparison insn. This setup can involve doing a BLKmode
4031 comparison or emitting a library call to perform the comparison if no insn
4032 is available to handle it.
4033 The values which are passed in through pointers can be modified; the caller
4034 should perform the comparison on the modified values. Constant
4035 comparisons must have already been folded. */
4038 prepare_cmp_insn (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4039 int unsignedp
, enum optab_methods methods
,
4040 rtx
*ptest
, machine_mode
*pmode
)
4042 machine_mode mode
= *pmode
;
4044 machine_mode cmp_mode
;
4045 enum mode_class mclass
;
4047 /* The other methods are not needed. */
4048 gcc_assert (methods
== OPTAB_DIRECT
|| methods
== OPTAB_WIDEN
4049 || methods
== OPTAB_LIB_WIDEN
);
4051 /* If we are optimizing, force expensive constants into a register. */
4052 if (CONSTANT_P (x
) && optimize
4053 && (rtx_cost (x
, COMPARE
, 0, optimize_insn_for_speed_p ())
4054 > COSTS_N_INSNS (1)))
4055 x
= force_reg (mode
, x
);
4057 if (CONSTANT_P (y
) && optimize
4058 && (rtx_cost (y
, COMPARE
, 1, optimize_insn_for_speed_p ())
4059 > COSTS_N_INSNS (1)))
4060 y
= force_reg (mode
, y
);
4063 /* Make sure if we have a canonical comparison. The RTL
4064 documentation states that canonical comparisons are required only
4065 for targets which have cc0. */
4066 gcc_assert (!CONSTANT_P (x
) || CONSTANT_P (y
));
4069 /* Don't let both operands fail to indicate the mode. */
4070 if (GET_MODE (x
) == VOIDmode
&& GET_MODE (y
) == VOIDmode
)
4071 x
= force_reg (mode
, x
);
4072 if (mode
== VOIDmode
)
4073 mode
= GET_MODE (x
) != VOIDmode
? GET_MODE (x
) : GET_MODE (y
);
4075 /* Handle all BLKmode compares. */
4077 if (mode
== BLKmode
)
4079 machine_mode result_mode
;
4080 enum insn_code cmp_code
;
4085 = GEN_INT (MIN (MEM_ALIGN (x
), MEM_ALIGN (y
)) / BITS_PER_UNIT
);
4089 /* Try to use a memory block compare insn - either cmpstr
4090 or cmpmem will do. */
4091 for (cmp_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
4092 cmp_mode
!= VOIDmode
;
4093 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
))
4095 cmp_code
= direct_optab_handler (cmpmem_optab
, cmp_mode
);
4096 if (cmp_code
== CODE_FOR_nothing
)
4097 cmp_code
= direct_optab_handler (cmpstr_optab
, cmp_mode
);
4098 if (cmp_code
== CODE_FOR_nothing
)
4099 cmp_code
= direct_optab_handler (cmpstrn_optab
, cmp_mode
);
4100 if (cmp_code
== CODE_FOR_nothing
)
4103 /* Must make sure the size fits the insn's mode. */
4104 if ((CONST_INT_P (size
)
4105 && INTVAL (size
) >= (1 << GET_MODE_BITSIZE (cmp_mode
)))
4106 || (GET_MODE_BITSIZE (GET_MODE (size
))
4107 > GET_MODE_BITSIZE (cmp_mode
)))
4110 result_mode
= insn_data
[cmp_code
].operand
[0].mode
;
4111 result
= gen_reg_rtx (result_mode
);
4112 size
= convert_to_mode (cmp_mode
, size
, 1);
4113 emit_insn (GEN_FCN (cmp_code
) (result
, x
, y
, size
, opalign
));
4115 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, result
, const0_rtx
);
4116 *pmode
= result_mode
;
4120 if (methods
!= OPTAB_LIB
&& methods
!= OPTAB_LIB_WIDEN
)
4123 /* Otherwise call a library function, memcmp. */
4124 libfunc
= memcmp_libfunc
;
4125 length_type
= sizetype
;
4126 result_mode
= TYPE_MODE (integer_type_node
);
4127 cmp_mode
= TYPE_MODE (length_type
);
4128 size
= convert_to_mode (TYPE_MODE (length_type
), size
,
4129 TYPE_UNSIGNED (length_type
));
4131 result
= emit_library_call_value (libfunc
, 0, LCT_PURE
,
4139 methods
= OPTAB_LIB_WIDEN
;
4143 /* Don't allow operands to the compare to trap, as that can put the
4144 compare and branch in different basic blocks. */
4145 if (cfun
->can_throw_non_call_exceptions
)
4148 x
= force_reg (mode
, x
);
4150 y
= force_reg (mode
, y
);
4153 if (GET_MODE_CLASS (mode
) == MODE_CC
)
4155 enum insn_code icode
= optab_handler (cbranch_optab
, CCmode
);
4156 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4157 gcc_assert (icode
!= CODE_FOR_nothing
4158 && insn_operand_matches (icode
, 0, test
));
4163 mclass
= GET_MODE_CLASS (mode
);
4164 test
= gen_rtx_fmt_ee (comparison
, VOIDmode
, x
, y
);
4168 enum insn_code icode
;
4169 icode
= optab_handler (cbranch_optab
, cmp_mode
);
4170 if (icode
!= CODE_FOR_nothing
4171 && insn_operand_matches (icode
, 0, test
))
4173 rtx_insn
*last
= get_last_insn ();
4174 rtx op0
= prepare_operand (icode
, x
, 1, mode
, cmp_mode
, unsignedp
);
4175 rtx op1
= prepare_operand (icode
, y
, 2, mode
, cmp_mode
, unsignedp
);
4177 && insn_operand_matches (icode
, 1, op0
)
4178 && insn_operand_matches (icode
, 2, op1
))
4180 XEXP (test
, 0) = op0
;
4181 XEXP (test
, 1) = op1
;
4186 delete_insns_since (last
);
4189 if (methods
== OPTAB_DIRECT
|| !CLASS_HAS_WIDER_MODES_P (mclass
))
4191 cmp_mode
= GET_MODE_WIDER_MODE (cmp_mode
);
4193 while (cmp_mode
!= VOIDmode
);
4195 if (methods
!= OPTAB_LIB_WIDEN
)
4198 if (!SCALAR_FLOAT_MODE_P (mode
))
4201 machine_mode ret_mode
;
4203 /* Handle a libcall just for the mode we are using. */
4204 libfunc
= optab_libfunc (cmp_optab
, mode
);
4205 gcc_assert (libfunc
);
4207 /* If we want unsigned, and this mode has a distinct unsigned
4208 comparison routine, use that. */
4211 rtx ulibfunc
= optab_libfunc (ucmp_optab
, mode
);
4216 ret_mode
= targetm
.libgcc_cmp_return_mode ();
4217 result
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4218 ret_mode
, 2, x
, mode
, y
, mode
);
4220 /* There are two kinds of comparison routines. Biased routines
4221 return 0/1/2, and unbiased routines return -1/0/1. Other parts
4222 of gcc expect that the comparison operation is equivalent
4223 to the modified comparison. For signed comparisons compare the
4224 result against 1 in the biased case, and zero in the unbiased
4225 case. For unsigned comparisons always compare against 1 after
4226 biasing the unbiased result by adding 1. This gives us a way to
4228 The comparisons in the fixed-point helper library are always
4233 if (!TARGET_LIB_INT_CMP_BIASED
&& !ALL_FIXED_POINT_MODE_P (mode
))
4236 x
= plus_constant (ret_mode
, result
, 1);
4242 prepare_cmp_insn (x
, y
, comparison
, NULL_RTX
, unsignedp
, methods
,
4246 prepare_float_lib_cmp (x
, y
, comparison
, ptest
, pmode
);
4254 /* Before emitting an insn with code ICODE, make sure that X, which is going
4255 to be used for operand OPNUM of the insn, is converted from mode MODE to
4256 WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and
4257 that it is accepted by the operand predicate. Return the new value. */
4260 prepare_operand (enum insn_code icode
, rtx x
, int opnum
, machine_mode mode
,
4261 machine_mode wider_mode
, int unsignedp
)
4263 if (mode
!= wider_mode
)
4264 x
= convert_modes (wider_mode
, mode
, x
, unsignedp
);
4266 if (!insn_operand_matches (icode
, opnum
, x
))
4268 machine_mode op_mode
= insn_data
[(int) icode
].operand
[opnum
].mode
;
4269 if (reload_completed
)
4271 if (GET_MODE (x
) != op_mode
&& GET_MODE (x
) != VOIDmode
)
4273 x
= copy_to_mode_reg (op_mode
, x
);
4279 /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know
4280 we can do the branch. */
4283 emit_cmp_and_jump_insn_1 (rtx test
, machine_mode mode
, rtx label
, int prob
)
4285 machine_mode optab_mode
;
4286 enum mode_class mclass
;
4287 enum insn_code icode
;
4290 mclass
= GET_MODE_CLASS (mode
);
4291 optab_mode
= (mclass
== MODE_CC
) ? CCmode
: mode
;
4292 icode
= optab_handler (cbranch_optab
, optab_mode
);
4294 gcc_assert (icode
!= CODE_FOR_nothing
);
4295 gcc_assert (insn_operand_matches (icode
, 0, test
));
4296 insn
= emit_jump_insn (GEN_FCN (icode
) (test
, XEXP (test
, 0),
4297 XEXP (test
, 1), label
));
4299 && profile_status_for_fn (cfun
) != PROFILE_ABSENT
4302 && any_condjump_p (insn
)
4303 && !find_reg_note (insn
, REG_BR_PROB
, 0))
4304 add_int_reg_note (insn
, REG_BR_PROB
, prob
);
4307 /* Generate code to compare X with Y so that the condition codes are
4308 set and to jump to LABEL if the condition is true. If X is a
4309 constant and Y is not a constant, then the comparison is swapped to
4310 ensure that the comparison RTL has the canonical form.
4312 UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they
4313 need to be widened. UNSIGNEDP is also used to select the proper
4314 branch condition code.
4316 If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y.
4318 MODE is the mode of the inputs (in case they are const_int).
4320 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
4321 It will be potentially converted into an unsigned variant based on
4322 UNSIGNEDP to select a proper jump instruction.
4324 PROB is the probability of jumping to LABEL. */
4327 emit_cmp_and_jump_insns (rtx x
, rtx y
, enum rtx_code comparison
, rtx size
,
4328 machine_mode mode
, int unsignedp
, rtx label
,
4331 rtx op0
= x
, op1
= y
;
4334 /* Swap operands and condition to ensure canonical RTL. */
4335 if (swap_commutative_operands_p (x
, y
)
4336 && can_compare_p (swap_condition (comparison
), mode
, ccp_jump
))
4339 comparison
= swap_condition (comparison
);
4342 /* If OP0 is still a constant, then both X and Y must be constants
4343 or the opposite comparison is not supported. Force X into a register
4344 to create canonical RTL. */
4345 if (CONSTANT_P (op0
))
4346 op0
= force_reg (mode
, op0
);
4349 comparison
= unsigned_condition (comparison
);
4351 prepare_cmp_insn (op0
, op1
, comparison
, size
, unsignedp
, OPTAB_LIB_WIDEN
,
4353 emit_cmp_and_jump_insn_1 (test
, mode
, label
, prob
);
4357 /* Emit a library call comparison between floating point X and Y.
4358 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */
4361 prepare_float_lib_cmp (rtx x
, rtx y
, enum rtx_code comparison
,
4362 rtx
*ptest
, machine_mode
*pmode
)
4364 enum rtx_code swapped
= swap_condition (comparison
);
4365 enum rtx_code reversed
= reverse_condition_maybe_unordered (comparison
);
4366 machine_mode orig_mode
= GET_MODE (x
);
4367 machine_mode mode
, cmp_mode
;
4368 rtx true_rtx
, false_rtx
;
4369 rtx value
, target
, equiv
;
4372 bool reversed_p
= false;
4373 cmp_mode
= targetm
.libgcc_cmp_return_mode ();
4375 for (mode
= orig_mode
;
4377 mode
= GET_MODE_WIDER_MODE (mode
))
4379 if (code_to_optab (comparison
)
4380 && (libfunc
= optab_libfunc (code_to_optab (comparison
), mode
)))
4383 if (code_to_optab (swapped
)
4384 && (libfunc
= optab_libfunc (code_to_optab (swapped
), mode
)))
4387 tmp
= x
; x
= y
; y
= tmp
;
4388 comparison
= swapped
;
4392 if (code_to_optab (reversed
)
4393 && (libfunc
= optab_libfunc (code_to_optab (reversed
), mode
)))
4395 comparison
= reversed
;
4401 gcc_assert (mode
!= VOIDmode
);
4403 if (mode
!= orig_mode
)
4405 x
= convert_to_mode (mode
, x
, 0);
4406 y
= convert_to_mode (mode
, y
, 0);
4409 /* Attach a REG_EQUAL note describing the semantics of the libcall to
4410 the RTL. The allows the RTL optimizers to delete the libcall if the
4411 condition can be determined at compile-time. */
4412 if (comparison
== UNORDERED
4413 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4415 true_rtx
= const_true_rtx
;
4416 false_rtx
= const0_rtx
;
4423 true_rtx
= const0_rtx
;
4424 false_rtx
= const_true_rtx
;
4428 true_rtx
= const_true_rtx
;
4429 false_rtx
= const0_rtx
;
4433 true_rtx
= const1_rtx
;
4434 false_rtx
= const0_rtx
;
4438 true_rtx
= const0_rtx
;
4439 false_rtx
= constm1_rtx
;
4443 true_rtx
= constm1_rtx
;
4444 false_rtx
= const0_rtx
;
4448 true_rtx
= const0_rtx
;
4449 false_rtx
= const1_rtx
;
4457 if (comparison
== UNORDERED
)
4459 rtx temp
= simplify_gen_relational (NE
, cmp_mode
, mode
, x
, x
);
4460 equiv
= simplify_gen_relational (NE
, cmp_mode
, mode
, y
, y
);
4461 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4462 temp
, const_true_rtx
, equiv
);
4466 equiv
= simplify_gen_relational (comparison
, cmp_mode
, mode
, x
, y
);
4467 if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
))
4468 equiv
= simplify_gen_ternary (IF_THEN_ELSE
, cmp_mode
, cmp_mode
,
4469 equiv
, true_rtx
, false_rtx
);
4473 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
4474 cmp_mode
, 2, x
, mode
, y
, mode
);
4475 insns
= get_insns ();
4478 target
= gen_reg_rtx (cmp_mode
);
4479 emit_libcall_block (insns
, target
, value
, equiv
);
4481 if (comparison
== UNORDERED
4482 || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode
, comparison
)
4484 *ptest
= gen_rtx_fmt_ee (reversed_p
? EQ
: NE
, VOIDmode
, target
, false_rtx
);
4486 *ptest
= gen_rtx_fmt_ee (comparison
, VOIDmode
, target
, const0_rtx
);
4491 /* Generate code to indirectly jump to a location given in the rtx LOC. */
4494 emit_indirect_jump (rtx loc ATTRIBUTE_UNUSED
)
4496 #ifndef HAVE_indirect_jump
4497 sorry ("indirect jumps are not available on this target");
4499 struct expand_operand ops
[1];
4500 create_address_operand (&ops
[0], loc
);
4501 expand_jump_insn (CODE_FOR_indirect_jump
, 1, ops
);
4507 /* Emit a conditional move instruction if the machine supports one for that
4508 condition and machine mode.
4510 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4511 the mode to use should they be constants. If it is VOIDmode, they cannot
4514 OP2 should be stored in TARGET if the comparison is true, otherwise OP3
4515 should be stored there. MODE is the mode to use should they be constants.
4516 If it is VOIDmode, they cannot both be constants.
4518 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4519 is not supported. */
4522 emit_conditional_move (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4523 machine_mode cmode
, rtx op2
, rtx op3
,
4524 machine_mode mode
, int unsignedp
)
4528 enum insn_code icode
;
4529 enum rtx_code reversed
;
4531 /* If one operand is constant, make it the second one. Only do this
4532 if the other operand is not constant as well. */
4534 if (swap_commutative_operands_p (op0
, op1
))
4536 std::swap (op0
, op1
);
4537 code
= swap_condition (code
);
4540 /* get_condition will prefer to generate LT and GT even if the old
4541 comparison was against zero, so undo that canonicalization here since
4542 comparisons against zero are cheaper. */
4543 if (code
== LT
&& op1
== const1_rtx
)
4544 code
= LE
, op1
= const0_rtx
;
4545 else if (code
== GT
&& op1
== constm1_rtx
)
4546 code
= GE
, op1
= const0_rtx
;
4548 if (cmode
== VOIDmode
)
4549 cmode
= GET_MODE (op0
);
4551 if (swap_commutative_operands_p (op2
, op3
)
4552 && ((reversed
= reversed_comparison_code_parts (code
, op0
, op1
, NULL
))
4555 std::swap (op2
, op3
);
4559 if (mode
== VOIDmode
)
4560 mode
= GET_MODE (op2
);
4562 icode
= direct_optab_handler (movcc_optab
, mode
);
4564 if (icode
== CODE_FOR_nothing
)
4568 target
= gen_reg_rtx (mode
);
4570 code
= unsignedp
? unsigned_condition (code
) : code
;
4571 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4573 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4574 return NULL and let the caller figure out how best to deal with this
4576 if (!COMPARISON_P (comparison
))
4579 saved_pending_stack_adjust save
;
4580 save_pending_stack_adjust (&save
);
4581 last
= get_last_insn ();
4582 do_pending_stack_adjust ();
4583 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4584 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4585 &comparison
, &cmode
);
4588 struct expand_operand ops
[4];
4590 create_output_operand (&ops
[0], target
, mode
);
4591 create_fixed_operand (&ops
[1], comparison
);
4592 create_input_operand (&ops
[2], op2
, mode
);
4593 create_input_operand (&ops
[3], op3
, mode
);
4594 if (maybe_expand_insn (icode
, 4, ops
))
4596 if (ops
[0].value
!= target
)
4597 convert_move (target
, ops
[0].value
, false);
4601 delete_insns_since (last
);
4602 restore_pending_stack_adjust (&save
);
4606 /* Return nonzero if a conditional move of mode MODE is supported.
4608 This function is for combine so it can tell whether an insn that looks
4609 like a conditional move is actually supported by the hardware. If we
4610 guess wrong we lose a bit on optimization, but that's it. */
4611 /* ??? sparc64 supports conditionally moving integers values based on fp
4612 comparisons, and vice versa. How do we handle them? */
4615 can_conditionally_move_p (machine_mode mode
)
4617 if (direct_optab_handler (movcc_optab
, mode
) != CODE_FOR_nothing
)
4623 /* Emit a conditional addition instruction if the machine supports one for that
4624 condition and machine mode.
4626 OP0 and OP1 are the operands that should be compared using CODE. CMODE is
4627 the mode to use should they be constants. If it is VOIDmode, they cannot
4630 OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3
4631 should be stored there. MODE is the mode to use should they be constants.
4632 If it is VOIDmode, they cannot both be constants.
4634 The result is either TARGET (perhaps modified) or NULL_RTX if the operation
4635 is not supported. */
4638 emit_conditional_add (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
4639 machine_mode cmode
, rtx op2
, rtx op3
,
4640 machine_mode mode
, int unsignedp
)
4644 enum insn_code icode
;
4646 /* If one operand is constant, make it the second one. Only do this
4647 if the other operand is not constant as well. */
4649 if (swap_commutative_operands_p (op0
, op1
))
4651 std::swap (op0
, op1
);
4652 code
= swap_condition (code
);
4655 /* get_condition will prefer to generate LT and GT even if the old
4656 comparison was against zero, so undo that canonicalization here since
4657 comparisons against zero are cheaper. */
4658 if (code
== LT
&& op1
== const1_rtx
)
4659 code
= LE
, op1
= const0_rtx
;
4660 else if (code
== GT
&& op1
== constm1_rtx
)
4661 code
= GE
, op1
= const0_rtx
;
4663 if (cmode
== VOIDmode
)
4664 cmode
= GET_MODE (op0
);
4666 if (mode
== VOIDmode
)
4667 mode
= GET_MODE (op2
);
4669 icode
= optab_handler (addcc_optab
, mode
);
4671 if (icode
== CODE_FOR_nothing
)
4675 target
= gen_reg_rtx (mode
);
4677 code
= unsignedp
? unsigned_condition (code
) : code
;
4678 comparison
= simplify_gen_relational (code
, VOIDmode
, cmode
, op0
, op1
);
4680 /* We can get const0_rtx or const_true_rtx in some circumstances. Just
4681 return NULL and let the caller figure out how best to deal with this
4683 if (!COMPARISON_P (comparison
))
4686 do_pending_stack_adjust ();
4687 last
= get_last_insn ();
4688 prepare_cmp_insn (XEXP (comparison
, 0), XEXP (comparison
, 1),
4689 GET_CODE (comparison
), NULL_RTX
, unsignedp
, OPTAB_WIDEN
,
4690 &comparison
, &cmode
);
4693 struct expand_operand ops
[4];
4695 create_output_operand (&ops
[0], target
, mode
);
4696 create_fixed_operand (&ops
[1], comparison
);
4697 create_input_operand (&ops
[2], op2
, mode
);
4698 create_input_operand (&ops
[3], op3
, mode
);
4699 if (maybe_expand_insn (icode
, 4, ops
))
4701 if (ops
[0].value
!= target
)
4702 convert_move (target
, ops
[0].value
, false);
4706 delete_insns_since (last
);
4710 /* These functions attempt to generate an insn body, rather than
4711 emitting the insn, but if the gen function already emits them, we
4712 make no attempt to turn them back into naked patterns. */
4714 /* Generate and return an insn body to add Y to X. */
4717 gen_add2_insn (rtx x
, rtx y
)
4719 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (x
));
4721 gcc_assert (insn_operand_matches (icode
, 0, x
));
4722 gcc_assert (insn_operand_matches (icode
, 1, x
));
4723 gcc_assert (insn_operand_matches (icode
, 2, y
));
4725 return GEN_FCN (icode
) (x
, x
, y
);
4728 /* Generate and return an insn body to add r1 and c,
4729 storing the result in r0. */
4732 gen_add3_insn (rtx r0
, rtx r1
, rtx c
)
4734 enum insn_code icode
= optab_handler (add_optab
, GET_MODE (r0
));
4736 if (icode
== CODE_FOR_nothing
4737 || !insn_operand_matches (icode
, 0, r0
)
4738 || !insn_operand_matches (icode
, 1, r1
)
4739 || !insn_operand_matches (icode
, 2, c
))
4742 return GEN_FCN (icode
) (r0
, r1
, c
);
4746 have_add2_insn (rtx x
, rtx y
)
4748 enum insn_code icode
;
4750 gcc_assert (GET_MODE (x
) != VOIDmode
);
4752 icode
= optab_handler (add_optab
, GET_MODE (x
));
4754 if (icode
== CODE_FOR_nothing
)
4757 if (!insn_operand_matches (icode
, 0, x
)
4758 || !insn_operand_matches (icode
, 1, x
)
4759 || !insn_operand_matches (icode
, 2, y
))
4765 /* Generate and return an insn body to add Y to X. */
4768 gen_addptr3_insn (rtx x
, rtx y
, rtx z
)
4770 enum insn_code icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4772 gcc_assert (insn_operand_matches (icode
, 0, x
));
4773 gcc_assert (insn_operand_matches (icode
, 1, y
));
4774 gcc_assert (insn_operand_matches (icode
, 2, z
));
4776 return GEN_FCN (icode
) (x
, y
, z
);
4779 /* Return true if the target implements an addptr pattern and X, Y,
4780 and Z are valid for the pattern predicates. */
4783 have_addptr3_insn (rtx x
, rtx y
, rtx z
)
4785 enum insn_code icode
;
4787 gcc_assert (GET_MODE (x
) != VOIDmode
);
4789 icode
= optab_handler (addptr3_optab
, GET_MODE (x
));
4791 if (icode
== CODE_FOR_nothing
)
4794 if (!insn_operand_matches (icode
, 0, x
)
4795 || !insn_operand_matches (icode
, 1, y
)
4796 || !insn_operand_matches (icode
, 2, z
))
4802 /* Generate and return an insn body to subtract Y from X. */
4805 gen_sub2_insn (rtx x
, rtx y
)
4807 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (x
));
4809 gcc_assert (insn_operand_matches (icode
, 0, x
));
4810 gcc_assert (insn_operand_matches (icode
, 1, x
));
4811 gcc_assert (insn_operand_matches (icode
, 2, y
));
4813 return GEN_FCN (icode
) (x
, x
, y
);
4816 /* Generate and return an insn body to subtract r1 and c,
4817 storing the result in r0. */
4820 gen_sub3_insn (rtx r0
, rtx r1
, rtx c
)
4822 enum insn_code icode
= optab_handler (sub_optab
, GET_MODE (r0
));
4824 if (icode
== CODE_FOR_nothing
4825 || !insn_operand_matches (icode
, 0, r0
)
4826 || !insn_operand_matches (icode
, 1, r1
)
4827 || !insn_operand_matches (icode
, 2, c
))
4830 return GEN_FCN (icode
) (r0
, r1
, c
);
4834 have_sub2_insn (rtx x
, rtx y
)
4836 enum insn_code icode
;
4838 gcc_assert (GET_MODE (x
) != VOIDmode
);
4840 icode
= optab_handler (sub_optab
, GET_MODE (x
));
4842 if (icode
== CODE_FOR_nothing
)
4845 if (!insn_operand_matches (icode
, 0, x
)
4846 || !insn_operand_matches (icode
, 1, x
)
4847 || !insn_operand_matches (icode
, 2, y
))
4853 /* Return the insn code used to extend FROM_MODE to TO_MODE.
4854 UNSIGNEDP specifies zero-extension instead of sign-extension. If
4855 no such operation exists, CODE_FOR_nothing will be returned. */
4858 can_extend_p (machine_mode to_mode
, machine_mode from_mode
,
4862 #ifdef HAVE_ptr_extend
4864 return CODE_FOR_ptr_extend
;
4867 tab
= unsignedp
? zext_optab
: sext_optab
;
4868 return convert_optab_handler (tab
, to_mode
, from_mode
);
4871 /* Generate the body of an insn to extend Y (with mode MFROM)
4872 into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */
4875 gen_extend_insn (rtx x
, rtx y
, machine_mode mto
,
4876 machine_mode mfrom
, int unsignedp
)
4878 enum insn_code icode
= can_extend_p (mto
, mfrom
, unsignedp
);
4879 return GEN_FCN (icode
) (x
, y
);
4882 /* can_fix_p and can_float_p say whether the target machine
4883 can directly convert a given fixed point type to
4884 a given floating point type, or vice versa.
4885 The returned value is the CODE_FOR_... value to use,
4886 or CODE_FOR_nothing if these modes cannot be directly converted.
4888 *TRUNCP_PTR is set to 1 if it is necessary to output
4889 an explicit FTRUNC insn before the fix insn; otherwise 0. */
4891 static enum insn_code
4892 can_fix_p (machine_mode fixmode
, machine_mode fltmode
,
4893 int unsignedp
, int *truncp_ptr
)
4896 enum insn_code icode
;
4898 tab
= unsignedp
? ufixtrunc_optab
: sfixtrunc_optab
;
4899 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4900 if (icode
!= CODE_FOR_nothing
)
4906 /* FIXME: This requires a port to define both FIX and FTRUNC pattern
4907 for this to work. We need to rework the fix* and ftrunc* patterns
4908 and documentation. */
4909 tab
= unsignedp
? ufix_optab
: sfix_optab
;
4910 icode
= convert_optab_handler (tab
, fixmode
, fltmode
);
4911 if (icode
!= CODE_FOR_nothing
4912 && optab_handler (ftrunc_optab
, fltmode
) != CODE_FOR_nothing
)
4919 return CODE_FOR_nothing
;
4923 can_float_p (machine_mode fltmode
, machine_mode fixmode
,
4928 tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
4929 return convert_optab_handler (tab
, fltmode
, fixmode
);
4932 /* Function supportable_convert_operation
4934 Check whether an operation represented by the code CODE is a
4935 convert operation that is supported by the target platform in
4936 vector form (i.e., when operating on arguments of type VECTYPE_IN
4937 producing a result of type VECTYPE_OUT).
4939 Convert operations we currently support directly are FIX_TRUNC and FLOAT.
4940 This function checks if these operations are supported
4941 by the target platform either directly (via vector tree-codes), or via
4945 - CODE1 is code of vector operation to be used when
4946 vectorizing the operation, if available.
4947 - DECL is decl of target builtin functions to be used
4948 when vectorizing the operation, if available. In this case,
4949 CODE1 is CALL_EXPR. */
4952 supportable_convert_operation (enum tree_code code
,
4953 tree vectype_out
, tree vectype_in
,
4954 tree
*decl
, enum tree_code
*code1
)
4959 m1
= TYPE_MODE (vectype_out
);
4960 m2
= TYPE_MODE (vectype_in
);
4962 /* First check if we can done conversion directly. */
4963 if ((code
== FIX_TRUNC_EXPR
4964 && can_fix_p (m1
,m2
,TYPE_UNSIGNED (vectype_out
), &truncp
)
4965 != CODE_FOR_nothing
)
4966 || (code
== FLOAT_EXPR
4967 && can_float_p (m1
,m2
,TYPE_UNSIGNED (vectype_in
))
4968 != CODE_FOR_nothing
))
4974 /* Now check for builtin. */
4975 if (targetm
.vectorize
.builtin_conversion
4976 && targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
))
4979 *decl
= targetm
.vectorize
.builtin_conversion (code
, vectype_out
, vectype_in
);
4986 /* Generate code to convert FROM to floating point
4987 and store in TO. FROM must be fixed point and not VOIDmode.
4988 UNSIGNEDP nonzero means regard FROM as unsigned.
4989 Normally this is done by correcting the final value
4990 if it is negative. */
4993 expand_float (rtx to
, rtx from
, int unsignedp
)
4995 enum insn_code icode
;
4997 machine_mode fmode
, imode
;
4998 bool can_do_signed
= false;
5000 /* Crash now, because we won't be able to decide which mode to use. */
5001 gcc_assert (GET_MODE (from
) != VOIDmode
);
5003 /* Look for an insn to do the conversion. Do it in the specified
5004 modes if possible; otherwise convert either input, output or both to
5005 wider mode. If the integer mode is wider than the mode of FROM,
5006 we can do the conversion signed even if the input is unsigned. */
5008 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5009 fmode
= GET_MODE_WIDER_MODE (fmode
))
5010 for (imode
= GET_MODE (from
); imode
!= VOIDmode
;
5011 imode
= GET_MODE_WIDER_MODE (imode
))
5013 int doing_unsigned
= unsignedp
;
5015 if (fmode
!= GET_MODE (to
)
5016 && significand_size (fmode
) < GET_MODE_PRECISION (GET_MODE (from
)))
5019 icode
= can_float_p (fmode
, imode
, unsignedp
);
5020 if (icode
== CODE_FOR_nothing
&& unsignedp
)
5022 enum insn_code scode
= can_float_p (fmode
, imode
, 0);
5023 if (scode
!= CODE_FOR_nothing
)
5024 can_do_signed
= true;
5025 if (imode
!= GET_MODE (from
))
5026 icode
= scode
, doing_unsigned
= 0;
5029 if (icode
!= CODE_FOR_nothing
)
5031 if (imode
!= GET_MODE (from
))
5032 from
= convert_to_mode (imode
, from
, unsignedp
);
5034 if (fmode
!= GET_MODE (to
))
5035 target
= gen_reg_rtx (fmode
);
5037 emit_unop_insn (icode
, target
, from
,
5038 doing_unsigned
? UNSIGNED_FLOAT
: FLOAT
);
5041 convert_move (to
, target
, 0);
5046 /* Unsigned integer, and no way to convert directly. Convert as signed,
5047 then unconditionally adjust the result. */
5048 if (unsignedp
&& can_do_signed
)
5050 rtx_code_label
*label
= gen_label_rtx ();
5052 REAL_VALUE_TYPE offset
;
5054 /* Look for a usable floating mode FMODE wider than the source and at
5055 least as wide as the target. Using FMODE will avoid rounding woes
5056 with unsigned values greater than the signed maximum value. */
5058 for (fmode
= GET_MODE (to
); fmode
!= VOIDmode
;
5059 fmode
= GET_MODE_WIDER_MODE (fmode
))
5060 if (GET_MODE_PRECISION (GET_MODE (from
)) < GET_MODE_BITSIZE (fmode
)
5061 && can_float_p (fmode
, GET_MODE (from
), 0) != CODE_FOR_nothing
)
5064 if (fmode
== VOIDmode
)
5066 /* There is no such mode. Pretend the target is wide enough. */
5067 fmode
= GET_MODE (to
);
5069 /* Avoid double-rounding when TO is narrower than FROM. */
5070 if ((significand_size (fmode
) + 1)
5071 < GET_MODE_PRECISION (GET_MODE (from
)))
5074 rtx_code_label
*neglabel
= gen_label_rtx ();
5076 /* Don't use TARGET if it isn't a register, is a hard register,
5077 or is the wrong mode. */
5079 || REGNO (target
) < FIRST_PSEUDO_REGISTER
5080 || GET_MODE (target
) != fmode
)
5081 target
= gen_reg_rtx (fmode
);
5083 imode
= GET_MODE (from
);
5084 do_pending_stack_adjust ();
5086 /* Test whether the sign bit is set. */
5087 emit_cmp_and_jump_insns (from
, const0_rtx
, LT
, NULL_RTX
, imode
,
5090 /* The sign bit is not set. Convert as signed. */
5091 expand_float (target
, from
, 0);
5092 emit_jump_insn (gen_jump (label
));
5095 /* The sign bit is set.
5096 Convert to a usable (positive signed) value by shifting right
5097 one bit, while remembering if a nonzero bit was shifted
5098 out; i.e., compute (from & 1) | (from >> 1). */
5100 emit_label (neglabel
);
5101 temp
= expand_binop (imode
, and_optab
, from
, const1_rtx
,
5102 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
5103 temp1
= expand_shift (RSHIFT_EXPR
, imode
, from
, 1, NULL_RTX
, 1);
5104 temp
= expand_binop (imode
, ior_optab
, temp
, temp1
, temp
, 1,
5106 expand_float (target
, temp
, 0);
5108 /* Multiply by 2 to undo the shift above. */
5109 temp
= expand_binop (fmode
, add_optab
, target
, target
,
5110 target
, 0, OPTAB_LIB_WIDEN
);
5112 emit_move_insn (target
, temp
);
5114 do_pending_stack_adjust ();
5120 /* If we are about to do some arithmetic to correct for an
5121 unsigned operand, do it in a pseudo-register. */
5123 if (GET_MODE (to
) != fmode
5124 || !REG_P (to
) || REGNO (to
) < FIRST_PSEUDO_REGISTER
)
5125 target
= gen_reg_rtx (fmode
);
5127 /* Convert as signed integer to floating. */
5128 expand_float (target
, from
, 0);
5130 /* If FROM is negative (and therefore TO is negative),
5131 correct its value by 2**bitwidth. */
5133 do_pending_stack_adjust ();
5134 emit_cmp_and_jump_insns (from
, const0_rtx
, GE
, NULL_RTX
, GET_MODE (from
),
5138 real_2expN (&offset
, GET_MODE_PRECISION (GET_MODE (from
)), fmode
);
5139 temp
= expand_binop (fmode
, add_optab
, target
,
5140 CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
),
5141 target
, 0, OPTAB_LIB_WIDEN
);
5143 emit_move_insn (target
, temp
);
5145 do_pending_stack_adjust ();
5150 /* No hardware instruction available; call a library routine. */
5155 convert_optab tab
= unsignedp
? ufloat_optab
: sfloat_optab
;
5157 if (GET_MODE_PRECISION (GET_MODE (from
)) < GET_MODE_PRECISION (SImode
))
5158 from
= convert_to_mode (SImode
, from
, unsignedp
);
5160 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5161 gcc_assert (libfunc
);
5165 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5166 GET_MODE (to
), 1, from
,
5168 insns
= get_insns ();
5171 emit_libcall_block (insns
, target
, value
,
5172 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FLOAT
: FLOAT
,
5173 GET_MODE (to
), from
));
5178 /* Copy result to requested destination
5179 if we have been computing in a temp location. */
5183 if (GET_MODE (target
) == GET_MODE (to
))
5184 emit_move_insn (to
, target
);
5186 convert_move (to
, target
, 0);
5190 /* Generate code to convert FROM to fixed point and store in TO. FROM
5191 must be floating point. */
5194 expand_fix (rtx to
, rtx from
, int unsignedp
)
5196 enum insn_code icode
;
5198 machine_mode fmode
, imode
;
5201 /* We first try to find a pair of modes, one real and one integer, at
5202 least as wide as FROM and TO, respectively, in which we can open-code
5203 this conversion. If the integer mode is wider than the mode of TO,
5204 we can do the conversion either signed or unsigned. */
5206 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5207 fmode
= GET_MODE_WIDER_MODE (fmode
))
5208 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5209 imode
= GET_MODE_WIDER_MODE (imode
))
5211 int doing_unsigned
= unsignedp
;
5213 icode
= can_fix_p (imode
, fmode
, unsignedp
, &must_trunc
);
5214 if (icode
== CODE_FOR_nothing
&& imode
!= GET_MODE (to
) && unsignedp
)
5215 icode
= can_fix_p (imode
, fmode
, 0, &must_trunc
), doing_unsigned
= 0;
5217 if (icode
!= CODE_FOR_nothing
)
5219 rtx_insn
*last
= get_last_insn ();
5220 if (fmode
!= GET_MODE (from
))
5221 from
= convert_to_mode (fmode
, from
, 0);
5225 rtx temp
= gen_reg_rtx (GET_MODE (from
));
5226 from
= expand_unop (GET_MODE (from
), ftrunc_optab
, from
,
5230 if (imode
!= GET_MODE (to
))
5231 target
= gen_reg_rtx (imode
);
5233 if (maybe_emit_unop_insn (icode
, target
, from
,
5234 doing_unsigned
? UNSIGNED_FIX
: FIX
))
5237 convert_move (to
, target
, unsignedp
);
5240 delete_insns_since (last
);
5244 /* For an unsigned conversion, there is one more way to do it.
5245 If we have a signed conversion, we generate code that compares
5246 the real value to the largest representable positive number. If if
5247 is smaller, the conversion is done normally. Otherwise, subtract
5248 one plus the highest signed number, convert, and add it back.
5250 We only need to check all real modes, since we know we didn't find
5251 anything with a wider integer mode.
5253 This code used to extend FP value into mode wider than the destination.
5254 This is needed for decimal float modes which cannot accurately
5255 represent one plus the highest signed number of the same size, but
5256 not for binary modes. Consider, for instance conversion from SFmode
5259 The hot path through the code is dealing with inputs smaller than 2^63
5260 and doing just the conversion, so there is no bits to lose.
5262 In the other path we know the value is positive in the range 2^63..2^64-1
5263 inclusive. (as for other input overflow happens and result is undefined)
5264 So we know that the most important bit set in mantissa corresponds to
5265 2^63. The subtraction of 2^63 should not generate any rounding as it
5266 simply clears out that bit. The rest is trivial. */
5268 if (unsignedp
&& GET_MODE_PRECISION (GET_MODE (to
)) <= HOST_BITS_PER_WIDE_INT
)
5269 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5270 fmode
= GET_MODE_WIDER_MODE (fmode
))
5271 if (CODE_FOR_nothing
!= can_fix_p (GET_MODE (to
), fmode
, 0, &must_trunc
)
5272 && (!DECIMAL_FLOAT_MODE_P (fmode
)
5273 || GET_MODE_BITSIZE (fmode
) > GET_MODE_PRECISION (GET_MODE (to
))))
5276 REAL_VALUE_TYPE offset
;
5278 rtx_code_label
*lab1
, *lab2
;
5281 bitsize
= GET_MODE_PRECISION (GET_MODE (to
));
5282 real_2expN (&offset
, bitsize
- 1, fmode
);
5283 limit
= CONST_DOUBLE_FROM_REAL_VALUE (offset
, fmode
);
5284 lab1
= gen_label_rtx ();
5285 lab2
= gen_label_rtx ();
5287 if (fmode
!= GET_MODE (from
))
5288 from
= convert_to_mode (fmode
, from
, 0);
5290 /* See if we need to do the subtraction. */
5291 do_pending_stack_adjust ();
5292 emit_cmp_and_jump_insns (from
, limit
, GE
, NULL_RTX
, GET_MODE (from
),
5295 /* If not, do the signed "fix" and branch around fixup code. */
5296 expand_fix (to
, from
, 0);
5297 emit_jump_insn (gen_jump (lab2
));
5300 /* Otherwise, subtract 2**(N-1), convert to signed number,
5301 then add 2**(N-1). Do the addition using XOR since this
5302 will often generate better code. */
5304 target
= expand_binop (GET_MODE (from
), sub_optab
, from
, limit
,
5305 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
5306 expand_fix (to
, target
, 0);
5307 target
= expand_binop (GET_MODE (to
), xor_optab
, to
,
5309 ((HOST_WIDE_INT
) 1 << (bitsize
- 1),
5311 to
, 1, OPTAB_LIB_WIDEN
);
5314 emit_move_insn (to
, target
);
5318 if (optab_handler (mov_optab
, GET_MODE (to
)) != CODE_FOR_nothing
)
5320 /* Make a place for a REG_NOTE and add it. */
5321 insn
= emit_move_insn (to
, to
);
5322 set_dst_reg_note (insn
, REG_EQUAL
,
5323 gen_rtx_fmt_e (UNSIGNED_FIX
, GET_MODE (to
),
5331 /* We can't do it with an insn, so use a library call. But first ensure
5332 that the mode of TO is at least as wide as SImode, since those are the
5333 only library calls we know about. */
5335 if (GET_MODE_PRECISION (GET_MODE (to
)) < GET_MODE_PRECISION (SImode
))
5337 target
= gen_reg_rtx (SImode
);
5339 expand_fix (target
, from
, unsignedp
);
5347 convert_optab tab
= unsignedp
? ufix_optab
: sfix_optab
;
5348 libfunc
= convert_optab_libfunc (tab
, GET_MODE (to
), GET_MODE (from
));
5349 gcc_assert (libfunc
);
5353 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
,
5354 GET_MODE (to
), 1, from
,
5356 insns
= get_insns ();
5359 emit_libcall_block (insns
, target
, value
,
5360 gen_rtx_fmt_e (unsignedp
? UNSIGNED_FIX
: FIX
,
5361 GET_MODE (to
), from
));
5366 if (GET_MODE (to
) == GET_MODE (target
))
5367 emit_move_insn (to
, target
);
5369 convert_move (to
, target
, 0);
5373 /* Generate code to convert FROM or TO a fixed-point.
5374 If UINTP is true, either TO or FROM is an unsigned integer.
5375 If SATP is true, we need to saturate the result. */
5378 expand_fixed_convert (rtx to
, rtx from
, int uintp
, int satp
)
5380 machine_mode to_mode
= GET_MODE (to
);
5381 machine_mode from_mode
= GET_MODE (from
);
5383 enum rtx_code this_code
;
5384 enum insn_code code
;
5389 if (to_mode
== from_mode
)
5391 emit_move_insn (to
, from
);
5397 tab
= satp
? satfractuns_optab
: fractuns_optab
;
5398 this_code
= satp
? UNSIGNED_SAT_FRACT
: UNSIGNED_FRACT_CONVERT
;
5402 tab
= satp
? satfract_optab
: fract_optab
;
5403 this_code
= satp
? SAT_FRACT
: FRACT_CONVERT
;
5405 code
= convert_optab_handler (tab
, to_mode
, from_mode
);
5406 if (code
!= CODE_FOR_nothing
)
5408 emit_unop_insn (code
, to
, from
, this_code
);
5412 libfunc
= convert_optab_libfunc (tab
, to_mode
, from_mode
);
5413 gcc_assert (libfunc
);
5416 value
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_CONST
, to_mode
,
5417 1, from
, from_mode
);
5418 insns
= get_insns ();
5421 emit_libcall_block (insns
, to
, value
,
5422 gen_rtx_fmt_e (optab_to_code (tab
), to_mode
, from
));
5425 /* Generate code to convert FROM to fixed point and store in TO. FROM
5426 must be floating point, TO must be signed. Use the conversion optab
5427 TAB to do the conversion. */
5430 expand_sfix_optab (rtx to
, rtx from
, convert_optab tab
)
5432 enum insn_code icode
;
5434 machine_mode fmode
, imode
;
5436 /* We first try to find a pair of modes, one real and one integer, at
5437 least as wide as FROM and TO, respectively, in which we can open-code
5438 this conversion. If the integer mode is wider than the mode of TO,
5439 we can do the conversion either signed or unsigned. */
5441 for (fmode
= GET_MODE (from
); fmode
!= VOIDmode
;
5442 fmode
= GET_MODE_WIDER_MODE (fmode
))
5443 for (imode
= GET_MODE (to
); imode
!= VOIDmode
;
5444 imode
= GET_MODE_WIDER_MODE (imode
))
5446 icode
= convert_optab_handler (tab
, imode
, fmode
);
5447 if (icode
!= CODE_FOR_nothing
)
5449 rtx_insn
*last
= get_last_insn ();
5450 if (fmode
!= GET_MODE (from
))
5451 from
= convert_to_mode (fmode
, from
, 0);
5453 if (imode
!= GET_MODE (to
))
5454 target
= gen_reg_rtx (imode
);
5456 if (!maybe_emit_unop_insn (icode
, target
, from
, UNKNOWN
))
5458 delete_insns_since (last
);
5462 convert_move (to
, target
, 0);
5470 /* Report whether we have an instruction to perform the operation
5471 specified by CODE on operands of mode MODE. */
5473 have_insn_for (enum rtx_code code
, machine_mode mode
)
5475 return (code_to_optab (code
)
5476 && (optab_handler (code_to_optab (code
), mode
)
5477 != CODE_FOR_nothing
));
5480 /* Initialize the libfunc fields of an entire group of entries in some
5481 optab. Each entry is set equal to a string consisting of a leading
5482 pair of underscores followed by a generic operation name followed by
5483 a mode name (downshifted to lowercase) followed by a single character
5484 representing the number of operands for the given operation (which is
5485 usually one of the characters '2', '3', or '4').
5487 OPTABLE is the table in which libfunc fields are to be initialized.
5488 OPNAME is the generic (string) name of the operation.
5489 SUFFIX is the character which specifies the number of operands for
5490 the given generic operation.
5491 MODE is the mode to generate for.
5495 gen_libfunc (optab optable
, const char *opname
, int suffix
,
5498 unsigned opname_len
= strlen (opname
);
5499 const char *mname
= GET_MODE_NAME (mode
);
5500 unsigned mname_len
= strlen (mname
);
5501 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5502 int len
= prefix_len
+ opname_len
+ mname_len
+ 1 + 1;
5503 char *libfunc_name
= XALLOCAVEC (char, len
);
5510 if (targetm
.libfunc_gnu_prefix
)
5517 for (q
= opname
; *q
; )
5519 for (q
= mname
; *q
; q
++)
5520 *p
++ = TOLOWER (*q
);
5524 set_optab_libfunc (optable
, mode
,
5525 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5528 /* Like gen_libfunc, but verify that integer operation is involved. */
5531 gen_int_libfunc (optab optable
, const char *opname
, char suffix
,
5534 int maxsize
= 2 * BITS_PER_WORD
;
5535 int minsize
= BITS_PER_WORD
;
5537 if (GET_MODE_CLASS (mode
) != MODE_INT
)
5539 if (maxsize
< LONG_LONG_TYPE_SIZE
)
5540 maxsize
= LONG_LONG_TYPE_SIZE
;
5541 if (minsize
> INT_TYPE_SIZE
5542 && (trapv_binoptab_p (optable
)
5543 || trapv_unoptab_p (optable
)))
5544 minsize
= INT_TYPE_SIZE
;
5545 if (GET_MODE_BITSIZE (mode
) < minsize
5546 || GET_MODE_BITSIZE (mode
) > maxsize
)
5548 gen_libfunc (optable
, opname
, suffix
, mode
);
5551 /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */
5554 gen_fp_libfunc (optab optable
, const char *opname
, char suffix
,
5559 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5560 gen_libfunc (optable
, opname
, suffix
, mode
);
5561 if (DECIMAL_FLOAT_MODE_P (mode
))
5563 dec_opname
= XALLOCAVEC (char, sizeof (DECIMAL_PREFIX
) + strlen (opname
));
5564 /* For BID support, change the name to have either a bid_ or dpd_ prefix
5565 depending on the low level floating format used. */
5566 memcpy (dec_opname
, DECIMAL_PREFIX
, sizeof (DECIMAL_PREFIX
) - 1);
5567 strcpy (dec_opname
+ sizeof (DECIMAL_PREFIX
) - 1, opname
);
5568 gen_libfunc (optable
, dec_opname
, suffix
, mode
);
5572 /* Like gen_libfunc, but verify that fixed-point operation is involved. */
5575 gen_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5578 if (!ALL_FIXED_POINT_MODE_P (mode
))
5580 gen_libfunc (optable
, opname
, suffix
, mode
);
5583 /* Like gen_libfunc, but verify that signed fixed-point operation is
5587 gen_signed_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5590 if (!SIGNED_FIXED_POINT_MODE_P (mode
))
5592 gen_libfunc (optable
, opname
, suffix
, mode
);
5595 /* Like gen_libfunc, but verify that unsigned fixed-point operation is
5599 gen_unsigned_fixed_libfunc (optab optable
, const char *opname
, char suffix
,
5602 if (!UNSIGNED_FIXED_POINT_MODE_P (mode
))
5604 gen_libfunc (optable
, opname
, suffix
, mode
);
5607 /* Like gen_libfunc, but verify that FP or INT operation is involved. */
5610 gen_int_fp_libfunc (optab optable
, const char *name
, char suffix
,
5613 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5614 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5615 if (INTEGRAL_MODE_P (mode
))
5616 gen_int_libfunc (optable
, name
, suffix
, mode
);
5619 /* Like gen_libfunc, but verify that FP or INT operation is involved
5620 and add 'v' suffix for integer operation. */
5623 gen_intv_fp_libfunc (optab optable
, const char *name
, char suffix
,
5626 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5627 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5628 if (GET_MODE_CLASS (mode
) == MODE_INT
)
5630 int len
= strlen (name
);
5631 char *v_name
= XALLOCAVEC (char, len
+ 2);
5632 strcpy (v_name
, name
);
5634 v_name
[len
+ 1] = 0;
5635 gen_int_libfunc (optable
, v_name
, suffix
, mode
);
5639 /* Like gen_libfunc, but verify that FP or INT or FIXED operation is
5643 gen_int_fp_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5646 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5647 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5648 if (INTEGRAL_MODE_P (mode
))
5649 gen_int_libfunc (optable
, name
, suffix
, mode
);
5650 if (ALL_FIXED_POINT_MODE_P (mode
))
5651 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5654 /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is
5658 gen_int_fp_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5661 if (DECIMAL_FLOAT_MODE_P (mode
) || GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5662 gen_fp_libfunc (optable
, name
, suffix
, mode
);
5663 if (INTEGRAL_MODE_P (mode
))
5664 gen_int_libfunc (optable
, name
, suffix
, mode
);
5665 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5666 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5669 /* Like gen_libfunc, but verify that INT or FIXED operation is
5673 gen_int_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5676 if (INTEGRAL_MODE_P (mode
))
5677 gen_int_libfunc (optable
, name
, suffix
, mode
);
5678 if (ALL_FIXED_POINT_MODE_P (mode
))
5679 gen_fixed_libfunc (optable
, name
, suffix
, mode
);
5682 /* Like gen_libfunc, but verify that INT or signed FIXED operation is
5686 gen_int_signed_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5689 if (INTEGRAL_MODE_P (mode
))
5690 gen_int_libfunc (optable
, name
, suffix
, mode
);
5691 if (SIGNED_FIXED_POINT_MODE_P (mode
))
5692 gen_signed_fixed_libfunc (optable
, name
, suffix
, mode
);
5695 /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is
5699 gen_int_unsigned_fixed_libfunc (optab optable
, const char *name
, char suffix
,
5702 if (INTEGRAL_MODE_P (mode
))
5703 gen_int_libfunc (optable
, name
, suffix
, mode
);
5704 if (UNSIGNED_FIXED_POINT_MODE_P (mode
))
5705 gen_unsigned_fixed_libfunc (optable
, name
, suffix
, mode
);
5708 /* Initialize the libfunc fields of an entire group of entries of an
5709 inter-mode-class conversion optab. The string formation rules are
5710 similar to the ones for init_libfuncs, above, but instead of having
5711 a mode name and an operand count these functions have two mode names
5712 and no operand count. */
5715 gen_interclass_conv_libfunc (convert_optab tab
,
5720 size_t opname_len
= strlen (opname
);
5721 size_t mname_len
= 0;
5723 const char *fname
, *tname
;
5725 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5726 char *libfunc_name
, *suffix
;
5727 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5730 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5731 depends on which underlying decimal floating point format is used. */
5732 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5734 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5736 nondec_name
= XALLOCAVEC (char, prefix_len
+ opname_len
+ mname_len
+ 1 + 1);
5737 nondec_name
[0] = '_';
5738 nondec_name
[1] = '_';
5739 if (targetm
.libfunc_gnu_prefix
)
5741 nondec_name
[2] = 'g';
5742 nondec_name
[3] = 'n';
5743 nondec_name
[4] = 'u';
5744 nondec_name
[5] = '_';
5747 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5748 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5750 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5753 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5754 memcpy (&dec_name
[2+dec_len
], opname
, opname_len
);
5755 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5757 fname
= GET_MODE_NAME (fmode
);
5758 tname
= GET_MODE_NAME (tmode
);
5760 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5762 libfunc_name
= dec_name
;
5763 suffix
= dec_suffix
;
5767 libfunc_name
= nondec_name
;
5768 suffix
= nondec_suffix
;
5772 for (q
= fname
; *q
; p
++, q
++)
5774 for (q
= tname
; *q
; p
++, q
++)
5779 set_conv_libfunc (tab
, tmode
, fmode
,
5780 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5783 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5784 int->fp conversion. */
5787 gen_int_to_fp_conv_libfunc (convert_optab tab
,
5792 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5794 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5796 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5799 /* ufloat_optab is special by using floatun for FP and floatuns decimal fp
5803 gen_ufloat_conv_libfunc (convert_optab tab
,
5804 const char *opname ATTRIBUTE_UNUSED
,
5808 if (DECIMAL_FLOAT_MODE_P (tmode
))
5809 gen_int_to_fp_conv_libfunc (tab
, "floatuns", tmode
, fmode
);
5811 gen_int_to_fp_conv_libfunc (tab
, "floatun", tmode
, fmode
);
5814 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5815 fp->int conversion. */
5818 gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab
,
5823 if (GET_MODE_CLASS (fmode
) != MODE_INT
)
5825 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
)
5827 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5830 /* Same as gen_interclass_conv_libfunc but verify that we are producing
5831 fp->int conversion with no decimal floating point involved. */
5834 gen_fp_to_int_conv_libfunc (convert_optab tab
,
5839 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5841 if (GET_MODE_CLASS (tmode
) != MODE_INT
)
5843 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5846 /* Initialize the libfunc fields of an of an intra-mode-class conversion optab.
5847 The string formation rules are
5848 similar to the ones for init_libfunc, above. */
5851 gen_intraclass_conv_libfunc (convert_optab tab
, const char *opname
,
5852 machine_mode tmode
, machine_mode fmode
)
5854 size_t opname_len
= strlen (opname
);
5855 size_t mname_len
= 0;
5857 const char *fname
, *tname
;
5859 int prefix_len
= targetm
.libfunc_gnu_prefix
? 6 : 2;
5860 char *nondec_name
, *dec_name
, *nondec_suffix
, *dec_suffix
;
5861 char *libfunc_name
, *suffix
;
5864 /* If this is a decimal conversion, add the current BID vs. DPD prefix that
5865 depends on which underlying decimal floating point format is used. */
5866 const size_t dec_len
= sizeof (DECIMAL_PREFIX
) - 1;
5868 mname_len
= strlen (GET_MODE_NAME (tmode
)) + strlen (GET_MODE_NAME (fmode
));
5870 nondec_name
= XALLOCAVEC (char, 2 + opname_len
+ mname_len
+ 1 + 1);
5871 nondec_name
[0] = '_';
5872 nondec_name
[1] = '_';
5873 if (targetm
.libfunc_gnu_prefix
)
5875 nondec_name
[2] = 'g';
5876 nondec_name
[3] = 'n';
5877 nondec_name
[4] = 'u';
5878 nondec_name
[5] = '_';
5880 memcpy (&nondec_name
[prefix_len
], opname
, opname_len
);
5881 nondec_suffix
= nondec_name
+ opname_len
+ prefix_len
;
5883 dec_name
= XALLOCAVEC (char, 2 + dec_len
+ opname_len
+ mname_len
+ 1 + 1);
5886 memcpy (&dec_name
[2], DECIMAL_PREFIX
, dec_len
);
5887 memcpy (&dec_name
[2 + dec_len
], opname
, opname_len
);
5888 dec_suffix
= dec_name
+ dec_len
+ opname_len
+ 2;
5890 fname
= GET_MODE_NAME (fmode
);
5891 tname
= GET_MODE_NAME (tmode
);
5893 if (DECIMAL_FLOAT_MODE_P (fmode
) || DECIMAL_FLOAT_MODE_P (tmode
))
5895 libfunc_name
= dec_name
;
5896 suffix
= dec_suffix
;
5900 libfunc_name
= nondec_name
;
5901 suffix
= nondec_suffix
;
5905 for (q
= fname
; *q
; p
++, q
++)
5907 for (q
= tname
; *q
; p
++, q
++)
5913 set_conv_libfunc (tab
, tmode
, fmode
,
5914 ggc_alloc_string (libfunc_name
, p
- libfunc_name
));
5917 /* Pick proper libcall for trunc_optab. We need to chose if we do
5918 truncation or extension and interclass or intraclass. */
5921 gen_trunc_conv_libfunc (convert_optab tab
,
5926 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5928 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5933 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5934 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5935 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5937 if (GET_MODE_PRECISION (fmode
) <= GET_MODE_PRECISION (tmode
))
5940 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5941 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5942 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5943 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5946 /* Pick proper libcall for extend_optab. We need to chose if we do
5947 truncation or extension and interclass or intraclass. */
5950 gen_extend_conv_libfunc (convert_optab tab
,
5951 const char *opname ATTRIBUTE_UNUSED
,
5955 if (GET_MODE_CLASS (tmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (tmode
))
5957 if (GET_MODE_CLASS (fmode
) != MODE_FLOAT
&& !DECIMAL_FLOAT_MODE_P (fmode
))
5962 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (fmode
))
5963 || (GET_MODE_CLASS (fmode
) == MODE_FLOAT
&& DECIMAL_FLOAT_MODE_P (tmode
)))
5964 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5966 if (GET_MODE_PRECISION (fmode
) > GET_MODE_PRECISION (tmode
))
5969 if ((GET_MODE_CLASS (tmode
) == MODE_FLOAT
5970 && GET_MODE_CLASS (fmode
) == MODE_FLOAT
)
5971 || (DECIMAL_FLOAT_MODE_P (fmode
) && DECIMAL_FLOAT_MODE_P (tmode
)))
5972 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5975 /* Pick proper libcall for fract_optab. We need to chose if we do
5976 interclass or intraclass. */
5979 gen_fract_conv_libfunc (convert_optab tab
,
5986 if (!(ALL_FIXED_POINT_MODE_P (tmode
) || ALL_FIXED_POINT_MODE_P (fmode
)))
5989 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
5990 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5992 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
5995 /* Pick proper libcall for fractuns_optab. */
5998 gen_fractuns_conv_libfunc (convert_optab tab
,
6005 /* One mode must be a fixed-point mode, and the other must be an integer
6007 if (!((ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
)
6008 || (ALL_FIXED_POINT_MODE_P (fmode
)
6009 && GET_MODE_CLASS (tmode
) == MODE_INT
)))
6012 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6015 /* Pick proper libcall for satfract_optab. We need to chose if we do
6016 interclass or intraclass. */
6019 gen_satfract_conv_libfunc (convert_optab tab
,
6026 /* TMODE must be a fixed-point mode. */
6027 if (!ALL_FIXED_POINT_MODE_P (tmode
))
6030 if (GET_MODE_CLASS (tmode
) == GET_MODE_CLASS (fmode
))
6031 gen_intraclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6033 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6036 /* Pick proper libcall for satfractuns_optab. */
6039 gen_satfractuns_conv_libfunc (convert_optab tab
,
6046 /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */
6047 if (!(ALL_FIXED_POINT_MODE_P (tmode
) && GET_MODE_CLASS (fmode
) == MODE_INT
))
6050 gen_interclass_conv_libfunc (tab
, opname
, tmode
, fmode
);
6053 /* Hashtable callbacks for libfunc_decls. */
6055 struct libfunc_decl_hasher
: ggc_hasher
<tree
>
6060 return IDENTIFIER_HASH_VALUE (DECL_NAME (entry
));
6064 equal (tree decl
, tree name
)
6066 return DECL_NAME (decl
) == name
;
6070 /* A table of previously-created libfuncs, hashed by name. */
6071 static GTY (()) hash_table
<libfunc_decl_hasher
> *libfunc_decls
;
6073 /* Build a decl for a libfunc named NAME. */
6076 build_libfunc_function (const char *name
)
6078 tree decl
= build_decl (UNKNOWN_LOCATION
, FUNCTION_DECL
,
6079 get_identifier (name
),
6080 build_function_type (integer_type_node
, NULL_TREE
));
6081 /* ??? We don't have any type information except for this is
6082 a function. Pretend this is "int foo()". */
6083 DECL_ARTIFICIAL (decl
) = 1;
6084 DECL_EXTERNAL (decl
) = 1;
6085 TREE_PUBLIC (decl
) = 1;
6086 gcc_assert (DECL_ASSEMBLER_NAME (decl
));
6088 /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with
6089 are the flags assigned by targetm.encode_section_info. */
6090 SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl
), 0), NULL
);
6096 init_one_libfunc (const char *name
)
6101 if (libfunc_decls
== NULL
)
6102 libfunc_decls
= hash_table
<libfunc_decl_hasher
>::create_ggc (37);
6104 /* See if we have already created a libfunc decl for this function. */
6105 id
= get_identifier (name
);
6106 hash
= IDENTIFIER_HASH_VALUE (id
);
6107 tree
*slot
= libfunc_decls
->find_slot_with_hash (id
, hash
, INSERT
);
6111 /* Create a new decl, so that it can be passed to
6112 targetm.encode_section_info. */
6113 decl
= build_libfunc_function (name
);
6116 return XEXP (DECL_RTL (decl
), 0);
6119 /* Adjust the assembler name of libfunc NAME to ASMSPEC. */
6122 set_user_assembler_libfunc (const char *name
, const char *asmspec
)
6127 id
= get_identifier (name
);
6128 hash
= IDENTIFIER_HASH_VALUE (id
);
6129 tree
*slot
= libfunc_decls
->find_slot_with_hash (id
, hash
, NO_INSERT
);
6131 decl
= (tree
) *slot
;
6132 set_user_assembler_name (decl
, asmspec
);
6133 return XEXP (DECL_RTL (decl
), 0);
6136 /* Call this to reset the function entry for one optab (OPTABLE) in mode
6137 MODE to NAME, which should be either 0 or a string constant. */
6139 set_optab_libfunc (optab op
, machine_mode mode
, const char *name
)
6142 struct libfunc_entry e
;
6143 struct libfunc_entry
**slot
;
6150 val
= init_one_libfunc (name
);
6153 slot
= libfunc_hash
->find_slot (&e
, INSERT
);
6155 *slot
= ggc_alloc
<libfunc_entry
> ();
6157 (*slot
)->mode1
= mode
;
6158 (*slot
)->mode2
= VOIDmode
;
6159 (*slot
)->libfunc
= val
;
6162 /* Call this to reset the function entry for one conversion optab
6163 (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be
6164 either 0 or a string constant. */
6166 set_conv_libfunc (convert_optab optab
, machine_mode tmode
,
6167 machine_mode fmode
, const char *name
)
6170 struct libfunc_entry e
;
6171 struct libfunc_entry
**slot
;
6178 val
= init_one_libfunc (name
);
6181 slot
= libfunc_hash
->find_slot (&e
, INSERT
);
6183 *slot
= ggc_alloc
<libfunc_entry
> ();
6184 (*slot
)->op
= optab
;
6185 (*slot
)->mode1
= tmode
;
6186 (*slot
)->mode2
= fmode
;
6187 (*slot
)->libfunc
= val
;
6190 /* Call this to initialize the contents of the optabs
6191 appropriately for the current target machine. */
6197 libfunc_hash
->empty ();
6199 libfunc_hash
= hash_table
<libfunc_hasher
>::create_ggc (10);
6201 /* Fill in the optabs with the insns we support. */
6202 init_all_optabs (this_fn_optabs
);
6204 /* The ffs function operates on `int'. Fall back on it if we do not
6205 have a libgcc2 function for that width. */
6206 if (INT_TYPE_SIZE
< BITS_PER_WORD
)
6207 set_optab_libfunc (ffs_optab
, mode_for_size (INT_TYPE_SIZE
, MODE_INT
, 0),
6210 /* Explicitly initialize the bswap libfuncs since we need them to be
6211 valid for things other than word_mode. */
6212 if (targetm
.libfunc_gnu_prefix
)
6214 set_optab_libfunc (bswap_optab
, SImode
, "__gnu_bswapsi2");
6215 set_optab_libfunc (bswap_optab
, DImode
, "__gnu_bswapdi2");
6219 set_optab_libfunc (bswap_optab
, SImode
, "__bswapsi2");
6220 set_optab_libfunc (bswap_optab
, DImode
, "__bswapdi2");
6223 /* Use cabs for double complex abs, since systems generally have cabs.
6224 Don't define any libcall for float complex, so that cabs will be used. */
6225 if (complex_double_type_node
)
6226 set_optab_libfunc (abs_optab
, TYPE_MODE (complex_double_type_node
),
6229 abort_libfunc
= init_one_libfunc ("abort");
6230 memcpy_libfunc
= init_one_libfunc ("memcpy");
6231 memmove_libfunc
= init_one_libfunc ("memmove");
6232 memcmp_libfunc
= init_one_libfunc ("memcmp");
6233 memset_libfunc
= init_one_libfunc ("memset");
6234 setbits_libfunc
= init_one_libfunc ("__setbits");
6236 #ifndef DONT_USE_BUILTIN_SETJMP
6237 setjmp_libfunc
= init_one_libfunc ("__builtin_setjmp");
6238 longjmp_libfunc
= init_one_libfunc ("__builtin_longjmp");
6240 setjmp_libfunc
= init_one_libfunc ("setjmp");
6241 longjmp_libfunc
= init_one_libfunc ("longjmp");
6243 unwind_sjlj_register_libfunc
= init_one_libfunc ("_Unwind_SjLj_Register");
6244 unwind_sjlj_unregister_libfunc
6245 = init_one_libfunc ("_Unwind_SjLj_Unregister");
6247 /* For function entry/exit instrumentation. */
6248 profile_function_entry_libfunc
6249 = init_one_libfunc ("__cyg_profile_func_enter");
6250 profile_function_exit_libfunc
6251 = init_one_libfunc ("__cyg_profile_func_exit");
6253 gcov_flush_libfunc
= init_one_libfunc ("__gcov_flush");
6255 /* Allow the target to add more libcalls or rename some, etc. */
6256 targetm
.init_libfuncs ();
6259 /* Use the current target and options to initialize
6260 TREE_OPTIMIZATION_OPTABS (OPTNODE). */
6263 init_tree_optimization_optabs (tree optnode
)
6265 /* Quick exit if we have already computed optabs for this target. */
6266 if (TREE_OPTIMIZATION_BASE_OPTABS (optnode
) == this_target_optabs
)
6269 /* Forget any previous information and set up for the current target. */
6270 TREE_OPTIMIZATION_BASE_OPTABS (optnode
) = this_target_optabs
;
6271 struct target_optabs
*tmp_optabs
= (struct target_optabs
*)
6272 TREE_OPTIMIZATION_OPTABS (optnode
);
6274 memset (tmp_optabs
, 0, sizeof (struct target_optabs
));
6276 tmp_optabs
= ggc_alloc
<target_optabs
> ();
6278 /* Generate a new set of optabs into tmp_optabs. */
6279 init_all_optabs (tmp_optabs
);
6281 /* If the optabs changed, record it. */
6282 if (memcmp (tmp_optabs
, this_target_optabs
, sizeof (struct target_optabs
)))
6283 TREE_OPTIMIZATION_OPTABS (optnode
) = tmp_optabs
;
6286 TREE_OPTIMIZATION_OPTABS (optnode
) = NULL
;
6287 ggc_free (tmp_optabs
);
6291 /* A helper function for init_sync_libfuncs. Using the basename BASE,
6292 install libfuncs into TAB for BASE_N for 1 <= N <= MAX. */
6295 init_sync_libfuncs_1 (optab tab
, const char *base
, int max
)
6299 size_t len
= strlen (base
);
6302 gcc_assert (max
<= 8);
6303 gcc_assert (len
+ 3 < sizeof (buf
));
6305 memcpy (buf
, base
, len
);
6308 buf
[len
+ 2] = '\0';
6311 for (i
= 1; i
<= max
; i
*= 2)
6313 buf
[len
+ 1] = '0' + i
;
6314 set_optab_libfunc (tab
, mode
, buf
);
6315 mode
= GET_MODE_2XWIDER_MODE (mode
);
6320 init_sync_libfuncs (int max
)
6322 if (!flag_sync_libcalls
)
6325 init_sync_libfuncs_1 (sync_compare_and_swap_optab
,
6326 "__sync_val_compare_and_swap", max
);
6327 init_sync_libfuncs_1 (sync_lock_test_and_set_optab
,
6328 "__sync_lock_test_and_set", max
);
6330 init_sync_libfuncs_1 (sync_old_add_optab
, "__sync_fetch_and_add", max
);
6331 init_sync_libfuncs_1 (sync_old_sub_optab
, "__sync_fetch_and_sub", max
);
6332 init_sync_libfuncs_1 (sync_old_ior_optab
, "__sync_fetch_and_or", max
);
6333 init_sync_libfuncs_1 (sync_old_and_optab
, "__sync_fetch_and_and", max
);
6334 init_sync_libfuncs_1 (sync_old_xor_optab
, "__sync_fetch_and_xor", max
);
6335 init_sync_libfuncs_1 (sync_old_nand_optab
, "__sync_fetch_and_nand", max
);
6337 init_sync_libfuncs_1 (sync_new_add_optab
, "__sync_add_and_fetch", max
);
6338 init_sync_libfuncs_1 (sync_new_sub_optab
, "__sync_sub_and_fetch", max
);
6339 init_sync_libfuncs_1 (sync_new_ior_optab
, "__sync_or_and_fetch", max
);
6340 init_sync_libfuncs_1 (sync_new_and_optab
, "__sync_and_and_fetch", max
);
6341 init_sync_libfuncs_1 (sync_new_xor_optab
, "__sync_xor_and_fetch", max
);
6342 init_sync_libfuncs_1 (sync_new_nand_optab
, "__sync_nand_and_fetch", max
);
6345 /* Print information about the current contents of the optabs on
6349 debug_optab_libfuncs (void)
6353 /* Dump the arithmetic optabs. */
6354 for (i
= FIRST_NORM_OPTAB
; i
<= LAST_NORMLIB_OPTAB
; ++i
)
6355 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6357 rtx l
= optab_libfunc ((optab
) i
, (machine_mode
) j
);
6360 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6361 fprintf (stderr
, "%s\t%s:\t%s\n",
6362 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6368 /* Dump the conversion optabs. */
6369 for (i
= FIRST_CONV_OPTAB
; i
<= LAST_CONVLIB_OPTAB
; ++i
)
6370 for (j
= 0; j
< NUM_MACHINE_MODES
; ++j
)
6371 for (k
= 0; k
< NUM_MACHINE_MODES
; ++k
)
6373 rtx l
= convert_optab_libfunc ((optab
) i
, (machine_mode
) j
,
6377 gcc_assert (GET_CODE (l
) == SYMBOL_REF
);
6378 fprintf (stderr
, "%s\t%s\t%s:\t%s\n",
6379 GET_RTX_NAME (optab_to_code ((optab
) i
)),
6388 /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition
6389 CODE. Return 0 on failure. */
6392 gen_cond_trap (enum rtx_code code
, rtx op1
, rtx op2
, rtx tcode
)
6394 machine_mode mode
= GET_MODE (op1
);
6395 enum insn_code icode
;
6399 if (mode
== VOIDmode
)
6402 icode
= optab_handler (ctrap_optab
, mode
);
6403 if (icode
== CODE_FOR_nothing
)
6406 /* Some targets only accept a zero trap code. */
6407 if (!insn_operand_matches (icode
, 3, tcode
))
6410 do_pending_stack_adjust ();
6412 prepare_cmp_insn (op1
, op2
, code
, NULL_RTX
, false, OPTAB_DIRECT
,
6417 insn
= GEN_FCN (icode
) (trap_rtx
, XEXP (trap_rtx
, 0), XEXP (trap_rtx
, 1),
6420 /* If that failed, then give up. */
6428 insn
= get_insns ();
6433 /* Return rtx code for TCODE. Use UNSIGNEDP to select signed
6434 or unsigned operation code. */
6437 get_rtx_code (enum tree_code tcode
, bool unsignedp
)
6449 code
= unsignedp
? LTU
: LT
;
6452 code
= unsignedp
? LEU
: LE
;
6455 code
= unsignedp
? GTU
: GT
;
6458 code
= unsignedp
? GEU
: GE
;
6461 case UNORDERED_EXPR
:
6500 /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or
6501 unsigned operators. Do not generate compare instruction. */
6504 vector_compare_rtx (enum tree_code tcode
, tree t_op0
, tree t_op1
,
6505 bool unsignedp
, enum insn_code icode
)
6507 struct expand_operand ops
[2];
6508 rtx rtx_op0
, rtx_op1
;
6509 machine_mode m0
, m1
;
6510 enum rtx_code rcode
= get_rtx_code (tcode
, unsignedp
);
6512 gcc_assert (TREE_CODE_CLASS (tcode
) == tcc_comparison
);
6514 /* Expand operands. For vector types with scalar modes, e.g. where int64x1_t
6515 has mode DImode, this can produce a constant RTX of mode VOIDmode; in such
6516 cases, use the original mode. */
6517 rtx_op0
= expand_expr (t_op0
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op0
)),
6519 m0
= GET_MODE (rtx_op0
);
6521 m0
= TYPE_MODE (TREE_TYPE (t_op0
));
6523 rtx_op1
= expand_expr (t_op1
, NULL_RTX
, TYPE_MODE (TREE_TYPE (t_op1
)),
6525 m1
= GET_MODE (rtx_op1
);
6527 m1
= TYPE_MODE (TREE_TYPE (t_op1
));
6529 create_input_operand (&ops
[0], rtx_op0
, m0
);
6530 create_input_operand (&ops
[1], rtx_op1
, m1
);
6531 if (!maybe_legitimize_operands (icode
, 4, 2, ops
))
6533 return gen_rtx_fmt_ee (rcode
, VOIDmode
, ops
[0].value
, ops
[1].value
);
6536 /* Return true if VEC_PERM_EXPR of arbitrary input vectors can be expanded using
6537 SIMD extensions of the CPU. SEL may be NULL, which stands for an unknown
6538 constant. Note that additional permutations representing whole-vector shifts
6539 may also be handled via the vec_shr optab, but only where the second input
6540 vector is entirely constant zeroes; this case is not dealt with here. */
6543 can_vec_perm_p (machine_mode mode
, bool variable
,
6544 const unsigned char *sel
)
6546 machine_mode qimode
;
6548 /* If the target doesn't implement a vector mode for the vector type,
6549 then no operations are supported. */
6550 if (!VECTOR_MODE_P (mode
))
6555 if (direct_optab_handler (vec_perm_const_optab
, mode
) != CODE_FOR_nothing
6557 || targetm
.vectorize
.vec_perm_const_ok
== NULL
6558 || targetm
.vectorize
.vec_perm_const_ok (mode
, sel
)))
6562 if (direct_optab_handler (vec_perm_optab
, mode
) != CODE_FOR_nothing
)
6565 /* We allow fallback to a QI vector mode, and adjust the mask. */
6566 if (GET_MODE_INNER (mode
) == QImode
)
6568 qimode
= mode_for_vector (QImode
, GET_MODE_SIZE (mode
));
6569 if (!VECTOR_MODE_P (qimode
))
6572 /* ??? For completeness, we ought to check the QImode version of
6573 vec_perm_const_optab. But all users of this implicit lowering
6574 feature implement the variable vec_perm_optab. */
6575 if (direct_optab_handler (vec_perm_optab
, qimode
) == CODE_FOR_nothing
)
6578 /* In order to support the lowering of variable permutations,
6579 we need to support shifts and adds. */
6582 if (GET_MODE_UNIT_SIZE (mode
) > 2
6583 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
6584 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
)
6586 if (optab_handler (add_optab
, qimode
) == CODE_FOR_nothing
)
6593 /* Checks if vec_perm mask SEL is a constant equivalent to a shift of the first
6594 vec_perm operand, assuming the second operand is a constant vector of zeroes.
6595 Return the shift distance in bits if so, or NULL_RTX if the vec_perm is not a
6598 shift_amt_for_vec_perm_mask (rtx sel
)
6600 unsigned int i
, first
, nelt
= GET_MODE_NUNITS (GET_MODE (sel
));
6601 unsigned int bitsize
= GET_MODE_BITSIZE (GET_MODE_INNER (GET_MODE (sel
)));
6603 if (GET_CODE (sel
) != CONST_VECTOR
)
6606 first
= INTVAL (CONST_VECTOR_ELT (sel
, 0));
6607 if (first
>= 2*nelt
)
6609 for (i
= 1; i
< nelt
; i
++)
6611 int idx
= INTVAL (CONST_VECTOR_ELT (sel
, i
));
6612 unsigned int expected
= (i
+ first
) & (2 * nelt
- 1);
6613 /* Indices into the second vector are all equivalent. */
6614 if (idx
< 0 || (MIN (nelt
, (unsigned) idx
) != MIN (nelt
, expected
)))
6618 return GEN_INT (first
* bitsize
);
6621 /* A subroutine of expand_vec_perm for expanding one vec_perm insn. */
6624 expand_vec_perm_1 (enum insn_code icode
, rtx target
,
6625 rtx v0
, rtx v1
, rtx sel
)
6627 machine_mode tmode
= GET_MODE (target
);
6628 machine_mode smode
= GET_MODE (sel
);
6629 struct expand_operand ops
[4];
6631 create_output_operand (&ops
[0], target
, tmode
);
6632 create_input_operand (&ops
[3], sel
, smode
);
6634 /* Make an effort to preserve v0 == v1. The target expander is able to
6635 rely on this to determine if we're permuting a single input operand. */
6636 if (rtx_equal_p (v0
, v1
))
6638 if (!insn_operand_matches (icode
, 1, v0
))
6639 v0
= force_reg (tmode
, v0
);
6640 gcc_checking_assert (insn_operand_matches (icode
, 1, v0
));
6641 gcc_checking_assert (insn_operand_matches (icode
, 2, v0
));
6643 create_fixed_operand (&ops
[1], v0
);
6644 create_fixed_operand (&ops
[2], v0
);
6648 create_input_operand (&ops
[1], v0
, tmode
);
6649 /* See if this can be handled with a vec_shr. We only do this if the
6650 second vector is all zeroes. */
6651 enum insn_code shift_code
= optab_handler (vec_shr_optab
, GET_MODE (v0
));
6652 if (v1
== CONST0_RTX (GET_MODE (v1
)) && shift_code
)
6653 if (rtx shift_amt
= shift_amt_for_vec_perm_mask (sel
))
6655 create_convert_operand_from_type (&ops
[2], shift_amt
,
6656 sizetype_tab
[(int) stk_sizetype
]);
6657 if (maybe_expand_insn (shift_code
, 3, ops
))
6658 return ops
[0].value
;
6660 create_input_operand (&ops
[2], v1
, tmode
);
6663 if (maybe_expand_insn (icode
, 4, ops
))
6664 return ops
[0].value
;
6668 /* Generate instructions for vec_perm optab given its mode
6669 and three operands. */
6672 expand_vec_perm (machine_mode mode
, rtx v0
, rtx v1
, rtx sel
, rtx target
)
6674 enum insn_code icode
;
6675 machine_mode qimode
;
6676 unsigned int i
, w
, e
, u
;
6677 rtx tmp
, sel_qi
= NULL
;
6680 if (!target
|| GET_MODE (target
) != mode
)
6681 target
= gen_reg_rtx (mode
);
6683 w
= GET_MODE_SIZE (mode
);
6684 e
= GET_MODE_NUNITS (mode
);
6685 u
= GET_MODE_UNIT_SIZE (mode
);
6687 /* Set QIMODE to a different vector mode with byte elements.
6688 If no such mode, or if MODE already has byte elements, use VOIDmode. */
6690 if (GET_MODE_INNER (mode
) != QImode
)
6692 qimode
= mode_for_vector (QImode
, w
);
6693 if (!VECTOR_MODE_P (qimode
))
6697 /* If the input is a constant, expand it specially. */
6698 gcc_assert (GET_MODE_CLASS (GET_MODE (sel
)) == MODE_VECTOR_INT
);
6699 if (GET_CODE (sel
) == CONST_VECTOR
)
6701 icode
= direct_optab_handler (vec_perm_const_optab
, mode
);
6702 if (icode
!= CODE_FOR_nothing
)
6704 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6709 /* Fall back to a constant byte-based permutation. */
6710 if (qimode
!= VOIDmode
)
6712 vec
= rtvec_alloc (w
);
6713 for (i
= 0; i
< e
; ++i
)
6715 unsigned int j
, this_e
;
6717 this_e
= INTVAL (CONST_VECTOR_ELT (sel
, i
));
6718 this_e
&= 2 * e
- 1;
6721 for (j
= 0; j
< u
; ++j
)
6722 RTVEC_ELT (vec
, i
* u
+ j
) = GEN_INT (this_e
+ j
);
6724 sel_qi
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6726 icode
= direct_optab_handler (vec_perm_const_optab
, qimode
);
6727 if (icode
!= CODE_FOR_nothing
)
6729 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6730 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6731 gen_lowpart (qimode
, v1
), sel_qi
);
6733 return gen_lowpart (mode
, tmp
);
6738 /* Otherwise expand as a fully variable permuation. */
6739 icode
= direct_optab_handler (vec_perm_optab
, mode
);
6740 if (icode
!= CODE_FOR_nothing
)
6742 tmp
= expand_vec_perm_1 (icode
, target
, v0
, v1
, sel
);
6747 /* As a special case to aid several targets, lower the element-based
6748 permutation to a byte-based permutation and try again. */
6749 if (qimode
== VOIDmode
)
6751 icode
= direct_optab_handler (vec_perm_optab
, qimode
);
6752 if (icode
== CODE_FOR_nothing
)
6757 /* Multiply each element by its byte size. */
6758 machine_mode selmode
= GET_MODE (sel
);
6760 sel
= expand_simple_binop (selmode
, PLUS
, sel
, sel
,
6761 NULL
, 0, OPTAB_DIRECT
);
6763 sel
= expand_simple_binop (selmode
, ASHIFT
, sel
,
6764 GEN_INT (exact_log2 (u
)),
6765 NULL
, 0, OPTAB_DIRECT
);
6766 gcc_assert (sel
!= NULL
);
6768 /* Broadcast the low byte each element into each of its bytes. */
6769 vec
= rtvec_alloc (w
);
6770 for (i
= 0; i
< w
; ++i
)
6772 int this_e
= i
/ u
* u
;
6773 if (BYTES_BIG_ENDIAN
)
6775 RTVEC_ELT (vec
, i
) = GEN_INT (this_e
);
6777 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6778 sel
= gen_lowpart (qimode
, sel
);
6779 sel
= expand_vec_perm (qimode
, sel
, sel
, tmp
, NULL
);
6780 gcc_assert (sel
!= NULL
);
6782 /* Add the byte offset to each byte element. */
6783 /* Note that the definition of the indicies here is memory ordering,
6784 so there should be no difference between big and little endian. */
6785 vec
= rtvec_alloc (w
);
6786 for (i
= 0; i
< w
; ++i
)
6787 RTVEC_ELT (vec
, i
) = GEN_INT (i
% u
);
6788 tmp
= gen_rtx_CONST_VECTOR (qimode
, vec
);
6789 sel_qi
= expand_simple_binop (qimode
, PLUS
, sel
, tmp
,
6790 sel
, 0, OPTAB_DIRECT
);
6791 gcc_assert (sel_qi
!= NULL
);
6794 tmp
= mode
!= qimode
? gen_reg_rtx (qimode
) : target
;
6795 tmp
= expand_vec_perm_1 (icode
, tmp
, gen_lowpart (qimode
, v0
),
6796 gen_lowpart (qimode
, v1
), sel_qi
);
6798 tmp
= gen_lowpart (mode
, tmp
);
6802 /* Return insn code for a conditional operator with a comparison in
6803 mode CMODE, unsigned if UNS is true, resulting in a value of mode VMODE. */
6805 static inline enum insn_code
6806 get_vcond_icode (machine_mode vmode
, machine_mode cmode
, bool uns
)
6808 enum insn_code icode
= CODE_FOR_nothing
;
6810 icode
= convert_optab_handler (vcondu_optab
, vmode
, cmode
);
6812 icode
= convert_optab_handler (vcond_optab
, vmode
, cmode
);
6816 /* Return TRUE iff, appropriate vector insns are available
6817 for vector cond expr with vector type VALUE_TYPE and a comparison
6818 with operand vector types in CMP_OP_TYPE. */
6821 expand_vec_cond_expr_p (tree value_type
, tree cmp_op_type
)
6823 machine_mode value_mode
= TYPE_MODE (value_type
);
6824 machine_mode cmp_op_mode
= TYPE_MODE (cmp_op_type
);
6825 if (GET_MODE_SIZE (value_mode
) != GET_MODE_SIZE (cmp_op_mode
)
6826 || GET_MODE_NUNITS (value_mode
) != GET_MODE_NUNITS (cmp_op_mode
)
6827 || get_vcond_icode (TYPE_MODE (value_type
), TYPE_MODE (cmp_op_type
),
6828 TYPE_UNSIGNED (cmp_op_type
)) == CODE_FOR_nothing
)
6833 /* Generate insns for a VEC_COND_EXPR, given its TYPE and its
6837 expand_vec_cond_expr (tree vec_cond_type
, tree op0
, tree op1
, tree op2
,
6840 struct expand_operand ops
[6];
6841 enum insn_code icode
;
6842 rtx comparison
, rtx_op1
, rtx_op2
;
6843 machine_mode mode
= TYPE_MODE (vec_cond_type
);
6844 machine_mode cmp_op_mode
;
6847 enum tree_code tcode
;
6849 if (COMPARISON_CLASS_P (op0
))
6851 op0a
= TREE_OPERAND (op0
, 0);
6852 op0b
= TREE_OPERAND (op0
, 1);
6853 tcode
= TREE_CODE (op0
);
6858 gcc_assert (!TYPE_UNSIGNED (TREE_TYPE (op0
)));
6860 op0b
= build_zero_cst (TREE_TYPE (op0
));
6863 unsignedp
= TYPE_UNSIGNED (TREE_TYPE (op0a
));
6864 cmp_op_mode
= TYPE_MODE (TREE_TYPE (op0a
));
6867 gcc_assert (GET_MODE_SIZE (mode
) == GET_MODE_SIZE (cmp_op_mode
)
6868 && GET_MODE_NUNITS (mode
) == GET_MODE_NUNITS (cmp_op_mode
));
6870 icode
= get_vcond_icode (mode
, cmp_op_mode
, unsignedp
);
6871 if (icode
== CODE_FOR_nothing
)
6874 comparison
= vector_compare_rtx (tcode
, op0a
, op0b
, unsignedp
, icode
);
6875 rtx_op1
= expand_normal (op1
);
6876 rtx_op2
= expand_normal (op2
);
6878 create_output_operand (&ops
[0], target
, mode
);
6879 create_input_operand (&ops
[1], rtx_op1
, mode
);
6880 create_input_operand (&ops
[2], rtx_op2
, mode
);
6881 create_fixed_operand (&ops
[3], comparison
);
6882 create_fixed_operand (&ops
[4], XEXP (comparison
, 0));
6883 create_fixed_operand (&ops
[5], XEXP (comparison
, 1));
6884 expand_insn (icode
, 6, ops
);
6885 return ops
[0].value
;
6888 /* Return non-zero if a highpart multiply is supported of can be synthisized.
6889 For the benefit of expand_mult_highpart, the return value is 1 for direct,
6890 2 for even/odd widening, and 3 for hi/lo widening. */
6893 can_mult_highpart_p (machine_mode mode
, bool uns_p
)
6899 op
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6900 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6903 /* If the mode is an integral vector, synth from widening operations. */
6904 if (GET_MODE_CLASS (mode
) != MODE_VECTOR_INT
)
6907 nunits
= GET_MODE_NUNITS (mode
);
6908 sel
= XALLOCAVEC (unsigned char, nunits
);
6910 op
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6911 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6913 op
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6914 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6916 for (i
= 0; i
< nunits
; ++i
)
6917 sel
[i
] = !BYTES_BIG_ENDIAN
+ (i
& ~1) + ((i
& 1) ? nunits
: 0);
6918 if (can_vec_perm_p (mode
, false, sel
))
6923 op
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6924 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6926 op
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6927 if (optab_handler (op
, mode
) != CODE_FOR_nothing
)
6929 for (i
= 0; i
< nunits
; ++i
)
6930 sel
[i
] = 2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1);
6931 if (can_vec_perm_p (mode
, false, sel
))
6939 /* Expand a highpart multiply. */
6942 expand_mult_highpart (machine_mode mode
, rtx op0
, rtx op1
,
6943 rtx target
, bool uns_p
)
6945 struct expand_operand eops
[3];
6946 enum insn_code icode
;
6947 int method
, i
, nunits
;
6953 method
= can_mult_highpart_p (mode
, uns_p
);
6959 tab1
= uns_p
? umul_highpart_optab
: smul_highpart_optab
;
6960 return expand_binop (mode
, tab1
, op0
, op1
, target
, uns_p
,
6963 tab1
= uns_p
? vec_widen_umult_even_optab
: vec_widen_smult_even_optab
;
6964 tab2
= uns_p
? vec_widen_umult_odd_optab
: vec_widen_smult_odd_optab
;
6967 tab1
= uns_p
? vec_widen_umult_lo_optab
: vec_widen_smult_lo_optab
;
6968 tab2
= uns_p
? vec_widen_umult_hi_optab
: vec_widen_smult_hi_optab
;
6969 if (BYTES_BIG_ENDIAN
)
6980 icode
= optab_handler (tab1
, mode
);
6981 nunits
= GET_MODE_NUNITS (mode
);
6982 wmode
= insn_data
[icode
].operand
[0].mode
;
6983 gcc_checking_assert (2 * GET_MODE_NUNITS (wmode
) == nunits
);
6984 gcc_checking_assert (GET_MODE_SIZE (wmode
) == GET_MODE_SIZE (mode
));
6986 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6987 create_input_operand (&eops
[1], op0
, mode
);
6988 create_input_operand (&eops
[2], op1
, mode
);
6989 expand_insn (icode
, 3, eops
);
6990 m1
= gen_lowpart (mode
, eops
[0].value
);
6992 create_output_operand (&eops
[0], gen_reg_rtx (wmode
), wmode
);
6993 create_input_operand (&eops
[1], op0
, mode
);
6994 create_input_operand (&eops
[2], op1
, mode
);
6995 expand_insn (optab_handler (tab2
, mode
), 3, eops
);
6996 m2
= gen_lowpart (mode
, eops
[0].value
);
6998 v
= rtvec_alloc (nunits
);
7001 for (i
= 0; i
< nunits
; ++i
)
7002 RTVEC_ELT (v
, i
) = GEN_INT (!BYTES_BIG_ENDIAN
+ (i
& ~1)
7003 + ((i
& 1) ? nunits
: 0));
7007 for (i
= 0; i
< nunits
; ++i
)
7008 RTVEC_ELT (v
, i
) = GEN_INT (2 * i
+ (BYTES_BIG_ENDIAN
? 0 : 1));
7010 perm
= gen_rtx_CONST_VECTOR (mode
, v
);
7012 return expand_vec_perm (mode
, m1
, m2
, perm
, target
);
7015 /* Return true if target supports vector masked load/store for mode. */
7017 can_vec_mask_load_store_p (machine_mode mode
, bool is_load
)
7019 optab op
= is_load
? maskload_optab
: maskstore_optab
;
7021 unsigned int vector_sizes
;
7023 /* If mode is vector mode, check it directly. */
7024 if (VECTOR_MODE_P (mode
))
7025 return optab_handler (op
, mode
) != CODE_FOR_nothing
;
7027 /* Otherwise, return true if there is some vector mode with
7028 the mask load/store supported. */
7030 /* See if there is any chance the mask load or store might be
7031 vectorized. If not, punt. */
7032 vmode
= targetm
.vectorize
.preferred_simd_mode (mode
);
7033 if (!VECTOR_MODE_P (vmode
))
7036 if (optab_handler (op
, vmode
) != CODE_FOR_nothing
)
7039 vector_sizes
= targetm
.vectorize
.autovectorize_vector_sizes ();
7040 while (vector_sizes
!= 0)
7042 unsigned int cur
= 1 << floor_log2 (vector_sizes
);
7043 vector_sizes
&= ~cur
;
7044 if (cur
<= GET_MODE_SIZE (mode
))
7046 vmode
= mode_for_vector (mode
, cur
/ GET_MODE_SIZE (mode
));
7047 if (VECTOR_MODE_P (vmode
)
7048 && optab_handler (op
, vmode
) != CODE_FOR_nothing
)
7054 /* Return true if there is a compare_and_swap pattern. */
7057 can_compare_and_swap_p (machine_mode mode
, bool allow_libcall
)
7059 enum insn_code icode
;
7061 /* Check for __atomic_compare_and_swap. */
7062 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7063 if (icode
!= CODE_FOR_nothing
)
7066 /* Check for __sync_compare_and_swap. */
7067 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7068 if (icode
!= CODE_FOR_nothing
)
7070 if (allow_libcall
&& optab_libfunc (sync_compare_and_swap_optab
, mode
))
7073 /* No inline compare and swap. */
7077 /* Return true if an atomic exchange can be performed. */
7080 can_atomic_exchange_p (machine_mode mode
, bool allow_libcall
)
7082 enum insn_code icode
;
7084 /* Check for __atomic_exchange. */
7085 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7086 if (icode
!= CODE_FOR_nothing
)
7089 /* Don't check __sync_test_and_set, as on some platforms that
7090 has reduced functionality. Targets that really do support
7091 a proper exchange should simply be updated to the __atomics. */
7093 return can_compare_and_swap_p (mode
, allow_libcall
);
7097 /* Helper function to find the MODE_CC set in a sync_compare_and_swap
7101 find_cc_set (rtx x
, const_rtx pat
, void *data
)
7103 if (REG_P (x
) && GET_MODE_CLASS (GET_MODE (x
)) == MODE_CC
7104 && GET_CODE (pat
) == SET
)
7106 rtx
*p_cc_reg
= (rtx
*) data
;
7107 gcc_assert (!*p_cc_reg
);
7112 /* This is a helper function for the other atomic operations. This function
7113 emits a loop that contains SEQ that iterates until a compare-and-swap
7114 operation at the end succeeds. MEM is the memory to be modified. SEQ is
7115 a set of instructions that takes a value from OLD_REG as an input and
7116 produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be
7117 set to the current contents of MEM. After SEQ, a compare-and-swap will
7118 attempt to update MEM with NEW_REG. The function returns true when the
7119 loop was generated successfully. */
7122 expand_compare_and_swap_loop (rtx mem
, rtx old_reg
, rtx new_reg
, rtx seq
)
7124 machine_mode mode
= GET_MODE (mem
);
7125 rtx_code_label
*label
;
7126 rtx cmp_reg
, success
, oldval
;
7128 /* The loop we want to generate looks like
7134 (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg)
7138 Note that we only do the plain load from memory once. Subsequent
7139 iterations use the value loaded by the compare-and-swap pattern. */
7141 label
= gen_label_rtx ();
7142 cmp_reg
= gen_reg_rtx (mode
);
7144 emit_move_insn (cmp_reg
, mem
);
7146 emit_move_insn (old_reg
, cmp_reg
);
7152 if (!expand_atomic_compare_and_swap (&success
, &oldval
, mem
, old_reg
,
7153 new_reg
, false, MEMMODEL_SYNC_SEQ_CST
,
7157 if (oldval
!= cmp_reg
)
7158 emit_move_insn (cmp_reg
, oldval
);
7160 /* Mark this jump predicted not taken. */
7161 emit_cmp_and_jump_insns (success
, const0_rtx
, EQ
, const0_rtx
,
7162 GET_MODE (success
), 1, label
, 0);
7167 /* This function tries to emit an atomic_exchange intruction. VAL is written
7168 to *MEM using memory model MODEL. The previous contents of *MEM are returned,
7169 using TARGET if possible. */
7172 maybe_emit_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7174 machine_mode mode
= GET_MODE (mem
);
7175 enum insn_code icode
;
7177 /* If the target supports the exchange directly, great. */
7178 icode
= direct_optab_handler (atomic_exchange_optab
, mode
);
7179 if (icode
!= CODE_FOR_nothing
)
7181 struct expand_operand ops
[4];
7183 create_output_operand (&ops
[0], target
, mode
);
7184 create_fixed_operand (&ops
[1], mem
);
7185 create_input_operand (&ops
[2], val
, mode
);
7186 create_integer_operand (&ops
[3], model
);
7187 if (maybe_expand_insn (icode
, 4, ops
))
7188 return ops
[0].value
;
7194 /* This function tries to implement an atomic exchange operation using
7195 __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL.
7196 The previous contents of *MEM are returned, using TARGET if possible.
7197 Since this instructionn is an acquire barrier only, stronger memory
7198 models may require additional barriers to be emitted. */
7201 maybe_emit_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
,
7202 enum memmodel model
)
7204 machine_mode mode
= GET_MODE (mem
);
7205 enum insn_code icode
;
7206 rtx_insn
*last_insn
= get_last_insn ();
7208 icode
= optab_handler (sync_lock_test_and_set_optab
, mode
);
7210 /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern
7211 exists, and the memory model is stronger than acquire, add a release
7212 barrier before the instruction. */
7214 if (is_mm_seq_cst (model
) || is_mm_release (model
) || is_mm_acq_rel (model
))
7215 expand_mem_thread_fence (model
);
7217 if (icode
!= CODE_FOR_nothing
)
7219 struct expand_operand ops
[3];
7220 create_output_operand (&ops
[0], target
, mode
);
7221 create_fixed_operand (&ops
[1], mem
);
7222 create_input_operand (&ops
[2], val
, mode
);
7223 if (maybe_expand_insn (icode
, 3, ops
))
7224 return ops
[0].value
;
7227 /* If an external test-and-set libcall is provided, use that instead of
7228 any external compare-and-swap that we might get from the compare-and-
7229 swap-loop expansion later. */
7230 if (!can_compare_and_swap_p (mode
, false))
7232 rtx libfunc
= optab_libfunc (sync_lock_test_and_set_optab
, mode
);
7233 if (libfunc
!= NULL
)
7237 addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7238 return emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7239 mode
, 2, addr
, ptr_mode
,
7244 /* If the test_and_set can't be emitted, eliminate any barrier that might
7245 have been emitted. */
7246 delete_insns_since (last_insn
);
7250 /* This function tries to implement an atomic exchange operation using a
7251 compare_and_swap loop. VAL is written to *MEM. The previous contents of
7252 *MEM are returned, using TARGET if possible. No memory model is required
7253 since a compare_and_swap loop is seq-cst. */
7256 maybe_emit_compare_and_swap_exchange_loop (rtx target
, rtx mem
, rtx val
)
7258 machine_mode mode
= GET_MODE (mem
);
7260 if (can_compare_and_swap_p (mode
, true))
7262 if (!target
|| !register_operand (target
, mode
))
7263 target
= gen_reg_rtx (mode
);
7264 if (expand_compare_and_swap_loop (mem
, target
, val
, NULL_RTX
))
7271 /* This function tries to implement an atomic test-and-set operation
7272 using the atomic_test_and_set instruction pattern. A boolean value
7273 is returned from the operation, using TARGET if possible. */
7275 #ifndef HAVE_atomic_test_and_set
7276 #define HAVE_atomic_test_and_set 0
7277 #define CODE_FOR_atomic_test_and_set CODE_FOR_nothing
7281 maybe_emit_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7283 machine_mode pat_bool_mode
;
7284 struct expand_operand ops
[3];
7286 if (!HAVE_atomic_test_and_set
)
7289 /* While we always get QImode from __atomic_test_and_set, we get
7290 other memory modes from __sync_lock_test_and_set. Note that we
7291 use no endian adjustment here. This matches the 4.6 behavior
7292 in the Sparc backend. */
7294 (insn_data
[CODE_FOR_atomic_test_and_set
].operand
[1].mode
== QImode
);
7295 if (GET_MODE (mem
) != QImode
)
7296 mem
= adjust_address_nv (mem
, QImode
, 0);
7298 pat_bool_mode
= insn_data
[CODE_FOR_atomic_test_and_set
].operand
[0].mode
;
7299 create_output_operand (&ops
[0], target
, pat_bool_mode
);
7300 create_fixed_operand (&ops
[1], mem
);
7301 create_integer_operand (&ops
[2], model
);
7303 if (maybe_expand_insn (CODE_FOR_atomic_test_and_set
, 3, ops
))
7304 return ops
[0].value
;
7308 /* This function expands the legacy _sync_lock test_and_set operation which is
7309 generally an atomic exchange. Some limited targets only allow the
7310 constant 1 to be stored. This is an ACQUIRE operation.
7312 TARGET is an optional place to stick the return value.
7313 MEM is where VAL is stored. */
7316 expand_sync_lock_test_and_set (rtx target
, rtx mem
, rtx val
)
7320 /* Try an atomic_exchange first. */
7321 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, MEMMODEL_SYNC_ACQUIRE
);
7325 ret
= maybe_emit_sync_lock_test_and_set (target
, mem
, val
,
7326 MEMMODEL_SYNC_ACQUIRE
);
7330 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7334 /* If there are no other options, try atomic_test_and_set if the value
7335 being stored is 1. */
7336 if (val
== const1_rtx
)
7337 ret
= maybe_emit_atomic_test_and_set (target
, mem
, MEMMODEL_SYNC_ACQUIRE
);
7342 /* This function expands the atomic test_and_set operation:
7343 atomically store a boolean TRUE into MEM and return the previous value.
7345 MEMMODEL is the memory model variant to use.
7346 TARGET is an optional place to stick the return value. */
7349 expand_atomic_test_and_set (rtx target
, rtx mem
, enum memmodel model
)
7351 machine_mode mode
= GET_MODE (mem
);
7352 rtx ret
, trueval
, subtarget
;
7354 ret
= maybe_emit_atomic_test_and_set (target
, mem
, model
);
7358 /* Be binary compatible with non-default settings of trueval, and different
7359 cpu revisions. E.g. one revision may have atomic-test-and-set, but
7360 another only has atomic-exchange. */
7361 if (targetm
.atomic_test_and_set_trueval
== 1)
7363 trueval
= const1_rtx
;
7364 subtarget
= target
? target
: gen_reg_rtx (mode
);
7368 trueval
= gen_int_mode (targetm
.atomic_test_and_set_trueval
, mode
);
7369 subtarget
= gen_reg_rtx (mode
);
7372 /* Try the atomic-exchange optab... */
7373 ret
= maybe_emit_atomic_exchange (subtarget
, mem
, trueval
, model
);
7375 /* ... then an atomic-compare-and-swap loop ... */
7377 ret
= maybe_emit_compare_and_swap_exchange_loop (subtarget
, mem
, trueval
);
7379 /* ... before trying the vaguely defined legacy lock_test_and_set. */
7381 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, trueval
, model
);
7383 /* Recall that the legacy lock_test_and_set optab was allowed to do magic
7384 things with the value 1. Thus we try again without trueval. */
7385 if (!ret
&& targetm
.atomic_test_and_set_trueval
!= 1)
7386 ret
= maybe_emit_sync_lock_test_and_set (subtarget
, mem
, const1_rtx
, model
);
7388 /* Failing all else, assume a single threaded environment and simply
7389 perform the operation. */
7392 /* If the result is ignored skip the move to target. */
7393 if (subtarget
!= const0_rtx
)
7394 emit_move_insn (subtarget
, mem
);
7396 emit_move_insn (mem
, trueval
);
7400 /* Recall that have to return a boolean value; rectify if trueval
7401 is not exactly one. */
7402 if (targetm
.atomic_test_and_set_trueval
!= 1)
7403 ret
= emit_store_flag_force (target
, NE
, ret
, const0_rtx
, mode
, 0, 1);
7408 /* This function expands the atomic exchange operation:
7409 atomically store VAL in MEM and return the previous value in MEM.
7411 MEMMODEL is the memory model variant to use.
7412 TARGET is an optional place to stick the return value. */
7415 expand_atomic_exchange (rtx target
, rtx mem
, rtx val
, enum memmodel model
)
7419 ret
= maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7421 /* Next try a compare-and-swap loop for the exchange. */
7423 ret
= maybe_emit_compare_and_swap_exchange_loop (target
, mem
, val
);
7428 /* This function expands the atomic compare exchange operation:
7430 *PTARGET_BOOL is an optional place to store the boolean success/failure.
7431 *PTARGET_OVAL is an optional place to store the old value from memory.
7432 Both target parameters may be NULL to indicate that we do not care about
7433 that return value. Both target parameters are updated on success to
7434 the actual location of the corresponding result.
7436 MEMMODEL is the memory model variant to use.
7438 The return value of the function is true for success. */
7441 expand_atomic_compare_and_swap (rtx
*ptarget_bool
, rtx
*ptarget_oval
,
7442 rtx mem
, rtx expected
, rtx desired
,
7443 bool is_weak
, enum memmodel succ_model
,
7444 enum memmodel fail_model
)
7446 machine_mode mode
= GET_MODE (mem
);
7447 struct expand_operand ops
[8];
7448 enum insn_code icode
;
7449 rtx target_oval
, target_bool
= NULL_RTX
;
7452 /* Load expected into a register for the compare and swap. */
7453 if (MEM_P (expected
))
7454 expected
= copy_to_reg (expected
);
7456 /* Make sure we always have some place to put the return oldval.
7457 Further, make sure that place is distinct from the input expected,
7458 just in case we need that path down below. */
7459 if (ptarget_oval
== NULL
7460 || (target_oval
= *ptarget_oval
) == NULL
7461 || reg_overlap_mentioned_p (expected
, target_oval
))
7462 target_oval
= gen_reg_rtx (mode
);
7464 icode
= direct_optab_handler (atomic_compare_and_swap_optab
, mode
);
7465 if (icode
!= CODE_FOR_nothing
)
7467 machine_mode bool_mode
= insn_data
[icode
].operand
[0].mode
;
7469 /* Make sure we always have a place for the bool operand. */
7470 if (ptarget_bool
== NULL
7471 || (target_bool
= *ptarget_bool
) == NULL
7472 || GET_MODE (target_bool
) != bool_mode
)
7473 target_bool
= gen_reg_rtx (bool_mode
);
7475 /* Emit the compare_and_swap. */
7476 create_output_operand (&ops
[0], target_bool
, bool_mode
);
7477 create_output_operand (&ops
[1], target_oval
, mode
);
7478 create_fixed_operand (&ops
[2], mem
);
7479 create_input_operand (&ops
[3], expected
, mode
);
7480 create_input_operand (&ops
[4], desired
, mode
);
7481 create_integer_operand (&ops
[5], is_weak
);
7482 create_integer_operand (&ops
[6], succ_model
);
7483 create_integer_operand (&ops
[7], fail_model
);
7484 if (maybe_expand_insn (icode
, 8, ops
))
7486 /* Return success/failure. */
7487 target_bool
= ops
[0].value
;
7488 target_oval
= ops
[1].value
;
7493 /* Otherwise fall back to the original __sync_val_compare_and_swap
7494 which is always seq-cst. */
7495 icode
= optab_handler (sync_compare_and_swap_optab
, mode
);
7496 if (icode
!= CODE_FOR_nothing
)
7500 create_output_operand (&ops
[0], target_oval
, mode
);
7501 create_fixed_operand (&ops
[1], mem
);
7502 create_input_operand (&ops
[2], expected
, mode
);
7503 create_input_operand (&ops
[3], desired
, mode
);
7504 if (!maybe_expand_insn (icode
, 4, ops
))
7507 target_oval
= ops
[0].value
;
7509 /* If the caller isn't interested in the boolean return value,
7510 skip the computation of it. */
7511 if (ptarget_bool
== NULL
)
7514 /* Otherwise, work out if the compare-and-swap succeeded. */
7516 if (have_insn_for (COMPARE
, CCmode
))
7517 note_stores (PATTERN (get_last_insn ()), find_cc_set
, &cc_reg
);
7520 target_bool
= emit_store_flag_force (target_bool
, EQ
, cc_reg
,
7521 const0_rtx
, VOIDmode
, 0, 1);
7524 goto success_bool_from_val
;
7527 /* Also check for library support for __sync_val_compare_and_swap. */
7528 libfunc
= optab_libfunc (sync_compare_and_swap_optab
, mode
);
7529 if (libfunc
!= NULL
)
7531 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
7532 target_oval
= emit_library_call_value (libfunc
, NULL_RTX
, LCT_NORMAL
,
7533 mode
, 3, addr
, ptr_mode
,
7534 expected
, mode
, desired
, mode
);
7536 /* Compute the boolean return value only if requested. */
7538 goto success_bool_from_val
;
7546 success_bool_from_val
:
7547 target_bool
= emit_store_flag_force (target_bool
, EQ
, target_oval
,
7548 expected
, VOIDmode
, 1, 1);
7550 /* Make sure that the oval output winds up where the caller asked. */
7552 *ptarget_oval
= target_oval
;
7554 *ptarget_bool
= target_bool
;
7558 /* Generate asm volatile("" : : : "memory") as the memory barrier. */
7561 expand_asm_memory_barrier (void)
7565 asm_op
= gen_rtx_ASM_OPERANDS (VOIDmode
, empty_string
, empty_string
, 0,
7566 rtvec_alloc (0), rtvec_alloc (0),
7567 rtvec_alloc (0), UNKNOWN_LOCATION
);
7568 MEM_VOLATILE_P (asm_op
) = 1;
7570 clob
= gen_rtx_SCRATCH (VOIDmode
);
7571 clob
= gen_rtx_MEM (BLKmode
, clob
);
7572 clob
= gen_rtx_CLOBBER (VOIDmode
, clob
);
7574 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, asm_op
, clob
)));
7577 /* This routine will either emit the mem_thread_fence pattern or issue a
7578 sync_synchronize to generate a fence for memory model MEMMODEL. */
7581 expand_mem_thread_fence (enum memmodel model
)
7583 if (HAVE_mem_thread_fence
)
7584 emit_insn (gen_mem_thread_fence (GEN_INT (model
)));
7585 else if (!is_mm_relaxed (model
))
7587 if (HAVE_memory_barrier
)
7588 emit_insn (gen_memory_barrier ());
7589 else if (synchronize_libfunc
!= NULL_RTX
)
7590 emit_library_call (synchronize_libfunc
, LCT_NORMAL
, VOIDmode
, 0);
7592 expand_asm_memory_barrier ();
7596 /* This routine will either emit the mem_signal_fence pattern or issue a
7597 sync_synchronize to generate a fence for memory model MEMMODEL. */
7600 expand_mem_signal_fence (enum memmodel model
)
7602 if (HAVE_mem_signal_fence
)
7603 emit_insn (gen_mem_signal_fence (GEN_INT (model
)));
7604 else if (!is_mm_relaxed (model
))
7606 /* By default targets are coherent between a thread and the signal
7607 handler running on the same thread. Thus this really becomes a
7608 compiler barrier, in that stores must not be sunk past
7609 (or raised above) a given point. */
7610 expand_asm_memory_barrier ();
7614 /* This function expands the atomic load operation:
7615 return the atomically loaded value in MEM.
7617 MEMMODEL is the memory model variant to use.
7618 TARGET is an option place to stick the return value. */
7621 expand_atomic_load (rtx target
, rtx mem
, enum memmodel model
)
7623 machine_mode mode
= GET_MODE (mem
);
7624 enum insn_code icode
;
7626 /* If the target supports the load directly, great. */
7627 icode
= direct_optab_handler (atomic_load_optab
, mode
);
7628 if (icode
!= CODE_FOR_nothing
)
7630 struct expand_operand ops
[3];
7632 create_output_operand (&ops
[0], target
, mode
);
7633 create_fixed_operand (&ops
[1], mem
);
7634 create_integer_operand (&ops
[2], model
);
7635 if (maybe_expand_insn (icode
, 3, ops
))
7636 return ops
[0].value
;
7639 /* If the size of the object is greater than word size on this target,
7640 then we assume that a load will not be atomic. */
7641 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7643 /* Issue val = compare_and_swap (mem, 0, 0).
7644 This may cause the occasional harmless store of 0 when the value is
7645 already 0, but it seems to be OK according to the standards guys. */
7646 if (expand_atomic_compare_and_swap (NULL
, &target
, mem
, const0_rtx
,
7647 const0_rtx
, false, model
, model
))
7650 /* Otherwise there is no atomic load, leave the library call. */
7654 /* Otherwise assume loads are atomic, and emit the proper barriers. */
7655 if (!target
|| target
== const0_rtx
)
7656 target
= gen_reg_rtx (mode
);
7658 /* For SEQ_CST, emit a barrier before the load. */
7659 if (is_mm_seq_cst (model
))
7660 expand_mem_thread_fence (model
);
7662 emit_move_insn (target
, mem
);
7664 /* Emit the appropriate barrier after the load. */
7665 expand_mem_thread_fence (model
);
7670 /* This function expands the atomic store operation:
7671 Atomically store VAL in MEM.
7672 MEMMODEL is the memory model variant to use.
7673 USE_RELEASE is true if __sync_lock_release can be used as a fall back.
7674 function returns const0_rtx if a pattern was emitted. */
7677 expand_atomic_store (rtx mem
, rtx val
, enum memmodel model
, bool use_release
)
7679 machine_mode mode
= GET_MODE (mem
);
7680 enum insn_code icode
;
7681 struct expand_operand ops
[3];
7683 /* If the target supports the store directly, great. */
7684 icode
= direct_optab_handler (atomic_store_optab
, mode
);
7685 if (icode
!= CODE_FOR_nothing
)
7687 create_fixed_operand (&ops
[0], mem
);
7688 create_input_operand (&ops
[1], val
, mode
);
7689 create_integer_operand (&ops
[2], model
);
7690 if (maybe_expand_insn (icode
, 3, ops
))
7694 /* If using __sync_lock_release is a viable alternative, try it. */
7697 icode
= direct_optab_handler (sync_lock_release_optab
, mode
);
7698 if (icode
!= CODE_FOR_nothing
)
7700 create_fixed_operand (&ops
[0], mem
);
7701 create_input_operand (&ops
[1], const0_rtx
, mode
);
7702 if (maybe_expand_insn (icode
, 2, ops
))
7704 /* lock_release is only a release barrier. */
7705 if (is_mm_seq_cst (model
))
7706 expand_mem_thread_fence (model
);
7712 /* If the size of the object is greater than word size on this target,
7713 a default store will not be atomic, Try a mem_exchange and throw away
7714 the result. If that doesn't work, don't do anything. */
7715 if (GET_MODE_PRECISION (mode
) > BITS_PER_WORD
)
7717 rtx target
= maybe_emit_atomic_exchange (NULL_RTX
, mem
, val
, model
);
7719 target
= maybe_emit_compare_and_swap_exchange_loop (NULL_RTX
, mem
, val
);
7726 /* Otherwise assume stores are atomic, and emit the proper barriers. */
7727 expand_mem_thread_fence (model
);
7729 emit_move_insn (mem
, val
);
7731 /* For SEQ_CST, also emit a barrier after the store. */
7732 if (is_mm_seq_cst (model
))
7733 expand_mem_thread_fence (model
);
7739 /* Structure containing the pointers and values required to process the
7740 various forms of the atomic_fetch_op and atomic_op_fetch builtins. */
7742 struct atomic_op_functions
7744 direct_optab mem_fetch_before
;
7745 direct_optab mem_fetch_after
;
7746 direct_optab mem_no_result
;
7749 direct_optab no_result
;
7750 enum rtx_code reverse_code
;
7754 /* Fill in structure pointed to by OP with the various optab entries for an
7755 operation of type CODE. */
7758 get_atomic_op_for_code (struct atomic_op_functions
*op
, enum rtx_code code
)
7760 gcc_assert (op
!= NULL
);
7762 /* If SWITCHABLE_TARGET is defined, then subtargets can be switched
7763 in the source code during compilation, and the optab entries are not
7764 computable until runtime. Fill in the values at runtime. */
7768 op
->mem_fetch_before
= atomic_fetch_add_optab
;
7769 op
->mem_fetch_after
= atomic_add_fetch_optab
;
7770 op
->mem_no_result
= atomic_add_optab
;
7771 op
->fetch_before
= sync_old_add_optab
;
7772 op
->fetch_after
= sync_new_add_optab
;
7773 op
->no_result
= sync_add_optab
;
7774 op
->reverse_code
= MINUS
;
7777 op
->mem_fetch_before
= atomic_fetch_sub_optab
;
7778 op
->mem_fetch_after
= atomic_sub_fetch_optab
;
7779 op
->mem_no_result
= atomic_sub_optab
;
7780 op
->fetch_before
= sync_old_sub_optab
;
7781 op
->fetch_after
= sync_new_sub_optab
;
7782 op
->no_result
= sync_sub_optab
;
7783 op
->reverse_code
= PLUS
;
7786 op
->mem_fetch_before
= atomic_fetch_xor_optab
;
7787 op
->mem_fetch_after
= atomic_xor_fetch_optab
;
7788 op
->mem_no_result
= atomic_xor_optab
;
7789 op
->fetch_before
= sync_old_xor_optab
;
7790 op
->fetch_after
= sync_new_xor_optab
;
7791 op
->no_result
= sync_xor_optab
;
7792 op
->reverse_code
= XOR
;
7795 op
->mem_fetch_before
= atomic_fetch_and_optab
;
7796 op
->mem_fetch_after
= atomic_and_fetch_optab
;
7797 op
->mem_no_result
= atomic_and_optab
;
7798 op
->fetch_before
= sync_old_and_optab
;
7799 op
->fetch_after
= sync_new_and_optab
;
7800 op
->no_result
= sync_and_optab
;
7801 op
->reverse_code
= UNKNOWN
;
7804 op
->mem_fetch_before
= atomic_fetch_or_optab
;
7805 op
->mem_fetch_after
= atomic_or_fetch_optab
;
7806 op
->mem_no_result
= atomic_or_optab
;
7807 op
->fetch_before
= sync_old_ior_optab
;
7808 op
->fetch_after
= sync_new_ior_optab
;
7809 op
->no_result
= sync_ior_optab
;
7810 op
->reverse_code
= UNKNOWN
;
7813 op
->mem_fetch_before
= atomic_fetch_nand_optab
;
7814 op
->mem_fetch_after
= atomic_nand_fetch_optab
;
7815 op
->mem_no_result
= atomic_nand_optab
;
7816 op
->fetch_before
= sync_old_nand_optab
;
7817 op
->fetch_after
= sync_new_nand_optab
;
7818 op
->no_result
= sync_nand_optab
;
7819 op
->reverse_code
= UNKNOWN
;
7826 /* See if there is a more optimal way to implement the operation "*MEM CODE VAL"
7827 using memory order MODEL. If AFTER is true the operation needs to return
7828 the value of *MEM after the operation, otherwise the previous value.
7829 TARGET is an optional place to place the result. The result is unused if
7831 Return the result if there is a better sequence, otherwise NULL_RTX. */
7834 maybe_optimize_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
7835 enum memmodel model
, bool after
)
7837 /* If the value is prefetched, or not used, it may be possible to replace
7838 the sequence with a native exchange operation. */
7839 if (!after
|| target
== const0_rtx
)
7841 /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */
7842 if (code
== AND
&& val
== const0_rtx
)
7844 if (target
== const0_rtx
)
7845 target
= gen_reg_rtx (GET_MODE (mem
));
7846 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7849 /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */
7850 if (code
== IOR
&& val
== constm1_rtx
)
7852 if (target
== const0_rtx
)
7853 target
= gen_reg_rtx (GET_MODE (mem
));
7854 return maybe_emit_atomic_exchange (target
, mem
, val
, model
);
7861 /* Try to emit an instruction for a specific operation varaition.
7862 OPTAB contains the OP functions.
7863 TARGET is an optional place to return the result. const0_rtx means unused.
7864 MEM is the memory location to operate on.
7865 VAL is the value to use in the operation.
7866 USE_MEMMODEL is TRUE if the variation with a memory model should be tried.
7867 MODEL is the memory model, if used.
7868 AFTER is true if the returned result is the value after the operation. */
7871 maybe_emit_op (const struct atomic_op_functions
*optab
, rtx target
, rtx mem
,
7872 rtx val
, bool use_memmodel
, enum memmodel model
, bool after
)
7874 machine_mode mode
= GET_MODE (mem
);
7875 struct expand_operand ops
[4];
7876 enum insn_code icode
;
7880 /* Check to see if there is a result returned. */
7881 if (target
== const0_rtx
)
7885 icode
= direct_optab_handler (optab
->mem_no_result
, mode
);
7886 create_integer_operand (&ops
[2], model
);
7891 icode
= direct_optab_handler (optab
->no_result
, mode
);
7895 /* Otherwise, we need to generate a result. */
7900 icode
= direct_optab_handler (after
? optab
->mem_fetch_after
7901 : optab
->mem_fetch_before
, mode
);
7902 create_integer_operand (&ops
[3], model
);
7907 icode
= optab_handler (after
? optab
->fetch_after
7908 : optab
->fetch_before
, mode
);
7911 create_output_operand (&ops
[op_counter
++], target
, mode
);
7913 if (icode
== CODE_FOR_nothing
)
7916 create_fixed_operand (&ops
[op_counter
++], mem
);
7917 /* VAL may have been promoted to a wider mode. Shrink it if so. */
7918 create_convert_operand_to (&ops
[op_counter
++], val
, mode
, true);
7920 if (maybe_expand_insn (icode
, num_ops
, ops
))
7921 return (target
== const0_rtx
? const0_rtx
: ops
[0].value
);
7927 /* This function expands an atomic fetch_OP or OP_fetch operation:
7928 TARGET is an option place to stick the return value. const0_rtx indicates
7929 the result is unused.
7930 atomically fetch MEM, perform the operation with VAL and return it to MEM.
7931 CODE is the operation being performed (OP)
7932 MEMMODEL is the memory model variant to use.
7933 AFTER is true to return the result of the operation (OP_fetch).
7934 AFTER is false to return the value before the operation (fetch_OP).
7936 This function will *only* generate instructions if there is a direct
7937 optab. No compare and swap loops or libcalls will be generated. */
7940 expand_atomic_fetch_op_no_fallback (rtx target
, rtx mem
, rtx val
,
7941 enum rtx_code code
, enum memmodel model
,
7944 machine_mode mode
= GET_MODE (mem
);
7945 struct atomic_op_functions optab
;
7947 bool unused_result
= (target
== const0_rtx
);
7949 get_atomic_op_for_code (&optab
, code
);
7951 /* Check to see if there are any better instructions. */
7952 result
= maybe_optimize_fetch_op (target
, mem
, val
, code
, model
, after
);
7956 /* Check for the case where the result isn't used and try those patterns. */
7959 /* Try the memory model variant first. */
7960 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, true);
7964 /* Next try the old style withuot a memory model. */
7965 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, true);
7969 /* There is no no-result pattern, so try patterns with a result. */
7973 /* Try the __atomic version. */
7974 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, after
);
7978 /* Try the older __sync version. */
7979 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, after
);
7983 /* If the fetch value can be calculated from the other variation of fetch,
7984 try that operation. */
7985 if (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
)
7987 /* Try the __atomic version, then the older __sync version. */
7988 result
= maybe_emit_op (&optab
, target
, mem
, val
, true, model
, !after
);
7990 result
= maybe_emit_op (&optab
, target
, mem
, val
, false, model
, !after
);
7994 /* If the result isn't used, no need to do compensation code. */
7998 /* Issue compensation code. Fetch_after == fetch_before OP val.
7999 Fetch_before == after REVERSE_OP val. */
8001 code
= optab
.reverse_code
;
8004 result
= expand_simple_binop (mode
, AND
, result
, val
, NULL_RTX
,
8005 true, OPTAB_LIB_WIDEN
);
8006 result
= expand_simple_unop (mode
, NOT
, result
, target
, true);
8009 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
8010 true, OPTAB_LIB_WIDEN
);
8015 /* No direct opcode can be generated. */
8021 /* This function expands an atomic fetch_OP or OP_fetch operation:
8022 TARGET is an option place to stick the return value. const0_rtx indicates
8023 the result is unused.
8024 atomically fetch MEM, perform the operation with VAL and return it to MEM.
8025 CODE is the operation being performed (OP)
8026 MEMMODEL is the memory model variant to use.
8027 AFTER is true to return the result of the operation (OP_fetch).
8028 AFTER is false to return the value before the operation (fetch_OP). */
8030 expand_atomic_fetch_op (rtx target
, rtx mem
, rtx val
, enum rtx_code code
,
8031 enum memmodel model
, bool after
)
8033 machine_mode mode
= GET_MODE (mem
);
8035 bool unused_result
= (target
== const0_rtx
);
8037 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, val
, code
, model
,
8043 /* Add/sub can be implemented by doing the reverse operation with -(val). */
8044 if (code
== PLUS
|| code
== MINUS
)
8047 enum rtx_code reverse
= (code
== PLUS
? MINUS
: PLUS
);
8050 tmp
= expand_simple_unop (mode
, NEG
, val
, NULL_RTX
, true);
8051 result
= expand_atomic_fetch_op_no_fallback (target
, mem
, tmp
, reverse
,
8055 /* PLUS worked so emit the insns and return. */
8062 /* PLUS did not work, so throw away the negation code and continue. */
8066 /* Try the __sync libcalls only if we can't do compare-and-swap inline. */
8067 if (!can_compare_and_swap_p (mode
, false))
8071 enum rtx_code orig_code
= code
;
8072 struct atomic_op_functions optab
;
8074 get_atomic_op_for_code (&optab
, code
);
8075 libfunc
= optab_libfunc (after
? optab
.fetch_after
8076 : optab
.fetch_before
, mode
);
8078 && (after
|| unused_result
|| optab
.reverse_code
!= UNKNOWN
))
8082 code
= optab
.reverse_code
;
8083 libfunc
= optab_libfunc (after
? optab
.fetch_before
8084 : optab
.fetch_after
, mode
);
8086 if (libfunc
!= NULL
)
8088 rtx addr
= convert_memory_address (ptr_mode
, XEXP (mem
, 0));
8089 result
= emit_library_call_value (libfunc
, NULL
, LCT_NORMAL
, mode
,
8090 2, addr
, ptr_mode
, val
, mode
);
8092 if (!unused_result
&& fixup
)
8093 result
= expand_simple_binop (mode
, code
, result
, val
, target
,
8094 true, OPTAB_LIB_WIDEN
);
8098 /* We need the original code for any further attempts. */
8102 /* If nothing else has succeeded, default to a compare and swap loop. */
8103 if (can_compare_and_swap_p (mode
, true))
8106 rtx t0
= gen_reg_rtx (mode
), t1
;
8110 /* If the result is used, get a register for it. */
8113 if (!target
|| !register_operand (target
, mode
))
8114 target
= gen_reg_rtx (mode
);
8115 /* If fetch_before, copy the value now. */
8117 emit_move_insn (target
, t0
);
8120 target
= const0_rtx
;
8125 t1
= expand_simple_binop (mode
, AND
, t1
, val
, NULL_RTX
,
8126 true, OPTAB_LIB_WIDEN
);
8127 t1
= expand_simple_unop (mode
, code
, t1
, NULL_RTX
, true);
8130 t1
= expand_simple_binop (mode
, code
, t1
, val
, NULL_RTX
, true,
8133 /* For after, copy the value now. */
8134 if (!unused_result
&& after
)
8135 emit_move_insn (target
, t1
);
8136 insn
= get_insns ();
8139 if (t1
!= NULL
&& expand_compare_and_swap_loop (mem
, t0
, t1
, insn
))
8146 /* Return true if OPERAND is suitable for operand number OPNO of
8147 instruction ICODE. */
8150 insn_operand_matches (enum insn_code icode
, unsigned int opno
, rtx operand
)
8152 return (!insn_data
[(int) icode
].operand
[opno
].predicate
8153 || (insn_data
[(int) icode
].operand
[opno
].predicate
8154 (operand
, insn_data
[(int) icode
].operand
[opno
].mode
)));
8157 /* TARGET is a target of a multiword operation that we are going to
8158 implement as a series of word-mode operations. Return true if
8159 TARGET is suitable for this purpose. */
8162 valid_multiword_target_p (rtx target
)
8167 mode
= GET_MODE (target
);
8168 for (i
= 0; i
< GET_MODE_SIZE (mode
); i
+= UNITS_PER_WORD
)
8169 if (!validate_subreg (word_mode
, mode
, target
, i
))
8174 /* Like maybe_legitimize_operand, but do not change the code of the
8175 current rtx value. */
8178 maybe_legitimize_operand_same_code (enum insn_code icode
, unsigned int opno
,
8179 struct expand_operand
*op
)
8181 /* See if the operand matches in its current form. */
8182 if (insn_operand_matches (icode
, opno
, op
->value
))
8185 /* If the operand is a memory whose address has no side effects,
8186 try forcing the address into a non-virtual pseudo register.
8187 The check for side effects is important because copy_to_mode_reg
8188 cannot handle things like auto-modified addresses. */
8189 if (insn_data
[(int) icode
].operand
[opno
].allows_mem
&& MEM_P (op
->value
))
8194 addr
= XEXP (mem
, 0);
8195 if (!(REG_P (addr
) && REGNO (addr
) > LAST_VIRTUAL_REGISTER
)
8196 && !side_effects_p (addr
))
8201 last
= get_last_insn ();
8202 mode
= get_address_mode (mem
);
8203 mem
= replace_equiv_address (mem
, copy_to_mode_reg (mode
, addr
));
8204 if (insn_operand_matches (icode
, opno
, mem
))
8209 delete_insns_since (last
);
8216 /* Try to make OP match operand OPNO of instruction ICODE. Return true
8217 on success, storing the new operand value back in OP. */
8220 maybe_legitimize_operand (enum insn_code icode
, unsigned int opno
,
8221 struct expand_operand
*op
)
8223 machine_mode mode
, imode
;
8224 bool old_volatile_ok
, result
;
8230 old_volatile_ok
= volatile_ok
;
8232 result
= maybe_legitimize_operand_same_code (icode
, opno
, op
);
8233 volatile_ok
= old_volatile_ok
;
8237 gcc_assert (mode
!= VOIDmode
);
8239 && op
->value
!= const0_rtx
8240 && GET_MODE (op
->value
) == mode
8241 && maybe_legitimize_operand_same_code (icode
, opno
, op
))
8244 op
->value
= gen_reg_rtx (mode
);
8249 gcc_assert (mode
!= VOIDmode
);
8250 gcc_assert (GET_MODE (op
->value
) == VOIDmode
8251 || GET_MODE (op
->value
) == mode
);
8252 if (maybe_legitimize_operand_same_code (icode
, opno
, op
))
8255 op
->value
= copy_to_mode_reg (mode
, op
->value
);
8258 case EXPAND_CONVERT_TO
:
8259 gcc_assert (mode
!= VOIDmode
);
8260 op
->value
= convert_to_mode (mode
, op
->value
, op
->unsigned_p
);
8263 case EXPAND_CONVERT_FROM
:
8264 if (GET_MODE (op
->value
) != VOIDmode
)
8265 mode
= GET_MODE (op
->value
);
8267 /* The caller must tell us what mode this value has. */
8268 gcc_assert (mode
!= VOIDmode
);
8270 imode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8271 if (imode
!= VOIDmode
&& imode
!= mode
)
8273 op
->value
= convert_modes (imode
, mode
, op
->value
, op
->unsigned_p
);
8278 case EXPAND_ADDRESS
:
8279 gcc_assert (mode
!= VOIDmode
);
8280 op
->value
= convert_memory_address (mode
, op
->value
);
8283 case EXPAND_INTEGER
:
8284 mode
= insn_data
[(int) icode
].operand
[opno
].mode
;
8285 if (mode
!= VOIDmode
&& const_int_operand (op
->value
, mode
))
8289 return insn_operand_matches (icode
, opno
, op
->value
);
8292 /* Make OP describe an input operand that should have the same value
8293 as VALUE, after any mode conversion that the target might request.
8294 TYPE is the type of VALUE. */
8297 create_convert_operand_from_type (struct expand_operand
*op
,
8298 rtx value
, tree type
)
8300 create_convert_operand_from (op
, value
, TYPE_MODE (type
),
8301 TYPE_UNSIGNED (type
));
8304 /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS)
8305 of instruction ICODE. Return true on success, leaving the new operand
8306 values in the OPS themselves. Emit no code on failure. */
8309 maybe_legitimize_operands (enum insn_code icode
, unsigned int opno
,
8310 unsigned int nops
, struct expand_operand
*ops
)
8315 last
= get_last_insn ();
8316 for (i
= 0; i
< nops
; i
++)
8317 if (!maybe_legitimize_operand (icode
, opno
+ i
, &ops
[i
]))
8319 delete_insns_since (last
);
8325 /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS)
8326 as its operands. Return the instruction pattern on success,
8327 and emit any necessary set-up code. Return null and emit no
8331 maybe_gen_insn (enum insn_code icode
, unsigned int nops
,
8332 struct expand_operand
*ops
)
8334 gcc_assert (nops
== (unsigned int) insn_data
[(int) icode
].n_generator_args
);
8335 if (!maybe_legitimize_operands (icode
, 0, nops
, ops
))
8341 return GEN_FCN (icode
) (ops
[0].value
);
8343 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
);
8345 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
);
8347 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8350 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8351 ops
[3].value
, ops
[4].value
);
8353 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8354 ops
[3].value
, ops
[4].value
, ops
[5].value
);
8356 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8357 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8360 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8361 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8362 ops
[6].value
, ops
[7].value
);
8364 return GEN_FCN (icode
) (ops
[0].value
, ops
[1].value
, ops
[2].value
,
8365 ops
[3].value
, ops
[4].value
, ops
[5].value
,
8366 ops
[6].value
, ops
[7].value
, ops
[8].value
);
8371 /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS)
8372 as its operands. Return true on success and emit no code on failure. */
8375 maybe_expand_insn (enum insn_code icode
, unsigned int nops
,
8376 struct expand_operand
*ops
)
8378 rtx_insn
*pat
= maybe_gen_insn (icode
, nops
, ops
);
8387 /* Like maybe_expand_insn, but for jumps. */
8390 maybe_expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8391 struct expand_operand
*ops
)
8393 rtx_insn
*pat
= maybe_gen_insn (icode
, nops
, ops
);
8396 emit_jump_insn (pat
);
8402 /* Emit instruction ICODE, using operands [OPS, OPS + NOPS)
8406 expand_insn (enum insn_code icode
, unsigned int nops
,
8407 struct expand_operand
*ops
)
8409 if (!maybe_expand_insn (icode
, nops
, ops
))
8413 /* Like expand_insn, but for jumps. */
8416 expand_jump_insn (enum insn_code icode
, unsigned int nops
,
8417 struct expand_operand
*ops
)
8419 if (!maybe_expand_jump_insn (icode
, nops
, ops
))
8423 /* Reduce conditional compilation elsewhere. */
8426 #define CODE_FOR_insv CODE_FOR_nothing
8430 #define CODE_FOR_extv CODE_FOR_nothing
8433 #define HAVE_extzv 0
8434 #define CODE_FOR_extzv CODE_FOR_nothing
8437 /* Enumerates the possible types of structure operand to an
8439 enum extraction_type
{ ET_unaligned_mem
, ET_reg
};
8441 /* Check whether insv, extv or extzv pattern ICODE can be used for an
8442 insertion or extraction of type TYPE on a structure of mode MODE.
8443 Return true if so and fill in *INSN accordingly. STRUCT_OP is the
8444 operand number of the structure (the first sign_extract or zero_extract
8445 operand) and FIELD_OP is the operand number of the field (the other
8446 side of the set from the sign_extract or zero_extract). */
8449 get_traditional_extraction_insn (extraction_insn
*insn
,
8450 enum extraction_type type
,
8452 enum insn_code icode
,
8453 int struct_op
, int field_op
)
8455 const struct insn_data_d
*data
= &insn_data
[icode
];
8457 machine_mode struct_mode
= data
->operand
[struct_op
].mode
;
8458 if (struct_mode
== VOIDmode
)
8459 struct_mode
= word_mode
;
8460 if (mode
!= struct_mode
)
8463 machine_mode field_mode
= data
->operand
[field_op
].mode
;
8464 if (field_mode
== VOIDmode
)
8465 field_mode
= word_mode
;
8467 machine_mode pos_mode
= data
->operand
[struct_op
+ 2].mode
;
8468 if (pos_mode
== VOIDmode
)
8469 pos_mode
= word_mode
;
8471 insn
->icode
= icode
;
8472 insn
->field_mode
= field_mode
;
8473 insn
->struct_mode
= (type
== ET_unaligned_mem
? byte_mode
: struct_mode
);
8474 insn
->pos_mode
= pos_mode
;
8478 /* Return true if an optab exists to perform an insertion or extraction
8479 of type TYPE in mode MODE. Describe the instruction in *INSN if so.
8481 REG_OPTAB is the optab to use for register structures and
8482 MISALIGN_OPTAB is the optab to use for misaligned memory structures.
8483 POS_OP is the operand number of the bit position. */
8486 get_optab_extraction_insn (struct extraction_insn
*insn
,
8487 enum extraction_type type
,
8488 machine_mode mode
, direct_optab reg_optab
,
8489 direct_optab misalign_optab
, int pos_op
)
8491 direct_optab optab
= (type
== ET_unaligned_mem
? misalign_optab
: reg_optab
);
8492 enum insn_code icode
= direct_optab_handler (optab
, mode
);
8493 if (icode
== CODE_FOR_nothing
)
8496 const struct insn_data_d
*data
= &insn_data
[icode
];
8498 insn
->icode
= icode
;
8499 insn
->field_mode
= mode
;
8500 insn
->struct_mode
= (type
== ET_unaligned_mem
? BLKmode
: mode
);
8501 insn
->pos_mode
= data
->operand
[pos_op
].mode
;
8502 if (insn
->pos_mode
== VOIDmode
)
8503 insn
->pos_mode
= word_mode
;
8507 /* Return true if an instruction exists to perform an insertion or
8508 extraction (PATTERN says which) of type TYPE in mode MODE.
8509 Describe the instruction in *INSN if so. */
8512 get_extraction_insn (extraction_insn
*insn
,
8513 enum extraction_pattern pattern
,
8514 enum extraction_type type
,
8521 && get_traditional_extraction_insn (insn
, type
, mode
,
8522 CODE_FOR_insv
, 0, 3))
8524 return get_optab_extraction_insn (insn
, type
, mode
, insv_optab
,
8525 insvmisalign_optab
, 2);
8529 && get_traditional_extraction_insn (insn
, type
, mode
,
8530 CODE_FOR_extv
, 1, 0))
8532 return get_optab_extraction_insn (insn
, type
, mode
, extv_optab
,
8533 extvmisalign_optab
, 3);
8537 && get_traditional_extraction_insn (insn
, type
, mode
,
8538 CODE_FOR_extzv
, 1, 0))
8540 return get_optab_extraction_insn (insn
, type
, mode
, extzv_optab
,
8541 extzvmisalign_optab
, 3);
8548 /* Return true if an instruction exists to access a field of mode
8549 FIELDMODE in a structure that has STRUCT_BITS significant bits.
8550 Describe the "best" such instruction in *INSN if so. PATTERN and
8551 TYPE describe the type of insertion or extraction we want to perform.
8553 For an insertion, the number of significant structure bits includes
8554 all bits of the target. For an extraction, it need only include the
8555 most significant bit of the field. Larger widths are acceptable
8559 get_best_extraction_insn (extraction_insn
*insn
,
8560 enum extraction_pattern pattern
,
8561 enum extraction_type type
,
8562 unsigned HOST_WIDE_INT struct_bits
,
8563 machine_mode field_mode
)
8565 machine_mode mode
= smallest_mode_for_size (struct_bits
, MODE_INT
);
8566 while (mode
!= VOIDmode
)
8568 if (get_extraction_insn (insn
, pattern
, type
, mode
))
8570 while (mode
!= VOIDmode
8571 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (field_mode
)
8572 && !TRULY_NOOP_TRUNCATION_MODES_P (insn
->field_mode
,
8575 get_extraction_insn (insn
, pattern
, type
, mode
);
8576 mode
= GET_MODE_WIDER_MODE (mode
);
8580 mode
= GET_MODE_WIDER_MODE (mode
);
8585 /* Return true if an instruction exists to access a field of mode
8586 FIELDMODE in a register structure that has STRUCT_BITS significant bits.
8587 Describe the "best" such instruction in *INSN if so. PATTERN describes
8588 the type of insertion or extraction we want to perform.
8590 For an insertion, the number of significant structure bits includes
8591 all bits of the target. For an extraction, it need only include the
8592 most significant bit of the field. Larger widths are acceptable
8596 get_best_reg_extraction_insn (extraction_insn
*insn
,
8597 enum extraction_pattern pattern
,
8598 unsigned HOST_WIDE_INT struct_bits
,
8599 machine_mode field_mode
)
8601 return get_best_extraction_insn (insn
, pattern
, ET_reg
, struct_bits
,
8605 /* Return true if an instruction exists to access a field of BITSIZE
8606 bits starting BITNUM bits into a memory structure. Describe the
8607 "best" such instruction in *INSN if so. PATTERN describes the type
8608 of insertion or extraction we want to perform and FIELDMODE is the
8609 natural mode of the extracted field.
8611 The instructions considered here only access bytes that overlap
8612 the bitfield; they do not touch any surrounding bytes. */
8615 get_best_mem_extraction_insn (extraction_insn
*insn
,
8616 enum extraction_pattern pattern
,
8617 HOST_WIDE_INT bitsize
, HOST_WIDE_INT bitnum
,
8618 machine_mode field_mode
)
8620 unsigned HOST_WIDE_INT struct_bits
= (bitnum
% BITS_PER_UNIT
8622 + BITS_PER_UNIT
- 1);
8623 struct_bits
-= struct_bits
% BITS_PER_UNIT
;
8624 return get_best_extraction_insn (insn
, pattern
, ET_unaligned_mem
,
8625 struct_bits
, field_mode
);
8628 /* Determine whether "1 << x" is relatively cheap in word_mode. */
8631 lshift_cheap_p (bool speed_p
)
8633 /* FIXME: This should be made target dependent via this "this_target"
8634 mechanism, similar to e.g. can_copy_init_p in gcse.c. */
8635 static bool init
[2] = { false, false };
8636 static bool cheap
[2] = { true, true };
8638 /* If the targer has no lshift in word_mode, the operation will most
8639 probably not be cheap. ??? Does GCC even work for such targets? */
8640 if (optab_handler (ashl_optab
, word_mode
) == CODE_FOR_nothing
)
8645 rtx reg
= gen_raw_REG (word_mode
, 10000);
8646 int cost
= set_src_cost (gen_rtx_ASHIFT (word_mode
, const1_rtx
, reg
),
8648 cheap
[speed_p
] = cost
< COSTS_N_INSNS (3);
8649 init
[speed_p
] = true;
8652 return cheap
[speed_p
];
8655 #include "gt-optabs.h"