1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
39 #include "insn-codes.h"
43 #include "dominance.h"
47 #include "cfgcleanup.h"
48 #include "basic-block.h"
52 #include "diagnostic-core.h"
54 #include "double-int.h"
62 #include "tree-pass.h"
66 static int reload_cse_noop_set_p (rtx
);
67 static bool reload_cse_simplify (rtx_insn
*, rtx
);
68 static void reload_cse_regs_1 (void);
69 static int reload_cse_simplify_set (rtx
, rtx_insn
*);
70 static int reload_cse_simplify_operands (rtx_insn
*, rtx
);
72 static void reload_combine (void);
73 static void reload_combine_note_use (rtx
*, rtx_insn
*, int, rtx
);
74 static void reload_combine_note_store (rtx
, const_rtx
, void *);
76 static bool reload_cse_move2add (rtx_insn
*);
77 static void move2add_note_store (rtx
, const_rtx
, void *);
79 /* Call cse / combine like post-reload optimization phases.
80 FIRST is the first instruction. */
83 reload_cse_regs (rtx_insn
*first ATTRIBUTE_UNUSED
)
88 moves_converted
= reload_cse_move2add (first
);
89 if (flag_expensive_optimizations
)
97 /* See whether a single set SET is a noop. */
99 reload_cse_noop_set_p (rtx set
)
101 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
104 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
107 /* Try to simplify INSN. Return true if the CFG may have changed. */
109 reload_cse_simplify (rtx_insn
*insn
, rtx testreg
)
111 rtx body
= PATTERN (insn
);
112 basic_block insn_bb
= BLOCK_FOR_INSN (insn
);
113 unsigned insn_bb_succs
= EDGE_COUNT (insn_bb
->succs
);
115 if (GET_CODE (body
) == SET
)
119 /* Simplify even if we may think it is a no-op.
120 We may think a memory load of a value smaller than WORD_SIZE
121 is redundant because we haven't taken into account possible
122 implicit extension. reload_cse_simplify_set() will bring
123 this out, so it's safer to simplify before we delete. */
124 count
+= reload_cse_simplify_set (body
, insn
);
126 if (!count
&& reload_cse_noop_set_p (body
))
128 rtx value
= SET_DEST (body
);
130 && ! REG_FUNCTION_VALUE_P (value
))
132 if (check_for_inc_dec (insn
))
133 delete_insn_and_edges (insn
);
134 /* We're done with this insn. */
139 apply_change_group ();
141 reload_cse_simplify_operands (insn
, testreg
);
143 else if (GET_CODE (body
) == PARALLEL
)
147 rtx value
= NULL_RTX
;
149 /* Registers mentioned in the clobber list for an asm cannot be reused
150 within the body of the asm. Invalidate those registers now so that
151 we don't try to substitute values for them. */
152 if (asm_noperands (body
) >= 0)
154 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
156 rtx part
= XVECEXP (body
, 0, i
);
157 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
158 cselib_invalidate_rtx (XEXP (part
, 0));
162 /* If every action in a PARALLEL is a noop, we can delete
163 the entire PARALLEL. */
164 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
166 rtx part
= XVECEXP (body
, 0, i
);
167 if (GET_CODE (part
) == SET
)
169 if (! reload_cse_noop_set_p (part
))
171 if (REG_P (SET_DEST (part
))
172 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
176 value
= SET_DEST (part
);
179 else if (GET_CODE (part
) != CLOBBER
)
185 if (check_for_inc_dec (insn
))
186 delete_insn_and_edges (insn
);
187 /* We're done with this insn. */
191 /* It's not a no-op, but we can try to simplify it. */
192 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
193 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
194 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
197 apply_change_group ();
199 reload_cse_simplify_operands (insn
, testreg
);
203 return (EDGE_COUNT (insn_bb
->succs
) != insn_bb_succs
);
206 /* Do a very simple CSE pass over the hard registers.
208 This function detects no-op moves where we happened to assign two
209 different pseudo-registers to the same hard register, and then
210 copied one to the other. Reload will generate a useless
211 instruction copying a register to itself.
213 This function also detects cases where we load a value from memory
214 into two different registers, and (if memory is more expensive than
215 registers) changes it to simply copy the first register into the
218 Another optimization is performed that scans the operands of each
219 instruction to see whether the value is already available in a
220 hard register. It then replaces the operand with the hard register
221 if possible, much like an optional reload would. */
224 reload_cse_regs_1 (void)
226 bool cfg_changed
= false;
229 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
231 cselib_init (CSELIB_RECORD_MEMORY
);
232 init_alias_analysis ();
234 FOR_EACH_BB_FN (bb
, cfun
)
235 FOR_BB_INSNS (bb
, insn
)
238 cfg_changed
|= reload_cse_simplify (insn
, testreg
);
240 cselib_process_insn (insn
);
244 end_alias_analysis ();
250 /* Try to simplify a single SET instruction. SET is the set pattern.
251 INSN is the instruction it came from.
252 This function only handles one case: if we set a register to a value
253 which is not a register, we try to find that value in some other register
254 and change the set into a register copy. */
257 reload_cse_simplify_set (rtx set
, rtx_insn
*insn
)
265 struct elt_loc_list
*l
;
266 #ifdef LOAD_EXTEND_OP
267 enum rtx_code extend_op
= UNKNOWN
;
269 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
271 dreg
= true_regnum (SET_DEST (set
));
276 if (side_effects_p (src
) || true_regnum (src
) >= 0)
279 dclass
= REGNO_REG_CLASS (dreg
);
281 #ifdef LOAD_EXTEND_OP
282 /* When replacing a memory with a register, we need to honor assumptions
283 that combine made wrt the contents of sign bits. We'll do this by
284 generating an extend instruction instead of a reg->reg copy. Thus
285 the destination must be a register that we can widen. */
287 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
288 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
289 && !REG_P (SET_DEST (set
)))
293 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0, VOIDmode
);
297 /* If memory loads are cheaper than register copies, don't change them. */
299 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
300 else if (REG_P (src
))
301 old_cost
= register_move_cost (GET_MODE (src
),
302 REGNO_REG_CLASS (REGNO (src
)), dclass
);
304 old_cost
= set_src_cost (src
, speed
);
306 for (l
= val
->locs
; l
; l
= l
->next
)
308 rtx this_rtx
= l
->loc
;
311 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
313 #ifdef LOAD_EXTEND_OP
314 if (extend_op
!= UNKNOWN
)
318 if (!CONST_SCALAR_INT_P (this_rtx
))
324 result
= wide_int::from (std::make_pair (this_rtx
,
326 BITS_PER_WORD
, UNSIGNED
);
329 result
= wide_int::from (std::make_pair (this_rtx
,
331 BITS_PER_WORD
, SIGNED
);
336 this_rtx
= immed_wide_int_const (result
, word_mode
);
339 this_cost
= set_src_cost (this_rtx
, speed
);
341 else if (REG_P (this_rtx
))
343 #ifdef LOAD_EXTEND_OP
344 if (extend_op
!= UNKNOWN
)
346 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
347 this_cost
= set_src_cost (this_rtx
, speed
);
351 this_cost
= register_move_cost (GET_MODE (this_rtx
),
352 REGNO_REG_CLASS (REGNO (this_rtx
)),
358 /* If equal costs, prefer registers over anything else. That
359 tends to lead to smaller instructions on some machines. */
360 if (this_cost
< old_cost
361 || (this_cost
== old_cost
363 && !REG_P (SET_SRC (set
))))
365 #ifdef LOAD_EXTEND_OP
366 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
367 && extend_op
!= UNKNOWN
368 #ifdef CANNOT_CHANGE_MODE_CLASS
369 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
371 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
375 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
376 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
377 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
381 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
382 old_cost
= this_cost
, did_change
= 1;
389 /* Try to replace operands in INSN with equivalent values that are already
390 in registers. This can be viewed as optional reloading.
392 For each non-register operand in the insn, see if any hard regs are
393 known to be equivalent to that operand. Record the alternatives which
394 can accept these hard registers. Among all alternatives, select the
395 ones which are better or equal to the one currently matching, where
396 "better" is in terms of '?' and '!' constraints. Among the remaining
397 alternatives, select the one which replaces most operands with
401 reload_cse_simplify_operands (rtx_insn
*insn
, rtx testreg
)
405 /* For each operand, all registers that are equivalent to it. */
406 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
408 const char *constraints
[MAX_RECOG_OPERANDS
];
410 /* Vector recording how bad an alternative is. */
411 int *alternative_reject
;
412 /* Vector recording how many registers can be introduced by choosing
414 int *alternative_nregs
;
415 /* Array of vectors recording, for each operand and each alternative,
416 which hard register to substitute, or -1 if the operand should be
418 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
419 /* Array of alternatives, sorted in order of decreasing desirability. */
420 int *alternative_order
;
422 extract_constrain_insn (insn
);
424 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
427 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
428 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
429 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
430 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
431 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
433 /* For each operand, find out which regs are equivalent. */
434 for (i
= 0; i
< recog_data
.n_operands
; i
++)
437 struct elt_loc_list
*l
;
440 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
442 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
443 right, so avoid the problem here. Likewise if we have a constant
444 and the insn pattern doesn't tell us the mode we need. */
445 if (LABEL_P (recog_data
.operand
[i
])
446 || (CONSTANT_P (recog_data
.operand
[i
])
447 && recog_data
.operand_mode
[i
] == VOIDmode
))
450 op
= recog_data
.operand
[i
];
451 #ifdef LOAD_EXTEND_OP
453 && GET_MODE_BITSIZE (GET_MODE (op
)) < BITS_PER_WORD
454 && LOAD_EXTEND_OP (GET_MODE (op
)) != UNKNOWN
)
456 rtx set
= single_set (insn
);
458 /* We might have multiple sets, some of which do implicit
459 extension. Punt on this for now. */
462 /* If the destination is also a MEM or a STRICT_LOW_PART, no
464 Also, if there is an explicit extension, we don't have to
465 worry about an implicit one. */
466 else if (MEM_P (SET_DEST (set
))
467 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
468 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
469 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
470 ; /* Continue ordinary processing. */
471 #ifdef CANNOT_CHANGE_MODE_CLASS
472 /* If the register cannot change mode to word_mode, it follows that
473 it cannot have been used in word_mode. */
474 else if (REG_P (SET_DEST (set
))
475 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
477 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
478 ; /* Continue ordinary processing. */
480 /* If this is a straight load, make the extension explicit. */
481 else if (REG_P (SET_DEST (set
))
482 && recog_data
.n_operands
== 2
483 && SET_SRC (set
) == op
484 && SET_DEST (set
) == recog_data
.operand
[1-i
])
486 validate_change (insn
, recog_data
.operand_loc
[i
],
487 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op
)),
490 validate_change (insn
, recog_data
.operand_loc
[1-i
],
491 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
493 if (! apply_change_group ())
495 return reload_cse_simplify_operands (insn
, testreg
);
498 /* ??? There might be arithmetic operations with memory that are
499 safe to optimize, but is it worth the trouble? */
502 #endif /* LOAD_EXTEND_OP */
503 if (side_effects_p (op
))
505 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0, VOIDmode
);
509 for (l
= v
->locs
; l
; l
= l
->next
)
511 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
514 alternative_mask preferred
= get_preferred_alternatives (insn
);
515 for (i
= 0; i
< recog_data
.n_operands
; i
++)
521 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
522 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
523 op_alt_regno
[i
][j
] = -1;
525 p
= constraints
[i
] = recog_data
.constraints
[i
];
526 mode
= recog_data
.operand_mode
[i
];
528 /* Add the reject values for each alternative given by the constraints
537 alternative_reject
[j
] += 3;
539 alternative_reject
[j
] += 300;
542 /* We won't change operands which are already registers. We
543 also don't want to modify output operands. */
544 regno
= true_regnum (recog_data
.operand
[i
]);
546 || constraints
[i
][0] == '='
547 || constraints
[i
][0] == '+')
550 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
552 enum reg_class rclass
= NO_REGS
;
554 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
557 SET_REGNO_RAW (testreg
, regno
);
558 PUT_MODE (testreg
, mode
);
560 /* We found a register equal to this operand. Now look for all
561 alternatives that can accept this register and have not been
562 assigned a register they can use yet. */
572 rclass
= reg_class_subunion
[rclass
][GENERAL_REGS
];
577 = (reg_class_subunion
579 [reg_class_for_constraint (lookup_constraint (p
))]);
583 /* See if REGNO fits this alternative, and set it up as the
584 replacement register if we don't have one for this
585 alternative yet and the operand being replaced is not
586 a cheap CONST_INT. */
587 if (op_alt_regno
[i
][j
] == -1
588 && TEST_BIT (preferred
, j
)
589 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
590 && (!CONST_INT_P (recog_data
.operand
[i
])
591 || (set_src_cost (recog_data
.operand
[i
],
592 optimize_bb_for_speed_p
593 (BLOCK_FOR_INSN (insn
)))
594 > set_src_cost (testreg
,
595 optimize_bb_for_speed_p
596 (BLOCK_FOR_INSN (insn
))))))
598 alternative_nregs
[j
]++;
599 op_alt_regno
[i
][j
] = regno
;
605 p
+= CONSTRAINT_LEN (c
, p
);
613 /* Record all alternatives which are better or equal to the currently
614 matching one in the alternative_order array. */
615 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
616 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
617 alternative_order
[j
++] = i
;
618 recog_data
.n_alternatives
= j
;
620 /* Sort it. Given a small number of alternatives, a dumb algorithm
621 won't hurt too much. */
622 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
625 int best_reject
= alternative_reject
[alternative_order
[i
]];
626 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
629 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
631 int this_reject
= alternative_reject
[alternative_order
[j
]];
632 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
634 if (this_reject
< best_reject
635 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
638 best_reject
= this_reject
;
639 best_nregs
= this_nregs
;
643 tmp
= alternative_order
[best
];
644 alternative_order
[best
] = alternative_order
[i
];
645 alternative_order
[i
] = tmp
;
648 /* Substitute the operands as determined by op_alt_regno for the best
650 j
= alternative_order
[0];
652 for (i
= 0; i
< recog_data
.n_operands
; i
++)
654 machine_mode mode
= recog_data
.operand_mode
[i
];
655 if (op_alt_regno
[i
][j
] == -1)
658 validate_change (insn
, recog_data
.operand_loc
[i
],
659 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
662 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
664 int op
= recog_data
.dup_num
[i
];
665 machine_mode mode
= recog_data
.operand_mode
[op
];
667 if (op_alt_regno
[op
][j
] == -1)
670 validate_change (insn
, recog_data
.dup_loc
[i
],
671 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
674 return apply_change_group ();
677 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
679 This code might also be useful when reload gave up on reg+reg addressing
680 because of clashes between the return register and INDEX_REG_CLASS. */
682 /* The maximum number of uses of a register we can keep track of to
683 replace them with reg+reg addressing. */
684 #define RELOAD_COMBINE_MAX_USES 16
686 /* Describes a recorded use of a register. */
689 /* The insn where a register has been used. */
691 /* Points to the memory reference enclosing the use, if any, NULL_RTX
694 /* Location of the register within INSN. */
696 /* The reverse uid of the insn. */
700 /* If the register is used in some unknown fashion, USE_INDEX is negative.
701 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
702 indicates where it is first set or clobbered.
703 Otherwise, USE_INDEX is the index of the last encountered use of the
704 register (which is first among these we have seen since we scan backwards).
705 USE_RUID indicates the first encountered, i.e. last, of these uses.
706 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
707 with a constant offset; OFFSET contains this constant in that case.
708 STORE_RUID is always meaningful if we only want to use a value in a
709 register in a different place: it denotes the next insn in the insn
710 stream (i.e. the last encountered) that sets or clobbers the register.
711 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
714 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
720 bool all_offsets_match
;
721 } reg_state
[FIRST_PSEUDO_REGISTER
];
723 /* Reverse linear uid. This is increased in reload_combine while scanning
724 the instructions from last to first. It is used to set last_label_ruid
725 and the store_ruid / use_ruid fields in reg_state. */
726 static int reload_combine_ruid
;
728 /* The RUID of the last label we encountered in reload_combine. */
729 static int last_label_ruid
;
731 /* The RUID of the last jump we encountered in reload_combine. */
732 static int last_jump_ruid
;
734 /* The register numbers of the first and last index register. A value of
735 -1 in LAST_INDEX_REG indicates that we've previously computed these
736 values and found no suitable index registers. */
737 static int first_index_reg
= -1;
738 static int last_index_reg
;
740 #define LABEL_LIVE(LABEL) \
741 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
743 /* Subroutine of reload_combine_split_ruids, called to fix up a single
744 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
747 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
749 if (*pruid
> split_ruid
)
753 /* Called when we insert a new insn in a position we've already passed in
754 the scan. Examine all our state, increasing all ruids that are higher
755 than SPLIT_RUID by one in order to make room for a new insn. */
758 reload_combine_split_ruids (int split_ruid
)
762 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
763 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
764 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
766 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
768 int j
, idx
= reg_state
[i
].use_index
;
769 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
770 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
771 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
775 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
777 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
783 /* Called when we are about to rescan a previously encountered insn with
784 reload_combine_note_use after modifying some part of it. This clears all
785 information about uses in that particular insn. */
788 reload_combine_purge_insn_uses (rtx_insn
*insn
)
792 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
794 int j
, k
, idx
= reg_state
[i
].use_index
;
797 j
= k
= RELOAD_COMBINE_MAX_USES
;
800 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
804 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
807 reg_state
[i
].use_index
= k
;
811 /* Called when we need to forget about all uses of REGNO after an insn
812 which is identified by RUID. */
815 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
817 int j
, k
, idx
= reg_state
[regno
].use_index
;
820 j
= k
= RELOAD_COMBINE_MAX_USES
;
823 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
827 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
830 reg_state
[regno
].use_index
= k
;
833 /* Find the use of REGNO with the ruid that is highest among those
834 lower than RUID_LIMIT, and return it if it is the only use of this
835 reg in the insn. Return NULL otherwise. */
837 static struct reg_use
*
838 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
840 int i
, best_ruid
= 0;
841 int use_idx
= reg_state
[regno
].use_index
;
842 struct reg_use
*retval
;
847 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
849 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
850 int this_ruid
= use
->ruid
;
851 if (this_ruid
>= ruid_limit
)
853 if (this_ruid
> best_ruid
)
855 best_ruid
= this_ruid
;
858 else if (this_ruid
== best_ruid
)
861 if (last_label_ruid
>= best_ruid
)
866 /* After we've moved an add insn, fix up any debug insns that occur
867 between the old location of the add and the new location. REG is
868 the destination register of the add insn; REPLACEMENT is the
869 SET_SRC of the add. FROM and TO specify the range in which we
870 should make this change on debug insns. */
873 fixup_debug_insns (rtx reg
, rtx replacement
, rtx_insn
*from
, rtx_insn
*to
)
876 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
880 if (!DEBUG_INSN_P (insn
))
883 t
= INSN_VAR_LOCATION_LOC (insn
);
884 t
= simplify_replace_rtx (t
, reg
, replacement
);
885 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
889 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
890 with SRC in the insn described by USE, taking costs into account. Return
891 true if we made the replacement. */
894 try_replace_in_use (struct reg_use
*use
, rtx reg
, rtx src
)
896 rtx_insn
*use_insn
= use
->insn
;
897 rtx mem
= use
->containing_mem
;
898 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
902 addr_space_t as
= MEM_ADDR_SPACE (mem
);
903 rtx oldaddr
= XEXP (mem
, 0);
904 rtx newaddr
= NULL_RTX
;
905 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
908 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
909 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
911 XEXP (mem
, 0) = newaddr
;
912 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
913 XEXP (mem
, 0) = oldaddr
;
914 if (new_cost
<= old_cost
915 && validate_change (use_insn
,
916 &XEXP (mem
, 0), newaddr
, 0))
922 rtx new_set
= single_set (use_insn
);
924 && REG_P (SET_DEST (new_set
))
925 && GET_CODE (SET_SRC (new_set
)) == PLUS
926 && REG_P (XEXP (SET_SRC (new_set
), 0))
927 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
930 int old_cost
= set_src_cost (SET_SRC (new_set
), speed
);
932 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
933 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
935 if (set_src_cost (new_src
, speed
) <= old_cost
936 && validate_change (use_insn
, &SET_SRC (new_set
),
944 /* Called by reload_combine when scanning INSN. This function tries to detect
945 patterns where a constant is added to a register, and the result is used
947 Return true if no further processing is needed on INSN; false if it wasn't
948 recognized and should be handled normally. */
951 reload_combine_recognize_const_pattern (rtx_insn
*insn
)
953 int from_ruid
= reload_combine_ruid
;
954 rtx set
, pat
, reg
, src
, addreg
;
958 rtx_insn
*add_moved_after_insn
= NULL
;
959 int add_moved_after_ruid
= 0;
960 int clobbered_regno
= -1;
962 set
= single_set (insn
);
966 reg
= SET_DEST (set
);
969 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1
970 || GET_MODE (reg
) != Pmode
971 || reg
== stack_pointer_rtx
)
976 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
977 uses of REG1 inside an address, or inside another add insn. If
978 possible and profitable, merge the addition into subsequent
980 if (GET_CODE (src
) != PLUS
981 || !REG_P (XEXP (src
, 0))
982 || !CONSTANT_P (XEXP (src
, 1)))
985 addreg
= XEXP (src
, 0);
986 must_move_add
= rtx_equal_p (reg
, addreg
);
988 pat
= PATTERN (insn
);
989 if (must_move_add
&& set
!= pat
)
991 /* We have to be careful when moving the add; apart from the
992 single_set there may also be clobbers. Recognize one special
993 case, that of one clobber alongside the set (likely a clobber
994 of the CC register). */
995 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
996 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
997 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
998 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
1000 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
1005 use
= reload_combine_closest_single_use (regno
, from_ruid
);
1008 /* Start the search for the next use from here. */
1009 from_ruid
= use
->ruid
;
1011 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
1013 bool delete_add
= false;
1014 rtx_insn
*use_insn
= use
->insn
;
1015 int use_ruid
= use
->ruid
;
1017 /* Avoid moving the add insn past a jump. */
1018 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
1021 /* If the add clobbers another hard reg in parallel, don't move
1022 it past a real set of this hard reg. */
1023 if (must_move_add
&& clobbered_regno
>= 0
1024 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
1028 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
1029 if (must_move_add
&& sets_cc0_p (PATTERN (use_insn
)))
1033 gcc_assert (reg_state
[regno
].store_ruid
<= use_ruid
);
1034 /* Avoid moving a use of ADDREG past a point where it is stored. */
1035 if (reg_state
[REGNO (addreg
)].store_ruid
> use_ruid
)
1038 /* We also must not move the addition past an insn that sets
1039 the same register, unless we can combine two add insns. */
1040 if (must_move_add
&& reg_state
[regno
].store_ruid
== use_ruid
)
1042 if (use
->containing_mem
== NULL_RTX
)
1048 if (try_replace_in_use (use
, reg
, src
))
1050 reload_combine_purge_insn_uses (use_insn
);
1051 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
1052 use_ruid
, NULL_RTX
);
1056 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1062 add_moved_after_insn
= use_insn
;
1063 add_moved_after_ruid
= use_ruid
;
1068 /* If we get here, we couldn't handle this use. */
1074 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1075 /* Process the add normally. */
1078 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1080 reorder_insns (insn
, insn
, add_moved_after_insn
);
1081 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1082 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1083 reload_combine_note_use (&PATTERN (insn
), insn
,
1084 add_moved_after_ruid
, NULL_RTX
);
1085 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1090 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1091 can handle and improve. Return true if no further processing is needed on
1092 INSN; false if it wasn't recognized and should be handled normally. */
1095 reload_combine_recognize_pattern (rtx_insn
*insn
)
1100 set
= single_set (insn
);
1101 if (set
== NULL_RTX
)
1104 reg
= SET_DEST (set
);
1105 src
= SET_SRC (set
);
1107 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1)
1110 regno
= REGNO (reg
);
1112 /* Look for (set (REGX) (CONST_INT))
1113 (set (REGX) (PLUS (REGX) (REGY)))
1115 ... (MEM (REGX)) ...
1117 (set (REGZ) (CONST_INT))
1119 ... (MEM (PLUS (REGZ) (REGY)))... .
1121 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1122 and that we know all uses of REGX before it dies.
1123 Also, explicitly check that REGX != REGY; our life information
1124 does not yet show whether REGY changes in this insn. */
1126 if (GET_CODE (src
) == PLUS
1127 && reg_state
[regno
].all_offsets_match
1128 && last_index_reg
!= -1
1129 && REG_P (XEXP (src
, 1))
1130 && rtx_equal_p (XEXP (src
, 0), reg
)
1131 && !rtx_equal_p (XEXP (src
, 1), reg
)
1132 && reg_state
[regno
].use_index
>= 0
1133 && reg_state
[regno
].use_index
< RELOAD_COMBINE_MAX_USES
1134 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1136 rtx base
= XEXP (src
, 1);
1137 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
1138 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1139 rtx index_reg
= NULL_RTX
;
1140 rtx reg_sum
= NULL_RTX
;
1143 /* Now we need to set INDEX_REG to an index register (denoted as
1144 REGZ in the illustration above) and REG_SUM to the expression
1145 register+register that we want to use to substitute uses of REG
1146 (typically in MEMs) with. First check REG and BASE for being
1147 index registers; we can use them even if they are not dead. */
1148 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1149 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1157 /* Otherwise, look for a free index register. Since we have
1158 checked above that neither REG nor BASE are index registers,
1159 if we find anything at all, it will be different from these
1161 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1163 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1164 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1165 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1166 && (call_used_regs
[i
] || df_regs_ever_live_p (i
))
1167 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1168 && !fixed_regs
[i
] && !global_regs
[i
]
1169 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1
1170 && targetm
.hard_regno_scratch_ok (i
))
1172 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1173 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1179 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1180 (REGY), i.e. BASE, is not clobbered before the last use we'll
1184 && CONST_INT_P (SET_SRC (prev_set
))
1185 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1186 && (reg_state
[REGNO (base
)].store_ruid
1187 <= reg_state
[regno
].use_ruid
))
1189 /* Change destination register and, if necessary, the constant
1190 value in PREV, the constant loading instruction. */
1191 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1192 if (reg_state
[regno
].offset
!= const0_rtx
)
1193 validate_change (prev
,
1194 &SET_SRC (prev_set
),
1195 GEN_INT (INTVAL (SET_SRC (prev_set
))
1196 + INTVAL (reg_state
[regno
].offset
)),
1199 /* Now for every use of REG that we have recorded, replace REG
1201 for (i
= reg_state
[regno
].use_index
;
1202 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1203 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1204 reg_state
[regno
].reg_use
[i
].usep
,
1205 /* Each change must have its own
1209 if (apply_change_group ())
1211 struct reg_use
*lowest_ruid
= NULL
;
1213 /* For every new use of REG_SUM, we have to record the use
1214 of BASE therein, i.e. operand 1. */
1215 for (i
= reg_state
[regno
].use_index
;
1216 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1218 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1219 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1220 use
->ruid
, use
->containing_mem
);
1221 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1225 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1227 /* Delete the reg-reg addition. */
1230 if (reg_state
[regno
].offset
!= const0_rtx
)
1231 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1233 remove_reg_equal_equiv_notes (prev
);
1235 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1244 reload_combine (void)
1246 rtx_insn
*insn
, *prev
;
1249 int min_labelno
, n_labels
;
1250 HARD_REG_SET ever_live_at_start
, *label_live
;
1252 /* To avoid wasting too much time later searching for an index register,
1253 determine the minimum and maximum index register numbers. */
1254 if (INDEX_REG_CLASS
== NO_REGS
)
1255 last_index_reg
= -1;
1256 else if (first_index_reg
== -1 && last_index_reg
== 0)
1258 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1259 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1261 if (first_index_reg
== -1)
1262 first_index_reg
= r
;
1267 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1268 to -1 so we'll know to quit early the next time we get here. */
1269 if (first_index_reg
== -1)
1271 last_index_reg
= -1;
1276 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1277 information is a bit fuzzy immediately after reload, but it's
1278 still good enough to determine which registers are live at a jump
1280 min_labelno
= get_first_label_num ();
1281 n_labels
= max_label_num () - min_labelno
;
1282 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1283 CLEAR_HARD_REG_SET (ever_live_at_start
);
1285 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
1287 insn
= BB_HEAD (bb
);
1291 bitmap live_in
= df_get_live_in (bb
);
1293 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1294 compute_use_by_pseudos (&live
, live_in
);
1295 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
1296 IOR_HARD_REG_SET (ever_live_at_start
, live
);
1300 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1301 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1302 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1304 reg_state
[r
].store_ruid
= 0;
1305 reg_state
[r
].real_store_ruid
= 0;
1307 reg_state
[r
].use_index
= -1;
1309 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1312 for (insn
= get_last_insn (); insn
; insn
= prev
)
1314 bool control_flow_insn
;
1317 prev
= PREV_INSN (insn
);
1319 /* We cannot do our optimization across labels. Invalidating all the use
1320 information we have would be costly, so we just note where the label
1321 is and then later disable any optimization that would cross it. */
1323 last_label_ruid
= reload_combine_ruid
;
1324 else if (BARRIER_P (insn
))
1326 /* Crossing a barrier resets all the use information. */
1327 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1328 if (! fixed_regs
[r
])
1329 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1331 else if (INSN_P (insn
) && volatile_insn_p (PATTERN (insn
)))
1332 /* Optimizations across insns being marked as volatile must be
1333 prevented. All the usage information is invalidated
1335 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1337 && reg_state
[r
].use_index
!= RELOAD_COMBINE_MAX_USES
)
1338 reg_state
[r
].use_index
= -1;
1340 if (! NONDEBUG_INSN_P (insn
))
1343 reload_combine_ruid
++;
1345 control_flow_insn
= control_flow_insn_p (insn
);
1346 if (control_flow_insn
)
1347 last_jump_ruid
= reload_combine_ruid
;
1349 if (reload_combine_recognize_const_pattern (insn
)
1350 || reload_combine_recognize_pattern (insn
))
1353 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
1359 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1360 if (call_used_regs
[r
])
1362 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1363 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1366 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1367 link
= XEXP (link
, 1))
1369 rtx setuse
= XEXP (link
, 0);
1370 rtx usage_rtx
= XEXP (setuse
, 0);
1371 if ((GET_CODE (setuse
) == USE
|| GET_CODE (setuse
) == CLOBBER
)
1372 && REG_P (usage_rtx
))
1375 unsigned int start_reg
= REGNO (usage_rtx
);
1376 unsigned int num_regs
1377 = hard_regno_nregs
[start_reg
][GET_MODE (usage_rtx
)];
1378 unsigned int end_reg
= start_reg
+ num_regs
- 1;
1379 for (i
= start_reg
; i
<= end_reg
; i
++)
1380 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1382 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1383 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1386 reg_state
[i
].use_index
= -1;
1391 if (control_flow_insn
&& !ANY_RETURN_P (PATTERN (insn
)))
1393 /* Non-spill registers might be used at the call destination in
1394 some unknown fashion, so we have to mark the unknown use. */
1397 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1398 && JUMP_LABEL (insn
))
1400 if (ANY_RETURN_P (JUMP_LABEL (insn
)))
1403 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1406 live
= &ever_live_at_start
;
1409 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1410 if (TEST_HARD_REG_BIT (*live
, r
))
1411 reg_state
[r
].use_index
= -1;
1414 reload_combine_note_use (&PATTERN (insn
), insn
, reload_combine_ruid
,
1417 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1419 if (REG_NOTE_KIND (note
) == REG_INC
&& REG_P (XEXP (note
, 0)))
1421 int regno
= REGNO (XEXP (note
, 0));
1422 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1423 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1424 reg_state
[regno
].use_index
= -1;
1432 /* Check if DST is a register or a subreg of a register; if it is,
1433 update store_ruid, real_store_ruid and use_index in the reg_state
1434 structure accordingly. Called via note_stores from reload_combine. */
1437 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1441 machine_mode mode
= GET_MODE (dst
);
1443 if (GET_CODE (dst
) == SUBREG
)
1445 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1446 GET_MODE (SUBREG_REG (dst
)),
1449 dst
= SUBREG_REG (dst
);
1452 /* Some targets do argument pushes without adding REG_INC notes. */
1456 dst
= XEXP (dst
, 0);
1457 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1458 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
1459 || GET_CODE (dst
) == PRE_MODIFY
|| GET_CODE (dst
) == POST_MODIFY
)
1461 regno
= REGNO (XEXP (dst
, 0));
1462 mode
= GET_MODE (XEXP (dst
, 0));
1463 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1465 /* We could probably do better, but for now mark the register
1466 as used in an unknown fashion and set/clobbered at this
1468 reg_state
[i
].use_index
= -1;
1469 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1470 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1479 regno
+= REGNO (dst
);
1481 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1482 careful with registers / register parts that are not full words.
1483 Similarly for ZERO_EXTRACT. */
1484 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1485 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1487 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1489 reg_state
[i
].use_index
= -1;
1490 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1491 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1496 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1498 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1499 if (GET_CODE (set
) == SET
)
1500 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1501 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1506 /* XP points to a piece of rtl that has to be checked for any uses of
1508 *XP is the pattern of INSN, or a part of it.
1509 Called from reload_combine, and recursively by itself. */
1511 reload_combine_note_use (rtx
*xp
, rtx_insn
*insn
, int ruid
, rtx containing_mem
)
1514 enum rtx_code code
= x
->code
;
1517 rtx offset
= const0_rtx
; /* For the REG case below. */
1522 if (REG_P (SET_DEST (x
)))
1524 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1530 /* If this is the USE of a return value, we can't change it. */
1531 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1533 /* Mark the return register as used in an unknown fashion. */
1534 rtx reg
= XEXP (x
, 0);
1535 int regno
= REGNO (reg
);
1536 int nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1538 while (--nregs
>= 0)
1539 reg_state
[regno
+ nregs
].use_index
= -1;
1545 if (REG_P (SET_DEST (x
)))
1547 /* No spurious CLOBBERs of pseudo registers may remain. */
1548 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1554 /* We are interested in (plus (reg) (const_int)) . */
1555 if (!REG_P (XEXP (x
, 0))
1556 || !CONST_INT_P (XEXP (x
, 1)))
1558 offset
= XEXP (x
, 1);
1563 int regno
= REGNO (x
);
1567 /* No spurious USEs of pseudo registers may remain. */
1568 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1570 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1572 /* We can't substitute into multi-hard-reg uses. */
1575 while (--nregs
>= 0)
1576 reg_state
[regno
+ nregs
].use_index
= -1;
1580 /* We may be called to update uses in previously seen insns.
1581 Don't add uses beyond the last store we saw. */
1582 if (ruid
< reg_state
[regno
].store_ruid
)
1585 /* If this register is already used in some unknown fashion, we
1587 If we decrement the index from zero to -1, we can't store more
1588 uses, so this register becomes used in an unknown fashion. */
1589 use_index
= --reg_state
[regno
].use_index
;
1593 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1595 /* This is the first use of this register we have seen since we
1596 marked it as dead. */
1597 reg_state
[regno
].offset
= offset
;
1598 reg_state
[regno
].all_offsets_match
= true;
1599 reg_state
[regno
].use_ruid
= ruid
;
1603 if (reg_state
[regno
].use_ruid
> ruid
)
1604 reg_state
[regno
].use_ruid
= ruid
;
1606 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1607 reg_state
[regno
].all_offsets_match
= false;
1610 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1611 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1612 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1613 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1625 /* Recursively process the components of X. */
1626 fmt
= GET_RTX_FORMAT (code
);
1627 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1630 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1631 else if (fmt
[i
] == 'E')
1633 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1634 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1640 /* See if we can reduce the cost of a constant by replacing a move
1641 with an add. We track situations in which a register is set to a
1642 constant or to a register plus a constant. */
1643 /* We cannot do our optimization across labels. Invalidating all the
1644 information about register contents we have would be costly, so we
1645 use move2add_last_label_luid to note where the label is and then
1646 later disable any optimization that would cross it.
1647 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1648 are only valid if reg_set_luid[n] is greater than
1649 move2add_last_label_luid.
1650 For a set that established a new (potential) base register with
1651 non-constant value, we use move2add_luid from the place where the
1652 setting insn is encountered; registers based off that base then
1653 get the same reg_set_luid. Constants all get
1654 move2add_last_label_luid + 1 as their reg_set_luid. */
1655 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1657 /* If reg_base_reg[n] is negative, register n has been set to
1658 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1659 If reg_base_reg[n] is non-negative, register n has been set to the
1660 sum of reg_offset[n] and the value of register reg_base_reg[n]
1661 before reg_set_luid[n], calculated in mode reg_mode[n] .
1662 For multi-hard-register registers, all but the first one are
1663 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1664 marks it as invalid. */
1665 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1666 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1667 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1668 static machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1670 /* move2add_luid is linearly increased while scanning the instructions
1671 from first to last. It is used to set reg_set_luid in
1672 reload_cse_move2add and move2add_note_store. */
1673 static int move2add_luid
;
1675 /* move2add_last_label_luid is set whenever a label is found. Labels
1676 invalidate all previously collected reg_offset data. */
1677 static int move2add_last_label_luid
;
1679 /* ??? We don't know how zero / sign extension is handled, hence we
1680 can't go from a narrower to a wider mode. */
1681 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1682 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1683 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1684 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1686 /* Record that REG is being set to a value with the mode of REG. */
1689 move2add_record_mode (rtx reg
)
1692 machine_mode mode
= GET_MODE (reg
);
1694 if (GET_CODE (reg
) == SUBREG
)
1696 regno
= subreg_regno (reg
);
1697 nregs
= subreg_nregs (reg
);
1699 else if (REG_P (reg
))
1701 regno
= REGNO (reg
);
1702 nregs
= hard_regno_nregs
[regno
][mode
];
1706 for (int i
= nregs
- 1; i
> 0; i
--)
1707 reg_mode
[regno
+ i
] = BLKmode
;
1708 reg_mode
[regno
] = mode
;
1711 /* Record that REG is being set to the sum of SYM and OFF. */
1714 move2add_record_sym_value (rtx reg
, rtx sym
, rtx off
)
1716 int regno
= REGNO (reg
);
1718 move2add_record_mode (reg
);
1719 reg_set_luid
[regno
] = move2add_luid
;
1720 reg_base_reg
[regno
] = -1;
1721 reg_symbol_ref
[regno
] = sym
;
1722 reg_offset
[regno
] = INTVAL (off
);
1725 /* Check if REGNO contains a valid value in MODE. */
1728 move2add_valid_value_p (int regno
, machine_mode mode
)
1730 if (reg_set_luid
[regno
] <= move2add_last_label_luid
)
1733 if (mode
!= reg_mode
[regno
])
1735 if (!MODES_OK_FOR_MOVE2ADD (mode
, reg_mode
[regno
]))
1737 /* The value loaded into regno in reg_mode[regno] is also valid in
1738 mode after truncation only if (REG:mode regno) is the lowpart of
1739 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1740 regno of the lowpart might be different. */
1741 int s_off
= subreg_lowpart_offset (mode
, reg_mode
[regno
]);
1742 s_off
= subreg_regno_offset (regno
, reg_mode
[regno
], s_off
, mode
);
1744 /* We could in principle adjust regno, check reg_mode[regno] to be
1745 BLKmode, and return s_off to the caller (vs. -1 for failure),
1746 but we currently have no callers that could make use of this
1751 for (int i
= hard_regno_nregs
[regno
][mode
] - 1; i
> 0; i
--)
1752 if (reg_mode
[regno
+ i
] != BLKmode
)
1757 /* This function is called with INSN that sets REG to (SYM + OFF),
1758 while REG is known to already have value (SYM + offset).
1759 This function tries to change INSN into an add instruction
1760 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1761 It also updates the information about REG's known value.
1762 Return true if we made a change. */
1765 move2add_use_add2_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1767 rtx pat
= PATTERN (insn
);
1768 rtx src
= SET_SRC (pat
);
1769 int regno
= REGNO (reg
);
1770 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[regno
],
1772 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1773 bool changed
= false;
1775 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1776 use (set (reg) (reg)) instead.
1777 We don't delete this insn, nor do we convert it into a
1778 note, to avoid losing register notes or the return
1779 value flag. jump2 already knows how to get rid of
1781 if (new_src
== const0_rtx
)
1783 /* If the constants are different, this is a
1784 truncation, that, if turned into (set (reg)
1785 (reg)), would be discarded. Maybe we should
1786 try a truncMN pattern? */
1787 if (INTVAL (off
) == reg_offset
[regno
])
1788 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1792 struct full_rtx_costs oldcst
, newcst
;
1793 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1795 get_full_set_rtx_cost (pat
, &oldcst
);
1796 SET_SRC (pat
) = tem
;
1797 get_full_set_rtx_cost (pat
, &newcst
);
1798 SET_SRC (pat
) = src
;
1800 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1801 && have_add2_insn (reg
, new_src
))
1802 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1803 else if (sym
== NULL_RTX
&& GET_MODE (reg
) != BImode
)
1805 machine_mode narrow_mode
;
1806 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1807 narrow_mode
!= VOIDmode
1808 && narrow_mode
!= GET_MODE (reg
);
1809 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1811 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1812 && ((reg_offset
[regno
] & ~GET_MODE_MASK (narrow_mode
))
1813 == (INTVAL (off
) & ~GET_MODE_MASK (narrow_mode
))))
1815 rtx narrow_reg
= gen_lowpart_common (narrow_mode
, reg
);
1816 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1819 = gen_rtx_SET (VOIDmode
,
1820 gen_rtx_STRICT_LOW_PART (VOIDmode
,
1823 get_full_set_rtx_cost (new_set
, &newcst
);
1824 if (costs_lt_p (&newcst
, &oldcst
, speed
))
1826 changed
= validate_change (insn
, &PATTERN (insn
),
1835 move2add_record_sym_value (reg
, sym
, off
);
1840 /* This function is called with INSN that sets REG to (SYM + OFF),
1841 but REG doesn't have known value (SYM + offset). This function
1842 tries to find another register which is known to already have
1843 value (SYM + offset) and change INSN into an add instruction
1844 (set (REG) (plus (the found register) (OFF - offset))) if such
1845 a register is found. It also updates the information about
1847 Return true iff we made a change. */
1850 move2add_use_add3_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1852 rtx pat
= PATTERN (insn
);
1853 rtx src
= SET_SRC (pat
);
1854 int regno
= REGNO (reg
);
1856 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1858 bool changed
= false;
1859 struct full_rtx_costs oldcst
, newcst
, mincst
;
1862 init_costs_to_max (&mincst
);
1863 get_full_set_rtx_cost (pat
, &oldcst
);
1865 plus_expr
= gen_rtx_PLUS (GET_MODE (reg
), reg
, const0_rtx
);
1866 SET_SRC (pat
) = plus_expr
;
1868 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1869 if (move2add_valid_value_p (i
, GET_MODE (reg
))
1870 && reg_base_reg
[i
] < 0
1871 && reg_symbol_ref
[i
] != NULL_RTX
1872 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1874 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[i
],
1876 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1877 use (set (reg) (reg)) instead.
1878 We don't delete this insn, nor do we convert it into a
1879 note, to avoid losing register notes or the return
1880 value flag. jump2 already knows how to get rid of
1882 if (new_src
== const0_rtx
)
1884 init_costs_to_zero (&mincst
);
1890 XEXP (plus_expr
, 1) = new_src
;
1891 get_full_set_rtx_cost (pat
, &newcst
);
1893 if (costs_lt_p (&newcst
, &mincst
, speed
))
1900 SET_SRC (pat
) = src
;
1902 if (costs_lt_p (&mincst
, &oldcst
, speed
))
1906 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1909 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[min_regno
],
1911 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1913 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1916 reg_set_luid
[regno
] = move2add_luid
;
1917 move2add_record_sym_value (reg
, sym
, off
);
1921 /* Convert move insns with constant inputs to additions if they are cheaper.
1922 Return true if any changes were made. */
1924 reload_cse_move2add (rtx_insn
*first
)
1928 bool changed
= false;
1930 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1932 reg_set_luid
[i
] = 0;
1934 reg_base_reg
[i
] = 0;
1935 reg_symbol_ref
[i
] = NULL_RTX
;
1936 reg_mode
[i
] = VOIDmode
;
1939 move2add_last_label_luid
= 0;
1941 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1947 move2add_last_label_luid
= move2add_luid
;
1948 /* We're going to increment move2add_luid twice after a
1949 label, so that we can use move2add_last_label_luid + 1 as
1950 the luid for constants. */
1954 if (! INSN_P (insn
))
1956 pat
= PATTERN (insn
);
1957 /* For simplicity, we only perform this optimization on
1958 straightforward SETs. */
1959 if (GET_CODE (pat
) == SET
1960 && REG_P (SET_DEST (pat
)))
1962 rtx reg
= SET_DEST (pat
);
1963 int regno
= REGNO (reg
);
1964 rtx src
= SET_SRC (pat
);
1966 /* Check if we have valid information on the contents of this
1967 register in the mode of REG. */
1968 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
1969 && dbg_cnt (cse2_move2add
))
1971 /* Try to transform (set (REGX) (CONST_INT A))
1973 (set (REGX) (CONST_INT B))
1975 (set (REGX) (CONST_INT A))
1977 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1979 (set (REGX) (CONST_INT A))
1981 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1984 if (CONST_INT_P (src
)
1985 && reg_base_reg
[regno
] < 0
1986 && reg_symbol_ref
[regno
] == NULL_RTX
)
1988 changed
|= move2add_use_add2_insn (reg
, NULL_RTX
, src
, insn
);
1992 /* Try to transform (set (REGX) (REGY))
1993 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1996 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1999 (set (REGX) (PLUS (REGX) (CONST_INT A)))
2001 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
2002 else if (REG_P (src
)
2003 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
2004 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
2005 && move2add_valid_value_p (REGNO (src
), GET_MODE (reg
)))
2007 rtx_insn
*next
= next_nonnote_nondebug_insn (insn
);
2010 set
= single_set (next
);
2012 && SET_DEST (set
) == reg
2013 && GET_CODE (SET_SRC (set
)) == PLUS
2014 && XEXP (SET_SRC (set
), 0) == reg
2015 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
2017 rtx src3
= XEXP (SET_SRC (set
), 1);
2018 unsigned HOST_WIDE_INT added_offset
= UINTVAL (src3
);
2019 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
2020 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
2022 gen_int_mode (added_offset
2026 bool success
= false;
2027 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
2029 if (new_src
== const0_rtx
)
2030 /* See above why we create (set (reg) (reg)) here. */
2032 = validate_change (next
, &SET_SRC (set
), reg
, 0);
2035 rtx old_src
= SET_SRC (set
);
2036 struct full_rtx_costs oldcst
, newcst
;
2037 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
2039 get_full_set_rtx_cost (set
, &oldcst
);
2040 SET_SRC (set
) = tem
;
2041 get_full_set_src_cost (tem
, &newcst
);
2042 SET_SRC (set
) = old_src
;
2043 costs_add_n_insns (&oldcst
, 1);
2045 if (costs_lt_p (&newcst
, &oldcst
, speed
)
2046 && have_add2_insn (reg
, new_src
))
2048 rtx newpat
= gen_rtx_SET (VOIDmode
, reg
, tem
);
2050 = validate_change (next
, &PATTERN (next
),
2058 move2add_record_mode (reg
);
2060 = trunc_int_for_mode (added_offset
+ base_offset
,
2068 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2070 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2072 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2074 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2075 if ((GET_CODE (src
) == SYMBOL_REF
2076 || (GET_CODE (src
) == CONST
2077 && GET_CODE (XEXP (src
, 0)) == PLUS
2078 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
2079 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
2080 && dbg_cnt (cse2_move2add
))
2084 if (GET_CODE (src
) == SYMBOL_REF
)
2091 sym
= XEXP (XEXP (src
, 0), 0);
2092 off
= XEXP (XEXP (src
, 0), 1);
2095 /* If the reg already contains the value which is sum of
2096 sym and some constant value, we can use an add2 insn. */
2097 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
2098 && reg_base_reg
[regno
] < 0
2099 && reg_symbol_ref
[regno
] != NULL_RTX
2100 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
2101 changed
|= move2add_use_add2_insn (reg
, sym
, off
, insn
);
2103 /* Otherwise, we have to find a register whose value is sum
2104 of sym and some constant value. */
2106 changed
|= move2add_use_add3_insn (reg
, sym
, off
, insn
);
2112 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2114 if (REG_NOTE_KIND (note
) == REG_INC
2115 && REG_P (XEXP (note
, 0)))
2117 /* Reset the information about this register. */
2118 int regno
= REGNO (XEXP (note
, 0));
2119 if (regno
< FIRST_PSEUDO_REGISTER
)
2121 move2add_record_mode (XEXP (note
, 0));
2122 reg_mode
[regno
] = VOIDmode
;
2126 note_stores (PATTERN (insn
), move2add_note_store
, insn
);
2128 /* If INSN is a conditional branch, we try to extract an
2129 implicit set out of it. */
2130 if (any_condjump_p (insn
))
2132 rtx cnd
= fis_get_condition (insn
);
2135 && GET_CODE (cnd
) == NE
2136 && REG_P (XEXP (cnd
, 0))
2137 && !reg_set_p (XEXP (cnd
, 0), insn
)
2138 /* The following two checks, which are also in
2139 move2add_note_store, are intended to reduce the
2140 number of calls to gen_rtx_SET to avoid memory
2141 allocation if possible. */
2142 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
2143 && hard_regno_nregs
[REGNO (XEXP (cnd
, 0))][GET_MODE (XEXP (cnd
, 0))] == 1
2144 && CONST_INT_P (XEXP (cnd
, 1)))
2147 gen_rtx_SET (VOIDmode
, XEXP (cnd
, 0), XEXP (cnd
, 1));
2148 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
2152 /* If this is a CALL_INSN, all call used registers are stored with
2156 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
2158 if (call_used_regs
[i
])
2159 /* Reset the information about this register. */
2160 reg_mode
[i
] = VOIDmode
;
2167 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2169 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2170 Called from reload_cse_move2add via note_stores. */
2173 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2175 rtx_insn
*insn
= (rtx_insn
*) data
;
2176 unsigned int regno
= 0;
2177 machine_mode mode
= GET_MODE (dst
);
2179 /* Some targets do argument pushes without adding REG_INC notes. */
2183 dst
= XEXP (dst
, 0);
2184 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2185 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2186 reg_mode
[REGNO (XEXP (dst
, 0))] = VOIDmode
;
2190 if (GET_CODE (dst
) == SUBREG
)
2191 regno
= subreg_regno (dst
);
2192 else if (REG_P (dst
))
2193 regno
= REGNO (dst
);
2197 if (SCALAR_INT_MODE_P (mode
)
2198 && GET_CODE (set
) == SET
)
2200 rtx note
, sym
= NULL_RTX
;
2203 note
= find_reg_equal_equiv_note (insn
);
2204 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2206 sym
= XEXP (note
, 0);
2209 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2210 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2211 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2212 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2214 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2215 off
= XEXP (XEXP (XEXP (note
, 0), 0), 1);
2218 if (sym
!= NULL_RTX
)
2220 move2add_record_sym_value (dst
, sym
, off
);
2225 if (SCALAR_INT_MODE_P (mode
)
2226 && GET_CODE (set
) == SET
2227 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2228 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2230 rtx src
= SET_SRC (set
);
2232 unsigned HOST_WIDE_INT offset
;
2235 switch (GET_CODE (src
))
2238 if (REG_P (XEXP (src
, 0)))
2240 base_reg
= XEXP (src
, 0);
2242 if (CONST_INT_P (XEXP (src
, 1)))
2243 offset
= UINTVAL (XEXP (src
, 1));
2244 else if (REG_P (XEXP (src
, 1))
2245 && move2add_valid_value_p (REGNO (XEXP (src
, 1)), mode
))
2247 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0
2248 && reg_symbol_ref
[REGNO (XEXP (src
, 1))] == NULL_RTX
)
2249 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2250 /* Maybe the first register is known to be a
2252 else if (move2add_valid_value_p (REGNO (base_reg
), mode
)
2253 && reg_base_reg
[REGNO (base_reg
)] < 0
2254 && reg_symbol_ref
[REGNO (base_reg
)] == NULL_RTX
)
2256 offset
= reg_offset
[REGNO (base_reg
)];
2257 base_reg
= XEXP (src
, 1);
2276 /* Start tracking the register as a constant. */
2277 reg_base_reg
[regno
] = -1;
2278 reg_symbol_ref
[regno
] = NULL_RTX
;
2279 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2280 /* We assign the same luid to all registers set to constants. */
2281 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2282 move2add_record_mode (dst
);
2289 base_regno
= REGNO (base_reg
);
2290 /* If information about the base register is not valid, set it
2291 up as a new base register, pretending its value is known
2292 starting from the current insn. */
2293 if (!move2add_valid_value_p (base_regno
, mode
))
2295 reg_base_reg
[base_regno
] = base_regno
;
2296 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2297 reg_offset
[base_regno
] = 0;
2298 reg_set_luid
[base_regno
] = move2add_luid
;
2299 gcc_assert (GET_MODE (base_reg
) == mode
);
2300 move2add_record_mode (base_reg
);
2303 /* Copy base information from our base register. */
2304 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2305 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2306 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2308 /* Compute the sum of the offsets or constants. */
2310 = trunc_int_for_mode (offset
+ reg_offset
[base_regno
], mode
);
2312 move2add_record_mode (dst
);
2317 /* Invalidate the contents of the register. */
2318 move2add_record_mode (dst
);
2319 reg_mode
[regno
] = VOIDmode
;
2325 const pass_data pass_data_postreload_cse
=
2327 RTL_PASS
, /* type */
2328 "postreload", /* name */
2329 OPTGROUP_NONE
, /* optinfo_flags */
2330 TV_RELOAD_CSE_REGS
, /* tv_id */
2331 0, /* properties_required */
2332 0, /* properties_provided */
2333 0, /* properties_destroyed */
2334 0, /* todo_flags_start */
2335 TODO_df_finish
, /* todo_flags_finish */
2338 class pass_postreload_cse
: public rtl_opt_pass
2341 pass_postreload_cse (gcc::context
*ctxt
)
2342 : rtl_opt_pass (pass_data_postreload_cse
, ctxt
)
2345 /* opt_pass methods: */
2346 virtual bool gate (function
*) { return (optimize
> 0 && reload_completed
); }
2348 virtual unsigned int execute (function
*);
2350 }; // class pass_postreload_cse
2353 pass_postreload_cse::execute (function
*fun
)
2355 if (!dbg_cnt (postreload_cse
))
2358 /* Do a very simple CSE pass over just the hard registers. */
2359 reload_cse_regs (get_insns ());
2360 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2361 Remove any EH edges associated with them. */
2362 if (fun
->can_throw_non_call_exceptions
2363 && purge_all_dead_edges ())
2372 make_pass_postreload_cse (gcc::context
*ctxt
)
2374 return new pass_postreload_cse (ctxt
);