1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
38 #include "cfgcleanup.h"
41 #include "tree-pass.h"
44 static int reload_cse_noop_set_p (rtx
);
45 static bool reload_cse_simplify (rtx_insn
*, rtx
);
46 static void reload_cse_regs_1 (void);
47 static int reload_cse_simplify_set (rtx
, rtx_insn
*);
48 static int reload_cse_simplify_operands (rtx_insn
*, rtx
);
50 static void reload_combine (void);
51 static void reload_combine_note_use (rtx
*, rtx_insn
*, int, rtx
);
52 static void reload_combine_note_store (rtx
, const_rtx
, void *);
54 static bool reload_cse_move2add (rtx_insn
*);
55 static void move2add_note_store (rtx
, const_rtx
, void *);
57 /* Call cse / combine like post-reload optimization phases.
58 FIRST is the first instruction. */
61 reload_cse_regs (rtx_insn
*first ATTRIBUTE_UNUSED
)
66 moves_converted
= reload_cse_move2add (first
);
67 if (flag_expensive_optimizations
)
75 /* See whether a single set SET is a noop. */
77 reload_cse_noop_set_p (rtx set
)
79 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
82 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
85 /* Try to simplify INSN. Return true if the CFG may have changed. */
87 reload_cse_simplify (rtx_insn
*insn
, rtx testreg
)
89 rtx body
= PATTERN (insn
);
90 basic_block insn_bb
= BLOCK_FOR_INSN (insn
);
91 unsigned insn_bb_succs
= EDGE_COUNT (insn_bb
->succs
);
93 /* If NO_FUNCTION_CSE has been set by the target, then we should not try
94 to cse function calls. */
95 if (NO_FUNCTION_CSE
&& CALL_P (insn
))
98 if (GET_CODE (body
) == SET
)
102 /* Simplify even if we may think it is a no-op.
103 We may think a memory load of a value smaller than WORD_SIZE
104 is redundant because we haven't taken into account possible
105 implicit extension. reload_cse_simplify_set() will bring
106 this out, so it's safer to simplify before we delete. */
107 count
+= reload_cse_simplify_set (body
, insn
);
109 if (!count
&& reload_cse_noop_set_p (body
))
111 if (check_for_inc_dec (insn
))
112 delete_insn_and_edges (insn
);
113 /* We're done with this insn. */
118 apply_change_group ();
120 reload_cse_simplify_operands (insn
, testreg
);
122 else if (GET_CODE (body
) == PARALLEL
)
126 rtx value
= NULL_RTX
;
128 /* Registers mentioned in the clobber list for an asm cannot be reused
129 within the body of the asm. Invalidate those registers now so that
130 we don't try to substitute values for them. */
131 if (asm_noperands (body
) >= 0)
133 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
135 rtx part
= XVECEXP (body
, 0, i
);
136 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
137 cselib_invalidate_rtx (XEXP (part
, 0));
141 /* If every action in a PARALLEL is a noop, we can delete
142 the entire PARALLEL. */
143 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
145 rtx part
= XVECEXP (body
, 0, i
);
146 if (GET_CODE (part
) == SET
)
148 if (! reload_cse_noop_set_p (part
))
150 if (REG_P (SET_DEST (part
))
151 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
155 value
= SET_DEST (part
);
158 else if (GET_CODE (part
) != CLOBBER
159 && GET_CODE (part
) != USE
)
165 if (check_for_inc_dec (insn
))
166 delete_insn_and_edges (insn
);
167 /* We're done with this insn. */
171 /* It's not a no-op, but we can try to simplify it. */
172 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
173 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
174 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
177 apply_change_group ();
179 reload_cse_simplify_operands (insn
, testreg
);
183 return (EDGE_COUNT (insn_bb
->succs
) != insn_bb_succs
);
186 /* Do a very simple CSE pass over the hard registers.
188 This function detects no-op moves where we happened to assign two
189 different pseudo-registers to the same hard register, and then
190 copied one to the other. Reload will generate a useless
191 instruction copying a register to itself.
193 This function also detects cases where we load a value from memory
194 into two different registers, and (if memory is more expensive than
195 registers) changes it to simply copy the first register into the
198 Another optimization is performed that scans the operands of each
199 instruction to see whether the value is already available in a
200 hard register. It then replaces the operand with the hard register
201 if possible, much like an optional reload would. */
204 reload_cse_regs_1 (void)
206 bool cfg_changed
= false;
209 rtx testreg
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
211 cselib_init (CSELIB_RECORD_MEMORY
);
212 init_alias_analysis ();
214 FOR_EACH_BB_FN (bb
, cfun
)
215 FOR_BB_INSNS (bb
, insn
)
218 cfg_changed
|= reload_cse_simplify (insn
, testreg
);
220 cselib_process_insn (insn
);
224 end_alias_analysis ();
230 /* Try to simplify a single SET instruction. SET is the set pattern.
231 INSN is the instruction it came from.
232 This function only handles one case: if we set a register to a value
233 which is not a register, we try to find that value in some other register
234 and change the set into a register copy. */
237 reload_cse_simplify_set (rtx set
, rtx_insn
*insn
)
245 struct elt_loc_list
*l
;
246 enum rtx_code extend_op
= UNKNOWN
;
247 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
249 dreg
= true_regnum (SET_DEST (set
));
254 if (side_effects_p (src
) || true_regnum (src
) >= 0)
257 dclass
= REGNO_REG_CLASS (dreg
);
259 /* When replacing a memory with a register, we need to honor assumptions
260 that combine made wrt the contents of sign bits. We'll do this by
261 generating an extend instruction instead of a reg->reg copy. Thus
262 the destination must be a register that we can widen. */
264 && (extend_op
= load_extend_op (GET_MODE (src
))) != UNKNOWN
265 && !REG_P (SET_DEST (set
)))
268 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0, VOIDmode
);
272 /* If memory loads are cheaper than register copies, don't change them. */
274 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
275 else if (REG_P (src
))
276 old_cost
= register_move_cost (GET_MODE (src
),
277 REGNO_REG_CLASS (REGNO (src
)), dclass
);
279 old_cost
= set_src_cost (src
, GET_MODE (SET_DEST (set
)), speed
);
281 for (l
= val
->locs
; l
; l
= l
->next
)
283 rtx this_rtx
= l
->loc
;
286 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
288 if (extend_op
!= UNKNOWN
)
292 if (!CONST_SCALAR_INT_P (this_rtx
))
298 result
= wide_int::from (rtx_mode_t (this_rtx
,
300 BITS_PER_WORD
, UNSIGNED
);
303 result
= wide_int::from (rtx_mode_t (this_rtx
,
305 BITS_PER_WORD
, SIGNED
);
310 this_rtx
= immed_wide_int_const (result
, word_mode
);
313 this_cost
= set_src_cost (this_rtx
, GET_MODE (SET_DEST (set
)), speed
);
315 else if (REG_P (this_rtx
))
317 if (extend_op
!= UNKNOWN
)
319 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
320 this_cost
= set_src_cost (this_rtx
, word_mode
, speed
);
323 this_cost
= register_move_cost (GET_MODE (this_rtx
),
324 REGNO_REG_CLASS (REGNO (this_rtx
)),
330 /* If equal costs, prefer registers over anything else. That
331 tends to lead to smaller instructions on some machines. */
332 if (this_cost
< old_cost
333 || (this_cost
== old_cost
335 && !REG_P (SET_SRC (set
))))
337 if (extend_op
!= UNKNOWN
338 #ifdef CANNOT_CHANGE_MODE_CLASS
339 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
341 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
345 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
346 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
347 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
350 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
351 old_cost
= this_cost
, did_change
= 1;
358 /* Try to replace operands in INSN with equivalent values that are already
359 in registers. This can be viewed as optional reloading.
361 For each non-register operand in the insn, see if any hard regs are
362 known to be equivalent to that operand. Record the alternatives which
363 can accept these hard registers. Among all alternatives, select the
364 ones which are better or equal to the one currently matching, where
365 "better" is in terms of '?' and '!' constraints. Among the remaining
366 alternatives, select the one which replaces most operands with
370 reload_cse_simplify_operands (rtx_insn
*insn
, rtx testreg
)
374 /* For each operand, all registers that are equivalent to it. */
375 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
377 const char *constraints
[MAX_RECOG_OPERANDS
];
379 /* Vector recording how bad an alternative is. */
380 int *alternative_reject
;
381 /* Vector recording how many registers can be introduced by choosing
383 int *alternative_nregs
;
384 /* Array of vectors recording, for each operand and each alternative,
385 which hard register to substitute, or -1 if the operand should be
387 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
388 /* Array of alternatives, sorted in order of decreasing desirability. */
389 int *alternative_order
;
391 extract_constrain_insn (insn
);
393 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
396 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
397 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
398 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
399 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
400 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
402 /* For each operand, find out which regs are equivalent. */
403 for (i
= 0; i
< recog_data
.n_operands
; i
++)
406 struct elt_loc_list
*l
;
409 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
411 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
412 right, so avoid the problem here. Similarly NOTE_INSN_DELETED_LABEL.
413 Likewise if we have a constant and the insn pattern doesn't tell us
415 if (LABEL_P (recog_data
.operand
[i
])
416 || (NOTE_P (recog_data
.operand
[i
])
417 && NOTE_KIND (recog_data
.operand
[i
]) == NOTE_INSN_DELETED_LABEL
)
418 || (CONSTANT_P (recog_data
.operand
[i
])
419 && recog_data
.operand_mode
[i
] == VOIDmode
))
422 op
= recog_data
.operand
[i
];
423 if (MEM_P (op
) && load_extend_op (GET_MODE (op
)) != UNKNOWN
)
425 rtx set
= single_set (insn
);
427 /* We might have multiple sets, some of which do implicit
428 extension. Punt on this for now. */
431 /* If the destination is also a MEM or a STRICT_LOW_PART, no
433 Also, if there is an explicit extension, we don't have to
434 worry about an implicit one. */
435 else if (MEM_P (SET_DEST (set
))
436 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
437 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
438 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
439 ; /* Continue ordinary processing. */
440 #ifdef CANNOT_CHANGE_MODE_CLASS
441 /* If the register cannot change mode to word_mode, it follows that
442 it cannot have been used in word_mode. */
443 else if (REG_P (SET_DEST (set
))
444 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
446 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
447 ; /* Continue ordinary processing. */
449 /* If this is a straight load, make the extension explicit. */
450 else if (REG_P (SET_DEST (set
))
451 && recog_data
.n_operands
== 2
452 && SET_SRC (set
) == op
453 && SET_DEST (set
) == recog_data
.operand
[1-i
])
455 validate_change (insn
, recog_data
.operand_loc
[i
],
456 gen_rtx_fmt_e (load_extend_op (GET_MODE (op
)),
459 validate_change (insn
, recog_data
.operand_loc
[1-i
],
460 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
462 if (! apply_change_group ())
464 return reload_cse_simplify_operands (insn
, testreg
);
467 /* ??? There might be arithmetic operations with memory that are
468 safe to optimize, but is it worth the trouble? */
472 if (side_effects_p (op
))
474 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0, VOIDmode
);
478 for (l
= v
->locs
; l
; l
= l
->next
)
480 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
483 alternative_mask preferred
= get_preferred_alternatives (insn
);
484 for (i
= 0; i
< recog_data
.n_operands
; i
++)
490 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
491 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
492 op_alt_regno
[i
][j
] = -1;
494 p
= constraints
[i
] = recog_data
.constraints
[i
];
495 mode
= recog_data
.operand_mode
[i
];
497 /* Add the reject values for each alternative given by the constraints
506 alternative_reject
[j
] += 3;
508 alternative_reject
[j
] += 300;
511 /* We won't change operands which are already registers. We
512 also don't want to modify output operands. */
513 regno
= true_regnum (recog_data
.operand
[i
]);
515 || constraints
[i
][0] == '='
516 || constraints
[i
][0] == '+')
519 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
521 enum reg_class rclass
= NO_REGS
;
523 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
526 set_mode_and_regno (testreg
, mode
, regno
);
528 /* We found a register equal to this operand. Now look for all
529 alternatives that can accept this register and have not been
530 assigned a register they can use yet. */
540 rclass
= reg_class_subunion
[rclass
][GENERAL_REGS
];
545 = (reg_class_subunion
547 [reg_class_for_constraint (lookup_constraint (p
))]);
551 /* See if REGNO fits this alternative, and set it up as the
552 replacement register if we don't have one for this
553 alternative yet and the operand being replaced is not
554 a cheap CONST_INT. */
555 if (op_alt_regno
[i
][j
] == -1
556 && TEST_BIT (preferred
, j
)
557 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
558 && (!CONST_INT_P (recog_data
.operand
[i
])
559 || (set_src_cost (recog_data
.operand
[i
], mode
,
560 optimize_bb_for_speed_p
561 (BLOCK_FOR_INSN (insn
)))
562 > set_src_cost (testreg
, mode
,
563 optimize_bb_for_speed_p
564 (BLOCK_FOR_INSN (insn
))))))
566 alternative_nregs
[j
]++;
567 op_alt_regno
[i
][j
] = regno
;
573 p
+= CONSTRAINT_LEN (c
, p
);
581 /* Record all alternatives which are better or equal to the currently
582 matching one in the alternative_order array. */
583 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
584 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
585 alternative_order
[j
++] = i
;
586 recog_data
.n_alternatives
= j
;
588 /* Sort it. Given a small number of alternatives, a dumb algorithm
589 won't hurt too much. */
590 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
593 int best_reject
= alternative_reject
[alternative_order
[i
]];
594 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
596 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
598 int this_reject
= alternative_reject
[alternative_order
[j
]];
599 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
601 if (this_reject
< best_reject
602 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
605 best_reject
= this_reject
;
606 best_nregs
= this_nregs
;
610 std::swap (alternative_order
[best
], alternative_order
[i
]);
613 /* Substitute the operands as determined by op_alt_regno for the best
615 j
= alternative_order
[0];
617 for (i
= 0; i
< recog_data
.n_operands
; i
++)
619 machine_mode mode
= recog_data
.operand_mode
[i
];
620 if (op_alt_regno
[i
][j
] == -1)
623 validate_change (insn
, recog_data
.operand_loc
[i
],
624 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
627 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
629 int op
= recog_data
.dup_num
[i
];
630 machine_mode mode
= recog_data
.operand_mode
[op
];
632 if (op_alt_regno
[op
][j
] == -1)
635 validate_change (insn
, recog_data
.dup_loc
[i
],
636 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
639 return apply_change_group ();
642 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
644 This code might also be useful when reload gave up on reg+reg addressing
645 because of clashes between the return register and INDEX_REG_CLASS. */
647 /* The maximum number of uses of a register we can keep track of to
648 replace them with reg+reg addressing. */
649 #define RELOAD_COMBINE_MAX_USES 16
651 /* Describes a recorded use of a register. */
654 /* The insn where a register has been used. */
656 /* Points to the memory reference enclosing the use, if any, NULL_RTX
659 /* Location of the register within INSN. */
661 /* The reverse uid of the insn. */
665 /* If the register is used in some unknown fashion, USE_INDEX is negative.
666 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
667 indicates where it is first set or clobbered.
668 Otherwise, USE_INDEX is the index of the last encountered use of the
669 register (which is first among these we have seen since we scan backwards).
670 USE_RUID indicates the first encountered, i.e. last, of these uses.
671 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
672 with a constant offset; OFFSET contains this constant in that case.
673 STORE_RUID is always meaningful if we only want to use a value in a
674 register in a different place: it denotes the next insn in the insn
675 stream (i.e. the last encountered) that sets or clobbers the register.
676 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
679 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
685 bool all_offsets_match
;
686 } reg_state
[FIRST_PSEUDO_REGISTER
];
688 /* Reverse linear uid. This is increased in reload_combine while scanning
689 the instructions from last to first. It is used to set last_label_ruid
690 and the store_ruid / use_ruid fields in reg_state. */
691 static int reload_combine_ruid
;
693 /* The RUID of the last label we encountered in reload_combine. */
694 static int last_label_ruid
;
696 /* The RUID of the last jump we encountered in reload_combine. */
697 static int last_jump_ruid
;
699 /* The register numbers of the first and last index register. A value of
700 -1 in LAST_INDEX_REG indicates that we've previously computed these
701 values and found no suitable index registers. */
702 static int first_index_reg
= -1;
703 static int last_index_reg
;
705 #define LABEL_LIVE(LABEL) \
706 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
708 /* Subroutine of reload_combine_split_ruids, called to fix up a single
709 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
712 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
714 if (*pruid
> split_ruid
)
718 /* Called when we insert a new insn in a position we've already passed in
719 the scan. Examine all our state, increasing all ruids that are higher
720 than SPLIT_RUID by one in order to make room for a new insn. */
723 reload_combine_split_ruids (int split_ruid
)
727 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
728 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
729 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
731 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
733 int j
, idx
= reg_state
[i
].use_index
;
734 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
735 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
736 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
740 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
742 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
748 /* Called when we are about to rescan a previously encountered insn with
749 reload_combine_note_use after modifying some part of it. This clears all
750 information about uses in that particular insn. */
753 reload_combine_purge_insn_uses (rtx_insn
*insn
)
757 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
759 int j
, k
, idx
= reg_state
[i
].use_index
;
762 j
= k
= RELOAD_COMBINE_MAX_USES
;
765 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
769 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
772 reg_state
[i
].use_index
= k
;
776 /* Called when we need to forget about all uses of REGNO after an insn
777 which is identified by RUID. */
780 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
782 int j
, k
, idx
= reg_state
[regno
].use_index
;
785 j
= k
= RELOAD_COMBINE_MAX_USES
;
788 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
792 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
795 reg_state
[regno
].use_index
= k
;
798 /* Find the use of REGNO with the ruid that is highest among those
799 lower than RUID_LIMIT, and return it if it is the only use of this
800 reg in the insn. Return NULL otherwise. */
802 static struct reg_use
*
803 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
805 int i
, best_ruid
= 0;
806 int use_idx
= reg_state
[regno
].use_index
;
807 struct reg_use
*retval
;
812 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
814 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
815 int this_ruid
= use
->ruid
;
816 if (this_ruid
>= ruid_limit
)
818 if (this_ruid
> best_ruid
)
820 best_ruid
= this_ruid
;
823 else if (this_ruid
== best_ruid
)
826 if (last_label_ruid
>= best_ruid
)
831 /* After we've moved an add insn, fix up any debug insns that occur
832 between the old location of the add and the new location. REG is
833 the destination register of the add insn; REPLACEMENT is the
834 SET_SRC of the add. FROM and TO specify the range in which we
835 should make this change on debug insns. */
838 fixup_debug_insns (rtx reg
, rtx replacement
, rtx_insn
*from
, rtx_insn
*to
)
841 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
845 if (!DEBUG_INSN_P (insn
))
848 t
= INSN_VAR_LOCATION_LOC (insn
);
849 t
= simplify_replace_rtx (t
, reg
, replacement
);
850 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
854 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
855 with SRC in the insn described by USE, taking costs into account. Return
856 true if we made the replacement. */
859 try_replace_in_use (struct reg_use
*use
, rtx reg
, rtx src
)
861 rtx_insn
*use_insn
= use
->insn
;
862 rtx mem
= use
->containing_mem
;
863 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
867 addr_space_t as
= MEM_ADDR_SPACE (mem
);
868 rtx oldaddr
= XEXP (mem
, 0);
869 rtx newaddr
= NULL_RTX
;
870 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
873 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
874 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
876 XEXP (mem
, 0) = newaddr
;
877 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
878 XEXP (mem
, 0) = oldaddr
;
879 if (new_cost
<= old_cost
880 && validate_change (use_insn
,
881 &XEXP (mem
, 0), newaddr
, 0))
887 rtx new_set
= single_set (use_insn
);
889 && REG_P (SET_DEST (new_set
))
890 && GET_CODE (SET_SRC (new_set
)) == PLUS
891 && REG_P (XEXP (SET_SRC (new_set
), 0))
892 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
895 machine_mode mode
= GET_MODE (SET_DEST (new_set
));
896 int old_cost
= set_src_cost (SET_SRC (new_set
), mode
, speed
);
898 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
899 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
901 if (set_src_cost (new_src
, mode
, speed
) <= old_cost
902 && validate_change (use_insn
, &SET_SRC (new_set
),
910 /* Called by reload_combine when scanning INSN. This function tries to detect
911 patterns where a constant is added to a register, and the result is used
913 Return true if no further processing is needed on INSN; false if it wasn't
914 recognized and should be handled normally. */
917 reload_combine_recognize_const_pattern (rtx_insn
*insn
)
919 int from_ruid
= reload_combine_ruid
;
920 rtx set
, pat
, reg
, src
, addreg
;
924 rtx_insn
*add_moved_after_insn
= NULL
;
925 int add_moved_after_ruid
= 0;
926 int clobbered_regno
= -1;
928 set
= single_set (insn
);
932 reg
= SET_DEST (set
);
935 || REG_NREGS (reg
) != 1
936 || GET_MODE (reg
) != Pmode
937 || reg
== stack_pointer_rtx
)
942 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
943 uses of REG1 inside an address, or inside another add insn. If
944 possible and profitable, merge the addition into subsequent
946 if (GET_CODE (src
) != PLUS
947 || !REG_P (XEXP (src
, 0))
948 || !CONSTANT_P (XEXP (src
, 1)))
951 addreg
= XEXP (src
, 0);
952 must_move_add
= rtx_equal_p (reg
, addreg
);
954 pat
= PATTERN (insn
);
955 if (must_move_add
&& set
!= pat
)
957 /* We have to be careful when moving the add; apart from the
958 single_set there may also be clobbers. Recognize one special
959 case, that of one clobber alongside the set (likely a clobber
960 of the CC register). */
961 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
962 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
963 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
964 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
966 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
971 use
= reload_combine_closest_single_use (regno
, from_ruid
);
974 /* Start the search for the next use from here. */
975 from_ruid
= use
->ruid
;
977 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
979 bool delete_add
= false;
980 rtx_insn
*use_insn
= use
->insn
;
981 int use_ruid
= use
->ruid
;
983 /* Avoid moving the add insn past a jump. */
984 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
987 /* If the add clobbers another hard reg in parallel, don't move
988 it past a real set of this hard reg. */
989 if (must_move_add
&& clobbered_regno
>= 0
990 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
993 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
994 if (HAVE_cc0
&& must_move_add
&& sets_cc0_p (PATTERN (use_insn
)))
997 gcc_assert (reg_state
[regno
].store_ruid
<= use_ruid
);
998 /* Avoid moving a use of ADDREG past a point where it is stored. */
999 if (reg_state
[REGNO (addreg
)].store_ruid
> use_ruid
)
1002 /* We also must not move the addition past an insn that sets
1003 the same register, unless we can combine two add insns. */
1004 if (must_move_add
&& reg_state
[regno
].store_ruid
== use_ruid
)
1006 if (use
->containing_mem
== NULL_RTX
)
1012 if (try_replace_in_use (use
, reg
, src
))
1014 reload_combine_purge_insn_uses (use_insn
);
1015 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
1016 use_ruid
, NULL_RTX
);
1020 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1026 add_moved_after_insn
= use_insn
;
1027 add_moved_after_ruid
= use_ruid
;
1032 /* If we get here, we couldn't handle this use. */
1038 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1039 /* Process the add normally. */
1042 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1044 reorder_insns (insn
, insn
, add_moved_after_insn
);
1045 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1046 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1047 reload_combine_note_use (&PATTERN (insn
), insn
,
1048 add_moved_after_ruid
, NULL_RTX
);
1049 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1054 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1055 can handle and improve. Return true if no further processing is needed on
1056 INSN; false if it wasn't recognized and should be handled normally. */
1059 reload_combine_recognize_pattern (rtx_insn
*insn
)
1063 set
= single_set (insn
);
1064 if (set
== NULL_RTX
)
1067 reg
= SET_DEST (set
);
1068 src
= SET_SRC (set
);
1069 if (!REG_P (reg
) || REG_NREGS (reg
) != 1)
1072 unsigned int regno
= REGNO (reg
);
1073 machine_mode mode
= GET_MODE (reg
);
1075 if (reg_state
[regno
].use_index
< 0
1076 || reg_state
[regno
].use_index
>= RELOAD_COMBINE_MAX_USES
)
1079 for (int i
= reg_state
[regno
].use_index
;
1080 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1082 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1083 if (GET_MODE (*use
->usep
) != mode
)
1087 /* Look for (set (REGX) (CONST_INT))
1088 (set (REGX) (PLUS (REGX) (REGY)))
1090 ... (MEM (REGX)) ...
1092 (set (REGZ) (CONST_INT))
1094 ... (MEM (PLUS (REGZ) (REGY)))... .
1096 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1097 and that we know all uses of REGX before it dies.
1098 Also, explicitly check that REGX != REGY; our life information
1099 does not yet show whether REGY changes in this insn. */
1101 if (GET_CODE (src
) == PLUS
1102 && reg_state
[regno
].all_offsets_match
1103 && last_index_reg
!= -1
1104 && REG_P (XEXP (src
, 1))
1105 && rtx_equal_p (XEXP (src
, 0), reg
)
1106 && !rtx_equal_p (XEXP (src
, 1), reg
)
1107 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1109 rtx base
= XEXP (src
, 1);
1110 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
1111 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1112 rtx index_reg
= NULL_RTX
;
1113 rtx reg_sum
= NULL_RTX
;
1116 /* Now we need to set INDEX_REG to an index register (denoted as
1117 REGZ in the illustration above) and REG_SUM to the expression
1118 register+register that we want to use to substitute uses of REG
1119 (typically in MEMs) with. First check REG and BASE for being
1120 index registers; we can use them even if they are not dead. */
1121 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1122 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1130 /* Otherwise, look for a free index register. Since we have
1131 checked above that neither REG nor BASE are index registers,
1132 if we find anything at all, it will be different from these
1134 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1136 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1137 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1138 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1139 && (call_used_regs
[i
] || df_regs_ever_live_p (i
))
1140 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1141 && !fixed_regs
[i
] && !global_regs
[i
]
1142 && hard_regno_nregs (i
, GET_MODE (reg
)) == 1
1143 && targetm
.hard_regno_scratch_ok (i
))
1145 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1146 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1152 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1153 (REGY), i.e. BASE, is not clobbered before the last use we'll
1157 && CONST_INT_P (SET_SRC (prev_set
))
1158 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1159 && (reg_state
[REGNO (base
)].store_ruid
1160 <= reg_state
[regno
].use_ruid
))
1162 /* Change destination register and, if necessary, the constant
1163 value in PREV, the constant loading instruction. */
1164 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1165 if (reg_state
[regno
].offset
!= const0_rtx
)
1166 validate_change (prev
,
1167 &SET_SRC (prev_set
),
1168 GEN_INT (INTVAL (SET_SRC (prev_set
))
1169 + INTVAL (reg_state
[regno
].offset
)),
1172 /* Now for every use of REG that we have recorded, replace REG
1174 for (i
= reg_state
[regno
].use_index
;
1175 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1176 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1177 reg_state
[regno
].reg_use
[i
].usep
,
1178 /* Each change must have its own
1182 if (apply_change_group ())
1184 struct reg_use
*lowest_ruid
= NULL
;
1186 /* For every new use of REG_SUM, we have to record the use
1187 of BASE therein, i.e. operand 1. */
1188 for (i
= reg_state
[regno
].use_index
;
1189 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1191 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1192 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1193 use
->ruid
, use
->containing_mem
);
1194 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1198 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1200 /* Delete the reg-reg addition. */
1203 if (reg_state
[regno
].offset
!= const0_rtx
1204 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1206 && remove_reg_equal_equiv_notes (prev
))
1207 df_notes_rescan (prev
);
1209 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1218 reload_combine (void)
1220 rtx_insn
*insn
, *prev
;
1223 int min_labelno
, n_labels
;
1224 HARD_REG_SET ever_live_at_start
, *label_live
;
1226 /* To avoid wasting too much time later searching for an index register,
1227 determine the minimum and maximum index register numbers. */
1228 if (INDEX_REG_CLASS
== NO_REGS
)
1229 last_index_reg
= -1;
1230 else if (first_index_reg
== -1 && last_index_reg
== 0)
1232 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1233 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1235 if (first_index_reg
== -1)
1236 first_index_reg
= r
;
1241 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1242 to -1 so we'll know to quit early the next time we get here. */
1243 if (first_index_reg
== -1)
1245 last_index_reg
= -1;
1250 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1251 information is a bit fuzzy immediately after reload, but it's
1252 still good enough to determine which registers are live at a jump
1254 min_labelno
= get_first_label_num ();
1255 n_labels
= max_label_num () - min_labelno
;
1256 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1257 CLEAR_HARD_REG_SET (ever_live_at_start
);
1259 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
1261 insn
= BB_HEAD (bb
);
1265 bitmap live_in
= df_get_live_in (bb
);
1267 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1268 compute_use_by_pseudos (&live
, live_in
);
1269 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
1270 IOR_HARD_REG_SET (ever_live_at_start
, live
);
1274 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1275 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1276 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1278 reg_state
[r
].store_ruid
= 0;
1279 reg_state
[r
].real_store_ruid
= 0;
1281 reg_state
[r
].use_index
= -1;
1283 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1286 for (insn
= get_last_insn (); insn
; insn
= prev
)
1288 bool control_flow_insn
;
1291 prev
= PREV_INSN (insn
);
1293 /* We cannot do our optimization across labels. Invalidating all the use
1294 information we have would be costly, so we just note where the label
1295 is and then later disable any optimization that would cross it. */
1297 last_label_ruid
= reload_combine_ruid
;
1298 else if (BARRIER_P (insn
))
1300 /* Crossing a barrier resets all the use information. */
1301 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1302 if (! fixed_regs
[r
])
1303 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1305 else if (INSN_P (insn
) && volatile_insn_p (PATTERN (insn
)))
1306 /* Optimizations across insns being marked as volatile must be
1307 prevented. All the usage information is invalidated
1309 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1311 && reg_state
[r
].use_index
!= RELOAD_COMBINE_MAX_USES
)
1312 reg_state
[r
].use_index
= -1;
1314 if (! NONDEBUG_INSN_P (insn
))
1317 reload_combine_ruid
++;
1319 control_flow_insn
= control_flow_insn_p (insn
);
1320 if (control_flow_insn
)
1321 last_jump_ruid
= reload_combine_ruid
;
1323 if (reload_combine_recognize_const_pattern (insn
)
1324 || reload_combine_recognize_pattern (insn
))
1327 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
1332 HARD_REG_SET used_regs
;
1334 get_call_reg_set_usage (insn
, &used_regs
, call_used_reg_set
);
1336 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1337 if (TEST_HARD_REG_BIT (used_regs
, r
))
1339 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1340 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1343 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1344 link
= XEXP (link
, 1))
1346 rtx setuse
= XEXP (link
, 0);
1347 rtx usage_rtx
= XEXP (setuse
, 0);
1348 if ((GET_CODE (setuse
) == USE
|| GET_CODE (setuse
) == CLOBBER
)
1349 && REG_P (usage_rtx
))
1351 unsigned int end_regno
= END_REGNO (usage_rtx
);
1352 for (unsigned int i
= REGNO (usage_rtx
); i
< end_regno
; ++i
)
1353 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1355 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1356 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1359 reg_state
[i
].use_index
= -1;
1364 if (control_flow_insn
&& !ANY_RETURN_P (PATTERN (insn
)))
1366 /* Non-spill registers might be used at the call destination in
1367 some unknown fashion, so we have to mark the unknown use. */
1370 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1371 && JUMP_LABEL (insn
))
1373 if (ANY_RETURN_P (JUMP_LABEL (insn
)))
1376 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1379 live
= &ever_live_at_start
;
1382 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1383 if (TEST_HARD_REG_BIT (*live
, r
))
1384 reg_state
[r
].use_index
= -1;
1387 reload_combine_note_use (&PATTERN (insn
), insn
, reload_combine_ruid
,
1390 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1392 if (REG_NOTE_KIND (note
) == REG_INC
&& REG_P (XEXP (note
, 0)))
1394 int regno
= REGNO (XEXP (note
, 0));
1395 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1396 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1397 reg_state
[regno
].use_index
= -1;
1405 /* Check if DST is a register or a subreg of a register; if it is,
1406 update store_ruid, real_store_ruid and use_index in the reg_state
1407 structure accordingly. Called via note_stores from reload_combine. */
1410 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1414 machine_mode mode
= GET_MODE (dst
);
1416 if (GET_CODE (dst
) == SUBREG
)
1418 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1419 GET_MODE (SUBREG_REG (dst
)),
1422 dst
= SUBREG_REG (dst
);
1425 /* Some targets do argument pushes without adding REG_INC notes. */
1429 dst
= XEXP (dst
, 0);
1430 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1431 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
1432 || GET_CODE (dst
) == PRE_MODIFY
|| GET_CODE (dst
) == POST_MODIFY
)
1434 unsigned int end_regno
= END_REGNO (XEXP (dst
, 0));
1435 for (unsigned int i
= REGNO (XEXP (dst
, 0)); i
< end_regno
; ++i
)
1437 /* We could probably do better, but for now mark the register
1438 as used in an unknown fashion and set/clobbered at this
1440 reg_state
[i
].use_index
= -1;
1441 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1442 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1451 regno
+= REGNO (dst
);
1453 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1454 careful with registers / register parts that are not full words.
1455 Similarly for ZERO_EXTRACT. */
1456 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1457 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1459 for (i
= end_hard_regno (mode
, regno
) - 1; i
>= regno
; i
--)
1461 reg_state
[i
].use_index
= -1;
1462 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1463 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1468 for (i
= end_hard_regno (mode
, regno
) - 1; i
>= regno
; i
--)
1470 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1471 if (GET_CODE (set
) == SET
)
1472 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1473 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1478 /* XP points to a piece of rtl that has to be checked for any uses of
1480 *XP is the pattern of INSN, or a part of it.
1481 Called from reload_combine, and recursively by itself. */
1483 reload_combine_note_use (rtx
*xp
, rtx_insn
*insn
, int ruid
, rtx containing_mem
)
1486 enum rtx_code code
= x
->code
;
1489 rtx offset
= const0_rtx
; /* For the REG case below. */
1494 if (REG_P (SET_DEST (x
)))
1496 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1502 /* If this is the USE of a return value, we can't change it. */
1503 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1505 /* Mark the return register as used in an unknown fashion. */
1506 rtx reg
= XEXP (x
, 0);
1507 unsigned int end_regno
= END_REGNO (reg
);
1508 for (unsigned int regno
= REGNO (reg
); regno
< end_regno
; ++regno
)
1509 reg_state
[regno
].use_index
= -1;
1515 if (REG_P (SET_DEST (x
)))
1517 /* No spurious CLOBBERs of pseudo registers may remain. */
1518 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1524 /* We are interested in (plus (reg) (const_int)) . */
1525 if (!REG_P (XEXP (x
, 0))
1526 || !CONST_INT_P (XEXP (x
, 1)))
1528 offset
= XEXP (x
, 1);
1533 int regno
= REGNO (x
);
1537 /* No spurious USEs of pseudo registers may remain. */
1538 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1540 nregs
= REG_NREGS (x
);
1542 /* We can't substitute into multi-hard-reg uses. */
1545 while (--nregs
>= 0)
1546 reg_state
[regno
+ nregs
].use_index
= -1;
1550 /* We may be called to update uses in previously seen insns.
1551 Don't add uses beyond the last store we saw. */
1552 if (ruid
< reg_state
[regno
].store_ruid
)
1555 /* If this register is already used in some unknown fashion, we
1557 If we decrement the index from zero to -1, we can't store more
1558 uses, so this register becomes used in an unknown fashion. */
1559 use_index
= --reg_state
[regno
].use_index
;
1563 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1565 /* This is the first use of this register we have seen since we
1566 marked it as dead. */
1567 reg_state
[regno
].offset
= offset
;
1568 reg_state
[regno
].all_offsets_match
= true;
1569 reg_state
[regno
].use_ruid
= ruid
;
1573 if (reg_state
[regno
].use_ruid
> ruid
)
1574 reg_state
[regno
].use_ruid
= ruid
;
1576 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1577 reg_state
[regno
].all_offsets_match
= false;
1580 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1581 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1582 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1583 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1595 /* Recursively process the components of X. */
1596 fmt
= GET_RTX_FORMAT (code
);
1597 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1600 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1601 else if (fmt
[i
] == 'E')
1603 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1604 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1610 /* See if we can reduce the cost of a constant by replacing a move
1611 with an add. We track situations in which a register is set to a
1612 constant or to a register plus a constant. */
1613 /* We cannot do our optimization across labels. Invalidating all the
1614 information about register contents we have would be costly, so we
1615 use move2add_last_label_luid to note where the label is and then
1616 later disable any optimization that would cross it.
1617 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1618 are only valid if reg_set_luid[n] is greater than
1619 move2add_last_label_luid.
1620 For a set that established a new (potential) base register with
1621 non-constant value, we use move2add_luid from the place where the
1622 setting insn is encountered; registers based off that base then
1623 get the same reg_set_luid. Constants all get
1624 move2add_last_label_luid + 1 as their reg_set_luid. */
1625 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1627 /* If reg_base_reg[n] is negative, register n has been set to
1628 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1629 If reg_base_reg[n] is non-negative, register n has been set to the
1630 sum of reg_offset[n] and the value of register reg_base_reg[n]
1631 before reg_set_luid[n], calculated in mode reg_mode[n] .
1632 For multi-hard-register registers, all but the first one are
1633 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1634 marks it as invalid. */
1635 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1636 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1637 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1638 static machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1640 /* move2add_luid is linearly increased while scanning the instructions
1641 from first to last. It is used to set reg_set_luid in
1642 reload_cse_move2add and move2add_note_store. */
1643 static int move2add_luid
;
1645 /* move2add_last_label_luid is set whenever a label is found. Labels
1646 invalidate all previously collected reg_offset data. */
1647 static int move2add_last_label_luid
;
1649 /* ??? We don't know how zero / sign extension is handled, hence we
1650 can't go from a narrower to a wider mode. */
1651 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1652 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1653 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1654 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1656 /* Record that REG is being set to a value with the mode of REG. */
1659 move2add_record_mode (rtx reg
)
1662 machine_mode mode
= GET_MODE (reg
);
1664 if (GET_CODE (reg
) == SUBREG
)
1666 regno
= subreg_regno (reg
);
1667 nregs
= subreg_nregs (reg
);
1669 else if (REG_P (reg
))
1671 regno
= REGNO (reg
);
1672 nregs
= REG_NREGS (reg
);
1676 for (int i
= nregs
- 1; i
> 0; i
--)
1677 reg_mode
[regno
+ i
] = BLKmode
;
1678 reg_mode
[regno
] = mode
;
1681 /* Record that REG is being set to the sum of SYM and OFF. */
1684 move2add_record_sym_value (rtx reg
, rtx sym
, rtx off
)
1686 int regno
= REGNO (reg
);
1688 move2add_record_mode (reg
);
1689 reg_set_luid
[regno
] = move2add_luid
;
1690 reg_base_reg
[regno
] = -1;
1691 reg_symbol_ref
[regno
] = sym
;
1692 reg_offset
[regno
] = INTVAL (off
);
1695 /* Check if REGNO contains a valid value in MODE. */
1698 move2add_valid_value_p (int regno
, scalar_int_mode mode
)
1700 if (reg_set_luid
[regno
] <= move2add_last_label_luid
)
1703 if (mode
!= reg_mode
[regno
])
1705 scalar_int_mode old_mode
;
1706 if (!is_a
<scalar_int_mode
> (reg_mode
[regno
], &old_mode
)
1707 || !MODES_OK_FOR_MOVE2ADD (mode
, old_mode
))
1709 /* The value loaded into regno in reg_mode[regno] is also valid in
1710 mode after truncation only if (REG:mode regno) is the lowpart of
1711 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1712 regno of the lowpart might be different. */
1713 int s_off
= subreg_lowpart_offset (mode
, old_mode
);
1714 s_off
= subreg_regno_offset (regno
, old_mode
, s_off
, mode
);
1716 /* We could in principle adjust regno, check reg_mode[regno] to be
1717 BLKmode, and return s_off to the caller (vs. -1 for failure),
1718 but we currently have no callers that could make use of this
1723 for (int i
= end_hard_regno (mode
, regno
) - 1; i
> regno
; i
--)
1724 if (reg_mode
[i
] != BLKmode
)
1729 /* This function is called with INSN that sets REG (of mode MODE)
1730 to (SYM + OFF), while REG is known to already have value (SYM + offset).
1731 This function tries to change INSN into an add instruction
1732 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1733 It also updates the information about REG's known value.
1734 Return true if we made a change. */
1737 move2add_use_add2_insn (scalar_int_mode mode
, rtx reg
, rtx sym
, rtx off
,
1740 rtx pat
= PATTERN (insn
);
1741 rtx src
= SET_SRC (pat
);
1742 int regno
= REGNO (reg
);
1743 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[regno
], mode
);
1744 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1745 bool changed
= false;
1747 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1748 use (set (reg) (reg)) instead.
1749 We don't delete this insn, nor do we convert it into a
1750 note, to avoid losing register notes or the return
1751 value flag. jump2 already knows how to get rid of
1753 if (new_src
== const0_rtx
)
1755 /* If the constants are different, this is a
1756 truncation, that, if turned into (set (reg)
1757 (reg)), would be discarded. Maybe we should
1758 try a truncMN pattern? */
1759 if (INTVAL (off
) == reg_offset
[regno
])
1760 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1764 struct full_rtx_costs oldcst
, newcst
;
1765 rtx tem
= gen_rtx_PLUS (mode
, reg
, new_src
);
1767 get_full_set_rtx_cost (pat
, &oldcst
);
1768 SET_SRC (pat
) = tem
;
1769 get_full_set_rtx_cost (pat
, &newcst
);
1770 SET_SRC (pat
) = src
;
1772 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1773 && have_add2_insn (reg
, new_src
))
1774 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1775 else if (sym
== NULL_RTX
&& mode
!= BImode
)
1777 scalar_int_mode narrow_mode
;
1778 FOR_EACH_MODE_UNTIL (narrow_mode
, mode
)
1780 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1781 && ((reg_offset
[regno
] & ~GET_MODE_MASK (narrow_mode
))
1782 == (INTVAL (off
) & ~GET_MODE_MASK (narrow_mode
))))
1784 rtx narrow_reg
= gen_lowpart_common (narrow_mode
, reg
);
1785 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1788 = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode
,
1791 get_full_set_rtx_cost (new_set
, &newcst
);
1792 if (costs_lt_p (&newcst
, &oldcst
, speed
))
1794 changed
= validate_change (insn
, &PATTERN (insn
),
1803 move2add_record_sym_value (reg
, sym
, off
);
1808 /* This function is called with INSN that sets REG (of mode MODE) to
1809 (SYM + OFF), but REG doesn't have known value (SYM + offset). This
1810 function tries to find another register which is known to already have
1811 value (SYM + offset) and change INSN into an add instruction
1812 (set (REG) (plus (the found register) (OFF - offset))) if such
1813 a register is found. It also updates the information about
1815 Return true iff we made a change. */
1818 move2add_use_add3_insn (scalar_int_mode mode
, rtx reg
, rtx sym
, rtx off
,
1821 rtx pat
= PATTERN (insn
);
1822 rtx src
= SET_SRC (pat
);
1823 int regno
= REGNO (reg
);
1825 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1827 bool changed
= false;
1828 struct full_rtx_costs oldcst
, newcst
, mincst
;
1831 init_costs_to_max (&mincst
);
1832 get_full_set_rtx_cost (pat
, &oldcst
);
1834 plus_expr
= gen_rtx_PLUS (GET_MODE (reg
), reg
, const0_rtx
);
1835 SET_SRC (pat
) = plus_expr
;
1837 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1838 if (move2add_valid_value_p (i
, mode
)
1839 && reg_base_reg
[i
] < 0
1840 && reg_symbol_ref
[i
] != NULL_RTX
1841 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1843 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[i
],
1845 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1846 use (set (reg) (reg)) instead.
1847 We don't delete this insn, nor do we convert it into a
1848 note, to avoid losing register notes or the return
1849 value flag. jump2 already knows how to get rid of
1851 if (new_src
== const0_rtx
)
1853 init_costs_to_zero (&mincst
);
1859 XEXP (plus_expr
, 1) = new_src
;
1860 get_full_set_rtx_cost (pat
, &newcst
);
1862 if (costs_lt_p (&newcst
, &mincst
, speed
))
1869 SET_SRC (pat
) = src
;
1871 if (costs_lt_p (&mincst
, &oldcst
, speed
))
1875 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1878 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[min_regno
],
1880 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1882 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1885 reg_set_luid
[regno
] = move2add_luid
;
1886 move2add_record_sym_value (reg
, sym
, off
);
1890 /* Convert move insns with constant inputs to additions if they are cheaper.
1891 Return true if any changes were made. */
1893 reload_cse_move2add (rtx_insn
*first
)
1897 bool changed
= false;
1899 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1901 reg_set_luid
[i
] = 0;
1903 reg_base_reg
[i
] = 0;
1904 reg_symbol_ref
[i
] = NULL_RTX
;
1905 reg_mode
[i
] = VOIDmode
;
1908 move2add_last_label_luid
= 0;
1910 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1916 move2add_last_label_luid
= move2add_luid
;
1917 /* We're going to increment move2add_luid twice after a
1918 label, so that we can use move2add_last_label_luid + 1 as
1919 the luid for constants. */
1923 if (! INSN_P (insn
))
1925 pat
= PATTERN (insn
);
1926 /* For simplicity, we only perform this optimization on
1927 straightforward SETs. */
1928 scalar_int_mode mode
;
1929 if (GET_CODE (pat
) == SET
1930 && REG_P (SET_DEST (pat
))
1931 && is_a
<scalar_int_mode
> (GET_MODE (SET_DEST (pat
)), &mode
))
1933 rtx reg
= SET_DEST (pat
);
1934 int regno
= REGNO (reg
);
1935 rtx src
= SET_SRC (pat
);
1937 /* Check if we have valid information on the contents of this
1938 register in the mode of REG. */
1939 if (move2add_valid_value_p (regno
, mode
)
1940 && dbg_cnt (cse2_move2add
))
1942 /* Try to transform (set (REGX) (CONST_INT A))
1944 (set (REGX) (CONST_INT B))
1946 (set (REGX) (CONST_INT A))
1948 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1950 (set (REGX) (CONST_INT A))
1952 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1955 if (CONST_INT_P (src
)
1956 && reg_base_reg
[regno
] < 0
1957 && reg_symbol_ref
[regno
] == NULL_RTX
)
1959 changed
|= move2add_use_add2_insn (mode
, reg
, NULL_RTX
,
1964 /* Try to transform (set (REGX) (REGY))
1965 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1968 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1971 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1973 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1974 else if (REG_P (src
)
1975 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1976 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1977 && move2add_valid_value_p (REGNO (src
), mode
))
1979 rtx_insn
*next
= next_nonnote_nondebug_insn (insn
);
1982 set
= single_set (next
);
1984 && SET_DEST (set
) == reg
1985 && GET_CODE (SET_SRC (set
)) == PLUS
1986 && XEXP (SET_SRC (set
), 0) == reg
1987 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
1989 rtx src3
= XEXP (SET_SRC (set
), 1);
1990 unsigned HOST_WIDE_INT added_offset
= UINTVAL (src3
);
1991 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
1992 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
1994 gen_int_mode (added_offset
1998 bool success
= false;
1999 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
2001 if (new_src
== const0_rtx
)
2002 /* See above why we create (set (reg) (reg)) here. */
2004 = validate_change (next
, &SET_SRC (set
), reg
, 0);
2007 rtx old_src
= SET_SRC (set
);
2008 struct full_rtx_costs oldcst
, newcst
;
2009 rtx tem
= gen_rtx_PLUS (mode
, reg
, new_src
);
2011 get_full_set_rtx_cost (set
, &oldcst
);
2012 SET_SRC (set
) = tem
;
2013 get_full_set_src_cost (tem
, mode
, &newcst
);
2014 SET_SRC (set
) = old_src
;
2015 costs_add_n_insns (&oldcst
, 1);
2017 if (costs_lt_p (&newcst
, &oldcst
, speed
)
2018 && have_add2_insn (reg
, new_src
))
2020 rtx newpat
= gen_rtx_SET (reg
, tem
);
2022 = validate_change (next
, &PATTERN (next
),
2030 move2add_record_mode (reg
);
2032 = trunc_int_for_mode (added_offset
+ base_offset
,
2040 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2042 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2044 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2046 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2047 if ((GET_CODE (src
) == SYMBOL_REF
2048 || (GET_CODE (src
) == CONST
2049 && GET_CODE (XEXP (src
, 0)) == PLUS
2050 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
2051 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
2052 && dbg_cnt (cse2_move2add
))
2056 if (GET_CODE (src
) == SYMBOL_REF
)
2063 sym
= XEXP (XEXP (src
, 0), 0);
2064 off
= XEXP (XEXP (src
, 0), 1);
2067 /* If the reg already contains the value which is sum of
2068 sym and some constant value, we can use an add2 insn. */
2069 if (move2add_valid_value_p (regno
, mode
)
2070 && reg_base_reg
[regno
] < 0
2071 && reg_symbol_ref
[regno
] != NULL_RTX
2072 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
2073 changed
|= move2add_use_add2_insn (mode
, reg
, sym
, off
, insn
);
2075 /* Otherwise, we have to find a register whose value is sum
2076 of sym and some constant value. */
2078 changed
|= move2add_use_add3_insn (mode
, reg
, sym
, off
, insn
);
2084 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2086 if (REG_NOTE_KIND (note
) == REG_INC
2087 && REG_P (XEXP (note
, 0)))
2089 /* Reset the information about this register. */
2090 int regno
= REGNO (XEXP (note
, 0));
2091 if (regno
< FIRST_PSEUDO_REGISTER
)
2093 move2add_record_mode (XEXP (note
, 0));
2094 reg_mode
[regno
] = VOIDmode
;
2098 note_stores (PATTERN (insn
), move2add_note_store
, insn
);
2100 /* If INSN is a conditional branch, we try to extract an
2101 implicit set out of it. */
2102 if (any_condjump_p (insn
))
2104 rtx cnd
= fis_get_condition (insn
);
2107 && GET_CODE (cnd
) == NE
2108 && REG_P (XEXP (cnd
, 0))
2109 && !reg_set_p (XEXP (cnd
, 0), insn
)
2110 /* The following two checks, which are also in
2111 move2add_note_store, are intended to reduce the
2112 number of calls to gen_rtx_SET to avoid memory
2113 allocation if possible. */
2114 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
2115 && REG_NREGS (XEXP (cnd
, 0)) == 1
2116 && CONST_INT_P (XEXP (cnd
, 1)))
2119 gen_rtx_SET (XEXP (cnd
, 0), XEXP (cnd
, 1));
2120 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
2124 /* If this is a CALL_INSN, all call used registers are stored with
2130 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
2132 if (call_used_regs
[i
])
2133 /* Reset the information about this register. */
2134 reg_mode
[i
] = VOIDmode
;
2137 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
2138 link
= XEXP (link
, 1))
2140 rtx setuse
= XEXP (link
, 0);
2141 rtx usage_rtx
= XEXP (setuse
, 0);
2142 if (GET_CODE (setuse
) == CLOBBER
2143 && REG_P (usage_rtx
))
2145 unsigned int end_regno
= END_REGNO (usage_rtx
);
2146 for (unsigned int r
= REGNO (usage_rtx
); r
< end_regno
; ++r
)
2147 /* Reset the information about this register. */
2148 reg_mode
[r
] = VOIDmode
;
2156 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2158 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2159 Called from reload_cse_move2add via note_stores. */
2162 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2164 rtx_insn
*insn
= (rtx_insn
*) data
;
2165 unsigned int regno
= 0;
2166 scalar_int_mode mode
;
2168 /* Some targets do argument pushes without adding REG_INC notes. */
2172 dst
= XEXP (dst
, 0);
2173 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2174 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2175 reg_mode
[REGNO (XEXP (dst
, 0))] = VOIDmode
;
2179 if (GET_CODE (dst
) == SUBREG
)
2180 regno
= subreg_regno (dst
);
2181 else if (REG_P (dst
))
2182 regno
= REGNO (dst
);
2186 if (!is_a
<scalar_int_mode
> (GET_MODE (dst
), &mode
))
2189 if (GET_CODE (set
) == SET
)
2191 rtx note
, sym
= NULL_RTX
;
2194 note
= find_reg_equal_equiv_note (insn
);
2195 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2197 sym
= XEXP (note
, 0);
2200 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2201 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2202 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2203 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2205 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2206 off
= XEXP (XEXP (XEXP (note
, 0), 0), 1);
2209 if (sym
!= NULL_RTX
)
2211 move2add_record_sym_value (dst
, sym
, off
);
2216 if (GET_CODE (set
) == SET
2217 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2218 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2220 rtx src
= SET_SRC (set
);
2222 unsigned HOST_WIDE_INT offset
;
2225 switch (GET_CODE (src
))
2228 if (REG_P (XEXP (src
, 0)))
2230 base_reg
= XEXP (src
, 0);
2232 if (CONST_INT_P (XEXP (src
, 1)))
2233 offset
= UINTVAL (XEXP (src
, 1));
2234 else if (REG_P (XEXP (src
, 1))
2235 && move2add_valid_value_p (REGNO (XEXP (src
, 1)), mode
))
2237 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0
2238 && reg_symbol_ref
[REGNO (XEXP (src
, 1))] == NULL_RTX
)
2239 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2240 /* Maybe the first register is known to be a
2242 else if (move2add_valid_value_p (REGNO (base_reg
), mode
)
2243 && reg_base_reg
[REGNO (base_reg
)] < 0
2244 && reg_symbol_ref
[REGNO (base_reg
)] == NULL_RTX
)
2246 offset
= reg_offset
[REGNO (base_reg
)];
2247 base_reg
= XEXP (src
, 1);
2266 /* Start tracking the register as a constant. */
2267 reg_base_reg
[regno
] = -1;
2268 reg_symbol_ref
[regno
] = NULL_RTX
;
2269 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2270 /* We assign the same luid to all registers set to constants. */
2271 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2272 move2add_record_mode (dst
);
2279 base_regno
= REGNO (base_reg
);
2280 /* If information about the base register is not valid, set it
2281 up as a new base register, pretending its value is known
2282 starting from the current insn. */
2283 if (!move2add_valid_value_p (base_regno
, mode
))
2285 reg_base_reg
[base_regno
] = base_regno
;
2286 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2287 reg_offset
[base_regno
] = 0;
2288 reg_set_luid
[base_regno
] = move2add_luid
;
2289 gcc_assert (GET_MODE (base_reg
) == mode
);
2290 move2add_record_mode (base_reg
);
2293 /* Copy base information from our base register. */
2294 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2295 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2296 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2298 /* Compute the sum of the offsets or constants. */
2300 = trunc_int_for_mode (offset
+ reg_offset
[base_regno
], mode
);
2302 move2add_record_mode (dst
);
2307 /* Invalidate the contents of the register. */
2308 move2add_record_mode (dst
);
2309 reg_mode
[regno
] = VOIDmode
;
2315 const pass_data pass_data_postreload_cse
=
2317 RTL_PASS
, /* type */
2318 "postreload", /* name */
2319 OPTGROUP_NONE
, /* optinfo_flags */
2320 TV_RELOAD_CSE_REGS
, /* tv_id */
2321 0, /* properties_required */
2322 0, /* properties_provided */
2323 0, /* properties_destroyed */
2324 0, /* todo_flags_start */
2325 TODO_df_finish
, /* todo_flags_finish */
2328 class pass_postreload_cse
: public rtl_opt_pass
2331 pass_postreload_cse (gcc::context
*ctxt
)
2332 : rtl_opt_pass (pass_data_postreload_cse
, ctxt
)
2335 /* opt_pass methods: */
2336 virtual bool gate (function
*) { return (optimize
> 0 && reload_completed
); }
2338 virtual unsigned int execute (function
*);
2340 }; // class pass_postreload_cse
2343 pass_postreload_cse::execute (function
*fun
)
2345 if (!dbg_cnt (postreload_cse
))
2348 /* Do a very simple CSE pass over just the hard registers. */
2349 reload_cse_regs (get_insns ());
2350 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2351 Remove any EH edges associated with them. */
2352 if (fun
->can_throw_non_call_exceptions
2353 && purge_all_dead_edges ())
2362 make_pass_postreload_cse (gcc::context
*ctxt
)
2364 return new pass_postreload_cse (ctxt
);