1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009,
4 2010, 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
43 #include "diagnostic-core.h"
48 #include "tree-pass.h"
52 static int reload_cse_noop_set_p (rtx
);
53 static void reload_cse_simplify (rtx
, rtx
);
54 static void reload_cse_regs_1 (rtx
);
55 static int reload_cse_simplify_set (rtx
, rtx
);
56 static int reload_cse_simplify_operands (rtx
, rtx
);
58 static void reload_combine (void);
59 static void reload_combine_note_use (rtx
*, rtx
, int, rtx
);
60 static void reload_combine_note_store (rtx
, const_rtx
, void *);
62 static bool reload_cse_move2add (rtx
);
63 static void move2add_note_store (rtx
, const_rtx
, void *);
65 /* Call cse / combine like post-reload optimization phases.
66 FIRST is the first instruction. */
69 reload_cse_regs (rtx first ATTRIBUTE_UNUSED
)
72 reload_cse_regs_1 (first
);
74 moves_converted
= reload_cse_move2add (first
);
75 if (flag_expensive_optimizations
)
79 reload_cse_regs_1 (first
);
83 /* See whether a single set SET is a noop. */
85 reload_cse_noop_set_p (rtx set
)
87 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
90 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
93 /* Try to simplify INSN. */
95 reload_cse_simplify (rtx insn
, rtx testreg
)
97 rtx body
= PATTERN (insn
);
99 if (GET_CODE (body
) == SET
)
103 /* Simplify even if we may think it is a no-op.
104 We may think a memory load of a value smaller than WORD_SIZE
105 is redundant because we haven't taken into account possible
106 implicit extension. reload_cse_simplify_set() will bring
107 this out, so it's safer to simplify before we delete. */
108 count
+= reload_cse_simplify_set (body
, insn
);
110 if (!count
&& reload_cse_noop_set_p (body
))
112 rtx value
= SET_DEST (body
);
114 && ! REG_FUNCTION_VALUE_P (value
))
116 if (check_for_inc_dec (insn
))
117 delete_insn_and_edges (insn
);
122 apply_change_group ();
124 reload_cse_simplify_operands (insn
, testreg
);
126 else if (GET_CODE (body
) == PARALLEL
)
130 rtx value
= NULL_RTX
;
132 /* Registers mentioned in the clobber list for an asm cannot be reused
133 within the body of the asm. Invalidate those registers now so that
134 we don't try to substitute values for them. */
135 if (asm_noperands (body
) >= 0)
137 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
139 rtx part
= XVECEXP (body
, 0, i
);
140 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
141 cselib_invalidate_rtx (XEXP (part
, 0));
145 /* If every action in a PARALLEL is a noop, we can delete
146 the entire PARALLEL. */
147 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
149 rtx part
= XVECEXP (body
, 0, i
);
150 if (GET_CODE (part
) == SET
)
152 if (! reload_cse_noop_set_p (part
))
154 if (REG_P (SET_DEST (part
))
155 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
159 value
= SET_DEST (part
);
162 else if (GET_CODE (part
) != CLOBBER
)
168 if (check_for_inc_dec (insn
))
169 delete_insn_and_edges (insn
);
170 /* We're done with this insn. */
174 /* It's not a no-op, but we can try to simplify it. */
175 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
176 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
177 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
180 apply_change_group ();
182 reload_cse_simplify_operands (insn
, testreg
);
186 /* Do a very simple CSE pass over the hard registers.
188 This function detects no-op moves where we happened to assign two
189 different pseudo-registers to the same hard register, and then
190 copied one to the other. Reload will generate a useless
191 instruction copying a register to itself.
193 This function also detects cases where we load a value from memory
194 into two different registers, and (if memory is more expensive than
195 registers) changes it to simply copy the first register into the
198 Another optimization is performed that scans the operands of each
199 instruction to see whether the value is already available in a
200 hard register. It then replaces the operand with the hard register
201 if possible, much like an optional reload would. */
204 reload_cse_regs_1 (rtx first
)
207 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
209 cselib_init (CSELIB_RECORD_MEMORY
);
210 init_alias_analysis ();
212 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
215 reload_cse_simplify (insn
, testreg
);
217 cselib_process_insn (insn
);
221 end_alias_analysis ();
225 /* Try to simplify a single SET instruction. SET is the set pattern.
226 INSN is the instruction it came from.
227 This function only handles one case: if we set a register to a value
228 which is not a register, we try to find that value in some other register
229 and change the set into a register copy. */
232 reload_cse_simplify_set (rtx set
, rtx insn
)
240 struct elt_loc_list
*l
;
241 #ifdef LOAD_EXTEND_OP
242 enum rtx_code extend_op
= UNKNOWN
;
244 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
246 dreg
= true_regnum (SET_DEST (set
));
251 if (side_effects_p (src
) || true_regnum (src
) >= 0)
254 dclass
= REGNO_REG_CLASS (dreg
);
256 #ifdef LOAD_EXTEND_OP
257 /* When replacing a memory with a register, we need to honor assumptions
258 that combine made wrt the contents of sign bits. We'll do this by
259 generating an extend instruction instead of a reg->reg copy. Thus
260 the destination must be a register that we can widen. */
262 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
263 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
264 && !REG_P (SET_DEST (set
)))
268 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0, VOIDmode
);
272 /* If memory loads are cheaper than register copies, don't change them. */
274 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
275 else if (REG_P (src
))
276 old_cost
= register_move_cost (GET_MODE (src
),
277 REGNO_REG_CLASS (REGNO (src
)), dclass
);
279 old_cost
= set_src_cost (src
, speed
);
281 for (l
= val
->locs
; l
; l
= l
->next
)
283 rtx this_rtx
= l
->loc
;
286 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
288 #ifdef LOAD_EXTEND_OP
289 if (extend_op
!= UNKNOWN
)
291 HOST_WIDE_INT this_val
;
293 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
294 constants, such as SYMBOL_REF, cannot be extended. */
295 if (!CONST_INT_P (this_rtx
))
298 this_val
= INTVAL (this_rtx
);
302 this_val
&= GET_MODE_MASK (GET_MODE (src
));
305 /* ??? In theory we're already extended. */
306 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
311 this_rtx
= GEN_INT (this_val
);
314 this_cost
= set_src_cost (this_rtx
, speed
);
316 else if (REG_P (this_rtx
))
318 #ifdef LOAD_EXTEND_OP
319 if (extend_op
!= UNKNOWN
)
321 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
322 this_cost
= set_src_cost (this_rtx
, speed
);
326 this_cost
= register_move_cost (GET_MODE (this_rtx
),
327 REGNO_REG_CLASS (REGNO (this_rtx
)),
333 /* If equal costs, prefer registers over anything else. That
334 tends to lead to smaller instructions on some machines. */
335 if (this_cost
< old_cost
336 || (this_cost
== old_cost
338 && !REG_P (SET_SRC (set
))))
340 #ifdef LOAD_EXTEND_OP
341 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
342 && extend_op
!= UNKNOWN
343 #ifdef CANNOT_CHANGE_MODE_CLASS
344 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
346 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
350 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
351 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
352 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
356 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
357 old_cost
= this_cost
, did_change
= 1;
364 /* Try to replace operands in INSN with equivalent values that are already
365 in registers. This can be viewed as optional reloading.
367 For each non-register operand in the insn, see if any hard regs are
368 known to be equivalent to that operand. Record the alternatives which
369 can accept these hard registers. Among all alternatives, select the
370 ones which are better or equal to the one currently matching, where
371 "better" is in terms of '?' and '!' constraints. Among the remaining
372 alternatives, select the one which replaces most operands with
376 reload_cse_simplify_operands (rtx insn
, rtx testreg
)
380 /* For each operand, all registers that are equivalent to it. */
381 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
383 const char *constraints
[MAX_RECOG_OPERANDS
];
385 /* Vector recording how bad an alternative is. */
386 int *alternative_reject
;
387 /* Vector recording how many registers can be introduced by choosing
389 int *alternative_nregs
;
390 /* Array of vectors recording, for each operand and each alternative,
391 which hard register to substitute, or -1 if the operand should be
393 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
394 /* Array of alternatives, sorted in order of decreasing desirability. */
395 int *alternative_order
;
399 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
402 /* Figure out which alternative currently matches. */
403 if (! constrain_operands (1))
404 fatal_insn_not_found (insn
);
406 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
407 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
408 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
409 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
410 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
412 /* For each operand, find out which regs are equivalent. */
413 for (i
= 0; i
< recog_data
.n_operands
; i
++)
416 struct elt_loc_list
*l
;
419 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
421 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
422 right, so avoid the problem here. Likewise if we have a constant
423 and the insn pattern doesn't tell us the mode we need. */
424 if (LABEL_P (recog_data
.operand
[i
])
425 || (CONSTANT_P (recog_data
.operand
[i
])
426 && recog_data
.operand_mode
[i
] == VOIDmode
))
429 op
= recog_data
.operand
[i
];
430 #ifdef LOAD_EXTEND_OP
432 && GET_MODE_BITSIZE (GET_MODE (op
)) < BITS_PER_WORD
433 && LOAD_EXTEND_OP (GET_MODE (op
)) != UNKNOWN
)
435 rtx set
= single_set (insn
);
437 /* We might have multiple sets, some of which do implicit
438 extension. Punt on this for now. */
441 /* If the destination is also a MEM or a STRICT_LOW_PART, no
443 Also, if there is an explicit extension, we don't have to
444 worry about an implicit one. */
445 else if (MEM_P (SET_DEST (set
))
446 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
447 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
448 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
449 ; /* Continue ordinary processing. */
450 #ifdef CANNOT_CHANGE_MODE_CLASS
451 /* If the register cannot change mode to word_mode, it follows that
452 it cannot have been used in word_mode. */
453 else if (REG_P (SET_DEST (set
))
454 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
456 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
457 ; /* Continue ordinary processing. */
459 /* If this is a straight load, make the extension explicit. */
460 else if (REG_P (SET_DEST (set
))
461 && recog_data
.n_operands
== 2
462 && SET_SRC (set
) == op
463 && SET_DEST (set
) == recog_data
.operand
[1-i
])
465 validate_change (insn
, recog_data
.operand_loc
[i
],
466 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op
)),
469 validate_change (insn
, recog_data
.operand_loc
[1-i
],
470 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
472 if (! apply_change_group ())
474 return reload_cse_simplify_operands (insn
, testreg
);
477 /* ??? There might be arithmetic operations with memory that are
478 safe to optimize, but is it worth the trouble? */
481 #endif /* LOAD_EXTEND_OP */
482 if (side_effects_p (op
))
484 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0, VOIDmode
);
488 for (l
= v
->locs
; l
; l
= l
->next
)
490 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
493 for (i
= 0; i
< recog_data
.n_operands
; i
++)
495 enum machine_mode mode
;
499 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
500 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
501 op_alt_regno
[i
][j
] = -1;
503 p
= constraints
[i
] = recog_data
.constraints
[i
];
504 mode
= recog_data
.operand_mode
[i
];
506 /* Add the reject values for each alternative given by the constraints
515 alternative_reject
[j
] += 3;
517 alternative_reject
[j
] += 300;
520 /* We won't change operands which are already registers. We
521 also don't want to modify output operands. */
522 regno
= true_regnum (recog_data
.operand
[i
]);
524 || constraints
[i
][0] == '='
525 || constraints
[i
][0] == '+')
528 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
530 enum reg_class rclass
= NO_REGS
;
532 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
535 SET_REGNO_RAW (testreg
, regno
);
536 PUT_MODE (testreg
, mode
);
538 /* We found a register equal to this operand. Now look for all
539 alternatives that can accept this register and have not been
540 assigned a register they can use yet. */
549 case '=': case '+': case '?':
550 case '#': case '&': case '!':
552 case '0': case '1': case '2': case '3': case '4':
553 case '5': case '6': case '7': case '8': case '9':
554 case '<': case '>': case 'V': case 'o':
555 case 'E': case 'F': case 'G': case 'H':
556 case 's': case 'i': case 'n':
557 case 'I': case 'J': case 'K': case 'L':
558 case 'M': case 'N': case 'O': case 'P':
559 case 'p': case 'X': case TARGET_MEM_CONSTRAINT
:
560 /* These don't say anything we care about. */
564 rclass
= reg_class_subunion
[(int) rclass
][(int) GENERAL_REGS
];
569 = (reg_class_subunion
571 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
575 /* See if REGNO fits this alternative, and set it up as the
576 replacement register if we don't have one for this
577 alternative yet and the operand being replaced is not
578 a cheap CONST_INT. */
579 if (op_alt_regno
[i
][j
] == -1
580 && recog_data
.alternative_enabled_p
[j
]
581 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
582 && (!CONST_INT_P (recog_data
.operand
[i
])
583 || (set_src_cost (recog_data
.operand
[i
],
584 optimize_bb_for_speed_p
585 (BLOCK_FOR_INSN (insn
)))
586 > set_src_cost (testreg
,
587 optimize_bb_for_speed_p
588 (BLOCK_FOR_INSN (insn
))))))
590 alternative_nregs
[j
]++;
591 op_alt_regno
[i
][j
] = regno
;
597 p
+= CONSTRAINT_LEN (c
, p
);
605 /* Record all alternatives which are better or equal to the currently
606 matching one in the alternative_order array. */
607 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
608 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
609 alternative_order
[j
++] = i
;
610 recog_data
.n_alternatives
= j
;
612 /* Sort it. Given a small number of alternatives, a dumb algorithm
613 won't hurt too much. */
614 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
617 int best_reject
= alternative_reject
[alternative_order
[i
]];
618 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
621 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
623 int this_reject
= alternative_reject
[alternative_order
[j
]];
624 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
626 if (this_reject
< best_reject
627 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
630 best_reject
= this_reject
;
631 best_nregs
= this_nregs
;
635 tmp
= alternative_order
[best
];
636 alternative_order
[best
] = alternative_order
[i
];
637 alternative_order
[i
] = tmp
;
640 /* Substitute the operands as determined by op_alt_regno for the best
642 j
= alternative_order
[0];
644 for (i
= 0; i
< recog_data
.n_operands
; i
++)
646 enum machine_mode mode
= recog_data
.operand_mode
[i
];
647 if (op_alt_regno
[i
][j
] == -1)
650 validate_change (insn
, recog_data
.operand_loc
[i
],
651 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
654 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
656 int op
= recog_data
.dup_num
[i
];
657 enum machine_mode mode
= recog_data
.operand_mode
[op
];
659 if (op_alt_regno
[op
][j
] == -1)
662 validate_change (insn
, recog_data
.dup_loc
[i
],
663 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
666 return apply_change_group ();
669 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
671 This code might also be useful when reload gave up on reg+reg addressing
672 because of clashes between the return register and INDEX_REG_CLASS. */
674 /* The maximum number of uses of a register we can keep track of to
675 replace them with reg+reg addressing. */
676 #define RELOAD_COMBINE_MAX_USES 16
678 /* Describes a recorded use of a register. */
681 /* The insn where a register has been used. */
683 /* Points to the memory reference enclosing the use, if any, NULL_RTX
686 /* Location of the register withing INSN. */
688 /* The reverse uid of the insn. */
692 /* If the register is used in some unknown fashion, USE_INDEX is negative.
693 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
694 indicates where it is first set or clobbered.
695 Otherwise, USE_INDEX is the index of the last encountered use of the
696 register (which is first among these we have seen since we scan backwards).
697 USE_RUID indicates the first encountered, i.e. last, of these uses.
698 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
699 with a constant offset; OFFSET contains this constant in that case.
700 STORE_RUID is always meaningful if we only want to use a value in a
701 register in a different place: it denotes the next insn in the insn
702 stream (i.e. the last encountered) that sets or clobbers the register.
703 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
706 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
712 bool all_offsets_match
;
713 } reg_state
[FIRST_PSEUDO_REGISTER
];
715 /* Reverse linear uid. This is increased in reload_combine while scanning
716 the instructions from last to first. It is used to set last_label_ruid
717 and the store_ruid / use_ruid fields in reg_state. */
718 static int reload_combine_ruid
;
720 /* The RUID of the last label we encountered in reload_combine. */
721 static int last_label_ruid
;
723 /* The RUID of the last jump we encountered in reload_combine. */
724 static int last_jump_ruid
;
726 /* The register numbers of the first and last index register. A value of
727 -1 in LAST_INDEX_REG indicates that we've previously computed these
728 values and found no suitable index registers. */
729 static int first_index_reg
= -1;
730 static int last_index_reg
;
732 #define LABEL_LIVE(LABEL) \
733 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
735 /* Subroutine of reload_combine_split_ruids, called to fix up a single
736 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
739 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
741 if (*pruid
> split_ruid
)
745 /* Called when we insert a new insn in a position we've already passed in
746 the scan. Examine all our state, increasing all ruids that are higher
747 than SPLIT_RUID by one in order to make room for a new insn. */
750 reload_combine_split_ruids (int split_ruid
)
754 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
755 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
756 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
758 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
760 int j
, idx
= reg_state
[i
].use_index
;
761 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
762 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
763 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
767 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
769 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
775 /* Called when we are about to rescan a previously encountered insn with
776 reload_combine_note_use after modifying some part of it. This clears all
777 information about uses in that particular insn. */
780 reload_combine_purge_insn_uses (rtx insn
)
784 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
786 int j
, k
, idx
= reg_state
[i
].use_index
;
789 j
= k
= RELOAD_COMBINE_MAX_USES
;
792 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
796 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
799 reg_state
[i
].use_index
= k
;
803 /* Called when we need to forget about all uses of REGNO after an insn
804 which is identified by RUID. */
807 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
809 int j
, k
, idx
= reg_state
[regno
].use_index
;
812 j
= k
= RELOAD_COMBINE_MAX_USES
;
815 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
819 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
822 reg_state
[regno
].use_index
= k
;
825 /* Find the use of REGNO with the ruid that is highest among those
826 lower than RUID_LIMIT, and return it if it is the only use of this
827 reg in the insn. Return NULL otherwise. */
829 static struct reg_use
*
830 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
832 int i
, best_ruid
= 0;
833 int use_idx
= reg_state
[regno
].use_index
;
834 struct reg_use
*retval
;
839 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
841 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
842 int this_ruid
= use
->ruid
;
843 if (this_ruid
>= ruid_limit
)
845 if (this_ruid
> best_ruid
)
847 best_ruid
= this_ruid
;
850 else if (this_ruid
== best_ruid
)
853 if (last_label_ruid
>= best_ruid
)
858 /* After we've moved an add insn, fix up any debug insns that occur
859 between the old location of the add and the new location. REG is
860 the destination register of the add insn; REPLACEMENT is the
861 SET_SRC of the add. FROM and TO specify the range in which we
862 should make this change on debug insns. */
865 fixup_debug_insns (rtx reg
, rtx replacement
, rtx from
, rtx to
)
868 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
872 if (!DEBUG_INSN_P (insn
))
875 t
= INSN_VAR_LOCATION_LOC (insn
);
876 t
= simplify_replace_rtx (t
, reg
, replacement
);
877 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
881 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
882 with SRC in the insn described by USE, taking costs into account. Return
883 true if we made the replacement. */
886 try_replace_in_use (struct reg_use
*use
, rtx reg
, rtx src
)
888 rtx use_insn
= use
->insn
;
889 rtx mem
= use
->containing_mem
;
890 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
894 addr_space_t as
= MEM_ADDR_SPACE (mem
);
895 rtx oldaddr
= XEXP (mem
, 0);
896 rtx newaddr
= NULL_RTX
;
897 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
900 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
901 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
903 XEXP (mem
, 0) = newaddr
;
904 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
905 XEXP (mem
, 0) = oldaddr
;
906 if (new_cost
<= old_cost
907 && validate_change (use_insn
,
908 &XEXP (mem
, 0), newaddr
, 0))
914 rtx new_set
= single_set (use_insn
);
916 && REG_P (SET_DEST (new_set
))
917 && GET_CODE (SET_SRC (new_set
)) == PLUS
918 && REG_P (XEXP (SET_SRC (new_set
), 0))
919 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
922 int old_cost
= set_src_cost (SET_SRC (new_set
), speed
);
924 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
925 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
927 if (set_src_cost (new_src
, speed
) <= old_cost
928 && validate_change (use_insn
, &SET_SRC (new_set
),
936 /* Called by reload_combine when scanning INSN. This function tries to detect
937 patterns where a constant is added to a register, and the result is used
939 Return true if no further processing is needed on INSN; false if it wasn't
940 recognized and should be handled normally. */
943 reload_combine_recognize_const_pattern (rtx insn
)
945 int from_ruid
= reload_combine_ruid
;
946 rtx set
, pat
, reg
, src
, addreg
;
950 rtx add_moved_after_insn
= NULL_RTX
;
951 int add_moved_after_ruid
= 0;
952 int clobbered_regno
= -1;
954 set
= single_set (insn
);
958 reg
= SET_DEST (set
);
961 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1
962 || GET_MODE (reg
) != Pmode
963 || reg
== stack_pointer_rtx
)
968 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
969 uses of REG1 inside an address, or inside another add insn. If
970 possible and profitable, merge the addition into subsequent
972 if (GET_CODE (src
) != PLUS
973 || !REG_P (XEXP (src
, 0))
974 || !CONSTANT_P (XEXP (src
, 1)))
977 addreg
= XEXP (src
, 0);
978 must_move_add
= rtx_equal_p (reg
, addreg
);
980 pat
= PATTERN (insn
);
981 if (must_move_add
&& set
!= pat
)
983 /* We have to be careful when moving the add; apart from the
984 single_set there may also be clobbers. Recognize one special
985 case, that of one clobber alongside the set (likely a clobber
986 of the CC register). */
987 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
988 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
989 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
990 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
992 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
997 use
= reload_combine_closest_single_use (regno
, from_ruid
);
1000 /* Start the search for the next use from here. */
1001 from_ruid
= use
->ruid
;
1003 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
1005 bool delete_add
= false;
1006 rtx use_insn
= use
->insn
;
1007 int use_ruid
= use
->ruid
;
1009 /* Avoid moving the add insn past a jump. */
1010 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
1013 /* If the add clobbers another hard reg in parallel, don't move
1014 it past a real set of this hard reg. */
1015 if (must_move_add
&& clobbered_regno
>= 0
1016 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
1020 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
1021 if (must_move_add
&& sets_cc0_p (PATTERN (use_insn
)))
1025 gcc_assert (reg_state
[regno
].store_ruid
<= use_ruid
);
1026 /* Avoid moving a use of ADDREG past a point where it is stored. */
1027 if (reg_state
[REGNO (addreg
)].store_ruid
> use_ruid
)
1030 /* We also must not move the addition past an insn that sets
1031 the same register, unless we can combine two add insns. */
1032 if (must_move_add
&& reg_state
[regno
].store_ruid
== use_ruid
)
1034 if (use
->containing_mem
== NULL_RTX
)
1040 if (try_replace_in_use (use
, reg
, src
))
1042 reload_combine_purge_insn_uses (use_insn
);
1043 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
1044 use_ruid
, NULL_RTX
);
1048 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1054 add_moved_after_insn
= use_insn
;
1055 add_moved_after_ruid
= use_ruid
;
1060 /* If we get here, we couldn't handle this use. */
1066 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1067 /* Process the add normally. */
1070 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1072 reorder_insns (insn
, insn
, add_moved_after_insn
);
1073 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1074 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1075 reload_combine_note_use (&PATTERN (insn
), insn
,
1076 add_moved_after_ruid
, NULL_RTX
);
1077 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1082 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1083 can handle and improve. Return true if no further processing is needed on
1084 INSN; false if it wasn't recognized and should be handled normally. */
1087 reload_combine_recognize_pattern (rtx insn
)
1092 set
= single_set (insn
);
1093 if (set
== NULL_RTX
)
1096 reg
= SET_DEST (set
);
1097 src
= SET_SRC (set
);
1099 || hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] != 1)
1102 regno
= REGNO (reg
);
1104 /* Look for (set (REGX) (CONST_INT))
1105 (set (REGX) (PLUS (REGX) (REGY)))
1107 ... (MEM (REGX)) ...
1109 (set (REGZ) (CONST_INT))
1111 ... (MEM (PLUS (REGZ) (REGY)))... .
1113 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1114 and that we know all uses of REGX before it dies.
1115 Also, explicitly check that REGX != REGY; our life information
1116 does not yet show whether REGY changes in this insn. */
1118 if (GET_CODE (src
) == PLUS
1119 && reg_state
[regno
].all_offsets_match
1120 && last_index_reg
!= -1
1121 && REG_P (XEXP (src
, 1))
1122 && rtx_equal_p (XEXP (src
, 0), reg
)
1123 && !rtx_equal_p (XEXP (src
, 1), reg
)
1124 && reg_state
[regno
].use_index
>= 0
1125 && reg_state
[regno
].use_index
< RELOAD_COMBINE_MAX_USES
1126 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1128 rtx base
= XEXP (src
, 1);
1129 rtx prev
= prev_nonnote_nondebug_insn (insn
);
1130 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1131 rtx index_reg
= NULL_RTX
;
1132 rtx reg_sum
= NULL_RTX
;
1135 /* Now we need to set INDEX_REG to an index register (denoted as
1136 REGZ in the illustration above) and REG_SUM to the expression
1137 register+register that we want to use to substitute uses of REG
1138 (typically in MEMs) with. First check REG and BASE for being
1139 index registers; we can use them even if they are not dead. */
1140 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1141 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1149 /* Otherwise, look for a free index register. Since we have
1150 checked above that neither REG nor BASE are index registers,
1151 if we find anything at all, it will be different from these
1153 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1155 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1156 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1157 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1158 && (call_used_regs
[i
] || df_regs_ever_live_p (i
))
1159 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1160 && !fixed_regs
[i
] && !global_regs
[i
]
1161 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1
1162 && targetm
.hard_regno_scratch_ok (i
))
1164 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1165 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1171 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1172 (REGY), i.e. BASE, is not clobbered before the last use we'll
1176 && CONST_INT_P (SET_SRC (prev_set
))
1177 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1178 && (reg_state
[REGNO (base
)].store_ruid
1179 <= reg_state
[regno
].use_ruid
))
1181 /* Change destination register and, if necessary, the constant
1182 value in PREV, the constant loading instruction. */
1183 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1184 if (reg_state
[regno
].offset
!= const0_rtx
)
1185 validate_change (prev
,
1186 &SET_SRC (prev_set
),
1187 GEN_INT (INTVAL (SET_SRC (prev_set
))
1188 + INTVAL (reg_state
[regno
].offset
)),
1191 /* Now for every use of REG that we have recorded, replace REG
1193 for (i
= reg_state
[regno
].use_index
;
1194 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1195 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1196 reg_state
[regno
].reg_use
[i
].usep
,
1197 /* Each change must have its own
1201 if (apply_change_group ())
1203 struct reg_use
*lowest_ruid
= NULL
;
1205 /* For every new use of REG_SUM, we have to record the use
1206 of BASE therein, i.e. operand 1. */
1207 for (i
= reg_state
[regno
].use_index
;
1208 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1210 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1211 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1212 use
->ruid
, use
->containing_mem
);
1213 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1217 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1219 /* Delete the reg-reg addition. */
1222 if (reg_state
[regno
].offset
!= const0_rtx
)
1223 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1225 remove_reg_equal_equiv_notes (prev
);
1227 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1236 reload_combine (void)
1241 int min_labelno
, n_labels
;
1242 HARD_REG_SET ever_live_at_start
, *label_live
;
1244 /* To avoid wasting too much time later searching for an index register,
1245 determine the minimum and maximum index register numbers. */
1246 if (INDEX_REG_CLASS
== NO_REGS
)
1247 last_index_reg
= -1;
1248 else if (first_index_reg
== -1 && last_index_reg
== 0)
1250 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1251 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1253 if (first_index_reg
== -1)
1254 first_index_reg
= r
;
1259 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1260 to -1 so we'll know to quit early the next time we get here. */
1261 if (first_index_reg
== -1)
1263 last_index_reg
= -1;
1268 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1269 information is a bit fuzzy immediately after reload, but it's
1270 still good enough to determine which registers are live at a jump
1272 min_labelno
= get_first_label_num ();
1273 n_labels
= max_label_num () - min_labelno
;
1274 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1275 CLEAR_HARD_REG_SET (ever_live_at_start
);
1277 FOR_EACH_BB_REVERSE (bb
)
1279 insn
= BB_HEAD (bb
);
1283 bitmap live_in
= df_get_live_in (bb
);
1285 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1286 compute_use_by_pseudos (&live
, live_in
);
1287 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
1288 IOR_HARD_REG_SET (ever_live_at_start
, live
);
1292 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1293 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1294 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1296 reg_state
[r
].store_ruid
= 0;
1297 reg_state
[r
].real_store_ruid
= 0;
1299 reg_state
[r
].use_index
= -1;
1301 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1304 for (insn
= get_last_insn (); insn
; insn
= prev
)
1306 bool control_flow_insn
;
1309 prev
= PREV_INSN (insn
);
1311 /* We cannot do our optimization across labels. Invalidating all the use
1312 information we have would be costly, so we just note where the label
1313 is and then later disable any optimization that would cross it. */
1315 last_label_ruid
= reload_combine_ruid
;
1316 else if (BARRIER_P (insn
))
1318 /* Crossing a barrier resets all the use information. */
1319 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1320 if (! fixed_regs
[r
])
1321 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1323 else if (INSN_P (insn
) && volatile_insn_p (PATTERN (insn
)))
1324 /* Optimizations across insns being marked as volatile must be
1325 prevented. All the usage information is invalidated
1327 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1329 && reg_state
[r
].use_index
!= RELOAD_COMBINE_MAX_USES
)
1330 reg_state
[r
].use_index
= -1;
1332 if (! NONDEBUG_INSN_P (insn
))
1335 reload_combine_ruid
++;
1337 control_flow_insn
= control_flow_insn_p (insn
);
1338 if (control_flow_insn
)
1339 last_jump_ruid
= reload_combine_ruid
;
1341 if (reload_combine_recognize_const_pattern (insn
)
1342 || reload_combine_recognize_pattern (insn
))
1345 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
1351 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1352 if (call_used_regs
[r
])
1354 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1355 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1358 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1359 link
= XEXP (link
, 1))
1361 rtx setuse
= XEXP (link
, 0);
1362 rtx usage_rtx
= XEXP (setuse
, 0);
1363 if ((GET_CODE (setuse
) == USE
|| GET_CODE (setuse
) == CLOBBER
)
1364 && REG_P (usage_rtx
))
1367 unsigned int start_reg
= REGNO (usage_rtx
);
1368 unsigned int num_regs
1369 = hard_regno_nregs
[start_reg
][GET_MODE (usage_rtx
)];
1370 unsigned int end_reg
= start_reg
+ num_regs
- 1;
1371 for (i
= start_reg
; i
<= end_reg
; i
++)
1372 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1374 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1375 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1378 reg_state
[i
].use_index
= -1;
1383 if (control_flow_insn
&& GET_CODE (PATTERN (insn
)) != RETURN
)
1385 /* Non-spill registers might be used at the call destination in
1386 some unknown fashion, so we have to mark the unknown use. */
1389 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1390 && JUMP_LABEL (insn
))
1391 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1393 live
= &ever_live_at_start
;
1395 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1396 if (TEST_HARD_REG_BIT (*live
, r
))
1397 reg_state
[r
].use_index
= -1;
1400 reload_combine_note_use (&PATTERN (insn
), insn
, reload_combine_ruid
,
1403 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1405 if (REG_NOTE_KIND (note
) == REG_INC
&& REG_P (XEXP (note
, 0)))
1407 int regno
= REGNO (XEXP (note
, 0));
1408 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1409 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1410 reg_state
[regno
].use_index
= -1;
1418 /* Check if DST is a register or a subreg of a register; if it is,
1419 update store_ruid, real_store_ruid and use_index in the reg_state
1420 structure accordingly. Called via note_stores from reload_combine. */
1423 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1427 enum machine_mode mode
= GET_MODE (dst
);
1429 if (GET_CODE (dst
) == SUBREG
)
1431 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1432 GET_MODE (SUBREG_REG (dst
)),
1435 dst
= SUBREG_REG (dst
);
1438 /* Some targets do argument pushes without adding REG_INC notes. */
1442 dst
= XEXP (dst
, 0);
1443 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1444 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
1445 || GET_CODE (dst
) == PRE_MODIFY
|| GET_CODE (dst
) == POST_MODIFY
)
1447 regno
= REGNO (XEXP (dst
, 0));
1448 mode
= GET_MODE (XEXP (dst
, 0));
1449 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1451 /* We could probably do better, but for now mark the register
1452 as used in an unknown fashion and set/clobbered at this
1454 reg_state
[i
].use_index
= -1;
1455 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1456 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1465 regno
+= REGNO (dst
);
1467 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1468 careful with registers / register parts that are not full words.
1469 Similarly for ZERO_EXTRACT. */
1470 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1471 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1473 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1475 reg_state
[i
].use_index
= -1;
1476 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1477 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1482 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1484 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1485 if (GET_CODE (set
) == SET
)
1486 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1487 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1492 /* XP points to a piece of rtl that has to be checked for any uses of
1494 *XP is the pattern of INSN, or a part of it.
1495 Called from reload_combine, and recursively by itself. */
1497 reload_combine_note_use (rtx
*xp
, rtx insn
, int ruid
, rtx containing_mem
)
1500 enum rtx_code code
= x
->code
;
1503 rtx offset
= const0_rtx
; /* For the REG case below. */
1508 if (REG_P (SET_DEST (x
)))
1510 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1516 /* If this is the USE of a return value, we can't change it. */
1517 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1519 /* Mark the return register as used in an unknown fashion. */
1520 rtx reg
= XEXP (x
, 0);
1521 int regno
= REGNO (reg
);
1522 int nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1524 while (--nregs
>= 0)
1525 reg_state
[regno
+ nregs
].use_index
= -1;
1531 if (REG_P (SET_DEST (x
)))
1533 /* No spurious CLOBBERs of pseudo registers may remain. */
1534 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1540 /* We are interested in (plus (reg) (const_int)) . */
1541 if (!REG_P (XEXP (x
, 0))
1542 || !CONST_INT_P (XEXP (x
, 1)))
1544 offset
= XEXP (x
, 1);
1549 int regno
= REGNO (x
);
1553 /* No spurious USEs of pseudo registers may remain. */
1554 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1556 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1558 /* We can't substitute into multi-hard-reg uses. */
1561 while (--nregs
>= 0)
1562 reg_state
[regno
+ nregs
].use_index
= -1;
1566 /* We may be called to update uses in previously seen insns.
1567 Don't add uses beyond the last store we saw. */
1568 if (ruid
< reg_state
[regno
].store_ruid
)
1571 /* If this register is already used in some unknown fashion, we
1573 If we decrement the index from zero to -1, we can't store more
1574 uses, so this register becomes used in an unknown fashion. */
1575 use_index
= --reg_state
[regno
].use_index
;
1579 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1581 /* This is the first use of this register we have seen since we
1582 marked it as dead. */
1583 reg_state
[regno
].offset
= offset
;
1584 reg_state
[regno
].all_offsets_match
= true;
1585 reg_state
[regno
].use_ruid
= ruid
;
1589 if (reg_state
[regno
].use_ruid
> ruid
)
1590 reg_state
[regno
].use_ruid
= ruid
;
1592 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1593 reg_state
[regno
].all_offsets_match
= false;
1596 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1597 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1598 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1599 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1611 /* Recursively process the components of X. */
1612 fmt
= GET_RTX_FORMAT (code
);
1613 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1616 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1617 else if (fmt
[i
] == 'E')
1619 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1620 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1626 /* See if we can reduce the cost of a constant by replacing a move
1627 with an add. We track situations in which a register is set to a
1628 constant or to a register plus a constant. */
1629 /* We cannot do our optimization across labels. Invalidating all the
1630 information about register contents we have would be costly, so we
1631 use move2add_last_label_luid to note where the label is and then
1632 later disable any optimization that would cross it.
1633 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1634 are only valid if reg_set_luid[n] is greater than
1635 move2add_last_label_luid. */
1636 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1638 /* If reg_base_reg[n] is negative, register n has been set to
1639 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1640 If reg_base_reg[n] is non-negative, register n has been set to the
1641 sum of reg_offset[n] and the value of register reg_base_reg[n]
1642 before reg_set_luid[n], calculated in mode reg_mode[n] . */
1643 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1644 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1645 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1646 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1648 /* move2add_luid is linearly increased while scanning the instructions
1649 from first to last. It is used to set reg_set_luid in
1650 reload_cse_move2add and move2add_note_store. */
1651 static int move2add_luid
;
1653 /* move2add_last_label_luid is set whenever a label is found. Labels
1654 invalidate all previously collected reg_offset data. */
1655 static int move2add_last_label_luid
;
1657 /* ??? We don't know how zero / sign extension is handled, hence we
1658 can't go from a narrower to a wider mode. */
1659 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1660 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1661 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1662 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1664 /* This function is called with INSN that sets REG to (SYM + OFF),
1665 while REG is known to already have value (SYM + offset).
1666 This function tries to change INSN into an add instruction
1667 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1668 It also updates the information about REG's known value.
1669 Return true if we made a change. */
1672 move2add_use_add2_insn (rtx reg
, rtx sym
, rtx off
, rtx insn
)
1674 rtx pat
= PATTERN (insn
);
1675 rtx src
= SET_SRC (pat
);
1676 int regno
= REGNO (reg
);
1677 rtx new_src
= gen_int_mode (INTVAL (off
) - reg_offset
[regno
],
1679 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1680 bool changed
= false;
1682 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1683 use (set (reg) (reg)) instead.
1684 We don't delete this insn, nor do we convert it into a
1685 note, to avoid losing register notes or the return
1686 value flag. jump2 already knows how to get rid of
1688 if (new_src
== const0_rtx
)
1690 /* If the constants are different, this is a
1691 truncation, that, if turned into (set (reg)
1692 (reg)), would be discarded. Maybe we should
1693 try a truncMN pattern? */
1694 if (INTVAL (off
) == reg_offset
[regno
])
1695 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1699 struct full_rtx_costs oldcst
, newcst
;
1700 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1702 get_full_set_rtx_cost (pat
, &oldcst
);
1703 SET_SRC (pat
) = tem
;
1704 get_full_set_rtx_cost (pat
, &newcst
);
1705 SET_SRC (pat
) = src
;
1707 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1708 && have_add2_insn (reg
, new_src
))
1709 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1710 else if (sym
== NULL_RTX
&& GET_MODE (reg
) != BImode
)
1712 enum machine_mode narrow_mode
;
1713 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1714 narrow_mode
!= VOIDmode
1715 && narrow_mode
!= GET_MODE (reg
);
1716 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1718 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1719 && ((reg_offset
[regno
] & ~GET_MODE_MASK (narrow_mode
))
1720 == (INTVAL (off
) & ~GET_MODE_MASK (narrow_mode
))))
1722 rtx narrow_reg
= gen_rtx_REG (narrow_mode
,
1724 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1727 = gen_rtx_SET (VOIDmode
,
1728 gen_rtx_STRICT_LOW_PART (VOIDmode
,
1731 changed
= validate_change (insn
, &PATTERN (insn
),
1739 reg_set_luid
[regno
] = move2add_luid
;
1740 reg_base_reg
[regno
] = -1;
1741 reg_mode
[regno
] = GET_MODE (reg
);
1742 reg_symbol_ref
[regno
] = sym
;
1743 reg_offset
[regno
] = INTVAL (off
);
1748 /* This function is called with INSN that sets REG to (SYM + OFF),
1749 but REG doesn't have known value (SYM + offset). This function
1750 tries to find another register which is known to already have
1751 value (SYM + offset) and change INSN into an add instruction
1752 (set (REG) (plus (the found register) (OFF - offset))) if such
1753 a register is found. It also updates the information about
1755 Return true iff we made a change. */
1758 move2add_use_add3_insn (rtx reg
, rtx sym
, rtx off
, rtx insn
)
1760 rtx pat
= PATTERN (insn
);
1761 rtx src
= SET_SRC (pat
);
1762 int regno
= REGNO (reg
);
1764 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1766 bool changed
= false;
1767 struct full_rtx_costs oldcst
, newcst
, mincst
;
1770 init_costs_to_max (&mincst
);
1771 get_full_set_rtx_cost (pat
, &oldcst
);
1773 plus_expr
= gen_rtx_PLUS (GET_MODE (reg
), reg
, const0_rtx
);
1774 SET_SRC (pat
) = plus_expr
;
1776 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1777 if (reg_set_luid
[i
] > move2add_last_label_luid
1778 && reg_mode
[i
] == GET_MODE (reg
)
1779 && reg_base_reg
[i
] < 0
1780 && reg_symbol_ref
[i
] != NULL_RTX
1781 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1783 rtx new_src
= gen_int_mode (INTVAL (off
) - reg_offset
[i
],
1785 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1786 use (set (reg) (reg)) instead.
1787 We don't delete this insn, nor do we convert it into a
1788 note, to avoid losing register notes or the return
1789 value flag. jump2 already knows how to get rid of
1791 if (new_src
== const0_rtx
)
1793 init_costs_to_zero (&mincst
);
1799 XEXP (plus_expr
, 1) = new_src
;
1800 get_full_set_rtx_cost (pat
, &newcst
);
1802 if (costs_lt_p (&newcst
, &mincst
, speed
))
1809 SET_SRC (pat
) = src
;
1811 if (costs_lt_p (&mincst
, &oldcst
, speed
))
1815 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1818 rtx new_src
= gen_int_mode (INTVAL (off
) - reg_offset
[min_regno
],
1820 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1822 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1825 reg_set_luid
[regno
] = move2add_luid
;
1826 reg_base_reg
[regno
] = -1;
1827 reg_mode
[regno
] = GET_MODE (reg
);
1828 reg_symbol_ref
[regno
] = sym
;
1829 reg_offset
[regno
] = INTVAL (off
);
1833 /* Convert move insns with constant inputs to additions if they are cheaper.
1834 Return true if any changes were made. */
1836 reload_cse_move2add (rtx first
)
1840 bool changed
= false;
1842 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1844 reg_set_luid
[i
] = 0;
1846 reg_base_reg
[i
] = 0;
1847 reg_symbol_ref
[i
] = NULL_RTX
;
1848 reg_mode
[i
] = VOIDmode
;
1851 move2add_last_label_luid
= 0;
1853 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1859 move2add_last_label_luid
= move2add_luid
;
1860 /* We're going to increment move2add_luid twice after a
1861 label, so that we can use move2add_last_label_luid + 1 as
1862 the luid for constants. */
1866 if (! INSN_P (insn
))
1868 pat
= PATTERN (insn
);
1869 /* For simplicity, we only perform this optimization on
1870 straightforward SETs. */
1871 if (GET_CODE (pat
) == SET
1872 && REG_P (SET_DEST (pat
)))
1874 rtx reg
= SET_DEST (pat
);
1875 int regno
= REGNO (reg
);
1876 rtx src
= SET_SRC (pat
);
1878 /* Check if we have valid information on the contents of this
1879 register in the mode of REG. */
1880 if (reg_set_luid
[regno
] > move2add_last_label_luid
1881 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
])
1882 && dbg_cnt (cse2_move2add
))
1884 /* Try to transform (set (REGX) (CONST_INT A))
1886 (set (REGX) (CONST_INT B))
1888 (set (REGX) (CONST_INT A))
1890 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1892 (set (REGX) (CONST_INT A))
1894 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1897 if (CONST_INT_P (src
)
1898 && reg_base_reg
[regno
] < 0
1899 && reg_symbol_ref
[regno
] == NULL_RTX
)
1901 changed
|= move2add_use_add2_insn (reg
, NULL_RTX
, src
, insn
);
1905 /* Try to transform (set (REGX) (REGY))
1906 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1909 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1912 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1914 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1915 else if (REG_P (src
)
1916 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1917 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1918 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
),
1919 reg_mode
[REGNO (src
)]))
1921 rtx next
= next_nonnote_nondebug_insn (insn
);
1924 set
= single_set (next
);
1926 && SET_DEST (set
) == reg
1927 && GET_CODE (SET_SRC (set
)) == PLUS
1928 && XEXP (SET_SRC (set
), 0) == reg
1929 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
1931 rtx src3
= XEXP (SET_SRC (set
), 1);
1932 HOST_WIDE_INT added_offset
= INTVAL (src3
);
1933 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
1934 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
1936 gen_int_mode (added_offset
1940 bool success
= false;
1941 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1943 if (new_src
== const0_rtx
)
1944 /* See above why we create (set (reg) (reg)) here. */
1946 = validate_change (next
, &SET_SRC (set
), reg
, 0);
1949 rtx old_src
= SET_SRC (set
);
1950 struct full_rtx_costs oldcst
, newcst
;
1951 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1953 get_full_set_rtx_cost (set
, &oldcst
);
1954 SET_SRC (set
) = tem
;
1955 get_full_set_src_cost (tem
, &newcst
);
1956 SET_SRC (set
) = old_src
;
1957 costs_add_n_insns (&oldcst
, 1);
1959 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1960 && have_add2_insn (reg
, new_src
))
1962 rtx newpat
= gen_rtx_SET (VOIDmode
, reg
, tem
);
1964 = validate_change (next
, &PATTERN (next
),
1972 reg_mode
[regno
] = GET_MODE (reg
);
1974 trunc_int_for_mode (added_offset
+ base_offset
,
1982 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1984 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
1986 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
1988 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
1989 if ((GET_CODE (src
) == SYMBOL_REF
1990 || (GET_CODE (src
) == CONST
1991 && GET_CODE (XEXP (src
, 0)) == PLUS
1992 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
1993 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
1994 && dbg_cnt (cse2_move2add
))
1998 if (GET_CODE (src
) == SYMBOL_REF
)
2005 sym
= XEXP (XEXP (src
, 0), 0);
2006 off
= XEXP (XEXP (src
, 0), 1);
2009 /* If the reg already contains the value which is sum of
2010 sym and some constant value, we can use an add2 insn. */
2011 if (reg_set_luid
[regno
] > move2add_last_label_luid
2012 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
])
2013 && reg_base_reg
[regno
] < 0
2014 && reg_symbol_ref
[regno
] != NULL_RTX
2015 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
2016 changed
|= move2add_use_add2_insn (reg
, sym
, off
, insn
);
2018 /* Otherwise, we have to find a register whose value is sum
2019 of sym and some constant value. */
2021 changed
|= move2add_use_add3_insn (reg
, sym
, off
, insn
);
2027 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2029 if (REG_NOTE_KIND (note
) == REG_INC
2030 && REG_P (XEXP (note
, 0)))
2032 /* Reset the information about this register. */
2033 int regno
= REGNO (XEXP (note
, 0));
2034 if (regno
< FIRST_PSEUDO_REGISTER
)
2035 reg_set_luid
[regno
] = 0;
2038 note_stores (PATTERN (insn
), move2add_note_store
, insn
);
2040 /* If INSN is a conditional branch, we try to extract an
2041 implicit set out of it. */
2042 if (any_condjump_p (insn
))
2044 rtx cnd
= fis_get_condition (insn
);
2047 && GET_CODE (cnd
) == NE
2048 && REG_P (XEXP (cnd
, 0))
2049 && !reg_set_p (XEXP (cnd
, 0), insn
)
2050 /* The following two checks, which are also in
2051 move2add_note_store, are intended to reduce the
2052 number of calls to gen_rtx_SET to avoid memory
2053 allocation if possible. */
2054 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
2055 && hard_regno_nregs
[REGNO (XEXP (cnd
, 0))][GET_MODE (XEXP (cnd
, 0))] == 1
2056 && CONST_INT_P (XEXP (cnd
, 1)))
2059 gen_rtx_SET (VOIDmode
, XEXP (cnd
, 0), XEXP (cnd
, 1));
2060 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
2064 /* If this is a CALL_INSN, all call used registers are stored with
2068 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
2070 if (call_used_regs
[i
])
2071 /* Reset the information about this register. */
2072 reg_set_luid
[i
] = 0;
2079 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2081 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2082 Called from reload_cse_move2add via note_stores. */
2085 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2087 rtx insn
= (rtx
) data
;
2088 unsigned int regno
= 0;
2089 unsigned int nregs
= 0;
2091 enum machine_mode mode
= GET_MODE (dst
);
2093 if (GET_CODE (dst
) == SUBREG
)
2095 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
2096 GET_MODE (SUBREG_REG (dst
)),
2099 nregs
= subreg_nregs (dst
);
2100 dst
= SUBREG_REG (dst
);
2103 /* Some targets do argument pushes without adding REG_INC notes. */
2107 dst
= XEXP (dst
, 0);
2108 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2109 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2110 reg_set_luid
[REGNO (XEXP (dst
, 0))] = 0;
2116 regno
+= REGNO (dst
);
2118 nregs
= hard_regno_nregs
[regno
][mode
];
2120 if (SCALAR_INT_MODE_P (GET_MODE (dst
))
2121 && nregs
== 1 && GET_CODE (set
) == SET
)
2123 rtx note
, sym
= NULL_RTX
;
2126 note
= find_reg_equal_equiv_note (insn
);
2127 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2129 sym
= XEXP (note
, 0);
2132 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2133 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2134 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2135 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2137 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2138 off
= INTVAL (XEXP (XEXP (XEXP (note
, 0), 0), 1));
2141 if (sym
!= NULL_RTX
)
2143 reg_base_reg
[regno
] = -1;
2144 reg_symbol_ref
[regno
] = sym
;
2145 reg_offset
[regno
] = off
;
2146 reg_mode
[regno
] = mode
;
2147 reg_set_luid
[regno
] = move2add_luid
;
2152 if (SCALAR_INT_MODE_P (GET_MODE (dst
))
2153 && nregs
== 1 && GET_CODE (set
) == SET
2154 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2155 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2157 rtx src
= SET_SRC (set
);
2159 HOST_WIDE_INT offset
;
2161 /* This may be different from mode, if SET_DEST (set) is a
2163 enum machine_mode dst_mode
= GET_MODE (dst
);
2165 switch (GET_CODE (src
))
2168 if (REG_P (XEXP (src
, 0)))
2170 base_reg
= XEXP (src
, 0);
2172 if (CONST_INT_P (XEXP (src
, 1)))
2173 offset
= INTVAL (XEXP (src
, 1));
2174 else if (REG_P (XEXP (src
, 1))
2175 && (reg_set_luid
[REGNO (XEXP (src
, 1))]
2176 > move2add_last_label_luid
)
2177 && (MODES_OK_FOR_MOVE2ADD
2178 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))])))
2180 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0
2181 && reg_symbol_ref
[REGNO (XEXP (src
, 1))] == NULL_RTX
)
2182 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2183 /* Maybe the first register is known to be a
2185 else if (reg_set_luid
[REGNO (base_reg
)]
2186 > move2add_last_label_luid
2187 && (MODES_OK_FOR_MOVE2ADD
2188 (dst_mode
, reg_mode
[REGNO (base_reg
)]))
2189 && reg_base_reg
[REGNO (base_reg
)] < 0
2190 && reg_symbol_ref
[REGNO (base_reg
)] == NULL_RTX
)
2192 offset
= reg_offset
[REGNO (base_reg
)];
2193 base_reg
= XEXP (src
, 1);
2212 /* Start tracking the register as a constant. */
2213 reg_base_reg
[regno
] = -1;
2214 reg_symbol_ref
[regno
] = NULL_RTX
;
2215 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2216 /* We assign the same luid to all registers set to constants. */
2217 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2218 reg_mode
[regno
] = mode
;
2223 /* Invalidate the contents of the register. */
2224 reg_set_luid
[regno
] = 0;
2228 base_regno
= REGNO (base_reg
);
2229 /* If information about the base register is not valid, set it
2230 up as a new base register, pretending its value is known
2231 starting from the current insn. */
2232 if (reg_set_luid
[base_regno
] <= move2add_last_label_luid
)
2234 reg_base_reg
[base_regno
] = base_regno
;
2235 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2236 reg_offset
[base_regno
] = 0;
2237 reg_set_luid
[base_regno
] = move2add_luid
;
2238 reg_mode
[base_regno
] = mode
;
2240 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode
,
2241 reg_mode
[base_regno
]))
2244 reg_mode
[regno
] = mode
;
2246 /* Copy base information from our base register. */
2247 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2248 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2249 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2251 /* Compute the sum of the offsets or constants. */
2252 reg_offset
[regno
] = trunc_int_for_mode (offset
2253 + reg_offset
[base_regno
],
2258 unsigned int endregno
= regno
+ nregs
;
2260 for (i
= regno
; i
< endregno
; i
++)
2261 /* Reset the information about this register. */
2262 reg_set_luid
[i
] = 0;
2267 gate_handle_postreload (void)
2269 return (optimize
> 0 && reload_completed
);
2274 rest_of_handle_postreload (void)
2276 if (!dbg_cnt (postreload_cse
))
2279 /* Do a very simple CSE pass over just the hard registers. */
2280 reload_cse_regs (get_insns ());
2281 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2282 Remove any EH edges associated with them. */
2283 if (cfun
->can_throw_non_call_exceptions
)
2284 purge_all_dead_edges ();
2289 struct rtl_opt_pass pass_postreload_cse
=
2293 "postreload", /* name */
2294 gate_handle_postreload
, /* gate */
2295 rest_of_handle_postreload
, /* execute */
2298 0, /* static_pass_number */
2299 TV_RELOAD_CSE_REGS
, /* tv_id */
2300 0, /* properties_required */
2301 0, /* properties_provided */
2302 0, /* properties_destroyed */
2303 0, /* todo_flags_start */
2304 TODO_df_finish
| TODO_verify_rtl_sharing
|
2305 0 /* todo_flags_finish */