1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "hard-reg-set.h"
36 #include "basic-block.h"
40 #ifndef STACK_PUSH_CODE
41 #ifdef STACK_GROWS_DOWNWARD
42 #define STACK_PUSH_CODE PRE_DEC
44 #define STACK_PUSH_CODE PRE_INC
48 #ifndef STACK_POP_CODE
49 #ifdef STACK_GROWS_DOWNWARD
50 #define STACK_POP_CODE POST_INC
52 #define STACK_POP_CODE POST_DEC
56 static void validate_replace_rtx_1
PARAMS ((rtx
*, rtx
, rtx
, rtx
));
57 static rtx
*find_single_use_1
PARAMS ((rtx
, rtx
*));
58 static rtx
*find_constant_term_loc
PARAMS ((rtx
*));
59 static void validate_replace_src_1
PARAMS ((rtx
*, void *));
60 static rtx split_insn
PARAMS ((rtx
));
62 /* Nonzero means allow operands to be volatile.
63 This should be 0 if you are generating rtl, such as if you are calling
64 the functions in optabs.c and expmed.c (most of the time).
65 This should be 1 if all valid insns need to be recognized,
66 such as in regclass.c and final.c and reload.c.
68 init_recog and init_recog_no_volatile are responsible for setting this. */
72 struct recog_data recog_data
;
74 /* Contains a vector of operand_alternative structures for every operand.
75 Set up by preprocess_constraints. */
76 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
78 /* On return from `constrain_operands', indicate which alternative
81 int which_alternative
;
83 /* Nonzero after end of reload pass.
84 Set to 1 or 0 by toplev.c.
85 Controls the significance of (SUBREG (MEM)). */
89 /* Initialize data used by the function `recog'.
90 This must be called once in the compilation of a function
91 before any insn recognition may be done in the function. */
94 init_recog_no_volatile ()
105 /* Try recognizing the instruction INSN,
106 and return the code number that results.
107 Remember the code so that repeated calls do not
108 need to spend the time for actual rerecognition.
110 This function is the normal interface to instruction recognition.
111 The automatically-generated function `recog' is normally called
112 through this one. (The only exception is in combine.c.) */
115 recog_memoized_1 (insn
)
118 if (INSN_CODE (insn
) < 0)
119 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, 0);
120 return INSN_CODE (insn
);
123 /* Check that X is an insn-body for an `asm' with operands
124 and that the operands mentioned in it are legitimate. */
127 check_asm_operands (x
)
132 const char **constraints
;
135 /* Post-reload, be more strict with things. */
136 if (reload_completed
)
138 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
139 extract_insn (make_insn_raw (x
));
140 constrain_operands (1);
141 return which_alternative
>= 0;
144 noperands
= asm_noperands (x
);
150 operands
= (rtx
*) alloca (noperands
* sizeof (rtx
));
151 constraints
= (const char **) alloca (noperands
* sizeof (char *));
153 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
);
155 for (i
= 0; i
< noperands
; i
++)
157 const char *c
= constraints
[i
];
160 if (ISDIGIT ((unsigned char)c
[0]) && c
[1] == '\0')
161 c
= constraints
[c
[0] - '0'];
163 if (! asm_operand_ok (operands
[i
], c
))
170 /* Static data for the next two routines. */
172 typedef struct change_t
180 static change_t
*changes
;
181 static int changes_allocated
;
183 static int num_changes
= 0;
185 /* Validate a proposed change to OBJECT. LOC is the location in the rtl for
186 at which NEW will be placed. If OBJECT is zero, no validation is done,
187 the change is simply made.
189 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
190 will be called with the address and mode as parameters. If OBJECT is
191 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
194 IN_GROUP is non-zero if this is part of a group of changes that must be
195 performed as a group. In that case, the changes will be stored. The
196 function `apply_change_group' will validate and apply the changes.
198 If IN_GROUP is zero, this is a single change. Try to recognize the insn
199 or validate the memory reference with the change applied. If the result
200 is not valid for the machine, suppress the change and return zero.
201 Otherwise, perform the change and return 1. */
204 validate_change (object
, loc
, new, in_group
)
212 if (old
== new || rtx_equal_p (old
, new))
215 if (in_group
== 0 && num_changes
!= 0)
220 /* Save the information describing this change. */
221 if (num_changes
>= changes_allocated
)
223 if (changes_allocated
== 0)
224 /* This value allows for repeated substitutions inside complex
225 indexed addresses, or changes in up to 5 insns. */
226 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
228 changes_allocated
*= 2;
231 (change_t
*) xrealloc (changes
,
232 sizeof (change_t
) * changes_allocated
);
235 changes
[num_changes
].object
= object
;
236 changes
[num_changes
].loc
= loc
;
237 changes
[num_changes
].old
= old
;
239 if (object
&& GET_CODE (object
) != MEM
)
241 /* Set INSN_CODE to force rerecognition of insn. Save old code in
243 changes
[num_changes
].old_code
= INSN_CODE (object
);
244 INSN_CODE (object
) = -1;
249 /* If we are making a group of changes, return 1. Otherwise, validate the
250 change group we made. */
255 return apply_change_group ();
258 /* This subroutine of apply_change_group verifies whether the changes to INSN
259 were valid; i.e. whether INSN can still be recognized. */
262 insn_invalid_p (insn
)
265 rtx pat
= PATTERN (insn
);
266 int num_clobbers
= 0;
267 /* If we are before reload and the pattern is a SET, see if we can add
269 int icode
= recog (pat
, insn
,
270 (GET_CODE (pat
) == SET
271 && ! reload_completed
&& ! reload_in_progress
)
272 ? &num_clobbers
: 0);
273 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
276 /* If this is an asm and the operand aren't legal, then fail. Likewise if
277 this is not an asm and the insn wasn't recognized. */
278 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
279 || (!is_asm
&& icode
< 0))
282 /* If we have to add CLOBBERs, fail if we have to add ones that reference
283 hard registers since our callers can't know if they are live or not.
284 Otherwise, add them. */
285 if (num_clobbers
> 0)
289 if (added_clobbers_hard_reg_p (icode
))
292 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
293 XVECEXP (newpat
, 0, 0) = pat
;
294 add_clobbers (newpat
, icode
);
295 PATTERN (insn
) = pat
= newpat
;
298 /* After reload, verify that all constraints are satisfied. */
299 if (reload_completed
)
303 if (! constrain_operands (1))
307 INSN_CODE (insn
) = icode
;
311 /* Apply a group of changes previously issued with `validate_change'.
312 Return 1 if all changes are valid, zero otherwise. */
315 apply_change_group ()
318 rtx last_validated
= NULL_RTX
;
320 /* The changes have been applied and all INSN_CODEs have been reset to force
323 The changes are valid if we aren't given an object, or if we are
324 given a MEM and it still is a valid address, or if this is in insn
325 and it is recognized. In the latter case, if reload has completed,
326 we also require that the operands meet the constraints for
329 for (i
= 0; i
< num_changes
; i
++)
331 rtx object
= changes
[i
].object
;
333 /* if there is no object to test or if it is the same as the one we
334 already tested, ignore it. */
335 if (object
== 0 || object
== last_validated
)
338 if (GET_CODE (object
) == MEM
)
340 if (! memory_address_p (GET_MODE (object
), XEXP (object
, 0)))
343 else if (insn_invalid_p (object
))
345 rtx pat
= PATTERN (object
);
347 /* Perhaps we couldn't recognize the insn because there were
348 extra CLOBBERs at the end. If so, try to re-recognize
349 without the last CLOBBER (later iterations will cause each of
350 them to be eliminated, in turn). But don't do this if we
351 have an ASM_OPERAND. */
352 if (GET_CODE (pat
) == PARALLEL
353 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
354 && asm_noperands (PATTERN (object
)) < 0)
358 if (XVECLEN (pat
, 0) == 2)
359 newpat
= XVECEXP (pat
, 0, 0);
365 = gen_rtx_PARALLEL (VOIDmode
,
366 rtvec_alloc (XVECLEN (pat
, 0) - 1));
367 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
368 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
371 /* Add a new change to this group to replace the pattern
372 with this new pattern. Then consider this change
373 as having succeeded. The change we added will
374 cause the entire call to fail if things remain invalid.
376 Note that this can lose if a later change than the one
377 we are processing specified &XVECEXP (PATTERN (object), 0, X)
378 but this shouldn't occur. */
380 validate_change (object
, &PATTERN (object
), newpat
, 1);
383 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
384 /* If this insn is a CLOBBER or USE, it is always valid, but is
390 last_validated
= object
;
393 if (i
== num_changes
)
405 /* Return the number of changes so far in the current group. */
408 num_validated_changes ()
413 /* Retract the changes numbered NUM and up. */
421 /* Back out all the changes. Do this in the opposite order in which
423 for (i
= num_changes
- 1; i
>= num
; i
--)
425 *changes
[i
].loc
= changes
[i
].old
;
426 if (changes
[i
].object
&& GET_CODE (changes
[i
].object
) != MEM
)
427 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
432 /* Replace every occurrence of FROM in X with TO. Mark each change with
433 validate_change passing OBJECT. */
436 validate_replace_rtx_1 (loc
, from
, to
, object
)
438 rtx from
, to
, object
;
441 register const char *fmt
;
442 register rtx x
= *loc
;
444 enum machine_mode op0_mode
= VOIDmode
;
445 int prev_changes
= num_changes
;
452 fmt
= GET_RTX_FORMAT (code
);
454 op0_mode
= GET_MODE (XEXP (x
, 0));
456 /* X matches FROM if it is the same rtx or they are both referring to the
457 same register in the same mode. Avoid calling rtx_equal_p unless the
458 operands look similar. */
461 || (GET_CODE (x
) == REG
&& GET_CODE (from
) == REG
462 && GET_MODE (x
) == GET_MODE (from
)
463 && REGNO (x
) == REGNO (from
))
464 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
465 && rtx_equal_p (x
, from
)))
467 validate_change (object
, loc
, to
, 1);
471 /* Call ourseves recursivly to perform the replacements. */
473 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
476 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
);
477 else if (fmt
[i
] == 'E')
478 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
479 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
);
482 /* In case we didn't substituted, there is nothing to do. */
483 if (num_changes
== prev_changes
)
486 /* Allow substituted expression to have different mode. This is used by
487 regmove to change mode of pseudo register. */
488 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
489 op0_mode
= GET_MODE (XEXP (x
, 0));
491 /* Do changes needed to keep rtx consistent. Don't do any other
492 simplifications, as it is not our job. */
494 if ((GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
495 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
497 validate_change (object
, loc
,
498 gen_rtx_fmt_ee (GET_RTX_CLASS (code
) == 'c' ? code
499 : swap_condition (code
),
500 GET_MODE (x
), XEXP (x
, 1),
509 /* If we have a PLUS whose second operand is now a CONST_INT, use
510 plus_constant to try to simplify it.
511 ??? We may want later to remove this, once simplification is
512 separated from this function. */
513 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
514 validate_change (object
, loc
,
515 plus_constant (XEXP (x
, 0), INTVAL (XEXP (x
, 1))), 1);
518 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
519 || GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
)
520 validate_change (object
, loc
,
522 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
523 simplify_gen_unary (NEG
,
524 op0_mode
, XEXP (x
, 1),
529 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
531 new = simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
533 /* If any of the above failed, substitute in something that
534 we know won't be recognized. */
536 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
537 validate_change (object
, loc
, new, 1);
541 /* All subregs possible to simplify should be simplified. */
542 new = simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
545 /* Subregs of VOIDmode operands are incorect. */
546 if (!new && GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
547 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
549 validate_change (object
, loc
, new, 1);
553 /* If we are replacing a register with memory, try to change the memory
554 to be the mode required for memory in extract operations (this isn't
555 likely to be an insertion operation; if it was, nothing bad will
556 happen, we might just fail in some cases). */
558 if (GET_CODE (XEXP (x
, 0)) == MEM
559 && GET_CODE (XEXP (x
, 1)) == CONST_INT
560 && GET_CODE (XEXP (x
, 2)) == CONST_INT
561 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0))
562 && !MEM_VOLATILE_P (XEXP (x
, 0)))
564 enum machine_mode wanted_mode
= VOIDmode
;
565 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
566 int pos
= INTVAL (XEXP (x
, 2));
569 if (code
== ZERO_EXTRACT
)
571 wanted_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
572 if (wanted_mode
== VOIDmode
)
573 wanted_mode
= word_mode
;
577 if (code
== SIGN_EXTRACT
)
579 wanted_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
580 if (wanted_mode
== VOIDmode
)
581 wanted_mode
= word_mode
;
585 /* If we have a narrower mode, we can do something. */
586 if (wanted_mode
!= VOIDmode
587 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
589 int offset
= pos
/ BITS_PER_UNIT
;
592 /* If the bytes and bits are counted differently, we
593 must adjust the offset. */
594 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
596 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
599 pos
%= GET_MODE_BITSIZE (wanted_mode
);
601 newmem
= gen_rtx_MEM (wanted_mode
,
602 plus_constant (XEXP (XEXP (x
, 0), 0),
604 MEM_COPY_ATTRIBUTES (newmem
, XEXP (x
, 0));
606 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
607 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
618 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
619 with TO. After all changes have been made, validate by seeing
620 if INSN is still valid. */
623 validate_replace_rtx_subexp (from
, to
, insn
, loc
)
624 rtx from
, to
, insn
, *loc
;
626 validate_replace_rtx_1 (loc
, from
, to
, insn
);
627 return apply_change_group ();
630 /* Try replacing every occurrence of FROM in INSN with TO. After all
631 changes have been made, validate by seeing if INSN is still valid. */
634 validate_replace_rtx (from
, to
, insn
)
637 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
638 return apply_change_group ();
641 /* Try replacing every occurrence of FROM in INSN with TO. */
644 validate_replace_rtx_group (from
, to
, insn
)
647 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
650 /* Function called by note_uses to replace used subexpressions. */
651 struct validate_replace_src_data
653 rtx from
; /* Old RTX */
654 rtx to
; /* New RTX */
655 rtx insn
; /* Insn in which substitution is occurring. */
659 validate_replace_src_1 (x
, data
)
663 struct validate_replace_src_data
*d
664 = (struct validate_replace_src_data
*) data
;
666 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
);
669 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
670 SET_DESTs. After all changes have been made, validate by seeing if
671 INSN is still valid. */
674 validate_replace_src (from
, to
, insn
)
677 struct validate_replace_src_data d
;
682 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
683 return apply_change_group ();
687 /* Return 1 if the insn using CC0 set by INSN does not contain
688 any ordered tests applied to the condition codes.
689 EQ and NE tests do not count. */
692 next_insn_tests_no_inequality (insn
)
695 register rtx next
= next_cc0_user (insn
);
697 /* If there is no next insn, we have to take the conservative choice. */
701 return ((GET_CODE (next
) == JUMP_INSN
702 || GET_CODE (next
) == INSN
703 || GET_CODE (next
) == CALL_INSN
)
704 && ! inequality_comparisons_p (PATTERN (next
)));
707 #if 0 /* This is useless since the insn that sets the cc's
708 must be followed immediately by the use of them. */
709 /* Return 1 if the CC value set up by INSN is not used. */
712 next_insns_test_no_inequality (insn
)
715 register rtx next
= NEXT_INSN (insn
);
717 for (; next
!= 0; next
= NEXT_INSN (next
))
719 if (GET_CODE (next
) == CODE_LABEL
720 || GET_CODE (next
) == BARRIER
)
722 if (GET_CODE (next
) == NOTE
)
724 if (inequality_comparisons_p (PATTERN (next
)))
726 if (sets_cc0_p (PATTERN (next
)) == 1)
728 if (! reg_mentioned_p (cc0_rtx
, PATTERN (next
)))
736 /* This is used by find_single_use to locate an rtx that contains exactly one
737 use of DEST, which is typically either a REG or CC0. It returns a
738 pointer to the innermost rtx expression containing DEST. Appearances of
739 DEST that are being used to totally replace it are not counted. */
742 find_single_use_1 (dest
, loc
)
747 enum rtx_code code
= GET_CODE (x
);
764 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
765 of a REG that occupies all of the REG, the insn uses DEST if
766 it is mentioned in the destination or the source. Otherwise, we
767 need just check the source. */
768 if (GET_CODE (SET_DEST (x
)) != CC0
769 && GET_CODE (SET_DEST (x
)) != PC
770 && GET_CODE (SET_DEST (x
)) != REG
771 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
772 && GET_CODE (SUBREG_REG (SET_DEST (x
))) == REG
773 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
774 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
775 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
776 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
779 return find_single_use_1 (dest
, &SET_SRC (x
));
783 return find_single_use_1 (dest
, &XEXP (x
, 0));
789 /* If it wasn't one of the common cases above, check each expression and
790 vector of this code. Look for a unique usage of DEST. */
792 fmt
= GET_RTX_FORMAT (code
);
793 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
797 if (dest
== XEXP (x
, i
)
798 || (GET_CODE (dest
) == REG
&& GET_CODE (XEXP (x
, i
)) == REG
799 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
802 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
805 result
= this_result
;
806 else if (this_result
)
807 /* Duplicate usage. */
810 else if (fmt
[i
] == 'E')
814 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
816 if (XVECEXP (x
, i
, j
) == dest
817 || (GET_CODE (dest
) == REG
818 && GET_CODE (XVECEXP (x
, i
, j
)) == REG
819 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
822 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
825 result
= this_result
;
826 else if (this_result
)
835 /* See if DEST, produced in INSN, is used only a single time in the
836 sequel. If so, return a pointer to the innermost rtx expression in which
839 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
841 This routine will return usually zero either before flow is called (because
842 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
843 note can't be trusted).
845 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
846 care about REG_DEAD notes or LOG_LINKS.
848 Otherwise, we find the single use by finding an insn that has a
849 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
850 only referenced once in that insn, we know that it must be the first
851 and last insn referencing DEST. */
854 find_single_use (dest
, insn
, ploc
)
866 next
= NEXT_INSN (insn
);
868 || (GET_CODE (next
) != INSN
&& GET_CODE (next
) != JUMP_INSN
))
871 result
= find_single_use_1 (dest
, &PATTERN (next
));
878 if (reload_completed
|| reload_in_progress
|| GET_CODE (dest
) != REG
)
881 for (next
= next_nonnote_insn (insn
);
882 next
!= 0 && GET_CODE (next
) != CODE_LABEL
;
883 next
= next_nonnote_insn (next
))
884 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
886 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
887 if (XEXP (link
, 0) == insn
)
892 result
= find_single_use_1 (dest
, &PATTERN (next
));
902 /* Return 1 if OP is a valid general operand for machine mode MODE.
903 This is either a register reference, a memory reference,
904 or a constant. In the case of a memory reference, the address
905 is checked for general validity for the target machine.
907 Register and memory references must have mode MODE in order to be valid,
908 but some constants have no machine mode and are valid for any mode.
910 If MODE is VOIDmode, OP is checked for validity for whatever mode
913 The main use of this function is as a predicate in match_operand
914 expressions in the machine description.
916 For an explanation of this function's behavior for registers of
917 class NO_REGS, see the comment for `register_operand'. */
920 general_operand (op
, mode
)
922 enum machine_mode mode
;
924 register enum rtx_code code
= GET_CODE (op
);
926 if (mode
== VOIDmode
)
927 mode
= GET_MODE (op
);
929 /* Don't accept CONST_INT or anything similar
930 if the caller wants something floating. */
931 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
932 && GET_MODE_CLASS (mode
) != MODE_INT
933 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
936 if (GET_CODE (op
) == CONST_INT
937 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
941 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
943 #ifdef LEGITIMATE_PIC_OPERAND_P
944 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
946 && LEGITIMATE_CONSTANT_P (op
));
948 /* Except for certain constants with VOIDmode, already checked for,
949 OP's mode must match MODE if MODE specifies a mode. */
951 if (GET_MODE (op
) != mode
)
956 #ifdef INSN_SCHEDULING
957 /* On machines that have insn scheduling, we want all memory
958 reference to be explicit, so outlaw paradoxical SUBREGs. */
959 if (GET_CODE (SUBREG_REG (op
)) == MEM
960 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
963 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
964 may result in incorrect reference. We should simplify all valid
965 subregs of MEM anyway. But allow this after reload because we
966 might be called from cleanup_subreg_operands.
968 ??? This is a kludge. */
969 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
970 && GET_CODE (SUBREG_REG (op
)) == MEM
)
973 op
= SUBREG_REG (op
);
974 code
= GET_CODE (op
);
978 /* A register whose class is NO_REGS is not a general operand. */
979 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
980 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
984 register rtx y
= XEXP (op
, 0);
986 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
989 if (GET_CODE (y
) == ADDRESSOF
)
992 /* Use the mem's mode, since it will be reloaded thus. */
993 mode
= GET_MODE (op
);
994 GO_IF_LEGITIMATE_ADDRESS (mode
, y
, win
);
997 /* Pretend this is an operand for now; we'll run force_operand
998 on its replacement in fixup_var_refs_1. */
999 if (code
== ADDRESSOF
)
1008 /* Return 1 if OP is a valid memory address for a memory reference
1011 The main use of this function is as a predicate in match_operand
1012 expressions in the machine description. */
1015 address_operand (op
, mode
)
1017 enum machine_mode mode
;
1019 return memory_address_p (mode
, op
);
1022 /* Return 1 if OP is a register reference of mode MODE.
1023 If MODE is VOIDmode, accept a register in any mode.
1025 The main use of this function is as a predicate in match_operand
1026 expressions in the machine description.
1028 As a special exception, registers whose class is NO_REGS are
1029 not accepted by `register_operand'. The reason for this change
1030 is to allow the representation of special architecture artifacts
1031 (such as a condition code register) without extending the rtl
1032 definitions. Since registers of class NO_REGS cannot be used
1033 as registers in any case where register classes are examined,
1034 it is most consistent to keep this function from accepting them. */
1037 register_operand (op
, mode
)
1039 enum machine_mode mode
;
1041 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1044 if (GET_CODE (op
) == SUBREG
)
1046 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1047 because it is guaranteed to be reloaded into one.
1048 Just make sure the MEM is valid in itself.
1049 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1050 but currently it does result from (SUBREG (REG)...) where the
1051 reg went on the stack.) */
1052 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1053 return general_operand (op
, mode
);
1055 #ifdef CLASS_CANNOT_CHANGE_MODE
1056 if (GET_CODE (SUBREG_REG (op
)) == REG
1057 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
1058 && (TEST_HARD_REG_BIT
1059 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
1060 REGNO (SUBREG_REG (op
))))
1061 && CLASS_CANNOT_CHANGE_MODE_P (mode
, GET_MODE (SUBREG_REG (op
)))
1062 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_INT
1063 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_FLOAT
)
1067 op
= SUBREG_REG (op
);
1070 /* If we have an ADDRESSOF, consider it valid since it will be
1071 converted into something that will not be a MEM. */
1072 if (GET_CODE (op
) == ADDRESSOF
)
1075 /* We don't consider registers whose class is NO_REGS
1076 to be a register operand. */
1077 return (GET_CODE (op
) == REG
1078 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1079 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1082 /* Return 1 for a register in Pmode; ignore the tested mode. */
1085 pmode_register_operand (op
, mode
)
1087 enum machine_mode mode ATTRIBUTE_UNUSED
;
1089 return register_operand (op
, Pmode
);
1092 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1093 or a hard register. */
1096 scratch_operand (op
, mode
)
1098 enum machine_mode mode
;
1100 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1103 return (GET_CODE (op
) == SCRATCH
1104 || (GET_CODE (op
) == REG
1105 && REGNO (op
) < FIRST_PSEUDO_REGISTER
));
1108 /* Return 1 if OP is a valid immediate operand for mode MODE.
1110 The main use of this function is as a predicate in match_operand
1111 expressions in the machine description. */
1114 immediate_operand (op
, mode
)
1116 enum machine_mode mode
;
1118 /* Don't accept CONST_INT or anything similar
1119 if the caller wants something floating. */
1120 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1121 && GET_MODE_CLASS (mode
) != MODE_INT
1122 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1125 if (GET_CODE (op
) == CONST_INT
1126 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1129 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1130 result in 0/1. It seems a safe assumption that this is
1131 in range for everyone. */
1132 if (GET_CODE (op
) == CONSTANT_P_RTX
)
1135 return (CONSTANT_P (op
)
1136 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1137 || GET_MODE (op
) == VOIDmode
)
1138 #ifdef LEGITIMATE_PIC_OPERAND_P
1139 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1141 && LEGITIMATE_CONSTANT_P (op
));
1144 /* Returns 1 if OP is an operand that is a CONST_INT. */
1147 const_int_operand (op
, mode
)
1149 enum machine_mode mode
;
1151 if (GET_CODE (op
) != CONST_INT
)
1154 if (mode
!= VOIDmode
1155 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1161 /* Returns 1 if OP is an operand that is a constant integer or constant
1162 floating-point number. */
1165 const_double_operand (op
, mode
)
1167 enum machine_mode mode
;
1169 /* Don't accept CONST_INT or anything similar
1170 if the caller wants something floating. */
1171 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1172 && GET_MODE_CLASS (mode
) != MODE_INT
1173 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1176 return ((GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
)
1177 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1178 || GET_MODE (op
) == VOIDmode
));
1181 /* Return 1 if OP is a general operand that is not an immediate operand. */
1184 nonimmediate_operand (op
, mode
)
1186 enum machine_mode mode
;
1188 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1191 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1194 nonmemory_operand (op
, mode
)
1196 enum machine_mode mode
;
1198 if (CONSTANT_P (op
))
1200 /* Don't accept CONST_INT or anything similar
1201 if the caller wants something floating. */
1202 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1203 && GET_MODE_CLASS (mode
) != MODE_INT
1204 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1207 if (GET_CODE (op
) == CONST_INT
1208 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1211 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1212 || mode
== VOIDmode
)
1213 #ifdef LEGITIMATE_PIC_OPERAND_P
1214 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1216 && LEGITIMATE_CONSTANT_P (op
));
1219 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1222 if (GET_CODE (op
) == SUBREG
)
1224 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1225 because it is guaranteed to be reloaded into one.
1226 Just make sure the MEM is valid in itself.
1227 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1228 but currently it does result from (SUBREG (REG)...) where the
1229 reg went on the stack.) */
1230 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1231 return general_operand (op
, mode
);
1232 op
= SUBREG_REG (op
);
1235 /* We don't consider registers whose class is NO_REGS
1236 to be a register operand. */
1237 return (GET_CODE (op
) == REG
1238 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1239 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1242 /* Return 1 if OP is a valid operand that stands for pushing a
1243 value of mode MODE onto the stack.
1245 The main use of this function is as a predicate in match_operand
1246 expressions in the machine description. */
1249 push_operand (op
, mode
)
1251 enum machine_mode mode
;
1253 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1255 #ifdef PUSH_ROUNDING
1256 rounded_size
= PUSH_ROUNDING (rounded_size
);
1259 if (GET_CODE (op
) != MEM
)
1262 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1267 if (rounded_size
== GET_MODE_SIZE (mode
))
1269 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1274 if (GET_CODE (op
) != PRE_MODIFY
1275 || GET_CODE (XEXP (op
, 1)) != PLUS
1276 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1277 || GET_CODE (XEXP (XEXP (op
, 1), 1)) != CONST_INT
1278 #ifdef STACK_GROWS_DOWNWARD
1279 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1281 || INTVAL (XEXP (XEXP (op
, 1), 1)) != rounded_size
1287 return XEXP (op
, 0) == stack_pointer_rtx
;
1290 /* Return 1 if OP is a valid operand that stands for popping a
1291 value of mode MODE off the stack.
1293 The main use of this function is as a predicate in match_operand
1294 expressions in the machine description. */
1297 pop_operand (op
, mode
)
1299 enum machine_mode mode
;
1301 if (GET_CODE (op
) != MEM
)
1304 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1309 if (GET_CODE (op
) != STACK_POP_CODE
)
1312 return XEXP (op
, 0) == stack_pointer_rtx
;
1315 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1318 memory_address_p (mode
, addr
)
1319 enum machine_mode mode ATTRIBUTE_UNUSED
;
1322 if (GET_CODE (addr
) == ADDRESSOF
)
1325 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1332 /* Return 1 if OP is a valid memory reference with mode MODE,
1333 including a valid address.
1335 The main use of this function is as a predicate in match_operand
1336 expressions in the machine description. */
1339 memory_operand (op
, mode
)
1341 enum machine_mode mode
;
1345 if (! reload_completed
)
1346 /* Note that no SUBREG is a memory operand before end of reload pass,
1347 because (SUBREG (MEM...)) forces reloading into a register. */
1348 return GET_CODE (op
) == MEM
&& general_operand (op
, mode
);
1350 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1354 if (GET_CODE (inner
) == SUBREG
)
1355 inner
= SUBREG_REG (inner
);
1357 return (GET_CODE (inner
) == MEM
&& general_operand (op
, mode
));
1360 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1361 that is, a memory reference whose address is a general_operand. */
1364 indirect_operand (op
, mode
)
1366 enum machine_mode mode
;
1368 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1369 if (! reload_completed
1370 && GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1372 register int offset
= SUBREG_BYTE (op
);
1373 rtx inner
= SUBREG_REG (op
);
1375 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1378 /* The only way that we can have a general_operand as the resulting
1379 address is if OFFSET is zero and the address already is an operand
1380 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1383 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1384 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1385 && GET_CODE (XEXP (XEXP (inner
, 0), 1)) == CONST_INT
1386 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1387 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1390 return (GET_CODE (op
) == MEM
1391 && memory_operand (op
, mode
)
1392 && general_operand (XEXP (op
, 0), Pmode
));
1395 /* Return 1 if this is a comparison operator. This allows the use of
1396 MATCH_OPERATOR to recognize all the branch insns. */
1399 comparison_operator (op
, mode
)
1401 enum machine_mode mode
;
1403 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1404 && GET_RTX_CLASS (GET_CODE (op
)) == '<');
1407 /* If BODY is an insn body that uses ASM_OPERANDS,
1408 return the number of operands (both input and output) in the insn.
1409 Otherwise return -1. */
1412 asm_noperands (body
)
1415 switch (GET_CODE (body
))
1418 /* No output operands: return number of input operands. */
1419 return ASM_OPERANDS_INPUT_LENGTH (body
);
1421 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1422 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1423 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body
)) + 1;
1427 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
1428 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1430 /* Multiple output operands, or 1 output plus some clobbers:
1431 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1435 /* Count backwards through CLOBBERs to determine number of SETs. */
1436 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1438 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1440 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1444 /* N_SETS is now number of output operands. */
1447 /* Verify that all the SETs we have
1448 came from a single original asm_operands insn
1449 (so that invalid combinations are blocked). */
1450 for (i
= 0; i
< n_sets
; i
++)
1452 rtx elt
= XVECEXP (body
, 0, i
);
1453 if (GET_CODE (elt
) != SET
)
1455 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1457 /* If these ASM_OPERANDS rtx's came from different original insns
1458 then they aren't allowed together. */
1459 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1460 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body
, 0, 0))))
1463 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body
, 0, 0)))
1466 else if (GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1468 /* 0 outputs, but some clobbers:
1469 body is [(asm_operands ...) (clobber (reg ...))...]. */
1472 /* Make sure all the other parallel things really are clobbers. */
1473 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1474 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1477 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body
, 0, 0));
1486 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1487 copy its operands (both input and output) into the vector OPERANDS,
1488 the locations of the operands within the insn into the vector OPERAND_LOCS,
1489 and the constraints for the operands into CONSTRAINTS.
1490 Write the modes of the operands into MODES.
1491 Return the assembler-template.
1493 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1494 we don't store that info. */
1497 decode_asm_operands (body
, operands
, operand_locs
, constraints
, modes
)
1501 const char **constraints
;
1502 enum machine_mode
*modes
;
1506 const char *template = 0;
1508 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1510 rtx asmop
= SET_SRC (body
);
1511 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1513 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
) + 1;
1515 for (i
= 1; i
< noperands
; i
++)
1518 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
- 1);
1520 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
- 1);
1522 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
- 1);
1524 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
- 1);
1527 /* The output is in the SET.
1528 Its constraint is in the ASM_OPERANDS itself. */
1530 operands
[0] = SET_DEST (body
);
1532 operand_locs
[0] = &SET_DEST (body
);
1534 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1536 modes
[0] = GET_MODE (SET_DEST (body
));
1537 template = ASM_OPERANDS_TEMPLATE (asmop
);
1539 else if (GET_CODE (body
) == ASM_OPERANDS
)
1542 /* No output operands: BODY is (asm_operands ....). */
1544 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1546 /* The input operands are found in the 1st element vector. */
1547 /* Constraints for inputs are in the 2nd element vector. */
1548 for (i
= 0; i
< noperands
; i
++)
1551 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1553 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1555 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1557 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1559 template = ASM_OPERANDS_TEMPLATE (asmop
);
1561 else if (GET_CODE (body
) == PARALLEL
1562 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1564 rtx asmop
= SET_SRC (XVECEXP (body
, 0, 0));
1565 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1566 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1567 int nout
= 0; /* Does not include CLOBBERs. */
1569 /* At least one output, plus some CLOBBERs. */
1571 /* The outputs are in the SETs.
1572 Their constraints are in the ASM_OPERANDS itself. */
1573 for (i
= 0; i
< nparallel
; i
++)
1575 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1576 break; /* Past last SET */
1579 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1581 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1583 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1585 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1589 for (i
= 0; i
< nin
; i
++)
1592 operand_locs
[i
+ nout
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1594 operands
[i
+ nout
] = ASM_OPERANDS_INPUT (asmop
, i
);
1596 constraints
[i
+ nout
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1598 modes
[i
+ nout
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1601 template = ASM_OPERANDS_TEMPLATE (asmop
);
1603 else if (GET_CODE (body
) == PARALLEL
1604 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1606 /* No outputs, but some CLOBBERs. */
1608 rtx asmop
= XVECEXP (body
, 0, 0);
1609 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1611 for (i
= 0; i
< nin
; i
++)
1614 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1616 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1618 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1620 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1623 template = ASM_OPERANDS_TEMPLATE (asmop
);
1629 /* Check if an asm_operand matches it's constraints.
1630 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1633 asm_operand_ok (op
, constraint
)
1635 const char *constraint
;
1639 /* Use constrain_operands after reload. */
1640 if (reload_completed
)
1645 char c
= *constraint
++;
1659 case '0': case '1': case '2': case '3': case '4':
1660 case '5': case '6': case '7': case '8': case '9':
1661 /* For best results, our caller should have given us the
1662 proper matching constraint, but we can't actually fail
1663 the check if they didn't. Indicate that results are
1669 if (address_operand (op
, VOIDmode
))
1674 case 'V': /* non-offsettable */
1675 if (memory_operand (op
, VOIDmode
))
1679 case 'o': /* offsettable */
1680 if (offsettable_nonstrict_memref_p (op
))
1685 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1686 excepting those that expand_call created. Further, on some
1687 machines which do not have generalized auto inc/dec, an inc/dec
1688 is not a memory_operand.
1690 Match any memory and hope things are resolved after reload. */
1692 if (GET_CODE (op
) == MEM
1694 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1695 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1700 if (GET_CODE (op
) == MEM
1702 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1703 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1708 #ifndef REAL_ARITHMETIC
1709 /* Match any floating double constant, but only if
1710 we can examine the bits of it reliably. */
1711 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1712 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1713 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1719 if (GET_CODE (op
) == CONST_DOUBLE
)
1724 if (GET_CODE (op
) == CONST_DOUBLE
1725 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, 'G'))
1729 if (GET_CODE (op
) == CONST_DOUBLE
1730 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, 'H'))
1735 if (GET_CODE (op
) == CONST_INT
1736 || (GET_CODE (op
) == CONST_DOUBLE
1737 && GET_MODE (op
) == VOIDmode
))
1743 #ifdef LEGITIMATE_PIC_OPERAND_P
1744 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1751 if (GET_CODE (op
) == CONST_INT
1752 || (GET_CODE (op
) == CONST_DOUBLE
1753 && GET_MODE (op
) == VOIDmode
))
1758 if (GET_CODE (op
) == CONST_INT
1759 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I'))
1763 if (GET_CODE (op
) == CONST_INT
1764 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'J'))
1768 if (GET_CODE (op
) == CONST_INT
1769 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K'))
1773 if (GET_CODE (op
) == CONST_INT
1774 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'))
1778 if (GET_CODE (op
) == CONST_INT
1779 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'M'))
1783 if (GET_CODE (op
) == CONST_INT
1784 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'N'))
1788 if (GET_CODE (op
) == CONST_INT
1789 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'))
1793 if (GET_CODE (op
) == CONST_INT
1794 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'P'))
1802 if (general_operand (op
, VOIDmode
))
1807 /* For all other letters, we first check for a register class,
1808 otherwise it is an EXTRA_CONSTRAINT. */
1809 if (REG_CLASS_FROM_LETTER (c
) != NO_REGS
)
1812 if (GET_MODE (op
) == BLKmode
)
1814 if (register_operand (op
, VOIDmode
))
1817 #ifdef EXTRA_CONSTRAINT
1818 if (EXTRA_CONSTRAINT (op
, c
))
1828 /* Given an rtx *P, if it is a sum containing an integer constant term,
1829 return the location (type rtx *) of the pointer to that constant term.
1830 Otherwise, return a null pointer. */
1833 find_constant_term_loc (p
)
1837 register enum rtx_code code
= GET_CODE (*p
);
1839 /* If *P IS such a constant term, P is its location. */
1841 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1845 /* Otherwise, if not a sum, it has no constant term. */
1847 if (GET_CODE (*p
) != PLUS
)
1850 /* If one of the summands is constant, return its location. */
1852 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1853 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1856 /* Otherwise, check each summand for containing a constant term. */
1858 if (XEXP (*p
, 0) != 0)
1860 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1865 if (XEXP (*p
, 1) != 0)
1867 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1875 /* Return 1 if OP is a memory reference
1876 whose address contains no side effects
1877 and remains valid after the addition
1878 of a positive integer less than the
1879 size of the object being referenced.
1881 We assume that the original address is valid and do not check it.
1883 This uses strict_memory_address_p as a subroutine, so
1884 don't use it before reload. */
1887 offsettable_memref_p (op
)
1890 return ((GET_CODE (op
) == MEM
)
1891 && offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)));
1894 /* Similar, but don't require a strictly valid mem ref:
1895 consider pseudo-regs valid as index or base regs. */
1898 offsettable_nonstrict_memref_p (op
)
1901 return ((GET_CODE (op
) == MEM
)
1902 && offsettable_address_p (0, GET_MODE (op
), XEXP (op
, 0)));
1905 /* Return 1 if Y is a memory address which contains no side effects
1906 and would remain valid after the addition of a positive integer
1907 less than the size of that mode.
1909 We assume that the original address is valid and do not check it.
1910 We do check that it is valid for narrower modes.
1912 If STRICTP is nonzero, we require a strictly valid address,
1913 for the sake of use in reload.c. */
1916 offsettable_address_p (strictp
, mode
, y
)
1918 enum machine_mode mode
;
1921 register enum rtx_code ycode
= GET_CODE (y
);
1925 int (*addressp
) PARAMS ((enum machine_mode
, rtx
)) =
1926 (strictp
? strict_memory_address_p
: memory_address_p
);
1927 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1929 if (CONSTANT_ADDRESS_P (y
))
1932 /* Adjusting an offsettable address involves changing to a narrower mode.
1933 Make sure that's OK. */
1935 if (mode_dependent_address_p (y
))
1938 /* ??? How much offset does an offsettable BLKmode reference need?
1939 Clearly that depends on the situation in which it's being used.
1940 However, the current situation in which we test 0xffffffff is
1941 less than ideal. Caveat user. */
1943 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1945 /* If the expression contains a constant term,
1946 see if it remains valid when max possible offset is added. */
1948 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1953 *y2
= plus_constant (*y2
, mode_sz
- 1);
1954 /* Use QImode because an odd displacement may be automatically invalid
1955 for any wider mode. But it should be valid for a single byte. */
1956 good
= (*addressp
) (QImode
, y
);
1958 /* In any case, restore old contents of memory. */
1963 if (GET_RTX_CLASS (ycode
) == 'a')
1966 /* The offset added here is chosen as the maximum offset that
1967 any instruction could need to add when operating on something
1968 of the specified mode. We assume that if Y and Y+c are
1969 valid addresses then so is Y+d for all 0<d<c. */
1971 z
= plus_constant (y
, mode_sz
- 1);
1973 /* Use QImode because an odd displacement may be automatically invalid
1974 for any wider mode. But it should be valid for a single byte. */
1975 return (*addressp
) (QImode
, z
);
1978 /* Return 1 if ADDR is an address-expression whose effect depends
1979 on the mode of the memory reference it is used in.
1981 Autoincrement addressing is a typical example of mode-dependence
1982 because the amount of the increment depends on the mode. */
1985 mode_dependent_address_p (addr
)
1986 rtx addr ATTRIBUTE_UNUSED
; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
1988 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, win
);
1990 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1991 win
: ATTRIBUTE_UNUSED_LABEL
1995 /* Return 1 if OP is a general operand
1996 other than a memory ref with a mode dependent address. */
1999 mode_independent_operand (op
, mode
)
2000 enum machine_mode mode
;
2005 if (! general_operand (op
, mode
))
2008 if (GET_CODE (op
) != MEM
)
2011 addr
= XEXP (op
, 0);
2012 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, lose
);
2014 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
2015 lose
: ATTRIBUTE_UNUSED_LABEL
2019 /* Given an operand OP that is a valid memory reference which
2020 satisfies offsettable_memref_p, return a new memory reference whose
2021 address has been adjusted by OFFSET. OFFSET should be positive and
2022 less than the size of the object referenced. */
2025 adj_offsettable_operand (op
, offset
)
2029 register enum rtx_code code
= GET_CODE (op
);
2033 register rtx y
= XEXP (op
, 0);
2036 if (CONSTANT_ADDRESS_P (y
))
2038 new = gen_rtx_MEM (GET_MODE (op
), plus_constant (y
, offset
));
2039 MEM_COPY_ATTRIBUTES (new, op
);
2043 if (GET_CODE (y
) == PLUS
)
2046 register rtx
*const_loc
;
2050 const_loc
= find_constant_term_loc (&z
);
2053 *const_loc
= plus_constant (*const_loc
, offset
);
2058 new = gen_rtx_MEM (GET_MODE (op
), plus_constant (y
, offset
));
2059 MEM_COPY_ATTRIBUTES (new, op
);
2065 /* Like extract_insn, but save insn extracted and don't extract again, when
2066 called again for the same insn expecting that recog_data still contain the
2067 valid information. This is used primary by gen_attr infrastructure that
2068 often does extract insn again and again. */
2070 extract_insn_cached (insn
)
2073 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2075 extract_insn (insn
);
2076 recog_data
.insn
= insn
;
2078 /* Do cached extract_insn, constrain_operand and complain about failures.
2079 Used by insn_attrtab. */
2081 extract_constrain_insn_cached (insn
)
2084 extract_insn_cached (insn
);
2085 if (which_alternative
== -1
2086 && !constrain_operands (reload_completed
))
2087 fatal_insn_not_found (insn
);
2089 /* Do cached constrain_operand and complain about failures. */
2091 constrain_operands_cached (strict
)
2094 if (which_alternative
== -1)
2095 return constrain_operands (strict
);
2100 /* Analyze INSN and fill in recog_data. */
2109 rtx body
= PATTERN (insn
);
2111 recog_data
.insn
= NULL
;
2112 recog_data
.n_operands
= 0;
2113 recog_data
.n_alternatives
= 0;
2114 recog_data
.n_dups
= 0;
2115 which_alternative
= -1;
2117 switch (GET_CODE (body
))
2127 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2132 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2133 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2134 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2140 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2143 /* This insn is an `asm' with operands. */
2145 /* expand_asm_operands makes sure there aren't too many operands. */
2146 if (noperands
> MAX_RECOG_OPERANDS
)
2149 /* Now get the operand values and constraints out of the insn. */
2150 decode_asm_operands (body
, recog_data
.operand
,
2151 recog_data
.operand_loc
,
2152 recog_data
.constraints
,
2153 recog_data
.operand_mode
);
2156 const char *p
= recog_data
.constraints
[0];
2157 recog_data
.n_alternatives
= 1;
2159 recog_data
.n_alternatives
+= (*p
++ == ',');
2163 fatal_insn_not_found (insn
);
2167 /* Ordinary insn: recognize it, get the operands via insn_extract
2168 and get the constraints. */
2170 icode
= recog_memoized (insn
);
2172 fatal_insn_not_found (insn
);
2174 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2175 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2176 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2178 insn_extract (insn
);
2180 for (i
= 0; i
< noperands
; i
++)
2182 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2183 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2184 /* VOIDmode match_operands gets mode from their real operand. */
2185 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2186 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2189 for (i
= 0; i
< noperands
; i
++)
2190 recog_data
.operand_type
[i
]
2191 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2192 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2195 if (recog_data
.n_alternatives
> MAX_RECOG_ALTERNATIVES
)
2199 /* After calling extract_insn, you can use this function to extract some
2200 information from the constraint strings into a more usable form.
2201 The collected data is stored in recog_op_alt. */
2203 preprocess_constraints ()
2207 memset (recog_op_alt
, 0, sizeof recog_op_alt
);
2208 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2211 struct operand_alternative
*op_alt
;
2212 const char *p
= recog_data
.constraints
[i
];
2214 op_alt
= recog_op_alt
[i
];
2216 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2218 op_alt
[j
].class = NO_REGS
;
2219 op_alt
[j
].constraint
= p
;
2220 op_alt
[j
].matches
= -1;
2221 op_alt
[j
].matched
= -1;
2223 if (*p
== '\0' || *p
== ',')
2225 op_alt
[j
].anything_ok
= 1;
2235 while (c
!= ',' && c
!= '\0');
2236 if (c
== ',' || c
== '\0')
2241 case '=': case '+': case '*': case '%':
2242 case 'E': case 'F': case 'G': case 'H':
2243 case 's': case 'i': case 'n':
2244 case 'I': case 'J': case 'K': case 'L':
2245 case 'M': case 'N': case 'O': case 'P':
2246 /* These don't say anything we care about. */
2250 op_alt
[j
].reject
+= 6;
2253 op_alt
[j
].reject
+= 600;
2256 op_alt
[j
].earlyclobber
= 1;
2259 case '0': case '1': case '2': case '3': case '4':
2260 case '5': case '6': case '7': case '8': case '9':
2261 op_alt
[j
].matches
= c
- '0';
2262 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2266 op_alt
[j
].memory_ok
= 1;
2269 op_alt
[j
].decmem_ok
= 1;
2272 op_alt
[j
].incmem_ok
= 1;
2275 op_alt
[j
].nonoffmem_ok
= 1;
2278 op_alt
[j
].offmem_ok
= 1;
2281 op_alt
[j
].anything_ok
= 1;
2285 op_alt
[j
].is_address
= 1;
2286 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) BASE_REG_CLASS
];
2290 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) GENERAL_REGS
];
2294 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
2302 /* Check the operands of an insn against the insn's operand constraints
2303 and return 1 if they are valid.
2304 The information about the insn's operands, constraints, operand modes
2305 etc. is obtained from the global variables set up by extract_insn.
2307 WHICH_ALTERNATIVE is set to a number which indicates which
2308 alternative of constraints was matched: 0 for the first alternative,
2309 1 for the next, etc.
2311 In addition, when two operands are match
2312 and it happens that the output operand is (reg) while the
2313 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2314 make the output operand look like the input.
2315 This is because the output operand is the one the template will print.
2317 This is used in final, just before printing the assembler code and by
2318 the routines that determine an insn's attribute.
2320 If STRICT is a positive non-zero value, it means that we have been
2321 called after reload has been completed. In that case, we must
2322 do all checks strictly. If it is zero, it means that we have been called
2323 before reload has completed. In that case, we first try to see if we can
2324 find an alternative that matches strictly. If not, we try again, this
2325 time assuming that reload will fix up the insn. This provides a "best
2326 guess" for the alternative and is used to compute attributes of insns prior
2327 to reload. A negative value of STRICT is used for this internal call. */
2335 constrain_operands (strict
)
2338 const char *constraints
[MAX_RECOG_OPERANDS
];
2339 int matching_operands
[MAX_RECOG_OPERANDS
];
2340 int earlyclobber
[MAX_RECOG_OPERANDS
];
2343 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2344 int funny_match_index
;
2346 which_alternative
= 0;
2347 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2350 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2352 constraints
[c
] = recog_data
.constraints
[c
];
2353 matching_operands
[c
] = -1;
2360 funny_match_index
= 0;
2362 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2364 register rtx op
= recog_data
.operand
[opno
];
2365 enum machine_mode mode
= GET_MODE (op
);
2366 register const char *p
= constraints
[opno
];
2371 earlyclobber
[opno
] = 0;
2373 /* A unary operator may be accepted by the predicate, but it
2374 is irrelevant for matching constraints. */
2375 if (GET_RTX_CLASS (GET_CODE (op
)) == '1')
2378 if (GET_CODE (op
) == SUBREG
)
2380 if (GET_CODE (SUBREG_REG (op
)) == REG
2381 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2382 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2383 GET_MODE (SUBREG_REG (op
)),
2386 op
= SUBREG_REG (op
);
2389 /* An empty constraint or empty alternative
2390 allows anything which matched the pattern. */
2391 if (*p
== 0 || *p
== ',')
2394 while (*p
&& (c
= *p
++) != ',')
2397 case '?': case '!': case '*': case '%':
2402 /* Ignore rest of this alternative as far as
2403 constraint checking is concerned. */
2404 while (*p
&& *p
!= ',')
2409 earlyclobber
[opno
] = 1;
2412 case '0': case '1': case '2': case '3': case '4':
2413 case '5': case '6': case '7': case '8': case '9':
2415 /* This operand must be the same as a previous one.
2416 This kind of constraint is used for instructions such
2417 as add when they take only two operands.
2419 Note that the lower-numbered operand is passed first.
2421 If we are not testing strictly, assume that this constraint
2422 will be satisfied. */
2427 rtx op1
= recog_data
.operand
[c
- '0'];
2428 rtx op2
= recog_data
.operand
[opno
];
2430 /* A unary operator may be accepted by the predicate,
2431 but it is irrelevant for matching constraints. */
2432 if (GET_RTX_CLASS (GET_CODE (op1
)) == '1')
2433 op1
= XEXP (op1
, 0);
2434 if (GET_RTX_CLASS (GET_CODE (op2
)) == '1')
2435 op2
= XEXP (op2
, 0);
2437 val
= operands_match_p (op1
, op2
);
2440 matching_operands
[opno
] = c
- '0';
2441 matching_operands
[c
- '0'] = opno
;
2445 /* If output is *x and input is *--x,
2446 arrange later to change the output to *--x as well,
2447 since the output op is the one that will be printed. */
2448 if (val
== 2 && strict
> 0)
2450 funny_match
[funny_match_index
].this = opno
;
2451 funny_match
[funny_match_index
++].other
= c
- '0';
2456 /* p is used for address_operands. When we are called by
2457 gen_reload, no one will have checked that the address is
2458 strictly valid, i.e., that all pseudos requiring hard regs
2459 have gotten them. */
2461 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2466 /* No need to check general_operand again;
2467 it was done in insn-recog.c. */
2469 /* Anything goes unless it is a REG and really has a hard reg
2470 but the hard reg is not in the class GENERAL_REGS. */
2472 || GENERAL_REGS
== ALL_REGS
2473 || GET_CODE (op
) != REG
2474 || (reload_in_progress
2475 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2476 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2481 /* This is used for a MATCH_SCRATCH in the cases when
2482 we don't actually need anything. So anything goes
2488 if (GET_CODE (op
) == MEM
2489 /* Before reload, accept what reload can turn into mem. */
2490 || (strict
< 0 && CONSTANT_P (op
))
2491 /* During reload, accept a pseudo */
2492 || (reload_in_progress
&& GET_CODE (op
) == REG
2493 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2498 if (GET_CODE (op
) == MEM
2499 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2500 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2505 if (GET_CODE (op
) == MEM
2506 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2507 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2512 #ifndef REAL_ARITHMETIC
2513 /* Match any CONST_DOUBLE, but only if
2514 we can examine the bits of it reliably. */
2515 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
2516 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
2517 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
2520 if (GET_CODE (op
) == CONST_DOUBLE
)
2525 if (GET_CODE (op
) == CONST_DOUBLE
)
2531 if (GET_CODE (op
) == CONST_DOUBLE
2532 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
2537 if (GET_CODE (op
) == CONST_INT
2538 || (GET_CODE (op
) == CONST_DOUBLE
2539 && GET_MODE (op
) == VOIDmode
))
2542 if (CONSTANT_P (op
))
2547 if (GET_CODE (op
) == CONST_INT
2548 || (GET_CODE (op
) == CONST_DOUBLE
2549 && GET_MODE (op
) == VOIDmode
))
2561 if (GET_CODE (op
) == CONST_INT
2562 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
2567 if (GET_CODE (op
) == MEM
2568 && ((strict
> 0 && ! offsettable_memref_p (op
))
2570 && !(CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
2571 || (reload_in_progress
2572 && !(GET_CODE (op
) == REG
2573 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2578 if ((strict
> 0 && offsettable_memref_p (op
))
2579 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2580 /* Before reload, accept what reload can handle. */
2582 && (CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
2583 /* During reload, accept a pseudo */
2584 || (reload_in_progress
&& GET_CODE (op
) == REG
2585 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2591 enum reg_class
class;
2593 class = (c
== 'r' ? GENERAL_REGS
: REG_CLASS_FROM_LETTER (c
));
2594 if (class != NO_REGS
)
2598 && GET_CODE (op
) == REG
2599 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2600 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2601 || (GET_CODE (op
) == REG
2602 && reg_fits_class_p (op
, class, offset
, mode
)))
2605 #ifdef EXTRA_CONSTRAINT
2606 else if (EXTRA_CONSTRAINT (op
, c
))
2613 constraints
[opno
] = p
;
2614 /* If this operand did not win somehow,
2615 this alternative loses. */
2619 /* This alternative won; the operands are ok.
2620 Change whichever operands this alternative says to change. */
2625 /* See if any earlyclobber operand conflicts with some other
2629 for (eopno
= 0; eopno
< recog_data
.n_operands
; eopno
++)
2630 /* Ignore earlyclobber operands now in memory,
2631 because we would often report failure when we have
2632 two memory operands, one of which was formerly a REG. */
2633 if (earlyclobber
[eopno
]
2634 && GET_CODE (recog_data
.operand
[eopno
]) == REG
)
2635 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2636 if ((GET_CODE (recog_data
.operand
[opno
]) == MEM
2637 || recog_data
.operand_type
[opno
] != OP_OUT
)
2639 /* Ignore things like match_operator operands. */
2640 && *recog_data
.constraints
[opno
] != 0
2641 && ! (matching_operands
[opno
] == eopno
2642 && operands_match_p (recog_data
.operand
[opno
],
2643 recog_data
.operand
[eopno
]))
2644 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2645 recog_data
.operand
[eopno
]))
2650 while (--funny_match_index
>= 0)
2652 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2653 = recog_data
.operand
[funny_match
[funny_match_index
].this];
2660 which_alternative
++;
2662 while (which_alternative
< recog_data
.n_alternatives
);
2664 which_alternative
= -1;
2665 /* If we are about to reject this, but we are not to test strictly,
2666 try a very loose test. Only return failure if it fails also. */
2668 return constrain_operands (-1);
2673 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2674 is a hard reg in class CLASS when its regno is offset by OFFSET
2675 and changed to mode MODE.
2676 If REG occupies multiple hard regs, all of them must be in CLASS. */
2679 reg_fits_class_p (operand
, class, offset
, mode
)
2681 register enum reg_class
class;
2683 enum machine_mode mode
;
2685 register int regno
= REGNO (operand
);
2686 if (regno
< FIRST_PSEUDO_REGISTER
2687 && TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
2692 for (sr
= HARD_REGNO_NREGS (regno
, mode
) - 1;
2694 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
2703 /* Split single instruction. Helper function for split_all_insns.
2704 Return last insn in the sequence if succesfull, or NULL if unsuccesfull. */
2712 /* Don't split no-op move insns. These should silently
2713 disappear later in final. Splitting such insns would
2714 break the code that handles REG_NO_CONFLICT blocks. */
2716 else if ((set
= single_set (insn
)) != NULL
&& set_noop_p (set
))
2718 /* Nops get in the way while scheduling, so delete them
2719 now if register allocation has already been done. It
2720 is too risky to try to do this before register
2721 allocation, and there are unlikely to be very many
2722 nops then anyways. */
2723 if (reload_completed
)
2725 PUT_CODE (insn
, NOTE
);
2726 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2727 NOTE_SOURCE_FILE (insn
) = 0;
2732 /* Split insns here to get max fine-grain parallelism. */
2733 rtx first
= PREV_INSN (insn
);
2734 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2738 /* try_split returns the NOTE that INSN became. */
2739 PUT_CODE (insn
, NOTE
);
2740 NOTE_SOURCE_FILE (insn
) = 0;
2741 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2743 /* ??? Coddle to md files that generate subregs in post-
2744 reload splitters instead of computing the proper
2746 if (reload_completed
&& first
!= last
)
2748 first
= NEXT_INSN (first
);
2752 cleanup_subreg_operands (first
);
2755 first
= NEXT_INSN (first
);
2763 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2766 split_all_insns (upd_life
)
2777 for (insn
= get_insns (); insn
; insn
= next
)
2781 /* Can't use `next_real_insn' because that might go across
2782 CODE_LABELS and short-out basic blocks. */
2783 next
= NEXT_INSN (insn
);
2784 last
= split_insn (insn
);
2789 blocks
= sbitmap_alloc (n_basic_blocks
);
2790 sbitmap_zero (blocks
);
2793 for (i
= n_basic_blocks
- 1; i
>= 0; --i
)
2795 basic_block bb
= BASIC_BLOCK (i
);
2798 for (insn
= bb
->head
; insn
; insn
= next
)
2802 /* Can't use `next_real_insn' because that might go across
2803 CODE_LABELS and short-out basic blocks. */
2804 next
= NEXT_INSN (insn
);
2805 last
= split_insn (insn
);
2808 SET_BIT (blocks
, i
);
2810 if (insn
== bb
->end
)
2815 if (insn
== bb
->end
)
2823 if (changed
&& upd_life
)
2825 compute_bb_for_insn (get_max_uid ());
2826 count_or_remove_death_notes (blocks
, 1);
2827 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
2830 sbitmap_free (blocks
);
2833 #ifdef HAVE_peephole2
2834 struct peep2_insn_data
2840 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2841 static int peep2_current
;
2843 /* A non-insn marker indicating the last insn of the block.
2844 The live_before regset for this element is correct, indicating
2845 global_live_at_end for the block. */
2846 #define PEEP2_EOB pc_rtx
2848 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2849 does not exist. Used by the recognizer to find the next insn to match
2850 in a multi-insn pattern. */
2856 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2860 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2861 n
-= MAX_INSNS_PER_PEEP2
+ 1;
2863 if (peep2_insn_data
[n
].insn
== PEEP2_EOB
)
2865 return peep2_insn_data
[n
].insn
;
2868 /* Return true if REGNO is dead before the Nth non-note insn
2872 peep2_regno_dead_p (ofs
, regno
)
2876 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2879 ofs
+= peep2_current
;
2880 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2881 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2883 if (peep2_insn_data
[ofs
].insn
== NULL_RTX
)
2886 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
2889 /* Similarly for a REG. */
2892 peep2_reg_dead_p (ofs
, reg
)
2898 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2901 ofs
+= peep2_current
;
2902 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2903 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2905 if (peep2_insn_data
[ofs
].insn
== NULL_RTX
)
2908 regno
= REGNO (reg
);
2909 n
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
2911 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
2916 /* Try to find a hard register of mode MODE, matching the register class in
2917 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2918 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2919 in which case the only condition is that the register must be available
2920 before CURRENT_INSN.
2921 Registers that already have bits set in REG_SET will not be considered.
2923 If an appropriate register is available, it will be returned and the
2924 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2928 peep2_find_free_register (from
, to
, class_str
, mode
, reg_set
)
2930 const char *class_str
;
2931 enum machine_mode mode
;
2932 HARD_REG_SET
*reg_set
;
2934 static int search_ofs
;
2935 enum reg_class
class;
2939 if (from
>= MAX_INSNS_PER_PEEP2
+ 1 || to
>= MAX_INSNS_PER_PEEP2
+ 1)
2942 from
+= peep2_current
;
2943 if (from
>= MAX_INSNS_PER_PEEP2
+ 1)
2944 from
-= MAX_INSNS_PER_PEEP2
+ 1;
2945 to
+= peep2_current
;
2946 if (to
>= MAX_INSNS_PER_PEEP2
+ 1)
2947 to
-= MAX_INSNS_PER_PEEP2
+ 1;
2949 if (peep2_insn_data
[from
].insn
== NULL_RTX
)
2951 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
2955 HARD_REG_SET this_live
;
2957 if (++from
>= MAX_INSNS_PER_PEEP2
+ 1)
2959 if (peep2_insn_data
[from
].insn
== NULL_RTX
)
2961 REG_SET_TO_HARD_REG_SET (this_live
, peep2_insn_data
[from
].live_before
);
2962 IOR_HARD_REG_SET (live
, this_live
);
2965 class = (class_str
[0] == 'r' ? GENERAL_REGS
2966 : REG_CLASS_FROM_LETTER (class_str
[0]));
2968 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2970 int raw_regno
, regno
, success
, j
;
2972 /* Distribute the free registers as much as possible. */
2973 raw_regno
= search_ofs
+ i
;
2974 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
2975 raw_regno
-= FIRST_PSEUDO_REGISTER
;
2976 #ifdef REG_ALLOC_ORDER
2977 regno
= reg_alloc_order
[raw_regno
];
2982 /* Don't allocate fixed registers. */
2983 if (fixed_regs
[regno
])
2985 /* Make sure the register is of the right class. */
2986 if (! TEST_HARD_REG_BIT (reg_class_contents
[class], regno
))
2988 /* And can support the mode we need. */
2989 if (! HARD_REGNO_MODE_OK (regno
, mode
))
2991 /* And that we don't create an extra save/restore. */
2992 if (! call_used_regs
[regno
] && ! regs_ever_live
[regno
])
2994 /* And we don't clobber traceback for noreturn functions. */
2995 if ((regno
== FRAME_POINTER_REGNUM
|| regno
== HARD_FRAME_POINTER_REGNUM
)
2996 && (! reload_completed
|| frame_pointer_needed
))
3000 for (j
= HARD_REGNO_NREGS (regno
, mode
) - 1; j
>= 0; j
--)
3002 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3003 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3011 for (j
= HARD_REGNO_NREGS (regno
, mode
) - 1; j
>= 0; j
--)
3012 SET_HARD_REG_BIT (*reg_set
, regno
+ j
);
3014 /* Start the next search with the next register. */
3015 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3017 search_ofs
= raw_regno
;
3019 return gen_rtx_REG (mode
, regno
);
3027 /* Perform the peephole2 optimization pass. */
3030 peephole2_optimize (dump_file
)
3031 FILE *dump_file ATTRIBUTE_UNUSED
;
3033 regset_head rs_heads
[MAX_INSNS_PER_PEEP2
+ 2];
3037 #ifdef HAVE_conditional_execution
3042 /* Initialize the regsets we're going to use. */
3043 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3044 peep2_insn_data
[i
].live_before
= INITIALIZE_REG_SET (rs_heads
[i
]);
3045 live
= INITIALIZE_REG_SET (rs_heads
[i
]);
3047 #ifdef HAVE_conditional_execution
3048 blocks
= sbitmap_alloc (n_basic_blocks
);
3049 sbitmap_zero (blocks
);
3052 count_or_remove_death_notes (NULL
, 1);
3055 for (b
= n_basic_blocks
- 1; b
>= 0; --b
)
3057 basic_block bb
= BASIC_BLOCK (b
);
3058 struct propagate_block_info
*pbi
;
3060 /* Indicate that all slots except the last holds invalid data. */
3061 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3062 peep2_insn_data
[i
].insn
= NULL_RTX
;
3064 /* Indicate that the last slot contains live_after data. */
3065 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3066 peep2_current
= MAX_INSNS_PER_PEEP2
;
3068 /* Start up propagation. */
3069 COPY_REG_SET (live
, bb
->global_live_at_end
);
3070 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3072 #ifdef HAVE_conditional_execution
3073 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, 0);
3075 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, PROP_DEATH_NOTES
);
3078 for (insn
= bb
->end
; ; insn
= prev
)
3080 prev
= PREV_INSN (insn
);
3086 /* Record this insn. */
3087 if (--peep2_current
< 0)
3088 peep2_current
= MAX_INSNS_PER_PEEP2
;
3089 peep2_insn_data
[peep2_current
].insn
= insn
;
3090 propagate_one_insn (pbi
, insn
);
3091 COPY_REG_SET (peep2_insn_data
[peep2_current
].live_before
, live
);
3093 /* Match the peephole. */
3094 try = peephole2_insns (PATTERN (insn
), insn
, &match_len
);
3097 i
= match_len
+ peep2_current
;
3098 if (i
>= MAX_INSNS_PER_PEEP2
+ 1)
3099 i
-= MAX_INSNS_PER_PEEP2
+ 1;
3101 /* Replace the old sequence with the new. */
3102 flow_delete_insn_chain (insn
, peep2_insn_data
[i
].insn
);
3103 try = emit_insn_after (try, prev
);
3105 /* Adjust the basic block boundaries. */
3106 if (peep2_insn_data
[i
].insn
== bb
->end
)
3108 if (insn
== bb
->head
)
3109 bb
->head
= NEXT_INSN (prev
);
3111 #ifdef HAVE_conditional_execution
3112 /* With conditional execution, we cannot back up the
3113 live information so easily, since the conditional
3114 death data structures are not so self-contained.
3115 So record that we've made a modification to this
3116 block and update life information at the end. */
3117 SET_BIT (blocks
, b
);
3120 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3121 peep2_insn_data
[i
].insn
= NULL_RTX
;
3122 peep2_insn_data
[peep2_current
].insn
= PEEP2_EOB
;
3124 /* Back up lifetime information past the end of the
3125 newly created sequence. */
3126 if (++i
>= MAX_INSNS_PER_PEEP2
+ 1)
3128 COPY_REG_SET (live
, peep2_insn_data
[i
].live_before
);
3130 /* Update life information for the new sequence. */
3136 i
= MAX_INSNS_PER_PEEP2
;
3137 peep2_insn_data
[i
].insn
= try;
3138 propagate_one_insn (pbi
, try);
3139 COPY_REG_SET (peep2_insn_data
[i
].live_before
, live
);
3141 try = PREV_INSN (try);
3143 while (try != prev
);
3145 /* ??? Should verify that LIVE now matches what we
3146 had before the new sequence. */
3153 if (insn
== bb
->head
)
3157 free_propagate_block_info (pbi
);
3160 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3161 FREE_REG_SET (peep2_insn_data
[i
].live_before
);
3162 FREE_REG_SET (live
);
3164 #ifdef HAVE_conditional_execution
3165 count_or_remove_death_notes (blocks
, 1);
3166 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
3167 sbitmap_free (blocks
);
3170 #endif /* HAVE_peephole2 */