1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
27 #include "insn-config.h"
28 #include "insn-attr.h"
29 #include "hard-reg-set.h"
37 #include "basic-block.h"
41 #ifndef STACK_PUSH_CODE
42 #ifdef STACK_GROWS_DOWNWARD
43 #define STACK_PUSH_CODE PRE_DEC
45 #define STACK_PUSH_CODE PRE_INC
49 #ifndef STACK_POP_CODE
50 #ifdef STACK_GROWS_DOWNWARD
51 #define STACK_POP_CODE POST_INC
53 #define STACK_POP_CODE POST_DEC
57 static void validate_replace_rtx_1
PARAMS ((rtx
*, rtx
, rtx
, rtx
));
58 static rtx
*find_single_use_1
PARAMS ((rtx
, rtx
*));
59 static void validate_replace_src_1
PARAMS ((rtx
*, void *));
60 static rtx split_insn
PARAMS ((rtx
));
62 /* Nonzero means allow operands to be volatile.
63 This should be 0 if you are generating rtl, such as if you are calling
64 the functions in optabs.c and expmed.c (most of the time).
65 This should be 1 if all valid insns need to be recognized,
66 such as in regclass.c and final.c and reload.c.
68 init_recog and init_recog_no_volatile are responsible for setting this. */
72 struct recog_data recog_data
;
74 /* Contains a vector of operand_alternative structures for every operand.
75 Set up by preprocess_constraints. */
76 struct operand_alternative recog_op_alt
[MAX_RECOG_OPERANDS
][MAX_RECOG_ALTERNATIVES
];
78 /* On return from `constrain_operands', indicate which alternative
81 int which_alternative
;
83 /* Nonzero after end of reload pass.
84 Set to 1 or 0 by toplev.c.
85 Controls the significance of (SUBREG (MEM)). */
89 /* Initialize data used by the function `recog'.
90 This must be called once in the compilation of a function
91 before any insn recognition may be done in the function. */
94 init_recog_no_volatile ()
105 /* Try recognizing the instruction INSN,
106 and return the code number that results.
107 Remember the code so that repeated calls do not
108 need to spend the time for actual rerecognition.
110 This function is the normal interface to instruction recognition.
111 The automatically-generated function `recog' is normally called
112 through this one. (The only exception is in combine.c.) */
115 recog_memoized_1 (insn
)
118 if (INSN_CODE (insn
) < 0)
119 INSN_CODE (insn
) = recog (PATTERN (insn
), insn
, 0);
120 return INSN_CODE (insn
);
123 /* Check that X is an insn-body for an `asm' with operands
124 and that the operands mentioned in it are legitimate. */
127 check_asm_operands (x
)
132 const char **constraints
;
135 /* Post-reload, be more strict with things. */
136 if (reload_completed
)
138 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
139 extract_insn (make_insn_raw (x
));
140 constrain_operands (1);
141 return which_alternative
>= 0;
144 noperands
= asm_noperands (x
);
150 operands
= (rtx
*) alloca (noperands
* sizeof (rtx
));
151 constraints
= (const char **) alloca (noperands
* sizeof (char *));
153 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
);
155 for (i
= 0; i
< noperands
; i
++)
157 const char *c
= constraints
[i
];
160 if (ISDIGIT ((unsigned char)c
[0]) && c
[1] == '\0')
161 c
= constraints
[c
[0] - '0'];
163 if (! asm_operand_ok (operands
[i
], c
))
170 /* Static data for the next two routines. */
172 typedef struct change_t
180 static change_t
*changes
;
181 static int changes_allocated
;
183 static int num_changes
= 0;
185 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
186 at which NEW will be placed. If OBJECT is zero, no validation is done,
187 the change is simply made.
189 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
190 will be called with the address and mode as parameters. If OBJECT is
191 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
194 IN_GROUP is non-zero if this is part of a group of changes that must be
195 performed as a group. In that case, the changes will be stored. The
196 function `apply_change_group' will validate and apply the changes.
198 If IN_GROUP is zero, this is a single change. Try to recognize the insn
199 or validate the memory reference with the change applied. If the result
200 is not valid for the machine, suppress the change and return zero.
201 Otherwise, perform the change and return 1. */
204 validate_change (object
, loc
, new, in_group
)
212 if (old
== new || rtx_equal_p (old
, new))
215 if (in_group
== 0 && num_changes
!= 0)
220 /* Save the information describing this change. */
221 if (num_changes
>= changes_allocated
)
223 if (changes_allocated
== 0)
224 /* This value allows for repeated substitutions inside complex
225 indexed addresses, or changes in up to 5 insns. */
226 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
228 changes_allocated
*= 2;
231 (change_t
*) xrealloc (changes
,
232 sizeof (change_t
) * changes_allocated
);
235 changes
[num_changes
].object
= object
;
236 changes
[num_changes
].loc
= loc
;
237 changes
[num_changes
].old
= old
;
239 if (object
&& GET_CODE (object
) != MEM
)
241 /* Set INSN_CODE to force rerecognition of insn. Save old code in
243 changes
[num_changes
].old_code
= INSN_CODE (object
);
244 INSN_CODE (object
) = -1;
249 /* If we are making a group of changes, return 1. Otherwise, validate the
250 change group we made. */
255 return apply_change_group ();
258 /* This subroutine of apply_change_group verifies whether the changes to INSN
259 were valid; i.e. whether INSN can still be recognized. */
262 insn_invalid_p (insn
)
265 rtx pat
= PATTERN (insn
);
266 int num_clobbers
= 0;
267 /* If we are before reload and the pattern is a SET, see if we can add
269 int icode
= recog (pat
, insn
,
270 (GET_CODE (pat
) == SET
271 && ! reload_completed
&& ! reload_in_progress
)
272 ? &num_clobbers
: 0);
273 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
276 /* If this is an asm and the operand aren't legal, then fail. Likewise if
277 this is not an asm and the insn wasn't recognized. */
278 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
279 || (!is_asm
&& icode
< 0))
282 /* If we have to add CLOBBERs, fail if we have to add ones that reference
283 hard registers since our callers can't know if they are live or not.
284 Otherwise, add them. */
285 if (num_clobbers
> 0)
289 if (added_clobbers_hard_reg_p (icode
))
292 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
293 XVECEXP (newpat
, 0, 0) = pat
;
294 add_clobbers (newpat
, icode
);
295 PATTERN (insn
) = pat
= newpat
;
298 /* After reload, verify that all constraints are satisfied. */
299 if (reload_completed
)
303 if (! constrain_operands (1))
307 INSN_CODE (insn
) = icode
;
311 /* Apply a group of changes previously issued with `validate_change'.
312 Return 1 if all changes are valid, zero otherwise. */
315 apply_change_group ()
318 rtx last_validated
= NULL_RTX
;
320 /* The changes have been applied and all INSN_CODEs have been reset to force
323 The changes are valid if we aren't given an object, or if we are
324 given a MEM and it still is a valid address, or if this is in insn
325 and it is recognized. In the latter case, if reload has completed,
326 we also require that the operands meet the constraints for
329 for (i
= 0; i
< num_changes
; i
++)
331 rtx object
= changes
[i
].object
;
333 /* if there is no object to test or if it is the same as the one we
334 already tested, ignore it. */
335 if (object
== 0 || object
== last_validated
)
338 if (GET_CODE (object
) == MEM
)
340 if (! memory_address_p (GET_MODE (object
), XEXP (object
, 0)))
343 else if (insn_invalid_p (object
))
345 rtx pat
= PATTERN (object
);
347 /* Perhaps we couldn't recognize the insn because there were
348 extra CLOBBERs at the end. If so, try to re-recognize
349 without the last CLOBBER (later iterations will cause each of
350 them to be eliminated, in turn). But don't do this if we
351 have an ASM_OPERAND. */
352 if (GET_CODE (pat
) == PARALLEL
353 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
354 && asm_noperands (PATTERN (object
)) < 0)
358 if (XVECLEN (pat
, 0) == 2)
359 newpat
= XVECEXP (pat
, 0, 0);
365 = gen_rtx_PARALLEL (VOIDmode
,
366 rtvec_alloc (XVECLEN (pat
, 0) - 1));
367 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
368 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
371 /* Add a new change to this group to replace the pattern
372 with this new pattern. Then consider this change
373 as having succeeded. The change we added will
374 cause the entire call to fail if things remain invalid.
376 Note that this can lose if a later change than the one
377 we are processing specified &XVECEXP (PATTERN (object), 0, X)
378 but this shouldn't occur. */
380 validate_change (object
, &PATTERN (object
), newpat
, 1);
383 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
)
384 /* If this insn is a CLOBBER or USE, it is always valid, but is
390 last_validated
= object
;
393 if (i
== num_changes
)
405 /* Return the number of changes so far in the current group. */
408 num_validated_changes ()
413 /* Retract the changes numbered NUM and up. */
421 /* Back out all the changes. Do this in the opposite order in which
423 for (i
= num_changes
- 1; i
>= num
; i
--)
425 *changes
[i
].loc
= changes
[i
].old
;
426 if (changes
[i
].object
&& GET_CODE (changes
[i
].object
) != MEM
)
427 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
432 /* Replace every occurrence of FROM in X with TO. Mark each change with
433 validate_change passing OBJECT. */
436 validate_replace_rtx_1 (loc
, from
, to
, object
)
438 rtx from
, to
, object
;
444 enum machine_mode op0_mode
= VOIDmode
;
445 int prev_changes
= num_changes
;
452 fmt
= GET_RTX_FORMAT (code
);
454 op0_mode
= GET_MODE (XEXP (x
, 0));
456 /* X matches FROM if it is the same rtx or they are both referring to the
457 same register in the same mode. Avoid calling rtx_equal_p unless the
458 operands look similar. */
461 || (GET_CODE (x
) == REG
&& GET_CODE (from
) == REG
462 && GET_MODE (x
) == GET_MODE (from
)
463 && REGNO (x
) == REGNO (from
))
464 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
465 && rtx_equal_p (x
, from
)))
467 validate_change (object
, loc
, to
, 1);
471 /* Call ourseves recursivly to perform the replacements. */
473 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
476 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
);
477 else if (fmt
[i
] == 'E')
478 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
479 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
);
482 /* In case we didn't substituted, there is nothing to do. */
483 if (num_changes
== prev_changes
)
486 /* Allow substituted expression to have different mode. This is used by
487 regmove to change mode of pseudo register. */
488 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
489 op0_mode
= GET_MODE (XEXP (x
, 0));
491 /* Do changes needed to keep rtx consistent. Don't do any other
492 simplifications, as it is not our job. */
494 if ((GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
495 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
497 validate_change (object
, loc
,
498 gen_rtx_fmt_ee (GET_RTX_CLASS (code
) == 'c' ? code
499 : swap_condition (code
),
500 GET_MODE (x
), XEXP (x
, 1),
509 /* If we have a PLUS whose second operand is now a CONST_INT, use
510 plus_constant to try to simplify it.
511 ??? We may want later to remove this, once simplification is
512 separated from this function. */
513 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
514 validate_change (object
, loc
,
515 plus_constant (XEXP (x
, 0), INTVAL (XEXP (x
, 1))), 1);
518 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
519 || GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
)
520 validate_change (object
, loc
,
522 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
523 simplify_gen_unary (NEG
,
524 GET_MODE (x
), XEXP (x
, 1),
529 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
531 new = simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
533 /* If any of the above failed, substitute in something that
534 we know won't be recognized. */
536 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
537 validate_change (object
, loc
, new, 1);
541 /* All subregs possible to simplify should be simplified. */
542 new = simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
545 /* Subregs of VOIDmode operands are incorect. */
546 if (!new && GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
547 new = gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
549 validate_change (object
, loc
, new, 1);
553 /* If we are replacing a register with memory, try to change the memory
554 to be the mode required for memory in extract operations (this isn't
555 likely to be an insertion operation; if it was, nothing bad will
556 happen, we might just fail in some cases). */
558 if (GET_CODE (XEXP (x
, 0)) == MEM
559 && GET_CODE (XEXP (x
, 1)) == CONST_INT
560 && GET_CODE (XEXP (x
, 2)) == CONST_INT
561 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0))
562 && !MEM_VOLATILE_P (XEXP (x
, 0)))
564 enum machine_mode wanted_mode
= VOIDmode
;
565 enum machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
566 int pos
= INTVAL (XEXP (x
, 2));
568 if (GET_CODE (x
) == ZERO_EXTRACT
)
570 enum machine_mode new_mode
571 = mode_for_extraction (EP_extzv
, 1);
572 if (new_mode
!= MAX_MACHINE_MODE
)
573 wanted_mode
= new_mode
;
575 else if (GET_CODE (x
) == SIGN_EXTRACT
)
577 enum machine_mode new_mode
578 = mode_for_extraction (EP_extv
, 1);
579 if (new_mode
!= MAX_MACHINE_MODE
)
580 wanted_mode
= new_mode
;
583 /* If we have a narrower mode, we can do something. */
584 if (wanted_mode
!= VOIDmode
585 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
587 int offset
= pos
/ BITS_PER_UNIT
;
590 /* If the bytes and bits are counted differently, we
591 must adjust the offset. */
592 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
594 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
597 pos
%= GET_MODE_BITSIZE (wanted_mode
);
599 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
601 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
602 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
613 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
614 with TO. After all changes have been made, validate by seeing
615 if INSN is still valid. */
618 validate_replace_rtx_subexp (from
, to
, insn
, loc
)
619 rtx from
, to
, insn
, *loc
;
621 validate_replace_rtx_1 (loc
, from
, to
, insn
);
622 return apply_change_group ();
625 /* Try replacing every occurrence of FROM in INSN with TO. After all
626 changes have been made, validate by seeing if INSN is still valid. */
629 validate_replace_rtx (from
, to
, insn
)
632 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
633 return apply_change_group ();
636 /* Try replacing every occurrence of FROM in INSN with TO. */
639 validate_replace_rtx_group (from
, to
, insn
)
642 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
);
645 /* Function called by note_uses to replace used subexpressions. */
646 struct validate_replace_src_data
648 rtx from
; /* Old RTX */
649 rtx to
; /* New RTX */
650 rtx insn
; /* Insn in which substitution is occurring. */
654 validate_replace_src_1 (x
, data
)
658 struct validate_replace_src_data
*d
659 = (struct validate_replace_src_data
*) data
;
661 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
);
664 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
665 SET_DESTs. After all changes have been made, validate by seeing if
666 INSN is still valid. */
669 validate_replace_src (from
, to
, insn
)
672 struct validate_replace_src_data d
;
677 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
678 return apply_change_group ();
682 /* Return 1 if the insn using CC0 set by INSN does not contain
683 any ordered tests applied to the condition codes.
684 EQ and NE tests do not count. */
687 next_insn_tests_no_inequality (insn
)
690 rtx next
= next_cc0_user (insn
);
692 /* If there is no next insn, we have to take the conservative choice. */
696 return ((GET_CODE (next
) == JUMP_INSN
697 || GET_CODE (next
) == INSN
698 || GET_CODE (next
) == CALL_INSN
)
699 && ! inequality_comparisons_p (PATTERN (next
)));
702 #if 0 /* This is useless since the insn that sets the cc's
703 must be followed immediately by the use of them. */
704 /* Return 1 if the CC value set up by INSN is not used. */
707 next_insns_test_no_inequality (insn
)
710 rtx next
= NEXT_INSN (insn
);
712 for (; next
!= 0; next
= NEXT_INSN (next
))
714 if (GET_CODE (next
) == CODE_LABEL
715 || GET_CODE (next
) == BARRIER
)
717 if (GET_CODE (next
) == NOTE
)
719 if (inequality_comparisons_p (PATTERN (next
)))
721 if (sets_cc0_p (PATTERN (next
)) == 1)
723 if (! reg_mentioned_p (cc0_rtx
, PATTERN (next
)))
731 /* This is used by find_single_use to locate an rtx that contains exactly one
732 use of DEST, which is typically either a REG or CC0. It returns a
733 pointer to the innermost rtx expression containing DEST. Appearances of
734 DEST that are being used to totally replace it are not counted. */
737 find_single_use_1 (dest
, loc
)
742 enum rtx_code code
= GET_CODE (x
);
759 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
760 of a REG that occupies all of the REG, the insn uses DEST if
761 it is mentioned in the destination or the source. Otherwise, we
762 need just check the source. */
763 if (GET_CODE (SET_DEST (x
)) != CC0
764 && GET_CODE (SET_DEST (x
)) != PC
765 && GET_CODE (SET_DEST (x
)) != REG
766 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
767 && GET_CODE (SUBREG_REG (SET_DEST (x
))) == REG
768 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
769 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
770 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
771 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
774 return find_single_use_1 (dest
, &SET_SRC (x
));
778 return find_single_use_1 (dest
, &XEXP (x
, 0));
784 /* If it wasn't one of the common cases above, check each expression and
785 vector of this code. Look for a unique usage of DEST. */
787 fmt
= GET_RTX_FORMAT (code
);
788 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
792 if (dest
== XEXP (x
, i
)
793 || (GET_CODE (dest
) == REG
&& GET_CODE (XEXP (x
, i
)) == REG
794 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
797 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
800 result
= this_result
;
801 else if (this_result
)
802 /* Duplicate usage. */
805 else if (fmt
[i
] == 'E')
809 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
811 if (XVECEXP (x
, i
, j
) == dest
812 || (GET_CODE (dest
) == REG
813 && GET_CODE (XVECEXP (x
, i
, j
)) == REG
814 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
817 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
820 result
= this_result
;
821 else if (this_result
)
830 /* See if DEST, produced in INSN, is used only a single time in the
831 sequel. If so, return a pointer to the innermost rtx expression in which
834 If PLOC is non-zero, *PLOC is set to the insn containing the single use.
836 This routine will return usually zero either before flow is called (because
837 there will be no LOG_LINKS notes) or after reload (because the REG_DEAD
838 note can't be trusted).
840 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
841 care about REG_DEAD notes or LOG_LINKS.
843 Otherwise, we find the single use by finding an insn that has a
844 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
845 only referenced once in that insn, we know that it must be the first
846 and last insn referencing DEST. */
849 find_single_use (dest
, insn
, ploc
)
861 next
= NEXT_INSN (insn
);
863 || (GET_CODE (next
) != INSN
&& GET_CODE (next
) != JUMP_INSN
))
866 result
= find_single_use_1 (dest
, &PATTERN (next
));
873 if (reload_completed
|| reload_in_progress
|| GET_CODE (dest
) != REG
)
876 for (next
= next_nonnote_insn (insn
);
877 next
!= 0 && GET_CODE (next
) != CODE_LABEL
;
878 next
= next_nonnote_insn (next
))
879 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
881 for (link
= LOG_LINKS (next
); link
; link
= XEXP (link
, 1))
882 if (XEXP (link
, 0) == insn
)
887 result
= find_single_use_1 (dest
, &PATTERN (next
));
897 /* Return 1 if OP is a valid general operand for machine mode MODE.
898 This is either a register reference, a memory reference,
899 or a constant. In the case of a memory reference, the address
900 is checked for general validity for the target machine.
902 Register and memory references must have mode MODE in order to be valid,
903 but some constants have no machine mode and are valid for any mode.
905 If MODE is VOIDmode, OP is checked for validity for whatever mode
908 The main use of this function is as a predicate in match_operand
909 expressions in the machine description.
911 For an explanation of this function's behavior for registers of
912 class NO_REGS, see the comment for `register_operand'. */
915 general_operand (op
, mode
)
917 enum machine_mode mode
;
919 enum rtx_code code
= GET_CODE (op
);
921 if (mode
== VOIDmode
)
922 mode
= GET_MODE (op
);
924 /* Don't accept CONST_INT or anything similar
925 if the caller wants something floating. */
926 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
927 && GET_MODE_CLASS (mode
) != MODE_INT
928 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
931 if (GET_CODE (op
) == CONST_INT
932 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
936 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
938 #ifdef LEGITIMATE_PIC_OPERAND_P
939 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
941 && LEGITIMATE_CONSTANT_P (op
));
943 /* Except for certain constants with VOIDmode, already checked for,
944 OP's mode must match MODE if MODE specifies a mode. */
946 if (GET_MODE (op
) != mode
)
951 #ifdef INSN_SCHEDULING
952 /* On machines that have insn scheduling, we want all memory
953 reference to be explicit, so outlaw paradoxical SUBREGs. */
954 if (GET_CODE (SUBREG_REG (op
)) == MEM
955 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
958 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
959 may result in incorrect reference. We should simplify all valid
960 subregs of MEM anyway. But allow this after reload because we
961 might be called from cleanup_subreg_operands.
963 ??? This is a kludge. */
964 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
965 && GET_CODE (SUBREG_REG (op
)) == MEM
)
968 op
= SUBREG_REG (op
);
969 code
= GET_CODE (op
);
973 /* A register whose class is NO_REGS is not a general operand. */
974 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
975 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
);
979 rtx y
= XEXP (op
, 0);
981 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
984 if (GET_CODE (y
) == ADDRESSOF
)
987 /* Use the mem's mode, since it will be reloaded thus. */
988 mode
= GET_MODE (op
);
989 GO_IF_LEGITIMATE_ADDRESS (mode
, y
, win
);
992 /* Pretend this is an operand for now; we'll run force_operand
993 on its replacement in fixup_var_refs_1. */
994 if (code
== ADDRESSOF
)
1003 /* Return 1 if OP is a valid memory address for a memory reference
1006 The main use of this function is as a predicate in match_operand
1007 expressions in the machine description. */
1010 address_operand (op
, mode
)
1012 enum machine_mode mode
;
1014 return memory_address_p (mode
, op
);
1017 /* Return 1 if OP is a register reference of mode MODE.
1018 If MODE is VOIDmode, accept a register in any mode.
1020 The main use of this function is as a predicate in match_operand
1021 expressions in the machine description.
1023 As a special exception, registers whose class is NO_REGS are
1024 not accepted by `register_operand'. The reason for this change
1025 is to allow the representation of special architecture artifacts
1026 (such as a condition code register) without extending the rtl
1027 definitions. Since registers of class NO_REGS cannot be used
1028 as registers in any case where register classes are examined,
1029 it is most consistent to keep this function from accepting them. */
1032 register_operand (op
, mode
)
1034 enum machine_mode mode
;
1036 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1039 if (GET_CODE (op
) == SUBREG
)
1041 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1042 because it is guaranteed to be reloaded into one.
1043 Just make sure the MEM is valid in itself.
1044 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1045 but currently it does result from (SUBREG (REG)...) where the
1046 reg went on the stack.) */
1047 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1048 return general_operand (op
, mode
);
1050 #ifdef CLASS_CANNOT_CHANGE_MODE
1051 if (GET_CODE (SUBREG_REG (op
)) == REG
1052 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
1053 && (TEST_HARD_REG_BIT
1054 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
],
1055 REGNO (SUBREG_REG (op
))))
1056 && CLASS_CANNOT_CHANGE_MODE_P (mode
, GET_MODE (SUBREG_REG (op
)))
1057 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_INT
1058 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op
))) != MODE_COMPLEX_FLOAT
)
1062 op
= SUBREG_REG (op
);
1065 /* If we have an ADDRESSOF, consider it valid since it will be
1066 converted into something that will not be a MEM. */
1067 if (GET_CODE (op
) == ADDRESSOF
)
1070 /* We don't consider registers whose class is NO_REGS
1071 to be a register operand. */
1072 return (GET_CODE (op
) == REG
1073 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1074 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1077 /* Return 1 for a register in Pmode; ignore the tested mode. */
1080 pmode_register_operand (op
, mode
)
1082 enum machine_mode mode ATTRIBUTE_UNUSED
;
1084 return register_operand (op
, Pmode
);
1087 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1088 or a hard register. */
1091 scratch_operand (op
, mode
)
1093 enum machine_mode mode
;
1095 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1098 return (GET_CODE (op
) == SCRATCH
1099 || (GET_CODE (op
) == REG
1100 && REGNO (op
) < FIRST_PSEUDO_REGISTER
));
1103 /* Return 1 if OP is a valid immediate operand for mode MODE.
1105 The main use of this function is as a predicate in match_operand
1106 expressions in the machine description. */
1109 immediate_operand (op
, mode
)
1111 enum machine_mode mode
;
1113 /* Don't accept CONST_INT or anything similar
1114 if the caller wants something floating. */
1115 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1116 && GET_MODE_CLASS (mode
) != MODE_INT
1117 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1120 if (GET_CODE (op
) == CONST_INT
1121 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1124 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and
1125 result in 0/1. It seems a safe assumption that this is
1126 in range for everyone. */
1127 if (GET_CODE (op
) == CONSTANT_P_RTX
)
1130 return (CONSTANT_P (op
)
1131 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1132 || GET_MODE (op
) == VOIDmode
)
1133 #ifdef LEGITIMATE_PIC_OPERAND_P
1134 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1136 && LEGITIMATE_CONSTANT_P (op
));
1139 /* Returns 1 if OP is an operand that is a CONST_INT. */
1142 const_int_operand (op
, mode
)
1144 enum machine_mode mode
;
1146 if (GET_CODE (op
) != CONST_INT
)
1149 if (mode
!= VOIDmode
1150 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1156 /* Returns 1 if OP is an operand that is a constant integer or constant
1157 floating-point number. */
1160 const_double_operand (op
, mode
)
1162 enum machine_mode mode
;
1164 /* Don't accept CONST_INT or anything similar
1165 if the caller wants something floating. */
1166 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1167 && GET_MODE_CLASS (mode
) != MODE_INT
1168 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1171 return ((GET_CODE (op
) == CONST_DOUBLE
|| GET_CODE (op
) == CONST_INT
)
1172 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1173 || GET_MODE (op
) == VOIDmode
));
1176 /* Return 1 if OP is a general operand that is not an immediate operand. */
1179 nonimmediate_operand (op
, mode
)
1181 enum machine_mode mode
;
1183 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1186 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1189 nonmemory_operand (op
, mode
)
1191 enum machine_mode mode
;
1193 if (CONSTANT_P (op
))
1195 /* Don't accept CONST_INT or anything similar
1196 if the caller wants something floating. */
1197 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1198 && GET_MODE_CLASS (mode
) != MODE_INT
1199 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1202 if (GET_CODE (op
) == CONST_INT
1203 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1206 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
1207 || mode
== VOIDmode
)
1208 #ifdef LEGITIMATE_PIC_OPERAND_P
1209 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1211 && LEGITIMATE_CONSTANT_P (op
));
1214 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1217 if (GET_CODE (op
) == SUBREG
)
1219 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1220 because it is guaranteed to be reloaded into one.
1221 Just make sure the MEM is valid in itself.
1222 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1223 but currently it does result from (SUBREG (REG)...) where the
1224 reg went on the stack.) */
1225 if (! reload_completed
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1226 return general_operand (op
, mode
);
1227 op
= SUBREG_REG (op
);
1230 /* We don't consider registers whose class is NO_REGS
1231 to be a register operand. */
1232 return (GET_CODE (op
) == REG
1233 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1234 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
1237 /* Return 1 if OP is a valid operand that stands for pushing a
1238 value of mode MODE onto the stack.
1240 The main use of this function is as a predicate in match_operand
1241 expressions in the machine description. */
1244 push_operand (op
, mode
)
1246 enum machine_mode mode
;
1248 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1250 #ifdef PUSH_ROUNDING
1251 rounded_size
= PUSH_ROUNDING (rounded_size
);
1254 if (GET_CODE (op
) != MEM
)
1257 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1262 if (rounded_size
== GET_MODE_SIZE (mode
))
1264 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1269 if (GET_CODE (op
) != PRE_MODIFY
1270 || GET_CODE (XEXP (op
, 1)) != PLUS
1271 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1272 || GET_CODE (XEXP (XEXP (op
, 1), 1)) != CONST_INT
1273 #ifdef STACK_GROWS_DOWNWARD
1274 || INTVAL (XEXP (XEXP (op
, 1), 1)) != - (int) rounded_size
1276 || INTVAL (XEXP (XEXP (op
, 1), 1)) != rounded_size
1282 return XEXP (op
, 0) == stack_pointer_rtx
;
1285 /* Return 1 if OP is a valid operand that stands for popping a
1286 value of mode MODE off the stack.
1288 The main use of this function is as a predicate in match_operand
1289 expressions in the machine description. */
1292 pop_operand (op
, mode
)
1294 enum machine_mode mode
;
1296 if (GET_CODE (op
) != MEM
)
1299 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1304 if (GET_CODE (op
) != STACK_POP_CODE
)
1307 return XEXP (op
, 0) == stack_pointer_rtx
;
1310 /* Return 1 if ADDR is a valid memory address for mode MODE. */
1313 memory_address_p (mode
, addr
)
1314 enum machine_mode mode ATTRIBUTE_UNUSED
;
1317 if (GET_CODE (addr
) == ADDRESSOF
)
1320 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1327 /* Return 1 if OP is a valid memory reference with mode MODE,
1328 including a valid address.
1330 The main use of this function is as a predicate in match_operand
1331 expressions in the machine description. */
1334 memory_operand (op
, mode
)
1336 enum machine_mode mode
;
1340 if (! reload_completed
)
1341 /* Note that no SUBREG is a memory operand before end of reload pass,
1342 because (SUBREG (MEM...)) forces reloading into a register. */
1343 return GET_CODE (op
) == MEM
&& general_operand (op
, mode
);
1345 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1349 if (GET_CODE (inner
) == SUBREG
)
1350 inner
= SUBREG_REG (inner
);
1352 return (GET_CODE (inner
) == MEM
&& general_operand (op
, mode
));
1355 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1356 that is, a memory reference whose address is a general_operand. */
1359 indirect_operand (op
, mode
)
1361 enum machine_mode mode
;
1363 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1364 if (! reload_completed
1365 && GET_CODE (op
) == SUBREG
&& GET_CODE (SUBREG_REG (op
)) == MEM
)
1367 int offset
= SUBREG_BYTE (op
);
1368 rtx inner
= SUBREG_REG (op
);
1370 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1373 /* The only way that we can have a general_operand as the resulting
1374 address is if OFFSET is zero and the address already is an operand
1375 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1378 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1379 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1380 && GET_CODE (XEXP (XEXP (inner
, 0), 1)) == CONST_INT
1381 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1382 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1385 return (GET_CODE (op
) == MEM
1386 && memory_operand (op
, mode
)
1387 && general_operand (XEXP (op
, 0), Pmode
));
1390 /* Return 1 if this is a comparison operator. This allows the use of
1391 MATCH_OPERATOR to recognize all the branch insns. */
1394 comparison_operator (op
, mode
)
1396 enum machine_mode mode
;
1398 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1399 && GET_RTX_CLASS (GET_CODE (op
)) == '<');
1402 /* If BODY is an insn body that uses ASM_OPERANDS,
1403 return the number of operands (both input and output) in the insn.
1404 Otherwise return -1. */
1407 asm_noperands (body
)
1410 switch (GET_CODE (body
))
1413 /* No output operands: return number of input operands. */
1414 return ASM_OPERANDS_INPUT_LENGTH (body
);
1416 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1417 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1418 return ASM_OPERANDS_INPUT_LENGTH (SET_SRC (body
)) + 1;
1422 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
1423 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
1425 /* Multiple output operands, or 1 output plus some clobbers:
1426 body is [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1430 /* Count backwards through CLOBBERs to determine number of SETs. */
1431 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1433 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1435 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1439 /* N_SETS is now number of output operands. */
1442 /* Verify that all the SETs we have
1443 came from a single original asm_operands insn
1444 (so that invalid combinations are blocked). */
1445 for (i
= 0; i
< n_sets
; i
++)
1447 rtx elt
= XVECEXP (body
, 0, i
);
1448 if (GET_CODE (elt
) != SET
)
1450 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1452 /* If these ASM_OPERANDS rtx's came from different original insns
1453 then they aren't allowed together. */
1454 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1455 != ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (body
, 0, 0))))
1458 return (ASM_OPERANDS_INPUT_LENGTH (SET_SRC (XVECEXP (body
, 0, 0)))
1461 else if (GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1463 /* 0 outputs, but some clobbers:
1464 body is [(asm_operands ...) (clobber (reg ...))...]. */
1467 /* Make sure all the other parallel things really are clobbers. */
1468 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1469 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1472 return ASM_OPERANDS_INPUT_LENGTH (XVECEXP (body
, 0, 0));
1481 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1482 copy its operands (both input and output) into the vector OPERANDS,
1483 the locations of the operands within the insn into the vector OPERAND_LOCS,
1484 and the constraints for the operands into CONSTRAINTS.
1485 Write the modes of the operands into MODES.
1486 Return the assembler-template.
1488 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1489 we don't store that info. */
1492 decode_asm_operands (body
, operands
, operand_locs
, constraints
, modes
)
1496 const char **constraints
;
1497 enum machine_mode
*modes
;
1501 const char *template = 0;
1503 if (GET_CODE (body
) == SET
&& GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
1505 rtx asmop
= SET_SRC (body
);
1506 /* Single output operand: BODY is (set OUTPUT (asm_operands ....)). */
1508 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
) + 1;
1510 for (i
= 1; i
< noperands
; i
++)
1513 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
- 1);
1515 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
- 1);
1517 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
- 1);
1519 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
- 1);
1522 /* The output is in the SET.
1523 Its constraint is in the ASM_OPERANDS itself. */
1525 operands
[0] = SET_DEST (body
);
1527 operand_locs
[0] = &SET_DEST (body
);
1529 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1531 modes
[0] = GET_MODE (SET_DEST (body
));
1532 template = ASM_OPERANDS_TEMPLATE (asmop
);
1534 else if (GET_CODE (body
) == ASM_OPERANDS
)
1537 /* No output operands: BODY is (asm_operands ....). */
1539 noperands
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1541 /* The input operands are found in the 1st element vector. */
1542 /* Constraints for inputs are in the 2nd element vector. */
1543 for (i
= 0; i
< noperands
; i
++)
1546 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1548 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1550 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1552 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1554 template = ASM_OPERANDS_TEMPLATE (asmop
);
1556 else if (GET_CODE (body
) == PARALLEL
1557 && GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1559 rtx asmop
= SET_SRC (XVECEXP (body
, 0, 0));
1560 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1561 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1562 int nout
= 0; /* Does not include CLOBBERs. */
1564 /* At least one output, plus some CLOBBERs. */
1566 /* The outputs are in the SETs.
1567 Their constraints are in the ASM_OPERANDS itself. */
1568 for (i
= 0; i
< nparallel
; i
++)
1570 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1571 break; /* Past last SET */
1574 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1576 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1578 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1580 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1584 for (i
= 0; i
< nin
; i
++)
1587 operand_locs
[i
+ nout
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1589 operands
[i
+ nout
] = ASM_OPERANDS_INPUT (asmop
, i
);
1591 constraints
[i
+ nout
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1593 modes
[i
+ nout
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1596 template = ASM_OPERANDS_TEMPLATE (asmop
);
1598 else if (GET_CODE (body
) == PARALLEL
1599 && GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
1601 /* No outputs, but some CLOBBERs. */
1603 rtx asmop
= XVECEXP (body
, 0, 0);
1604 int nin
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1606 for (i
= 0; i
< nin
; i
++)
1609 operand_locs
[i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1611 operands
[i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1613 constraints
[i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1615 modes
[i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1618 template = ASM_OPERANDS_TEMPLATE (asmop
);
1624 /* Check if an asm_operand matches it's constraints.
1625 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1628 asm_operand_ok (op
, constraint
)
1630 const char *constraint
;
1634 /* Use constrain_operands after reload. */
1635 if (reload_completed
)
1640 char c
= *constraint
++;
1654 case '0': case '1': case '2': case '3': case '4':
1655 case '5': case '6': case '7': case '8': case '9':
1656 /* For best results, our caller should have given us the
1657 proper matching constraint, but we can't actually fail
1658 the check if they didn't. Indicate that results are
1664 if (address_operand (op
, VOIDmode
))
1669 case 'V': /* non-offsettable */
1670 if (memory_operand (op
, VOIDmode
))
1674 case 'o': /* offsettable */
1675 if (offsettable_nonstrict_memref_p (op
))
1680 /* ??? Before flow, auto inc/dec insns are not supposed to exist,
1681 excepting those that expand_call created. Further, on some
1682 machines which do not have generalized auto inc/dec, an inc/dec
1683 is not a memory_operand.
1685 Match any memory and hope things are resolved after reload. */
1687 if (GET_CODE (op
) == MEM
1689 || GET_CODE (XEXP (op
, 0)) == PRE_DEC
1690 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1695 if (GET_CODE (op
) == MEM
1697 || GET_CODE (XEXP (op
, 0)) == PRE_INC
1698 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1703 #ifndef REAL_ARITHMETIC
1704 /* Match any floating double constant, but only if
1705 we can examine the bits of it reliably. */
1706 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
1707 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
1708 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
1714 if (GET_CODE (op
) == CONST_DOUBLE
)
1719 if (GET_CODE (op
) == CONST_DOUBLE
1720 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, 'G'))
1724 if (GET_CODE (op
) == CONST_DOUBLE
1725 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, 'H'))
1730 if (GET_CODE (op
) == CONST_INT
1731 || (GET_CODE (op
) == CONST_DOUBLE
1732 && GET_MODE (op
) == VOIDmode
))
1738 #ifdef LEGITIMATE_PIC_OPERAND_P
1739 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1746 if (GET_CODE (op
) == CONST_INT
1747 || (GET_CODE (op
) == CONST_DOUBLE
1748 && GET_MODE (op
) == VOIDmode
))
1753 if (GET_CODE (op
) == CONST_INT
1754 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'I'))
1758 if (GET_CODE (op
) == CONST_INT
1759 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'J'))
1763 if (GET_CODE (op
) == CONST_INT
1764 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'K'))
1768 if (GET_CODE (op
) == CONST_INT
1769 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'L'))
1773 if (GET_CODE (op
) == CONST_INT
1774 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'M'))
1778 if (GET_CODE (op
) == CONST_INT
1779 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'N'))
1783 if (GET_CODE (op
) == CONST_INT
1784 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'O'))
1788 if (GET_CODE (op
) == CONST_INT
1789 && CONST_OK_FOR_LETTER_P (INTVAL (op
), 'P'))
1797 if (general_operand (op
, VOIDmode
))
1802 /* For all other letters, we first check for a register class,
1803 otherwise it is an EXTRA_CONSTRAINT. */
1804 if (REG_CLASS_FROM_LETTER (c
) != NO_REGS
)
1807 if (GET_MODE (op
) == BLKmode
)
1809 if (register_operand (op
, VOIDmode
))
1812 #ifdef EXTRA_CONSTRAINT
1813 if (EXTRA_CONSTRAINT (op
, c
))
1823 /* Given an rtx *P, if it is a sum containing an integer constant term,
1824 return the location (type rtx *) of the pointer to that constant term.
1825 Otherwise, return a null pointer. */
1828 find_constant_term_loc (p
)
1832 enum rtx_code code
= GET_CODE (*p
);
1834 /* If *P IS such a constant term, P is its location. */
1836 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1840 /* Otherwise, if not a sum, it has no constant term. */
1842 if (GET_CODE (*p
) != PLUS
)
1845 /* If one of the summands is constant, return its location. */
1847 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1848 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1851 /* Otherwise, check each summand for containing a constant term. */
1853 if (XEXP (*p
, 0) != 0)
1855 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1860 if (XEXP (*p
, 1) != 0)
1862 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1870 /* Return 1 if OP is a memory reference
1871 whose address contains no side effects
1872 and remains valid after the addition
1873 of a positive integer less than the
1874 size of the object being referenced.
1876 We assume that the original address is valid and do not check it.
1878 This uses strict_memory_address_p as a subroutine, so
1879 don't use it before reload. */
1882 offsettable_memref_p (op
)
1885 return ((GET_CODE (op
) == MEM
)
1886 && offsettable_address_p (1, GET_MODE (op
), XEXP (op
, 0)));
1889 /* Similar, but don't require a strictly valid mem ref:
1890 consider pseudo-regs valid as index or base regs. */
1893 offsettable_nonstrict_memref_p (op
)
1896 return ((GET_CODE (op
) == MEM
)
1897 && offsettable_address_p (0, GET_MODE (op
), XEXP (op
, 0)));
1900 /* Return 1 if Y is a memory address which contains no side effects
1901 and would remain valid after the addition of a positive integer
1902 less than the size of that mode.
1904 We assume that the original address is valid and do not check it.
1905 We do check that it is valid for narrower modes.
1907 If STRICTP is nonzero, we require a strictly valid address,
1908 for the sake of use in reload.c. */
1911 offsettable_address_p (strictp
, mode
, y
)
1913 enum machine_mode mode
;
1916 enum rtx_code ycode
= GET_CODE (y
);
1920 int (*addressp
) PARAMS ((enum machine_mode
, rtx
)) =
1921 (strictp
? strict_memory_address_p
: memory_address_p
);
1922 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1924 if (CONSTANT_ADDRESS_P (y
))
1927 /* Adjusting an offsettable address involves changing to a narrower mode.
1928 Make sure that's OK. */
1930 if (mode_dependent_address_p (y
))
1933 /* ??? How much offset does an offsettable BLKmode reference need?
1934 Clearly that depends on the situation in which it's being used.
1935 However, the current situation in which we test 0xffffffff is
1936 less than ideal. Caveat user. */
1938 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1940 /* If the expression contains a constant term,
1941 see if it remains valid when max possible offset is added. */
1943 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1948 *y2
= plus_constant (*y2
, mode_sz
- 1);
1949 /* Use QImode because an odd displacement may be automatically invalid
1950 for any wider mode. But it should be valid for a single byte. */
1951 good
= (*addressp
) (QImode
, y
);
1953 /* In any case, restore old contents of memory. */
1958 if (GET_RTX_CLASS (ycode
) == 'a')
1961 /* The offset added here is chosen as the maximum offset that
1962 any instruction could need to add when operating on something
1963 of the specified mode. We assume that if Y and Y+c are
1964 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1965 go inside a LO_SUM here, so we do so as well. */
1966 if (GET_CODE (y
) == LO_SUM
)
1967 z
= gen_rtx_LO_SUM (GET_MODE (y
), XEXP (y
, 0),
1968 plus_constant (XEXP (y
, 1), mode_sz
- 1));
1970 z
= plus_constant (y
, mode_sz
- 1);
1972 /* Use QImode because an odd displacement may be automatically invalid
1973 for any wider mode. But it should be valid for a single byte. */
1974 return (*addressp
) (QImode
, z
);
1977 /* Return 1 if ADDR is an address-expression whose effect depends
1978 on the mode of the memory reference it is used in.
1980 Autoincrement addressing is a typical example of mode-dependence
1981 because the amount of the increment depends on the mode. */
1984 mode_dependent_address_p (addr
)
1985 rtx addr ATTRIBUTE_UNUSED
; /* Maybe used in GO_IF_MODE_DEPENDENT_ADDRESS. */
1987 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, win
);
1989 /* Label `win' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
1990 win
: ATTRIBUTE_UNUSED_LABEL
1994 /* Return 1 if OP is a general operand
1995 other than a memory ref with a mode dependent address. */
1998 mode_independent_operand (op
, mode
)
1999 enum machine_mode mode
;
2004 if (! general_operand (op
, mode
))
2007 if (GET_CODE (op
) != MEM
)
2010 addr
= XEXP (op
, 0);
2011 GO_IF_MODE_DEPENDENT_ADDRESS (addr
, lose
);
2013 /* Label `lose' might (not) be used via GO_IF_MODE_DEPENDENT_ADDRESS. */
2014 lose
: ATTRIBUTE_UNUSED_LABEL
2018 /* Like extract_insn, but save insn extracted and don't extract again, when
2019 called again for the same insn expecting that recog_data still contain the
2020 valid information. This is used primary by gen_attr infrastructure that
2021 often does extract insn again and again. */
2023 extract_insn_cached (insn
)
2026 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2028 extract_insn (insn
);
2029 recog_data
.insn
= insn
;
2031 /* Do cached extract_insn, constrain_operand and complain about failures.
2032 Used by insn_attrtab. */
2034 extract_constrain_insn_cached (insn
)
2037 extract_insn_cached (insn
);
2038 if (which_alternative
== -1
2039 && !constrain_operands (reload_completed
))
2040 fatal_insn_not_found (insn
);
2042 /* Do cached constrain_operand and complain about failures. */
2044 constrain_operands_cached (strict
)
2047 if (which_alternative
== -1)
2048 return constrain_operands (strict
);
2053 /* Analyze INSN and fill in recog_data. */
2062 rtx body
= PATTERN (insn
);
2064 recog_data
.insn
= NULL
;
2065 recog_data
.n_operands
= 0;
2066 recog_data
.n_alternatives
= 0;
2067 recog_data
.n_dups
= 0;
2068 which_alternative
= -1;
2070 switch (GET_CODE (body
))
2080 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2085 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2086 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2087 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2093 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2096 /* This insn is an `asm' with operands. */
2098 /* expand_asm_operands makes sure there aren't too many operands. */
2099 if (noperands
> MAX_RECOG_OPERANDS
)
2102 /* Now get the operand values and constraints out of the insn. */
2103 decode_asm_operands (body
, recog_data
.operand
,
2104 recog_data
.operand_loc
,
2105 recog_data
.constraints
,
2106 recog_data
.operand_mode
);
2109 const char *p
= recog_data
.constraints
[0];
2110 recog_data
.n_alternatives
= 1;
2112 recog_data
.n_alternatives
+= (*p
++ == ',');
2116 fatal_insn_not_found (insn
);
2120 /* Ordinary insn: recognize it, get the operands via insn_extract
2121 and get the constraints. */
2123 icode
= recog_memoized (insn
);
2125 fatal_insn_not_found (insn
);
2127 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2128 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2129 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2131 insn_extract (insn
);
2133 for (i
= 0; i
< noperands
; i
++)
2135 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2136 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2137 /* VOIDmode match_operands gets mode from their real operand. */
2138 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2139 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2142 for (i
= 0; i
< noperands
; i
++)
2143 recog_data
.operand_type
[i
]
2144 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2145 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2148 if (recog_data
.n_alternatives
> MAX_RECOG_ALTERNATIVES
)
2152 /* After calling extract_insn, you can use this function to extract some
2153 information from the constraint strings into a more usable form.
2154 The collected data is stored in recog_op_alt. */
2156 preprocess_constraints ()
2160 memset (recog_op_alt
, 0, sizeof recog_op_alt
);
2161 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2164 struct operand_alternative
*op_alt
;
2165 const char *p
= recog_data
.constraints
[i
];
2167 op_alt
= recog_op_alt
[i
];
2169 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
2171 op_alt
[j
].class = NO_REGS
;
2172 op_alt
[j
].constraint
= p
;
2173 op_alt
[j
].matches
= -1;
2174 op_alt
[j
].matched
= -1;
2176 if (*p
== '\0' || *p
== ',')
2178 op_alt
[j
].anything_ok
= 1;
2188 while (c
!= ',' && c
!= '\0');
2189 if (c
== ',' || c
== '\0')
2194 case '=': case '+': case '*': case '%':
2195 case 'E': case 'F': case 'G': case 'H':
2196 case 's': case 'i': case 'n':
2197 case 'I': case 'J': case 'K': case 'L':
2198 case 'M': case 'N': case 'O': case 'P':
2199 /* These don't say anything we care about. */
2203 op_alt
[j
].reject
+= 6;
2206 op_alt
[j
].reject
+= 600;
2209 op_alt
[j
].earlyclobber
= 1;
2212 case '0': case '1': case '2': case '3': case '4':
2213 case '5': case '6': case '7': case '8': case '9':
2214 op_alt
[j
].matches
= c
- '0';
2215 recog_op_alt
[op_alt
[j
].matches
][j
].matched
= i
;
2219 op_alt
[j
].memory_ok
= 1;
2222 op_alt
[j
].decmem_ok
= 1;
2225 op_alt
[j
].incmem_ok
= 1;
2228 op_alt
[j
].nonoffmem_ok
= 1;
2231 op_alt
[j
].offmem_ok
= 1;
2234 op_alt
[j
].anything_ok
= 1;
2238 op_alt
[j
].is_address
= 1;
2239 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) BASE_REG_CLASS
];
2243 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) GENERAL_REGS
];
2247 op_alt
[j
].class = reg_class_subunion
[(int) op_alt
[j
].class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c
)];
2255 /* Check the operands of an insn against the insn's operand constraints
2256 and return 1 if they are valid.
2257 The information about the insn's operands, constraints, operand modes
2258 etc. is obtained from the global variables set up by extract_insn.
2260 WHICH_ALTERNATIVE is set to a number which indicates which
2261 alternative of constraints was matched: 0 for the first alternative,
2262 1 for the next, etc.
2264 In addition, when two operands are match
2265 and it happens that the output operand is (reg) while the
2266 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2267 make the output operand look like the input.
2268 This is because the output operand is the one the template will print.
2270 This is used in final, just before printing the assembler code and by
2271 the routines that determine an insn's attribute.
2273 If STRICT is a positive non-zero value, it means that we have been
2274 called after reload has been completed. In that case, we must
2275 do all checks strictly. If it is zero, it means that we have been called
2276 before reload has completed. In that case, we first try to see if we can
2277 find an alternative that matches strictly. If not, we try again, this
2278 time assuming that reload will fix up the insn. This provides a "best
2279 guess" for the alternative and is used to compute attributes of insns prior
2280 to reload. A negative value of STRICT is used for this internal call. */
2288 constrain_operands (strict
)
2291 const char *constraints
[MAX_RECOG_OPERANDS
];
2292 int matching_operands
[MAX_RECOG_OPERANDS
];
2293 int earlyclobber
[MAX_RECOG_OPERANDS
];
2296 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2297 int funny_match_index
;
2299 which_alternative
= 0;
2300 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2303 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2305 constraints
[c
] = recog_data
.constraints
[c
];
2306 matching_operands
[c
] = -1;
2313 funny_match_index
= 0;
2315 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2317 rtx op
= recog_data
.operand
[opno
];
2318 enum machine_mode mode
= GET_MODE (op
);
2319 const char *p
= constraints
[opno
];
2324 earlyclobber
[opno
] = 0;
2326 /* A unary operator may be accepted by the predicate, but it
2327 is irrelevant for matching constraints. */
2328 if (GET_RTX_CLASS (GET_CODE (op
)) == '1')
2331 if (GET_CODE (op
) == SUBREG
)
2333 if (GET_CODE (SUBREG_REG (op
)) == REG
2334 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2335 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2336 GET_MODE (SUBREG_REG (op
)),
2339 op
= SUBREG_REG (op
);
2342 /* An empty constraint or empty alternative
2343 allows anything which matched the pattern. */
2344 if (*p
== 0 || *p
== ',')
2347 while (*p
&& (c
= *p
++) != ',')
2350 case '?': case '!': case '*': case '%':
2355 /* Ignore rest of this alternative as far as
2356 constraint checking is concerned. */
2357 while (*p
&& *p
!= ',')
2362 earlyclobber
[opno
] = 1;
2365 case '0': case '1': case '2': case '3': case '4':
2366 case '5': case '6': case '7': case '8': case '9':
2368 /* This operand must be the same as a previous one.
2369 This kind of constraint is used for instructions such
2370 as add when they take only two operands.
2372 Note that the lower-numbered operand is passed first.
2374 If we are not testing strictly, assume that this constraint
2375 will be satisfied. */
2380 rtx op1
= recog_data
.operand
[c
- '0'];
2381 rtx op2
= recog_data
.operand
[opno
];
2383 /* A unary operator may be accepted by the predicate,
2384 but it is irrelevant for matching constraints. */
2385 if (GET_RTX_CLASS (GET_CODE (op1
)) == '1')
2386 op1
= XEXP (op1
, 0);
2387 if (GET_RTX_CLASS (GET_CODE (op2
)) == '1')
2388 op2
= XEXP (op2
, 0);
2390 val
= operands_match_p (op1
, op2
);
2393 matching_operands
[opno
] = c
- '0';
2394 matching_operands
[c
- '0'] = opno
;
2398 /* If output is *x and input is *--x,
2399 arrange later to change the output to *--x as well,
2400 since the output op is the one that will be printed. */
2401 if (val
== 2 && strict
> 0)
2403 funny_match
[funny_match_index
].this = opno
;
2404 funny_match
[funny_match_index
++].other
= c
- '0';
2409 /* p is used for address_operands. When we are called by
2410 gen_reload, no one will have checked that the address is
2411 strictly valid, i.e., that all pseudos requiring hard regs
2412 have gotten them. */
2414 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2419 /* No need to check general_operand again;
2420 it was done in insn-recog.c. */
2422 /* Anything goes unless it is a REG and really has a hard reg
2423 but the hard reg is not in the class GENERAL_REGS. */
2425 || GENERAL_REGS
== ALL_REGS
2426 || GET_CODE (op
) != REG
2427 || (reload_in_progress
2428 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2429 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2434 /* This is used for a MATCH_SCRATCH in the cases when
2435 we don't actually need anything. So anything goes
2441 if (GET_CODE (op
) == MEM
2442 /* Before reload, accept what reload can turn into mem. */
2443 || (strict
< 0 && CONSTANT_P (op
))
2444 /* During reload, accept a pseudo */
2445 || (reload_in_progress
&& GET_CODE (op
) == REG
2446 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2451 if (GET_CODE (op
) == MEM
2452 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
2453 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
2458 if (GET_CODE (op
) == MEM
2459 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
2460 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
2465 #ifndef REAL_ARITHMETIC
2466 /* Match any CONST_DOUBLE, but only if
2467 we can examine the bits of it reliably. */
2468 if ((HOST_FLOAT_FORMAT
!= TARGET_FLOAT_FORMAT
2469 || HOST_BITS_PER_WIDE_INT
!= BITS_PER_WORD
)
2470 && GET_MODE (op
) != VOIDmode
&& ! flag_pretend_float
)
2473 if (GET_CODE (op
) == CONST_DOUBLE
)
2478 if (GET_CODE (op
) == CONST_DOUBLE
)
2484 if (GET_CODE (op
) == CONST_DOUBLE
2485 && CONST_DOUBLE_OK_FOR_LETTER_P (op
, c
))
2490 if (GET_CODE (op
) == CONST_INT
2491 || (GET_CODE (op
) == CONST_DOUBLE
2492 && GET_MODE (op
) == VOIDmode
))
2495 if (CONSTANT_P (op
))
2500 if (GET_CODE (op
) == CONST_INT
2501 || (GET_CODE (op
) == CONST_DOUBLE
2502 && GET_MODE (op
) == VOIDmode
))
2514 if (GET_CODE (op
) == CONST_INT
2515 && CONST_OK_FOR_LETTER_P (INTVAL (op
), c
))
2520 if (GET_CODE (op
) == MEM
2521 && ((strict
> 0 && ! offsettable_memref_p (op
))
2523 && !(CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
2524 || (reload_in_progress
2525 && !(GET_CODE (op
) == REG
2526 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))))
2531 if ((strict
> 0 && offsettable_memref_p (op
))
2532 || (strict
== 0 && offsettable_nonstrict_memref_p (op
))
2533 /* Before reload, accept what reload can handle. */
2535 && (CONSTANT_P (op
) || GET_CODE (op
) == MEM
))
2536 /* During reload, accept a pseudo */
2537 || (reload_in_progress
&& GET_CODE (op
) == REG
2538 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2544 enum reg_class
class;
2546 class = (c
== 'r' ? GENERAL_REGS
: REG_CLASS_FROM_LETTER (c
));
2547 if (class != NO_REGS
)
2551 && GET_CODE (op
) == REG
2552 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2553 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2554 || (GET_CODE (op
) == REG
2555 && reg_fits_class_p (op
, class, offset
, mode
)))
2558 #ifdef EXTRA_CONSTRAINT
2559 else if (EXTRA_CONSTRAINT (op
, c
))
2566 constraints
[opno
] = p
;
2567 /* If this operand did not win somehow,
2568 this alternative loses. */
2572 /* This alternative won; the operands are ok.
2573 Change whichever operands this alternative says to change. */
2578 /* See if any earlyclobber operand conflicts with some other
2582 for (eopno
= 0; eopno
< recog_data
.n_operands
; eopno
++)
2583 /* Ignore earlyclobber operands now in memory,
2584 because we would often report failure when we have
2585 two memory operands, one of which was formerly a REG. */
2586 if (earlyclobber
[eopno
]
2587 && GET_CODE (recog_data
.operand
[eopno
]) == REG
)
2588 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2589 if ((GET_CODE (recog_data
.operand
[opno
]) == MEM
2590 || recog_data
.operand_type
[opno
] != OP_OUT
)
2592 /* Ignore things like match_operator operands. */
2593 && *recog_data
.constraints
[opno
] != 0
2594 && ! (matching_operands
[opno
] == eopno
2595 && operands_match_p (recog_data
.operand
[opno
],
2596 recog_data
.operand
[eopno
]))
2597 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2598 recog_data
.operand
[eopno
]))
2603 while (--funny_match_index
>= 0)
2605 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2606 = recog_data
.operand
[funny_match
[funny_match_index
].this];
2613 which_alternative
++;
2615 while (which_alternative
< recog_data
.n_alternatives
);
2617 which_alternative
= -1;
2618 /* If we are about to reject this, but we are not to test strictly,
2619 try a very loose test. Only return failure if it fails also. */
2621 return constrain_operands (-1);
2626 /* Return 1 iff OPERAND (assumed to be a REG rtx)
2627 is a hard reg in class CLASS when its regno is offset by OFFSET
2628 and changed to mode MODE.
2629 If REG occupies multiple hard regs, all of them must be in CLASS. */
2632 reg_fits_class_p (operand
, class, offset
, mode
)
2634 enum reg_class
class;
2636 enum machine_mode mode
;
2638 int regno
= REGNO (operand
);
2639 if (regno
< FIRST_PSEUDO_REGISTER
2640 && TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
2645 for (sr
= HARD_REGNO_NREGS (regno
, mode
) - 1;
2647 if (! TEST_HARD_REG_BIT (reg_class_contents
[(int) class],
2656 /* Split single instruction. Helper function for split_all_insns.
2657 Return last insn in the sequence if succesfull, or NULL if unsuccesfull. */
2665 /* Don't split no-op move insns. These should silently
2666 disappear later in final. Splitting such insns would
2667 break the code that handles REG_NO_CONFLICT blocks. */
2669 else if ((set
= single_set (insn
)) != NULL
&& set_noop_p (set
))
2671 /* Nops get in the way while scheduling, so delete them
2672 now if register allocation has already been done. It
2673 is too risky to try to do this before register
2674 allocation, and there are unlikely to be very many
2675 nops then anyways. */
2676 if (reload_completed
)
2678 PUT_CODE (insn
, NOTE
);
2679 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2680 NOTE_SOURCE_FILE (insn
) = 0;
2685 /* Split insns here to get max fine-grain parallelism. */
2686 rtx first
= PREV_INSN (insn
);
2687 rtx last
= try_split (PATTERN (insn
), insn
, 1);
2691 /* try_split returns the NOTE that INSN became. */
2692 PUT_CODE (insn
, NOTE
);
2693 NOTE_SOURCE_FILE (insn
) = 0;
2694 NOTE_LINE_NUMBER (insn
) = NOTE_INSN_DELETED
;
2696 /* ??? Coddle to md files that generate subregs in post-
2697 reload splitters instead of computing the proper
2699 if (reload_completed
&& first
!= last
)
2701 first
= NEXT_INSN (first
);
2705 cleanup_subreg_operands (first
);
2708 first
= NEXT_INSN (first
);
2716 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2719 split_all_insns (upd_life
)
2726 blocks
= sbitmap_alloc (n_basic_blocks
);
2727 sbitmap_zero (blocks
);
2730 for (i
= n_basic_blocks
- 1; i
>= 0; --i
)
2732 basic_block bb
= BASIC_BLOCK (i
);
2735 for (insn
= bb
->head
; insn
; insn
= next
)
2739 /* Can't use `next_real_insn' because that might go across
2740 CODE_LABELS and short-out basic blocks. */
2741 next
= NEXT_INSN (insn
);
2742 last
= split_insn (insn
);
2745 /* The split sequence may include barrier, but the
2746 BB boundary we are interested in will be set to previous
2749 while (GET_CODE (last
) == BARRIER
)
2750 last
= PREV_INSN (last
);
2751 SET_BIT (blocks
, i
);
2756 if (insn
== bb
->end
)
2766 for (i
= 0; i
< n_basic_blocks
; i
++)
2767 find_sub_basic_blocks (BASIC_BLOCK (i
));
2770 if (changed
&& upd_life
)
2772 count_or_remove_death_notes (blocks
, 1);
2773 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
2775 #ifdef ENABLE_CHECKING
2776 verify_flow_info ();
2779 sbitmap_free (blocks
);
2782 /* Same as split_all_insns, but do not expect CFG to be available.
2783 Used by machine depedent reorg passes. */
2786 split_all_insns_noflow ()
2790 for (insn
= get_insns (); insn
; insn
= next
)
2792 next
= NEXT_INSN (insn
);
2798 #ifdef HAVE_peephole2
2799 struct peep2_insn_data
2805 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
2806 static int peep2_current
;
2808 /* A non-insn marker indicating the last insn of the block.
2809 The live_before regset for this element is correct, indicating
2810 global_live_at_end for the block. */
2811 #define PEEP2_EOB pc_rtx
2813 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
2814 does not exist. Used by the recognizer to find the next insn to match
2815 in a multi-insn pattern. */
2821 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2825 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
2826 n
-= MAX_INSNS_PER_PEEP2
+ 1;
2828 if (peep2_insn_data
[n
].insn
== PEEP2_EOB
)
2830 return peep2_insn_data
[n
].insn
;
2833 /* Return true if REGNO is dead before the Nth non-note insn
2837 peep2_regno_dead_p (ofs
, regno
)
2841 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2844 ofs
+= peep2_current
;
2845 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2846 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2848 if (peep2_insn_data
[ofs
].insn
== NULL_RTX
)
2851 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
2854 /* Similarly for a REG. */
2857 peep2_reg_dead_p (ofs
, reg
)
2863 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2866 ofs
+= peep2_current
;
2867 if (ofs
>= MAX_INSNS_PER_PEEP2
+ 1)
2868 ofs
-= MAX_INSNS_PER_PEEP2
+ 1;
2870 if (peep2_insn_data
[ofs
].insn
== NULL_RTX
)
2873 regno
= REGNO (reg
);
2874 n
= HARD_REGNO_NREGS (regno
, GET_MODE (reg
));
2876 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
+ n
))
2881 /* Try to find a hard register of mode MODE, matching the register class in
2882 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
2883 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
2884 in which case the only condition is that the register must be available
2885 before CURRENT_INSN.
2886 Registers that already have bits set in REG_SET will not be considered.
2888 If an appropriate register is available, it will be returned and the
2889 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
2893 peep2_find_free_register (from
, to
, class_str
, mode
, reg_set
)
2895 const char *class_str
;
2896 enum machine_mode mode
;
2897 HARD_REG_SET
*reg_set
;
2899 static int search_ofs
;
2900 enum reg_class
class;
2904 if (from
>= MAX_INSNS_PER_PEEP2
+ 1 || to
>= MAX_INSNS_PER_PEEP2
+ 1)
2907 from
+= peep2_current
;
2908 if (from
>= MAX_INSNS_PER_PEEP2
+ 1)
2909 from
-= MAX_INSNS_PER_PEEP2
+ 1;
2910 to
+= peep2_current
;
2911 if (to
>= MAX_INSNS_PER_PEEP2
+ 1)
2912 to
-= MAX_INSNS_PER_PEEP2
+ 1;
2914 if (peep2_insn_data
[from
].insn
== NULL_RTX
)
2916 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
2920 HARD_REG_SET this_live
;
2922 if (++from
>= MAX_INSNS_PER_PEEP2
+ 1)
2924 if (peep2_insn_data
[from
].insn
== NULL_RTX
)
2926 REG_SET_TO_HARD_REG_SET (this_live
, peep2_insn_data
[from
].live_before
);
2927 IOR_HARD_REG_SET (live
, this_live
);
2930 class = (class_str
[0] == 'r' ? GENERAL_REGS
2931 : REG_CLASS_FROM_LETTER (class_str
[0]));
2933 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2935 int raw_regno
, regno
, success
, j
;
2937 /* Distribute the free registers as much as possible. */
2938 raw_regno
= search_ofs
+ i
;
2939 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
2940 raw_regno
-= FIRST_PSEUDO_REGISTER
;
2941 #ifdef REG_ALLOC_ORDER
2942 regno
= reg_alloc_order
[raw_regno
];
2947 /* Don't allocate fixed registers. */
2948 if (fixed_regs
[regno
])
2950 /* Make sure the register is of the right class. */
2951 if (! TEST_HARD_REG_BIT (reg_class_contents
[class], regno
))
2953 /* And can support the mode we need. */
2954 if (! HARD_REGNO_MODE_OK (regno
, mode
))
2956 /* And that we don't create an extra save/restore. */
2957 if (! call_used_regs
[regno
] && ! regs_ever_live
[regno
])
2959 /* And we don't clobber traceback for noreturn functions. */
2960 if ((regno
== FRAME_POINTER_REGNUM
|| regno
== HARD_FRAME_POINTER_REGNUM
)
2961 && (! reload_completed
|| frame_pointer_needed
))
2965 for (j
= HARD_REGNO_NREGS (regno
, mode
) - 1; j
>= 0; j
--)
2967 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
2968 || TEST_HARD_REG_BIT (live
, regno
+ j
))
2976 for (j
= HARD_REGNO_NREGS (regno
, mode
) - 1; j
>= 0; j
--)
2977 SET_HARD_REG_BIT (*reg_set
, regno
+ j
);
2979 /* Start the next search with the next register. */
2980 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
2982 search_ofs
= raw_regno
;
2984 return gen_rtx_REG (mode
, regno
);
2992 /* Perform the peephole2 optimization pass. */
2995 peephole2_optimize (dump_file
)
2996 FILE *dump_file ATTRIBUTE_UNUSED
;
2998 regset_head rs_heads
[MAX_INSNS_PER_PEEP2
+ 2];
3002 #ifdef HAVE_conditional_execution
3007 /* Initialize the regsets we're going to use. */
3008 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3009 peep2_insn_data
[i
].live_before
= INITIALIZE_REG_SET (rs_heads
[i
]);
3010 live
= INITIALIZE_REG_SET (rs_heads
[i
]);
3012 #ifdef HAVE_conditional_execution
3013 blocks
= sbitmap_alloc (n_basic_blocks
);
3014 sbitmap_zero (blocks
);
3017 count_or_remove_death_notes (NULL
, 1);
3020 for (b
= n_basic_blocks
- 1; b
>= 0; --b
)
3022 basic_block bb
= BASIC_BLOCK (b
);
3023 struct propagate_block_info
*pbi
;
3025 /* Indicate that all slots except the last holds invalid data. */
3026 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3027 peep2_insn_data
[i
].insn
= NULL_RTX
;
3029 /* Indicate that the last slot contains live_after data. */
3030 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3031 peep2_current
= MAX_INSNS_PER_PEEP2
;
3033 /* Start up propagation. */
3034 COPY_REG_SET (live
, bb
->global_live_at_end
);
3035 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3037 #ifdef HAVE_conditional_execution
3038 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, 0);
3040 pbi
= init_propagate_block_info (bb
, live
, NULL
, NULL
, PROP_DEATH_NOTES
);
3043 for (insn
= bb
->end
; ; insn
= prev
)
3045 prev
= PREV_INSN (insn
);
3051 /* Record this insn. */
3052 if (--peep2_current
< 0)
3053 peep2_current
= MAX_INSNS_PER_PEEP2
;
3054 peep2_insn_data
[peep2_current
].insn
= insn
;
3055 propagate_one_insn (pbi
, insn
);
3056 COPY_REG_SET (peep2_insn_data
[peep2_current
].live_before
, live
);
3058 /* Match the peephole. */
3059 try = peephole2_insns (PATTERN (insn
), insn
, &match_len
);
3062 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3063 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3064 cfg-related call notes. */
3065 for (i
= 0; i
<= match_len
; ++i
)
3068 rtx old_insn
, new_insn
, note
;
3070 j
= i
+ peep2_current
;
3071 if (j
>= MAX_INSNS_PER_PEEP2
+ 1)
3072 j
-= MAX_INSNS_PER_PEEP2
+ 1;
3073 old_insn
= peep2_insn_data
[j
].insn
;
3074 if (GET_CODE (old_insn
) != CALL_INSN
)
3077 new_insn
= NULL_RTX
;
3078 if (GET_CODE (try) == SEQUENCE
)
3079 for (k
= XVECLEN (try, 0) - 1; k
>= 0; k
--)
3081 rtx x
= XVECEXP (try, 0, k
);
3082 if (GET_CODE (x
) == CALL_INSN
)
3088 else if (GET_CODE (try) == CALL_INSN
)
3093 CALL_INSN_FUNCTION_USAGE (new_insn
)
3094 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3096 for (note
= REG_NOTES (old_insn
);
3098 note
= XEXP (note
, 1))
3099 switch (REG_NOTE_KIND (note
))
3104 case REG_ALWAYS_RETURN
:
3105 REG_NOTES (new_insn
)
3106 = gen_rtx_EXPR_LIST (REG_NOTE_KIND (note
),
3108 REG_NOTES (new_insn
));
3112 /* Croak if there is another call in the sequence. */
3113 while (++i
<= match_len
)
3115 j
= i
+ peep2_current
;
3116 if (j
>= MAX_INSNS_PER_PEEP2
+ 1)
3117 j
-= MAX_INSNS_PER_PEEP2
+ 1;
3118 old_insn
= peep2_insn_data
[j
].insn
;
3119 if (GET_CODE (old_insn
) == CALL_INSN
)
3125 i
= match_len
+ peep2_current
;
3126 if (i
>= MAX_INSNS_PER_PEEP2
+ 1)
3127 i
-= MAX_INSNS_PER_PEEP2
+ 1;
3129 /* Replace the old sequence with the new. */
3130 try = emit_insn_after (try, peep2_insn_data
[i
].insn
);
3131 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
);
3133 #ifdef HAVE_conditional_execution
3134 /* With conditional execution, we cannot back up the
3135 live information so easily, since the conditional
3136 death data structures are not so self-contained.
3137 So record that we've made a modification to this
3138 block and update life information at the end. */
3139 SET_BIT (blocks
, b
);
3142 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3143 peep2_insn_data
[i
].insn
= NULL_RTX
;
3144 peep2_insn_data
[peep2_current
].insn
= PEEP2_EOB
;
3146 /* Back up lifetime information past the end of the
3147 newly created sequence. */
3148 if (++i
>= MAX_INSNS_PER_PEEP2
+ 1)
3150 COPY_REG_SET (live
, peep2_insn_data
[i
].live_before
);
3152 /* Update life information for the new sequence. */
3158 i
= MAX_INSNS_PER_PEEP2
;
3159 peep2_insn_data
[i
].insn
= try;
3160 propagate_one_insn (pbi
, try);
3161 COPY_REG_SET (peep2_insn_data
[i
].live_before
, live
);
3163 try = PREV_INSN (try);
3165 while (try != prev
);
3167 /* ??? Should verify that LIVE now matches what we
3168 had before the new sequence. */
3175 if (insn
== bb
->head
)
3179 free_propagate_block_info (pbi
);
3182 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3183 FREE_REG_SET (peep2_insn_data
[i
].live_before
);
3184 FREE_REG_SET (live
);
3186 #ifdef HAVE_conditional_execution
3187 count_or_remove_death_notes (blocks
, 1);
3188 update_life_info (blocks
, UPDATE_LIFE_LOCAL
, PROP_DEATH_NOTES
);
3189 sbitmap_free (blocks
);
3192 #endif /* HAVE_peephole2 */