1 /* Subroutines used by or related to instruction recognition.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
32 #include "insn-config.h"
37 #include "rtl-error.h"
38 #include "insn-attr.h"
39 #include "addresses.h"
49 #include "cfgcleanup.h"
51 #include "tree-pass.h"
53 #ifndef STACK_POP_CODE
54 #if STACK_GROWS_DOWNWARD
55 #define STACK_POP_CODE POST_INC
57 #define STACK_POP_CODE POST_DEC
61 static void validate_replace_rtx_1 (rtx
*, rtx
, rtx
, rtx_insn
*, bool);
62 static void validate_replace_src_1 (rtx
*, void *);
63 static rtx_insn
*split_insn (rtx_insn
*);
65 struct target_recog default_target_recog
;
67 struct target_recog
*this_target_recog
= &default_target_recog
;
70 /* Nonzero means allow operands to be volatile.
71 This should be 0 if you are generating rtl, such as if you are calling
72 the functions in optabs.c and expmed.c (most of the time).
73 This should be 1 if all valid insns need to be recognized,
74 such as in reginfo.c and final.c and reload.c.
76 init_recog and init_recog_no_volatile are responsible for setting this. */
80 struct recog_data_d recog_data
;
82 /* Contains a vector of operand_alternative structures, such that
83 operand OP of alternative A is at index A * n_operands + OP.
84 Set up by preprocess_constraints. */
85 const operand_alternative
*recog_op_alt
;
87 /* Used to provide recog_op_alt for asms. */
88 static operand_alternative asm_op_alt
[MAX_RECOG_OPERANDS
89 * MAX_RECOG_ALTERNATIVES
];
91 /* On return from `constrain_operands', indicate which alternative
94 int which_alternative
;
96 /* Nonzero after end of reload pass.
97 Set to 1 or 0 by toplev.c.
98 Controls the significance of (SUBREG (MEM)). */
100 int reload_completed
;
102 /* Nonzero after thread_prologue_and_epilogue_insns has run. */
103 int epilogue_completed
;
105 /* Initialize data used by the function `recog'.
106 This must be called once in the compilation of a function
107 before any insn recognition may be done in the function. */
110 init_recog_no_volatile (void)
122 /* Return true if labels in asm operands BODY are LABEL_REFs. */
125 asm_labels_ok (rtx body
)
130 asmop
= extract_asm_operands (body
);
131 if (asmop
== NULL_RTX
)
134 for (i
= 0; i
< ASM_OPERANDS_LABEL_LENGTH (asmop
); i
++)
135 if (GET_CODE (ASM_OPERANDS_LABEL (asmop
, i
)) != LABEL_REF
)
141 /* Check that X is an insn-body for an `asm' with operands
142 and that the operands mentioned in it are legitimate. */
145 check_asm_operands (rtx x
)
149 const char **constraints
;
152 if (!asm_labels_ok (x
))
155 /* Post-reload, be more strict with things. */
156 if (reload_completed
)
158 /* ??? Doh! We've not got the wrapping insn. Cook one up. */
159 rtx_insn
*insn
= make_insn_raw (x
);
161 constrain_operands (1, get_enabled_alternatives (insn
));
162 return which_alternative
>= 0;
165 noperands
= asm_noperands (x
);
171 operands
= XALLOCAVEC (rtx
, noperands
);
172 constraints
= XALLOCAVEC (const char *, noperands
);
174 decode_asm_operands (x
, operands
, NULL
, constraints
, NULL
, NULL
);
176 for (i
= 0; i
< noperands
; i
++)
178 const char *c
= constraints
[i
];
181 if (! asm_operand_ok (operands
[i
], c
, constraints
))
188 /* Static data for the next two routines. */
199 static change_t
*changes
;
200 static int changes_allocated
;
202 static int num_changes
= 0;
204 /* Validate a proposed change to OBJECT. LOC is the location in the rtl
205 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done,
206 the change is simply made.
208 Two types of objects are supported: If OBJECT is a MEM, memory_address_p
209 will be called with the address and mode as parameters. If OBJECT is
210 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with
213 IN_GROUP is nonzero if this is part of a group of changes that must be
214 performed as a group. In that case, the changes will be stored. The
215 function `apply_change_group' will validate and apply the changes.
217 If IN_GROUP is zero, this is a single change. Try to recognize the insn
218 or validate the memory reference with the change applied. If the result
219 is not valid for the machine, suppress the change and return zero.
220 Otherwise, perform the change and return 1. */
223 validate_change_1 (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
, bool unshare
)
227 if (old
== new_rtx
|| rtx_equal_p (old
, new_rtx
))
230 gcc_assert (in_group
!= 0 || num_changes
== 0);
234 /* Save the information describing this change. */
235 if (num_changes
>= changes_allocated
)
237 if (changes_allocated
== 0)
238 /* This value allows for repeated substitutions inside complex
239 indexed addresses, or changes in up to 5 insns. */
240 changes_allocated
= MAX_RECOG_OPERANDS
* 5;
242 changes_allocated
*= 2;
244 changes
= XRESIZEVEC (change_t
, changes
, changes_allocated
);
247 changes
[num_changes
].object
= object
;
248 changes
[num_changes
].loc
= loc
;
249 changes
[num_changes
].old
= old
;
250 changes
[num_changes
].unshare
= unshare
;
252 if (object
&& !MEM_P (object
))
254 /* Set INSN_CODE to force rerecognition of insn. Save old code in
256 changes
[num_changes
].old_code
= INSN_CODE (object
);
257 INSN_CODE (object
) = -1;
262 /* If we are making a group of changes, return 1. Otherwise, validate the
263 change group we made. */
268 return apply_change_group ();
271 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
275 validate_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
277 return validate_change_1 (object
, loc
, new_rtx
, in_group
, false);
280 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting
284 validate_unshare_change (rtx object
, rtx
*loc
, rtx new_rtx
, bool in_group
)
286 return validate_change_1 (object
, loc
, new_rtx
, in_group
, true);
290 /* Keep X canonicalized if some changes have made it non-canonical; only
291 modifies the operands of X, not (for example) its code. Simplifications
292 are not the job of this routine.
294 Return true if anything was changed. */
296 canonicalize_change_group (rtx_insn
*insn
, rtx x
)
298 if (COMMUTATIVE_P (x
)
299 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
301 /* Oops, the caller has made X no longer canonical.
302 Let's redo the changes in the correct order. */
303 rtx tem
= XEXP (x
, 0);
304 validate_unshare_change (insn
, &XEXP (x
, 0), XEXP (x
, 1), 1);
305 validate_unshare_change (insn
, &XEXP (x
, 1), tem
, 1);
313 /* This subroutine of apply_change_group verifies whether the changes to INSN
314 were valid; i.e. whether INSN can still be recognized.
316 If IN_GROUP is true clobbers which have to be added in order to
317 match the instructions will be added to the current change group.
318 Otherwise the changes will take effect immediately. */
321 insn_invalid_p (rtx_insn
*insn
, bool in_group
)
323 rtx pat
= PATTERN (insn
);
324 int num_clobbers
= 0;
325 /* If we are before reload and the pattern is a SET, see if we can add
327 int icode
= recog (pat
, insn
,
328 (GET_CODE (pat
) == SET
329 && ! reload_completed
330 && ! reload_in_progress
)
331 ? &num_clobbers
: 0);
332 int is_asm
= icode
< 0 && asm_noperands (PATTERN (insn
)) >= 0;
335 /* If this is an asm and the operand aren't legal, then fail. Likewise if
336 this is not an asm and the insn wasn't recognized. */
337 if ((is_asm
&& ! check_asm_operands (PATTERN (insn
)))
338 || (!is_asm
&& icode
< 0))
341 /* If we have to add CLOBBERs, fail if we have to add ones that reference
342 hard registers since our callers can't know if they are live or not.
343 Otherwise, add them. */
344 if (num_clobbers
> 0)
348 if (added_clobbers_hard_reg_p (icode
))
351 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_clobbers
+ 1));
352 XVECEXP (newpat
, 0, 0) = pat
;
353 add_clobbers (newpat
, icode
);
355 validate_change (insn
, &PATTERN (insn
), newpat
, 1);
357 PATTERN (insn
) = pat
= newpat
;
360 /* After reload, verify that all constraints are satisfied. */
361 if (reload_completed
)
365 if (! constrain_operands (1, get_preferred_alternatives (insn
)))
369 INSN_CODE (insn
) = icode
;
373 /* Return number of changes made and not validated yet. */
375 num_changes_pending (void)
380 /* Tentatively apply the changes numbered NUM and up.
381 Return 1 if all changes are valid, zero otherwise. */
384 verify_changes (int num
)
387 rtx last_validated
= NULL_RTX
;
389 /* The changes have been applied and all INSN_CODEs have been reset to force
392 The changes are valid if we aren't given an object, or if we are
393 given a MEM and it still is a valid address, or if this is in insn
394 and it is recognized. In the latter case, if reload has completed,
395 we also require that the operands meet the constraints for
398 for (i
= num
; i
< num_changes
; i
++)
400 rtx object
= changes
[i
].object
;
402 /* If there is no object to test or if it is the same as the one we
403 already tested, ignore it. */
404 if (object
== 0 || object
== last_validated
)
409 if (! memory_address_addr_space_p (GET_MODE (object
),
411 MEM_ADDR_SPACE (object
)))
414 else if (/* changes[i].old might be zero, e.g. when putting a
415 REG_FRAME_RELATED_EXPR into a previously empty list. */
417 && REG_P (changes
[i
].old
)
418 && asm_noperands (PATTERN (object
)) > 0
419 && REG_EXPR (changes
[i
].old
) != NULL_TREE
420 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes
[i
].old
))
421 && DECL_REGISTER (REG_EXPR (changes
[i
].old
)))
423 /* Don't allow changes of hard register operands to inline
424 assemblies if they have been defined as register asm ("x"). */
427 else if (DEBUG_INSN_P (object
))
429 else if (insn_invalid_p (as_a
<rtx_insn
*> (object
), true))
431 rtx pat
= PATTERN (object
);
433 /* Perhaps we couldn't recognize the insn because there were
434 extra CLOBBERs at the end. If so, try to re-recognize
435 without the last CLOBBER (later iterations will cause each of
436 them to be eliminated, in turn). But don't do this if we
437 have an ASM_OPERAND. */
438 if (GET_CODE (pat
) == PARALLEL
439 && GET_CODE (XVECEXP (pat
, 0, XVECLEN (pat
, 0) - 1)) == CLOBBER
440 && asm_noperands (PATTERN (object
)) < 0)
444 if (XVECLEN (pat
, 0) == 2)
445 newpat
= XVECEXP (pat
, 0, 0);
451 = gen_rtx_PARALLEL (VOIDmode
,
452 rtvec_alloc (XVECLEN (pat
, 0) - 1));
453 for (j
= 0; j
< XVECLEN (newpat
, 0); j
++)
454 XVECEXP (newpat
, 0, j
) = XVECEXP (pat
, 0, j
);
457 /* Add a new change to this group to replace the pattern
458 with this new pattern. Then consider this change
459 as having succeeded. The change we added will
460 cause the entire call to fail if things remain invalid.
462 Note that this can lose if a later change than the one
463 we are processing specified &XVECEXP (PATTERN (object), 0, X)
464 but this shouldn't occur. */
466 validate_change (object
, &PATTERN (object
), newpat
, 1);
469 else if (GET_CODE (pat
) == USE
|| GET_CODE (pat
) == CLOBBER
470 || GET_CODE (pat
) == VAR_LOCATION
)
471 /* If this insn is a CLOBBER or USE, it is always valid, but is
477 last_validated
= object
;
480 return (i
== num_changes
);
483 /* A group of changes has previously been issued with validate_change
484 and verified with verify_changes. Call df_insn_rescan for each of
485 the insn changed and clear num_changes. */
488 confirm_change_group (void)
491 rtx last_object
= NULL
;
493 for (i
= 0; i
< num_changes
; i
++)
495 rtx object
= changes
[i
].object
;
497 if (changes
[i
].unshare
)
498 *changes
[i
].loc
= copy_rtx (*changes
[i
].loc
);
500 /* Avoid unnecessary rescanning when multiple changes to same instruction
504 if (object
!= last_object
&& last_object
&& INSN_P (last_object
))
505 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
506 last_object
= object
;
510 if (last_object
&& INSN_P (last_object
))
511 df_insn_rescan (as_a
<rtx_insn
*> (last_object
));
515 /* Apply a group of changes previously issued with `validate_change'.
516 If all changes are valid, call confirm_change_group and return 1,
517 otherwise, call cancel_changes and return 0. */
520 apply_change_group (void)
522 if (verify_changes (0))
524 confirm_change_group ();
535 /* Return the number of changes so far in the current group. */
538 num_validated_changes (void)
543 /* Retract the changes numbered NUM and up. */
546 cancel_changes (int num
)
550 /* Back out all the changes. Do this in the opposite order in which
552 for (i
= num_changes
- 1; i
>= num
; i
--)
554 *changes
[i
].loc
= changes
[i
].old
;
555 if (changes
[i
].object
&& !MEM_P (changes
[i
].object
))
556 INSN_CODE (changes
[i
].object
) = changes
[i
].old_code
;
561 /* Reduce conditional compilation elsewhere. */
562 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting
566 simplify_while_replacing (rtx
*loc
, rtx to
, rtx_insn
*object
,
567 machine_mode op0_mode
)
570 enum rtx_code code
= GET_CODE (x
);
571 rtx new_rtx
= NULL_RTX
;
573 if (SWAPPABLE_OPERANDS_P (x
)
574 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
576 validate_unshare_change (object
, loc
,
577 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x
) ? code
578 : swap_condition (code
),
579 GET_MODE (x
), XEXP (x
, 1),
585 /* Canonicalize arithmetics with all constant operands. */
586 switch (GET_RTX_CLASS (code
))
589 if (CONSTANT_P (XEXP (x
, 0)))
590 new_rtx
= simplify_unary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
595 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
596 new_rtx
= simplify_binary_operation (code
, GET_MODE (x
), XEXP (x
, 0),
600 case RTX_COMM_COMPARE
:
601 if (CONSTANT_P (XEXP (x
, 0)) && CONSTANT_P (XEXP (x
, 1)))
602 new_rtx
= simplify_relational_operation (code
, GET_MODE (x
), op0_mode
,
603 XEXP (x
, 0), XEXP (x
, 1));
610 validate_change (object
, loc
, new_rtx
, 1);
617 /* If we have a PLUS whose second operand is now a CONST_INT, use
618 simplify_gen_binary to try to simplify it.
619 ??? We may want later to remove this, once simplification is
620 separated from this function. */
621 if (CONST_INT_P (XEXP (x
, 1)) && XEXP (x
, 1) == to
)
622 validate_change (object
, loc
,
624 (PLUS
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1)), 1);
627 if (CONST_SCALAR_INT_P (XEXP (x
, 1)))
628 validate_change (object
, loc
,
630 (PLUS
, GET_MODE (x
), XEXP (x
, 0),
631 simplify_gen_unary (NEG
,
632 GET_MODE (x
), XEXP (x
, 1),
637 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
639 new_rtx
= simplify_gen_unary (code
, GET_MODE (x
), XEXP (x
, 0),
641 /* If any of the above failed, substitute in something that
642 we know won't be recognized. */
644 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
645 validate_change (object
, loc
, new_rtx
, 1);
649 /* All subregs possible to simplify should be simplified. */
650 new_rtx
= simplify_subreg (GET_MODE (x
), SUBREG_REG (x
), op0_mode
,
653 /* Subregs of VOIDmode operands are incorrect. */
654 if (!new_rtx
&& GET_MODE (SUBREG_REG (x
)) == VOIDmode
)
655 new_rtx
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
657 validate_change (object
, loc
, new_rtx
, 1);
661 /* If we are replacing a register with memory, try to change the memory
662 to be the mode required for memory in extract operations (this isn't
663 likely to be an insertion operation; if it was, nothing bad will
664 happen, we might just fail in some cases). */
666 if (MEM_P (XEXP (x
, 0))
667 && CONST_INT_P (XEXP (x
, 1))
668 && CONST_INT_P (XEXP (x
, 2))
669 && !mode_dependent_address_p (XEXP (XEXP (x
, 0), 0),
670 MEM_ADDR_SPACE (XEXP (x
, 0)))
671 && !MEM_VOLATILE_P (XEXP (x
, 0)))
673 machine_mode wanted_mode
= VOIDmode
;
674 machine_mode is_mode
= GET_MODE (XEXP (x
, 0));
675 int pos
= INTVAL (XEXP (x
, 2));
677 if (GET_CODE (x
) == ZERO_EXTRACT
&& targetm
.have_extzv ())
679 wanted_mode
= insn_data
[targetm
.code_for_extzv
].operand
[1].mode
;
680 if (wanted_mode
== VOIDmode
)
681 wanted_mode
= word_mode
;
683 else if (GET_CODE (x
) == SIGN_EXTRACT
&& targetm
.have_extv ())
685 wanted_mode
= insn_data
[targetm
.code_for_extv
].operand
[1].mode
;
686 if (wanted_mode
== VOIDmode
)
687 wanted_mode
= word_mode
;
690 /* If we have a narrower mode, we can do something. */
691 if (wanted_mode
!= VOIDmode
692 && GET_MODE_SIZE (wanted_mode
) < GET_MODE_SIZE (is_mode
))
694 int offset
= pos
/ BITS_PER_UNIT
;
697 /* If the bytes and bits are counted differently, we
698 must adjust the offset. */
699 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
)
701 (GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (wanted_mode
) -
704 gcc_assert (GET_MODE_PRECISION (wanted_mode
)
705 == GET_MODE_BITSIZE (wanted_mode
));
706 pos
%= GET_MODE_BITSIZE (wanted_mode
);
708 newmem
= adjust_address_nv (XEXP (x
, 0), wanted_mode
, offset
);
710 validate_change (object
, &XEXP (x
, 2), GEN_INT (pos
), 1);
711 validate_change (object
, &XEXP (x
, 0), newmem
, 1);
722 /* Replace every occurrence of FROM in X with TO. Mark each change with
723 validate_change passing OBJECT. */
726 validate_replace_rtx_1 (rtx
*loc
, rtx from
, rtx to
, rtx_insn
*object
,
733 machine_mode op0_mode
= VOIDmode
;
734 int prev_changes
= num_changes
;
740 fmt
= GET_RTX_FORMAT (code
);
742 op0_mode
= GET_MODE (XEXP (x
, 0));
744 /* X matches FROM if it is the same rtx or they are both referring to the
745 same register in the same mode. Avoid calling rtx_equal_p unless the
746 operands look similar. */
749 || (REG_P (x
) && REG_P (from
)
750 && GET_MODE (x
) == GET_MODE (from
)
751 && REGNO (x
) == REGNO (from
))
752 || (GET_CODE (x
) == GET_CODE (from
) && GET_MODE (x
) == GET_MODE (from
)
753 && rtx_equal_p (x
, from
)))
755 validate_unshare_change (object
, loc
, to
, 1);
759 /* Call ourself recursively to perform the replacements.
760 We must not replace inside already replaced expression, otherwise we
761 get infinite recursion for replacements like (reg X)->(subreg (reg X))
762 so we must special case shared ASM_OPERANDS. */
764 if (GET_CODE (x
) == PARALLEL
)
766 for (j
= XVECLEN (x
, 0) - 1; j
>= 0; j
--)
768 if (j
&& GET_CODE (XVECEXP (x
, 0, j
)) == SET
769 && GET_CODE (SET_SRC (XVECEXP (x
, 0, j
))) == ASM_OPERANDS
)
771 /* Verify that operands are really shared. */
772 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x
, 0, 0)))
773 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP
775 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x
, 0, j
)),
776 from
, to
, object
, simplify
);
779 validate_replace_rtx_1 (&XVECEXP (x
, 0, j
), from
, to
, object
,
784 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
787 validate_replace_rtx_1 (&XEXP (x
, i
), from
, to
, object
, simplify
);
788 else if (fmt
[i
] == 'E')
789 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
790 validate_replace_rtx_1 (&XVECEXP (x
, i
, j
), from
, to
, object
,
794 /* If we didn't substitute, there is nothing more to do. */
795 if (num_changes
== prev_changes
)
798 /* ??? The regmove is no more, so is this aberration still necessary? */
799 /* Allow substituted expression to have different mode. This is used by
800 regmove to change mode of pseudo register. */
801 if (fmt
[0] == 'e' && GET_MODE (XEXP (x
, 0)) != VOIDmode
)
802 op0_mode
= GET_MODE (XEXP (x
, 0));
804 /* Do changes needed to keep rtx consistent. Don't do any other
805 simplifications, as it is not our job. */
807 simplify_while_replacing (loc
, to
, object
, op0_mode
);
810 /* Try replacing every occurrence of FROM in subexpression LOC of INSN
811 with TO. After all changes have been made, validate by seeing
812 if INSN is still valid. */
815 validate_replace_rtx_subexp (rtx from
, rtx to
, rtx_insn
*insn
, rtx
*loc
)
817 validate_replace_rtx_1 (loc
, from
, to
, insn
, true);
818 return apply_change_group ();
821 /* Try replacing every occurrence of FROM in INSN with TO. After all
822 changes have been made, validate by seeing if INSN is still valid. */
825 validate_replace_rtx (rtx from
, rtx to
, rtx_insn
*insn
)
827 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
828 return apply_change_group ();
831 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE
832 is a part of INSN. After all changes have been made, validate by seeing if
834 validate_replace_rtx (from, to, insn) is equivalent to
835 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */
838 validate_replace_rtx_part (rtx from
, rtx to
, rtx
*where
, rtx_insn
*insn
)
840 validate_replace_rtx_1 (where
, from
, to
, insn
, true);
841 return apply_change_group ();
844 /* Same as above, but do not simplify rtx afterwards. */
846 validate_replace_rtx_part_nosimplify (rtx from
, rtx to
, rtx
*where
,
849 validate_replace_rtx_1 (where
, from
, to
, insn
, false);
850 return apply_change_group ();
854 /* Try replacing every occurrence of FROM in INSN with TO. This also
855 will replace in REG_EQUAL and REG_EQUIV notes. */
858 validate_replace_rtx_group (rtx from
, rtx to
, rtx_insn
*insn
)
861 validate_replace_rtx_1 (&PATTERN (insn
), from
, to
, insn
, true);
862 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
863 if (REG_NOTE_KIND (note
) == REG_EQUAL
864 || REG_NOTE_KIND (note
) == REG_EQUIV
)
865 validate_replace_rtx_1 (&XEXP (note
, 0), from
, to
, insn
, true);
868 /* Function called by note_uses to replace used subexpressions. */
869 struct validate_replace_src_data
871 rtx from
; /* Old RTX */
872 rtx to
; /* New RTX */
873 rtx_insn
*insn
; /* Insn in which substitution is occurring. */
877 validate_replace_src_1 (rtx
*x
, void *data
)
879 struct validate_replace_src_data
*d
880 = (struct validate_replace_src_data
*) data
;
882 validate_replace_rtx_1 (x
, d
->from
, d
->to
, d
->insn
, true);
885 /* Try replacing every occurrence of FROM in INSN with TO, avoiding
889 validate_replace_src_group (rtx from
, rtx to
, rtx_insn
*insn
)
891 struct validate_replace_src_data d
;
896 note_uses (&PATTERN (insn
), validate_replace_src_1
, &d
);
899 /* Try simplify INSN.
900 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's
901 pattern and return true if something was simplified. */
904 validate_simplify_insn (rtx_insn
*insn
)
910 pat
= PATTERN (insn
);
912 if (GET_CODE (pat
) == SET
)
914 newpat
= simplify_rtx (SET_SRC (pat
));
915 if (newpat
&& !rtx_equal_p (SET_SRC (pat
), newpat
))
916 validate_change (insn
, &SET_SRC (pat
), newpat
, 1);
917 newpat
= simplify_rtx (SET_DEST (pat
));
918 if (newpat
&& !rtx_equal_p (SET_DEST (pat
), newpat
))
919 validate_change (insn
, &SET_DEST (pat
), newpat
, 1);
921 else if (GET_CODE (pat
) == PARALLEL
)
922 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
924 rtx s
= XVECEXP (pat
, 0, i
);
926 if (GET_CODE (XVECEXP (pat
, 0, i
)) == SET
)
928 newpat
= simplify_rtx (SET_SRC (s
));
929 if (newpat
&& !rtx_equal_p (SET_SRC (s
), newpat
))
930 validate_change (insn
, &SET_SRC (s
), newpat
, 1);
931 newpat
= simplify_rtx (SET_DEST (s
));
932 if (newpat
&& !rtx_equal_p (SET_DEST (s
), newpat
))
933 validate_change (insn
, &SET_DEST (s
), newpat
, 1);
936 return ((num_changes_pending () > 0) && (apply_change_group () > 0));
939 /* Return 1 if the insn using CC0 set by INSN does not contain
940 any ordered tests applied to the condition codes.
941 EQ and NE tests do not count. */
944 next_insn_tests_no_inequality (rtx_insn
*insn
)
946 rtx_insn
*next
= next_cc0_user (insn
);
948 /* If there is no next insn, we have to take the conservative choice. */
952 return (INSN_P (next
)
953 && ! inequality_comparisons_p (PATTERN (next
)));
956 /* Return 1 if OP is a valid general operand for machine mode MODE.
957 This is either a register reference, a memory reference,
958 or a constant. In the case of a memory reference, the address
959 is checked for general validity for the target machine.
961 Register and memory references must have mode MODE in order to be valid,
962 but some constants have no machine mode and are valid for any mode.
964 If MODE is VOIDmode, OP is checked for validity for whatever mode
967 The main use of this function is as a predicate in match_operand
968 expressions in the machine description. */
971 general_operand (rtx op
, machine_mode mode
)
973 enum rtx_code code
= GET_CODE (op
);
975 if (mode
== VOIDmode
)
976 mode
= GET_MODE (op
);
978 /* Don't accept CONST_INT or anything similar
979 if the caller wants something floating. */
980 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
981 && GET_MODE_CLASS (mode
) != MODE_INT
982 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
987 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
991 return ((GET_MODE (op
) == VOIDmode
|| GET_MODE (op
) == mode
993 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
994 && targetm
.legitimate_constant_p (mode
== VOIDmode
998 /* Except for certain constants with VOIDmode, already checked for,
999 OP's mode must match MODE if MODE specifies a mode. */
1001 if (GET_MODE (op
) != mode
)
1006 rtx sub
= SUBREG_REG (op
);
1008 #ifdef INSN_SCHEDULING
1009 /* On machines that have insn scheduling, we want all memory
1010 reference to be explicit, so outlaw paradoxical SUBREGs.
1011 However, we must allow them after reload so that they can
1012 get cleaned up by cleanup_subreg_operands. */
1013 if (!reload_completed
&& MEM_P (sub
)
1014 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (sub
)))
1017 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory
1018 may result in incorrect reference. We should simplify all valid
1019 subregs of MEM anyway. But allow this after reload because we
1020 might be called from cleanup_subreg_operands.
1022 ??? This is a kludge. */
1023 if (!reload_completed
&& SUBREG_BYTE (op
) != 0
1027 #ifdef CANNOT_CHANGE_MODE_CLASS
1029 && REGNO (sub
) < FIRST_PSEUDO_REGISTER
1030 && REG_CANNOT_CHANGE_MODE_P (REGNO (sub
), GET_MODE (sub
), mode
)
1031 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_INT
1032 && GET_MODE_CLASS (GET_MODE (sub
)) != MODE_COMPLEX_FLOAT
1033 /* LRA can generate some invalid SUBREGS just for matched
1034 operand reload presentation. LRA needs to treat them as
1036 && ! LRA_SUBREG_P (op
))
1040 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally
1041 create such rtl, and we must reject it. */
1042 if (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1043 /* LRA can use subreg to store a floating point value in an
1044 integer mode. Although the floating point and the
1045 integer modes need the same number of hard registers, the
1046 size of floating point mode can be less than the integer
1048 && ! lra_in_progress
1049 && GET_MODE_SIZE (GET_MODE (op
)) > GET_MODE_SIZE (GET_MODE (sub
)))
1053 code
= GET_CODE (op
);
1057 return (REGNO (op
) >= FIRST_PSEUDO_REGISTER
1058 || in_hard_reg_set_p (operand_reg_set
, GET_MODE (op
), REGNO (op
)));
1062 rtx y
= XEXP (op
, 0);
1064 if (! volatile_ok
&& MEM_VOLATILE_P (op
))
1067 /* Use the mem's mode, since it will be reloaded thus. LRA can
1068 generate move insn with invalid addresses which is made valid
1069 and efficiently calculated by LRA through further numerous
1072 || memory_address_addr_space_p (GET_MODE (op
), y
, MEM_ADDR_SPACE (op
)))
1079 /* Return 1 if OP is a valid memory address for a memory reference
1082 The main use of this function is as a predicate in match_operand
1083 expressions in the machine description. */
1086 address_operand (rtx op
, machine_mode mode
)
1088 return memory_address_p (mode
, op
);
1091 /* Return 1 if OP is a register reference of mode MODE.
1092 If MODE is VOIDmode, accept a register in any mode.
1094 The main use of this function is as a predicate in match_operand
1095 expressions in the machine description. */
1098 register_operand (rtx op
, machine_mode mode
)
1100 if (GET_CODE (op
) == SUBREG
)
1102 rtx sub
= SUBREG_REG (op
);
1104 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand
1105 because it is guaranteed to be reloaded into one.
1106 Just make sure the MEM is valid in itself.
1107 (Ideally, (SUBREG (MEM)...) should not exist after reload,
1108 but currently it does result from (SUBREG (REG)...) where the
1109 reg went on the stack.) */
1110 if (!REG_P (sub
) && (reload_completed
|| !MEM_P (sub
)))
1113 else if (!REG_P (op
))
1115 return general_operand (op
, mode
);
1118 /* Return 1 for a register in Pmode; ignore the tested mode. */
1121 pmode_register_operand (rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1123 return register_operand (op
, Pmode
);
1126 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH
1127 or a hard register. */
1130 scratch_operand (rtx op
, machine_mode mode
)
1132 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
1135 return (GET_CODE (op
) == SCRATCH
1138 || (REGNO (op
) < FIRST_PSEUDO_REGISTER
1139 && REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
))));
1142 /* Return 1 if OP is a valid immediate operand for mode MODE.
1144 The main use of this function is as a predicate in match_operand
1145 expressions in the machine description. */
1148 immediate_operand (rtx op
, machine_mode mode
)
1150 /* Don't accept CONST_INT or anything similar
1151 if the caller wants something floating. */
1152 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1153 && GET_MODE_CLASS (mode
) != MODE_INT
1154 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1157 if (CONST_INT_P (op
)
1159 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1162 return (CONSTANT_P (op
)
1163 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
1164 || GET_MODE (op
) == VOIDmode
)
1165 && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (op
))
1166 && targetm
.legitimate_constant_p (mode
== VOIDmode
1171 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */
1174 const_int_operand (rtx op
, machine_mode mode
)
1176 if (!CONST_INT_P (op
))
1179 if (mode
!= VOIDmode
1180 && trunc_int_for_mode (INTVAL (op
), mode
) != INTVAL (op
))
1186 #if TARGET_SUPPORTS_WIDE_INT
1187 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT
1190 const_scalar_int_operand (rtx op
, machine_mode mode
)
1192 if (!CONST_SCALAR_INT_P (op
))
1195 if (CONST_INT_P (op
))
1196 return const_int_operand (op
, mode
);
1198 if (mode
!= VOIDmode
)
1200 int prec
= GET_MODE_PRECISION (mode
);
1201 int bitsize
= GET_MODE_BITSIZE (mode
);
1203 if (CONST_WIDE_INT_NUNITS (op
) * HOST_BITS_PER_WIDE_INT
> bitsize
)
1206 if (prec
== bitsize
)
1210 /* Multiword partial int. */
1212 = CONST_WIDE_INT_ELT (op
, CONST_WIDE_INT_NUNITS (op
) - 1);
1213 return (sext_hwi (x
, prec
& (HOST_BITS_PER_WIDE_INT
- 1)) == x
);
1219 /* Returns 1 if OP is an operand that is a constant integer or constant
1220 floating-point number of MODE. */
1223 const_double_operand (rtx op
, machine_mode mode
)
1225 return (GET_CODE (op
) == CONST_DOUBLE
)
1226 && (GET_MODE (op
) == mode
|| mode
== VOIDmode
);
1229 /* Returns 1 if OP is an operand that is a constant integer or constant
1230 floating-point number of MODE. */
1233 const_double_operand (rtx op
, machine_mode mode
)
1235 /* Don't accept CONST_INT or anything similar
1236 if the caller wants something floating. */
1237 if (GET_MODE (op
) == VOIDmode
&& mode
!= VOIDmode
1238 && GET_MODE_CLASS (mode
) != MODE_INT
1239 && GET_MODE_CLASS (mode
) != MODE_PARTIAL_INT
)
1242 return ((CONST_DOUBLE_P (op
) || CONST_INT_P (op
))
1243 && (mode
== VOIDmode
|| GET_MODE (op
) == mode
1244 || GET_MODE (op
) == VOIDmode
));
1247 /* Return 1 if OP is a general operand that is not an immediate
1248 operand of mode MODE. */
1251 nonimmediate_operand (rtx op
, machine_mode mode
)
1253 return (general_operand (op
, mode
) && ! CONSTANT_P (op
));
1256 /* Return 1 if OP is a register reference or immediate value of mode MODE. */
1259 nonmemory_operand (rtx op
, machine_mode mode
)
1261 if (CONSTANT_P (op
))
1262 return immediate_operand (op
, mode
);
1263 return register_operand (op
, mode
);
1266 /* Return 1 if OP is a valid operand that stands for pushing a
1267 value of mode MODE onto the stack.
1269 The main use of this function is as a predicate in match_operand
1270 expressions in the machine description. */
1273 push_operand (rtx op
, machine_mode mode
)
1275 unsigned int rounded_size
= GET_MODE_SIZE (mode
);
1277 #ifdef PUSH_ROUNDING
1278 rounded_size
= PUSH_ROUNDING (rounded_size
);
1284 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1289 if (rounded_size
== GET_MODE_SIZE (mode
))
1291 if (GET_CODE (op
) != STACK_PUSH_CODE
)
1296 if (GET_CODE (op
) != PRE_MODIFY
1297 || GET_CODE (XEXP (op
, 1)) != PLUS
1298 || XEXP (XEXP (op
, 1), 0) != XEXP (op
, 0)
1299 || !CONST_INT_P (XEXP (XEXP (op
, 1), 1))
1300 || INTVAL (XEXP (XEXP (op
, 1), 1))
1301 != ((STACK_GROWS_DOWNWARD
? -1 : 1) * (int) rounded_size
))
1305 return XEXP (op
, 0) == stack_pointer_rtx
;
1308 /* Return 1 if OP is a valid operand that stands for popping a
1309 value of mode MODE off the stack.
1311 The main use of this function is as a predicate in match_operand
1312 expressions in the machine description. */
1315 pop_operand (rtx op
, machine_mode mode
)
1320 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1325 if (GET_CODE (op
) != STACK_POP_CODE
)
1328 return XEXP (op
, 0) == stack_pointer_rtx
;
1331 /* Return 1 if ADDR is a valid memory address
1332 for mode MODE in address space AS. */
1335 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED
,
1336 rtx addr
, addr_space_t as
)
1338 #ifdef GO_IF_LEGITIMATE_ADDRESS
1339 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
1340 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
1346 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
1350 /* Return 1 if OP is a valid memory reference with mode MODE,
1351 including a valid address.
1353 The main use of this function is as a predicate in match_operand
1354 expressions in the machine description. */
1357 memory_operand (rtx op
, machine_mode mode
)
1361 if (! reload_completed
)
1362 /* Note that no SUBREG is a memory operand before end of reload pass,
1363 because (SUBREG (MEM...)) forces reloading into a register. */
1364 return MEM_P (op
) && general_operand (op
, mode
);
1366 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1370 if (GET_CODE (inner
) == SUBREG
)
1371 inner
= SUBREG_REG (inner
);
1373 return (MEM_P (inner
) && general_operand (op
, mode
));
1376 /* Return 1 if OP is a valid indirect memory reference with mode MODE;
1377 that is, a memory reference whose address is a general_operand. */
1380 indirect_operand (rtx op
, machine_mode mode
)
1382 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
1383 if (! reload_completed
1384 && GET_CODE (op
) == SUBREG
&& MEM_P (SUBREG_REG (op
)))
1386 int offset
= SUBREG_BYTE (op
);
1387 rtx inner
= SUBREG_REG (op
);
1389 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1392 /* The only way that we can have a general_operand as the resulting
1393 address is if OFFSET is zero and the address already is an operand
1394 or if the address is (plus Y (const_int -OFFSET)) and Y is an
1397 return ((offset
== 0 && general_operand (XEXP (inner
, 0), Pmode
))
1398 || (GET_CODE (XEXP (inner
, 0)) == PLUS
1399 && CONST_INT_P (XEXP (XEXP (inner
, 0), 1))
1400 && INTVAL (XEXP (XEXP (inner
, 0), 1)) == -offset
1401 && general_operand (XEXP (XEXP (inner
, 0), 0), Pmode
)));
1405 && memory_operand (op
, mode
)
1406 && general_operand (XEXP (op
, 0), Pmode
));
1409 /* Return 1 if this is an ordered comparison operator (not including
1410 ORDERED and UNORDERED). */
1413 ordered_comparison_operator (rtx op
, machine_mode mode
)
1415 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
1417 switch (GET_CODE (op
))
1435 /* Return 1 if this is a comparison operator. This allows the use of
1436 MATCH_OPERATOR to recognize all the branch insns. */
1439 comparison_operator (rtx op
, machine_mode mode
)
1441 return ((mode
== VOIDmode
|| GET_MODE (op
) == mode
)
1442 && COMPARISON_P (op
));
1445 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */
1448 extract_asm_operands (rtx body
)
1451 switch (GET_CODE (body
))
1457 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */
1458 tmp
= SET_SRC (body
);
1459 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1464 tmp
= XVECEXP (body
, 0, 0);
1465 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1467 if (GET_CODE (tmp
) == SET
)
1469 tmp
= SET_SRC (tmp
);
1470 if (GET_CODE (tmp
) == ASM_OPERANDS
)
1481 /* If BODY is an insn body that uses ASM_OPERANDS,
1482 return the number of operands (both input and output) in the insn.
1483 Otherwise return -1. */
1486 asm_noperands (const_rtx body
)
1488 rtx asm_op
= extract_asm_operands (CONST_CAST_RTX (body
));
1494 if (GET_CODE (body
) == SET
)
1496 else if (GET_CODE (body
) == PARALLEL
)
1499 if (GET_CODE (XVECEXP (body
, 0, 0)) == SET
)
1501 /* Multiple output operands, or 1 output plus some clobbers:
1503 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */
1504 /* Count backwards through CLOBBERs to determine number of SETs. */
1505 for (i
= XVECLEN (body
, 0); i
> 0; i
--)
1507 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) == SET
)
1509 if (GET_CODE (XVECEXP (body
, 0, i
- 1)) != CLOBBER
)
1513 /* N_SETS is now number of output operands. */
1516 /* Verify that all the SETs we have
1517 came from a single original asm_operands insn
1518 (so that invalid combinations are blocked). */
1519 for (i
= 0; i
< n_sets
; i
++)
1521 rtx elt
= XVECEXP (body
, 0, i
);
1522 if (GET_CODE (elt
) != SET
)
1524 if (GET_CODE (SET_SRC (elt
)) != ASM_OPERANDS
)
1526 /* If these ASM_OPERANDS rtx's came from different original insns
1527 then they aren't allowed together. */
1528 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt
))
1529 != ASM_OPERANDS_INPUT_VEC (asm_op
))
1535 /* 0 outputs, but some clobbers:
1536 body is [(asm_operands ...) (clobber (reg ...))...]. */
1537 /* Make sure all the other parallel things really are clobbers. */
1538 for (i
= XVECLEN (body
, 0) - 1; i
> 0; i
--)
1539 if (GET_CODE (XVECEXP (body
, 0, i
)) != CLOBBER
)
1544 return (ASM_OPERANDS_INPUT_LENGTH (asm_op
)
1545 + ASM_OPERANDS_LABEL_LENGTH (asm_op
) + n_sets
);
1548 /* Assuming BODY is an insn body that uses ASM_OPERANDS,
1549 copy its operands (both input and output) into the vector OPERANDS,
1550 the locations of the operands within the insn into the vector OPERAND_LOCS,
1551 and the constraints for the operands into CONSTRAINTS.
1552 Write the modes of the operands into MODES.
1553 Return the assembler-template.
1555 If MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0,
1556 we don't store that info. */
1559 decode_asm_operands (rtx body
, rtx
*operands
, rtx
**operand_locs
,
1560 const char **constraints
, machine_mode
*modes
,
1563 int nbase
= 0, n
, i
;
1566 switch (GET_CODE (body
))
1569 /* Zero output asm: BODY is (asm_operands ...). */
1574 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */
1575 asmop
= SET_SRC (body
);
1577 /* The output is in the SET.
1578 Its constraint is in the ASM_OPERANDS itself. */
1580 operands
[0] = SET_DEST (body
);
1582 operand_locs
[0] = &SET_DEST (body
);
1584 constraints
[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop
);
1586 modes
[0] = GET_MODE (SET_DEST (body
));
1592 int nparallel
= XVECLEN (body
, 0); /* Includes CLOBBERs. */
1594 asmop
= XVECEXP (body
, 0, 0);
1595 if (GET_CODE (asmop
) == SET
)
1597 asmop
= SET_SRC (asmop
);
1599 /* At least one output, plus some CLOBBERs. The outputs are in
1600 the SETs. Their constraints are in the ASM_OPERANDS itself. */
1601 for (i
= 0; i
< nparallel
; i
++)
1603 if (GET_CODE (XVECEXP (body
, 0, i
)) == CLOBBER
)
1604 break; /* Past last SET */
1606 operands
[i
] = SET_DEST (XVECEXP (body
, 0, i
));
1608 operand_locs
[i
] = &SET_DEST (XVECEXP (body
, 0, i
));
1610 constraints
[i
] = XSTR (SET_SRC (XVECEXP (body
, 0, i
)), 1);
1612 modes
[i
] = GET_MODE (SET_DEST (XVECEXP (body
, 0, i
)));
1623 n
= ASM_OPERANDS_INPUT_LENGTH (asmop
);
1624 for (i
= 0; i
< n
; i
++)
1627 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_INPUT (asmop
, i
);
1629 operands
[nbase
+ i
] = ASM_OPERANDS_INPUT (asmop
, i
);
1631 constraints
[nbase
+ i
] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop
, i
);
1633 modes
[nbase
+ i
] = ASM_OPERANDS_INPUT_MODE (asmop
, i
);
1637 n
= ASM_OPERANDS_LABEL_LENGTH (asmop
);
1638 for (i
= 0; i
< n
; i
++)
1641 operand_locs
[nbase
+ i
] = &ASM_OPERANDS_LABEL (asmop
, i
);
1643 operands
[nbase
+ i
] = ASM_OPERANDS_LABEL (asmop
, i
);
1645 constraints
[nbase
+ i
] = "";
1647 modes
[nbase
+ i
] = Pmode
;
1651 *loc
= ASM_OPERANDS_SOURCE_LOCATION (asmop
);
1653 return ASM_OPERANDS_TEMPLATE (asmop
);
1656 /* Parse inline assembly string STRING and determine which operands are
1657 referenced by % markers. For the first NOPERANDS operands, set USED[I]
1658 to true if operand I is referenced.
1660 This is intended to distinguish barrier-like asms such as:
1662 asm ("" : "=m" (...));
1664 from real references such as:
1666 asm ("sw\t$0, %0" : "=m" (...)); */
1669 get_referenced_operands (const char *string
, bool *used
,
1670 unsigned int noperands
)
1672 memset (used
, 0, sizeof (bool) * noperands
);
1673 const char *p
= string
;
1679 /* A letter followed by a digit indicates an operand number. */
1680 if (ISALPHA (p
[0]) && ISDIGIT (p
[1]))
1685 unsigned long opnum
= strtoul (p
, &endptr
, 10);
1686 if (endptr
!= p
&& opnum
< noperands
)
1700 /* Check if an asm_operand matches its constraints.
1701 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */
1704 asm_operand_ok (rtx op
, const char *constraint
, const char **constraints
)
1707 bool incdec_ok
= false;
1709 /* Use constrain_operands after reload. */
1710 gcc_assert (!reload_completed
);
1712 /* Empty constraint string is the same as "X,...,X", i.e. X for as
1713 many alternatives as required to match the other operands. */
1714 if (*constraint
== '\0')
1719 enum constraint_num cn
;
1720 char c
= *constraint
;
1728 case '0': case '1': case '2': case '3': case '4':
1729 case '5': case '6': case '7': case '8': case '9':
1730 /* If caller provided constraints pointer, look up
1731 the matching constraint. Otherwise, our caller should have
1732 given us the proper matching constraint, but we can't
1733 actually fail the check if they didn't. Indicate that
1734 results are inconclusive. */
1738 unsigned long match
;
1740 match
= strtoul (constraint
, &end
, 10);
1742 result
= asm_operand_ok (op
, constraints
[match
], NULL
);
1743 constraint
= (const char *) end
;
1749 while (ISDIGIT (*constraint
));
1755 /* The rest of the compiler assumes that reloading the address
1756 of a MEM into a register will make it fit an 'o' constraint.
1757 That is, if it sees a MEM operand for an 'o' constraint,
1758 it assumes that (mem (base-reg)) will fit.
1760 That assumption fails on targets that don't have offsettable
1761 addresses at all. We therefore need to treat 'o' asm
1762 constraints as a special case and only accept operands that
1763 are already offsettable, thus proving that at least one
1764 offsettable address exists. */
1765 case 'o': /* offsettable */
1766 if (offsettable_nonstrict_memref_p (op
))
1771 if (general_operand (op
, VOIDmode
))
1777 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed
1778 to exist, excepting those that expand_call created. Further,
1779 on some machines which do not have generalized auto inc/dec,
1780 an inc/dec is not a memory_operand.
1782 Match any memory and hope things are resolved after reload. */
1785 cn
= lookup_constraint (constraint
);
1786 switch (get_constraint_type (cn
))
1790 && reg_class_for_constraint (cn
) != NO_REGS
1791 && GET_MODE (op
) != BLKmode
1792 && register_operand (op
, VOIDmode
))
1799 && insn_const_int_ok_for_constraint (INTVAL (op
), cn
))
1804 /* Every memory operand can be reloaded to fit. */
1805 result
= result
|| memory_operand (op
, VOIDmode
);
1809 /* Every address operand can be reloaded to fit. */
1810 result
= result
|| address_operand (op
, VOIDmode
);
1814 result
= result
|| constraint_satisfied_p (op
, cn
);
1819 len
= CONSTRAINT_LEN (c
, constraint
);
1822 while (--len
&& *constraint
);
1827 /* For operands without < or > constraints reject side-effects. */
1828 if (AUTO_INC_DEC
&& !incdec_ok
&& result
&& MEM_P (op
))
1829 switch (GET_CODE (XEXP (op
, 0)))
1845 /* Given an rtx *P, if it is a sum containing an integer constant term,
1846 return the location (type rtx *) of the pointer to that constant term.
1847 Otherwise, return a null pointer. */
1850 find_constant_term_loc (rtx
*p
)
1853 enum rtx_code code
= GET_CODE (*p
);
1855 /* If *P IS such a constant term, P is its location. */
1857 if (code
== CONST_INT
|| code
== SYMBOL_REF
|| code
== LABEL_REF
1861 /* Otherwise, if not a sum, it has no constant term. */
1863 if (GET_CODE (*p
) != PLUS
)
1866 /* If one of the summands is constant, return its location. */
1868 if (XEXP (*p
, 0) && CONSTANT_P (XEXP (*p
, 0))
1869 && XEXP (*p
, 1) && CONSTANT_P (XEXP (*p
, 1)))
1872 /* Otherwise, check each summand for containing a constant term. */
1874 if (XEXP (*p
, 0) != 0)
1876 tem
= find_constant_term_loc (&XEXP (*p
, 0));
1881 if (XEXP (*p
, 1) != 0)
1883 tem
= find_constant_term_loc (&XEXP (*p
, 1));
1891 /* Return 1 if OP is a memory reference
1892 whose address contains no side effects
1893 and remains valid after the addition
1894 of a positive integer less than the
1895 size of the object being referenced.
1897 We assume that the original address is valid and do not check it.
1899 This uses strict_memory_address_p as a subroutine, so
1900 don't use it before reload. */
1903 offsettable_memref_p (rtx op
)
1905 return ((MEM_P (op
))
1906 && offsettable_address_addr_space_p (1, GET_MODE (op
), XEXP (op
, 0),
1907 MEM_ADDR_SPACE (op
)));
1910 /* Similar, but don't require a strictly valid mem ref:
1911 consider pseudo-regs valid as index or base regs. */
1914 offsettable_nonstrict_memref_p (rtx op
)
1916 return ((MEM_P (op
))
1917 && offsettable_address_addr_space_p (0, GET_MODE (op
), XEXP (op
, 0),
1918 MEM_ADDR_SPACE (op
)));
1921 /* Return 1 if Y is a memory address which contains no side effects
1922 and would remain valid for address space AS after the addition of
1923 a positive integer less than the size of that mode.
1925 We assume that the original address is valid and do not check it.
1926 We do check that it is valid for narrower modes.
1928 If STRICTP is nonzero, we require a strictly valid address,
1929 for the sake of use in reload.c. */
1932 offsettable_address_addr_space_p (int strictp
, machine_mode mode
, rtx y
,
1935 enum rtx_code ycode
= GET_CODE (y
);
1939 int (*addressp
) (machine_mode
, rtx
, addr_space_t
) =
1940 (strictp
? strict_memory_address_addr_space_p
1941 : memory_address_addr_space_p
);
1942 unsigned int mode_sz
= GET_MODE_SIZE (mode
);
1944 if (CONSTANT_ADDRESS_P (y
))
1947 /* Adjusting an offsettable address involves changing to a narrower mode.
1948 Make sure that's OK. */
1950 if (mode_dependent_address_p (y
, as
))
1953 machine_mode address_mode
= GET_MODE (y
);
1954 if (address_mode
== VOIDmode
)
1955 address_mode
= targetm
.addr_space
.address_mode (as
);
1956 #ifdef POINTERS_EXTEND_UNSIGNED
1957 machine_mode pointer_mode
= targetm
.addr_space
.pointer_mode (as
);
1960 /* ??? How much offset does an offsettable BLKmode reference need?
1961 Clearly that depends on the situation in which it's being used.
1962 However, the current situation in which we test 0xffffffff is
1963 less than ideal. Caveat user. */
1965 mode_sz
= BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
;
1967 /* If the expression contains a constant term,
1968 see if it remains valid when max possible offset is added. */
1970 if ((ycode
== PLUS
) && (y2
= find_constant_term_loc (&y1
)))
1975 *y2
= plus_constant (address_mode
, *y2
, mode_sz
- 1);
1976 /* Use QImode because an odd displacement may be automatically invalid
1977 for any wider mode. But it should be valid for a single byte. */
1978 good
= (*addressp
) (QImode
, y
, as
);
1980 /* In any case, restore old contents of memory. */
1985 if (GET_RTX_CLASS (ycode
) == RTX_AUTOINC
)
1988 /* The offset added here is chosen as the maximum offset that
1989 any instruction could need to add when operating on something
1990 of the specified mode. We assume that if Y and Y+c are
1991 valid addresses then so is Y+d for all 0<d<c. adjust_address will
1992 go inside a LO_SUM here, so we do so as well. */
1993 if (GET_CODE (y
) == LO_SUM
1995 && mode_sz
<= GET_MODE_ALIGNMENT (mode
) / BITS_PER_UNIT
)
1996 z
= gen_rtx_LO_SUM (address_mode
, XEXP (y
, 0),
1997 plus_constant (address_mode
, XEXP (y
, 1),
1999 #ifdef POINTERS_EXTEND_UNSIGNED
2000 /* Likewise for a ZERO_EXTEND from pointer_mode. */
2001 else if (POINTERS_EXTEND_UNSIGNED
> 0
2002 && GET_CODE (y
) == ZERO_EXTEND
2003 && GET_MODE (XEXP (y
, 0)) == pointer_mode
)
2004 z
= gen_rtx_ZERO_EXTEND (address_mode
,
2005 plus_constant (pointer_mode
, XEXP (y
, 0),
2009 z
= plus_constant (address_mode
, y
, mode_sz
- 1);
2011 /* Use QImode because an odd displacement may be automatically invalid
2012 for any wider mode. But it should be valid for a single byte. */
2013 return (*addressp
) (QImode
, z
, as
);
2016 /* Return 1 if ADDR is an address-expression whose effect depends
2017 on the mode of the memory reference it is used in.
2019 ADDRSPACE is the address space associated with the address.
2021 Autoincrement addressing is a typical example of mode-dependence
2022 because the amount of the increment depends on the mode. */
2025 mode_dependent_address_p (rtx addr
, addr_space_t addrspace
)
2027 /* Auto-increment addressing with anything other than post_modify
2028 or pre_modify always introduces a mode dependency. Catch such
2029 cases now instead of deferring to the target. */
2030 if (GET_CODE (addr
) == PRE_INC
2031 || GET_CODE (addr
) == POST_INC
2032 || GET_CODE (addr
) == PRE_DEC
2033 || GET_CODE (addr
) == POST_DEC
)
2036 return targetm
.mode_dependent_address_p (addr
, addrspace
);
2039 /* Return true if boolean attribute ATTR is supported. */
2042 have_bool_attr (bool_attr attr
)
2047 return HAVE_ATTR_enabled
;
2048 case BA_PREFERRED_FOR_SIZE
:
2049 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_size
;
2050 case BA_PREFERRED_FOR_SPEED
:
2051 return HAVE_ATTR_enabled
|| HAVE_ATTR_preferred_for_speed
;
2056 /* Return the value of ATTR for instruction INSN. */
2059 get_bool_attr (rtx_insn
*insn
, bool_attr attr
)
2064 return get_attr_enabled (insn
);
2065 case BA_PREFERRED_FOR_SIZE
:
2066 return get_attr_enabled (insn
) && get_attr_preferred_for_size (insn
);
2067 case BA_PREFERRED_FOR_SPEED
:
2068 return get_attr_enabled (insn
) && get_attr_preferred_for_speed (insn
);
2073 /* Like get_bool_attr_mask, but don't use the cache. */
2075 static alternative_mask
2076 get_bool_attr_mask_uncached (rtx_insn
*insn
, bool_attr attr
)
2078 /* Temporarily install enough information for get_attr_<foo> to assume
2079 that the insn operands are already cached. As above, the attribute
2080 mustn't depend on the values of operands, so we don't provide their
2081 real values here. */
2082 rtx_insn
*old_insn
= recog_data
.insn
;
2083 int old_alternative
= which_alternative
;
2085 recog_data
.insn
= insn
;
2086 alternative_mask mask
= ALL_ALTERNATIVES
;
2087 int n_alternatives
= insn_data
[INSN_CODE (insn
)].n_alternatives
;
2088 for (int i
= 0; i
< n_alternatives
; i
++)
2090 which_alternative
= i
;
2091 if (!get_bool_attr (insn
, attr
))
2092 mask
&= ~ALTERNATIVE_BIT (i
);
2095 recog_data
.insn
= old_insn
;
2096 which_alternative
= old_alternative
;
2100 /* Return the mask of operand alternatives that are allowed for INSN
2101 by boolean attribute ATTR. This mask depends only on INSN and on
2102 the current target; it does not depend on things like the values of
2105 static alternative_mask
2106 get_bool_attr_mask (rtx_insn
*insn
, bool_attr attr
)
2108 /* Quick exit for asms and for targets that don't use these attributes. */
2109 int code
= INSN_CODE (insn
);
2110 if (code
< 0 || !have_bool_attr (attr
))
2111 return ALL_ALTERNATIVES
;
2113 /* Calling get_attr_<foo> can be expensive, so cache the mask
2115 if (!this_target_recog
->x_bool_attr_masks
[code
][attr
])
2116 this_target_recog
->x_bool_attr_masks
[code
][attr
]
2117 = get_bool_attr_mask_uncached (insn
, attr
);
2118 return this_target_recog
->x_bool_attr_masks
[code
][attr
];
2121 /* Return the set of alternatives of INSN that are allowed by the current
2125 get_enabled_alternatives (rtx_insn
*insn
)
2127 return get_bool_attr_mask (insn
, BA_ENABLED
);
2130 /* Return the set of alternatives of INSN that are allowed by the current
2131 target and are preferred for the current size/speed optimization
2135 get_preferred_alternatives (rtx_insn
*insn
)
2137 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
)))
2138 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2140 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2143 /* Return the set of alternatives of INSN that are allowed by the current
2144 target and are preferred for the size/speed optimization choice
2145 associated with BB. Passing a separate BB is useful if INSN has not
2146 been emitted yet or if we are considering moving it to a different
2150 get_preferred_alternatives (rtx_insn
*insn
, basic_block bb
)
2152 if (optimize_bb_for_speed_p (bb
))
2153 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SPEED
);
2155 return get_bool_attr_mask (insn
, BA_PREFERRED_FOR_SIZE
);
2158 /* Assert that the cached boolean attributes for INSN are still accurate.
2159 The backend is required to define these attributes in a way that only
2160 depends on the current target (rather than operands, compiler phase,
2164 check_bool_attrs (rtx_insn
*insn
)
2166 int code
= INSN_CODE (insn
);
2168 for (int i
= 0; i
<= BA_LAST
; ++i
)
2170 enum bool_attr attr
= (enum bool_attr
) i
;
2171 if (this_target_recog
->x_bool_attr_masks
[code
][attr
])
2172 gcc_assert (this_target_recog
->x_bool_attr_masks
[code
][attr
]
2173 == get_bool_attr_mask_uncached (insn
, attr
));
2178 /* Like extract_insn, but save insn extracted and don't extract again, when
2179 called again for the same insn expecting that recog_data still contain the
2180 valid information. This is used primary by gen_attr infrastructure that
2181 often does extract insn again and again. */
2183 extract_insn_cached (rtx_insn
*insn
)
2185 if (recog_data
.insn
== insn
&& INSN_CODE (insn
) >= 0)
2187 extract_insn (insn
);
2188 recog_data
.insn
= insn
;
2191 /* Do uncached extract_insn, constrain_operands and complain about failures.
2192 This should be used when extracting a pre-existing constrained instruction
2193 if the caller wants to know which alternative was chosen. */
2195 extract_constrain_insn (rtx_insn
*insn
)
2197 extract_insn (insn
);
2198 if (!constrain_operands (reload_completed
, get_enabled_alternatives (insn
)))
2199 fatal_insn_not_found (insn
);
2202 /* Do cached extract_insn, constrain_operands and complain about failures.
2203 Used by insn_attrtab. */
2205 extract_constrain_insn_cached (rtx_insn
*insn
)
2207 extract_insn_cached (insn
);
2208 if (which_alternative
== -1
2209 && !constrain_operands (reload_completed
,
2210 get_enabled_alternatives (insn
)))
2211 fatal_insn_not_found (insn
);
2214 /* Do cached constrain_operands on INSN and complain about failures. */
2216 constrain_operands_cached (rtx_insn
*insn
, int strict
)
2218 if (which_alternative
== -1)
2219 return constrain_operands (strict
, get_enabled_alternatives (insn
));
2224 /* Analyze INSN and fill in recog_data. */
2227 extract_insn (rtx_insn
*insn
)
2232 rtx body
= PATTERN (insn
);
2234 recog_data
.n_operands
= 0;
2235 recog_data
.n_alternatives
= 0;
2236 recog_data
.n_dups
= 0;
2237 recog_data
.is_asm
= false;
2239 switch (GET_CODE (body
))
2250 if (GET_CODE (SET_SRC (body
)) == ASM_OPERANDS
)
2255 if ((GET_CODE (XVECEXP (body
, 0, 0)) == SET
2256 && GET_CODE (SET_SRC (XVECEXP (body
, 0, 0))) == ASM_OPERANDS
)
2257 || GET_CODE (XVECEXP (body
, 0, 0)) == ASM_OPERANDS
)
2263 recog_data
.n_operands
= noperands
= asm_noperands (body
);
2266 /* This insn is an `asm' with operands. */
2268 /* expand_asm_operands makes sure there aren't too many operands. */
2269 gcc_assert (noperands
<= MAX_RECOG_OPERANDS
);
2271 /* Now get the operand values and constraints out of the insn. */
2272 decode_asm_operands (body
, recog_data
.operand
,
2273 recog_data
.operand_loc
,
2274 recog_data
.constraints
,
2275 recog_data
.operand_mode
, NULL
);
2276 memset (recog_data
.is_operator
, 0, sizeof recog_data
.is_operator
);
2279 const char *p
= recog_data
.constraints
[0];
2280 recog_data
.n_alternatives
= 1;
2282 recog_data
.n_alternatives
+= (*p
++ == ',');
2284 recog_data
.is_asm
= true;
2287 fatal_insn_not_found (insn
);
2291 /* Ordinary insn: recognize it, get the operands via insn_extract
2292 and get the constraints. */
2294 icode
= recog_memoized (insn
);
2296 fatal_insn_not_found (insn
);
2298 recog_data
.n_operands
= noperands
= insn_data
[icode
].n_operands
;
2299 recog_data
.n_alternatives
= insn_data
[icode
].n_alternatives
;
2300 recog_data
.n_dups
= insn_data
[icode
].n_dups
;
2302 insn_extract (insn
);
2304 for (i
= 0; i
< noperands
; i
++)
2306 recog_data
.constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2307 recog_data
.is_operator
[i
] = insn_data
[icode
].operand
[i
].is_operator
;
2308 recog_data
.operand_mode
[i
] = insn_data
[icode
].operand
[i
].mode
;
2309 /* VOIDmode match_operands gets mode from their real operand. */
2310 if (recog_data
.operand_mode
[i
] == VOIDmode
)
2311 recog_data
.operand_mode
[i
] = GET_MODE (recog_data
.operand
[i
]);
2314 for (i
= 0; i
< noperands
; i
++)
2315 recog_data
.operand_type
[i
]
2316 = (recog_data
.constraints
[i
][0] == '=' ? OP_OUT
2317 : recog_data
.constraints
[i
][0] == '+' ? OP_INOUT
2320 gcc_assert (recog_data
.n_alternatives
<= MAX_RECOG_ALTERNATIVES
);
2322 recog_data
.insn
= NULL
;
2323 which_alternative
= -1;
2326 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS operands,
2327 N_ALTERNATIVES alternatives and constraint strings CONSTRAINTS.
2328 OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries and CONSTRAINTS
2329 has N_OPERANDS entries. */
2332 preprocess_constraints (int n_operands
, int n_alternatives
,
2333 const char **constraints
,
2334 operand_alternative
*op_alt_base
)
2336 for (int i
= 0; i
< n_operands
; i
++)
2339 struct operand_alternative
*op_alt
;
2340 const char *p
= constraints
[i
];
2342 op_alt
= op_alt_base
;
2344 for (j
= 0; j
< n_alternatives
; j
++, op_alt
+= n_operands
)
2346 op_alt
[i
].cl
= NO_REGS
;
2347 op_alt
[i
].constraint
= p
;
2348 op_alt
[i
].matches
= -1;
2349 op_alt
[i
].matched
= -1;
2351 if (*p
== '\0' || *p
== ',')
2353 op_alt
[i
].anything_ok
= 1;
2363 while (c
!= ',' && c
!= '\0');
2364 if (c
== ',' || c
== '\0')
2373 op_alt
[i
].reject
+= 6;
2376 op_alt
[i
].reject
+= 600;
2379 op_alt
[i
].earlyclobber
= 1;
2382 case '0': case '1': case '2': case '3': case '4':
2383 case '5': case '6': case '7': case '8': case '9':
2386 op_alt
[i
].matches
= strtoul (p
, &end
, 10);
2387 op_alt
[op_alt
[i
].matches
].matched
= i
;
2393 op_alt
[i
].anything_ok
= 1;
2398 reg_class_subunion
[(int) op_alt
[i
].cl
][(int) GENERAL_REGS
];
2402 enum constraint_num cn
= lookup_constraint (p
);
2404 switch (get_constraint_type (cn
))
2407 cl
= reg_class_for_constraint (cn
);
2409 op_alt
[i
].cl
= reg_class_subunion
[op_alt
[i
].cl
][cl
];
2416 op_alt
[i
].memory_ok
= 1;
2420 op_alt
[i
].is_address
= 1;
2422 = (reg_class_subunion
2423 [(int) op_alt
[i
].cl
]
2424 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
2425 ADDRESS
, SCRATCH
)]);
2433 p
+= CONSTRAINT_LEN (c
, p
);
2439 /* Return an array of operand_alternative instructions for
2440 instruction ICODE. */
2442 const operand_alternative
*
2443 preprocess_insn_constraints (unsigned int icode
)
2445 gcc_checking_assert (IN_RANGE (icode
, 0, NUM_INSN_CODES
- 1));
2446 if (this_target_recog
->x_op_alt
[icode
])
2447 return this_target_recog
->x_op_alt
[icode
];
2449 int n_operands
= insn_data
[icode
].n_operands
;
2450 if (n_operands
== 0)
2452 /* Always provide at least one alternative so that which_op_alt ()
2453 works correctly. If the instruction has 0 alternatives (i.e. all
2454 constraint strings are empty) then each operand in this alternative
2455 will have anything_ok set. */
2456 int n_alternatives
= MAX (insn_data
[icode
].n_alternatives
, 1);
2457 int n_entries
= n_operands
* n_alternatives
;
2459 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
, n_entries
);
2460 const char **constraints
= XALLOCAVEC (const char *, n_operands
);
2462 for (int i
= 0; i
< n_operands
; ++i
)
2463 constraints
[i
] = insn_data
[icode
].operand
[i
].constraint
;
2464 preprocess_constraints (n_operands
, n_alternatives
, constraints
, op_alt
);
2466 this_target_recog
->x_op_alt
[icode
] = op_alt
;
2470 /* After calling extract_insn, you can use this function to extract some
2471 information from the constraint strings into a more usable form.
2472 The collected data is stored in recog_op_alt. */
2475 preprocess_constraints (rtx_insn
*insn
)
2477 int icode
= INSN_CODE (insn
);
2479 recog_op_alt
= preprocess_insn_constraints (icode
);
2482 int n_operands
= recog_data
.n_operands
;
2483 int n_alternatives
= recog_data
.n_alternatives
;
2484 int n_entries
= n_operands
* n_alternatives
;
2485 memset (asm_op_alt
, 0, n_entries
* sizeof (operand_alternative
));
2486 preprocess_constraints (n_operands
, n_alternatives
,
2487 recog_data
.constraints
, asm_op_alt
);
2488 recog_op_alt
= asm_op_alt
;
2492 /* Check the operands of an insn against the insn's operand constraints
2493 and return 1 if they match any of the alternatives in ALTERNATIVES.
2495 The information about the insn's operands, constraints, operand modes
2496 etc. is obtained from the global variables set up by extract_insn.
2498 WHICH_ALTERNATIVE is set to a number which indicates which
2499 alternative of constraints was matched: 0 for the first alternative,
2500 1 for the next, etc.
2502 In addition, when two operands are required to match
2503 and it happens that the output operand is (reg) while the
2504 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec),
2505 make the output operand look like the input.
2506 This is because the output operand is the one the template will print.
2508 This is used in final, just before printing the assembler code and by
2509 the routines that determine an insn's attribute.
2511 If STRICT is a positive nonzero value, it means that we have been
2512 called after reload has been completed. In that case, we must
2513 do all checks strictly. If it is zero, it means that we have been called
2514 before reload has completed. In that case, we first try to see if we can
2515 find an alternative that matches strictly. If not, we try again, this
2516 time assuming that reload will fix up the insn. This provides a "best
2517 guess" for the alternative and is used to compute attributes of insns prior
2518 to reload. A negative value of STRICT is used for this internal call. */
2526 constrain_operands (int strict
, alternative_mask alternatives
)
2528 const char *constraints
[MAX_RECOG_OPERANDS
];
2529 int matching_operands
[MAX_RECOG_OPERANDS
];
2530 int earlyclobber
[MAX_RECOG_OPERANDS
];
2533 struct funny_match funny_match
[MAX_RECOG_OPERANDS
];
2534 int funny_match_index
;
2536 which_alternative
= 0;
2537 if (recog_data
.n_operands
== 0 || recog_data
.n_alternatives
== 0)
2540 for (c
= 0; c
< recog_data
.n_operands
; c
++)
2542 constraints
[c
] = recog_data
.constraints
[c
];
2543 matching_operands
[c
] = -1;
2548 int seen_earlyclobber_at
= -1;
2551 funny_match_index
= 0;
2553 if (!TEST_BIT (alternatives
, which_alternative
))
2557 for (i
= 0; i
< recog_data
.n_operands
; i
++)
2558 constraints
[i
] = skip_alternative (constraints
[i
]);
2560 which_alternative
++;
2564 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2566 rtx op
= recog_data
.operand
[opno
];
2567 machine_mode mode
= GET_MODE (op
);
2568 const char *p
= constraints
[opno
];
2574 earlyclobber
[opno
] = 0;
2576 /* A unary operator may be accepted by the predicate, but it
2577 is irrelevant for matching constraints. */
2581 if (GET_CODE (op
) == SUBREG
)
2583 if (REG_P (SUBREG_REG (op
))
2584 && REGNO (SUBREG_REG (op
)) < FIRST_PSEUDO_REGISTER
)
2585 offset
= subreg_regno_offset (REGNO (SUBREG_REG (op
)),
2586 GET_MODE (SUBREG_REG (op
)),
2589 op
= SUBREG_REG (op
);
2592 /* An empty constraint or empty alternative
2593 allows anything which matched the pattern. */
2594 if (*p
== 0 || *p
== ',')
2598 switch (c
= *p
, len
= CONSTRAINT_LEN (c
, p
), c
)
2608 /* Ignore rest of this alternative as far as
2609 constraint checking is concerned. */
2612 while (*p
&& *p
!= ',');
2617 earlyclobber
[opno
] = 1;
2618 if (seen_earlyclobber_at
< 0)
2619 seen_earlyclobber_at
= opno
;
2622 case '0': case '1': case '2': case '3': case '4':
2623 case '5': case '6': case '7': case '8': case '9':
2625 /* This operand must be the same as a previous one.
2626 This kind of constraint is used for instructions such
2627 as add when they take only two operands.
2629 Note that the lower-numbered operand is passed first.
2631 If we are not testing strictly, assume that this
2632 constraint will be satisfied. */
2637 match
= strtoul (p
, &end
, 10);
2644 rtx op1
= recog_data
.operand
[match
];
2645 rtx op2
= recog_data
.operand
[opno
];
2647 /* A unary operator may be accepted by the predicate,
2648 but it is irrelevant for matching constraints. */
2650 op1
= XEXP (op1
, 0);
2652 op2
= XEXP (op2
, 0);
2654 val
= operands_match_p (op1
, op2
);
2657 matching_operands
[opno
] = match
;
2658 matching_operands
[match
] = opno
;
2663 /* If output is *x and input is *--x, arrange later
2664 to change the output to *--x as well, since the
2665 output op is the one that will be printed. */
2666 if (val
== 2 && strict
> 0)
2668 funny_match
[funny_match_index
].this_op
= opno
;
2669 funny_match
[funny_match_index
++].other
= match
;
2676 /* p is used for address_operands. When we are called by
2677 gen_reload, no one will have checked that the address is
2678 strictly valid, i.e., that all pseudos requiring hard regs
2679 have gotten them. */
2681 || (strict_memory_address_p (recog_data
.operand_mode
[opno
],
2686 /* No need to check general_operand again;
2687 it was done in insn-recog.c. Well, except that reload
2688 doesn't check the validity of its replacements, but
2689 that should only matter when there's a bug. */
2691 /* Anything goes unless it is a REG and really has a hard reg
2692 but the hard reg is not in the class GENERAL_REGS. */
2696 || GENERAL_REGS
== ALL_REGS
2697 || (reload_in_progress
2698 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2699 || reg_fits_class_p (op
, GENERAL_REGS
, offset
, mode
))
2702 else if (strict
< 0 || general_operand (op
, mode
))
2708 enum constraint_num cn
= lookup_constraint (p
);
2709 enum reg_class cl
= reg_class_for_constraint (cn
);
2715 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2716 || (strict
== 0 && GET_CODE (op
) == SCRATCH
)
2718 && reg_fits_class_p (op
, cl
, offset
, mode
)))
2722 else if (constraint_satisfied_p (op
, cn
))
2725 else if (insn_extra_memory_constraint (cn
)
2726 /* Every memory operand can be reloaded to fit. */
2727 && ((strict
< 0 && MEM_P (op
))
2728 /* Before reload, accept what reload can turn
2730 || (strict
< 0 && CONSTANT_P (op
))
2731 /* Before reload, accept a pseudo,
2732 since LRA can turn it into a mem. */
2733 || (strict
< 0 && targetm
.lra_p () && REG_P (op
)
2734 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)
2735 /* During reload, accept a pseudo */
2736 || (reload_in_progress
&& REG_P (op
)
2737 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)))
2739 else if (insn_extra_address_constraint (cn
)
2740 /* Every address operand can be reloaded to fit. */
2743 /* Cater to architectures like IA-64 that define extra memory
2744 constraints without using define_memory_constraint. */
2745 else if (reload_in_progress
2747 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
2748 && reg_renumber
[REGNO (op
)] < 0
2749 && reg_equiv_mem (REGNO (op
)) != 0
2750 && constraint_satisfied_p
2751 (reg_equiv_mem (REGNO (op
)), cn
))
2756 while (p
+= len
, c
);
2758 constraints
[opno
] = p
;
2759 /* If this operand did not win somehow,
2760 this alternative loses. */
2764 /* This alternative won; the operands are ok.
2765 Change whichever operands this alternative says to change. */
2770 /* See if any earlyclobber operand conflicts with some other
2773 if (strict
> 0 && seen_earlyclobber_at
>= 0)
2774 for (eopno
= seen_earlyclobber_at
;
2775 eopno
< recog_data
.n_operands
;
2777 /* Ignore earlyclobber operands now in memory,
2778 because we would often report failure when we have
2779 two memory operands, one of which was formerly a REG. */
2780 if (earlyclobber
[eopno
]
2781 && REG_P (recog_data
.operand
[eopno
]))
2782 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2783 if ((MEM_P (recog_data
.operand
[opno
])
2784 || recog_data
.operand_type
[opno
] != OP_OUT
)
2786 /* Ignore things like match_operator operands. */
2787 && *recog_data
.constraints
[opno
] != 0
2788 && ! (matching_operands
[opno
] == eopno
2789 && operands_match_p (recog_data
.operand
[opno
],
2790 recog_data
.operand
[eopno
]))
2791 && ! safe_from_earlyclobber (recog_data
.operand
[opno
],
2792 recog_data
.operand
[eopno
]))
2797 while (--funny_match_index
>= 0)
2799 recog_data
.operand
[funny_match
[funny_match_index
].other
]
2800 = recog_data
.operand
[funny_match
[funny_match_index
].this_op
];
2803 /* For operands without < or > constraints reject side-effects. */
2804 if (AUTO_INC_DEC
&& recog_data
.is_asm
)
2806 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2807 if (MEM_P (recog_data
.operand
[opno
]))
2808 switch (GET_CODE (XEXP (recog_data
.operand
[opno
], 0)))
2816 if (strchr (recog_data
.constraints
[opno
], '<') == NULL
2817 && strchr (recog_data
.constraints
[opno
], '>')
2830 which_alternative
++;
2832 while (which_alternative
< recog_data
.n_alternatives
);
2834 which_alternative
= -1;
2835 /* If we are about to reject this, but we are not to test strictly,
2836 try a very loose test. Only return failure if it fails also. */
2838 return constrain_operands (-1, alternatives
);
2843 /* Return true iff OPERAND (assumed to be a REG rtx)
2844 is a hard reg in class CLASS when its regno is offset by OFFSET
2845 and changed to mode MODE.
2846 If REG occupies multiple hard regs, all of them must be in CLASS. */
2849 reg_fits_class_p (const_rtx operand
, reg_class_t cl
, int offset
,
2852 unsigned int regno
= REGNO (operand
);
2857 /* Regno must not be a pseudo register. Offset may be negative. */
2858 return (HARD_REGISTER_NUM_P (regno
)
2859 && HARD_REGISTER_NUM_P (regno
+ offset
)
2860 && in_hard_reg_set_p (reg_class_contents
[(int) cl
], mode
,
2864 /* Split single instruction. Helper function for split_all_insns and
2865 split_all_insns_noflow. Return last insn in the sequence if successful,
2866 or NULL if unsuccessful. */
2869 split_insn (rtx_insn
*insn
)
2871 /* Split insns here to get max fine-grain parallelism. */
2872 rtx_insn
*first
= PREV_INSN (insn
);
2873 rtx_insn
*last
= try_split (PATTERN (insn
), insn
, 1);
2874 rtx insn_set
, last_set
, note
;
2879 /* If the original instruction was a single set that was known to be
2880 equivalent to a constant, see if we can say the same about the last
2881 instruction in the split sequence. The two instructions must set
2882 the same destination. */
2883 insn_set
= single_set (insn
);
2886 last_set
= single_set (last
);
2887 if (last_set
&& rtx_equal_p (SET_DEST (last_set
), SET_DEST (insn_set
)))
2889 note
= find_reg_equal_equiv_note (insn
);
2890 if (note
&& CONSTANT_P (XEXP (note
, 0)))
2891 set_unique_reg_note (last
, REG_EQUAL
, XEXP (note
, 0));
2892 else if (CONSTANT_P (SET_SRC (insn_set
)))
2893 set_unique_reg_note (last
, REG_EQUAL
,
2894 copy_rtx (SET_SRC (insn_set
)));
2898 /* try_split returns the NOTE that INSN became. */
2899 SET_INSN_DELETED (insn
);
2901 /* ??? Coddle to md files that generate subregs in post-reload
2902 splitters instead of computing the proper hard register. */
2903 if (reload_completed
&& first
!= last
)
2905 first
= NEXT_INSN (first
);
2909 cleanup_subreg_operands (first
);
2912 first
= NEXT_INSN (first
);
2919 /* Split all insns in the function. If UPD_LIFE, update life info after. */
2922 split_all_insns (void)
2928 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
2929 bitmap_clear (blocks
);
2932 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
2934 rtx_insn
*insn
, *next
;
2935 bool finish
= false;
2937 rtl_profile_for_bb (bb
);
2938 for (insn
= BB_HEAD (bb
); !finish
; insn
= next
)
2940 /* Can't use `next_real_insn' because that might go across
2941 CODE_LABELS and short-out basic blocks. */
2942 next
= NEXT_INSN (insn
);
2943 finish
= (insn
== BB_END (bb
));
2946 rtx set
= single_set (insn
);
2948 /* Don't split no-op move insns. These should silently
2949 disappear later in final. Splitting such insns would
2950 break the code that handles LIBCALL blocks. */
2951 if (set
&& set_noop_p (set
))
2953 /* Nops get in the way while scheduling, so delete them
2954 now if register allocation has already been done. It
2955 is too risky to try to do this before register
2956 allocation, and there are unlikely to be very many
2957 nops then anyways. */
2958 if (reload_completed
)
2959 delete_insn_and_edges (insn
);
2963 if (split_insn (insn
))
2965 bitmap_set_bit (blocks
, bb
->index
);
2973 default_rtl_profile ();
2975 find_many_sub_basic_blocks (blocks
);
2977 checking_verify_flow_info ();
2979 sbitmap_free (blocks
);
2982 /* Same as split_all_insns, but do not expect CFG to be available.
2983 Used by machine dependent reorg passes. */
2986 split_all_insns_noflow (void)
2988 rtx_insn
*next
, *insn
;
2990 for (insn
= get_insns (); insn
; insn
= next
)
2992 next
= NEXT_INSN (insn
);
2995 /* Don't split no-op move insns. These should silently
2996 disappear later in final. Splitting such insns would
2997 break the code that handles LIBCALL blocks. */
2998 rtx set
= single_set (insn
);
2999 if (set
&& set_noop_p (set
))
3001 /* Nops get in the way while scheduling, so delete them
3002 now if register allocation has already been done. It
3003 is too risky to try to do this before register
3004 allocation, and there are unlikely to be very many
3007 ??? Should we use delete_insn when the CFG isn't valid? */
3008 if (reload_completed
)
3009 delete_insn_and_edges (insn
);
3018 struct peep2_insn_data
3024 static struct peep2_insn_data peep2_insn_data
[MAX_INSNS_PER_PEEP2
+ 1];
3025 static int peep2_current
;
3027 static bool peep2_do_rebuild_jump_labels
;
3028 static bool peep2_do_cleanup_cfg
;
3030 /* The number of instructions available to match a peep2. */
3031 int peep2_current_count
;
3033 /* A marker indicating the last insn of the block. The live_before regset
3034 for this element is correct, indicating DF_LIVE_OUT for the block. */
3035 #define PEEP2_EOB invalid_insn_rtx
3037 /* Wrap N to fit into the peep2_insn_data buffer. */
3040 peep2_buf_position (int n
)
3042 if (n
>= MAX_INSNS_PER_PEEP2
+ 1)
3043 n
-= MAX_INSNS_PER_PEEP2
+ 1;
3047 /* Return the Nth non-note insn after `current', or return NULL_RTX if it
3048 does not exist. Used by the recognizer to find the next insn to match
3049 in a multi-insn pattern. */
3052 peep2_next_insn (int n
)
3054 gcc_assert (n
<= peep2_current_count
);
3056 n
= peep2_buf_position (peep2_current
+ n
);
3058 return peep2_insn_data
[n
].insn
;
3061 /* Return true if REGNO is dead before the Nth non-note insn
3065 peep2_regno_dead_p (int ofs
, int regno
)
3067 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3069 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3071 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3073 return ! REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
);
3076 /* Similarly for a REG. */
3079 peep2_reg_dead_p (int ofs
, rtx reg
)
3081 gcc_assert (ofs
< MAX_INSNS_PER_PEEP2
+ 1);
3083 ofs
= peep2_buf_position (peep2_current
+ ofs
);
3085 gcc_assert (peep2_insn_data
[ofs
].insn
!= NULL_RTX
);
3087 unsigned int end_regno
= END_REGNO (reg
);
3088 for (unsigned int regno
= REGNO (reg
); regno
< end_regno
; ++regno
)
3089 if (REGNO_REG_SET_P (peep2_insn_data
[ofs
].live_before
, regno
))
3094 /* Regno offset to be used in the register search. */
3095 static int search_ofs
;
3097 /* Try to find a hard register of mode MODE, matching the register class in
3098 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and
3099 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX,
3100 in which case the only condition is that the register must be available
3101 before CURRENT_INSN.
3102 Registers that already have bits set in REG_SET will not be considered.
3104 If an appropriate register is available, it will be returned and the
3105 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is
3109 peep2_find_free_register (int from
, int to
, const char *class_str
,
3110 machine_mode mode
, HARD_REG_SET
*reg_set
)
3117 gcc_assert (from
< MAX_INSNS_PER_PEEP2
+ 1);
3118 gcc_assert (to
< MAX_INSNS_PER_PEEP2
+ 1);
3120 from
= peep2_buf_position (peep2_current
+ from
);
3121 to
= peep2_buf_position (peep2_current
+ to
);
3123 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3124 REG_SET_TO_HARD_REG_SET (live
, peep2_insn_data
[from
].live_before
);
3128 gcc_assert (peep2_insn_data
[from
].insn
!= NULL_RTX
);
3130 /* Don't use registers set or clobbered by the insn. */
3131 FOR_EACH_INSN_DEF (def
, peep2_insn_data
[from
].insn
)
3132 SET_HARD_REG_BIT (live
, DF_REF_REGNO (def
));
3134 from
= peep2_buf_position (from
+ 1);
3137 cl
= reg_class_for_constraint (lookup_constraint (class_str
));
3139 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3141 int raw_regno
, regno
, success
, j
;
3143 /* Distribute the free registers as much as possible. */
3144 raw_regno
= search_ofs
+ i
;
3145 if (raw_regno
>= FIRST_PSEUDO_REGISTER
)
3146 raw_regno
-= FIRST_PSEUDO_REGISTER
;
3147 #ifdef REG_ALLOC_ORDER
3148 regno
= reg_alloc_order
[raw_regno
];
3153 /* Can it support the mode we need? */
3154 if (! HARD_REGNO_MODE_OK (regno
, mode
))
3158 for (j
= 0; success
&& j
< hard_regno_nregs
[regno
][mode
]; j
++)
3160 /* Don't allocate fixed registers. */
3161 if (fixed_regs
[regno
+ j
])
3166 /* Don't allocate global registers. */
3167 if (global_regs
[regno
+ j
])
3172 /* Make sure the register is of the right class. */
3173 if (! TEST_HARD_REG_BIT (reg_class_contents
[cl
], regno
+ j
))
3178 /* And that we don't create an extra save/restore. */
3179 if (! call_used_regs
[regno
+ j
] && ! df_regs_ever_live_p (regno
+ j
))
3185 if (! targetm
.hard_regno_scratch_ok (regno
+ j
))
3191 /* And we don't clobber traceback for noreturn functions. */
3192 if ((regno
+ j
== FRAME_POINTER_REGNUM
3193 || regno
+ j
== HARD_FRAME_POINTER_REGNUM
)
3194 && (! reload_completed
|| frame_pointer_needed
))
3200 if (TEST_HARD_REG_BIT (*reg_set
, regno
+ j
)
3201 || TEST_HARD_REG_BIT (live
, regno
+ j
))
3210 add_to_hard_reg_set (reg_set
, mode
, regno
);
3212 /* Start the next search with the next register. */
3213 if (++raw_regno
>= FIRST_PSEUDO_REGISTER
)
3215 search_ofs
= raw_regno
;
3217 return gen_rtx_REG (mode
, regno
);
3225 /* Forget all currently tracked instructions, only remember current
3229 peep2_reinit_state (regset live
)
3233 /* Indicate that all slots except the last holds invalid data. */
3234 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
; ++i
)
3235 peep2_insn_data
[i
].insn
= NULL
;
3236 peep2_current_count
= 0;
3238 /* Indicate that the last slot contains live_after data. */
3239 peep2_insn_data
[MAX_INSNS_PER_PEEP2
].insn
= PEEP2_EOB
;
3240 peep2_current
= MAX_INSNS_PER_PEEP2
;
3242 COPY_REG_SET (peep2_insn_data
[MAX_INSNS_PER_PEEP2
].live_before
, live
);
3245 /* While scanning basic block BB, we found a match of length MATCH_LEN,
3246 starting at INSN. Perform the replacement, removing the old insns and
3247 replacing them with ATTEMPT. Returns the last insn emitted, or NULL
3248 if the replacement is rejected. */
3251 peep2_attempt (basic_block bb
, rtx_insn
*insn
, int match_len
, rtx_insn
*attempt
)
3254 rtx_insn
*last
, *before_try
, *x
;
3255 rtx eh_note
, as_note
;
3258 bool was_call
= false;
3260 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to
3261 match more than one insn, or to be split into more than one insn. */
3262 old_insn
= peep2_insn_data
[peep2_current
].insn
;
3263 if (RTX_FRAME_RELATED_P (old_insn
))
3265 bool any_note
= false;
3271 /* Look for one "active" insn. I.e. ignore any "clobber" insns that
3272 may be in the stream for the purpose of register allocation. */
3273 if (active_insn_p (attempt
))
3276 new_insn
= next_active_insn (attempt
);
3277 if (next_active_insn (new_insn
))
3280 /* We have a 1-1 replacement. Copy over any frame-related info. */
3281 RTX_FRAME_RELATED_P (new_insn
) = 1;
3283 /* Allow the backend to fill in a note during the split. */
3284 for (note
= REG_NOTES (new_insn
); note
; note
= XEXP (note
, 1))
3285 switch (REG_NOTE_KIND (note
))
3287 case REG_FRAME_RELATED_EXPR
:
3288 case REG_CFA_DEF_CFA
:
3289 case REG_CFA_ADJUST_CFA
:
3290 case REG_CFA_OFFSET
:
3291 case REG_CFA_REGISTER
:
3292 case REG_CFA_EXPRESSION
:
3293 case REG_CFA_RESTORE
:
3294 case REG_CFA_SET_VDRAP
:
3301 /* If the backend didn't supply a note, copy one over. */
3303 for (note
= REG_NOTES (old_insn
); note
; note
= XEXP (note
, 1))
3304 switch (REG_NOTE_KIND (note
))
3306 case REG_FRAME_RELATED_EXPR
:
3307 case REG_CFA_DEF_CFA
:
3308 case REG_CFA_ADJUST_CFA
:
3309 case REG_CFA_OFFSET
:
3310 case REG_CFA_REGISTER
:
3311 case REG_CFA_EXPRESSION
:
3312 case REG_CFA_RESTORE
:
3313 case REG_CFA_SET_VDRAP
:
3314 add_reg_note (new_insn
, REG_NOTE_KIND (note
), XEXP (note
, 0));
3321 /* If there still isn't a note, make sure the unwind info sees the
3322 same expression as before the split. */
3325 rtx old_set
, new_set
;
3327 /* The old insn had better have been simple, or annotated. */
3328 old_set
= single_set (old_insn
);
3329 gcc_assert (old_set
!= NULL
);
3331 new_set
= single_set (new_insn
);
3332 if (!new_set
|| !rtx_equal_p (new_set
, old_set
))
3333 add_reg_note (new_insn
, REG_FRAME_RELATED_EXPR
, old_set
);
3336 /* Copy prologue/epilogue status. This is required in order to keep
3337 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */
3338 maybe_copy_prologue_epilogue_insn (old_insn
, new_insn
);
3341 /* If we are splitting a CALL_INSN, look for the CALL_INSN
3342 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other
3343 cfg-related call notes. */
3344 for (i
= 0; i
<= match_len
; ++i
)
3349 j
= peep2_buf_position (peep2_current
+ i
);
3350 old_insn
= peep2_insn_data
[j
].insn
;
3351 if (!CALL_P (old_insn
))
3356 while (new_insn
!= NULL_RTX
)
3358 if (CALL_P (new_insn
))
3360 new_insn
= NEXT_INSN (new_insn
);
3363 gcc_assert (new_insn
!= NULL_RTX
);
3365 CALL_INSN_FUNCTION_USAGE (new_insn
)
3366 = CALL_INSN_FUNCTION_USAGE (old_insn
);
3367 SIBLING_CALL_P (new_insn
) = SIBLING_CALL_P (old_insn
);
3369 for (note
= REG_NOTES (old_insn
);
3371 note
= XEXP (note
, 1))
3372 switch (REG_NOTE_KIND (note
))
3377 add_reg_note (new_insn
, REG_NOTE_KIND (note
),
3381 /* Discard all other reg notes. */
3385 /* Croak if there is another call in the sequence. */
3386 while (++i
<= match_len
)
3388 j
= peep2_buf_position (peep2_current
+ i
);
3389 old_insn
= peep2_insn_data
[j
].insn
;
3390 gcc_assert (!CALL_P (old_insn
));
3395 /* If we matched any instruction that had a REG_ARGS_SIZE, then
3396 move those notes over to the new sequence. */
3398 for (i
= match_len
; i
>= 0; --i
)
3400 int j
= peep2_buf_position (peep2_current
+ i
);
3401 old_insn
= peep2_insn_data
[j
].insn
;
3403 as_note
= find_reg_note (old_insn
, REG_ARGS_SIZE
, NULL
);
3408 i
= peep2_buf_position (peep2_current
+ match_len
);
3409 eh_note
= find_reg_note (peep2_insn_data
[i
].insn
, REG_EH_REGION
, NULL_RTX
);
3411 /* Replace the old sequence with the new. */
3412 rtx_insn
*peepinsn
= peep2_insn_data
[i
].insn
;
3413 last
= emit_insn_after_setloc (attempt
,
3414 peep2_insn_data
[i
].insn
,
3415 INSN_LOCATION (peepinsn
));
3416 before_try
= PREV_INSN (insn
);
3417 delete_insn_chain (insn
, peep2_insn_data
[i
].insn
, false);
3419 /* Re-insert the EH_REGION notes. */
3420 if (eh_note
|| (was_call
&& nonlocal_goto_handler_labels
))
3425 FOR_EACH_EDGE (eh_edge
, ei
, bb
->succs
)
3426 if (eh_edge
->flags
& (EDGE_EH
| EDGE_ABNORMAL_CALL
))
3430 copy_reg_eh_region_note_backward (eh_note
, last
, before_try
);
3433 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3434 if (x
!= BB_END (bb
)
3435 && (can_throw_internal (x
)
3436 || can_nonlocal_goto (x
)))
3441 nfte
= split_block (bb
, x
);
3442 flags
= (eh_edge
->flags
3443 & (EDGE_EH
| EDGE_ABNORMAL
));
3445 flags
|= EDGE_ABNORMAL_CALL
;
3446 nehe
= make_edge (nfte
->src
, eh_edge
->dest
,
3449 nehe
->probability
= eh_edge
->probability
;
3451 = REG_BR_PROB_BASE
- nehe
->probability
;
3453 peep2_do_cleanup_cfg
|= purge_dead_edges (nfte
->dest
);
3458 /* Converting possibly trapping insn to non-trapping is
3459 possible. Zap dummy outgoing edges. */
3460 peep2_do_cleanup_cfg
|= purge_dead_edges (bb
);
3463 /* Re-insert the ARGS_SIZE notes. */
3465 fixup_args_size_notes (before_try
, last
, INTVAL (XEXP (as_note
, 0)));
3467 /* If we generated a jump instruction, it won't have
3468 JUMP_LABEL set. Recompute after we're done. */
3469 for (x
= last
; x
!= before_try
; x
= PREV_INSN (x
))
3472 peep2_do_rebuild_jump_labels
= true;
3479 /* After performing a replacement in basic block BB, fix up the life
3480 information in our buffer. LAST is the last of the insns that we
3481 emitted as a replacement. PREV is the insn before the start of
3482 the replacement. MATCH_LEN is the number of instructions that were
3483 matched, and which now need to be replaced in the buffer. */
3486 peep2_update_life (basic_block bb
, int match_len
, rtx_insn
*last
,
3489 int i
= peep2_buf_position (peep2_current
+ match_len
+ 1);
3493 INIT_REG_SET (&live
);
3494 COPY_REG_SET (&live
, peep2_insn_data
[i
].live_before
);
3496 gcc_assert (peep2_current_count
>= match_len
+ 1);
3497 peep2_current_count
-= match_len
+ 1;
3505 if (peep2_current_count
< MAX_INSNS_PER_PEEP2
)
3507 peep2_current_count
++;
3509 i
= MAX_INSNS_PER_PEEP2
;
3510 peep2_insn_data
[i
].insn
= x
;
3511 df_simulate_one_insn_backwards (bb
, x
, &live
);
3512 COPY_REG_SET (peep2_insn_data
[i
].live_before
, &live
);
3518 CLEAR_REG_SET (&live
);
3523 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible.
3524 Return true if we added it, false otherwise. The caller will try to match
3525 peepholes against the buffer if we return false; otherwise it will try to
3526 add more instructions to the buffer. */
3529 peep2_fill_buffer (basic_block bb
, rtx_insn
*insn
, regset live
)
3533 /* Once we have filled the maximum number of insns the buffer can hold,
3534 allow the caller to match the insns against peepholes. We wait until
3535 the buffer is full in case the target has similar peepholes of different
3536 length; we always want to match the longest if possible. */
3537 if (peep2_current_count
== MAX_INSNS_PER_PEEP2
)
3540 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with
3541 any other pattern, lest it change the semantics of the frame info. */
3542 if (RTX_FRAME_RELATED_P (insn
))
3544 /* Let the buffer drain first. */
3545 if (peep2_current_count
> 0)
3547 /* Now the insn will be the only thing in the buffer. */
3550 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3551 peep2_insn_data
[pos
].insn
= insn
;
3552 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3553 peep2_current_count
++;
3555 df_simulate_one_insn_forwards (bb
, insn
, live
);
3559 /* Perform the peephole2 optimization pass. */
3562 peephole2_optimize (void)
3569 peep2_do_cleanup_cfg
= false;
3570 peep2_do_rebuild_jump_labels
= false;
3572 df_set_flags (DF_LR_RUN_DCE
);
3573 df_note_add_problem ();
3576 /* Initialize the regsets we're going to use. */
3577 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3578 peep2_insn_data
[i
].live_before
= BITMAP_ALLOC (®_obstack
);
3580 live
= BITMAP_ALLOC (®_obstack
);
3582 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
3584 bool past_end
= false;
3587 rtl_profile_for_bb (bb
);
3589 /* Start up propagation. */
3590 bitmap_copy (live
, DF_LR_IN (bb
));
3591 df_simulate_initialize_forwards (bb
, live
);
3592 peep2_reinit_state (live
);
3594 insn
= BB_HEAD (bb
);
3597 rtx_insn
*attempt
, *head
;
3600 if (!past_end
&& !NONDEBUG_INSN_P (insn
))
3603 insn
= NEXT_INSN (insn
);
3604 if (insn
== NEXT_INSN (BB_END (bb
)))
3608 if (!past_end
&& peep2_fill_buffer (bb
, insn
, live
))
3611 /* If we did not fill an empty buffer, it signals the end of the
3613 if (peep2_current_count
== 0)
3616 /* The buffer filled to the current maximum, so try to match. */
3618 pos
= peep2_buf_position (peep2_current
+ peep2_current_count
);
3619 peep2_insn_data
[pos
].insn
= PEEP2_EOB
;
3620 COPY_REG_SET (peep2_insn_data
[pos
].live_before
, live
);
3622 /* Match the peephole. */
3623 head
= peep2_insn_data
[peep2_current
].insn
;
3624 attempt
= peephole2_insns (PATTERN (head
), head
, &match_len
);
3625 if (attempt
!= NULL
)
3627 rtx_insn
*last
= peep2_attempt (bb
, head
, match_len
, attempt
);
3630 peep2_update_life (bb
, match_len
, last
, PREV_INSN (attempt
));
3635 /* No match: advance the buffer by one insn. */
3636 peep2_current
= peep2_buf_position (peep2_current
+ 1);
3637 peep2_current_count
--;
3641 default_rtl_profile ();
3642 for (i
= 0; i
< MAX_INSNS_PER_PEEP2
+ 1; ++i
)
3643 BITMAP_FREE (peep2_insn_data
[i
].live_before
);
3645 if (peep2_do_rebuild_jump_labels
)
3646 rebuild_jump_labels (get_insns ());
3647 if (peep2_do_cleanup_cfg
)
3648 cleanup_cfg (CLEANUP_CFG_CHANGED
);
3651 /* Common predicates for use with define_bypass. */
3653 /* True if the dependency between OUT_INSN and IN_INSN is on the store
3654 data not the address operand(s) of the store. IN_INSN and OUT_INSN
3655 must be either a single_set or a PARALLEL with SETs inside. */
3658 store_data_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3660 rtx out_set
, in_set
;
3661 rtx out_pat
, in_pat
;
3662 rtx out_exp
, in_exp
;
3665 in_set
= single_set (in_insn
);
3668 if (!MEM_P (SET_DEST (in_set
)))
3671 out_set
= single_set (out_insn
);
3674 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_set
)))
3679 out_pat
= PATTERN (out_insn
);
3681 if (GET_CODE (out_pat
) != PARALLEL
)
3684 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3686 out_exp
= XVECEXP (out_pat
, 0, i
);
3688 if (GET_CODE (out_exp
) == CLOBBER
)
3691 gcc_assert (GET_CODE (out_exp
) == SET
);
3693 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_set
)))
3700 in_pat
= PATTERN (in_insn
);
3701 gcc_assert (GET_CODE (in_pat
) == PARALLEL
);
3703 for (i
= 0; i
< XVECLEN (in_pat
, 0); i
++)
3705 in_exp
= XVECEXP (in_pat
, 0, i
);
3707 if (GET_CODE (in_exp
) == CLOBBER
)
3710 gcc_assert (GET_CODE (in_exp
) == SET
);
3712 if (!MEM_P (SET_DEST (in_exp
)))
3715 out_set
= single_set (out_insn
);
3718 if (reg_mentioned_p (SET_DEST (out_set
), SET_DEST (in_exp
)))
3723 out_pat
= PATTERN (out_insn
);
3724 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3726 for (j
= 0; j
< XVECLEN (out_pat
, 0); j
++)
3728 out_exp
= XVECEXP (out_pat
, 0, j
);
3730 if (GET_CODE (out_exp
) == CLOBBER
)
3733 gcc_assert (GET_CODE (out_exp
) == SET
);
3735 if (reg_mentioned_p (SET_DEST (out_exp
), SET_DEST (in_exp
)))
3745 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE
3746 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single
3747 or multiple set; IN_INSN should be single_set for truth, but for convenience
3748 of insn categorization may be any JUMP or CALL insn. */
3751 if_test_bypass_p (rtx_insn
*out_insn
, rtx_insn
*in_insn
)
3753 rtx out_set
, in_set
;
3755 in_set
= single_set (in_insn
);
3758 gcc_assert (JUMP_P (in_insn
) || CALL_P (in_insn
));
3762 if (GET_CODE (SET_SRC (in_set
)) != IF_THEN_ELSE
)
3764 in_set
= SET_SRC (in_set
);
3766 out_set
= single_set (out_insn
);
3769 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3770 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3778 out_pat
= PATTERN (out_insn
);
3779 gcc_assert (GET_CODE (out_pat
) == PARALLEL
);
3781 for (i
= 0; i
< XVECLEN (out_pat
, 0); i
++)
3783 rtx exp
= XVECEXP (out_pat
, 0, i
);
3785 if (GET_CODE (exp
) == CLOBBER
)
3788 gcc_assert (GET_CODE (exp
) == SET
);
3790 if (reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 1))
3791 || reg_mentioned_p (SET_DEST (out_set
), XEXP (in_set
, 2)))
3800 rest_of_handle_peephole2 (void)
3803 peephole2_optimize ();
3810 const pass_data pass_data_peephole2
=
3812 RTL_PASS
, /* type */
3813 "peephole2", /* name */
3814 OPTGROUP_NONE
, /* optinfo_flags */
3815 TV_PEEPHOLE2
, /* tv_id */
3816 0, /* properties_required */
3817 0, /* properties_provided */
3818 0, /* properties_destroyed */
3819 0, /* todo_flags_start */
3820 TODO_df_finish
, /* todo_flags_finish */
3823 class pass_peephole2
: public rtl_opt_pass
3826 pass_peephole2 (gcc::context
*ctxt
)
3827 : rtl_opt_pass (pass_data_peephole2
, ctxt
)
3830 /* opt_pass methods: */
3831 /* The epiphany backend creates a second instance of this pass, so we need
3833 opt_pass
* clone () { return new pass_peephole2 (m_ctxt
); }
3834 virtual bool gate (function
*) { return (optimize
> 0 && flag_peephole2
); }
3835 virtual unsigned int execute (function
*)
3837 return rest_of_handle_peephole2 ();
3840 }; // class pass_peephole2
3845 make_pass_peephole2 (gcc::context
*ctxt
)
3847 return new pass_peephole2 (ctxt
);
3852 const pass_data pass_data_split_all_insns
=
3854 RTL_PASS
, /* type */
3855 "split1", /* name */
3856 OPTGROUP_NONE
, /* optinfo_flags */
3857 TV_NONE
, /* tv_id */
3858 0, /* properties_required */
3859 0, /* properties_provided */
3860 0, /* properties_destroyed */
3861 0, /* todo_flags_start */
3862 0, /* todo_flags_finish */
3865 class pass_split_all_insns
: public rtl_opt_pass
3868 pass_split_all_insns (gcc::context
*ctxt
)
3869 : rtl_opt_pass (pass_data_split_all_insns
, ctxt
)
3872 /* opt_pass methods: */
3873 /* The epiphany backend creates a second instance of this pass, so
3874 we need a clone method. */
3875 opt_pass
* clone () { return new pass_split_all_insns (m_ctxt
); }
3876 virtual unsigned int execute (function
*)
3882 }; // class pass_split_all_insns
3887 make_pass_split_all_insns (gcc::context
*ctxt
)
3889 return new pass_split_all_insns (ctxt
);
3893 rest_of_handle_split_after_reload (void)
3895 /* If optimizing, then go ahead and split insns now. */
3905 const pass_data pass_data_split_after_reload
=
3907 RTL_PASS
, /* type */
3908 "split2", /* name */
3909 OPTGROUP_NONE
, /* optinfo_flags */
3910 TV_NONE
, /* tv_id */
3911 0, /* properties_required */
3912 0, /* properties_provided */
3913 0, /* properties_destroyed */
3914 0, /* todo_flags_start */
3915 0, /* todo_flags_finish */
3918 class pass_split_after_reload
: public rtl_opt_pass
3921 pass_split_after_reload (gcc::context
*ctxt
)
3922 : rtl_opt_pass (pass_data_split_after_reload
, ctxt
)
3925 /* opt_pass methods: */
3926 virtual unsigned int execute (function
*)
3928 return rest_of_handle_split_after_reload ();
3931 }; // class pass_split_after_reload
3936 make_pass_split_after_reload (gcc::context
*ctxt
)
3938 return new pass_split_after_reload (ctxt
);
3943 const pass_data pass_data_split_before_regstack
=
3945 RTL_PASS
, /* type */
3946 "split3", /* name */
3947 OPTGROUP_NONE
, /* optinfo_flags */
3948 TV_NONE
, /* tv_id */
3949 0, /* properties_required */
3950 0, /* properties_provided */
3951 0, /* properties_destroyed */
3952 0, /* todo_flags_start */
3953 0, /* todo_flags_finish */
3956 class pass_split_before_regstack
: public rtl_opt_pass
3959 pass_split_before_regstack (gcc::context
*ctxt
)
3960 : rtl_opt_pass (pass_data_split_before_regstack
, ctxt
)
3963 /* opt_pass methods: */
3964 virtual bool gate (function
*);
3965 virtual unsigned int execute (function
*)
3971 }; // class pass_split_before_regstack
3974 pass_split_before_regstack::gate (function
*)
3976 #if HAVE_ATTR_length && defined (STACK_REGS)
3977 /* If flow2 creates new instructions which need splitting
3978 and scheduling after reload is not done, they might not be
3979 split until final which doesn't allow splitting
3980 if HAVE_ATTR_length. */
3981 # ifdef INSN_SCHEDULING
3982 return (optimize
&& !flag_schedule_insns_after_reload
);
3994 make_pass_split_before_regstack (gcc::context
*ctxt
)
3996 return new pass_split_before_regstack (ctxt
);
4000 rest_of_handle_split_before_sched2 (void)
4002 #ifdef INSN_SCHEDULING
4010 const pass_data pass_data_split_before_sched2
=
4012 RTL_PASS
, /* type */
4013 "split4", /* name */
4014 OPTGROUP_NONE
, /* optinfo_flags */
4015 TV_NONE
, /* tv_id */
4016 0, /* properties_required */
4017 0, /* properties_provided */
4018 0, /* properties_destroyed */
4019 0, /* todo_flags_start */
4020 0, /* todo_flags_finish */
4023 class pass_split_before_sched2
: public rtl_opt_pass
4026 pass_split_before_sched2 (gcc::context
*ctxt
)
4027 : rtl_opt_pass (pass_data_split_before_sched2
, ctxt
)
4030 /* opt_pass methods: */
4031 virtual bool gate (function
*)
4033 #ifdef INSN_SCHEDULING
4034 return optimize
> 0 && flag_schedule_insns_after_reload
;
4040 virtual unsigned int execute (function
*)
4042 return rest_of_handle_split_before_sched2 ();
4045 }; // class pass_split_before_sched2
4050 make_pass_split_before_sched2 (gcc::context
*ctxt
)
4052 return new pass_split_before_sched2 (ctxt
);
4057 const pass_data pass_data_split_for_shorten_branches
=
4059 RTL_PASS
, /* type */
4060 "split5", /* name */
4061 OPTGROUP_NONE
, /* optinfo_flags */
4062 TV_NONE
, /* tv_id */
4063 0, /* properties_required */
4064 0, /* properties_provided */
4065 0, /* properties_destroyed */
4066 0, /* todo_flags_start */
4067 0, /* todo_flags_finish */
4070 class pass_split_for_shorten_branches
: public rtl_opt_pass
4073 pass_split_for_shorten_branches (gcc::context
*ctxt
)
4074 : rtl_opt_pass (pass_data_split_for_shorten_branches
, ctxt
)
4077 /* opt_pass methods: */
4078 virtual bool gate (function
*)
4080 /* The placement of the splitting that we do for shorten_branches
4081 depends on whether regstack is used by the target or not. */
4082 #if HAVE_ATTR_length && !defined (STACK_REGS)
4089 virtual unsigned int execute (function
*)
4091 return split_all_insns_noflow ();
4094 }; // class pass_split_for_shorten_branches
4099 make_pass_split_for_shorten_branches (gcc::context
*ctxt
)
4101 return new pass_split_for_shorten_branches (ctxt
);
4104 /* (Re)initialize the target information after a change in target. */
4109 /* The information is zero-initialized, so we don't need to do anything
4110 first time round. */
4111 if (!this_target_recog
->x_initialized
)
4113 this_target_recog
->x_initialized
= true;
4116 memset (this_target_recog
->x_bool_attr_masks
, 0,
4117 sizeof (this_target_recog
->x_bool_attr_masks
));
4118 for (unsigned int i
= 0; i
< NUM_INSN_CODES
; ++i
)
4119 if (this_target_recog
->x_op_alt
[i
])
4121 free (this_target_recog
->x_op_alt
[i
]);
4122 this_target_recog
->x_op_alt
[i
] = 0;