1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
36 #include "rtl-error.h"
38 #include "addresses.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 struct target_reload default_target_reload
;
82 struct target_reload
*this_target_reload
= &default_target_reload
;
85 #define spill_indirect_levels \
86 (this_target_reload->x_spill_indirect_levels)
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx
*reg_last_reload_reg
;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static regset_head reg_has_output_reload
;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload
;
100 /* Widest mode in which each pseudo reg is referred to (via subreg). */
101 static machine_mode
*reg_max_ref_mode
;
103 /* Vector to remember old contents of reg_renumber before spilling. */
104 static short *reg_old_renumber
;
106 /* During reload_as_needed, element N contains the last pseudo regno reloaded
107 into hard register N. If that pseudo reg occupied more than one register,
108 reg_reloaded_contents points to that pseudo for each spill register in
109 use; all of these must remain set for an inheritance to occur. */
110 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
112 /* During reload_as_needed, element N contains the insn for which
113 hard register N was last used. Its contents are significant only
114 when reg_reloaded_valid is set for this register. */
115 static rtx_insn
*reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
117 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
118 static HARD_REG_SET reg_reloaded_valid
;
119 /* Indicate if the register was dead at the end of the reload.
120 This is only valid if reg_reloaded_contents is set and valid. */
121 static HARD_REG_SET reg_reloaded_dead
;
123 /* Indicate whether the register's current value is one that is not
124 safe to retain across a call, even for registers that are normally
125 call-saved. This is only meaningful for members of reg_reloaded_valid. */
126 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
128 /* Number of spill-regs so far; number of valid elements of spill_regs. */
131 /* In parallel with spill_regs, contains REG rtx's for those regs.
132 Holds the last rtx used for any given reg, or 0 if it has never
133 been used for spilling yet. This rtx is reused, provided it has
135 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
137 /* In parallel with spill_regs, contains nonzero for a spill reg
138 that was stored after the last time it was used.
139 The precise value is the insn generated to do the store. */
140 static rtx_insn
*spill_reg_store
[FIRST_PSEUDO_REGISTER
];
142 /* This is the register that was stored with spill_reg_store. This is a
143 copy of reload_out / reload_out_reg when the value was stored; if
144 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
145 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
147 /* This table is the inverse mapping of spill_regs:
148 indexed by hard reg number,
149 it contains the position of that reg in spill_regs,
150 or -1 for something that is not in spill_regs.
152 ?!? This is no longer accurate. */
153 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
155 /* This reg set indicates registers that can't be used as spill registers for
156 the currently processed insn. These are the hard registers which are live
157 during the insn, but not allocated to pseudos, as well as fixed
159 static HARD_REG_SET bad_spill_regs
;
161 /* These are the hard registers that can't be used as spill register for any
162 insn. This includes registers used for user variables and registers that
163 we can't eliminate. A register that appears in this set also can't be used
164 to retry register allocation. */
165 static HARD_REG_SET bad_spill_regs_global
;
167 /* Describes order of use of registers for reloading
168 of spilled pseudo-registers. `n_spills' is the number of
169 elements that are actually valid; new ones are added at the end.
171 Both spill_regs and spill_reg_order are used on two occasions:
172 once during find_reload_regs, where they keep track of the spill registers
173 for a single insn, but also during reload_as_needed where they show all
174 the registers ever used by reload. For the latter case, the information
175 is calculated during finish_spills. */
176 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
178 /* This vector of reg sets indicates, for each pseudo, which hard registers
179 may not be used for retrying global allocation because the register was
180 formerly spilled from one of them. If we allowed reallocating a pseudo to
181 a register that it was already allocated to, reload might not
183 static HARD_REG_SET
*pseudo_previous_regs
;
185 /* This vector of reg sets indicates, for each pseudo, which hard
186 registers may not be used for retrying global allocation because they
187 are used as spill registers during one of the insns in which the
189 static HARD_REG_SET
*pseudo_forbidden_regs
;
191 /* All hard regs that have been used as spill registers for any insn are
192 marked in this set. */
193 static HARD_REG_SET used_spill_regs
;
195 /* Index of last register assigned as a spill register. We allocate in
196 a round-robin fashion. */
197 static int last_spill_reg
;
199 /* Record the stack slot for each spilled hard register. */
200 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
202 /* Width allocated so far for that stack slot. */
203 static poly_uint64_pod spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
205 /* Record which pseudos needed to be spilled. */
206 static regset_head spilled_pseudos
;
208 /* Record which pseudos changed their allocation in finish_spills. */
209 static regset_head changed_allocation_pseudos
;
211 /* Used for communication between order_regs_for_reload and count_pseudo.
212 Used to avoid counting one pseudo twice. */
213 static regset_head pseudos_counted
;
215 /* First uid used by insns created by reload in this function.
216 Used in find_equiv_reg. */
217 int reload_first_uid
;
219 /* Flag set by local-alloc or global-alloc if anything is live in
220 a call-clobbered reg across calls. */
221 int caller_save_needed
;
223 /* Set to 1 while reload_as_needed is operating.
224 Required by some machines to handle any generated moves differently. */
225 int reload_in_progress
= 0;
227 /* This obstack is used for allocation of rtl during register elimination.
228 The allocated storage can be freed once find_reloads has processed the
230 static struct obstack reload_obstack
;
232 /* Points to the beginning of the reload_obstack. All insn_chain structures
233 are allocated first. */
234 static char *reload_startobj
;
236 /* The point after all insn_chain structures. Used to quickly deallocate
237 memory allocated in copy_reloads during calculate_needs_all_insns. */
238 static char *reload_firstobj
;
240 /* This points before all local rtl generated by register elimination.
241 Used to quickly free all memory after processing one insn. */
242 static char *reload_insn_firstobj
;
244 /* List of insn_chain instructions, one for every insn that reload needs to
246 class insn_chain
*reload_insn_chain
;
248 /* TRUE if we potentially left dead insns in the insn stream and want to
249 run DCE immediately after reload, FALSE otherwise. */
250 static bool need_dce
;
252 /* List of all insns needing reloads. */
253 static class insn_chain
*insns_need_reload
;
255 /* This structure is used to record information about register eliminations.
256 Each array entry describes one possible way of eliminating a register
257 in favor of another. If there is more than one way of eliminating a
258 particular register, the most preferred should be specified first. */
262 int from
; /* Register number to be eliminated. */
263 int to
; /* Register number used as replacement. */
264 poly_int64_pod initial_offset
; /* Initial difference between values. */
265 int can_eliminate
; /* Nonzero if this elimination can be done. */
266 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
267 target hook in previous scan over insns
269 poly_int64_pod offset
; /* Current offset between the two regs. */
270 poly_int64_pod previous_offset
; /* Offset at end of previous insn. */
271 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
272 rtx from_rtx
; /* REG rtx for the register to be eliminated.
273 We cannot simply compare the number since
274 we might then spuriously replace a hard
275 register corresponding to a pseudo
276 assigned to the reg to be eliminated. */
277 rtx to_rtx
; /* REG rtx for the replacement. */
280 static struct elim_table
*reg_eliminate
= 0;
282 /* This is an intermediate structure to initialize the table. It has
283 exactly the members provided by ELIMINABLE_REGS. */
284 static const struct elim_table_1
288 } reg_eliminate_1
[] =
292 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
294 /* Record the number of pending eliminations that have an offset not equal
295 to their initial offset. If nonzero, we use a new copy of each
296 replacement result in any insns encountered. */
297 int num_not_at_initial_offset
;
299 /* Count the number of registers that we may be able to eliminate. */
300 static int num_eliminable
;
301 /* And the number of registers that are equivalent to a constant that
302 can be eliminated to frame_pointer / arg_pointer + constant. */
303 static int num_eliminable_invariants
;
305 /* For each label, we record the offset of each elimination. If we reach
306 a label by more than one path and an offset differs, we cannot do the
307 elimination. This information is indexed by the difference of the
308 number of the label and the first label number. We can't offset the
309 pointer itself as this can cause problems on machines with segmented
310 memory. The first table is an array of flags that records whether we
311 have yet encountered a label and the second table is an array of arrays,
312 one entry in the latter array for each elimination. */
314 static int first_label_num
;
315 static char *offsets_known_at
;
316 static poly_int64_pod (*offsets_at
)[NUM_ELIMINABLE_REGS
];
318 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
320 /* Stack of addresses where an rtx has been changed. We can undo the
321 changes by popping items off the stack and restoring the original
322 value at each location.
324 We use this simplistic undo capability rather than copy_rtx as copy_rtx
325 will not make a deep copy of a normally sharable rtx, such as
326 (const (plus (symbol_ref) (const_int))). If such an expression appears
327 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
328 rtx expression would be changed. See PR 42431. */
331 static vec
<rtx_p
> substitute_stack
;
333 /* Number of labels in the current function. */
335 static int num_labels
;
337 static void replace_pseudos_in (rtx
*, machine_mode
, rtx
);
338 static void maybe_fix_stack_asms (void);
339 static void copy_reloads (class insn_chain
*);
340 static void calculate_needs_all_insns (int);
341 static int find_reg (class insn_chain
*, int);
342 static void find_reload_regs (class insn_chain
*);
343 static void select_reload_regs (void);
344 static void delete_caller_save_insns (void);
346 static void spill_failure (rtx_insn
*, enum reg_class
);
347 static void count_spilled_pseudo (int, int, int);
348 static void delete_dead_insn (rtx_insn
*);
349 static void alter_reg (int, int, bool);
350 static void set_label_offsets (rtx
, rtx_insn
*, int);
351 static void check_eliminable_occurrences (rtx
);
352 static void elimination_effects (rtx
, machine_mode
);
353 static rtx
eliminate_regs_1 (rtx
, machine_mode
, rtx
, bool, bool);
354 static int eliminate_regs_in_insn (rtx_insn
*, int);
355 static void update_eliminable_offsets (void);
356 static void mark_not_eliminable (rtx
, const_rtx
, void *);
357 static void set_initial_elim_offsets (void);
358 static bool verify_initial_elim_offsets (void);
359 static void set_initial_label_offsets (void);
360 static void set_offsets_for_label (rtx_insn
*);
361 static void init_eliminable_invariants (rtx_insn
*, bool);
362 static void init_elim_table (void);
363 static void free_reg_equiv (void);
364 static void update_eliminables (HARD_REG_SET
*);
365 static bool update_eliminables_and_spill (void);
366 static void elimination_costs_in_insn (rtx_insn
*);
367 static void spill_hard_reg (unsigned int, int);
368 static int finish_spills (int);
369 static void scan_paradoxical_subregs (rtx
);
370 static void count_pseudo (int);
371 static void order_regs_for_reload (class insn_chain
*);
372 static void reload_as_needed (int);
373 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
374 static void forget_marked_reloads (regset
);
375 static int reload_reg_class_lower (const void *, const void *);
376 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
378 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
380 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
381 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
383 static int free_for_value_p (int, machine_mode
, int, enum reload_type
,
385 static int allocate_reload_reg (class insn_chain
*, int, int);
386 static int conflicts_with_override (rtx
);
387 static void failed_reload (rtx_insn
*, int);
388 static int set_reload_reg (int, int);
389 static void choose_reload_regs_init (class insn_chain
*, rtx
*);
390 static void choose_reload_regs (class insn_chain
*);
391 static void emit_input_reload_insns (class insn_chain
*, struct reload
*,
393 static void emit_output_reload_insns (class insn_chain
*, struct reload
*,
395 static void do_input_reload (class insn_chain
*, struct reload
*, int);
396 static void do_output_reload (class insn_chain
*, struct reload
*, int);
397 static void emit_reload_insns (class insn_chain
*);
398 static void delete_output_reload (rtx_insn
*, int, int, rtx
);
399 static void delete_address_reloads (rtx_insn
*, rtx_insn
*);
400 static void delete_address_reloads_1 (rtx_insn
*, rtx
, rtx_insn
*);
401 static void inc_for_reload (rtx
, rtx
, rtx
, poly_int64
);
402 static void add_auto_inc_notes (rtx_insn
*, rtx
);
403 static void substitute (rtx
*, const_rtx
, rtx
);
404 static bool gen_reload_chain_without_interm_reg_p (int, int);
405 static int reloads_conflict (int, int);
406 static rtx_insn
*gen_reload (rtx
, rtx
, int, enum reload_type
);
407 static rtx_insn
*emit_insn_if_valid_for_reload (rtx
);
409 /* Initialize the reload pass. This is called at the beginning of compilation
410 and may be called again if the target is reinitialized. */
417 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
418 Set spill_indirect_levels to the number of levels such addressing is
419 permitted, zero if it is not permitted at all. */
422 = gen_rtx_MEM (Pmode
,
425 LAST_VIRTUAL_REGISTER
+ 1),
426 gen_int_mode (4, Pmode
)));
427 spill_indirect_levels
= 0;
429 while (memory_address_p (QImode
, tem
))
431 spill_indirect_levels
++;
432 tem
= gen_rtx_MEM (Pmode
, tem
);
435 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
437 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
438 indirect_symref_ok
= memory_address_p (QImode
, tem
);
440 /* See if reg+reg is a valid (and offsettable) address. */
442 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
444 tem
= gen_rtx_PLUS (Pmode
,
445 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
446 gen_rtx_REG (Pmode
, i
));
448 /* This way, we make sure that reg+reg is an offsettable address. */
449 tem
= plus_constant (Pmode
, tem
, 4);
451 for (int mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
452 if (!double_reg_address_ok
[mode
]
453 && memory_address_p ((enum machine_mode
)mode
, tem
))
454 double_reg_address_ok
[mode
] = 1;
457 /* Initialize obstack for our rtl allocation. */
458 if (reload_startobj
== NULL
)
460 gcc_obstack_init (&reload_obstack
);
461 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
464 INIT_REG_SET (&spilled_pseudos
);
465 INIT_REG_SET (&changed_allocation_pseudos
);
466 INIT_REG_SET (&pseudos_counted
);
469 /* List of insn chains that are currently unused. */
470 static class insn_chain
*unused_insn_chains
= 0;
472 /* Allocate an empty insn_chain structure. */
474 new_insn_chain (void)
478 if (unused_insn_chains
== 0)
480 c
= XOBNEW (&reload_obstack
, class insn_chain
);
481 INIT_REG_SET (&c
->live_throughout
);
482 INIT_REG_SET (&c
->dead_or_set
);
486 c
= unused_insn_chains
;
487 unused_insn_chains
= c
->next
;
489 c
->is_caller_save_insn
= 0;
490 c
->need_operand_change
= 0;
496 /* Small utility function to set all regs in hard reg set TO which are
497 allocated to pseudos in regset FROM. */
500 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
503 reg_set_iterator rsi
;
505 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
507 int r
= reg_renumber
[regno
];
511 /* reload_combine uses the information from DF_LIVE_IN,
512 which might still contain registers that have not
513 actually been allocated since they have an
515 gcc_assert (ira_conflicts_p
|| reload_completed
);
518 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
522 /* Replace all pseudos found in LOC with their corresponding
526 replace_pseudos_in (rtx
*loc
, machine_mode mem_mode
, rtx usage
)
539 unsigned int regno
= REGNO (x
);
541 if (regno
< FIRST_PSEUDO_REGISTER
)
544 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
548 replace_pseudos_in (loc
, mem_mode
, usage
);
552 if (reg_equiv_constant (regno
))
553 *loc
= reg_equiv_constant (regno
);
554 else if (reg_equiv_invariant (regno
))
555 *loc
= reg_equiv_invariant (regno
);
556 else if (reg_equiv_mem (regno
))
557 *loc
= reg_equiv_mem (regno
);
558 else if (reg_equiv_address (regno
))
559 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
562 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
563 || REGNO (regno_reg_rtx
[regno
]) != regno
);
564 *loc
= regno_reg_rtx
[regno
];
569 else if (code
== MEM
)
571 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
575 /* Process each of our operands recursively. */
576 fmt
= GET_RTX_FORMAT (code
);
577 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
579 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
580 else if (*fmt
== 'E')
581 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
582 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
585 /* Determine if the current function has an exception receiver block
586 that reaches the exit block via non-exceptional edges */
589 has_nonexceptional_receiver (void)
593 basic_block
*tos
, *worklist
, bb
;
595 /* If we're not optimizing, then just err on the safe side. */
599 /* First determine which blocks can reach exit via normal paths. */
600 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
602 FOR_EACH_BB_FN (bb
, cfun
)
603 bb
->flags
&= ~BB_REACHABLE
;
605 /* Place the exit block on our worklist. */
606 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
607 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
609 /* Iterate: find everything reachable from what we've already seen. */
610 while (tos
!= worklist
)
614 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
615 if (!(e
->flags
& EDGE_ABNORMAL
))
617 basic_block src
= e
->src
;
619 if (!(src
->flags
& BB_REACHABLE
))
621 src
->flags
|= BB_REACHABLE
;
628 /* Now see if there's a reachable block with an exceptional incoming
630 FOR_EACH_BB_FN (bb
, cfun
)
631 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
634 /* No exceptional block reached exit unexceptionally. */
638 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
639 zero elements) to MAX_REG_NUM elements.
641 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
643 grow_reg_equivs (void)
645 int old_size
= vec_safe_length (reg_equivs
);
646 int max_regno
= max_reg_num ();
650 memset (&ze
, 0, sizeof (reg_equivs_t
));
651 vec_safe_reserve (reg_equivs
, max_regno
);
652 for (i
= old_size
; i
< max_regno
; i
++)
653 reg_equivs
->quick_insert (i
, ze
);
657 /* Global variables used by reload and its subroutines. */
659 /* The current basic block while in calculate_elim_costs_all_insns. */
660 static basic_block elim_bb
;
662 /* Set during calculate_needs if an insn needs register elimination. */
663 static int something_needs_elimination
;
664 /* Set during calculate_needs if an insn needs an operand changed. */
665 static int something_needs_operands_changed
;
666 /* Set by alter_regs if we spilled a register to the stack. */
667 static bool something_was_spilled
;
669 /* Nonzero means we couldn't get enough spill regs. */
672 /* Temporary array of pseudo-register number. */
673 static int *temp_pseudo_reg_arr
;
675 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
676 If that insn didn't set the register (i.e., it copied the register to
677 memory), just delete that insn instead of the equivalencing insn plus
678 anything now dead. If we call delete_dead_insn on that insn, we may
679 delete the insn that actually sets the register if the register dies
680 there and that is incorrect. */
684 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
686 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
689 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
691 rtx_insn
*equiv_insn
= as_a
<rtx_insn
*> (XEXP (list
, 0));
693 /* If we already deleted the insn or if it may trap, we can't
694 delete it. The latter case shouldn't happen, but can
695 if an insn has a variable address, gets a REG_EH_REGION
696 note added to it, and then gets converted into a load
697 from a constant address. */
698 if (NOTE_P (equiv_insn
)
699 || can_throw_internal (equiv_insn
))
701 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
702 delete_dead_insn (equiv_insn
);
704 SET_INSN_DELETED (equiv_insn
);
710 /* Return true if remove_init_insns will delete INSN. */
712 will_delete_init_insn_p (rtx_insn
*insn
)
714 rtx set
= single_set (insn
);
715 if (!set
|| !REG_P (SET_DEST (set
)))
717 unsigned regno
= REGNO (SET_DEST (set
));
719 if (can_throw_internal (insn
))
722 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
725 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
727 rtx equiv_insn
= XEXP (list
, 0);
728 if (equiv_insn
== insn
)
734 /* Main entry point for the reload pass.
736 FIRST is the first insn of the function being compiled.
738 GLOBAL nonzero means we were called from global_alloc
739 and should attempt to reallocate any pseudoregs that we
740 displace from hard regs we will use for reloads.
741 If GLOBAL is zero, we do not have enough information to do that,
742 so any pseudo reg that is spilled must go to the stack.
744 Return value is TRUE if reload likely left dead insns in the
745 stream and a DCE pass should be run to elimiante them. Else the
746 return value is FALSE. */
749 reload (rtx_insn
*first
, int global
)
753 struct elim_table
*ep
;
757 /* Make sure even insns with volatile mem refs are recognizable. */
762 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
764 /* Make sure that the last insn in the chain
765 is not something that needs reloading. */
766 emit_note (NOTE_INSN_DELETED
);
768 /* Enable find_equiv_reg to distinguish insns made by reload. */
769 reload_first_uid
= get_max_uid ();
771 /* Initialize the secondary memory table. */
772 clear_secondary_mem ();
774 /* We don't have a stack slot for any spill reg yet. */
775 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
776 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
778 /* Initialize the save area information for caller-save, in case some
782 /* Compute which hard registers are now in use
783 as homes for pseudo registers.
784 This is done here rather than (eg) in global_alloc
785 because this point is reached even if not optimizing. */
786 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
789 /* A function that has a nonlocal label that can reach the exit
790 block via non-exceptional paths must save all call-saved
792 if (cfun
->has_nonlocal_label
793 && has_nonexceptional_receiver ())
794 crtl
->saves_all_registers
= 1;
796 if (crtl
->saves_all_registers
)
797 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
798 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
799 df_set_regs_ever_live (i
, true);
801 /* Find all the pseudo registers that didn't get hard regs
802 but do have known equivalent constants or memory slots.
803 These include parameters (known equivalent to parameter slots)
804 and cse'd or loop-moved constant memory addresses.
806 Record constant equivalents in reg_equiv_constant
807 so they will be substituted by find_reloads.
808 Record memory equivalents in reg_mem_equiv so they can
809 be substituted eventually by altering the REG-rtx's. */
812 reg_old_renumber
= XCNEWVEC (short, max_regno
);
813 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
814 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
815 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
817 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
819 init_eliminable_invariants (first
, true);
822 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
823 stack slots to the pseudos that lack hard regs or equivalents.
824 Do not touch virtual registers. */
826 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
827 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
828 temp_pseudo_reg_arr
[n
++] = i
;
831 /* Ask IRA to order pseudo-registers for better stack slot
833 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_mode
);
835 for (i
= 0; i
< n
; i
++)
836 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
838 /* If we have some registers we think can be eliminated, scan all insns to
839 see if there is an insn that sets one of these registers to something
840 other than itself plus a constant. If so, the register cannot be
841 eliminated. Doing this scan here eliminates an extra pass through the
842 main reload loop in the most common case where register elimination
844 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
846 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
848 maybe_fix_stack_asms ();
850 insns_need_reload
= 0;
851 something_needs_elimination
= 0;
853 /* Initialize to -1, which means take the first spill register. */
856 /* Spill any hard regs that we know we can't eliminate. */
857 CLEAR_HARD_REG_SET (used_spill_regs
);
858 /* There can be multiple ways to eliminate a register;
859 they should be listed adjacently.
860 Elimination for any register fails only if all possible ways fail. */
861 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
864 int can_eliminate
= 0;
867 can_eliminate
|= ep
->can_eliminate
;
870 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
872 spill_hard_reg (from
, 1);
875 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
&& frame_pointer_needed
)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
878 finish_spills (global
);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress
= 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed
;
890 poly_int64 starting_frame_size
;
892 starting_frame_size
= get_frame_size ();
893 something_was_spilled
= false;
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
923 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
925 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
928 if (strict_memory_address_addr_space_p
929 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
931 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
932 else if (CONSTANT_P (XEXP (x
, 0))
933 || (REG_P (XEXP (x
, 0))
934 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
935 || (GET_CODE (XEXP (x
, 0)) == PLUS
936 && REG_P (XEXP (XEXP (x
, 0), 0))
937 && (REGNO (XEXP (XEXP (x
, 0), 0))
938 < FIRST_PSEUDO_REGISTER
)
939 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
940 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
943 /* Make a new stack slot. Then indicate that something
944 changed so we go back and recompute offsets for
945 eliminable registers because the allocation of memory
946 below might change some offset. reg_equiv_{mem,address}
947 will be set up for this pseudo on the next pass around
949 reg_equiv_memory_loc (i
) = 0;
950 reg_equiv_init (i
) = 0;
951 alter_reg (i
, -1, true);
955 if (caller_save_needed
)
958 if (maybe_ne (starting_frame_size
, 0) && crtl
->stack_alignment_needed
)
960 /* If we have a stack frame, we must align it now. The
961 stack size may be a part of the offset computation for
962 register elimination. So if this changes the stack size,
963 then repeat the elimination bookkeeping. We don't
964 realign when there is no stack, as that will cause a
965 stack frame when none is needed should
966 TARGET_STARTING_FRAME_OFFSET not be already aligned to
968 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
970 /* If we allocated another stack slot, redo elimination bookkeeping. */
971 if (something_was_spilled
972 || maybe_ne (starting_frame_size
, get_frame_size ()))
974 if (update_eliminables_and_spill ())
979 if (caller_save_needed
)
981 save_call_clobbered_regs ();
982 /* That might have allocated new insn_chain structures. */
983 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
986 calculate_needs_all_insns (global
);
988 if (! ira_conflicts_p
)
989 /* Don't do it for IRA. We need this info because we don't
990 change live_throughout and dead_or_set for chains when IRA
992 CLEAR_REG_SET (&spilled_pseudos
);
994 something_changed
= 0;
996 /* If we allocated any new memory locations, make another pass
997 since it might have changed elimination offsets. */
998 if (something_was_spilled
999 || maybe_ne (starting_frame_size
, get_frame_size ()))
1000 something_changed
= 1;
1002 /* Even if the frame size remained the same, we might still have
1003 changed elimination offsets, e.g. if find_reloads called
1004 force_const_mem requiring the back end to allocate a constant
1005 pool base register that needs to be saved on the stack. */
1006 else if (!verify_initial_elim_offsets ())
1007 something_changed
= 1;
1009 if (update_eliminables_and_spill ())
1012 something_changed
= 1;
1016 select_reload_regs ();
1019 if (insns_need_reload
)
1020 something_changed
|= finish_spills (global
);
1023 if (! something_changed
)
1026 if (caller_save_needed
)
1027 delete_caller_save_insns ();
1029 obstack_free (&reload_obstack
, reload_firstobj
);
1032 /* If global-alloc was run, notify it of any register eliminations we have
1035 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1036 if (ep
->can_eliminate
)
1037 mark_elimination (ep
->from
, ep
->to
);
1039 remove_init_insns ();
1041 /* Use the reload registers where necessary
1042 by generating move instructions to move the must-be-register
1043 values into or out of the reload registers. */
1045 if (insns_need_reload
!= 0 || something_needs_elimination
1046 || something_needs_operands_changed
)
1048 poly_int64 old_frame_size
= get_frame_size ();
1050 reload_as_needed (global
);
1052 gcc_assert (known_eq (old_frame_size
, get_frame_size ()));
1054 gcc_assert (verify_initial_elim_offsets ());
1057 /* If we were able to eliminate the frame pointer, show that it is no
1058 longer live at the start of any basic block. If it ls live by
1059 virtue of being in a pseudo, that pseudo will be marked live
1060 and hence the frame pointer will be known to be live via that
1063 if (! frame_pointer_needed
)
1064 FOR_EACH_BB_FN (bb
, cfun
)
1065 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1067 /* Come here (with failure set nonzero) if we can't get enough spill
1071 CLEAR_REG_SET (&changed_allocation_pseudos
);
1072 CLEAR_REG_SET (&spilled_pseudos
);
1073 reload_in_progress
= 0;
1075 /* Now eliminate all pseudo regs by modifying them into
1076 their equivalent memory references.
1077 The REG-rtx's for the pseudos are modified in place,
1078 so all insns that used to refer to them now refer to memory.
1080 For a reg that has a reg_equiv_address, all those insns
1081 were changed by reloading so that no insns refer to it any longer;
1082 but the DECL_RTL of a variable decl may refer to it,
1083 and if so this causes the debugging info to mention the variable. */
1085 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1089 if (reg_equiv_mem (i
))
1090 addr
= XEXP (reg_equiv_mem (i
), 0);
1092 if (reg_equiv_address (i
))
1093 addr
= reg_equiv_address (i
);
1097 if (reg_renumber
[i
] < 0)
1099 rtx reg
= regno_reg_rtx
[i
];
1101 REG_USERVAR_P (reg
) = 0;
1102 PUT_CODE (reg
, MEM
);
1103 XEXP (reg
, 0) = addr
;
1104 if (reg_equiv_memory_loc (i
))
1105 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1107 MEM_ATTRS (reg
) = 0;
1108 MEM_NOTRAP_P (reg
) = 1;
1110 else if (reg_equiv_mem (i
))
1111 XEXP (reg_equiv_mem (i
), 0) = addr
;
1114 /* We don't want complex addressing modes in debug insns
1115 if simpler ones will do, so delegitimize equivalences
1117 if (MAY_HAVE_DEBUG_BIND_INSNS
&& reg_renumber
[i
] < 0)
1119 rtx reg
= regno_reg_rtx
[i
];
1123 if (reg_equiv_constant (i
))
1124 equiv
= reg_equiv_constant (i
);
1125 else if (reg_equiv_invariant (i
))
1126 equiv
= reg_equiv_invariant (i
);
1127 else if (reg
&& MEM_P (reg
))
1128 equiv
= targetm
.delegitimize_address (reg
);
1129 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1135 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1137 insn
= DF_REF_INSN (use
);
1139 /* Make sure the next ref is for a different instruction,
1140 so that we're not affected by the rescan. */
1141 next
= DF_REF_NEXT_REG (use
);
1142 while (next
&& DF_REF_INSN (next
) == insn
)
1143 next
= DF_REF_NEXT_REG (next
);
1145 if (DEBUG_BIND_INSN_P (insn
))
1149 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1150 df_insn_rescan_debug_internal (insn
);
1153 INSN_VAR_LOCATION_LOC (insn
)
1154 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1161 /* We must set reload_completed now since the cleanup_subreg_operands call
1162 below will re-recognize each insn and reload may have generated insns
1163 which are only valid during and after reload. */
1164 reload_completed
= 1;
1166 /* Make a pass over all the insns and delete all USEs which we inserted
1167 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1168 notes. Delete all CLOBBER insns, except those that refer to the return
1169 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1170 from misarranging variable-array code, and simplify (subreg (reg))
1171 operands. Strip and regenerate REG_INC notes that may have been moved
1174 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1180 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1181 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1183 if ((GET_CODE (PATTERN (insn
)) == USE
1184 /* We mark with QImode USEs introduced by reload itself. */
1185 && (GET_MODE (insn
) == QImode
1186 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1187 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1188 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1189 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1190 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1191 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1192 != stack_pointer_rtx
))
1193 && (!REG_P (XEXP (PATTERN (insn
), 0))
1194 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1200 /* Some CLOBBERs may survive until here and still reference unassigned
1201 pseudos with const equivalent, which may in turn cause ICE in later
1202 passes if the reference remains in place. */
1203 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1204 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1205 VOIDmode
, PATTERN (insn
));
1207 /* Discard obvious no-ops, even without -O. This optimization
1208 is fast and doesn't interfere with debugging. */
1209 if (NONJUMP_INSN_P (insn
)
1210 && GET_CODE (PATTERN (insn
)) == SET
1211 && REG_P (SET_SRC (PATTERN (insn
)))
1212 && REG_P (SET_DEST (PATTERN (insn
)))
1213 && (REGNO (SET_SRC (PATTERN (insn
)))
1214 == REGNO (SET_DEST (PATTERN (insn
)))))
1220 pnote
= ®_NOTES (insn
);
1223 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1224 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1225 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1226 *pnote
= XEXP (*pnote
, 1);
1228 pnote
= &XEXP (*pnote
, 1);
1232 add_auto_inc_notes (insn
, PATTERN (insn
));
1234 /* Simplify (subreg (reg)) if it appears as an operand. */
1235 cleanup_subreg_operands (insn
);
1237 /* Clean up invalid ASMs so that they don't confuse later passes.
1239 if (asm_noperands (PATTERN (insn
)) >= 0)
1241 extract_insn (insn
);
1242 if (!constrain_operands (1, get_enabled_alternatives (insn
)))
1244 error_for_asm (insn
,
1245 "%<asm%> operand has impossible constraints");
1252 free (temp_pseudo_reg_arr
);
1254 /* Indicate that we no longer have known memory locations or constants. */
1257 free (reg_max_ref_mode
);
1258 free (reg_old_renumber
);
1259 free (pseudo_previous_regs
);
1260 free (pseudo_forbidden_regs
);
1262 CLEAR_HARD_REG_SET (used_spill_regs
);
1263 for (i
= 0; i
< n_spills
; i
++)
1264 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1266 /* Free all the insn_chain structures at once. */
1267 obstack_free (&reload_obstack
, reload_startobj
);
1268 unused_insn_chains
= 0;
1270 inserted
= fixup_abnormal_edges ();
1272 /* We've possibly turned single trapping insn into multiple ones. */
1273 if (cfun
->can_throw_non_call_exceptions
)
1275 auto_sbitmap
blocks (last_basic_block_for_fn (cfun
));
1276 bitmap_ones (blocks
);
1277 find_many_sub_basic_blocks (blocks
);
1281 commit_edge_insertions ();
1283 /* Replacing pseudos with their memory equivalents might have
1284 created shared rtx. Subsequent passes would get confused
1285 by this, so unshare everything here. */
1286 unshare_all_rtl_again (first
);
1288 #ifdef STACK_BOUNDARY
1289 /* init_emit has set the alignment of the hard frame pointer
1290 to STACK_BOUNDARY. It is very likely no longer valid if
1291 the hard frame pointer was used for register allocation. */
1292 if (!frame_pointer_needed
)
1293 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1296 substitute_stack
.release ();
1298 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1300 reload_completed
= !failure
;
1305 /* Yet another special case. Unfortunately, reg-stack forces people to
1306 write incorrect clobbers in asm statements. These clobbers must not
1307 cause the register to appear in bad_spill_regs, otherwise we'll call
1308 fatal_insn later. We clear the corresponding regnos in the live
1309 register sets to avoid this.
1310 The whole thing is rather sick, I'm afraid. */
1313 maybe_fix_stack_asms (void)
1316 const char *constraints
[MAX_RECOG_OPERANDS
];
1317 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1318 class insn_chain
*chain
;
1320 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1323 HARD_REG_SET clobbered
, allowed
;
1326 if (! INSN_P (chain
->insn
)
1327 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1329 pat
= PATTERN (chain
->insn
);
1330 if (GET_CODE (pat
) != PARALLEL
)
1333 CLEAR_HARD_REG_SET (clobbered
);
1334 CLEAR_HARD_REG_SET (allowed
);
1336 /* First, make a mask of all stack regs that are clobbered. */
1337 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1339 rtx t
= XVECEXP (pat
, 0, i
);
1340 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1341 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1342 /* CLOBBER_HIGH is only supported for LRA. */
1343 gcc_assert (GET_CODE (t
) != CLOBBER_HIGH
);
1346 /* Get the operand values and constraints out of the insn. */
1347 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1348 constraints
, operand_mode
, NULL
);
1350 /* For every operand, see what registers are allowed. */
1351 for (i
= 0; i
< noperands
; i
++)
1353 const char *p
= constraints
[i
];
1354 /* For every alternative, we compute the class of registers allowed
1355 for reloading in CLS, and merge its contents into the reg set
1357 int cls
= (int) NO_REGS
;
1363 if (c
== '\0' || c
== ',' || c
== '#')
1365 /* End of one alternative - mark the regs in the current
1366 class, and reset the class. */
1367 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1373 } while (c
!= '\0' && c
!= ',');
1382 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1386 enum constraint_num cn
= lookup_constraint (p
);
1387 if (insn_extra_address_constraint (cn
))
1388 cls
= (int) reg_class_subunion
[cls
]
1389 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1392 cls
= (int) reg_class_subunion
[cls
]
1393 [reg_class_for_constraint (cn
)];
1396 p
+= CONSTRAINT_LEN (c
, p
);
1399 /* Those of the registers which are clobbered, but allowed by the
1400 constraints, must be usable as reload registers. So clear them
1401 out of the life information. */
1402 AND_HARD_REG_SET (allowed
, clobbered
);
1403 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1404 if (TEST_HARD_REG_BIT (allowed
, i
))
1406 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1407 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1414 /* Copy the global variables n_reloads and rld into the corresponding elts
1417 copy_reloads (class insn_chain
*chain
)
1419 chain
->n_reloads
= n_reloads
;
1420 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1421 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1422 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1425 /* Walk the chain of insns, and determine for each whether it needs reloads
1426 and/or eliminations. Build the corresponding insns_need_reload list, and
1427 set something_needs_elimination as appropriate. */
1429 calculate_needs_all_insns (int global
)
1431 class insn_chain
**pprev_reload
= &insns_need_reload
;
1432 class insn_chain
*chain
, *next
= 0;
1434 something_needs_elimination
= 0;
1436 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1437 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1439 rtx_insn
*insn
= chain
->insn
;
1443 /* Clear out the shortcuts. */
1444 chain
->n_reloads
= 0;
1445 chain
->need_elim
= 0;
1446 chain
->need_reload
= 0;
1447 chain
->need_operand_change
= 0;
1449 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1450 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1451 what effects this has on the known offsets at labels. */
1453 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1454 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1455 set_label_offsets (insn
, insn
, 0);
1459 rtx old_body
= PATTERN (insn
);
1460 int old_code
= INSN_CODE (insn
);
1461 rtx old_notes
= REG_NOTES (insn
);
1462 int did_elimination
= 0;
1463 int operands_changed
= 0;
1465 /* Skip insns that only set an equivalence. */
1466 if (will_delete_init_insn_p (insn
))
1469 /* If needed, eliminate any eliminable registers. */
1470 if (num_eliminable
|| num_eliminable_invariants
)
1471 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1473 /* Analyze the instruction. */
1474 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1475 global
, spill_reg_order
);
1477 /* If a no-op set needs more than one reload, this is likely
1478 to be something that needs input address reloads. We
1479 can't get rid of this cleanly later, and it is of no use
1480 anyway, so discard it now.
1481 We only do this when expensive_optimizations is enabled,
1482 since this complements reload inheritance / output
1483 reload deletion, and it can make debugging harder. */
1484 if (flag_expensive_optimizations
&& n_reloads
> 1)
1486 rtx set
= single_set (insn
);
1489 ((SET_SRC (set
) == SET_DEST (set
)
1490 && REG_P (SET_SRC (set
))
1491 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1492 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1493 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1494 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1495 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1496 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1497 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1498 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1500 if (ira_conflicts_p
)
1501 /* Inform IRA about the insn deletion. */
1502 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1503 REGNO (SET_SRC (set
)));
1505 /* Delete it from the reload chain. */
1507 chain
->prev
->next
= next
;
1509 reload_insn_chain
= next
;
1511 next
->prev
= chain
->prev
;
1512 chain
->next
= unused_insn_chains
;
1513 unused_insn_chains
= chain
;
1518 update_eliminable_offsets ();
1520 /* Remember for later shortcuts which insns had any reloads or
1521 register eliminations. */
1522 chain
->need_elim
= did_elimination
;
1523 chain
->need_reload
= n_reloads
> 0;
1524 chain
->need_operand_change
= operands_changed
;
1526 /* Discard any register replacements done. */
1527 if (did_elimination
)
1529 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1530 PATTERN (insn
) = old_body
;
1531 INSN_CODE (insn
) = old_code
;
1532 REG_NOTES (insn
) = old_notes
;
1533 something_needs_elimination
= 1;
1536 something_needs_operands_changed
|= operands_changed
;
1540 copy_reloads (chain
);
1541 *pprev_reload
= chain
;
1542 pprev_reload
= &chain
->next_need_reload
;
1549 /* This function is called from the register allocator to set up estimates
1550 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1551 an invariant. The structure is similar to calculate_needs_all_insns. */
1554 calculate_elim_costs_all_insns (void)
1556 int *reg_equiv_init_cost
;
1560 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1562 init_eliminable_invariants (get_insns (), false);
1564 set_initial_elim_offsets ();
1565 set_initial_label_offsets ();
1567 FOR_EACH_BB_FN (bb
, cfun
)
1572 FOR_BB_INSNS (bb
, insn
)
1574 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1575 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1576 what effects this has on the known offsets at labels. */
1578 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1579 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1580 set_label_offsets (insn
, insn
, 0);
1584 rtx set
= single_set (insn
);
1586 /* Skip insns that only set an equivalence. */
1587 if (set
&& REG_P (SET_DEST (set
))
1588 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1589 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1590 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1592 unsigned regno
= REGNO (SET_DEST (set
));
1593 rtx_insn_list
*init
= reg_equiv_init (regno
);
1596 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1598 machine_mode mode
= GET_MODE (SET_DEST (set
));
1599 int cost
= set_src_cost (t
, mode
,
1600 optimize_bb_for_speed_p (bb
));
1601 int freq
= REG_FREQ_FROM_BB (bb
);
1603 reg_equiv_init_cost
[regno
] = cost
* freq
;
1607 /* If needed, eliminate any eliminable registers. */
1608 if (num_eliminable
|| num_eliminable_invariants
)
1609 elimination_costs_in_insn (insn
);
1612 update_eliminable_offsets ();
1616 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1618 if (reg_equiv_invariant (i
))
1620 if (reg_equiv_init (i
))
1622 int cost
= reg_equiv_init_cost
[i
];
1625 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1627 ira_adjust_equiv_reg_cost (i
, cost
);
1633 "Reg %d had equivalence, but can't be eliminated\n",
1635 ira_adjust_equiv_reg_cost (i
, 0);
1640 free (reg_equiv_init_cost
);
1641 free (offsets_known_at
);
1644 offsets_known_at
= NULL
;
1647 /* Comparison function for qsort to decide which of two reloads
1648 should be handled first. *P1 and *P2 are the reload numbers. */
1651 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1653 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1656 /* Consider required reloads before optional ones. */
1657 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1661 /* Count all solitary classes before non-solitary ones. */
1662 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1663 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1667 /* Aside from solitaires, consider all multi-reg groups first. */
1668 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1672 /* Consider reloads in order of increasing reg-class number. */
1673 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1677 /* If reloads are equally urgent, sort by reload number,
1678 so that the results of qsort leave nothing to chance. */
1682 /* The cost of spilling each hard reg. */
1683 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1685 /* When spilling multiple hard registers, we use SPILL_COST for the first
1686 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1687 only the first hard reg for a multi-reg pseudo. */
1688 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1690 /* Map of hard regno to pseudo regno currently occupying the hard
1692 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1694 /* Update the spill cost arrays, considering that pseudo REG is live. */
1697 count_pseudo (int reg
)
1699 int freq
= REG_FREQ (reg
);
1700 int r
= reg_renumber
[reg
];
1703 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1704 if (ira_conflicts_p
&& r
< 0)
1707 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1708 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1711 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1713 gcc_assert (r
>= 0);
1715 spill_add_cost
[r
] += freq
;
1716 nregs
= hard_regno_nregs (r
, PSEUDO_REGNO_MODE (reg
));
1719 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1720 spill_cost
[r
+ nregs
] += freq
;
1724 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1725 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1728 order_regs_for_reload (class insn_chain
*chain
)
1731 HARD_REG_SET used_by_pseudos
;
1732 HARD_REG_SET used_by_pseudos2
;
1733 reg_set_iterator rsi
;
1735 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1737 memset (spill_cost
, 0, sizeof spill_cost
);
1738 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1739 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1740 hard_regno_to_pseudo_regno
[i
] = -1;
1742 /* Count number of uses of each hard reg by pseudo regs allocated to it
1743 and then order them by decreasing use. First exclude hard registers
1744 that are live in or across this insn. */
1746 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1747 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1748 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1749 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1751 /* Now find out which pseudos are allocated to it, and update
1753 CLEAR_REG_SET (&pseudos_counted
);
1755 EXECUTE_IF_SET_IN_REG_SET
1756 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1760 EXECUTE_IF_SET_IN_REG_SET
1761 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1765 CLEAR_REG_SET (&pseudos_counted
);
1768 /* Vector of reload-numbers showing the order in which the reloads should
1770 static short reload_order
[MAX_RELOADS
];
1772 /* This is used to keep track of the spill regs used in one insn. */
1773 static HARD_REG_SET used_spill_regs_local
;
1775 /* We decided to spill hard register SPILLED, which has a size of
1776 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1777 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1778 update SPILL_COST/SPILL_ADD_COST. */
1781 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1783 int freq
= REG_FREQ (reg
);
1784 int r
= reg_renumber
[reg
];
1787 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1788 if (ira_conflicts_p
&& r
< 0)
1791 gcc_assert (r
>= 0);
1793 nregs
= hard_regno_nregs (r
, PSEUDO_REGNO_MODE (reg
));
1795 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1796 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1799 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1801 spill_add_cost
[r
] -= freq
;
1804 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1805 spill_cost
[r
+ nregs
] -= freq
;
1809 /* Find reload register to use for reload number ORDER. */
1812 find_reg (class insn_chain
*chain
, int order
)
1814 int rnum
= reload_order
[order
];
1815 struct reload
*rl
= rld
+ rnum
;
1816 int best_cost
= INT_MAX
;
1818 unsigned int i
, j
, n
;
1820 HARD_REG_SET not_usable
;
1821 HARD_REG_SET used_by_other_reload
;
1822 reg_set_iterator rsi
;
1823 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1824 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1826 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1827 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1828 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1830 CLEAR_HARD_REG_SET (used_by_other_reload
);
1831 for (k
= 0; k
< order
; k
++)
1833 int other
= reload_order
[k
];
1835 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1836 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1837 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1840 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1842 #ifdef REG_ALLOC_ORDER
1843 unsigned int regno
= reg_alloc_order
[i
];
1845 unsigned int regno
= i
;
1848 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1849 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1850 && targetm
.hard_regno_mode_ok (regno
, rl
->mode
))
1852 int this_cost
= spill_cost
[regno
];
1854 unsigned int this_nregs
= hard_regno_nregs (regno
, rl
->mode
);
1856 for (j
= 1; j
< this_nregs
; j
++)
1858 this_cost
+= spill_add_cost
[regno
+ j
];
1859 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1860 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1866 if (ira_conflicts_p
)
1868 /* Ask IRA to find a better pseudo-register for
1870 for (n
= j
= 0; j
< this_nregs
; j
++)
1872 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1876 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1877 regno_pseudo_regs
[n
++] = r
;
1879 regno_pseudo_regs
[n
++] = -1;
1881 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1882 best_regno_pseudo_regs
,
1889 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1890 if (regno_pseudo_regs
[j
] < 0)
1897 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1899 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1901 if (this_cost
< best_cost
1902 /* Among registers with equal cost, prefer caller-saved ones, or
1903 use REG_ALLOC_ORDER if it is defined. */
1904 || (this_cost
== best_cost
1905 #ifdef REG_ALLOC_ORDER
1906 && (inv_reg_alloc_order
[regno
]
1907 < inv_reg_alloc_order
[best_reg
])
1909 && call_used_regs
[regno
]
1910 && ! call_used_regs
[best_reg
]
1915 best_cost
= this_cost
;
1923 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1925 rl
->nregs
= hard_regno_nregs (best_reg
, rl
->mode
);
1926 rl
->regno
= best_reg
;
1928 EXECUTE_IF_SET_IN_REG_SET
1929 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1931 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1934 EXECUTE_IF_SET_IN_REG_SET
1935 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1937 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1940 for (i
= 0; i
< rl
->nregs
; i
++)
1942 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1943 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1944 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1945 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1950 /* Find more reload regs to satisfy the remaining need of an insn, which
1952 Do it by ascending class number, since otherwise a reg
1953 might be spilled for a big class and might fail to count
1954 for a smaller class even though it belongs to that class. */
1957 find_reload_regs (class insn_chain
*chain
)
1961 /* In order to be certain of getting the registers we need,
1962 we must sort the reloads into order of increasing register class.
1963 Then our grabbing of reload registers will parallel the process
1964 that provided the reload registers. */
1965 for (i
= 0; i
< chain
->n_reloads
; i
++)
1967 /* Show whether this reload already has a hard reg. */
1968 if (chain
->rld
[i
].reg_rtx
)
1970 chain
->rld
[i
].regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1971 chain
->rld
[i
].nregs
= REG_NREGS (chain
->rld
[i
].reg_rtx
);
1974 chain
->rld
[i
].regno
= -1;
1975 reload_order
[i
] = i
;
1978 n_reloads
= chain
->n_reloads
;
1979 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1981 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1984 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1986 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1988 /* Compute the order of preference for hard registers to spill. */
1990 order_regs_for_reload (chain
);
1992 for (i
= 0; i
< n_reloads
; i
++)
1994 int r
= reload_order
[i
];
1996 /* Ignore reloads that got marked inoperative. */
1997 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1998 && ! rld
[r
].optional
1999 && rld
[r
].regno
== -1)
2000 if (! find_reg (chain
, i
))
2003 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2004 spill_failure (chain
->insn
, rld
[r
].rclass
);
2010 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2011 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2013 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2017 select_reload_regs (void)
2019 class insn_chain
*chain
;
2021 /* Try to satisfy the needs for each insn. */
2022 for (chain
= insns_need_reload
; chain
!= 0;
2023 chain
= chain
->next_need_reload
)
2024 find_reload_regs (chain
);
2027 /* Delete all insns that were inserted by emit_caller_save_insns during
2030 delete_caller_save_insns (void)
2032 class insn_chain
*c
= reload_insn_chain
;
2036 while (c
!= 0 && c
->is_caller_save_insn
)
2038 class insn_chain
*next
= c
->next
;
2039 rtx_insn
*insn
= c
->insn
;
2041 if (c
== reload_insn_chain
)
2042 reload_insn_chain
= next
;
2046 next
->prev
= c
->prev
;
2048 c
->prev
->next
= next
;
2049 c
->next
= unused_insn_chains
;
2050 unused_insn_chains
= c
;
2058 /* Handle the failure to find a register to spill.
2059 INSN should be one of the insns which needed this particular spill reg. */
2062 spill_failure (rtx_insn
*insn
, enum reg_class rclass
)
2064 if (asm_noperands (PATTERN (insn
)) >= 0)
2065 error_for_asm (insn
, "cannot find a register in class %qs while "
2066 "reloading %<asm%>",
2067 reg_class_names
[rclass
]);
2070 error ("unable to find a register to spill in class %qs",
2071 reg_class_names
[rclass
]);
2075 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2076 debug_reload_to_stream (dump_file
);
2078 fatal_insn ("this is the insn:", insn
);
2082 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2083 data that is dead in INSN. */
2086 delete_dead_insn (rtx_insn
*insn
)
2088 rtx_insn
*prev
= prev_active_insn (insn
);
2091 /* If the previous insn sets a register that dies in our insn make
2092 a note that we want to run DCE immediately after reload.
2094 We used to delete the previous insn & recurse, but that's wrong for
2095 block local equivalences. Instead of trying to figure out the exact
2096 circumstances where we can delete the potentially dead insns, just
2097 let DCE do the job. */
2098 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2099 && GET_CODE (PATTERN (prev
)) == SET
2100 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2101 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2102 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2103 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2106 SET_INSN_DELETED (insn
);
2109 /* Modify the home of pseudo-reg I.
2110 The new home is present in reg_renumber[I].
2112 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2113 or it may be -1, meaning there is none or it is not relevant.
2114 This is used so that all pseudos spilled from a given hard reg
2115 can share one stack slot. */
2118 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2120 /* When outputting an inline function, this can happen
2121 for a reg that isn't actually used. */
2122 if (regno_reg_rtx
[i
] == 0)
2125 /* If the reg got changed to a MEM at rtl-generation time,
2127 if (!REG_P (regno_reg_rtx
[i
]))
2130 /* Modify the reg-rtx to contain the new hard reg
2131 number or else to contain its pseudo reg number. */
2132 SET_REGNO (regno_reg_rtx
[i
],
2133 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2135 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2136 allocate a stack slot for it. */
2138 if (reg_renumber
[i
] < 0
2139 && REG_N_REFS (i
) > 0
2140 && reg_equiv_constant (i
) == 0
2141 && (reg_equiv_invariant (i
) == 0
2142 || reg_equiv_init (i
) == 0)
2143 && reg_equiv_memory_loc (i
) == 0)
2146 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2147 poly_uint64 inherent_size
= GET_MODE_SIZE (mode
);
2148 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2149 machine_mode wider_mode
= wider_subreg_mode (mode
, reg_max_ref_mode
[i
]);
2150 poly_uint64 total_size
= GET_MODE_SIZE (wider_mode
);
2151 /* ??? Seems strange to derive the minimum alignment from the size,
2152 but that's the traditional behavior. For polynomial-size modes,
2153 the natural extension is to use the minimum possible size. */
2154 unsigned int min_align
2155 = constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode
[i
]));
2156 poly_int64 adjust
= 0;
2158 something_was_spilled
= true;
2160 if (ira_conflicts_p
)
2162 /* Mark the spill for IRA. */
2163 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2165 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2171 /* Each pseudo reg has an inherent size which comes from its own mode,
2172 and a total size which provides room for paradoxical subregs
2173 which refer to the pseudo reg in wider modes.
2175 We can use a slot already allocated if it provides both
2176 enough inherent space and enough total space.
2177 Otherwise, we allocate a new slot, making sure that it has no less
2178 inherent space, and no less total space, then the previous slot. */
2179 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2183 /* The sizes are taken from a subreg operation, which guarantees
2184 that they're ordered. */
2185 gcc_checking_assert (ordered_p (total_size
, inherent_size
));
2187 /* No known place to spill from => no slot to reuse. */
2188 x
= assign_stack_local (mode
, total_size
,
2189 min_align
> inherent_align
2190 || maybe_gt (total_size
, inherent_size
)
2195 /* Cancel the big-endian correction done in assign_stack_local.
2196 Get the address of the beginning of the slot. This is so we
2197 can do a big-endian correction unconditionally below. */
2198 if (BYTES_BIG_ENDIAN
)
2200 adjust
= inherent_size
- total_size
;
2201 if (maybe_ne (adjust
, 0))
2203 poly_uint64 total_bits
= total_size
* BITS_PER_UNIT
;
2204 machine_mode mem_mode
2205 = int_mode_for_size (total_bits
, 1).else_blk ();
2206 stack_slot
= adjust_address_nv (x
, mem_mode
, adjust
);
2210 if (! dont_share_p
&& ira_conflicts_p
)
2211 /* Inform IRA about allocation a new stack slot. */
2212 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2215 /* Reuse a stack slot if possible. */
2216 else if (spill_stack_slot
[from_reg
] != 0
2217 && known_ge (spill_stack_slot_width
[from_reg
], total_size
)
2218 && known_ge (GET_MODE_SIZE
2219 (GET_MODE (spill_stack_slot
[from_reg
])),
2221 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2222 x
= spill_stack_slot
[from_reg
];
2224 /* Allocate a bigger slot. */
2227 /* Compute maximum size needed, both for inherent size
2228 and for total size. */
2231 if (spill_stack_slot
[from_reg
])
2233 if (partial_subreg_p (mode
,
2234 GET_MODE (spill_stack_slot
[from_reg
])))
2235 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2236 total_size
= ordered_max (total_size
,
2237 spill_stack_slot_width
[from_reg
]);
2238 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2239 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2242 /* The sizes are taken from a subreg operation, which guarantees
2243 that they're ordered. */
2244 gcc_checking_assert (ordered_p (total_size
, inherent_size
));
2246 /* Make a slot with that size. */
2247 x
= assign_stack_local (mode
, total_size
,
2248 min_align
> inherent_align
2249 || maybe_gt (total_size
, inherent_size
)
2253 /* Cancel the big-endian correction done in assign_stack_local.
2254 Get the address of the beginning of the slot. This is so we
2255 can do a big-endian correction unconditionally below. */
2256 if (BYTES_BIG_ENDIAN
)
2258 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2259 if (maybe_ne (adjust
, 0))
2261 poly_uint64 total_bits
= total_size
* BITS_PER_UNIT
;
2262 machine_mode mem_mode
2263 = int_mode_for_size (total_bits
, 1).else_blk ();
2264 stack_slot
= adjust_address_nv (x
, mem_mode
, adjust
);
2268 spill_stack_slot
[from_reg
] = stack_slot
;
2269 spill_stack_slot_width
[from_reg
] = total_size
;
2272 /* On a big endian machine, the "address" of the slot
2273 is the address of the low part that fits its inherent mode. */
2274 adjust
+= subreg_size_lowpart_offset (inherent_size
, total_size
);
2276 /* If we have any adjustment to make, or if the stack slot is the
2277 wrong mode, make a new stack slot. */
2278 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2280 /* Set all of the memory attributes as appropriate for a spill. */
2281 set_mem_attrs_for_spill (x
);
2283 /* Save the stack slot for later. */
2284 reg_equiv_memory_loc (i
) = x
;
2288 /* Mark the slots in regs_ever_live for the hard regs used by
2289 pseudo-reg number REGNO, accessed in MODE. */
2292 mark_home_live_1 (int regno
, machine_mode mode
)
2296 i
= reg_renumber
[regno
];
2299 lim
= end_hard_regno (mode
, i
);
2301 df_set_regs_ever_live (i
++, true);
2304 /* Mark the slots in regs_ever_live for the hard regs
2305 used by pseudo-reg number REGNO. */
2308 mark_home_live (int regno
)
2310 if (reg_renumber
[regno
] >= 0)
2311 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2314 /* This function handles the tracking of elimination offsets around branches.
2316 X is a piece of RTL being scanned.
2318 INSN is the insn that it came from, if any.
2320 INITIAL_P is nonzero if we are to set the offset to be the initial
2321 offset and zero if we are setting the offset of the label to be the
2325 set_label_offsets (rtx x
, rtx_insn
*insn
, int initial_p
)
2327 enum rtx_code code
= GET_CODE (x
);
2330 struct elim_table
*p
;
2335 if (LABEL_REF_NONLOCAL_P (x
))
2338 x
= label_ref_label (x
);
2343 /* If we know nothing about this label, set the desired offsets. Note
2344 that this sets the offset at a label to be the offset before a label
2345 if we don't know anything about the label. This is not correct for
2346 the label after a BARRIER, but is the best guess we can make. If
2347 we guessed wrong, we will suppress an elimination that might have
2348 been possible had we been able to guess correctly. */
2350 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2352 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2353 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2354 = (initial_p
? reg_eliminate
[i
].initial_offset
2355 : reg_eliminate
[i
].offset
);
2356 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2359 /* Otherwise, if this is the definition of a label and it is
2360 preceded by a BARRIER, set our offsets to the known offset of
2364 && (tem
= prev_nonnote_insn (insn
)) != 0
2366 set_offsets_for_label (insn
);
2368 /* If neither of the above cases is true, compare each offset
2369 with those previously recorded and suppress any eliminations
2370 where the offsets disagree. */
2372 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2373 if (maybe_ne (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
],
2374 (initial_p
? reg_eliminate
[i
].initial_offset
2375 : reg_eliminate
[i
].offset
)))
2376 reg_eliminate
[i
].can_eliminate
= 0;
2380 case JUMP_TABLE_DATA
:
2381 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2385 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2391 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2392 to indirectly and hence must have all eliminations at their
2394 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2395 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2396 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2402 /* Each of the labels in the parallel or address vector must be
2403 at their initial offsets. We want the first field for PARALLEL
2404 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2406 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2407 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2412 /* We only care about setting PC. If the source is not RETURN,
2413 IF_THEN_ELSE, or a label, disable any eliminations not at
2414 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2415 isn't one of those possibilities. For branches to a label,
2416 call ourselves recursively.
2418 Note that this can disable elimination unnecessarily when we have
2419 a non-local goto since it will look like a non-constant jump to
2420 someplace in the current function. This isn't a significant
2421 problem since such jumps will normally be when all elimination
2422 pairs are back to their initial offsets. */
2424 if (SET_DEST (x
) != pc_rtx
)
2427 switch (GET_CODE (SET_SRC (x
)))
2434 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2438 tem
= XEXP (SET_SRC (x
), 1);
2439 if (GET_CODE (tem
) == LABEL_REF
)
2440 set_label_offsets (label_ref_label (tem
), insn
, initial_p
);
2441 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2444 tem
= XEXP (SET_SRC (x
), 2);
2445 if (GET_CODE (tem
) == LABEL_REF
)
2446 set_label_offsets (label_ref_label (tem
), insn
, initial_p
);
2447 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2455 /* If we reach here, all eliminations must be at their initial
2456 offset because we are doing a jump to a variable address. */
2457 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2458 if (maybe_ne (p
->offset
, p
->initial_offset
))
2459 p
->can_eliminate
= 0;
2467 /* This function examines every reg that occurs in X and adjusts the
2468 costs for its elimination which are gathered by IRA. INSN is the
2469 insn in which X occurs. We do not recurse into MEM expressions. */
2472 note_reg_elim_costly (const_rtx x
, rtx insn
)
2474 subrtx_iterator::array_type array
;
2475 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
2477 const_rtx x
= *iter
;
2479 iter
.skip_subrtxes ();
2481 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2482 && reg_equiv_init (REGNO (x
))
2483 && reg_equiv_invariant (REGNO (x
)))
2485 rtx t
= reg_equiv_invariant (REGNO (x
));
2486 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2487 int cost
= set_src_cost (new_rtx
, Pmode
,
2488 optimize_bb_for_speed_p (elim_bb
));
2489 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2492 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2497 /* Scan X and replace any eliminable registers (such as fp) with a
2498 replacement (such as sp), plus an offset.
2500 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2501 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2502 MEM, we are allowed to replace a sum of a register and the constant zero
2503 with the register, which we cannot do outside a MEM. In addition, we need
2504 to record the fact that a register is referenced outside a MEM.
2506 If INSN is an insn, it is the insn containing X. If we replace a REG
2507 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2508 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2509 the REG is being modified.
2511 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2512 That's used when we eliminate in expressions stored in notes.
2513 This means, do not set ref_outside_mem even if the reference
2516 If FOR_COSTS is true, we are being called before reload in order to
2517 estimate the costs of keeping registers with an equivalence unallocated.
2519 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2520 replacements done assuming all offsets are at their initial values. If
2521 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2522 encounter, return the actual location so that find_reloads will do
2523 the proper thing. */
2526 eliminate_regs_1 (rtx x
, machine_mode mem_mode
, rtx insn
,
2527 bool may_use_invariant
, bool for_costs
)
2529 enum rtx_code code
= GET_CODE (x
);
2530 struct elim_table
*ep
;
2537 if (! current_function_decl
)
2557 /* First handle the case where we encounter a bare register that
2558 is eliminable. Replace it with a PLUS. */
2559 if (regno
< FIRST_PSEUDO_REGISTER
)
2561 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2563 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2564 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2567 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2569 && reg_equiv_invariant (regno
))
2571 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2572 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2573 mem_mode
, insn
, true, for_costs
);
2574 /* There exists at least one use of REGNO that cannot be
2575 eliminated. Prevent the defining insn from being deleted. */
2576 reg_equiv_init (regno
) = NULL
;
2578 alter_reg (regno
, -1, true);
2582 /* You might think handling MINUS in a manner similar to PLUS is a
2583 good idea. It is not. It has been tried multiple times and every
2584 time the change has had to have been reverted.
2586 Other parts of reload know a PLUS is special (gen_reload for example)
2587 and require special code to handle code a reloaded PLUS operand.
2589 Also consider backends where the flags register is clobbered by a
2590 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2591 lea instruction comes to mind). If we try to reload a MINUS, we
2592 may kill the flags register that was holding a useful value.
2594 So, please before trying to handle MINUS, consider reload as a
2595 whole instead of this little section as well as the backend issues. */
2597 /* If this is the sum of an eliminable register and a constant, rework
2599 if (REG_P (XEXP (x
, 0))
2600 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2601 && CONSTANT_P (XEXP (x
, 1)))
2603 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2605 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2607 /* The only time we want to replace a PLUS with a REG (this
2608 occurs when the constant operand of the PLUS is the negative
2609 of the offset) is when we are inside a MEM. We won't want
2610 to do so at other times because that would change the
2611 structure of the insn in a way that reload can't handle.
2612 We special-case the commonest situation in
2613 eliminate_regs_in_insn, so just replace a PLUS with a
2614 PLUS here, unless inside a MEM. */
2616 && CONST_INT_P (XEXP (x
, 1))
2617 && known_eq (INTVAL (XEXP (x
, 1)), -ep
->previous_offset
))
2620 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2621 plus_constant (Pmode
, XEXP (x
, 1),
2622 ep
->previous_offset
));
2625 /* If the register is not eliminable, we are done since the other
2626 operand is a constant. */
2630 /* If this is part of an address, we want to bring any constant to the
2631 outermost PLUS. We will do this by doing register replacement in
2632 our operands and seeing if a constant shows up in one of them.
2634 Note that there is no risk of modifying the structure of the insn,
2635 since we only get called for its operands, thus we are either
2636 modifying the address inside a MEM, or something like an address
2637 operand of a load-address insn. */
2640 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2642 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2645 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2647 /* If one side is a PLUS and the other side is a pseudo that
2648 didn't get a hard register but has a reg_equiv_constant,
2649 we must replace the constant here since it may no longer
2650 be in the position of any operand. */
2651 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2652 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2653 && reg_renumber
[REGNO (new1
)] < 0
2655 && reg_equiv_constant (REGNO (new1
)) != 0)
2656 new1
= reg_equiv_constant (REGNO (new1
));
2657 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2658 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2659 && reg_renumber
[REGNO (new0
)] < 0
2660 && reg_equiv_constant (REGNO (new0
)) != 0)
2661 new0
= reg_equiv_constant (REGNO (new0
));
2663 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2665 /* As above, if we are not inside a MEM we do not want to
2666 turn a PLUS into something else. We might try to do so here
2667 for an addition of 0 if we aren't optimizing. */
2668 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2669 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2677 /* If this is the product of an eliminable register and a
2678 constant, apply the distribute law and move the constant out
2679 so that we have (plus (mult ..) ..). This is needed in order
2680 to keep load-address insns valid. This case is pathological.
2681 We ignore the possibility of overflow here. */
2682 if (REG_P (XEXP (x
, 0))
2683 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2684 && CONST_INT_P (XEXP (x
, 1)))
2685 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2687 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2690 /* Refs inside notes or in DEBUG_INSNs don't count for
2692 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2693 || GET_CODE (insn
) == INSN_LIST
2694 || DEBUG_INSN_P (insn
))))
2695 ep
->ref_outside_mem
= 1;
2698 plus_constant (Pmode
,
2699 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2700 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2707 /* See comments before PLUS about handling MINUS. */
2709 case DIV
: case UDIV
:
2710 case MOD
: case UMOD
:
2711 case AND
: case IOR
: case XOR
:
2712 case ROTATERT
: case ROTATE
:
2713 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2715 case GE
: case GT
: case GEU
: case GTU
:
2716 case LE
: case LT
: case LEU
: case LTU
:
2718 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2720 rtx new1
= XEXP (x
, 1)
2721 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2724 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2725 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2730 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2733 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2735 if (new_rtx
!= XEXP (x
, 0))
2737 /* If this is a REG_DEAD note, it is not valid anymore.
2738 Using the eliminated version could result in creating a
2739 REG_DEAD note for the stack or frame pointer. */
2740 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2742 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2746 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2754 /* Now do eliminations in the rest of the chain. If this was
2755 an EXPR_LIST, this might result in allocating more memory than is
2756 strictly needed, but it simplifies the code. */
2759 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2761 if (new_rtx
!= XEXP (x
, 1))
2763 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2771 /* We do not support elimination of a register that is modified.
2772 elimination_effects has already make sure that this does not
2778 /* We do not support elimination of a register that is modified.
2779 elimination_effects has already make sure that this does not
2780 happen. The only remaining case we need to consider here is
2781 that the increment value may be an eliminable register. */
2782 if (GET_CODE (XEXP (x
, 1)) == PLUS
2783 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2785 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2786 insn
, true, for_costs
);
2788 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2789 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2790 gen_rtx_PLUS (GET_MODE (x
),
2791 XEXP (x
, 0), new_rtx
));
2795 case STRICT_LOW_PART
:
2797 case SIGN_EXTEND
: case ZERO_EXTEND
:
2798 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2799 case FLOAT
: case FIX
:
2800 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2809 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2811 if (new_rtx
!= XEXP (x
, 0))
2812 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2816 /* Similar to above processing, but preserve SUBREG_BYTE.
2817 Convert (subreg (mem)) to (mem) if not paradoxical.
2818 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2819 pseudo didn't get a hard reg, we must replace this with the
2820 eliminated version of the memory location because push_reload
2821 may do the replacement in certain circumstances. */
2822 if (REG_P (SUBREG_REG (x
))
2823 && !paradoxical_subreg_p (x
)
2825 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2827 new_rtx
= SUBREG_REG (x
);
2830 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2832 if (new_rtx
!= SUBREG_REG (x
))
2834 poly_int64 x_size
= GET_MODE_SIZE (GET_MODE (x
));
2835 poly_int64 new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2838 && ((partial_subreg_p (GET_MODE (x
), GET_MODE (new_rtx
))
2839 /* On RISC machines, combine can create rtl of the form
2840 (set (subreg:m1 (reg:m2 R) 0) ...)
2841 where m1 < m2, and expects something interesting to
2842 happen to the entire word. Moreover, it will use the
2843 (reg:m2 R) later, expecting all bits to be preserved.
2844 So if the number of words is the same, preserve the
2845 subreg so that push_reload can see it. */
2846 && !(WORD_REGISTER_OPERATIONS
2847 && known_equal_after_align_down (x_size
- 1,
2850 || known_eq (x_size
, new_size
))
2852 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2853 else if (insn
&& GET_CODE (insn
) == DEBUG_INSN
)
2854 return gen_rtx_raw_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2856 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2862 /* Our only special processing is to pass the mode of the MEM to our
2863 recursive call and copy the flags. While we are here, handle this
2864 case more efficiently. */
2866 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2869 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2870 && !memory_address_p (GET_MODE (x
), new_rtx
))
2871 note_reg_elim_costly (XEXP (x
, 0), insn
);
2873 return replace_equiv_address_nv (x
, new_rtx
);
2876 /* Handle insn_list USE that a call to a pure function may generate. */
2877 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2879 if (new_rtx
!= XEXP (x
, 0))
2880 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2886 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2896 /* Process each of our operands recursively. If any have changed, make a
2898 fmt
= GET_RTX_FORMAT (code
);
2899 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2903 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2905 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2907 x
= shallow_copy_rtx (x
);
2910 XEXP (x
, i
) = new_rtx
;
2912 else if (*fmt
== 'E')
2915 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2917 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2919 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2921 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2925 x
= shallow_copy_rtx (x
);
2928 XVEC (x
, i
) = new_v
;
2931 XVECEXP (x
, i
, j
) = new_rtx
;
2940 eliminate_regs (rtx x
, machine_mode mem_mode
, rtx insn
)
2942 if (reg_eliminate
== NULL
)
2944 gcc_assert (targetm
.no_register_allocation
);
2947 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2950 /* Scan rtx X for modifications of elimination target registers. Update
2951 the table of eliminables to reflect the changed state. MEM_MODE is
2952 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2955 elimination_effects (rtx x
, machine_mode mem_mode
)
2957 enum rtx_code code
= GET_CODE (x
);
2958 struct elim_table
*ep
;
2980 /* First handle the case where we encounter a bare register that
2981 is eliminable. Replace it with a PLUS. */
2982 if (regno
< FIRST_PSEUDO_REGISTER
)
2984 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2986 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2989 ep
->ref_outside_mem
= 1;
2994 else if (reg_renumber
[regno
] < 0
2996 && reg_equiv_constant (regno
)
2997 && ! function_invariant_p (reg_equiv_constant (regno
)))
2998 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3007 /* If we modify the source of an elimination rule, disable it. */
3008 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3009 if (ep
->from_rtx
== XEXP (x
, 0))
3010 ep
->can_eliminate
= 0;
3012 /* If we modify the target of an elimination rule by adding a constant,
3013 update its offset. If we modify the target in any other way, we'll
3014 have to disable the rule as well. */
3015 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3016 if (ep
->to_rtx
== XEXP (x
, 0))
3018 poly_int64 size
= GET_MODE_SIZE (mem_mode
);
3020 /* If more bytes than MEM_MODE are pushed, account for them. */
3021 #ifdef PUSH_ROUNDING
3022 if (ep
->to_rtx
== stack_pointer_rtx
)
3023 size
= PUSH_ROUNDING (size
);
3025 if (code
== PRE_DEC
|| code
== POST_DEC
)
3027 else if (code
== PRE_INC
|| code
== POST_INC
)
3029 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3031 if (GET_CODE (XEXP (x
, 1)) == PLUS
3032 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3033 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3034 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3036 ep
->can_eliminate
= 0;
3040 /* These two aren't unary operators. */
3041 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3044 /* Fall through to generic unary operation case. */
3046 case STRICT_LOW_PART
:
3048 case SIGN_EXTEND
: case ZERO_EXTEND
:
3049 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3050 case FLOAT
: case FIX
:
3051 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3060 elimination_effects (XEXP (x
, 0), mem_mode
);
3064 if (REG_P (SUBREG_REG (x
))
3065 && !paradoxical_subreg_p (x
)
3067 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3070 elimination_effects (SUBREG_REG (x
), mem_mode
);
3074 /* If using a register that is the source of an eliminate we still
3075 think can be performed, note it cannot be performed since we don't
3076 know how this register is used. */
3077 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3078 if (ep
->from_rtx
== XEXP (x
, 0))
3079 ep
->can_eliminate
= 0;
3081 elimination_effects (XEXP (x
, 0), mem_mode
);
3085 /* If clobbering a register that is the replacement register for an
3086 elimination we still think can be performed, note that it cannot
3087 be performed. Otherwise, we need not be concerned about it. */
3088 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3089 if (ep
->to_rtx
== XEXP (x
, 0))
3090 ep
->can_eliminate
= 0;
3092 elimination_effects (XEXP (x
, 0), mem_mode
);
3096 /* CLOBBER_HIGH is only supported for LRA. */
3100 /* Check for setting a register that we know about. */
3101 if (REG_P (SET_DEST (x
)))
3103 /* See if this is setting the replacement register for an
3106 If DEST is the hard frame pointer, we do nothing because we
3107 assume that all assignments to the frame pointer are for
3108 non-local gotos and are being done at a time when they are valid
3109 and do not disturb anything else. Some machines want to
3110 eliminate a fake argument pointer (or even a fake frame pointer)
3111 with either the real frame or the stack pointer. Assignments to
3112 the hard frame pointer must not prevent this elimination. */
3114 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3116 if (ep
->to_rtx
== SET_DEST (x
)
3117 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3119 /* If it is being incremented, adjust the offset. Otherwise,
3120 this elimination can't be done. */
3121 rtx src
= SET_SRC (x
);
3123 if (GET_CODE (src
) == PLUS
3124 && XEXP (src
, 0) == SET_DEST (x
)
3125 && CONST_INT_P (XEXP (src
, 1)))
3126 ep
->offset
-= INTVAL (XEXP (src
, 1));
3128 ep
->can_eliminate
= 0;
3132 elimination_effects (SET_DEST (x
), VOIDmode
);
3133 elimination_effects (SET_SRC (x
), VOIDmode
);
3137 /* Our only special processing is to pass the mode of the MEM to our
3139 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3146 fmt
= GET_RTX_FORMAT (code
);
3147 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3150 elimination_effects (XEXP (x
, i
), mem_mode
);
3151 else if (*fmt
== 'E')
3152 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3153 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3157 /* Descend through rtx X and verify that no references to eliminable registers
3158 remain. If any do remain, mark the involved register as not
3162 check_eliminable_occurrences (rtx x
)
3171 code
= GET_CODE (x
);
3173 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3175 struct elim_table
*ep
;
3177 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3178 if (ep
->from_rtx
== x
)
3179 ep
->can_eliminate
= 0;
3183 fmt
= GET_RTX_FORMAT (code
);
3184 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3187 check_eliminable_occurrences (XEXP (x
, i
));
3188 else if (*fmt
== 'E')
3191 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3192 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3197 /* Scan INSN and eliminate all eliminable registers in it.
3199 If REPLACE is nonzero, do the replacement destructively. Also
3200 delete the insn as dead it if it is setting an eliminable register.
3202 If REPLACE is zero, do all our allocations in reload_obstack.
3204 If no eliminations were done and this insn doesn't require any elimination
3205 processing (these are not identical conditions: it might be updating sp,
3206 but not referencing fp; this needs to be seen during reload_as_needed so
3207 that the offset between fp and sp can be taken into consideration), zero
3208 is returned. Otherwise, 1 is returned. */
3211 eliminate_regs_in_insn (rtx_insn
*insn
, int replace
)
3213 int icode
= recog_memoized (insn
);
3214 rtx old_body
= PATTERN (insn
);
3215 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3216 rtx old_set
= single_set (insn
);
3220 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3221 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3222 struct elim_table
*ep
;
3223 rtx plus_src
, plus_cst_src
;
3225 if (! insn_is_asm
&& icode
< 0)
3227 gcc_assert (DEBUG_INSN_P (insn
)
3228 || GET_CODE (PATTERN (insn
)) == USE
3229 || GET_CODE (PATTERN (insn
)) == CLOBBER
3230 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3231 if (DEBUG_BIND_INSN_P (insn
))
3232 INSN_VAR_LOCATION_LOC (insn
)
3233 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3237 /* We allow one special case which happens to work on all machines we
3238 currently support: a single set with the source or a REG_EQUAL
3239 note being a PLUS of an eliminable register and a constant. */
3240 plus_src
= plus_cst_src
= 0;
3241 if (old_set
&& REG_P (SET_DEST (old_set
)))
3243 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3244 plus_src
= SET_SRC (old_set
);
3245 /* First see if the source is of the form (plus (...) CST). */
3247 && CONST_INT_P (XEXP (plus_src
, 1)))
3248 plus_cst_src
= plus_src
;
3249 else if (REG_P (SET_SRC (old_set
))
3252 /* Otherwise, see if we have a REG_EQUAL note of the form
3253 (plus (...) CST). */
3255 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3257 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3258 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3259 && GET_CODE (XEXP (links
, 0)) == PLUS
3260 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3262 plus_cst_src
= XEXP (links
, 0);
3268 /* Check that the first operand of the PLUS is a hard reg or
3269 the lowpart subreg of one. */
3272 rtx reg
= XEXP (plus_cst_src
, 0);
3273 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3274 reg
= SUBREG_REG (reg
);
3276 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3282 rtx reg
= XEXP (plus_cst_src
, 0);
3283 poly_int64 offset
= INTVAL (XEXP (plus_cst_src
, 1));
3285 if (GET_CODE (reg
) == SUBREG
)
3286 reg
= SUBREG_REG (reg
);
3288 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3289 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3291 rtx to_rtx
= ep
->to_rtx
;
3292 offset
+= ep
->offset
;
3293 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3295 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3296 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3298 /* If we have a nonzero offset, and the source is already
3299 a simple REG, the following transformation would
3300 increase the cost of the insn by replacing a simple REG
3301 with (plus (reg sp) CST). So try only when we already
3302 had a PLUS before. */
3303 if (known_eq (offset
, 0) || plus_src
)
3305 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3308 new_body
= old_body
;
3311 new_body
= copy_insn (old_body
);
3312 if (REG_NOTES (insn
))
3313 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3315 PATTERN (insn
) = new_body
;
3316 old_set
= single_set (insn
);
3318 /* First see if this insn remains valid when we make the
3319 change. If not, try to replace the whole pattern with
3320 a simple set (this may help if the original insn was a
3321 PARALLEL that was only recognized as single_set due to
3322 REG_UNUSED notes). If this isn't valid either, keep
3323 the INSN_CODE the same and let reload fix it up. */
3324 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3326 rtx new_pat
= gen_rtx_SET (SET_DEST (old_set
), new_src
);
3328 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3329 SET_SRC (old_set
) = new_src
;
3336 /* This can't have an effect on elimination offsets, so skip right
3342 /* Determine the effects of this insn on elimination offsets. */
3343 elimination_effects (old_body
, VOIDmode
);
3345 /* Eliminate all eliminable registers occurring in operands that
3346 can be handled by reload. */
3347 extract_insn (insn
);
3348 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3350 orig_operand
[i
] = recog_data
.operand
[i
];
3351 substed_operand
[i
] = recog_data
.operand
[i
];
3353 /* For an asm statement, every operand is eliminable. */
3354 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3356 bool is_set_src
, in_plus
;
3358 /* Check for setting a register that we know about. */
3359 if (recog_data
.operand_type
[i
] != OP_IN
3360 && REG_P (orig_operand
[i
]))
3362 /* If we are assigning to a register that can be eliminated, it
3363 must be as part of a PARALLEL, since the code above handles
3364 single SETs. We must indicate that we can no longer
3365 eliminate this reg. */
3366 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3368 if (ep
->from_rtx
== orig_operand
[i
])
3369 ep
->can_eliminate
= 0;
3372 /* Companion to the above plus substitution, we can allow
3373 invariants as the source of a plain move. */
3376 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3380 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3381 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3385 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3386 replace
? insn
: NULL_RTX
,
3387 is_set_src
|| in_plus
, false);
3388 if (substed_operand
[i
] != orig_operand
[i
])
3390 /* Terminate the search in check_eliminable_occurrences at
3392 *recog_data
.operand_loc
[i
] = 0;
3394 /* If an output operand changed from a REG to a MEM and INSN is an
3395 insn, write a CLOBBER insn. */
3396 if (recog_data
.operand_type
[i
] != OP_IN
3397 && REG_P (orig_operand
[i
])
3398 && MEM_P (substed_operand
[i
])
3400 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3404 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3405 *recog_data
.dup_loc
[i
]
3406 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3408 /* If any eliminable remain, they aren't eliminable anymore. */
3409 check_eliminable_occurrences (old_body
);
3411 /* Substitute the operands; the new values are in the substed_operand
3413 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3414 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3415 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3416 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3418 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3419 re-recognize the insn. We do this in case we had a simple addition
3420 but now can do this as a load-address. This saves an insn in this
3422 If re-recognition fails, the old insn code number will still be used,
3423 and some register operands may have changed into PLUS expressions.
3424 These will be handled by find_reloads by loading them into a register
3429 /* If we aren't replacing things permanently and we changed something,
3430 make another copy to ensure that all the RTL is new. Otherwise
3431 things can go wrong if find_reload swaps commutative operands
3432 and one is inside RTL that has been copied while the other is not. */
3433 new_body
= old_body
;
3436 new_body
= copy_insn (old_body
);
3437 if (REG_NOTES (insn
))
3438 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3440 PATTERN (insn
) = new_body
;
3442 /* If we had a move insn but now we don't, rerecognize it. This will
3443 cause spurious re-recognition if the old move had a PARALLEL since
3444 the new one still will, but we can't call single_set without
3445 having put NEW_BODY into the insn and the re-recognition won't
3446 hurt in this rare case. */
3447 /* ??? Why this huge if statement - why don't we just rerecognize the
3451 && ((REG_P (SET_SRC (old_set
))
3452 && (GET_CODE (new_body
) != SET
3453 || !REG_P (SET_SRC (new_body
))))
3454 /* If this was a load from or store to memory, compare
3455 the MEM in recog_data.operand to the one in the insn.
3456 If they are not equal, then rerecognize the insn. */
3458 && ((MEM_P (SET_SRC (old_set
))
3459 && SET_SRC (old_set
) != recog_data
.operand
[1])
3460 || (MEM_P (SET_DEST (old_set
))
3461 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3462 /* If this was an add insn before, rerecognize. */
3463 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3465 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3467 INSN_CODE (insn
) = new_icode
;
3471 /* Restore the old body. If there were any changes to it, we made a copy
3472 of it while the changes were still in place, so we'll correctly return
3473 a modified insn below. */
3476 /* Restore the old body. */
3477 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3478 /* Restoring a top-level match_parallel would clobber the new_body
3479 we installed in the insn. */
3480 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3481 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3482 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3483 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3486 /* Update all elimination pairs to reflect the status after the current
3487 insn. The changes we make were determined by the earlier call to
3488 elimination_effects.
3490 We also detect cases where register elimination cannot be done,
3491 namely, if a register would be both changed and referenced outside a MEM
3492 in the resulting insn since such an insn is often undefined and, even if
3493 not, we cannot know what meaning will be given to it. Note that it is
3494 valid to have a register used in an address in an insn that changes it
3495 (presumably with a pre- or post-increment or decrement).
3497 If anything changes, return nonzero. */
3499 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3501 if (maybe_ne (ep
->previous_offset
, ep
->offset
) && ep
->ref_outside_mem
)
3502 ep
->can_eliminate
= 0;
3504 ep
->ref_outside_mem
= 0;
3506 if (maybe_ne (ep
->previous_offset
, ep
->offset
))
3511 /* If we changed something, perform elimination in REG_NOTES. This is
3512 needed even when REPLACE is zero because a REG_DEAD note might refer
3513 to a register that we eliminate and could cause a different number
3514 of spill registers to be needed in the final reload pass than in
3516 if (val
&& REG_NOTES (insn
) != 0)
3518 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3524 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3525 register allocator. INSN is the instruction we need to examine, we perform
3526 eliminations in its operands and record cases where eliminating a reg with
3527 an invariant equivalence would add extra cost. */
3529 #pragma GCC diagnostic push
3530 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3532 elimination_costs_in_insn (rtx_insn
*insn
)
3534 int icode
= recog_memoized (insn
);
3535 rtx old_body
= PATTERN (insn
);
3536 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3537 rtx old_set
= single_set (insn
);
3539 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3540 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3541 struct elim_table
*ep
;
3542 rtx plus_src
, plus_cst_src
;
3545 if (! insn_is_asm
&& icode
< 0)
3547 gcc_assert (DEBUG_INSN_P (insn
)
3548 || GET_CODE (PATTERN (insn
)) == USE
3549 || GET_CODE (PATTERN (insn
)) == CLOBBER
3550 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3554 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3555 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3557 /* Check for setting an eliminable register. */
3558 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3559 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3563 /* We allow one special case which happens to work on all machines we
3564 currently support: a single set with the source or a REG_EQUAL
3565 note being a PLUS of an eliminable register and a constant. */
3566 plus_src
= plus_cst_src
= 0;
3568 if (old_set
&& REG_P (SET_DEST (old_set
)))
3571 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3572 plus_src
= SET_SRC (old_set
);
3573 /* First see if the source is of the form (plus (...) CST). */
3575 && CONST_INT_P (XEXP (plus_src
, 1)))
3576 plus_cst_src
= plus_src
;
3577 else if (REG_P (SET_SRC (old_set
))
3580 /* Otherwise, see if we have a REG_EQUAL note of the form
3581 (plus (...) CST). */
3583 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3585 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3586 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3587 && GET_CODE (XEXP (links
, 0)) == PLUS
3588 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3590 plus_cst_src
= XEXP (links
, 0);
3597 /* Determine the effects of this insn on elimination offsets. */
3598 elimination_effects (old_body
, VOIDmode
);
3600 /* Eliminate all eliminable registers occurring in operands that
3601 can be handled by reload. */
3602 extract_insn (insn
);
3603 int n_dups
= recog_data
.n_dups
;
3604 for (i
= 0; i
< n_dups
; i
++)
3605 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3607 int n_operands
= recog_data
.n_operands
;
3608 for (i
= 0; i
< n_operands
; i
++)
3610 orig_operand
[i
] = recog_data
.operand
[i
];
3612 /* For an asm statement, every operand is eliminable. */
3613 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3615 bool is_set_src
, in_plus
;
3617 /* Check for setting a register that we know about. */
3618 if (recog_data
.operand_type
[i
] != OP_IN
3619 && REG_P (orig_operand
[i
]))
3621 /* If we are assigning to a register that can be eliminated, it
3622 must be as part of a PARALLEL, since the code above handles
3623 single SETs. We must indicate that we can no longer
3624 eliminate this reg. */
3625 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3627 if (ep
->from_rtx
== orig_operand
[i
])
3628 ep
->can_eliminate
= 0;
3631 /* Companion to the above plus substitution, we can allow
3632 invariants as the source of a plain move. */
3634 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3636 if (is_set_src
&& !sets_reg_p
)
3637 note_reg_elim_costly (SET_SRC (old_set
), insn
);
3639 if (plus_src
&& sets_reg_p
3640 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3641 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3644 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3646 is_set_src
|| in_plus
, true);
3647 /* Terminate the search in check_eliminable_occurrences at
3649 *recog_data
.operand_loc
[i
] = 0;
3653 for (i
= 0; i
< n_dups
; i
++)
3654 *recog_data
.dup_loc
[i
]
3655 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3657 /* If any eliminable remain, they aren't eliminable anymore. */
3658 check_eliminable_occurrences (old_body
);
3660 /* Restore the old body. */
3661 for (i
= 0; i
< n_operands
; i
++)
3662 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3663 for (i
= 0; i
< n_dups
; i
++)
3664 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3666 /* Update all elimination pairs to reflect the status after the current
3667 insn. The changes we make were determined by the earlier call to
3668 elimination_effects. */
3670 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3672 if (maybe_ne (ep
->previous_offset
, ep
->offset
) && ep
->ref_outside_mem
)
3673 ep
->can_eliminate
= 0;
3675 ep
->ref_outside_mem
= 0;
3680 #pragma GCC diagnostic pop
3682 /* Loop through all elimination pairs.
3683 Recalculate the number not at initial offset.
3685 Compute the maximum offset (minimum offset if the stack does not
3686 grow downward) for each elimination pair. */
3689 update_eliminable_offsets (void)
3691 struct elim_table
*ep
;
3693 num_not_at_initial_offset
= 0;
3694 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3696 ep
->previous_offset
= ep
->offset
;
3697 if (ep
->can_eliminate
&& maybe_ne (ep
->offset
, ep
->initial_offset
))
3698 num_not_at_initial_offset
++;
3702 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3703 replacement we currently believe is valid, mark it as not eliminable if X
3704 modifies DEST in any way other than by adding a constant integer to it.
3706 If DEST is the frame pointer, we do nothing because we assume that
3707 all assignments to the hard frame pointer are nonlocal gotos and are being
3708 done at a time when they are valid and do not disturb anything else.
3709 Some machines want to eliminate a fake argument pointer with either the
3710 frame or stack pointer. Assignments to the hard frame pointer must not
3711 prevent this elimination.
3713 Called via note_stores from reload before starting its passes to scan
3714 the insns of the function. */
3717 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3721 /* A SUBREG of a hard register here is just changing its mode. We should
3722 not see a SUBREG of an eliminable hard register, but check just in
3724 if (GET_CODE (dest
) == SUBREG
)
3725 dest
= SUBREG_REG (dest
);
3727 if (dest
== hard_frame_pointer_rtx
)
3730 /* CLOBBER_HIGH is only supported for LRA. */
3731 gcc_assert (GET_CODE (x
) != CLOBBER_HIGH
);
3733 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3734 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3735 && (GET_CODE (x
) != SET
3736 || GET_CODE (SET_SRC (x
)) != PLUS
3737 || XEXP (SET_SRC (x
), 0) != dest
3738 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3740 reg_eliminate
[i
].can_eliminate_previous
3741 = reg_eliminate
[i
].can_eliminate
= 0;
3746 /* Verify that the initial elimination offsets did not change since the
3747 last call to set_initial_elim_offsets. This is used to catch cases
3748 where something illegal happened during reload_as_needed that could
3749 cause incorrect code to be generated if we did not check for it. */
3752 verify_initial_elim_offsets (void)
3755 struct elim_table
*ep
;
3757 if (!num_eliminable
)
3760 targetm
.compute_frame_layout ();
3761 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3763 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3764 if (maybe_ne (t
, ep
->initial_offset
))
3771 /* Reset all offsets on eliminable registers to their initial values. */
3774 set_initial_elim_offsets (void)
3776 struct elim_table
*ep
= reg_eliminate
;
3778 targetm
.compute_frame_layout ();
3779 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3781 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3782 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3785 num_not_at_initial_offset
= 0;
3788 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3791 set_initial_eh_label_offset (rtx label
)
3793 set_label_offsets (label
, NULL
, 1);
3796 /* Initialize the known label offsets.
3797 Set a known offset for each forced label to be at the initial offset
3798 of each elimination. We do this because we assume that all
3799 computed jumps occur from a location where each elimination is
3800 at its initial offset.
3801 For all other labels, show that we don't know the offsets. */
3804 set_initial_label_offsets (void)
3806 memset (offsets_known_at
, 0, num_labels
);
3810 FOR_EACH_VEC_SAFE_ELT (forced_labels
, i
, insn
)
3811 set_label_offsets (insn
, NULL
, 1);
3813 for (rtx_insn_list
*x
= nonlocal_goto_handler_labels
; x
; x
= x
->next ())
3815 set_label_offsets (x
->insn (), NULL
, 1);
3817 for_each_eh_label (set_initial_eh_label_offset
);
3820 /* Set all elimination offsets to the known values for the code label given
3824 set_offsets_for_label (rtx_insn
*insn
)
3827 int label_nr
= CODE_LABEL_NUMBER (insn
);
3828 struct elim_table
*ep
;
3830 num_not_at_initial_offset
= 0;
3831 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3833 ep
->offset
= ep
->previous_offset
3834 = offsets_at
[label_nr
- first_label_num
][i
];
3835 if (ep
->can_eliminate
&& maybe_ne (ep
->offset
, ep
->initial_offset
))
3836 num_not_at_initial_offset
++;
3840 /* See if anything that happened changes which eliminations are valid.
3841 For example, on the SPARC, whether or not the frame pointer can
3842 be eliminated can depend on what registers have been used. We need
3843 not check some conditions again (such as flag_omit_frame_pointer)
3844 since they can't have changed. */
3847 update_eliminables (HARD_REG_SET
*pset
)
3849 int previous_frame_pointer_needed
= frame_pointer_needed
;
3850 struct elim_table
*ep
;
3852 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3853 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3854 && targetm
.frame_pointer_required ())
3855 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3857 ep
->can_eliminate
= 0;
3859 /* Look for the case where we have discovered that we can't replace
3860 register A with register B and that means that we will now be
3861 trying to replace register A with register C. This means we can
3862 no longer replace register C with register B and we need to disable
3863 such an elimination, if it exists. This occurs often with A == ap,
3864 B == sp, and C == fp. */
3866 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3868 struct elim_table
*op
;
3871 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3873 /* Find the current elimination for ep->from, if there is a
3875 for (op
= reg_eliminate
;
3876 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3877 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3883 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3885 for (op
= reg_eliminate
;
3886 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3887 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3888 op
->can_eliminate
= 0;
3892 /* See if any registers that we thought we could eliminate the previous
3893 time are no longer eliminable. If so, something has changed and we
3894 must spill the register. Also, recompute the number of eliminable
3895 registers and see if the frame pointer is needed; it is if there is
3896 no elimination of the frame pointer that we can perform. */
3898 frame_pointer_needed
= 1;
3899 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3901 if (ep
->can_eliminate
3902 && ep
->from
== FRAME_POINTER_REGNUM
3903 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
3904 && (! SUPPORTS_STACK_ALIGNMENT
3905 || ! crtl
->stack_realign_needed
))
3906 frame_pointer_needed
= 0;
3908 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3910 ep
->can_eliminate_previous
= 0;
3911 SET_HARD_REG_BIT (*pset
, ep
->from
);
3916 /* If we didn't need a frame pointer last time, but we do now, spill
3917 the hard frame pointer. */
3918 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3919 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3922 /* Call update_eliminables an spill any registers we can't eliminate anymore.
3923 Return true iff a register was spilled. */
3926 update_eliminables_and_spill (void)
3929 bool did_spill
= false;
3930 HARD_REG_SET to_spill
;
3931 CLEAR_HARD_REG_SET (to_spill
);
3932 update_eliminables (&to_spill
);
3933 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
3935 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3936 if (TEST_HARD_REG_BIT (to_spill
, i
))
3938 spill_hard_reg (i
, 1);
3941 /* Regardless of the state of spills, if we previously had
3942 a register that we thought we could eliminate, but now
3943 cannot eliminate, we must run another pass.
3945 Consider pseudos which have an entry in reg_equiv_* which
3946 reference an eliminable register. We must make another pass
3947 to update reg_equiv_* so that we do not substitute in the
3948 old value from when we thought the elimination could be
3954 /* Return true if X is used as the target register of an elimination. */
3957 elimination_target_reg_p (rtx x
)
3959 struct elim_table
*ep
;
3961 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3962 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
3968 /* Initialize the table of registers to eliminate.
3969 Pre-condition: global flag frame_pointer_needed has been set before
3970 calling this function. */
3973 init_elim_table (void)
3975 struct elim_table
*ep
;
3976 const struct elim_table_1
*ep1
;
3979 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
3983 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3984 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3986 ep
->from
= ep1
->from
;
3988 ep
->can_eliminate
= ep
->can_eliminate_previous
3989 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
3990 && ! (ep
->to
== STACK_POINTER_REGNUM
3991 && frame_pointer_needed
3992 && (! SUPPORTS_STACK_ALIGNMENT
3993 || ! stack_realign_fp
)));
3996 /* Count the number of eliminable registers and build the FROM and TO
3997 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3998 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3999 We depend on this. */
4000 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4002 num_eliminable
+= ep
->can_eliminate
;
4003 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4004 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4008 /* Find all the pseudo registers that didn't get hard regs
4009 but do have known equivalent constants or memory slots.
4010 These include parameters (known equivalent to parameter slots)
4011 and cse'd or loop-moved constant memory addresses.
4013 Record constant equivalents in reg_equiv_constant
4014 so they will be substituted by find_reloads.
4015 Record memory equivalents in reg_mem_equiv so they can
4016 be substituted eventually by altering the REG-rtx's. */
4019 init_eliminable_invariants (rtx_insn
*first
, bool do_subregs
)
4026 reg_max_ref_mode
= XCNEWVEC (machine_mode
, max_regno
);
4028 reg_max_ref_mode
= NULL
;
4030 num_eliminable_invariants
= 0;
4032 first_label_num
= get_first_label_num ();
4033 num_labels
= max_label_num () - first_label_num
;
4035 /* Allocate the tables used to store offset information at labels. */
4036 offsets_known_at
= XNEWVEC (char, num_labels
);
4037 offsets_at
= (poly_int64_pod (*)[NUM_ELIMINABLE_REGS
])
4038 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (poly_int64
));
4040 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4041 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4042 find largest such for each pseudo. FIRST is the head of the insn
4045 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4047 rtx set
= single_set (insn
);
4049 /* We may introduce USEs that we want to remove at the end, so
4050 we'll mark them with QImode. Make sure there are no
4051 previously-marked insns left by say regmove. */
4052 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4053 && GET_MODE (insn
) != VOIDmode
)
4054 PUT_MODE (insn
, VOIDmode
);
4056 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4057 scan_paradoxical_subregs (PATTERN (insn
));
4059 if (set
!= 0 && REG_P (SET_DEST (set
)))
4061 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4067 i
= REGNO (SET_DEST (set
));
4070 if (i
<= LAST_VIRTUAL_REGISTER
)
4073 /* If flag_pic and we have constant, verify it's legitimate. */
4075 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4077 /* It can happen that a REG_EQUIV note contains a MEM
4078 that is not a legitimate memory operand. As later
4079 stages of reload assume that all addresses found
4080 in the reg_equiv_* arrays were originally legitimate,
4081 we ignore such REG_EQUIV notes. */
4082 if (memory_operand (x
, VOIDmode
))
4084 /* Always unshare the equivalence, so we can
4085 substitute into this insn without touching the
4087 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4089 else if (function_invariant_p (x
))
4093 mode
= GET_MODE (SET_DEST (set
));
4094 if (GET_CODE (x
) == PLUS
)
4096 /* This is PLUS of frame pointer and a constant,
4097 and might be shared. Unshare it. */
4098 reg_equiv_invariant (i
) = copy_rtx (x
);
4099 num_eliminable_invariants
++;
4101 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4103 reg_equiv_invariant (i
) = x
;
4104 num_eliminable_invariants
++;
4106 else if (targetm
.legitimate_constant_p (mode
, x
))
4107 reg_equiv_constant (i
) = x
;
4110 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4111 if (! reg_equiv_memory_loc (i
))
4112 reg_equiv_init (i
) = NULL
;
4117 reg_equiv_init (i
) = NULL
;
4122 reg_equiv_init (i
) = NULL
;
4127 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4128 if (reg_equiv_init (i
))
4130 fprintf (dump_file
, "init_insns for %u: ", i
);
4131 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4132 fprintf (dump_file
, "\n");
4136 /* Indicate that we no longer have known memory locations or constants.
4137 Free all data involved in tracking these. */
4140 free_reg_equiv (void)
4144 free (offsets_known_at
);
4147 offsets_known_at
= 0;
4149 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4150 if (reg_equiv_alt_mem_list (i
))
4151 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4152 vec_free (reg_equivs
);
4155 /* Kick all pseudos out of hard register REGNO.
4157 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4158 because we found we can't eliminate some register. In the case, no pseudos
4159 are allowed to be in the register, even if they are only in a block that
4160 doesn't require spill registers, unlike the case when we are spilling this
4161 hard reg to produce another spill register.
4163 Return nonzero if any pseudos needed to be kicked out. */
4166 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4172 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4173 df_set_regs_ever_live (regno
, true);
4176 /* Spill every pseudo reg that was allocated to this reg
4177 or to something that overlaps this reg. */
4179 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4180 if (reg_renumber
[i
] >= 0
4181 && (unsigned int) reg_renumber
[i
] <= regno
4182 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4183 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4186 /* After spill_hard_reg was called and/or find_reload_regs was run for all
4187 insns that need reloads, this function is used to actually spill pseudo
4188 registers and try to reallocate them. It also sets up the spill_regs
4189 array for use by choose_reload_regs.
4191 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4192 that we displace from hard registers. */
4195 finish_spills (int global
)
4197 class insn_chain
*chain
;
4198 int something_changed
= 0;
4200 reg_set_iterator rsi
;
4202 /* Build the spill_regs array for the function. */
4203 /* If there are some registers still to eliminate and one of the spill regs
4204 wasn't ever used before, additional stack space may have to be
4205 allocated to store this register. Thus, we may have changed the offset
4206 between the stack and frame pointers, so mark that something has changed.
4208 One might think that we need only set VAL to 1 if this is a call-used
4209 register. However, the set of registers that must be saved by the
4210 prologue is not identical to the call-used set. For example, the
4211 register used by the call insn for the return PC is a call-used register,
4212 but must be saved by the prologue. */
4215 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4216 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4218 spill_reg_order
[i
] = n_spills
;
4219 spill_regs
[n_spills
++] = i
;
4220 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4221 something_changed
= 1;
4222 df_set_regs_ever_live (i
, true);
4225 spill_reg_order
[i
] = -1;
4227 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4228 if (reg_renumber
[i
] >= 0)
4230 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4231 /* Mark it as no longer having a hard register home. */
4232 reg_renumber
[i
] = -1;
4233 if (ira_conflicts_p
)
4234 /* Inform IRA about the change. */
4235 ira_mark_allocation_change (i
);
4236 /* We will need to scan everything again. */
4237 something_changed
= 1;
4240 /* Retry global register allocation if possible. */
4241 if (global
&& ira_conflicts_p
)
4245 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4246 /* For every insn that needs reloads, set the registers used as spill
4247 regs in pseudo_forbidden_regs for every pseudo live across the
4249 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4251 EXECUTE_IF_SET_IN_REG_SET
4252 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4254 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4255 chain
->used_spill_regs
);
4257 EXECUTE_IF_SET_IN_REG_SET
4258 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4260 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4261 chain
->used_spill_regs
);
4265 /* Retry allocating the pseudos spilled in IRA and the
4266 reload. For each reg, merge the various reg sets that
4267 indicate which hard regs can't be used, and call
4268 ira_reassign_pseudos. */
4269 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4270 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4272 if (reg_renumber
[i
] < 0)
4273 temp_pseudo_reg_arr
[n
++] = i
;
4275 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4277 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4278 bad_spill_regs_global
,
4279 pseudo_forbidden_regs
, pseudo_previous_regs
,
4281 something_changed
= 1;
4283 /* Fix up the register information in the insn chain.
4284 This involves deleting those of the spilled pseudos which did not get
4285 a new hard register home from the live_{before,after} sets. */
4286 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4288 HARD_REG_SET used_by_pseudos
;
4289 HARD_REG_SET used_by_pseudos2
;
4291 if (! ira_conflicts_p
)
4293 /* Don't do it for IRA because IRA and the reload still can
4294 assign hard registers to the spilled pseudos on next
4295 reload iterations. */
4296 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4297 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4299 /* Mark any unallocated hard regs as available for spills. That
4300 makes inheritance work somewhat better. */
4301 if (chain
->need_reload
)
4303 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4304 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4305 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4307 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4308 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4309 /* Value of chain->used_spill_regs from previous iteration
4310 may be not included in the value calculated here because
4311 of possible removing caller-saves insns (see function
4312 delete_caller_save_insns. */
4313 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4314 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4318 CLEAR_REG_SET (&changed_allocation_pseudos
);
4319 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4320 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4322 int regno
= reg_renumber
[i
];
4323 if (reg_old_renumber
[i
] == regno
)
4326 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4328 alter_reg (i
, reg_old_renumber
[i
], false);
4329 reg_old_renumber
[i
] = regno
;
4333 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4335 fprintf (dump_file
, " Register %d now in %d.\n\n",
4336 i
, reg_renumber
[i
]);
4340 return something_changed
;
4343 /* Find all paradoxical subregs within X and update reg_max_ref_mode. */
4346 scan_paradoxical_subregs (rtx x
)
4350 enum rtx_code code
= GET_CODE (x
);
4367 if (REG_P (SUBREG_REG (x
)))
4369 unsigned int regno
= REGNO (SUBREG_REG (x
));
4370 if (partial_subreg_p (reg_max_ref_mode
[regno
], GET_MODE (x
)))
4372 reg_max_ref_mode
[regno
] = GET_MODE (x
);
4373 mark_home_live_1 (regno
, GET_MODE (x
));
4382 fmt
= GET_RTX_FORMAT (code
);
4383 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4386 scan_paradoxical_subregs (XEXP (x
, i
));
4387 else if (fmt
[i
] == 'E')
4390 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4391 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4396 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4397 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4398 and apply the corresponding narrowing subreg to *OTHER_PTR.
4399 Return true if the operands were changed, false otherwise. */
4402 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4404 rtx op
, inner
, other
, tem
;
4407 if (!paradoxical_subreg_p (op
))
4409 inner
= SUBREG_REG (op
);
4412 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4416 /* If the lowpart operation turned a hard register into a subreg,
4417 rather than simplifying it to another hard register, then the
4418 mode change cannot be properly represented. For example, OTHER
4419 might be valid in its current mode, but not in the new one. */
4420 if (GET_CODE (tem
) == SUBREG
4422 && HARD_REGISTER_P (other
))
4430 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4431 examine all of the reload insns between PREV and NEXT exclusive, and
4432 annotate all that may trap. */
4435 fixup_eh_region_note (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4437 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4440 if (!insn_could_throw_p (insn
))
4441 remove_note (insn
, note
);
4442 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4445 /* Reload pseudo-registers into hard regs around each insn as needed.
4446 Additional register load insns are output before the insn that needs it
4447 and perhaps store insns after insns that modify the reloaded pseudo reg.
4449 reg_last_reload_reg and reg_reloaded_contents keep track of
4450 which registers are already available in reload registers.
4451 We update these for the reloads that we perform,
4452 as the insns are scanned. */
4455 reload_as_needed (int live_known
)
4457 class insn_chain
*chain
;
4463 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4464 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4465 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4466 INIT_REG_SET (®_has_output_reload
);
4467 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4468 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4470 set_initial_elim_offsets ();
4472 /* Generate a marker insn that we will move around. */
4473 marker
= emit_note (NOTE_INSN_DELETED
);
4474 unlink_insn_chain (marker
, marker
);
4476 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4479 rtx_insn
*insn
= chain
->insn
;
4480 rtx_insn
*old_next
= NEXT_INSN (insn
);
4482 rtx_insn
*old_prev
= PREV_INSN (insn
);
4485 if (will_delete_init_insn_p (insn
))
4488 /* If we pass a label, copy the offsets from the label information
4489 into the current offsets of each elimination. */
4491 set_offsets_for_label (insn
);
4493 else if (INSN_P (insn
))
4495 regset_head regs_to_forget
;
4496 INIT_REG_SET (®s_to_forget
);
4497 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4499 /* If this is a USE and CLOBBER of a MEM, ensure that any
4500 references to eliminable registers have been removed. */
4502 if ((GET_CODE (PATTERN (insn
)) == USE
4503 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4504 && MEM_P (XEXP (PATTERN (insn
), 0)))
4505 XEXP (XEXP (PATTERN (insn
), 0), 0)
4506 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4507 GET_MODE (XEXP (PATTERN (insn
), 0)),
4510 /* If we need to do register elimination processing, do so.
4511 This might delete the insn, in which case we are done. */
4512 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4514 eliminate_regs_in_insn (insn
, 1);
4517 update_eliminable_offsets ();
4518 CLEAR_REG_SET (®s_to_forget
);
4523 /* If need_elim is nonzero but need_reload is zero, one might think
4524 that we could simply set n_reloads to 0. However, find_reloads
4525 could have done some manipulation of the insn (such as swapping
4526 commutative operands), and these manipulations are lost during
4527 the first pass for every insn that needs register elimination.
4528 So the actions of find_reloads must be redone here. */
4530 if (! chain
->need_elim
&& ! chain
->need_reload
4531 && ! chain
->need_operand_change
)
4533 /* First find the pseudo regs that must be reloaded for this insn.
4534 This info is returned in the tables reload_... (see reload.h).
4535 Also modify the body of INSN by substituting RELOAD
4536 rtx's for those pseudo regs. */
4539 CLEAR_REG_SET (®_has_output_reload
);
4540 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4542 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4548 rtx_insn
*next
= NEXT_INSN (insn
);
4550 /* ??? PREV can get deleted by reload inheritance.
4551 Work around this by emitting a marker note. */
4552 prev
= PREV_INSN (insn
);
4553 reorder_insns_nobb (marker
, marker
, prev
);
4555 /* Now compute which reload regs to reload them into. Perhaps
4556 reusing reload regs from previous insns, or else output
4557 load insns to reload them. Maybe output store insns too.
4558 Record the choices of reload reg in reload_reg_rtx. */
4559 choose_reload_regs (chain
);
4561 /* Generate the insns to reload operands into or out of
4562 their reload regs. */
4563 emit_reload_insns (chain
);
4565 /* Substitute the chosen reload regs from reload_reg_rtx
4566 into the insn's body (or perhaps into the bodies of other
4567 load and store insn that we just made for reloading
4568 and that we moved the structure into). */
4569 subst_reloads (insn
);
4571 prev
= PREV_INSN (marker
);
4572 unlink_insn_chain (marker
, marker
);
4574 /* Adjust the exception region notes for loads and stores. */
4575 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4576 fixup_eh_region_note (insn
, prev
, next
);
4578 /* Adjust the location of REG_ARGS_SIZE. */
4579 rtx p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4582 remove_note (insn
, p
);
4583 fixup_args_size_notes (prev
, PREV_INSN (next
),
4587 /* If this was an ASM, make sure that all the reload insns
4588 we have generated are valid. If not, give an error
4590 if (asm_noperands (PATTERN (insn
)) >= 0)
4591 for (rtx_insn
*p
= NEXT_INSN (prev
);
4594 if (p
!= insn
&& INSN_P (p
)
4595 && GET_CODE (PATTERN (p
)) != USE
4596 && (recog_memoized (p
) < 0
4597 || (extract_insn (p
),
4598 !(constrain_operands (1,
4599 get_enabled_alternatives (p
))))))
4601 error_for_asm (insn
,
4602 "%<asm%> operand requires "
4603 "impossible reload");
4608 if (num_eliminable
&& chain
->need_elim
)
4609 update_eliminable_offsets ();
4611 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4612 is no longer validly lying around to save a future reload.
4613 Note that this does not detect pseudos that were reloaded
4614 for this insn in order to be stored in
4615 (obeying register constraints). That is correct; such reload
4616 registers ARE still valid. */
4617 forget_marked_reloads (®s_to_forget
);
4618 CLEAR_REG_SET (®s_to_forget
);
4620 /* There may have been CLOBBER insns placed after INSN. So scan
4621 between INSN and NEXT and use them to forget old reloads. */
4622 for (rtx_insn
*x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4623 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4624 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4627 /* Likewise for regs altered by auto-increment in this insn.
4628 REG_INC notes have been changed by reloading:
4629 find_reloads_address_1 records substitutions for them,
4630 which have been performed by subst_reloads above. */
4631 for (i
= n_reloads
- 1; i
>= 0; i
--)
4633 rtx in_reg
= rld
[i
].in_reg
;
4636 enum rtx_code code
= GET_CODE (in_reg
);
4637 /* PRE_INC / PRE_DEC will have the reload register ending up
4638 with the same value as the stack slot, but that doesn't
4639 hold true for POST_INC / POST_DEC. Either we have to
4640 convert the memory access to a true POST_INC / POST_DEC,
4641 or we can't use the reload register for inheritance. */
4642 if ((code
== POST_INC
|| code
== POST_DEC
)
4643 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4644 REGNO (rld
[i
].reg_rtx
))
4645 /* Make sure it is the inc/dec pseudo, and not
4646 some other (e.g. output operand) pseudo. */
4647 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4648 == REGNO (XEXP (in_reg
, 0))))
4651 rtx reload_reg
= rld
[i
].reg_rtx
;
4652 machine_mode mode
= GET_MODE (reload_reg
);
4656 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4658 /* We really want to ignore REG_INC notes here, so
4659 use PATTERN (p) as argument to reg_set_p . */
4660 if (reg_set_p (reload_reg
, PATTERN (p
)))
4662 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4668 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4670 validate_replace_rtx_group (reload_reg
,
4672 n
= verify_changes (0);
4674 /* We must also verify that the constraints
4675 are met after the replacement. Make sure
4676 extract_insn is only called for an insn
4677 where the replacements were found to be
4682 n
= constrain_operands (1,
4683 get_enabled_alternatives (p
));
4686 /* If the constraints were not met, then
4687 undo the replacement, else confirm it. */
4691 confirm_change_group ();
4697 add_reg_note (p
, REG_INC
, reload_reg
);
4698 /* Mark this as having an output reload so that the
4699 REG_INC processing code below won't invalidate
4700 the reload for inheritance. */
4701 SET_HARD_REG_BIT (reg_is_output_reload
,
4702 REGNO (reload_reg
));
4703 SET_REGNO_REG_SET (®_has_output_reload
,
4704 REGNO (XEXP (in_reg
, 0)));
4707 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4710 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4711 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4712 REGNO (rld
[i
].reg_rtx
))
4713 /* Make sure it is the inc/dec pseudo, and not
4714 some other (e.g. output operand) pseudo. */
4715 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4716 == REGNO (XEXP (in_reg
, 0))))
4718 SET_HARD_REG_BIT (reg_is_output_reload
,
4719 REGNO (rld
[i
].reg_rtx
));
4720 SET_REGNO_REG_SET (®_has_output_reload
,
4721 REGNO (XEXP (in_reg
, 0)));
4723 else if (code
== PRE_INC
|| code
== PRE_DEC
4724 || code
== POST_INC
|| code
== POST_DEC
)
4726 int in_regno
= REGNO (XEXP (in_reg
, 0));
4728 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4731 bool forget_p
= true;
4733 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4734 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4737 for (rtx_insn
*x
= (old_prev
?
4738 NEXT_INSN (old_prev
) : insn
);
4741 if (x
== reg_reloaded_insn
[in_hard_regno
])
4747 /* If for some reasons, we didn't set up
4748 reg_last_reload_reg in this insn,
4749 invalidate inheritance from previous
4750 insns for the incremented/decremented
4751 register. Such registers will be not in
4752 reg_has_output_reload. Invalidate it
4753 also if the corresponding element in
4754 reg_reloaded_insn is also
4757 forget_old_reloads_1 (XEXP (in_reg
, 0),
4763 /* If a pseudo that got a hard register is auto-incremented,
4764 we must purge records of copying it into pseudos without
4766 for (rtx x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4767 if (REG_NOTE_KIND (x
) == REG_INC
)
4769 /* See if this pseudo reg was reloaded in this insn.
4770 If so, its last-reload info is still valid
4771 because it is based on this insn's reload. */
4772 for (i
= 0; i
< n_reloads
; i
++)
4773 if (rld
[i
].out
== XEXP (x
, 0))
4777 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4781 /* A reload reg's contents are unknown after a label. */
4783 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4785 /* Don't assume a reload reg is still good after a call insn
4786 if it is a call-used reg, or if it contains a value that will
4787 be partially clobbered by the call. */
4788 else if (CALL_P (insn
))
4790 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4791 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4793 /* If this is a call to a setjmp-type function, we must not
4794 reuse any reload reg contents across the call; that will
4795 just be clobbered by other uses of the register in later
4796 code, before the longjmp. */
4797 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4798 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4803 free (reg_last_reload_reg
);
4804 CLEAR_REG_SET (®_has_output_reload
);
4807 /* Discard all record of any value reloaded from X,
4808 or reloaded in X from someplace else;
4809 unless X is an output reload reg of the current insn.
4811 X may be a hard reg (the reload reg)
4812 or it may be a pseudo reg that was reloaded from.
4814 When DATA is non-NULL just mark the registers in regset
4815 to be forgotten later. */
4818 forget_old_reloads_1 (rtx x
, const_rtx setter
,
4823 regset regs
= (regset
) data
;
4825 /* note_stores does give us subregs of hard regs,
4826 subreg_regno_offset requires a hard reg. */
4827 while (GET_CODE (x
) == SUBREG
)
4829 /* We ignore the subreg offset when calculating the regno,
4830 because we are using the entire underlying hard register
4838 /* CLOBBER_HIGH is only supported for LRA. */
4839 gcc_assert (setter
== NULL_RTX
|| GET_CODE (setter
) != CLOBBER_HIGH
);
4843 if (regno
>= FIRST_PSEUDO_REGISTER
)
4850 /* Storing into a spilled-reg invalidates its contents.
4851 This can happen if a block-local pseudo is allocated to that reg
4852 and it wasn't spilled because this block's total need is 0.
4853 Then some insn might have an optional reload and use this reg. */
4855 for (i
= 0; i
< nr
; i
++)
4856 /* But don't do this if the reg actually serves as an output
4857 reload reg in the current instruction. */
4859 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4861 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4862 spill_reg_store
[regno
+ i
] = 0;
4868 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4871 /* Since value of X has changed,
4872 forget any value previously copied from it. */
4875 /* But don't forget a copy if this is the output reload
4876 that establishes the copy's validity. */
4878 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4879 reg_last_reload_reg
[regno
+ nr
] = 0;
4883 /* Forget the reloads marked in regset by previous function. */
4885 forget_marked_reloads (regset regs
)
4888 reg_set_iterator rsi
;
4889 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4891 if (reg
< FIRST_PSEUDO_REGISTER
4892 /* But don't do this if the reg actually serves as an output
4893 reload reg in the current instruction. */
4895 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4897 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4898 spill_reg_store
[reg
] = 0;
4901 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4902 reg_last_reload_reg
[reg
] = 0;
4906 /* The following HARD_REG_SETs indicate when each hard register is
4907 used for a reload of various parts of the current insn. */
4909 /* If reg is unavailable for all reloads. */
4910 static HARD_REG_SET reload_reg_unavailable
;
4911 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4912 static HARD_REG_SET reload_reg_used
;
4913 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4914 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4915 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4916 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4917 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4918 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4919 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4920 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4921 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4922 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4923 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4924 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4925 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4926 static HARD_REG_SET reload_reg_used_in_op_addr
;
4927 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4928 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4929 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4930 static HARD_REG_SET reload_reg_used_in_insn
;
4931 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4932 static HARD_REG_SET reload_reg_used_in_other_addr
;
4934 /* If reg is in use as a reload reg for any sort of reload. */
4935 static HARD_REG_SET reload_reg_used_at_all
;
4937 /* If reg is use as an inherited reload. We just mark the first register
4939 static HARD_REG_SET reload_reg_used_for_inherit
;
4941 /* Records which hard regs are used in any way, either as explicit use or
4942 by being allocated to a pseudo during any point of the current insn. */
4943 static HARD_REG_SET reg_used_in_insn
;
4945 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4946 TYPE. MODE is used to indicate how many consecutive regs are
4950 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4956 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
4959 case RELOAD_FOR_INPUT_ADDRESS
:
4960 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
4963 case RELOAD_FOR_INPADDR_ADDRESS
:
4964 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
4967 case RELOAD_FOR_OUTPUT_ADDRESS
:
4968 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
4971 case RELOAD_FOR_OUTADDR_ADDRESS
:
4972 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
4975 case RELOAD_FOR_OPERAND_ADDRESS
:
4976 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
4979 case RELOAD_FOR_OPADDR_ADDR
:
4980 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
4983 case RELOAD_FOR_OTHER_ADDRESS
:
4984 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
4987 case RELOAD_FOR_INPUT
:
4988 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
4991 case RELOAD_FOR_OUTPUT
:
4992 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
4995 case RELOAD_FOR_INSN
:
4996 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5000 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5003 /* Similarly, but show REGNO is no longer in use for a reload. */
5006 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5007 enum reload_type type
, machine_mode mode
)
5009 unsigned int nregs
= hard_regno_nregs (regno
, mode
);
5010 unsigned int start_regno
, end_regno
, r
;
5012 /* A complication is that for some reload types, inheritance might
5013 allow multiple reloads of the same types to share a reload register.
5014 We set check_opnum if we have to check only reloads with the same
5015 operand number, and check_any if we have to check all reloads. */
5016 int check_opnum
= 0;
5018 HARD_REG_SET
*used_in_set
;
5023 used_in_set
= &reload_reg_used
;
5026 case RELOAD_FOR_INPUT_ADDRESS
:
5027 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5030 case RELOAD_FOR_INPADDR_ADDRESS
:
5032 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5035 case RELOAD_FOR_OUTPUT_ADDRESS
:
5036 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5039 case RELOAD_FOR_OUTADDR_ADDRESS
:
5041 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5044 case RELOAD_FOR_OPERAND_ADDRESS
:
5045 used_in_set
= &reload_reg_used_in_op_addr
;
5048 case RELOAD_FOR_OPADDR_ADDR
:
5050 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5053 case RELOAD_FOR_OTHER_ADDRESS
:
5054 used_in_set
= &reload_reg_used_in_other_addr
;
5058 case RELOAD_FOR_INPUT
:
5059 used_in_set
= &reload_reg_used_in_input
[opnum
];
5062 case RELOAD_FOR_OUTPUT
:
5063 used_in_set
= &reload_reg_used_in_output
[opnum
];
5066 case RELOAD_FOR_INSN
:
5067 used_in_set
= &reload_reg_used_in_insn
;
5072 /* We resolve conflicts with remaining reloads of the same type by
5073 excluding the intervals of reload registers by them from the
5074 interval of freed reload registers. Since we only keep track of
5075 one set of interval bounds, we might have to exclude somewhat
5076 more than what would be necessary if we used a HARD_REG_SET here.
5077 But this should only happen very infrequently, so there should
5078 be no reason to worry about it. */
5080 start_regno
= regno
;
5081 end_regno
= regno
+ nregs
;
5082 if (check_opnum
|| check_any
)
5084 for (i
= n_reloads
- 1; i
>= 0; i
--)
5086 if (rld
[i
].when_needed
== type
5087 && (check_any
|| rld
[i
].opnum
== opnum
)
5090 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5091 unsigned int conflict_end
5092 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5094 /* If there is an overlap with the first to-be-freed register,
5095 adjust the interval start. */
5096 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5097 start_regno
= conflict_end
;
5098 /* Otherwise, if there is a conflict with one of the other
5099 to-be-freed registers, adjust the interval end. */
5100 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5101 end_regno
= conflict_start
;
5106 for (r
= start_regno
; r
< end_regno
; r
++)
5107 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5110 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5111 specified by OPNUM and TYPE. */
5114 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5118 /* In use for a RELOAD_OTHER means it's not available for anything. */
5119 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5120 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5126 /* In use for anything means we can't use it for RELOAD_OTHER. */
5127 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5128 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5129 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5130 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5133 for (i
= 0; i
< reload_n_operands
; i
++)
5134 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5135 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5136 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5137 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5138 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5139 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5144 case RELOAD_FOR_INPUT
:
5145 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5146 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5149 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5152 /* If it is used for some other input, can't use it. */
5153 for (i
= 0; i
< reload_n_operands
; i
++)
5154 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5157 /* If it is used in a later operand's address, can't use it. */
5158 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5159 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5160 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5165 case RELOAD_FOR_INPUT_ADDRESS
:
5166 /* Can't use a register if it is used for an input address for this
5167 operand or used as an input in an earlier one. */
5168 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5169 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5172 for (i
= 0; i
< opnum
; i
++)
5173 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5178 case RELOAD_FOR_INPADDR_ADDRESS
:
5179 /* Can't use a register if it is used for an input address
5180 for this operand or used as an input in an earlier
5182 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5185 for (i
= 0; i
< opnum
; i
++)
5186 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5191 case RELOAD_FOR_OUTPUT_ADDRESS
:
5192 /* Can't use a register if it is used for an output address for this
5193 operand or used as an output in this or a later operand. Note
5194 that multiple output operands are emitted in reverse order, so
5195 the conflicting ones are those with lower indices. */
5196 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5199 for (i
= 0; i
<= opnum
; i
++)
5200 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5205 case RELOAD_FOR_OUTADDR_ADDRESS
:
5206 /* Can't use a register if it is used for an output address
5207 for this operand or used as an output in this or a
5208 later operand. Note that multiple output operands are
5209 emitted in reverse order, so the conflicting ones are
5210 those with lower indices. */
5211 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5214 for (i
= 0; i
<= opnum
; i
++)
5215 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5220 case RELOAD_FOR_OPERAND_ADDRESS
:
5221 for (i
= 0; i
< reload_n_operands
; i
++)
5222 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5225 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5226 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5228 case RELOAD_FOR_OPADDR_ADDR
:
5229 for (i
= 0; i
< reload_n_operands
; i
++)
5230 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5233 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5235 case RELOAD_FOR_OUTPUT
:
5236 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5237 outputs, or an operand address for this or an earlier output.
5238 Note that multiple output operands are emitted in reverse order,
5239 so the conflicting ones are those with higher indices. */
5240 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5243 for (i
= 0; i
< reload_n_operands
; i
++)
5244 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5247 for (i
= opnum
; i
< reload_n_operands
; i
++)
5248 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5249 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5254 case RELOAD_FOR_INSN
:
5255 for (i
= 0; i
< reload_n_operands
; i
++)
5256 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5257 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5260 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5261 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5263 case RELOAD_FOR_OTHER_ADDRESS
:
5264 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5271 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5272 the number RELOADNUM, is still available in REGNO at the end of the insn.
5274 We can assume that the reload reg was already tested for availability
5275 at the time it is needed, and we should not check this again,
5276 in case the reg has already been marked in use. */
5279 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5281 int opnum
= rld
[reloadnum
].opnum
;
5282 enum reload_type type
= rld
[reloadnum
].when_needed
;
5285 /* See if there is a reload with the same type for this operand, using
5286 the same register. This case is not handled by the code below. */
5287 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5291 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5293 reg
= rld
[i
].reg_rtx
;
5294 if (reg
== NULL_RTX
)
5296 if (regno
>= REGNO (reg
) && regno
< END_REGNO (reg
))
5303 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5304 its value must reach the end. */
5307 /* If this use is for part of the insn,
5308 its value reaches if no subsequent part uses the same register.
5309 Just like the above function, don't try to do this with lots
5312 case RELOAD_FOR_OTHER_ADDRESS
:
5313 /* Here we check for everything else, since these don't conflict
5314 with anything else and everything comes later. */
5316 for (i
= 0; i
< reload_n_operands
; i
++)
5317 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5318 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5319 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5320 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5321 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5322 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5325 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5326 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5327 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5328 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5330 case RELOAD_FOR_INPUT_ADDRESS
:
5331 case RELOAD_FOR_INPADDR_ADDRESS
:
5332 /* Similar, except that we check only for this and subsequent inputs
5333 and the address of only subsequent inputs and we do not need
5334 to check for RELOAD_OTHER objects since they are known not to
5337 for (i
= opnum
; i
< reload_n_operands
; i
++)
5338 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5341 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5342 could be killed if the register is also used by reload with type
5343 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5344 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5345 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5348 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5349 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5350 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5353 for (i
= 0; i
< reload_n_operands
; i
++)
5354 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5355 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5356 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5359 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5362 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5363 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5364 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5366 case RELOAD_FOR_INPUT
:
5367 /* Similar to input address, except we start at the next operand for
5368 both input and input address and we do not check for
5369 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5372 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5373 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5374 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5375 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5378 /* ... fall through ... */
5380 case RELOAD_FOR_OPERAND_ADDRESS
:
5381 /* Check outputs and their addresses. */
5383 for (i
= 0; i
< reload_n_operands
; i
++)
5384 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5385 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5386 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5389 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5391 case RELOAD_FOR_OPADDR_ADDR
:
5392 for (i
= 0; i
< reload_n_operands
; i
++)
5393 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5394 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5395 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5398 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5399 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5400 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5402 case RELOAD_FOR_INSN
:
5403 /* These conflict with other outputs with RELOAD_OTHER. So
5404 we need only check for output addresses. */
5406 opnum
= reload_n_operands
;
5410 case RELOAD_FOR_OUTPUT
:
5411 case RELOAD_FOR_OUTPUT_ADDRESS
:
5412 case RELOAD_FOR_OUTADDR_ADDRESS
:
5413 /* We already know these can't conflict with a later output. So the
5414 only thing to check are later output addresses.
5415 Note that multiple output operands are emitted in reverse order,
5416 so the conflicting ones are those with lower indices. */
5417 for (i
= 0; i
< opnum
; i
++)
5418 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5419 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5422 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5423 could be killed if the register is also used by reload with type
5424 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5425 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5426 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5436 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5437 every register in REG. */
5440 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5444 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5445 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5451 /* Returns whether R1 and R2 are uniquely chained: the value of one
5452 is used by the other, and that value is not used by any other
5453 reload for this insn. This is used to partially undo the decision
5454 made in find_reloads when in the case of multiple
5455 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5456 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5457 reloads. This code tries to avoid the conflict created by that
5458 change. It might be cleaner to explicitly keep track of which
5459 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5460 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5461 this after the fact. */
5463 reloads_unique_chain_p (int r1
, int r2
)
5467 /* We only check input reloads. */
5468 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5471 /* Avoid anything with output reloads. */
5472 if (rld
[r1
].out
|| rld
[r2
].out
)
5475 /* "chained" means one reload is a component of the other reload,
5476 not the same as the other reload. */
5477 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5478 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5479 || rld
[r1
].optional
|| rld
[r2
].optional
5480 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5481 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5484 /* The following loop assumes that r1 is the reload that feeds r2. */
5488 for (i
= 0; i
< n_reloads
; i
++)
5489 /* Look for input reloads that aren't our two */
5490 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5492 /* If our reload is mentioned at all, it isn't a simple chain. */
5493 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5499 /* The recursive function change all occurrences of WHAT in *WHERE
5502 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5511 if (*where
== what
|| rtx_equal_p (*where
, what
))
5513 /* Record the location of the changed rtx. */
5514 substitute_stack
.safe_push (where
);
5519 code
= GET_CODE (*where
);
5520 fmt
= GET_RTX_FORMAT (code
);
5521 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5527 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5528 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5530 else if (fmt
[i
] == 'e')
5531 substitute (&XEXP (*where
, i
), what
, repl
);
5535 /* The function returns TRUE if chain of reload R1 and R2 (in any
5536 order) can be evaluated without usage of intermediate register for
5537 the reload containing another reload. It is important to see
5538 gen_reload to understand what the function is trying to do. As an
5539 example, let us have reload chain
5542 r1: <something> + const
5544 and reload R2 got reload reg HR. The function returns true if
5545 there is a correct insn HR = HR + <something>. Otherwise,
5546 gen_reload will use intermediate register (and this is the reload
5547 reg for R1) to reload <something>.
5549 We need this function to find a conflict for chain reloads. In our
5550 example, if HR = HR + <something> is incorrect insn, then we cannot
5551 use HR as a reload register for R2. If we do use it then we get a
5560 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5562 /* Assume other cases in gen_reload are not possible for
5563 chain reloads or do need an intermediate hard registers. */
5568 rtx_insn
*last
= get_last_insn ();
5570 /* Make r2 a component of r1. */
5571 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5574 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5575 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5576 gcc_assert (regno
>= 0);
5577 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5579 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5581 /* If IN is a paradoxical SUBREG, remove it and try to put the
5582 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5583 strip_paradoxical_subreg (&in
, &out
);
5585 if (GET_CODE (in
) == PLUS
5586 && (REG_P (XEXP (in
, 0))
5587 || GET_CODE (XEXP (in
, 0)) == SUBREG
5588 || MEM_P (XEXP (in
, 0)))
5589 && (REG_P (XEXP (in
, 1))
5590 || GET_CODE (XEXP (in
, 1)) == SUBREG
5591 || CONSTANT_P (XEXP (in
, 1))
5592 || MEM_P (XEXP (in
, 1))))
5594 insn
= emit_insn (gen_rtx_SET (out
, in
));
5595 code
= recog_memoized (insn
);
5600 extract_insn (insn
);
5601 /* We want constrain operands to treat this insn strictly in
5602 its validity determination, i.e., the way it would after
5603 reload has completed. */
5604 result
= constrain_operands (1, get_enabled_alternatives (insn
));
5607 delete_insns_since (last
);
5610 /* Restore the original value at each changed address within R1. */
5611 while (!substitute_stack
.is_empty ())
5613 rtx
*where
= substitute_stack
.pop ();
5614 *where
= rld
[r2
].in
;
5620 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5623 This function uses the same algorithm as reload_reg_free_p above. */
5626 reloads_conflict (int r1
, int r2
)
5628 enum reload_type r1_type
= rld
[r1
].when_needed
;
5629 enum reload_type r2_type
= rld
[r2
].when_needed
;
5630 int r1_opnum
= rld
[r1
].opnum
;
5631 int r2_opnum
= rld
[r2
].opnum
;
5633 /* RELOAD_OTHER conflicts with everything. */
5634 if (r2_type
== RELOAD_OTHER
)
5637 /* Otherwise, check conflicts differently for each type. */
5641 case RELOAD_FOR_INPUT
:
5642 return (r2_type
== RELOAD_FOR_INSN
5643 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5644 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5645 || r2_type
== RELOAD_FOR_INPUT
5646 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5647 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5648 && r2_opnum
> r1_opnum
));
5650 case RELOAD_FOR_INPUT_ADDRESS
:
5651 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5652 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5654 case RELOAD_FOR_INPADDR_ADDRESS
:
5655 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5656 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5658 case RELOAD_FOR_OUTPUT_ADDRESS
:
5659 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5660 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5662 case RELOAD_FOR_OUTADDR_ADDRESS
:
5663 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5664 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5666 case RELOAD_FOR_OPERAND_ADDRESS
:
5667 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5668 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5669 && (!reloads_unique_chain_p (r1
, r2
)
5670 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5672 case RELOAD_FOR_OPADDR_ADDR
:
5673 return (r2_type
== RELOAD_FOR_INPUT
5674 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5676 case RELOAD_FOR_OUTPUT
:
5677 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5678 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5679 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5680 && r2_opnum
>= r1_opnum
));
5682 case RELOAD_FOR_INSN
:
5683 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5684 || r2_type
== RELOAD_FOR_INSN
5685 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5687 case RELOAD_FOR_OTHER_ADDRESS
:
5688 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5698 /* Indexed by reload number, 1 if incoming value
5699 inherited from previous insns. */
5700 static char reload_inherited
[MAX_RELOADS
];
5702 /* For an inherited reload, this is the insn the reload was inherited from,
5703 if we know it. Otherwise, this is 0. */
5704 static rtx_insn
*reload_inheritance_insn
[MAX_RELOADS
];
5706 /* If nonzero, this is a place to get the value of the reload,
5707 rather than using reload_in. */
5708 static rtx reload_override_in
[MAX_RELOADS
];
5710 /* For each reload, the hard register number of the register used,
5711 or -1 if we did not need a register for this reload. */
5712 static int reload_spill_index
[MAX_RELOADS
];
5714 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5715 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5717 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5718 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5720 /* Subroutine of free_for_value_p, used to check a single register.
5721 START_REGNO is the starting regno of the full reload register
5722 (possibly comprising multiple hard registers) that we are considering. */
5725 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5726 enum reload_type type
, rtx value
, rtx out
,
5727 int reloadnum
, int ignore_address_reloads
)
5730 /* Set if we see an input reload that must not share its reload register
5731 with any new earlyclobber, but might otherwise share the reload
5732 register with an output or input-output reload. */
5733 int check_earlyclobber
= 0;
5737 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5740 if (out
== const0_rtx
)
5746 /* We use some pseudo 'time' value to check if the lifetimes of the
5747 new register use would overlap with the one of a previous reload
5748 that is not read-only or uses a different value.
5749 The 'time' used doesn't have to be linear in any shape or form, just
5751 Some reload types use different 'buckets' for each operand.
5752 So there are MAX_RECOG_OPERANDS different time values for each
5754 We compute TIME1 as the time when the register for the prospective
5755 new reload ceases to be live, and TIME2 for each existing
5756 reload as the time when that the reload register of that reload
5758 Where there is little to be gained by exact lifetime calculations,
5759 we just make conservative assumptions, i.e. a longer lifetime;
5760 this is done in the 'default:' cases. */
5763 case RELOAD_FOR_OTHER_ADDRESS
:
5764 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5765 time1
= copy
? 0 : 1;
5768 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5770 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5771 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5772 respectively, to the time values for these, we get distinct time
5773 values. To get distinct time values for each operand, we have to
5774 multiply opnum by at least three. We round that up to four because
5775 multiply by four is often cheaper. */
5776 case RELOAD_FOR_INPADDR_ADDRESS
:
5777 time1
= opnum
* 4 + 2;
5779 case RELOAD_FOR_INPUT_ADDRESS
:
5780 time1
= opnum
* 4 + 3;
5782 case RELOAD_FOR_INPUT
:
5783 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5784 executes (inclusive). */
5785 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5787 case RELOAD_FOR_OPADDR_ADDR
:
5789 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5790 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5792 case RELOAD_FOR_OPERAND_ADDRESS
:
5793 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5795 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5797 case RELOAD_FOR_OUTADDR_ADDRESS
:
5798 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5800 case RELOAD_FOR_OUTPUT_ADDRESS
:
5801 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5804 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5807 for (i
= 0; i
< n_reloads
; i
++)
5809 rtx reg
= rld
[i
].reg_rtx
;
5810 if (reg
&& REG_P (reg
)
5811 && (unsigned) regno
- true_regnum (reg
) < REG_NREGS (reg
)
5814 rtx other_input
= rld
[i
].in
;
5816 /* If the other reload loads the same input value, that
5817 will not cause a conflict only if it's loading it into
5818 the same register. */
5819 if (true_regnum (reg
) != start_regno
)
5820 other_input
= NULL_RTX
;
5821 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5822 || rld
[i
].out
|| out
)
5825 switch (rld
[i
].when_needed
)
5827 case RELOAD_FOR_OTHER_ADDRESS
:
5830 case RELOAD_FOR_INPADDR_ADDRESS
:
5831 /* find_reloads makes sure that a
5832 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5833 by at most one - the first -
5834 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5835 address reload is inherited, the address address reload
5836 goes away, so we can ignore this conflict. */
5837 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5838 && ignore_address_reloads
5839 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5840 Then the address address is still needed to store
5841 back the new address. */
5842 && ! rld
[reloadnum
].out
)
5844 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5845 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5847 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5848 && ignore_address_reloads
5849 /* Unless we are reloading an auto_inc expression. */
5850 && ! rld
[reloadnum
].out
)
5852 time2
= rld
[i
].opnum
* 4 + 2;
5854 case RELOAD_FOR_INPUT_ADDRESS
:
5855 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5856 && ignore_address_reloads
5857 && ! rld
[reloadnum
].out
)
5859 time2
= rld
[i
].opnum
* 4 + 3;
5861 case RELOAD_FOR_INPUT
:
5862 time2
= rld
[i
].opnum
* 4 + 4;
5863 check_earlyclobber
= 1;
5865 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5866 == MAX_RECOG_OPERAND * 4 */
5867 case RELOAD_FOR_OPADDR_ADDR
:
5868 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5869 && ignore_address_reloads
5870 && ! rld
[reloadnum
].out
)
5872 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5874 case RELOAD_FOR_OPERAND_ADDRESS
:
5875 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5876 check_earlyclobber
= 1;
5878 case RELOAD_FOR_INSN
:
5879 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5881 case RELOAD_FOR_OUTPUT
:
5882 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5883 instruction is executed. */
5884 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5886 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5887 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5889 case RELOAD_FOR_OUTADDR_ADDRESS
:
5890 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5891 && ignore_address_reloads
5892 && ! rld
[reloadnum
].out
)
5894 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5896 case RELOAD_FOR_OUTPUT_ADDRESS
:
5897 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5900 /* If there is no conflict in the input part, handle this
5901 like an output reload. */
5902 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5904 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5905 /* Earlyclobbered outputs must conflict with inputs. */
5906 if (earlyclobber_operand_p (rld
[i
].out
))
5907 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5912 /* RELOAD_OTHER might be live beyond instruction execution,
5913 but this is not obvious when we set time2 = 1. So check
5914 here if there might be a problem with the new reload
5915 clobbering the register used by the RELOAD_OTHER. */
5923 && (! rld
[i
].in
|| rld
[i
].out
5924 || ! rtx_equal_p (other_input
, value
)))
5925 || (out
&& rld
[reloadnum
].out_reg
5926 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5932 /* Earlyclobbered outputs must conflict with inputs. */
5933 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5939 /* Return 1 if the value in reload reg REGNO, as used by a reload
5940 needed for the part of the insn specified by OPNUM and TYPE,
5941 may be used to load VALUE into it.
5943 MODE is the mode in which the register is used, this is needed to
5944 determine how many hard regs to test.
5946 Other read-only reloads with the same value do not conflict
5947 unless OUT is nonzero and these other reloads have to live while
5948 output reloads live.
5949 If OUT is CONST0_RTX, this is a special case: it means that the
5950 test should not be for using register REGNO as reload register, but
5951 for copying from register REGNO into the reload register.
5953 RELOADNUM is the number of the reload we want to load this value for;
5954 a reload does not conflict with itself.
5956 When IGNORE_ADDRESS_RELOADS is set, we cannot have conflicts with
5957 reloads that load an address for the very reload we are considering.
5959 The caller has to make sure that there is no conflict with the return
5963 free_for_value_p (int regno
, machine_mode mode
, int opnum
,
5964 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5965 int ignore_address_reloads
)
5967 int nregs
= hard_regno_nregs (regno
, mode
);
5969 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5970 value
, out
, reloadnum
,
5971 ignore_address_reloads
))
5976 /* Return nonzero if the rtx X is invariant over the current function. */
5977 /* ??? Actually, the places where we use this expect exactly what is
5978 tested here, and not everything that is function invariant. In
5979 particular, the frame pointer and arg pointer are special cased;
5980 pic_offset_table_rtx is not, and we must not spill these things to
5984 function_invariant_p (const_rtx x
)
5988 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5990 if (GET_CODE (x
) == PLUS
5991 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5992 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5997 /* Determine whether the reload reg X overlaps any rtx'es used for
5998 overriding inheritance. Return nonzero if so. */
6001 conflicts_with_override (rtx x
)
6004 for (i
= 0; i
< n_reloads
; i
++)
6005 if (reload_override_in
[i
]
6006 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6011 /* Give an error message saying we failed to find a reload for INSN,
6012 and clear out reload R. */
6014 failed_reload (rtx_insn
*insn
, int r
)
6016 if (asm_noperands (PATTERN (insn
)) < 0)
6017 /* It's the compiler's fault. */
6018 fatal_insn ("could not find a spill register", insn
);
6020 /* It's the user's fault; the operand's mode and constraint
6021 don't match. Disable this reload so we don't crash in final. */
6022 error_for_asm (insn
,
6023 "%<asm%> operand constraint incompatible with operand size");
6027 rld
[r
].optional
= 1;
6028 rld
[r
].secondary_p
= 1;
6031 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6032 for reload R. If it's valid, get an rtx for it. Return nonzero if
6035 set_reload_reg (int i
, int r
)
6038 rtx reg
= spill_reg_rtx
[i
];
6040 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6041 spill_reg_rtx
[i
] = reg
6042 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6044 regno
= true_regnum (reg
);
6046 /* Detect when the reload reg can't hold the reload mode.
6047 This used to be one `if', but Sequent compiler can't handle that. */
6048 if (targetm
.hard_regno_mode_ok (regno
, rld
[r
].mode
))
6050 machine_mode test_mode
= VOIDmode
;
6052 test_mode
= GET_MODE (rld
[r
].in
);
6053 /* If rld[r].in has VOIDmode, it means we will load it
6054 in whatever mode the reload reg has: to wit, rld[r].mode.
6055 We have already tested that for validity. */
6056 /* Aside from that, we need to test that the expressions
6057 to reload from or into have modes which are valid for this
6058 reload register. Otherwise the reload insns would be invalid. */
6059 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6060 && !targetm
.hard_regno_mode_ok (regno
, test_mode
)))
6061 if (! (rld
[r
].out
!= 0
6062 && !targetm
.hard_regno_mode_ok (regno
, GET_MODE (rld
[r
].out
))))
6064 /* The reg is OK. */
6067 /* Mark as in use for this insn the reload regs we use
6069 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6070 rld
[r
].when_needed
, rld
[r
].mode
);
6072 rld
[r
].reg_rtx
= reg
;
6073 reload_spill_index
[r
] = spill_regs
[i
];
6080 /* Find a spill register to use as a reload register for reload R.
6081 LAST_RELOAD is nonzero if this is the last reload for the insn being
6084 Set rld[R].reg_rtx to the register allocated.
6086 We return 1 if successful, or 0 if we couldn't find a spill reg and
6087 we didn't change anything. */
6090 allocate_reload_reg (class insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6095 /* If we put this reload ahead, thinking it is a group,
6096 then insist on finding a group. Otherwise we can grab a
6097 reg that some other reload needs.
6098 (That can happen when we have a 68000 DATA_OR_FP_REG
6099 which is a group of data regs or one fp reg.)
6100 We need not be so restrictive if there are no more reloads
6103 ??? Really it would be nicer to have smarter handling
6104 for that kind of reg class, where a problem like this is normal.
6105 Perhaps those classes should be avoided for reloading
6106 by use of more alternatives. */
6108 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6110 /* If we want a single register and haven't yet found one,
6111 take any reg in the right class and not in use.
6112 If we want a consecutive group, here is where we look for it.
6114 We use three passes so we can first look for reload regs to
6115 reuse, which are already in use for other reloads in this insn,
6116 and only then use additional registers which are not "bad", then
6117 finally any register.
6119 I think that maximizing reuse is needed to make sure we don't
6120 run out of reload regs. Suppose we have three reloads, and
6121 reloads A and B can share regs. These need two regs.
6122 Suppose A and B are given different regs.
6123 That leaves none for C. */
6124 for (pass
= 0; pass
< 3; pass
++)
6126 /* I is the index in spill_regs.
6127 We advance it round-robin between insns to use all spill regs
6128 equally, so that inherited reloads have a chance
6129 of leapfrogging each other. */
6133 for (count
= 0; count
< n_spills
; count
++)
6135 int rclass
= (int) rld
[r
].rclass
;
6141 regnum
= spill_regs
[i
];
6143 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6146 /* We check reload_reg_used to make sure we
6147 don't clobber the return register. */
6148 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6149 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6150 rld
[r
].when_needed
, rld
[r
].in
,
6152 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6153 && targetm
.hard_regno_mode_ok (regnum
, rld
[r
].mode
)
6154 /* Look first for regs to share, then for unshared. But
6155 don't share regs used for inherited reloads; they are
6156 the ones we want to preserve. */
6158 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6160 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6163 int nr
= hard_regno_nregs (regnum
, rld
[r
].mode
);
6165 /* During the second pass we want to avoid reload registers
6166 which are "bad" for this reload. */
6168 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6171 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6172 (on 68000) got us two FP regs. If NR is 1,
6173 we would reject both of them. */
6176 /* If we need only one reg, we have already won. */
6179 /* But reject a single reg if we demand a group. */
6184 /* Otherwise check that as many consecutive regs as we need
6185 are available here. */
6188 int regno
= regnum
+ nr
- 1;
6189 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6190 && spill_reg_order
[regno
] >= 0
6191 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6192 rld
[r
].when_needed
)))
6201 /* If we found something on the current pass, omit later passes. */
6202 if (count
< n_spills
)
6206 /* We should have found a spill register by now. */
6207 if (count
>= n_spills
)
6210 /* I is the index in SPILL_REG_RTX of the reload register we are to
6211 allocate. Get an rtx for it and find its register number. */
6213 return set_reload_reg (i
, r
);
6216 /* Initialize all the tables needed to allocate reload registers.
6217 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6218 is the array we use to restore the reg_rtx field for every reload. */
6221 choose_reload_regs_init (class insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6225 for (i
= 0; i
< n_reloads
; i
++)
6226 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6228 memset (reload_inherited
, 0, MAX_RELOADS
);
6229 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6230 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6232 CLEAR_HARD_REG_SET (reload_reg_used
);
6233 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6234 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6235 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6236 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6237 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6239 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6242 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6243 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6244 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6245 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6246 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6247 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6250 for (i
= 0; i
< reload_n_operands
; i
++)
6252 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6253 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6254 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6255 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6256 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6257 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6260 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6262 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6264 for (i
= 0; i
< n_reloads
; i
++)
6265 /* If we have already decided to use a certain register,
6266 don't use it in another way. */
6268 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6269 rld
[i
].when_needed
, rld
[i
].mode
);
6272 /* If X is not a subreg, return it unmodified. If it is a subreg,
6273 look up whether we made a replacement for the SUBREG_REG. Return
6274 either the replacement or the SUBREG_REG. */
6277 replaced_subreg (rtx x
)
6279 if (GET_CODE (x
) == SUBREG
)
6280 return find_replacement (&SUBREG_REG (x
));
6284 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6285 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6286 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6287 otherwise it is NULL. */
6290 compute_reload_subreg_offset (machine_mode outermode
,
6292 machine_mode innermode
)
6294 poly_int64 outer_offset
;
6295 machine_mode middlemode
;
6298 return subreg_lowpart_offset (outermode
, innermode
);
6300 outer_offset
= SUBREG_BYTE (subreg
);
6301 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6303 /* If SUBREG is paradoxical then return the normal lowpart offset
6304 for OUTERMODE and INNERMODE. Our caller has already checked
6305 that OUTERMODE fits in INNERMODE. */
6306 if (paradoxical_subreg_p (outermode
, middlemode
))
6307 return subreg_lowpart_offset (outermode
, innermode
);
6309 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6310 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6311 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6314 /* Assign hard reg targets for the pseudo-registers we must reload
6315 into hard regs for this insn.
6316 Also output the instructions to copy them in and out of the hard regs.
6318 For machines with register classes, we are responsible for
6319 finding a reload reg in the proper class. */
6322 choose_reload_regs (class insn_chain
*chain
)
6324 rtx_insn
*insn
= chain
->insn
;
6326 unsigned int max_group_size
= 1;
6327 enum reg_class group_class
= NO_REGS
;
6328 int pass
, win
, inheritance
;
6330 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6332 /* In order to be certain of getting the registers we need,
6333 we must sort the reloads into order of increasing register class.
6334 Then our grabbing of reload registers will parallel the process
6335 that provided the reload registers.
6337 Also note whether any of the reloads wants a consecutive group of regs.
6338 If so, record the maximum size of the group desired and what
6339 register class contains all the groups needed by this insn. */
6341 for (j
= 0; j
< n_reloads
; j
++)
6343 reload_order
[j
] = j
;
6344 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6346 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6347 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6348 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6351 reload_spill_index
[j
] = -1;
6353 if (rld
[j
].nregs
> 1)
6355 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6357 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6360 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6364 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6366 /* If -O, try first with inheritance, then turning it off.
6367 If not -O, don't do inheritance.
6368 Using inheritance when not optimizing leads to paradoxes
6369 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6370 because one side of the comparison might be inherited. */
6372 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6374 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6376 /* Process the reloads in order of preference just found.
6377 Beyond this point, subregs can be found in reload_reg_rtx.
6379 This used to look for an existing reloaded home for all of the
6380 reloads, and only then perform any new reloads. But that could lose
6381 if the reloads were done out of reg-class order because a later
6382 reload with a looser constraint might have an old home in a register
6383 needed by an earlier reload with a tighter constraint.
6385 To solve this, we make two passes over the reloads, in the order
6386 described above. In the first pass we try to inherit a reload
6387 from a previous insn. If there is a later reload that needs a
6388 class that is a proper subset of the class being processed, we must
6389 also allocate a spill register during the first pass.
6391 Then make a second pass over the reloads to allocate any reloads
6392 that haven't been given registers yet. */
6394 for (j
= 0; j
< n_reloads
; j
++)
6396 int r
= reload_order
[j
];
6397 rtx search_equiv
= NULL_RTX
;
6399 /* Ignore reloads that got marked inoperative. */
6400 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6401 && ! rld
[r
].secondary_p
)
6404 /* If find_reloads chose to use reload_in or reload_out as a reload
6405 register, we don't need to chose one. Otherwise, try even if it
6406 found one since we might save an insn if we find the value lying
6408 Try also when reload_in is a pseudo without a hard reg. */
6409 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6410 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6411 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6412 && !MEM_P (rld
[r
].in
)
6413 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6416 #if 0 /* No longer needed for correct operation.
6417 It might give better code, or might not; worth an experiment? */
6418 /* If this is an optional reload, we can't inherit from earlier insns
6419 until we are sure that any non-optional reloads have been allocated.
6420 The following code takes advantage of the fact that optional reloads
6421 are at the end of reload_order. */
6422 if (rld
[r
].optional
!= 0)
6423 for (i
= 0; i
< j
; i
++)
6424 if ((rld
[reload_order
[i
]].out
!= 0
6425 || rld
[reload_order
[i
]].in
!= 0
6426 || rld
[reload_order
[i
]].secondary_p
)
6427 && ! rld
[reload_order
[i
]].optional
6428 && rld
[reload_order
[i
]].reg_rtx
== 0)
6429 allocate_reload_reg (chain
, reload_order
[i
], 0);
6432 /* First see if this pseudo is already available as reloaded
6433 for a previous insn. We cannot try to inherit for reloads
6434 that are smaller than the maximum number of registers needed
6435 for groups unless the register we would allocate cannot be used
6438 We could check here to see if this is a secondary reload for
6439 an object that is already in a register of the desired class.
6440 This would avoid the need for the secondary reload register.
6441 But this is complex because we can't easily determine what
6442 objects might want to be loaded via this reload. So let a
6443 register be allocated here. In `emit_reload_insns' we suppress
6444 one of the loads in the case described above. */
6448 poly_int64 byte
= 0;
6450 machine_mode mode
= VOIDmode
;
6451 rtx subreg
= NULL_RTX
;
6455 else if (REG_P (rld
[r
].in
))
6457 regno
= REGNO (rld
[r
].in
);
6458 mode
= GET_MODE (rld
[r
].in
);
6460 else if (REG_P (rld
[r
].in_reg
))
6462 regno
= REGNO (rld
[r
].in_reg
);
6463 mode
= GET_MODE (rld
[r
].in_reg
);
6465 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6466 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6468 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6469 if (regno
< FIRST_PSEUDO_REGISTER
)
6470 regno
= subreg_regno (rld
[r
].in_reg
);
6473 subreg
= rld
[r
].in_reg
;
6474 byte
= SUBREG_BYTE (subreg
);
6476 mode
= GET_MODE (rld
[r
].in_reg
);
6479 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6480 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6482 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6483 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6484 rld
[r
].out
= rld
[r
].in
;
6488 /* This won't work, since REGNO can be a pseudo reg number.
6489 Also, it takes much more hair to keep track of all the things
6490 that can invalidate an inherited reload of part of a pseudoreg. */
6491 else if (GET_CODE (rld
[r
].in
) == SUBREG
6492 && REG_P (SUBREG_REG (rld
[r
].in
)))
6493 regno
= subreg_regno (rld
[r
].in
);
6497 && reg_last_reload_reg
[regno
] != 0
6499 (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
])),
6500 GET_MODE_SIZE (mode
) + byte
))
6501 /* Verify that the register it's in can be used in
6503 && (REG_CAN_CHANGE_MODE_P
6504 (REGNO (reg_last_reload_reg
[regno
]),
6505 GET_MODE (reg_last_reload_reg
[regno
]),
6508 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6509 rtx last_reg
= reg_last_reload_reg
[regno
];
6511 i
= REGNO (last_reg
);
6512 byte
= compute_reload_subreg_offset (mode
,
6514 GET_MODE (last_reg
));
6515 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6516 last_class
= REGNO_REG_CLASS (i
);
6518 if (reg_reloaded_contents
[i
] == regno
6519 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6520 && targetm
.hard_regno_mode_ok (i
, rld
[r
].mode
)
6521 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6522 /* Even if we can't use this register as a reload
6523 register, we might use it for reload_override_in,
6524 if copying it to the desired class is cheap
6526 || ((register_move_cost (mode
, last_class
, rclass
)
6527 < memory_move_cost (mode
, rclass
, true))
6528 && (secondary_reload_class (1, rclass
, mode
,
6531 && !(targetm
.secondary_memory_needed
6532 (mode
, last_class
, rclass
))))
6533 && (rld
[r
].nregs
== max_group_size
6534 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6536 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6537 rld
[r
].when_needed
, rld
[r
].in
,
6540 /* If a group is needed, verify that all the subsequent
6541 registers still have their values intact. */
6542 int nr
= hard_regno_nregs (i
, rld
[r
].mode
);
6545 for (k
= 1; k
< nr
; k
++)
6546 if (reg_reloaded_contents
[i
+ k
] != regno
6547 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6555 last_reg
= (GET_MODE (last_reg
) == mode
6556 ? last_reg
: gen_rtx_REG (mode
, i
));
6559 for (k
= 0; k
< nr
; k
++)
6560 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6563 /* We found a register that contains the
6564 value we need. If this register is the
6565 same as an `earlyclobber' operand of the
6566 current insn, just mark it as a place to
6567 reload from since we can't use it as the
6568 reload register itself. */
6570 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6571 if (reg_overlap_mentioned_for_reload_p
6572 (reg_last_reload_reg
[regno
],
6573 reload_earlyclobbers
[i1
]))
6576 if (i1
!= n_earlyclobbers
6577 || ! (free_for_value_p (i
, rld
[r
].mode
,
6579 rld
[r
].when_needed
, rld
[r
].in
,
6581 /* Don't use it if we'd clobber a pseudo reg. */
6582 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6584 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6585 /* Don't clobber the frame pointer. */
6586 || (i
== HARD_FRAME_POINTER_REGNUM
6587 && frame_pointer_needed
6589 /* Don't really use the inherited spill reg
6590 if we need it wider than we've got it. */
6591 || paradoxical_subreg_p (rld
[r
].mode
, mode
)
6594 /* If find_reloads chose reload_out as reload
6595 register, stay with it - that leaves the
6596 inherited register for subsequent reloads. */
6597 || (rld
[r
].out
&& rld
[r
].reg_rtx
6598 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6600 if (! rld
[r
].optional
)
6602 reload_override_in
[r
] = last_reg
;
6603 reload_inheritance_insn
[r
]
6604 = reg_reloaded_insn
[i
];
6610 /* We can use this as a reload reg. */
6611 /* Mark the register as in use for this part of
6613 mark_reload_reg_in_use (i
,
6617 rld
[r
].reg_rtx
= last_reg
;
6618 reload_inherited
[r
] = 1;
6619 reload_inheritance_insn
[r
]
6620 = reg_reloaded_insn
[i
];
6621 reload_spill_index
[r
] = i
;
6622 for (k
= 0; k
< nr
; k
++)
6623 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6631 /* Here's another way to see if the value is already lying around. */
6634 && ! reload_inherited
[r
]
6636 && (CONSTANT_P (rld
[r
].in
)
6637 || GET_CODE (rld
[r
].in
) == PLUS
6638 || REG_P (rld
[r
].in
)
6639 || MEM_P (rld
[r
].in
))
6640 && (rld
[r
].nregs
== max_group_size
6641 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6642 search_equiv
= rld
[r
].in
;
6647 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6648 -1, NULL
, 0, rld
[r
].mode
);
6654 regno
= REGNO (equiv
);
6657 /* This must be a SUBREG of a hard register.
6658 Make a new REG since this might be used in an
6659 address and not all machines support SUBREGs
6661 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6662 regno
= subreg_regno (equiv
);
6663 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6664 /* If we choose EQUIV as the reload register, but the
6665 loop below decides to cancel the inheritance, we'll
6666 end up reloading EQUIV in rld[r].mode, not the mode
6667 it had originally. That isn't safe when EQUIV isn't
6668 available as a spill register since its value might
6669 still be live at this point. */
6670 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6671 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6676 /* If we found a spill reg, reject it unless it is free
6677 and of the desired class. */
6681 int bad_for_class
= 0;
6682 int max_regno
= regno
+ rld
[r
].nregs
;
6684 for (i
= regno
; i
< max_regno
; i
++)
6686 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6688 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6693 && ! free_for_value_p (regno
, rld
[r
].mode
,
6694 rld
[r
].opnum
, rld
[r
].when_needed
,
6695 rld
[r
].in
, rld
[r
].out
, r
, 1))
6701 && !targetm
.hard_regno_mode_ok (regno
, rld
[r
].mode
))
6704 /* We found a register that contains the value we need.
6705 If this register is the same as an `earlyclobber' operand
6706 of the current insn, just mark it as a place to reload from
6707 since we can't use it as the reload register itself. */
6710 for (i
= 0; i
< n_earlyclobbers
; i
++)
6711 if (reg_overlap_mentioned_for_reload_p (equiv
,
6712 reload_earlyclobbers
[i
]))
6714 if (! rld
[r
].optional
)
6715 reload_override_in
[r
] = equiv
;
6720 /* If the equiv register we have found is explicitly clobbered
6721 in the current insn, it depends on the reload type if we
6722 can use it, use it for reload_override_in, or not at all.
6723 In particular, we then can't use EQUIV for a
6724 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6728 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6729 switch (rld
[r
].when_needed
)
6731 case RELOAD_FOR_OTHER_ADDRESS
:
6732 case RELOAD_FOR_INPADDR_ADDRESS
:
6733 case RELOAD_FOR_INPUT_ADDRESS
:
6734 case RELOAD_FOR_OPADDR_ADDR
:
6737 case RELOAD_FOR_INPUT
:
6738 case RELOAD_FOR_OPERAND_ADDRESS
:
6739 if (! rld
[r
].optional
)
6740 reload_override_in
[r
] = equiv
;
6746 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6747 switch (rld
[r
].when_needed
)
6749 case RELOAD_FOR_OTHER_ADDRESS
:
6750 case RELOAD_FOR_INPADDR_ADDRESS
:
6751 case RELOAD_FOR_INPUT_ADDRESS
:
6752 case RELOAD_FOR_OPADDR_ADDR
:
6753 case RELOAD_FOR_OPERAND_ADDRESS
:
6754 case RELOAD_FOR_INPUT
:
6757 if (! rld
[r
].optional
)
6758 reload_override_in
[r
] = equiv
;
6766 /* If we found an equivalent reg, say no code need be generated
6767 to load it, and use it as our reload reg. */
6769 && (regno
!= HARD_FRAME_POINTER_REGNUM
6770 || !frame_pointer_needed
))
6772 int nr
= hard_regno_nregs (regno
, rld
[r
].mode
);
6774 rld
[r
].reg_rtx
= equiv
;
6775 reload_spill_index
[r
] = regno
;
6776 reload_inherited
[r
] = 1;
6778 /* If reg_reloaded_valid is not set for this register,
6779 there might be a stale spill_reg_store lying around.
6780 We must clear it, since otherwise emit_reload_insns
6781 might delete the store. */
6782 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6783 spill_reg_store
[regno
] = NULL
;
6784 /* If any of the hard registers in EQUIV are spill
6785 registers, mark them as in use for this insn. */
6786 for (k
= 0; k
< nr
; k
++)
6788 i
= spill_reg_order
[regno
+ k
];
6791 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6794 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6801 /* If we found a register to use already, or if this is an optional
6802 reload, we are done. */
6803 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6807 /* No longer needed for correct operation. Might or might
6808 not give better code on the average. Want to experiment? */
6810 /* See if there is a later reload that has a class different from our
6811 class that intersects our class or that requires less register
6812 than our reload. If so, we must allocate a register to this
6813 reload now, since that reload might inherit a previous reload
6814 and take the only available register in our class. Don't do this
6815 for optional reloads since they will force all previous reloads
6816 to be allocated. Also don't do this for reloads that have been
6819 for (i
= j
+ 1; i
< n_reloads
; i
++)
6821 int s
= reload_order
[i
];
6823 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6824 && ! rld
[s
].secondary_p
)
6828 if ((rld
[s
].rclass
!= rld
[r
].rclass
6829 && reg_classes_intersect_p (rld
[r
].rclass
,
6831 || rld
[s
].nregs
< rld
[r
].nregs
)
6838 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6842 /* Now allocate reload registers for anything non-optional that
6843 didn't get one yet. */
6844 for (j
= 0; j
< n_reloads
; j
++)
6846 int r
= reload_order
[j
];
6848 /* Ignore reloads that got marked inoperative. */
6849 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6852 /* Skip reloads that already have a register allocated or are
6854 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6857 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6861 /* If that loop got all the way, we have won. */
6868 /* Loop around and try without any inheritance. */
6873 /* First undo everything done by the failed attempt
6874 to allocate with inheritance. */
6875 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6877 /* Some sanity tests to verify that the reloads found in the first
6878 pass are identical to the ones we have now. */
6879 gcc_assert (chain
->n_reloads
== n_reloads
);
6881 for (i
= 0; i
< n_reloads
; i
++)
6883 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6885 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6886 for (j
= 0; j
< n_spills
; j
++)
6887 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6888 if (! set_reload_reg (j
, i
))
6889 failed_reload (chain
->insn
, i
);
6893 /* If we thought we could inherit a reload, because it seemed that
6894 nothing else wanted the same reload register earlier in the insn,
6895 verify that assumption, now that all reloads have been assigned.
6896 Likewise for reloads where reload_override_in has been set. */
6898 /* If doing expensive optimizations, do one preliminary pass that doesn't
6899 cancel any inheritance, but removes reloads that have been needed only
6900 for reloads that we know can be inherited. */
6901 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6903 for (j
= 0; j
< n_reloads
; j
++)
6905 int r
= reload_order
[j
];
6908 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6909 check_reg
= rld
[r
].reg_rtx
;
6910 else if (reload_override_in
[r
]
6911 && (REG_P (reload_override_in
[r
])
6912 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6913 check_reg
= reload_override_in
[r
];
6916 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6917 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6918 (reload_inherited
[r
]
6919 ? rld
[r
].out
: const0_rtx
),
6924 reload_inherited
[r
] = 0;
6925 reload_override_in
[r
] = 0;
6927 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6928 reload_override_in, then we do not need its related
6929 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6930 likewise for other reload types.
6931 We handle this by removing a reload when its only replacement
6932 is mentioned in reload_in of the reload we are going to inherit.
6933 A special case are auto_inc expressions; even if the input is
6934 inherited, we still need the address for the output. We can
6935 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6936 If we succeeded removing some reload and we are doing a preliminary
6937 pass just to remove such reloads, make another pass, since the
6938 removal of one reload might allow us to inherit another one. */
6940 && rld
[r
].out
!= rld
[r
].in
6941 && remove_address_replacements (rld
[r
].in
))
6946 /* If we needed a memory location for the reload, we also have to
6947 remove its related reloads. */
6949 && rld
[r
].out
!= rld
[r
].in
6950 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
6951 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
6952 && (targetm
.secondary_memory_needed
6953 (rld
[r
].inmode
, REGNO_REG_CLASS (REGNO (tem
)),
6955 && remove_address_replacements
6956 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
6957 rld
[r
].when_needed
)))
6965 /* Now that reload_override_in is known valid,
6966 actually override reload_in. */
6967 for (j
= 0; j
< n_reloads
; j
++)
6968 if (reload_override_in
[j
])
6969 rld
[j
].in
= reload_override_in
[j
];
6971 /* If this reload won't be done because it has been canceled or is
6972 optional and not inherited, clear reload_reg_rtx so other
6973 routines (such as subst_reloads) don't get confused. */
6974 for (j
= 0; j
< n_reloads
; j
++)
6975 if (rld
[j
].reg_rtx
!= 0
6976 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6977 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6978 && ! rld
[j
].secondary_p
)))
6980 int regno
= true_regnum (rld
[j
].reg_rtx
);
6982 if (spill_reg_order
[regno
] >= 0)
6983 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6984 rld
[j
].when_needed
, rld
[j
].mode
);
6986 reload_spill_index
[j
] = -1;
6989 /* Record which pseudos and which spill regs have output reloads. */
6990 for (j
= 0; j
< n_reloads
; j
++)
6992 int r
= reload_order
[j
];
6994 i
= reload_spill_index
[r
];
6996 /* I is nonneg if this reload uses a register.
6997 If rld[r].reg_rtx is 0, this is an optional reload
6998 that we opted to ignore. */
6999 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7000 && rld
[r
].reg_rtx
!= 0)
7002 int nregno
= REGNO (rld
[r
].out_reg
);
7005 if (nregno
< FIRST_PSEUDO_REGISTER
)
7006 nr
= hard_regno_nregs (nregno
, rld
[r
].mode
);
7009 SET_REGNO_REG_SET (®_has_output_reload
,
7013 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7015 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7016 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7017 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7022 /* Deallocate the reload register for reload R. This is called from
7023 remove_address_replacements. */
7026 deallocate_reload_reg (int r
)
7030 if (! rld
[r
].reg_rtx
)
7032 regno
= true_regnum (rld
[r
].reg_rtx
);
7034 if (spill_reg_order
[regno
] >= 0)
7035 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7037 reload_spill_index
[r
] = -1;
7040 /* These arrays are filled by emit_reload_insns and its subroutines. */
7041 static rtx_insn
*input_reload_insns
[MAX_RECOG_OPERANDS
];
7042 static rtx_insn
*other_input_address_reload_insns
= 0;
7043 static rtx_insn
*other_input_reload_insns
= 0;
7044 static rtx_insn
*input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7045 static rtx_insn
*inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7046 static rtx_insn
*output_reload_insns
[MAX_RECOG_OPERANDS
];
7047 static rtx_insn
*output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7048 static rtx_insn
*outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7049 static rtx_insn
*operand_reload_insns
= 0;
7050 static rtx_insn
*other_operand_reload_insns
= 0;
7051 static rtx_insn
*other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7053 /* Values to be put in spill_reg_store are put here first. Instructions
7054 must only be placed here if the associated reload register reaches
7055 the end of the instruction's reload sequence. */
7056 static rtx_insn
*new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7057 static HARD_REG_SET reg_reloaded_died
;
7059 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7060 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7061 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7062 adjusted register, and return true. Otherwise, return false. */
7064 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7065 enum reg_class new_class
,
7066 machine_mode new_mode
)
7071 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7073 unsigned regno
= REGNO (reg
);
7075 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7077 if (GET_MODE (reg
) != new_mode
)
7079 if (!targetm
.hard_regno_mode_ok (regno
, new_mode
))
7081 if (hard_regno_nregs (regno
, new_mode
) > REG_NREGS (reg
))
7083 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7091 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7092 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7093 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7094 adjusted register, and return true. Otherwise, return false. */
7096 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7097 enum insn_code icode
)
7100 enum reg_class new_class
= scratch_reload_class (icode
);
7101 machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7103 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7104 new_class
, new_mode
);
7107 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7108 has the number J. OLD contains the value to be used as input. */
7111 emit_input_reload_insns (class insn_chain
*chain
, struct reload
*rl
,
7114 rtx_insn
*insn
= chain
->insn
;
7116 rtx oldequiv_reg
= 0;
7122 /* delete_output_reload is only invoked properly if old contains
7123 the original pseudo register. Since this is replaced with a
7124 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7125 find the pseudo in RELOAD_IN_REG. This is also used to
7126 determine whether a secondary reload is needed. */
7127 if (reload_override_in
[j
]
7128 && (REG_P (rl
->in_reg
)
7129 || (GET_CODE (rl
->in_reg
) == SUBREG
7130 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7137 else if (REG_P (oldequiv
))
7138 oldequiv_reg
= oldequiv
;
7139 else if (GET_CODE (oldequiv
) == SUBREG
)
7140 oldequiv_reg
= SUBREG_REG (oldequiv
);
7142 reloadreg
= reload_reg_rtx_for_input
[j
];
7143 mode
= GET_MODE (reloadreg
);
7145 /* If we are reloading from a register that was recently stored in
7146 with an output-reload, see if we can prove there was
7147 actually no need to store the old value in it. */
7149 if (optimize
&& REG_P (oldequiv
)
7150 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7151 && spill_reg_store
[REGNO (oldequiv
)]
7153 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7154 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7156 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7158 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7161 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7162 oldequiv
= SUBREG_REG (oldequiv
);
7163 if (GET_MODE (oldequiv
) != VOIDmode
7164 && mode
!= GET_MODE (oldequiv
))
7165 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7167 /* Switch to the right place to emit the reload insns. */
7168 switch (rl
->when_needed
)
7171 where
= &other_input_reload_insns
;
7173 case RELOAD_FOR_INPUT
:
7174 where
= &input_reload_insns
[rl
->opnum
];
7176 case RELOAD_FOR_INPUT_ADDRESS
:
7177 where
= &input_address_reload_insns
[rl
->opnum
];
7179 case RELOAD_FOR_INPADDR_ADDRESS
:
7180 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7182 case RELOAD_FOR_OUTPUT_ADDRESS
:
7183 where
= &output_address_reload_insns
[rl
->opnum
];
7185 case RELOAD_FOR_OUTADDR_ADDRESS
:
7186 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7188 case RELOAD_FOR_OPERAND_ADDRESS
:
7189 where
= &operand_reload_insns
;
7191 case RELOAD_FOR_OPADDR_ADDR
:
7192 where
= &other_operand_reload_insns
;
7194 case RELOAD_FOR_OTHER_ADDRESS
:
7195 where
= &other_input_address_reload_insns
;
7201 push_to_sequence (*where
);
7203 /* Auto-increment addresses must be reloaded in a special way. */
7204 if (rl
->out
&& ! rl
->out_reg
)
7206 /* We are not going to bother supporting the case where a
7207 incremented register can't be copied directly from
7208 OLDEQUIV since this seems highly unlikely. */
7209 gcc_assert (rl
->secondary_in_reload
< 0);
7211 if (reload_inherited
[j
])
7212 oldequiv
= reloadreg
;
7214 old
= XEXP (rl
->in_reg
, 0);
7216 /* Prevent normal processing of this reload. */
7218 /* Output a special code sequence for this case. */
7219 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7222 /* If we are reloading a pseudo-register that was set by the previous
7223 insn, see if we can get rid of that pseudo-register entirely
7224 by redirecting the previous insn into our reload register. */
7226 else if (optimize
&& REG_P (old
)
7227 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7228 && dead_or_set_p (insn
, old
)
7229 /* This is unsafe if some other reload
7230 uses the same reg first. */
7231 && ! conflicts_with_override (reloadreg
)
7232 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7233 rl
->when_needed
, old
, rl
->out
, j
, 0))
7235 rtx_insn
*temp
= PREV_INSN (insn
);
7236 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7237 temp
= PREV_INSN (temp
);
7239 && NONJUMP_INSN_P (temp
)
7240 && GET_CODE (PATTERN (temp
)) == SET
7241 && SET_DEST (PATTERN (temp
)) == old
7242 /* Make sure we can access insn_operand_constraint. */
7243 && asm_noperands (PATTERN (temp
)) < 0
7244 /* This is unsafe if operand occurs more than once in current
7245 insn. Perhaps some occurrences aren't reloaded. */
7246 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7248 rtx old
= SET_DEST (PATTERN (temp
));
7249 /* Store into the reload register instead of the pseudo. */
7250 SET_DEST (PATTERN (temp
)) = reloadreg
;
7252 /* Verify that resulting insn is valid.
7254 Note that we have replaced the destination of TEMP with
7255 RELOADREG. If TEMP references RELOADREG within an
7256 autoincrement addressing mode, then the resulting insn
7257 is ill-formed and we must reject this optimization. */
7258 extract_insn (temp
);
7259 if (constrain_operands (1, get_enabled_alternatives (temp
))
7260 && (!AUTO_INC_DEC
|| ! find_reg_note (temp
, REG_INC
, reloadreg
)))
7262 /* If the previous insn is an output reload, the source is
7263 a reload register, and its spill_reg_store entry will
7264 contain the previous destination. This is now
7266 if (REG_P (SET_SRC (PATTERN (temp
)))
7267 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7269 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7270 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7273 /* If these are the only uses of the pseudo reg,
7274 pretend for GDB it lives in the reload reg we used. */
7275 if (REG_N_DEATHS (REGNO (old
)) == 1
7276 && REG_N_SETS (REGNO (old
)) == 1)
7278 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7279 if (ira_conflicts_p
)
7280 /* Inform IRA about the change. */
7281 ira_mark_allocation_change (REGNO (old
));
7282 alter_reg (REGNO (old
), -1, false);
7286 /* Adjust any debug insns between temp and insn. */
7287 while ((temp
= NEXT_INSN (temp
)) != insn
)
7288 if (DEBUG_BIND_INSN_P (temp
))
7289 INSN_VAR_LOCATION_LOC (temp
)
7290 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp
),
7293 gcc_assert (DEBUG_INSN_P (temp
) || NOTE_P (temp
));
7297 SET_DEST (PATTERN (temp
)) = old
;
7302 /* We can't do that, so output an insn to load RELOADREG. */
7304 /* If we have a secondary reload, pick up the secondary register
7305 and icode, if any. If OLDEQUIV and OLD are different or
7306 if this is an in-out reload, recompute whether or not we
7307 still need a secondary register and what the icode should
7308 be. If we still need a secondary register and the class or
7309 icode is different, go back to reloading from OLD if using
7310 OLDEQUIV means that we got the wrong type of register. We
7311 cannot have different class or icode due to an in-out reload
7312 because we don't make such reloads when both the input and
7313 output need secondary reload registers. */
7315 if (! special
&& rl
->secondary_in_reload
>= 0)
7317 rtx second_reload_reg
= 0;
7318 rtx third_reload_reg
= 0;
7319 int secondary_reload
= rl
->secondary_in_reload
;
7320 rtx real_oldequiv
= oldequiv
;
7323 enum insn_code icode
;
7324 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7326 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7327 and similarly for OLD.
7328 See comments in get_secondary_reload in reload.c. */
7329 /* If it is a pseudo that cannot be replaced with its
7330 equivalent MEM, we must fall back to reload_in, which
7331 will have all the necessary substitutions registered.
7332 Likewise for a pseudo that can't be replaced with its
7333 equivalent constant.
7335 Take extra care for subregs of such pseudos. Note that
7336 we cannot use reg_equiv_mem in this case because it is
7337 not in the right mode. */
7340 if (GET_CODE (tmp
) == SUBREG
)
7341 tmp
= SUBREG_REG (tmp
);
7343 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7344 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7345 || reg_equiv_constant (REGNO (tmp
)) != 0))
7347 if (! reg_equiv_mem (REGNO (tmp
))
7348 || num_not_at_initial_offset
7349 || GET_CODE (oldequiv
) == SUBREG
)
7350 real_oldequiv
= rl
->in
;
7352 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7356 if (GET_CODE (tmp
) == SUBREG
)
7357 tmp
= SUBREG_REG (tmp
);
7359 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7360 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7361 || reg_equiv_constant (REGNO (tmp
)) != 0))
7363 if (! reg_equiv_mem (REGNO (tmp
))
7364 || num_not_at_initial_offset
7365 || GET_CODE (old
) == SUBREG
)
7368 real_old
= reg_equiv_mem (REGNO (tmp
));
7371 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7372 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7374 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7376 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7377 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7378 /* We'd have to add more code for quartary reloads. */
7379 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7381 icode
= rl
->secondary_in_icode
;
7383 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7384 || (rl
->in
!= 0 && rl
->out
!= 0))
7386 secondary_reload_info sri
, sri2
;
7387 enum reg_class new_class
, new_t_class
;
7389 sri
.icode
= CODE_FOR_nothing
;
7390 sri
.prev_sri
= NULL
;
7392 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7396 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7397 second_reload_reg
= 0;
7398 else if (new_class
== NO_REGS
)
7400 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7402 (enum insn_code
) sri
.icode
))
7404 icode
= (enum insn_code
) sri
.icode
;
7405 third_reload_reg
= 0;
7410 real_oldequiv
= real_old
;
7413 else if (sri
.icode
!= CODE_FOR_nothing
)
7414 /* We currently lack a way to express this in reloads. */
7418 sri2
.icode
= CODE_FOR_nothing
;
7419 sri2
.prev_sri
= &sri
;
7421 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7424 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7426 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7430 third_reload_reg
= 0;
7431 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7436 real_oldequiv
= real_old
;
7439 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7441 rtx intermediate
= second_reload_reg
;
7443 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7445 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7449 second_reload_reg
= intermediate
;
7450 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7455 real_oldequiv
= real_old
;
7458 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7460 rtx intermediate
= second_reload_reg
;
7462 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7464 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7467 second_reload_reg
= intermediate
;
7468 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7473 real_oldequiv
= real_old
;
7478 /* This could be handled more intelligently too. */
7480 real_oldequiv
= real_old
;
7485 /* If we still need a secondary reload register, check
7486 to see if it is being used as a scratch or intermediate
7487 register and generate code appropriately. If we need
7488 a scratch register, use REAL_OLDEQUIV since the form of
7489 the insn may depend on the actual address if it is
7492 if (second_reload_reg
)
7494 if (icode
!= CODE_FOR_nothing
)
7496 /* We'd have to add extra code to handle this case. */
7497 gcc_assert (!third_reload_reg
);
7499 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7500 second_reload_reg
));
7505 /* See if we need a scratch register to load the
7506 intermediate register (a tertiary reload). */
7507 if (tertiary_icode
!= CODE_FOR_nothing
)
7509 emit_insn ((GEN_FCN (tertiary_icode
)
7510 (second_reload_reg
, real_oldequiv
,
7511 third_reload_reg
)));
7513 else if (third_reload_reg
)
7515 gen_reload (third_reload_reg
, real_oldequiv
,
7518 gen_reload (second_reload_reg
, third_reload_reg
,
7523 gen_reload (second_reload_reg
, real_oldequiv
,
7527 oldequiv
= second_reload_reg
;
7532 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7534 rtx real_oldequiv
= oldequiv
;
7536 if ((REG_P (oldequiv
)
7537 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7538 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7539 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7540 || (GET_CODE (oldequiv
) == SUBREG
7541 && REG_P (SUBREG_REG (oldequiv
))
7542 && (REGNO (SUBREG_REG (oldequiv
))
7543 >= FIRST_PSEUDO_REGISTER
)
7544 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7545 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7546 || (CONSTANT_P (oldequiv
)
7547 && (targetm
.preferred_reload_class (oldequiv
,
7548 REGNO_REG_CLASS (REGNO (reloadreg
)))
7550 real_oldequiv
= rl
->in
;
7551 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7555 if (cfun
->can_throw_non_call_exceptions
)
7556 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7558 /* End this sequence. */
7559 *where
= get_insns ();
7562 /* Update reload_override_in so that delete_address_reloads_1
7563 can see the actual register usage. */
7565 reload_override_in
[j
] = oldequiv
;
7568 /* Generate insns to for the output reload RL, which is for the insn described
7569 by CHAIN and has the number J. */
7571 emit_output_reload_insns (class insn_chain
*chain
, struct reload
*rl
,
7575 rtx_insn
*insn
= chain
->insn
;
7582 if (rl
->when_needed
== RELOAD_OTHER
)
7585 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7587 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7588 mode
= GET_MODE (rl_reg_rtx
);
7590 reloadreg
= rl_reg_rtx
;
7592 /* If we need two reload regs, set RELOADREG to the intermediate
7593 one, since it will be stored into OLD. We might need a secondary
7594 register only for an input reload, so check again here. */
7596 if (rl
->secondary_out_reload
>= 0)
7599 int secondary_reload
= rl
->secondary_out_reload
;
7600 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7602 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7603 && reg_equiv_mem (REGNO (old
)) != 0)
7604 real_old
= reg_equiv_mem (REGNO (old
));
7606 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7608 rtx second_reloadreg
= reloadreg
;
7609 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7611 /* See if RELOADREG is to be used as a scratch register
7612 or as an intermediate register. */
7613 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7615 /* We'd have to add extra code to handle this case. */
7616 gcc_assert (tertiary_reload
< 0);
7618 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7619 (real_old
, second_reloadreg
, reloadreg
)));
7624 /* See if we need both a scratch and intermediate reload
7627 enum insn_code tertiary_icode
7628 = rld
[secondary_reload
].secondary_out_icode
;
7630 /* We'd have to add more code for quartary reloads. */
7631 gcc_assert (tertiary_reload
< 0
7632 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7634 if (GET_MODE (reloadreg
) != mode
)
7635 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7637 if (tertiary_icode
!= CODE_FOR_nothing
)
7639 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7641 /* Copy primary reload reg to secondary reload reg.
7642 (Note that these have been swapped above, then
7643 secondary reload reg to OLD using our insn.) */
7645 /* If REAL_OLD is a paradoxical SUBREG, remove it
7646 and try to put the opposite SUBREG on
7648 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7650 gen_reload (reloadreg
, second_reloadreg
,
7651 rl
->opnum
, rl
->when_needed
);
7652 emit_insn ((GEN_FCN (tertiary_icode
)
7653 (real_old
, reloadreg
, third_reloadreg
)));
7659 /* Copy between the reload regs here and then to
7662 gen_reload (reloadreg
, second_reloadreg
,
7663 rl
->opnum
, rl
->when_needed
);
7664 if (tertiary_reload
>= 0)
7666 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7668 gen_reload (third_reloadreg
, reloadreg
,
7669 rl
->opnum
, rl
->when_needed
);
7670 reloadreg
= third_reloadreg
;
7677 /* Output the last reload insn. */
7682 /* Don't output the last reload if OLD is not the dest of
7683 INSN and is in the src and is clobbered by INSN. */
7684 if (! flag_expensive_optimizations
7686 || !(set
= single_set (insn
))
7687 || rtx_equal_p (old
, SET_DEST (set
))
7688 || !reg_mentioned_p (old
, SET_SRC (set
))
7689 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7690 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7691 gen_reload (old
, reloadreg
, rl
->opnum
,
7695 /* Look at all insns we emitted, just to be safe. */
7696 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7699 rtx pat
= PATTERN (p
);
7701 /* If this output reload doesn't come from a spill reg,
7702 clear any memory of reloaded copies of the pseudo reg.
7703 If this output reload comes from a spill reg,
7704 reg_has_output_reload will make this do nothing. */
7705 note_stores (pat
, forget_old_reloads_1
, NULL
);
7707 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7709 rtx set
= single_set (insn
);
7710 if (reload_spill_index
[j
] < 0
7712 && SET_SRC (set
) == rl_reg_rtx
)
7714 int src
= REGNO (SET_SRC (set
));
7716 reload_spill_index
[j
] = src
;
7717 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7718 if (find_regno_note (insn
, REG_DEAD
, src
))
7719 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7721 if (HARD_REGISTER_P (rl_reg_rtx
))
7723 int s
= rl
->secondary_out_reload
;
7724 set
= single_set (p
);
7725 /* If this reload copies only to the secondary reload
7726 register, the secondary reload does the actual
7728 if (s
>= 0 && set
== NULL_RTX
)
7729 /* We can't tell what function the secondary reload
7730 has and where the actual store to the pseudo is
7731 made; leave new_spill_reg_store alone. */
7734 && SET_SRC (set
) == rl_reg_rtx
7735 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7737 /* Usually the next instruction will be the
7738 secondary reload insn; if we can confirm
7739 that it is, setting new_spill_reg_store to
7740 that insn will allow an extra optimization. */
7741 rtx s_reg
= rld
[s
].reg_rtx
;
7742 rtx_insn
*next
= NEXT_INSN (p
);
7743 rld
[s
].out
= rl
->out
;
7744 rld
[s
].out_reg
= rl
->out_reg
;
7745 set
= single_set (next
);
7746 if (set
&& SET_SRC (set
) == s_reg
7747 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7749 SET_HARD_REG_BIT (reg_is_output_reload
,
7751 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7754 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7755 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7760 if (rl
->when_needed
== RELOAD_OTHER
)
7762 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7763 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7766 output_reload_insns
[rl
->opnum
] = get_insns ();
7768 if (cfun
->can_throw_non_call_exceptions
)
7769 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7774 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7775 and has the number J. */
7777 do_input_reload (class insn_chain
*chain
, struct reload
*rl
, int j
)
7779 rtx_insn
*insn
= chain
->insn
;
7780 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7781 ? rl
->in_reg
: rl
->in
);
7782 rtx reg_rtx
= rl
->reg_rtx
;
7788 /* Determine the mode to reload in.
7789 This is very tricky because we have three to choose from.
7790 There is the mode the insn operand wants (rl->inmode).
7791 There is the mode of the reload register RELOADREG.
7792 There is the intrinsic mode of the operand, which we could find
7793 by stripping some SUBREGs.
7794 It turns out that RELOADREG's mode is irrelevant:
7795 we can change that arbitrarily.
7797 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7798 then the reload reg may not support QImode moves, so use SImode.
7799 If foo is in memory due to spilling a pseudo reg, this is safe,
7800 because the QImode value is in the least significant part of a
7801 slot big enough for a SImode. If foo is some other sort of
7802 memory reference, then it is impossible to reload this case,
7803 so previous passes had better make sure this never happens.
7805 Then consider a one-word union which has SImode and one of its
7806 members is a float, being fetched as (SUBREG:SF union:SI).
7807 We must fetch that as SFmode because we could be loading into
7808 a float-only register. In this case OLD's mode is correct.
7810 Consider an immediate integer: it has VOIDmode. Here we need
7811 to get a mode from something else.
7813 In some cases, there is a fourth mode, the operand's
7814 containing mode. If the insn specifies a containing mode for
7815 this operand, it overrides all others.
7817 I am not sure whether the algorithm here is always right,
7818 but it does the right things in those cases. */
7820 mode
= GET_MODE (old
);
7821 if (mode
== VOIDmode
)
7824 /* We cannot use gen_lowpart_common since it can do the wrong thing
7825 when REG_RTX has a multi-word mode. Note that REG_RTX must
7826 always be a REG here. */
7827 if (GET_MODE (reg_rtx
) != mode
)
7828 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7830 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7833 /* AUTO_INC reloads need to be handled even if inherited. We got an
7834 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7835 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7836 && ! rtx_equal_p (reg_rtx
, old
)
7838 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7840 /* When inheriting a wider reload, we have a MEM in rl->in,
7841 e.g. inheriting a SImode output reload for
7842 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7843 if (optimize
&& reload_inherited
[j
] && rl
->in
7845 && MEM_P (rl
->in_reg
)
7846 && reload_spill_index
[j
] >= 0
7847 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7848 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7850 /* If we are reloading a register that was recently stored in with an
7851 output-reload, see if we can prove there was
7852 actually no need to store the old value in it. */
7855 && (reload_inherited
[j
] || reload_override_in
[j
])
7858 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7860 /* There doesn't seem to be any reason to restrict this to pseudos
7861 and doing so loses in the case where we are copying from a
7862 register of the wrong class. */
7863 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7865 /* The insn might have already some references to stackslots
7866 replaced by MEMs, while reload_out_reg still names the
7868 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7869 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7870 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7873 /* Do output reloading for reload RL, which is for the insn described by
7874 CHAIN and has the number J.
7875 ??? At some point we need to support handling output reloads of
7876 JUMP_INSNs or insns that set cc0. */
7878 do_output_reload (class insn_chain
*chain
, struct reload
*rl
, int j
)
7881 rtx_insn
*insn
= chain
->insn
;
7882 /* If this is an output reload that stores something that is
7883 not loaded in this same reload, see if we can eliminate a previous
7885 rtx pseudo
= rl
->out_reg
;
7886 rtx reg_rtx
= rl
->reg_rtx
;
7888 if (rl
->out
&& reg_rtx
)
7892 /* Determine the mode to reload in.
7893 See comments above (for input reloading). */
7894 mode
= GET_MODE (rl
->out
);
7895 if (mode
== VOIDmode
)
7897 /* VOIDmode should never happen for an output. */
7898 if (asm_noperands (PATTERN (insn
)) < 0)
7899 /* It's the compiler's fault. */
7900 fatal_insn ("VOIDmode on an output", insn
);
7901 error_for_asm (insn
, "output operand is constant in %<asm%>");
7902 /* Prevent crash--use something we know is valid. */
7904 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7906 if (GET_MODE (reg_rtx
) != mode
)
7907 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7909 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7914 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7915 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7916 && reg_last_reload_reg
[REGNO (pseudo
)])
7918 int pseudo_no
= REGNO (pseudo
);
7919 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7921 /* We don't need to test full validity of last_regno for
7922 inherit here; we only want to know if the store actually
7923 matches the pseudo. */
7924 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7925 && reg_reloaded_contents
[last_regno
] == pseudo_no
7926 && spill_reg_store
[last_regno
]
7927 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7928 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7934 || rtx_equal_p (old
, reg_rtx
))
7937 /* An output operand that dies right away does need a reload,
7938 but need not be copied from it. Show the new location in the
7940 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7941 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7943 XEXP (note
, 0) = reg_rtx
;
7946 /* Likewise for a SUBREG of an operand that dies. */
7947 else if (GET_CODE (old
) == SUBREG
7948 && REG_P (SUBREG_REG (old
))
7949 && (note
= find_reg_note (insn
, REG_UNUSED
,
7950 SUBREG_REG (old
))) != 0)
7952 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7955 else if (GET_CODE (old
) == SCRATCH
)
7956 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7957 but we don't want to make an output reload. */
7960 /* If is a JUMP_INSN, we can't support output reloads yet. */
7961 gcc_assert (NONJUMP_INSN_P (insn
));
7963 emit_output_reload_insns (chain
, rld
+ j
, j
);
7966 /* A reload copies values of MODE from register SRC to register DEST.
7967 Return true if it can be treated for inheritance purposes like a
7968 group of reloads, each one reloading a single hard register. The
7969 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7970 occupy the same number of hard registers. */
7973 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
7974 int src ATTRIBUTE_UNUSED
,
7975 machine_mode mode ATTRIBUTE_UNUSED
)
7977 return (REG_CAN_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
7978 && REG_CAN_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
7981 /* Output insns to reload values in and out of the chosen reload regs. */
7984 emit_reload_insns (class insn_chain
*chain
)
7986 rtx_insn
*insn
= chain
->insn
;
7990 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7992 for (j
= 0; j
< reload_n_operands
; j
++)
7993 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7994 = inpaddr_address_reload_insns
[j
]
7995 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7996 = outaddr_address_reload_insns
[j
]
7997 = other_output_reload_insns
[j
] = 0;
7998 other_input_address_reload_insns
= 0;
7999 other_input_reload_insns
= 0;
8000 operand_reload_insns
= 0;
8001 other_operand_reload_insns
= 0;
8003 /* Dump reloads into the dump file. */
8006 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8007 debug_reload_to_stream (dump_file
);
8010 for (j
= 0; j
< n_reloads
; j
++)
8011 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8015 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8016 new_spill_reg_store
[i
] = 0;
8019 /* Now output the instructions to copy the data into and out of the
8020 reload registers. Do these in the order that the reloads were reported,
8021 since reloads of base and index registers precede reloads of operands
8022 and the operands may need the base and index registers reloaded. */
8024 for (j
= 0; j
< n_reloads
; j
++)
8026 do_input_reload (chain
, rld
+ j
, j
);
8027 do_output_reload (chain
, rld
+ j
, j
);
8030 /* Now write all the insns we made for reloads in the order expected by
8031 the allocation functions. Prior to the insn being reloaded, we write
8032 the following reloads:
8034 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8036 RELOAD_OTHER reloads.
8038 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8039 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8040 RELOAD_FOR_INPUT reload for the operand.
8042 RELOAD_FOR_OPADDR_ADDRS reloads.
8044 RELOAD_FOR_OPERAND_ADDRESS reloads.
8046 After the insn being reloaded, we write the following:
8048 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8049 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8050 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8051 reloads for the operand. The RELOAD_OTHER output reloads are
8052 output in descending order by reload number. */
8054 emit_insn_before (other_input_address_reload_insns
, insn
);
8055 emit_insn_before (other_input_reload_insns
, insn
);
8057 for (j
= 0; j
< reload_n_operands
; j
++)
8059 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8060 emit_insn_before (input_address_reload_insns
[j
], insn
);
8061 emit_insn_before (input_reload_insns
[j
], insn
);
8064 emit_insn_before (other_operand_reload_insns
, insn
);
8065 emit_insn_before (operand_reload_insns
, insn
);
8067 for (j
= 0; j
< reload_n_operands
; j
++)
8069 rtx_insn
*x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8070 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8071 x
= emit_insn_after (output_reload_insns
[j
], x
);
8072 emit_insn_after (other_output_reload_insns
[j
], x
);
8075 /* For all the spill regs newly reloaded in this instruction,
8076 record what they were reloaded from, so subsequent instructions
8077 can inherit the reloads.
8079 Update spill_reg_store for the reloads of this insn.
8080 Copy the elements that were updated in the loop above. */
8082 for (j
= 0; j
< n_reloads
; j
++)
8084 int r
= reload_order
[j
];
8085 int i
= reload_spill_index
[r
];
8087 /* If this is a non-inherited input reload from a pseudo, we must
8088 clear any memory of a previous store to the same pseudo. Only do
8089 something if there will not be an output reload for the pseudo
8091 if (rld
[r
].in_reg
!= 0
8092 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8094 rtx reg
= rld
[r
].in_reg
;
8096 if (GET_CODE (reg
) == SUBREG
)
8097 reg
= SUBREG_REG (reg
);
8100 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8101 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8103 int nregno
= REGNO (reg
);
8105 if (reg_last_reload_reg
[nregno
])
8107 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8109 if (reg_reloaded_contents
[last_regno
] == nregno
)
8110 spill_reg_store
[last_regno
] = 0;
8115 /* I is nonneg if this reload used a register.
8116 If rld[r].reg_rtx is 0, this is an optional reload
8117 that we opted to ignore. */
8119 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8121 int nr
= hard_regno_nregs (i
, GET_MODE (rld
[r
].reg_rtx
));
8124 /* For a multi register reload, we need to check if all or part
8125 of the value lives to the end. */
8126 for (k
= 0; k
< nr
; k
++)
8127 if (reload_reg_reaches_end_p (i
+ k
, r
))
8128 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8130 /* Maybe the spill reg contains a copy of reload_out. */
8132 && (REG_P (rld
[r
].out
)
8134 ? REG_P (rld
[r
].out_reg
)
8135 /* The reload value is an auto-modification of
8136 some kind. For PRE_INC, POST_INC, PRE_DEC
8137 and POST_DEC, we record an equivalence
8138 between the reload register and the operand
8139 on the optimistic assumption that we can make
8140 the equivalence hold. reload_as_needed must
8141 then either make it hold or invalidate the
8144 PRE_MODIFY and POST_MODIFY addresses are reloaded
8145 somewhat differently, and allowing them here leads
8147 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8148 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8152 reg
= reload_reg_rtx_for_output
[r
];
8153 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8155 machine_mode mode
= GET_MODE (reg
);
8156 int regno
= REGNO (reg
);
8157 int nregs
= REG_NREGS (reg
);
8158 rtx out
= (REG_P (rld
[r
].out
)
8162 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8163 int out_regno
= REGNO (out
);
8164 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8165 : hard_regno_nregs (out_regno
, mode
));
8168 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8169 spill_reg_stored_to
[regno
] = out
;
8170 reg_last_reload_reg
[out_regno
] = reg
;
8172 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8173 && nregs
== out_nregs
8174 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8176 /* If OUT_REGNO is a hard register, it may occupy more than
8177 one register. If it does, say what is in the
8178 rest of the registers assuming that both registers
8179 agree on how many words the object takes. If not,
8180 invalidate the subsequent registers. */
8182 if (HARD_REGISTER_NUM_P (out_regno
))
8183 for (k
= 1; k
< out_nregs
; k
++)
8184 reg_last_reload_reg
[out_regno
+ k
]
8185 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8187 /* Now do the inverse operation. */
8188 for (k
= 0; k
< nregs
; k
++)
8190 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8191 reg_reloaded_contents
[regno
+ k
]
8192 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8195 reg_reloaded_insn
[regno
+ k
] = insn
;
8196 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8197 if (targetm
.hard_regno_call_part_clobbered (NULL
,
8200 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8203 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8208 /* Maybe the spill reg contains a copy of reload_in. Only do
8209 something if there will not be an output reload for
8210 the register being reloaded. */
8211 else if (rld
[r
].out_reg
== 0
8213 && ((REG_P (rld
[r
].in
)
8214 && !HARD_REGISTER_P (rld
[r
].in
)
8215 && !REGNO_REG_SET_P (®_has_output_reload
,
8217 || (REG_P (rld
[r
].in_reg
)
8218 && !REGNO_REG_SET_P (®_has_output_reload
,
8219 REGNO (rld
[r
].in_reg
))))
8220 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8224 reg
= reload_reg_rtx_for_input
[r
];
8225 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8235 mode
= GET_MODE (reg
);
8236 regno
= REGNO (reg
);
8237 nregs
= REG_NREGS (reg
);
8238 if (REG_P (rld
[r
].in
)
8239 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8241 else if (REG_P (rld
[r
].in_reg
))
8244 in
= XEXP (rld
[r
].in_reg
, 0);
8245 in_regno
= REGNO (in
);
8247 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8248 : hard_regno_nregs (in_regno
, mode
));
8250 reg_last_reload_reg
[in_regno
] = reg
;
8252 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8253 && nregs
== in_nregs
8254 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8256 if (HARD_REGISTER_NUM_P (in_regno
))
8257 for (k
= 1; k
< in_nregs
; k
++)
8258 reg_last_reload_reg
[in_regno
+ k
]
8259 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8261 /* Unless we inherited this reload, show we haven't
8262 recently done a store.
8263 Previous stores of inherited auto_inc expressions
8264 also have to be discarded. */
8265 if (! reload_inherited
[r
]
8266 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8267 spill_reg_store
[regno
] = 0;
8269 for (k
= 0; k
< nregs
; k
++)
8271 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8272 reg_reloaded_contents
[regno
+ k
]
8273 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8276 reg_reloaded_insn
[regno
+ k
] = insn
;
8277 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8278 if (targetm
.hard_regno_call_part_clobbered (NULL
,
8281 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8284 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8291 /* The following if-statement was #if 0'd in 1.34 (or before...).
8292 It's reenabled in 1.35 because supposedly nothing else
8293 deals with this problem. */
8295 /* If a register gets output-reloaded from a non-spill register,
8296 that invalidates any previous reloaded copy of it.
8297 But forget_old_reloads_1 won't get to see it, because
8298 it thinks only about the original insn. So invalidate it here.
8299 Also do the same thing for RELOAD_OTHER constraints where the
8300 output is discarded. */
8302 && ((rld
[r
].out
!= 0
8303 && (REG_P (rld
[r
].out
)
8304 || (MEM_P (rld
[r
].out
)
8305 && REG_P (rld
[r
].out_reg
))))
8306 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8307 && REG_P (rld
[r
].out_reg
))))
8309 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8310 ? rld
[r
].out
: rld
[r
].out_reg
);
8311 int out_regno
= REGNO (out
);
8312 machine_mode mode
= GET_MODE (out
);
8314 /* REG_RTX is now set or clobbered by the main instruction.
8315 As the comment above explains, forget_old_reloads_1 only
8316 sees the original instruction, and there is no guarantee
8317 that the original instruction also clobbered REG_RTX.
8318 For example, if find_reloads sees that the input side of
8319 a matched operand pair dies in this instruction, it may
8320 use the input register as the reload register.
8322 Calling forget_old_reloads_1 is a waste of effort if
8323 REG_RTX is also the output register.
8325 If we know that REG_RTX holds the value of a pseudo
8326 register, the code after the call will record that fact. */
8327 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8328 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8330 if (!HARD_REGISTER_NUM_P (out_regno
))
8333 rtx_insn
*store_insn
= NULL
;
8335 reg_last_reload_reg
[out_regno
] = 0;
8337 /* If we can find a hard register that is stored, record
8338 the storing insn so that we may delete this insn with
8339 delete_output_reload. */
8340 src_reg
= reload_reg_rtx_for_output
[r
];
8344 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8345 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8351 /* If this is an optional reload, try to find the
8352 source reg from an input reload. */
8353 rtx set
= single_set (insn
);
8354 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8358 src_reg
= SET_SRC (set
);
8360 for (k
= 0; k
< n_reloads
; k
++)
8362 if (rld
[k
].in
== src_reg
)
8364 src_reg
= reload_reg_rtx_for_input
[k
];
8370 if (src_reg
&& REG_P (src_reg
)
8371 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8373 int src_regno
, src_nregs
, k
;
8376 gcc_assert (GET_MODE (src_reg
) == mode
);
8377 src_regno
= REGNO (src_reg
);
8378 src_nregs
= hard_regno_nregs (src_regno
, mode
);
8379 /* The place where to find a death note varies with
8380 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8381 necessarily checked exactly in the code that moves
8382 notes, so just check both locations. */
8383 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8384 if (! note
&& store_insn
)
8385 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8386 for (k
= 0; k
< src_nregs
; k
++)
8388 spill_reg_store
[src_regno
+ k
] = store_insn
;
8389 spill_reg_stored_to
[src_regno
+ k
] = out
;
8390 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8391 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8392 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8393 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8394 if (targetm
.hard_regno_call_part_clobbered
8395 (NULL
, src_regno
+ k
, mode
))
8396 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8399 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8401 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8403 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8405 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8407 reg_last_reload_reg
[out_regno
] = src_reg
;
8408 /* We have to set reg_has_output_reload here, or else
8409 forget_old_reloads_1 will clear reg_last_reload_reg
8411 SET_REGNO_REG_SET (®_has_output_reload
,
8417 int k
, out_nregs
= hard_regno_nregs (out_regno
, mode
);
8419 for (k
= 0; k
< out_nregs
; k
++)
8420 reg_last_reload_reg
[out_regno
+ k
] = 0;
8424 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8427 /* Go through the motions to emit INSN and test if it is strictly valid.
8428 Return the emitted insn if valid, else return NULL. */
8431 emit_insn_if_valid_for_reload (rtx pat
)
8433 rtx_insn
*last
= get_last_insn ();
8436 rtx_insn
*insn
= emit_insn (pat
);
8437 code
= recog_memoized (insn
);
8441 extract_insn (insn
);
8442 /* We want constrain operands to treat this insn strictly in its
8443 validity determination, i.e., the way it would after reload has
8445 if (constrain_operands (1, get_enabled_alternatives (insn
)))
8449 delete_insns_since (last
);
8453 /* Emit code to perform a reload from IN (which may be a reload register) to
8454 OUT (which may also be a reload register). IN or OUT is from operand
8455 OPNUM with reload type TYPE.
8457 Returns first insn emitted. */
8460 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8462 rtx_insn
*last
= get_last_insn ();
8466 /* If IN is a paradoxical SUBREG, remove it and try to put the
8467 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8468 if (!strip_paradoxical_subreg (&in
, &out
))
8469 strip_paradoxical_subreg (&out
, &in
);
8471 /* How to do this reload can get quite tricky. Normally, we are being
8472 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8473 register that didn't get a hard register. In that case we can just
8474 call emit_move_insn.
8476 We can also be asked to reload a PLUS that adds a register or a MEM to
8477 another register, constant or MEM. This can occur during frame pointer
8478 elimination and while reloading addresses. This case is handled by
8479 trying to emit a single insn to perform the add. If it is not valid,
8480 we use a two insn sequence.
8482 Or we can be asked to reload an unary operand that was a fragment of
8483 an addressing mode, into a register. If it isn't recognized as-is,
8484 we try making the unop operand and the reload-register the same:
8485 (set reg:X (unop:X expr:Y))
8486 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8488 Finally, we could be called to handle an 'o' constraint by putting
8489 an address into a register. In that case, we first try to do this
8490 with a named pattern of "reload_load_address". If no such pattern
8491 exists, we just emit a SET insn and hope for the best (it will normally
8492 be valid on machines that use 'o').
8494 This entire process is made complex because reload will never
8495 process the insns we generate here and so we must ensure that
8496 they will fit their constraints and also by the fact that parts of
8497 IN might be being reloaded separately and replaced with spill registers.
8498 Because of this, we are, in some sense, just guessing the right approach
8499 here. The one listed above seems to work.
8501 ??? At some point, this whole thing needs to be rethought. */
8503 if (GET_CODE (in
) == PLUS
8504 && (REG_P (XEXP (in
, 0))
8505 || GET_CODE (XEXP (in
, 0)) == SUBREG
8506 || MEM_P (XEXP (in
, 0)))
8507 && (REG_P (XEXP (in
, 1))
8508 || GET_CODE (XEXP (in
, 1)) == SUBREG
8509 || CONSTANT_P (XEXP (in
, 1))
8510 || MEM_P (XEXP (in
, 1))))
8512 /* We need to compute the sum of a register or a MEM and another
8513 register, constant, or MEM, and put it into the reload
8514 register. The best possible way of doing this is if the machine
8515 has a three-operand ADD insn that accepts the required operands.
8517 The simplest approach is to try to generate such an insn and see if it
8518 is recognized and matches its constraints. If so, it can be used.
8520 It might be better not to actually emit the insn unless it is valid,
8521 but we need to pass the insn as an operand to `recog' and
8522 `extract_insn' and it is simpler to emit and then delete the insn if
8523 not valid than to dummy things up. */
8527 enum insn_code code
;
8529 op0
= find_replacement (&XEXP (in
, 0));
8530 op1
= find_replacement (&XEXP (in
, 1));
8532 /* Since constraint checking is strict, commutativity won't be
8533 checked, so we need to do that here to avoid spurious failure
8534 if the add instruction is two-address and the second operand
8535 of the add is the same as the reload reg, which is frequently
8536 the case. If the insn would be A = B + A, rearrange it so
8537 it will be A = A + B as constrain_operands expects. */
8539 if (REG_P (XEXP (in
, 1))
8540 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8541 tem
= op0
, op0
= op1
, op1
= tem
;
8543 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8544 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8546 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8550 /* If that failed, we must use a conservative two-insn sequence.
8552 Use a move to copy one operand into the reload register. Prefer
8553 to reload a constant, MEM or pseudo since the move patterns can
8554 handle an arbitrary operand. If OP1 is not a constant, MEM or
8555 pseudo and OP1 is not a valid operand for an add instruction, then
8558 After reloading one of the operands into the reload register, add
8559 the reload register to the output register.
8561 If there is another way to do this for a specific machine, a
8562 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8565 code
= optab_handler (add_optab
, GET_MODE (out
));
8567 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8569 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8570 || (code
!= CODE_FOR_nothing
8571 && !insn_operand_matches (code
, 2, op1
)))
8572 tem
= op0
, op0
= op1
, op1
= tem
;
8574 gen_reload (out
, op0
, opnum
, type
);
8576 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8577 This fixes a problem on the 32K where the stack pointer cannot
8578 be used as an operand of an add insn. */
8580 if (rtx_equal_p (op0
, op1
))
8583 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8586 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8587 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8591 /* If that failed, copy the address register to the reload register.
8592 Then add the constant to the reload register. */
8594 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8595 gen_reload (out
, op1
, opnum
, type
);
8596 insn
= emit_insn (gen_add2_insn (out
, op0
));
8597 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8600 /* If we need a memory location to do the move, do it that way. */
8601 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8602 (REG_P (tem1
) && REG_P (tem2
)))
8603 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8604 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8605 && targetm
.secondary_memory_needed (GET_MODE (out
),
8606 REGNO_REG_CLASS (REGNO (tem1
)),
8607 REGNO_REG_CLASS (REGNO (tem2
))))
8609 /* Get the memory to use and rewrite both registers to its mode. */
8610 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8612 if (GET_MODE (loc
) != GET_MODE (out
))
8613 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8615 if (GET_MODE (loc
) != GET_MODE (in
))
8616 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8618 gen_reload (loc
, in
, opnum
, type
);
8619 gen_reload (out
, loc
, opnum
, type
);
8621 else if (REG_P (out
) && UNARY_P (in
))
8627 op1
= find_replacement (&XEXP (in
, 0));
8628 if (op1
!= XEXP (in
, 0))
8629 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8631 /* First, try a plain SET. */
8632 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8636 /* If that failed, move the inner operand to the reload
8637 register, and try the same unop with the inner expression
8638 replaced with the reload register. */
8640 if (GET_MODE (op1
) != GET_MODE (out
))
8641 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8645 gen_reload (out_moded
, op1
, opnum
, type
);
8647 rtx temp
= gen_rtx_SET (out
, gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8649 rtx_insn
*insn
= emit_insn_if_valid_for_reload (temp
);
8652 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8656 fatal_insn ("failure trying to reload:", set
);
8658 /* If IN is a simple operand, use gen_move_insn. */
8659 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8661 tem
= emit_insn (gen_move_insn (out
, in
));
8662 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8663 mark_jump_label (in
, tem
, 0);
8666 else if (targetm
.have_reload_load_address ())
8667 emit_insn (targetm
.gen_reload_load_address (out
, in
));
8669 /* Otherwise, just write (set OUT IN) and hope for the best. */
8671 emit_insn (gen_rtx_SET (out
, in
));
8673 /* Return the first insn emitted.
8674 We cannot just return get_last_insn, because there may have
8675 been multiple instructions emitted. Also note that gen_move_insn may
8676 emit more than one insn itself, so we cannot assume that there is one
8677 insn emitted per emit_insn_before call. */
8679 return last
? NEXT_INSN (last
) : get_insns ();
8682 /* Delete a previously made output-reload whose result we now believe
8683 is not needed. First we double-check.
8685 INSN is the insn now being processed.
8686 LAST_RELOAD_REG is the hard register number for which we want to delete
8687 the last output reload.
8688 J is the reload-number that originally used REG. The caller has made
8689 certain that reload J doesn't use REG any longer for input.
8690 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8693 delete_output_reload (rtx_insn
*insn
, int j
, int last_reload_reg
,
8696 rtx_insn
*output_reload_insn
= spill_reg_store
[last_reload_reg
];
8697 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8700 int n_inherited
= 0;
8705 /* It is possible that this reload has been only used to set another reload
8706 we eliminated earlier and thus deleted this instruction too. */
8707 if (output_reload_insn
->deleted ())
8710 /* Get the raw pseudo-register referred to. */
8712 while (GET_CODE (reg
) == SUBREG
)
8713 reg
= SUBREG_REG (reg
);
8714 substed
= reg_equiv_memory_loc (REGNO (reg
));
8716 /* This is unsafe if the operand occurs more often in the current
8717 insn than it is inherited. */
8718 for (k
= n_reloads
- 1; k
>= 0; k
--)
8720 rtx reg2
= rld
[k
].in
;
8723 if (MEM_P (reg2
) || reload_override_in
[k
])
8724 reg2
= rld
[k
].in_reg
;
8726 if (AUTO_INC_DEC
&& rld
[k
].out
&& ! rld
[k
].out_reg
)
8727 reg2
= XEXP (rld
[k
].in_reg
, 0);
8729 while (GET_CODE (reg2
) == SUBREG
)
8730 reg2
= SUBREG_REG (reg2
);
8731 if (rtx_equal_p (reg2
, reg
))
8733 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8739 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8740 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8741 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8744 n_occurrences
+= count_occurrences (PATTERN (insn
),
8745 eliminate_regs (substed
, VOIDmode
,
8747 for (rtx i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8749 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8750 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8752 if (n_occurrences
> n_inherited
)
8755 regno
= REGNO (reg
);
8756 nregs
= REG_NREGS (reg
);
8758 /* If the pseudo-reg we are reloading is no longer referenced
8759 anywhere between the store into it and here,
8760 and we're within the same basic block, then the value can only
8761 pass through the reload reg and end up here.
8762 Otherwise, give up--return. */
8763 for (rtx_insn
*i1
= NEXT_INSN (output_reload_insn
);
8764 i1
!= insn
; i1
= NEXT_INSN (i1
))
8766 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8768 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8769 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8771 /* If this is USE in front of INSN, we only have to check that
8772 there are no more references than accounted for by inheritance. */
8773 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8775 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8776 i1
= NEXT_INSN (i1
);
8778 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8784 /* We will be deleting the insn. Remove the spill reg information. */
8785 for (k
= hard_regno_nregs (last_reload_reg
, GET_MODE (reg
)); k
-- > 0; )
8787 spill_reg_store
[last_reload_reg
+ k
] = 0;
8788 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8791 /* The caller has already checked that REG dies or is set in INSN.
8792 It has also checked that we are optimizing, and thus some
8793 inaccuracies in the debugging information are acceptable.
8794 So we could just delete output_reload_insn. But in some cases
8795 we can improve the debugging information without sacrificing
8796 optimization - maybe even improving the code: See if the pseudo
8797 reg has been completely replaced with reload regs. If so, delete
8798 the store insn and forget we had a stack slot for the pseudo. */
8799 if (rld
[j
].out
!= rld
[j
].in
8800 && REG_N_DEATHS (REGNO (reg
)) == 1
8801 && REG_N_SETS (REGNO (reg
)) == 1
8802 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8803 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8807 /* We know that it was used only between here and the beginning of
8808 the current basic block. (We also know that the last use before
8809 INSN was the output reload we are thinking of deleting, but never
8810 mind that.) Search that range; see if any ref remains. */
8811 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8813 rtx set
= single_set (i2
);
8815 /* Uses which just store in the pseudo don't count,
8816 since if they are the only uses, they are dead. */
8817 if (set
!= 0 && SET_DEST (set
) == reg
)
8819 if (LABEL_P (i2
) || JUMP_P (i2
))
8821 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8822 && reg_mentioned_p (reg
, PATTERN (i2
)))
8824 /* Some other ref remains; just delete the output reload we
8826 delete_address_reloads (output_reload_insn
, insn
);
8827 delete_insn (output_reload_insn
);
8832 /* Delete the now-dead stores into this pseudo. Note that this
8833 loop also takes care of deleting output_reload_insn. */
8834 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8836 rtx set
= single_set (i2
);
8838 if (set
!= 0 && SET_DEST (set
) == reg
)
8840 delete_address_reloads (i2
, insn
);
8843 if (LABEL_P (i2
) || JUMP_P (i2
))
8847 /* For the debugging info, say the pseudo lives in this reload reg. */
8848 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8849 if (ira_conflicts_p
)
8850 /* Inform IRA about the change. */
8851 ira_mark_allocation_change (REGNO (reg
));
8852 alter_reg (REGNO (reg
), -1, false);
8856 delete_address_reloads (output_reload_insn
, insn
);
8857 delete_insn (output_reload_insn
);
8861 /* We are going to delete DEAD_INSN. Recursively delete loads of
8862 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8863 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8865 delete_address_reloads (rtx_insn
*dead_insn
, rtx_insn
*current_insn
)
8867 rtx set
= single_set (dead_insn
);
8869 rtx_insn
*prev
, *next
;
8872 rtx dst
= SET_DEST (set
);
8874 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8876 /* If we deleted the store from a reloaded post_{in,de}c expression,
8877 we can delete the matching adds. */
8878 prev
= PREV_INSN (dead_insn
);
8879 next
= NEXT_INSN (dead_insn
);
8880 if (! prev
|| ! next
)
8882 set
= single_set (next
);
8883 set2
= single_set (prev
);
8885 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8886 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8887 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8889 dst
= SET_DEST (set
);
8890 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8891 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8892 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8893 || (INTVAL (XEXP (SET_SRC (set
), 1))
8894 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8896 delete_related_insns (prev
);
8897 delete_related_insns (next
);
8900 /* Subfunction of delete_address_reloads: process registers found in X. */
8902 delete_address_reloads_1 (rtx_insn
*dead_insn
, rtx x
, rtx_insn
*current_insn
)
8904 rtx_insn
*prev
, *i2
;
8907 enum rtx_code code
= GET_CODE (x
);
8911 const char *fmt
= GET_RTX_FORMAT (code
);
8912 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8915 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8916 else if (fmt
[i
] == 'E')
8918 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8919 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8926 if (spill_reg_order
[REGNO (x
)] < 0)
8929 /* Scan backwards for the insn that sets x. This might be a way back due
8931 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8933 code
= GET_CODE (prev
);
8934 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8938 if (reg_set_p (x
, PATTERN (prev
)))
8940 if (reg_referenced_p (x
, PATTERN (prev
)))
8943 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8945 /* Check that PREV only sets the reload register. */
8946 set
= single_set (prev
);
8949 dst
= SET_DEST (set
);
8951 || ! rtx_equal_p (dst
, x
))
8953 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8955 /* Check if DST was used in a later insn -
8956 it might have been inherited. */
8957 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8963 if (reg_referenced_p (dst
, PATTERN (i2
)))
8965 /* If there is a reference to the register in the current insn,
8966 it might be loaded in a non-inherited reload. If no other
8967 reload uses it, that means the register is set before
8969 if (i2
== current_insn
)
8971 for (j
= n_reloads
- 1; j
>= 0; j
--)
8972 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8973 || reload_override_in
[j
] == dst
)
8975 for (j
= n_reloads
- 1; j
>= 0; j
--)
8976 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8985 /* If DST is still live at CURRENT_INSN, check if it is used for
8986 any reload. Note that even if CURRENT_INSN sets DST, we still
8987 have to check the reloads. */
8988 if (i2
== current_insn
)
8990 for (j
= n_reloads
- 1; j
>= 0; j
--)
8991 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8992 || reload_override_in
[j
] == dst
)
8994 /* ??? We can't finish the loop here, because dst might be
8995 allocated to a pseudo in this block if no reload in this
8996 block needs any of the classes containing DST - see
8997 spill_hard_reg. There is no easy way to tell this, so we
8998 have to scan till the end of the basic block. */
9000 if (reg_set_p (dst
, PATTERN (i2
)))
9004 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9005 reg_reloaded_contents
[REGNO (dst
)] = -1;
9009 /* Output reload-insns to reload VALUE into RELOADREG.
9010 VALUE is an autoincrement or autodecrement RTX whose operand
9011 is a register or memory location;
9012 so reloading involves incrementing that location.
9013 IN is either identical to VALUE, or some cheaper place to reload from.
9015 INC_AMOUNT is the number to increment or decrement by (always positive).
9016 This cannot be deduced from VALUE. */
9019 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, poly_int64 inc_amount
)
9021 /* REG or MEM to be copied and incremented. */
9022 rtx incloc
= find_replacement (&XEXP (value
, 0));
9023 /* Nonzero if increment after copying. */
9024 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9025 || GET_CODE (value
) == POST_MODIFY
);
9030 rtx real_in
= in
== value
? incloc
: in
;
9032 /* No hard register is equivalent to this register after
9033 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9034 we could inc/dec that register as well (maybe even using it for
9035 the source), but I'm not sure it's worth worrying about. */
9037 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9039 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9041 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9042 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9046 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9047 inc_amount
= -inc_amount
;
9049 inc
= gen_int_mode (inc_amount
, Pmode
);
9052 /* If this is post-increment, first copy the location to the reload reg. */
9053 if (post
&& real_in
!= reloadreg
)
9054 emit_insn (gen_move_insn (reloadreg
, real_in
));
9058 /* See if we can directly increment INCLOC. Use a method similar to
9059 that in gen_reload. */
9061 last
= get_last_insn ();
9062 add_insn
= emit_insn (gen_rtx_SET (incloc
,
9063 gen_rtx_PLUS (GET_MODE (incloc
),
9066 code
= recog_memoized (add_insn
);
9069 extract_insn (add_insn
);
9070 if (constrain_operands (1, get_enabled_alternatives (add_insn
)))
9072 /* If this is a pre-increment and we have incremented the value
9073 where it lives, copy the incremented value to RELOADREG to
9074 be used as an address. */
9077 emit_insn (gen_move_insn (reloadreg
, incloc
));
9081 delete_insns_since (last
);
9084 /* If couldn't do the increment directly, must increment in RELOADREG.
9085 The way we do this depends on whether this is pre- or post-increment.
9086 For pre-increment, copy INCLOC to the reload register, increment it
9087 there, then save back. */
9091 if (in
!= reloadreg
)
9092 emit_insn (gen_move_insn (reloadreg
, real_in
));
9093 emit_insn (gen_add2_insn (reloadreg
, inc
));
9094 emit_insn (gen_move_insn (incloc
, reloadreg
));
9099 Because this might be a jump insn or a compare, and because RELOADREG
9100 may not be available after the insn in an input reload, we must do
9101 the incrementation before the insn being reloaded for.
9103 We have already copied IN to RELOADREG. Increment the copy in
9104 RELOADREG, save that back, then decrement RELOADREG so it has
9105 the original value. */
9107 emit_insn (gen_add2_insn (reloadreg
, inc
));
9108 emit_insn (gen_move_insn (incloc
, reloadreg
));
9109 if (CONST_INT_P (inc
))
9110 emit_insn (gen_add2_insn (reloadreg
,
9111 gen_int_mode (-INTVAL (inc
),
9112 GET_MODE (reloadreg
))));
9114 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9119 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
9121 enum rtx_code code
= GET_CODE (x
);
9125 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9127 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9131 /* Scan all the operand sub-expressions. */
9132 fmt
= GET_RTX_FORMAT (code
);
9133 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9136 add_auto_inc_notes (insn
, XEXP (x
, i
));
9137 else if (fmt
[i
] == 'E')
9138 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9139 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));