1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
36 #include "rtl-error.h"
38 #include "addresses.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 struct target_reload default_target_reload
;
82 struct target_reload
*this_target_reload
= &default_target_reload
;
85 #define spill_indirect_levels \
86 (this_target_reload->x_spill_indirect_levels)
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx
*reg_last_reload_reg
;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static regset_head reg_has_output_reload
;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload
;
100 /* Widest width in which each pseudo reg is referred to (via subreg). */
101 static unsigned int *reg_max_ref_width
;
103 /* Vector to remember old contents of reg_renumber before spilling. */
104 static short *reg_old_renumber
;
106 /* During reload_as_needed, element N contains the last pseudo regno reloaded
107 into hard register N. If that pseudo reg occupied more than one register,
108 reg_reloaded_contents points to that pseudo for each spill register in
109 use; all of these must remain set for an inheritance to occur. */
110 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
112 /* During reload_as_needed, element N contains the insn for which
113 hard register N was last used. Its contents are significant only
114 when reg_reloaded_valid is set for this register. */
115 static rtx_insn
*reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
117 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
118 static HARD_REG_SET reg_reloaded_valid
;
119 /* Indicate if the register was dead at the end of the reload.
120 This is only valid if reg_reloaded_contents is set and valid. */
121 static HARD_REG_SET reg_reloaded_dead
;
123 /* Indicate whether the register's current value is one that is not
124 safe to retain across a call, even for registers that are normally
125 call-saved. This is only meaningful for members of reg_reloaded_valid. */
126 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
128 /* Number of spill-regs so far; number of valid elements of spill_regs. */
131 /* In parallel with spill_regs, contains REG rtx's for those regs.
132 Holds the last rtx used for any given reg, or 0 if it has never
133 been used for spilling yet. This rtx is reused, provided it has
135 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
137 /* In parallel with spill_regs, contains nonzero for a spill reg
138 that was stored after the last time it was used.
139 The precise value is the insn generated to do the store. */
140 static rtx_insn
*spill_reg_store
[FIRST_PSEUDO_REGISTER
];
142 /* This is the register that was stored with spill_reg_store. This is a
143 copy of reload_out / reload_out_reg when the value was stored; if
144 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
145 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
147 /* This table is the inverse mapping of spill_regs:
148 indexed by hard reg number,
149 it contains the position of that reg in spill_regs,
150 or -1 for something that is not in spill_regs.
152 ?!? This is no longer accurate. */
153 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
155 /* This reg set indicates registers that can't be used as spill registers for
156 the currently processed insn. These are the hard registers which are live
157 during the insn, but not allocated to pseudos, as well as fixed
159 static HARD_REG_SET bad_spill_regs
;
161 /* These are the hard registers that can't be used as spill register for any
162 insn. This includes registers used for user variables and registers that
163 we can't eliminate. A register that appears in this set also can't be used
164 to retry register allocation. */
165 static HARD_REG_SET bad_spill_regs_global
;
167 /* Describes order of use of registers for reloading
168 of spilled pseudo-registers. `n_spills' is the number of
169 elements that are actually valid; new ones are added at the end.
171 Both spill_regs and spill_reg_order are used on two occasions:
172 once during find_reload_regs, where they keep track of the spill registers
173 for a single insn, but also during reload_as_needed where they show all
174 the registers ever used by reload. For the latter case, the information
175 is calculated during finish_spills. */
176 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
178 /* This vector of reg sets indicates, for each pseudo, which hard registers
179 may not be used for retrying global allocation because the register was
180 formerly spilled from one of them. If we allowed reallocating a pseudo to
181 a register that it was already allocated to, reload might not
183 static HARD_REG_SET
*pseudo_previous_regs
;
185 /* This vector of reg sets indicates, for each pseudo, which hard
186 registers may not be used for retrying global allocation because they
187 are used as spill registers during one of the insns in which the
189 static HARD_REG_SET
*pseudo_forbidden_regs
;
191 /* All hard regs that have been used as spill registers for any insn are
192 marked in this set. */
193 static HARD_REG_SET used_spill_regs
;
195 /* Index of last register assigned as a spill register. We allocate in
196 a round-robin fashion. */
197 static int last_spill_reg
;
199 /* Record the stack slot for each spilled hard register. */
200 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
202 /* Width allocated so far for that stack slot. */
203 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
205 /* Record which pseudos needed to be spilled. */
206 static regset_head spilled_pseudos
;
208 /* Record which pseudos changed their allocation in finish_spills. */
209 static regset_head changed_allocation_pseudos
;
211 /* Used for communication between order_regs_for_reload and count_pseudo.
212 Used to avoid counting one pseudo twice. */
213 static regset_head pseudos_counted
;
215 /* First uid used by insns created by reload in this function.
216 Used in find_equiv_reg. */
217 int reload_first_uid
;
219 /* Flag set by local-alloc or global-alloc if anything is live in
220 a call-clobbered reg across calls. */
221 int caller_save_needed
;
223 /* Set to 1 while reload_as_needed is operating.
224 Required by some machines to handle any generated moves differently. */
225 int reload_in_progress
= 0;
227 /* This obstack is used for allocation of rtl during register elimination.
228 The allocated storage can be freed once find_reloads has processed the
230 static struct obstack reload_obstack
;
232 /* Points to the beginning of the reload_obstack. All insn_chain structures
233 are allocated first. */
234 static char *reload_startobj
;
236 /* The point after all insn_chain structures. Used to quickly deallocate
237 memory allocated in copy_reloads during calculate_needs_all_insns. */
238 static char *reload_firstobj
;
240 /* This points before all local rtl generated by register elimination.
241 Used to quickly free all memory after processing one insn. */
242 static char *reload_insn_firstobj
;
244 /* List of insn_chain instructions, one for every insn that reload needs to
246 struct insn_chain
*reload_insn_chain
;
248 /* TRUE if we potentially left dead insns in the insn stream and want to
249 run DCE immediately after reload, FALSE otherwise. */
250 static bool need_dce
;
252 /* List of all insns needing reloads. */
253 static struct insn_chain
*insns_need_reload
;
255 /* This structure is used to record information about register eliminations.
256 Each array entry describes one possible way of eliminating a register
257 in favor of another. If there is more than one way of eliminating a
258 particular register, the most preferred should be specified first. */
262 int from
; /* Register number to be eliminated. */
263 int to
; /* Register number used as replacement. */
264 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
265 int can_eliminate
; /* Nonzero if this elimination can be done. */
266 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
267 target hook in previous scan over insns
269 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
270 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
271 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
272 rtx from_rtx
; /* REG rtx for the register to be eliminated.
273 We cannot simply compare the number since
274 we might then spuriously replace a hard
275 register corresponding to a pseudo
276 assigned to the reg to be eliminated. */
277 rtx to_rtx
; /* REG rtx for the replacement. */
280 static struct elim_table
*reg_eliminate
= 0;
282 /* This is an intermediate structure to initialize the table. It has
283 exactly the members provided by ELIMINABLE_REGS. */
284 static const struct elim_table_1
288 } reg_eliminate_1
[] =
292 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
294 /* Record the number of pending eliminations that have an offset not equal
295 to their initial offset. If nonzero, we use a new copy of each
296 replacement result in any insns encountered. */
297 int num_not_at_initial_offset
;
299 /* Count the number of registers that we may be able to eliminate. */
300 static int num_eliminable
;
301 /* And the number of registers that are equivalent to a constant that
302 can be eliminated to frame_pointer / arg_pointer + constant. */
303 static int num_eliminable_invariants
;
305 /* For each label, we record the offset of each elimination. If we reach
306 a label by more than one path and an offset differs, we cannot do the
307 elimination. This information is indexed by the difference of the
308 number of the label and the first label number. We can't offset the
309 pointer itself as this can cause problems on machines with segmented
310 memory. The first table is an array of flags that records whether we
311 have yet encountered a label and the second table is an array of arrays,
312 one entry in the latter array for each elimination. */
314 static int first_label_num
;
315 static char *offsets_known_at
;
316 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
318 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
320 /* Stack of addresses where an rtx has been changed. We can undo the
321 changes by popping items off the stack and restoring the original
322 value at each location.
324 We use this simplistic undo capability rather than copy_rtx as copy_rtx
325 will not make a deep copy of a normally sharable rtx, such as
326 (const (plus (symbol_ref) (const_int))). If such an expression appears
327 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
328 rtx expression would be changed. See PR 42431. */
331 static vec
<rtx_p
> substitute_stack
;
333 /* Number of labels in the current function. */
335 static int num_labels
;
337 static void replace_pseudos_in (rtx
*, machine_mode
, rtx
);
338 static void maybe_fix_stack_asms (void);
339 static void copy_reloads (struct insn_chain
*);
340 static void calculate_needs_all_insns (int);
341 static int find_reg (struct insn_chain
*, int);
342 static void find_reload_regs (struct insn_chain
*);
343 static void select_reload_regs (void);
344 static void delete_caller_save_insns (void);
346 static void spill_failure (rtx_insn
*, enum reg_class
);
347 static void count_spilled_pseudo (int, int, int);
348 static void delete_dead_insn (rtx_insn
*);
349 static void alter_reg (int, int, bool);
350 static void set_label_offsets (rtx
, rtx_insn
*, int);
351 static void check_eliminable_occurrences (rtx
);
352 static void elimination_effects (rtx
, machine_mode
);
353 static rtx
eliminate_regs_1 (rtx
, machine_mode
, rtx
, bool, bool);
354 static int eliminate_regs_in_insn (rtx_insn
*, int);
355 static void update_eliminable_offsets (void);
356 static void mark_not_eliminable (rtx
, const_rtx
, void *);
357 static void set_initial_elim_offsets (void);
358 static bool verify_initial_elim_offsets (void);
359 static void set_initial_label_offsets (void);
360 static void set_offsets_for_label (rtx_insn
*);
361 static void init_eliminable_invariants (rtx_insn
*, bool);
362 static void init_elim_table (void);
363 static void free_reg_equiv (void);
364 static void update_eliminables (HARD_REG_SET
*);
365 static bool update_eliminables_and_spill (void);
366 static void elimination_costs_in_insn (rtx_insn
*);
367 static void spill_hard_reg (unsigned int, int);
368 static int finish_spills (int);
369 static void scan_paradoxical_subregs (rtx
);
370 static void count_pseudo (int);
371 static void order_regs_for_reload (struct insn_chain
*);
372 static void reload_as_needed (int);
373 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
374 static void forget_marked_reloads (regset
);
375 static int reload_reg_class_lower (const void *, const void *);
376 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
378 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
380 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
381 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
383 static int free_for_value_p (int, machine_mode
, int, enum reload_type
,
385 static int allocate_reload_reg (struct insn_chain
*, int, int);
386 static int conflicts_with_override (rtx
);
387 static void failed_reload (rtx_insn
*, int);
388 static int set_reload_reg (int, int);
389 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
390 static void choose_reload_regs (struct insn_chain
*);
391 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
393 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
395 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
396 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
397 static void emit_reload_insns (struct insn_chain
*);
398 static void delete_output_reload (rtx_insn
*, int, int, rtx
);
399 static void delete_address_reloads (rtx_insn
*, rtx_insn
*);
400 static void delete_address_reloads_1 (rtx_insn
*, rtx
, rtx_insn
*);
401 static void inc_for_reload (rtx
, rtx
, rtx
, int);
402 static void add_auto_inc_notes (rtx_insn
*, rtx
);
403 static void substitute (rtx
*, const_rtx
, rtx
);
404 static bool gen_reload_chain_without_interm_reg_p (int, int);
405 static int reloads_conflict (int, int);
406 static rtx_insn
*gen_reload (rtx
, rtx
, int, enum reload_type
);
407 static rtx_insn
*emit_insn_if_valid_for_reload (rtx
);
409 /* Initialize the reload pass. This is called at the beginning of compilation
410 and may be called again if the target is reinitialized. */
417 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
418 Set spill_indirect_levels to the number of levels such addressing is
419 permitted, zero if it is not permitted at all. */
422 = gen_rtx_MEM (Pmode
,
425 LAST_VIRTUAL_REGISTER
+ 1),
426 gen_int_mode (4, Pmode
)));
427 spill_indirect_levels
= 0;
429 while (memory_address_p (QImode
, tem
))
431 spill_indirect_levels
++;
432 tem
= gen_rtx_MEM (Pmode
, tem
);
435 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
437 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
438 indirect_symref_ok
= memory_address_p (QImode
, tem
);
440 /* See if reg+reg is a valid (and offsettable) address. */
442 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
444 tem
= gen_rtx_PLUS (Pmode
,
445 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
446 gen_rtx_REG (Pmode
, i
));
448 /* This way, we make sure that reg+reg is an offsettable address. */
449 tem
= plus_constant (Pmode
, tem
, 4);
451 for (int mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
452 if (!double_reg_address_ok
[mode
]
453 && memory_address_p ((enum machine_mode
)mode
, tem
))
454 double_reg_address_ok
[mode
] = 1;
457 /* Initialize obstack for our rtl allocation. */
458 if (reload_startobj
== NULL
)
460 gcc_obstack_init (&reload_obstack
);
461 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
464 INIT_REG_SET (&spilled_pseudos
);
465 INIT_REG_SET (&changed_allocation_pseudos
);
466 INIT_REG_SET (&pseudos_counted
);
469 /* List of insn chains that are currently unused. */
470 static struct insn_chain
*unused_insn_chains
= 0;
472 /* Allocate an empty insn_chain structure. */
474 new_insn_chain (void)
476 struct insn_chain
*c
;
478 if (unused_insn_chains
== 0)
480 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
481 INIT_REG_SET (&c
->live_throughout
);
482 INIT_REG_SET (&c
->dead_or_set
);
486 c
= unused_insn_chains
;
487 unused_insn_chains
= c
->next
;
489 c
->is_caller_save_insn
= 0;
490 c
->need_operand_change
= 0;
496 /* Small utility function to set all regs in hard reg set TO which are
497 allocated to pseudos in regset FROM. */
500 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
503 reg_set_iterator rsi
;
505 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
507 int r
= reg_renumber
[regno
];
511 /* reload_combine uses the information from DF_LIVE_IN,
512 which might still contain registers that have not
513 actually been allocated since they have an
515 gcc_assert (ira_conflicts_p
|| reload_completed
);
518 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
522 /* Replace all pseudos found in LOC with their corresponding
526 replace_pseudos_in (rtx
*loc
, machine_mode mem_mode
, rtx usage
)
539 unsigned int regno
= REGNO (x
);
541 if (regno
< FIRST_PSEUDO_REGISTER
)
544 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
548 replace_pseudos_in (loc
, mem_mode
, usage
);
552 if (reg_equiv_constant (regno
))
553 *loc
= reg_equiv_constant (regno
);
554 else if (reg_equiv_invariant (regno
))
555 *loc
= reg_equiv_invariant (regno
);
556 else if (reg_equiv_mem (regno
))
557 *loc
= reg_equiv_mem (regno
);
558 else if (reg_equiv_address (regno
))
559 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
562 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
563 || REGNO (regno_reg_rtx
[regno
]) != regno
);
564 *loc
= regno_reg_rtx
[regno
];
569 else if (code
== MEM
)
571 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
575 /* Process each of our operands recursively. */
576 fmt
= GET_RTX_FORMAT (code
);
577 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
579 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
580 else if (*fmt
== 'E')
581 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
582 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
585 /* Determine if the current function has an exception receiver block
586 that reaches the exit block via non-exceptional edges */
589 has_nonexceptional_receiver (void)
593 basic_block
*tos
, *worklist
, bb
;
595 /* If we're not optimizing, then just err on the safe side. */
599 /* First determine which blocks can reach exit via normal paths. */
600 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
602 FOR_EACH_BB_FN (bb
, cfun
)
603 bb
->flags
&= ~BB_REACHABLE
;
605 /* Place the exit block on our worklist. */
606 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
607 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
609 /* Iterate: find everything reachable from what we've already seen. */
610 while (tos
!= worklist
)
614 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
615 if (!(e
->flags
& EDGE_ABNORMAL
))
617 basic_block src
= e
->src
;
619 if (!(src
->flags
& BB_REACHABLE
))
621 src
->flags
|= BB_REACHABLE
;
628 /* Now see if there's a reachable block with an exceptional incoming
630 FOR_EACH_BB_FN (bb
, cfun
)
631 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
634 /* No exceptional block reached exit unexceptionally. */
638 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
639 zero elements) to MAX_REG_NUM elements.
641 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
643 grow_reg_equivs (void)
645 int old_size
= vec_safe_length (reg_equivs
);
646 int max_regno
= max_reg_num ();
650 memset (&ze
, 0, sizeof (reg_equivs_t
));
651 vec_safe_reserve (reg_equivs
, max_regno
);
652 for (i
= old_size
; i
< max_regno
; i
++)
653 reg_equivs
->quick_insert (i
, ze
);
657 /* Global variables used by reload and its subroutines. */
659 /* The current basic block while in calculate_elim_costs_all_insns. */
660 static basic_block elim_bb
;
662 /* Set during calculate_needs if an insn needs register elimination. */
663 static int something_needs_elimination
;
664 /* Set during calculate_needs if an insn needs an operand changed. */
665 static int something_needs_operands_changed
;
666 /* Set by alter_regs if we spilled a register to the stack. */
667 static bool something_was_spilled
;
669 /* Nonzero means we couldn't get enough spill regs. */
672 /* Temporary array of pseudo-register number. */
673 static int *temp_pseudo_reg_arr
;
675 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
676 If that insn didn't set the register (i.e., it copied the register to
677 memory), just delete that insn instead of the equivalencing insn plus
678 anything now dead. If we call delete_dead_insn on that insn, we may
679 delete the insn that actually sets the register if the register dies
680 there and that is incorrect. */
684 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
686 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
689 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
691 rtx_insn
*equiv_insn
= as_a
<rtx_insn
*> (XEXP (list
, 0));
693 /* If we already deleted the insn or if it may trap, we can't
694 delete it. The latter case shouldn't happen, but can
695 if an insn has a variable address, gets a REG_EH_REGION
696 note added to it, and then gets converted into a load
697 from a constant address. */
698 if (NOTE_P (equiv_insn
)
699 || can_throw_internal (equiv_insn
))
701 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
702 delete_dead_insn (equiv_insn
);
704 SET_INSN_DELETED (equiv_insn
);
710 /* Return true if remove_init_insns will delete INSN. */
712 will_delete_init_insn_p (rtx_insn
*insn
)
714 rtx set
= single_set (insn
);
715 if (!set
|| !REG_P (SET_DEST (set
)))
717 unsigned regno
= REGNO (SET_DEST (set
));
719 if (can_throw_internal (insn
))
722 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
725 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
727 rtx equiv_insn
= XEXP (list
, 0);
728 if (equiv_insn
== insn
)
734 /* Main entry point for the reload pass.
736 FIRST is the first insn of the function being compiled.
738 GLOBAL nonzero means we were called from global_alloc
739 and should attempt to reallocate any pseudoregs that we
740 displace from hard regs we will use for reloads.
741 If GLOBAL is zero, we do not have enough information to do that,
742 so any pseudo reg that is spilled must go to the stack.
744 Return value is TRUE if reload likely left dead insns in the
745 stream and a DCE pass should be run to elimiante them. Else the
746 return value is FALSE. */
749 reload (rtx_insn
*first
, int global
)
753 struct elim_table
*ep
;
757 /* Make sure even insns with volatile mem refs are recognizable. */
762 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
764 /* Make sure that the last insn in the chain
765 is not something that needs reloading. */
766 emit_note (NOTE_INSN_DELETED
);
768 /* Enable find_equiv_reg to distinguish insns made by reload. */
769 reload_first_uid
= get_max_uid ();
771 #ifdef SECONDARY_MEMORY_NEEDED
772 /* Initialize the secondary memory table. */
773 clear_secondary_mem ();
776 /* We don't have a stack slot for any spill reg yet. */
777 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
778 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
780 /* Initialize the save area information for caller-save, in case some
784 /* Compute which hard registers are now in use
785 as homes for pseudo registers.
786 This is done here rather than (eg) in global_alloc
787 because this point is reached even if not optimizing. */
788 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
791 /* A function that has a nonlocal label that can reach the exit
792 block via non-exceptional paths must save all call-saved
794 if (cfun
->has_nonlocal_label
795 && has_nonexceptional_receiver ())
796 crtl
->saves_all_registers
= 1;
798 if (crtl
->saves_all_registers
)
799 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
800 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
801 df_set_regs_ever_live (i
, true);
803 /* Find all the pseudo registers that didn't get hard regs
804 but do have known equivalent constants or memory slots.
805 These include parameters (known equivalent to parameter slots)
806 and cse'd or loop-moved constant memory addresses.
808 Record constant equivalents in reg_equiv_constant
809 so they will be substituted by find_reloads.
810 Record memory equivalents in reg_mem_equiv so they can
811 be substituted eventually by altering the REG-rtx's. */
814 reg_old_renumber
= XCNEWVEC (short, max_regno
);
815 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
816 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
817 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
819 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
821 init_eliminable_invariants (first
, true);
824 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
825 stack slots to the pseudos that lack hard regs or equivalents.
826 Do not touch virtual registers. */
828 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
829 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
830 temp_pseudo_reg_arr
[n
++] = i
;
833 /* Ask IRA to order pseudo-registers for better stack slot
835 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
837 for (i
= 0; i
< n
; i
++)
838 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
840 /* If we have some registers we think can be eliminated, scan all insns to
841 see if there is an insn that sets one of these registers to something
842 other than itself plus a constant. If so, the register cannot be
843 eliminated. Doing this scan here eliminates an extra pass through the
844 main reload loop in the most common case where register elimination
846 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
848 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
850 maybe_fix_stack_asms ();
852 insns_need_reload
= 0;
853 something_needs_elimination
= 0;
855 /* Initialize to -1, which means take the first spill register. */
858 /* Spill any hard regs that we know we can't eliminate. */
859 CLEAR_HARD_REG_SET (used_spill_regs
);
860 /* There can be multiple ways to eliminate a register;
861 they should be listed adjacently.
862 Elimination for any register fails only if all possible ways fail. */
863 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
866 int can_eliminate
= 0;
869 can_eliminate
|= ep
->can_eliminate
;
872 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
874 spill_hard_reg (from
, 1);
877 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
&& frame_pointer_needed
)
878 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
880 finish_spills (global
);
882 /* From now on, we may need to generate moves differently. We may also
883 allow modifications of insns which cause them to not be recognized.
884 Any such modifications will be cleaned up during reload itself. */
885 reload_in_progress
= 1;
887 /* This loop scans the entire function each go-round
888 and repeats until one repetition spills no additional hard regs. */
891 int something_changed
;
892 HOST_WIDE_INT starting_frame_size
;
894 starting_frame_size
= get_frame_size ();
895 something_was_spilled
= false;
897 set_initial_elim_offsets ();
898 set_initial_label_offsets ();
900 /* For each pseudo register that has an equivalent location defined,
901 try to eliminate any eliminable registers (such as the frame pointer)
902 assuming initial offsets for the replacement register, which
905 If the resulting location is directly addressable, substitute
906 the MEM we just got directly for the old REG.
908 If it is not addressable but is a constant or the sum of a hard reg
909 and constant, it is probably not addressable because the constant is
910 out of range, in that case record the address; we will generate
911 hairy code to compute the address in a register each time it is
912 needed. Similarly if it is a hard register, but one that is not
913 valid as an address register.
915 If the location is not addressable, but does not have one of the
916 above forms, assign a stack slot. We have to do this to avoid the
917 potential of producing lots of reloads if, e.g., a location involves
918 a pseudo that didn't get a hard register and has an equivalent memory
919 location that also involves a pseudo that didn't get a hard register.
921 Perhaps at some point we will improve reload_when_needed handling
922 so this problem goes away. But that's very hairy. */
924 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
925 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
927 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
930 if (strict_memory_address_addr_space_p
931 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
933 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
934 else if (CONSTANT_P (XEXP (x
, 0))
935 || (REG_P (XEXP (x
, 0))
936 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
937 || (GET_CODE (XEXP (x
, 0)) == PLUS
938 && REG_P (XEXP (XEXP (x
, 0), 0))
939 && (REGNO (XEXP (XEXP (x
, 0), 0))
940 < FIRST_PSEUDO_REGISTER
)
941 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
942 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
945 /* Make a new stack slot. Then indicate that something
946 changed so we go back and recompute offsets for
947 eliminable registers because the allocation of memory
948 below might change some offset. reg_equiv_{mem,address}
949 will be set up for this pseudo on the next pass around
951 reg_equiv_memory_loc (i
) = 0;
952 reg_equiv_init (i
) = 0;
953 alter_reg (i
, -1, true);
957 if (caller_save_needed
)
960 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
962 /* If we have a stack frame, we must align it now. The
963 stack size may be a part of the offset computation for
964 register elimination. So if this changes the stack size,
965 then repeat the elimination bookkeeping. We don't
966 realign when there is no stack, as that will cause a
967 stack frame when none is needed should
968 STARTING_FRAME_OFFSET not be already aligned to
970 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
972 /* If we allocated another stack slot, redo elimination bookkeeping. */
973 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
975 if (update_eliminables_and_spill ())
980 if (caller_save_needed
)
982 save_call_clobbered_regs ();
983 /* That might have allocated new insn_chain structures. */
984 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
987 calculate_needs_all_insns (global
);
989 if (! ira_conflicts_p
)
990 /* Don't do it for IRA. We need this info because we don't
991 change live_throughout and dead_or_set for chains when IRA
993 CLEAR_REG_SET (&spilled_pseudos
);
995 something_changed
= 0;
997 /* If we allocated any new memory locations, make another pass
998 since it might have changed elimination offsets. */
999 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
1000 something_changed
= 1;
1002 /* Even if the frame size remained the same, we might still have
1003 changed elimination offsets, e.g. if find_reloads called
1004 force_const_mem requiring the back end to allocate a constant
1005 pool base register that needs to be saved on the stack. */
1006 else if (!verify_initial_elim_offsets ())
1007 something_changed
= 1;
1009 if (update_eliminables_and_spill ())
1012 something_changed
= 1;
1016 select_reload_regs ();
1019 if (insns_need_reload
)
1020 something_changed
|= finish_spills (global
);
1023 if (! something_changed
)
1026 if (caller_save_needed
)
1027 delete_caller_save_insns ();
1029 obstack_free (&reload_obstack
, reload_firstobj
);
1032 /* If global-alloc was run, notify it of any register eliminations we have
1035 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1036 if (ep
->can_eliminate
)
1037 mark_elimination (ep
->from
, ep
->to
);
1039 remove_init_insns ();
1041 /* Use the reload registers where necessary
1042 by generating move instructions to move the must-be-register
1043 values into or out of the reload registers. */
1045 if (insns_need_reload
!= 0 || something_needs_elimination
1046 || something_needs_operands_changed
)
1048 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1050 reload_as_needed (global
);
1052 gcc_assert (old_frame_size
== get_frame_size ());
1054 gcc_assert (verify_initial_elim_offsets ());
1057 /* If we were able to eliminate the frame pointer, show that it is no
1058 longer live at the start of any basic block. If it ls live by
1059 virtue of being in a pseudo, that pseudo will be marked live
1060 and hence the frame pointer will be known to be live via that
1063 if (! frame_pointer_needed
)
1064 FOR_EACH_BB_FN (bb
, cfun
)
1065 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1067 /* Come here (with failure set nonzero) if we can't get enough spill
1071 CLEAR_REG_SET (&changed_allocation_pseudos
);
1072 CLEAR_REG_SET (&spilled_pseudos
);
1073 reload_in_progress
= 0;
1075 /* Now eliminate all pseudo regs by modifying them into
1076 their equivalent memory references.
1077 The REG-rtx's for the pseudos are modified in place,
1078 so all insns that used to refer to them now refer to memory.
1080 For a reg that has a reg_equiv_address, all those insns
1081 were changed by reloading so that no insns refer to it any longer;
1082 but the DECL_RTL of a variable decl may refer to it,
1083 and if so this causes the debugging info to mention the variable. */
1085 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1089 if (reg_equiv_mem (i
))
1090 addr
= XEXP (reg_equiv_mem (i
), 0);
1092 if (reg_equiv_address (i
))
1093 addr
= reg_equiv_address (i
);
1097 if (reg_renumber
[i
] < 0)
1099 rtx reg
= regno_reg_rtx
[i
];
1101 REG_USERVAR_P (reg
) = 0;
1102 PUT_CODE (reg
, MEM
);
1103 XEXP (reg
, 0) = addr
;
1104 if (reg_equiv_memory_loc (i
))
1105 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1107 MEM_ATTRS (reg
) = 0;
1108 MEM_NOTRAP_P (reg
) = 1;
1110 else if (reg_equiv_mem (i
))
1111 XEXP (reg_equiv_mem (i
), 0) = addr
;
1114 /* We don't want complex addressing modes in debug insns
1115 if simpler ones will do, so delegitimize equivalences
1117 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1119 rtx reg
= regno_reg_rtx
[i
];
1123 if (reg_equiv_constant (i
))
1124 equiv
= reg_equiv_constant (i
);
1125 else if (reg_equiv_invariant (i
))
1126 equiv
= reg_equiv_invariant (i
);
1127 else if (reg
&& MEM_P (reg
))
1128 equiv
= targetm
.delegitimize_address (reg
);
1129 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1135 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1137 insn
= DF_REF_INSN (use
);
1139 /* Make sure the next ref is for a different instruction,
1140 so that we're not affected by the rescan. */
1141 next
= DF_REF_NEXT_REG (use
);
1142 while (next
&& DF_REF_INSN (next
) == insn
)
1143 next
= DF_REF_NEXT_REG (next
);
1145 if (DEBUG_INSN_P (insn
))
1149 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1150 df_insn_rescan_debug_internal (insn
);
1153 INSN_VAR_LOCATION_LOC (insn
)
1154 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1161 /* We must set reload_completed now since the cleanup_subreg_operands call
1162 below will re-recognize each insn and reload may have generated insns
1163 which are only valid during and after reload. */
1164 reload_completed
= 1;
1166 /* Make a pass over all the insns and delete all USEs which we inserted
1167 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1168 notes. Delete all CLOBBER insns, except those that refer to the return
1169 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1170 from misarranging variable-array code, and simplify (subreg (reg))
1171 operands. Strip and regenerate REG_INC notes that may have been moved
1174 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1180 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1181 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1183 if ((GET_CODE (PATTERN (insn
)) == USE
1184 /* We mark with QImode USEs introduced by reload itself. */
1185 && (GET_MODE (insn
) == QImode
1186 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1187 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1188 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1189 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1190 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1191 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1192 != stack_pointer_rtx
))
1193 && (!REG_P (XEXP (PATTERN (insn
), 0))
1194 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1200 /* Some CLOBBERs may survive until here and still reference unassigned
1201 pseudos with const equivalent, which may in turn cause ICE in later
1202 passes if the reference remains in place. */
1203 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1204 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1205 VOIDmode
, PATTERN (insn
));
1207 /* Discard obvious no-ops, even without -O. This optimization
1208 is fast and doesn't interfere with debugging. */
1209 if (NONJUMP_INSN_P (insn
)
1210 && GET_CODE (PATTERN (insn
)) == SET
1211 && REG_P (SET_SRC (PATTERN (insn
)))
1212 && REG_P (SET_DEST (PATTERN (insn
)))
1213 && (REGNO (SET_SRC (PATTERN (insn
)))
1214 == REGNO (SET_DEST (PATTERN (insn
)))))
1220 pnote
= ®_NOTES (insn
);
1223 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1224 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1225 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1226 *pnote
= XEXP (*pnote
, 1);
1228 pnote
= &XEXP (*pnote
, 1);
1232 add_auto_inc_notes (insn
, PATTERN (insn
));
1234 /* Simplify (subreg (reg)) if it appears as an operand. */
1235 cleanup_subreg_operands (insn
);
1237 /* Clean up invalid ASMs so that they don't confuse later passes.
1239 if (asm_noperands (PATTERN (insn
)) >= 0)
1241 extract_insn (insn
);
1242 if (!constrain_operands (1, get_enabled_alternatives (insn
)))
1244 error_for_asm (insn
,
1245 "%<asm%> operand has impossible constraints");
1252 free (temp_pseudo_reg_arr
);
1254 /* Indicate that we no longer have known memory locations or constants. */
1257 free (reg_max_ref_width
);
1258 free (reg_old_renumber
);
1259 free (pseudo_previous_regs
);
1260 free (pseudo_forbidden_regs
);
1262 CLEAR_HARD_REG_SET (used_spill_regs
);
1263 for (i
= 0; i
< n_spills
; i
++)
1264 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1266 /* Free all the insn_chain structures at once. */
1267 obstack_free (&reload_obstack
, reload_startobj
);
1268 unused_insn_chains
= 0;
1270 inserted
= fixup_abnormal_edges ();
1272 /* We've possibly turned single trapping insn into multiple ones. */
1273 if (cfun
->can_throw_non_call_exceptions
)
1275 auto_sbitmap
blocks (last_basic_block_for_fn (cfun
));
1276 bitmap_ones (blocks
);
1277 find_many_sub_basic_blocks (blocks
);
1281 commit_edge_insertions ();
1283 /* Replacing pseudos with their memory equivalents might have
1284 created shared rtx. Subsequent passes would get confused
1285 by this, so unshare everything here. */
1286 unshare_all_rtl_again (first
);
1288 #ifdef STACK_BOUNDARY
1289 /* init_emit has set the alignment of the hard frame pointer
1290 to STACK_BOUNDARY. It is very likely no longer valid if
1291 the hard frame pointer was used for register allocation. */
1292 if (!frame_pointer_needed
)
1293 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1296 substitute_stack
.release ();
1298 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1300 reload_completed
= !failure
;
1305 /* Yet another special case. Unfortunately, reg-stack forces people to
1306 write incorrect clobbers in asm statements. These clobbers must not
1307 cause the register to appear in bad_spill_regs, otherwise we'll call
1308 fatal_insn later. We clear the corresponding regnos in the live
1309 register sets to avoid this.
1310 The whole thing is rather sick, I'm afraid. */
1313 maybe_fix_stack_asms (void)
1316 const char *constraints
[MAX_RECOG_OPERANDS
];
1317 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1318 struct insn_chain
*chain
;
1320 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1323 HARD_REG_SET clobbered
, allowed
;
1326 if (! INSN_P (chain
->insn
)
1327 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1329 pat
= PATTERN (chain
->insn
);
1330 if (GET_CODE (pat
) != PARALLEL
)
1333 CLEAR_HARD_REG_SET (clobbered
);
1334 CLEAR_HARD_REG_SET (allowed
);
1336 /* First, make a mask of all stack regs that are clobbered. */
1337 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1339 rtx t
= XVECEXP (pat
, 0, i
);
1340 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1341 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1344 /* Get the operand values and constraints out of the insn. */
1345 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1346 constraints
, operand_mode
, NULL
);
1348 /* For every operand, see what registers are allowed. */
1349 for (i
= 0; i
< noperands
; i
++)
1351 const char *p
= constraints
[i
];
1352 /* For every alternative, we compute the class of registers allowed
1353 for reloading in CLS, and merge its contents into the reg set
1355 int cls
= (int) NO_REGS
;
1361 if (c
== '\0' || c
== ',' || c
== '#')
1363 /* End of one alternative - mark the regs in the current
1364 class, and reset the class. */
1365 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1371 } while (c
!= '\0' && c
!= ',');
1380 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1384 enum constraint_num cn
= lookup_constraint (p
);
1385 if (insn_extra_address_constraint (cn
))
1386 cls
= (int) reg_class_subunion
[cls
]
1387 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1390 cls
= (int) reg_class_subunion
[cls
]
1391 [reg_class_for_constraint (cn
)];
1394 p
+= CONSTRAINT_LEN (c
, p
);
1397 /* Those of the registers which are clobbered, but allowed by the
1398 constraints, must be usable as reload registers. So clear them
1399 out of the life information. */
1400 AND_HARD_REG_SET (allowed
, clobbered
);
1401 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1402 if (TEST_HARD_REG_BIT (allowed
, i
))
1404 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1405 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1412 /* Copy the global variables n_reloads and rld into the corresponding elts
1415 copy_reloads (struct insn_chain
*chain
)
1417 chain
->n_reloads
= n_reloads
;
1418 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1419 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1420 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1423 /* Walk the chain of insns, and determine for each whether it needs reloads
1424 and/or eliminations. Build the corresponding insns_need_reload list, and
1425 set something_needs_elimination as appropriate. */
1427 calculate_needs_all_insns (int global
)
1429 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1430 struct insn_chain
*chain
, *next
= 0;
1432 something_needs_elimination
= 0;
1434 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1435 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1437 rtx_insn
*insn
= chain
->insn
;
1441 /* Clear out the shortcuts. */
1442 chain
->n_reloads
= 0;
1443 chain
->need_elim
= 0;
1444 chain
->need_reload
= 0;
1445 chain
->need_operand_change
= 0;
1447 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1448 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1449 what effects this has on the known offsets at labels. */
1451 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1452 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1453 set_label_offsets (insn
, insn
, 0);
1457 rtx old_body
= PATTERN (insn
);
1458 int old_code
= INSN_CODE (insn
);
1459 rtx old_notes
= REG_NOTES (insn
);
1460 int did_elimination
= 0;
1461 int operands_changed
= 0;
1463 /* Skip insns that only set an equivalence. */
1464 if (will_delete_init_insn_p (insn
))
1467 /* If needed, eliminate any eliminable registers. */
1468 if (num_eliminable
|| num_eliminable_invariants
)
1469 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1471 /* Analyze the instruction. */
1472 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1473 global
, spill_reg_order
);
1475 /* If a no-op set needs more than one reload, this is likely
1476 to be something that needs input address reloads. We
1477 can't get rid of this cleanly later, and it is of no use
1478 anyway, so discard it now.
1479 We only do this when expensive_optimizations is enabled,
1480 since this complements reload inheritance / output
1481 reload deletion, and it can make debugging harder. */
1482 if (flag_expensive_optimizations
&& n_reloads
> 1)
1484 rtx set
= single_set (insn
);
1487 ((SET_SRC (set
) == SET_DEST (set
)
1488 && REG_P (SET_SRC (set
))
1489 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1490 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1491 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1492 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1493 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1494 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1495 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1496 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1498 if (ira_conflicts_p
)
1499 /* Inform IRA about the insn deletion. */
1500 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1501 REGNO (SET_SRC (set
)));
1503 /* Delete it from the reload chain. */
1505 chain
->prev
->next
= next
;
1507 reload_insn_chain
= next
;
1509 next
->prev
= chain
->prev
;
1510 chain
->next
= unused_insn_chains
;
1511 unused_insn_chains
= chain
;
1516 update_eliminable_offsets ();
1518 /* Remember for later shortcuts which insns had any reloads or
1519 register eliminations. */
1520 chain
->need_elim
= did_elimination
;
1521 chain
->need_reload
= n_reloads
> 0;
1522 chain
->need_operand_change
= operands_changed
;
1524 /* Discard any register replacements done. */
1525 if (did_elimination
)
1527 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1528 PATTERN (insn
) = old_body
;
1529 INSN_CODE (insn
) = old_code
;
1530 REG_NOTES (insn
) = old_notes
;
1531 something_needs_elimination
= 1;
1534 something_needs_operands_changed
|= operands_changed
;
1538 copy_reloads (chain
);
1539 *pprev_reload
= chain
;
1540 pprev_reload
= &chain
->next_need_reload
;
1547 /* This function is called from the register allocator to set up estimates
1548 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1549 an invariant. The structure is similar to calculate_needs_all_insns. */
1552 calculate_elim_costs_all_insns (void)
1554 int *reg_equiv_init_cost
;
1558 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1560 init_eliminable_invariants (get_insns (), false);
1562 set_initial_elim_offsets ();
1563 set_initial_label_offsets ();
1565 FOR_EACH_BB_FN (bb
, cfun
)
1570 FOR_BB_INSNS (bb
, insn
)
1572 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1573 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1574 what effects this has on the known offsets at labels. */
1576 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1577 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1578 set_label_offsets (insn
, insn
, 0);
1582 rtx set
= single_set (insn
);
1584 /* Skip insns that only set an equivalence. */
1585 if (set
&& REG_P (SET_DEST (set
))
1586 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1587 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1588 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1590 unsigned regno
= REGNO (SET_DEST (set
));
1591 rtx_insn_list
*init
= reg_equiv_init (regno
);
1594 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1596 machine_mode mode
= GET_MODE (SET_DEST (set
));
1597 int cost
= set_src_cost (t
, mode
,
1598 optimize_bb_for_speed_p (bb
));
1599 int freq
= REG_FREQ_FROM_BB (bb
);
1601 reg_equiv_init_cost
[regno
] = cost
* freq
;
1605 /* If needed, eliminate any eliminable registers. */
1606 if (num_eliminable
|| num_eliminable_invariants
)
1607 elimination_costs_in_insn (insn
);
1610 update_eliminable_offsets ();
1614 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1616 if (reg_equiv_invariant (i
))
1618 if (reg_equiv_init (i
))
1620 int cost
= reg_equiv_init_cost
[i
];
1623 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1625 ira_adjust_equiv_reg_cost (i
, cost
);
1631 "Reg %d had equivalence, but can't be eliminated\n",
1633 ira_adjust_equiv_reg_cost (i
, 0);
1638 free (reg_equiv_init_cost
);
1639 free (offsets_known_at
);
1642 offsets_known_at
= NULL
;
1645 /* Comparison function for qsort to decide which of two reloads
1646 should be handled first. *P1 and *P2 are the reload numbers. */
1649 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1651 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1654 /* Consider required reloads before optional ones. */
1655 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1659 /* Count all solitary classes before non-solitary ones. */
1660 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1661 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1665 /* Aside from solitaires, consider all multi-reg groups first. */
1666 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1670 /* Consider reloads in order of increasing reg-class number. */
1671 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1675 /* If reloads are equally urgent, sort by reload number,
1676 so that the results of qsort leave nothing to chance. */
1680 /* The cost of spilling each hard reg. */
1681 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1683 /* When spilling multiple hard registers, we use SPILL_COST for the first
1684 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1685 only the first hard reg for a multi-reg pseudo. */
1686 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1688 /* Map of hard regno to pseudo regno currently occupying the hard
1690 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1692 /* Update the spill cost arrays, considering that pseudo REG is live. */
1695 count_pseudo (int reg
)
1697 int freq
= REG_FREQ (reg
);
1698 int r
= reg_renumber
[reg
];
1701 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1702 if (ira_conflicts_p
&& r
< 0)
1705 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1706 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1709 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1711 gcc_assert (r
>= 0);
1713 spill_add_cost
[r
] += freq
;
1714 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1717 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1718 spill_cost
[r
+ nregs
] += freq
;
1722 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1723 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1726 order_regs_for_reload (struct insn_chain
*chain
)
1729 HARD_REG_SET used_by_pseudos
;
1730 HARD_REG_SET used_by_pseudos2
;
1731 reg_set_iterator rsi
;
1733 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1735 memset (spill_cost
, 0, sizeof spill_cost
);
1736 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1737 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1738 hard_regno_to_pseudo_regno
[i
] = -1;
1740 /* Count number of uses of each hard reg by pseudo regs allocated to it
1741 and then order them by decreasing use. First exclude hard registers
1742 that are live in or across this insn. */
1744 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1745 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1746 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1747 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1749 /* Now find out which pseudos are allocated to it, and update
1751 CLEAR_REG_SET (&pseudos_counted
);
1753 EXECUTE_IF_SET_IN_REG_SET
1754 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1758 EXECUTE_IF_SET_IN_REG_SET
1759 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1763 CLEAR_REG_SET (&pseudos_counted
);
1766 /* Vector of reload-numbers showing the order in which the reloads should
1768 static short reload_order
[MAX_RELOADS
];
1770 /* This is used to keep track of the spill regs used in one insn. */
1771 static HARD_REG_SET used_spill_regs_local
;
1773 /* We decided to spill hard register SPILLED, which has a size of
1774 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1775 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1776 update SPILL_COST/SPILL_ADD_COST. */
1779 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1781 int freq
= REG_FREQ (reg
);
1782 int r
= reg_renumber
[reg
];
1785 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1786 if (ira_conflicts_p
&& r
< 0)
1789 gcc_assert (r
>= 0);
1791 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1793 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1794 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1797 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1799 spill_add_cost
[r
] -= freq
;
1802 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1803 spill_cost
[r
+ nregs
] -= freq
;
1807 /* Find reload register to use for reload number ORDER. */
1810 find_reg (struct insn_chain
*chain
, int order
)
1812 int rnum
= reload_order
[order
];
1813 struct reload
*rl
= rld
+ rnum
;
1814 int best_cost
= INT_MAX
;
1816 unsigned int i
, j
, n
;
1818 HARD_REG_SET not_usable
;
1819 HARD_REG_SET used_by_other_reload
;
1820 reg_set_iterator rsi
;
1821 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1822 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1824 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1825 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1826 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1828 CLEAR_HARD_REG_SET (used_by_other_reload
);
1829 for (k
= 0; k
< order
; k
++)
1831 int other
= reload_order
[k
];
1833 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1834 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1835 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1838 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1840 #ifdef REG_ALLOC_ORDER
1841 unsigned int regno
= reg_alloc_order
[i
];
1843 unsigned int regno
= i
;
1846 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1847 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1848 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1850 int this_cost
= spill_cost
[regno
];
1852 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1854 for (j
= 1; j
< this_nregs
; j
++)
1856 this_cost
+= spill_add_cost
[regno
+ j
];
1857 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1858 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1864 if (ira_conflicts_p
)
1866 /* Ask IRA to find a better pseudo-register for
1868 for (n
= j
= 0; j
< this_nregs
; j
++)
1870 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1874 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1875 regno_pseudo_regs
[n
++] = r
;
1877 regno_pseudo_regs
[n
++] = -1;
1879 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1880 best_regno_pseudo_regs
,
1887 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1888 if (regno_pseudo_regs
[j
] < 0)
1895 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1897 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1899 if (this_cost
< best_cost
1900 /* Among registers with equal cost, prefer caller-saved ones, or
1901 use REG_ALLOC_ORDER if it is defined. */
1902 || (this_cost
== best_cost
1903 #ifdef REG_ALLOC_ORDER
1904 && (inv_reg_alloc_order
[regno
]
1905 < inv_reg_alloc_order
[best_reg
])
1907 && call_used_regs
[regno
]
1908 && ! call_used_regs
[best_reg
]
1913 best_cost
= this_cost
;
1921 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1923 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1924 rl
->regno
= best_reg
;
1926 EXECUTE_IF_SET_IN_REG_SET
1927 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1929 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1932 EXECUTE_IF_SET_IN_REG_SET
1933 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1935 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1938 for (i
= 0; i
< rl
->nregs
; i
++)
1940 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1941 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1942 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1943 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1948 /* Find more reload regs to satisfy the remaining need of an insn, which
1950 Do it by ascending class number, since otherwise a reg
1951 might be spilled for a big class and might fail to count
1952 for a smaller class even though it belongs to that class. */
1955 find_reload_regs (struct insn_chain
*chain
)
1959 /* In order to be certain of getting the registers we need,
1960 we must sort the reloads into order of increasing register class.
1961 Then our grabbing of reload registers will parallel the process
1962 that provided the reload registers. */
1963 for (i
= 0; i
< chain
->n_reloads
; i
++)
1965 /* Show whether this reload already has a hard reg. */
1966 if (chain
->rld
[i
].reg_rtx
)
1968 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1969 chain
->rld
[i
].regno
= regno
;
1971 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
1974 chain
->rld
[i
].regno
= -1;
1975 reload_order
[i
] = i
;
1978 n_reloads
= chain
->n_reloads
;
1979 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1981 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1984 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1986 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1988 /* Compute the order of preference for hard registers to spill. */
1990 order_regs_for_reload (chain
);
1992 for (i
= 0; i
< n_reloads
; i
++)
1994 int r
= reload_order
[i
];
1996 /* Ignore reloads that got marked inoperative. */
1997 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1998 && ! rld
[r
].optional
1999 && rld
[r
].regno
== -1)
2000 if (! find_reg (chain
, i
))
2003 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2004 spill_failure (chain
->insn
, rld
[r
].rclass
);
2010 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2011 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2013 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2017 select_reload_regs (void)
2019 struct insn_chain
*chain
;
2021 /* Try to satisfy the needs for each insn. */
2022 for (chain
= insns_need_reload
; chain
!= 0;
2023 chain
= chain
->next_need_reload
)
2024 find_reload_regs (chain
);
2027 /* Delete all insns that were inserted by emit_caller_save_insns during
2030 delete_caller_save_insns (void)
2032 struct insn_chain
*c
= reload_insn_chain
;
2036 while (c
!= 0 && c
->is_caller_save_insn
)
2038 struct insn_chain
*next
= c
->next
;
2039 rtx_insn
*insn
= c
->insn
;
2041 if (c
== reload_insn_chain
)
2042 reload_insn_chain
= next
;
2046 next
->prev
= c
->prev
;
2048 c
->prev
->next
= next
;
2049 c
->next
= unused_insn_chains
;
2050 unused_insn_chains
= c
;
2058 /* Handle the failure to find a register to spill.
2059 INSN should be one of the insns which needed this particular spill reg. */
2062 spill_failure (rtx_insn
*insn
, enum reg_class rclass
)
2064 if (asm_noperands (PATTERN (insn
)) >= 0)
2065 error_for_asm (insn
, "can%'t find a register in class %qs while "
2066 "reloading %<asm%>",
2067 reg_class_names
[rclass
]);
2070 error ("unable to find a register to spill in class %qs",
2071 reg_class_names
[rclass
]);
2075 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2076 debug_reload_to_stream (dump_file
);
2078 fatal_insn ("this is the insn:", insn
);
2082 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2083 data that is dead in INSN. */
2086 delete_dead_insn (rtx_insn
*insn
)
2088 rtx_insn
*prev
= prev_active_insn (insn
);
2091 /* If the previous insn sets a register that dies in our insn make
2092 a note that we want to run DCE immediately after reload.
2094 We used to delete the previous insn & recurse, but that's wrong for
2095 block local equivalences. Instead of trying to figure out the exact
2096 circumstances where we can delete the potentially dead insns, just
2097 let DCE do the job. */
2098 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2099 && GET_CODE (PATTERN (prev
)) == SET
2100 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2101 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2102 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2103 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2106 SET_INSN_DELETED (insn
);
2109 /* Modify the home of pseudo-reg I.
2110 The new home is present in reg_renumber[I].
2112 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2113 or it may be -1, meaning there is none or it is not relevant.
2114 This is used so that all pseudos spilled from a given hard reg
2115 can share one stack slot. */
2118 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2120 /* When outputting an inline function, this can happen
2121 for a reg that isn't actually used. */
2122 if (regno_reg_rtx
[i
] == 0)
2125 /* If the reg got changed to a MEM at rtl-generation time,
2127 if (!REG_P (regno_reg_rtx
[i
]))
2130 /* Modify the reg-rtx to contain the new hard reg
2131 number or else to contain its pseudo reg number. */
2132 SET_REGNO (regno_reg_rtx
[i
],
2133 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2135 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2136 allocate a stack slot for it. */
2138 if (reg_renumber
[i
] < 0
2139 && REG_N_REFS (i
) > 0
2140 && reg_equiv_constant (i
) == 0
2141 && (reg_equiv_invariant (i
) == 0
2142 || reg_equiv_init (i
) == 0)
2143 && reg_equiv_memory_loc (i
) == 0)
2146 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2147 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2148 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2149 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2150 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2153 something_was_spilled
= true;
2155 if (ira_conflicts_p
)
2157 /* Mark the spill for IRA. */
2158 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2160 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2166 /* Each pseudo reg has an inherent size which comes from its own mode,
2167 and a total size which provides room for paradoxical subregs
2168 which refer to the pseudo reg in wider modes.
2170 We can use a slot already allocated if it provides both
2171 enough inherent space and enough total space.
2172 Otherwise, we allocate a new slot, making sure that it has no less
2173 inherent space, and no less total space, then the previous slot. */
2174 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2178 /* No known place to spill from => no slot to reuse. */
2179 x
= assign_stack_local (mode
, total_size
,
2180 min_align
> inherent_align
2181 || total_size
> inherent_size
? -1 : 0);
2185 /* Cancel the big-endian correction done in assign_stack_local.
2186 Get the address of the beginning of the slot. This is so we
2187 can do a big-endian correction unconditionally below. */
2188 if (BYTES_BIG_ENDIAN
)
2190 adjust
= inherent_size
- total_size
;
2193 = adjust_address_nv (x
, mode_for_size (total_size
2199 if (! dont_share_p
&& ira_conflicts_p
)
2200 /* Inform IRA about allocation a new stack slot. */
2201 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2204 /* Reuse a stack slot if possible. */
2205 else if (spill_stack_slot
[from_reg
] != 0
2206 && spill_stack_slot_width
[from_reg
] >= total_size
2207 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2209 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2210 x
= spill_stack_slot
[from_reg
];
2212 /* Allocate a bigger slot. */
2215 /* Compute maximum size needed, both for inherent size
2216 and for total size. */
2219 if (spill_stack_slot
[from_reg
])
2221 if (partial_subreg_p (mode
,
2222 GET_MODE (spill_stack_slot
[from_reg
])))
2223 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2224 if (spill_stack_slot_width
[from_reg
] > total_size
)
2225 total_size
= spill_stack_slot_width
[from_reg
];
2226 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2227 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2230 /* Make a slot with that size. */
2231 x
= assign_stack_local (mode
, total_size
,
2232 min_align
> inherent_align
2233 || total_size
> inherent_size
? -1 : 0);
2236 /* Cancel the big-endian correction done in assign_stack_local.
2237 Get the address of the beginning of the slot. This is so we
2238 can do a big-endian correction unconditionally below. */
2239 if (BYTES_BIG_ENDIAN
)
2241 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2244 = adjust_address_nv (x
, mode_for_size (total_size
2250 spill_stack_slot
[from_reg
] = stack_slot
;
2251 spill_stack_slot_width
[from_reg
] = total_size
;
2254 /* On a big endian machine, the "address" of the slot
2255 is the address of the low part that fits its inherent mode. */
2256 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2257 adjust
+= (total_size
- inherent_size
);
2259 /* If we have any adjustment to make, or if the stack slot is the
2260 wrong mode, make a new stack slot. */
2261 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2263 /* Set all of the memory attributes as appropriate for a spill. */
2264 set_mem_attrs_for_spill (x
);
2266 /* Save the stack slot for later. */
2267 reg_equiv_memory_loc (i
) = x
;
2271 /* Mark the slots in regs_ever_live for the hard regs used by
2272 pseudo-reg number REGNO, accessed in MODE. */
2275 mark_home_live_1 (int regno
, machine_mode mode
)
2279 i
= reg_renumber
[regno
];
2282 lim
= end_hard_regno (mode
, i
);
2284 df_set_regs_ever_live (i
++, true);
2287 /* Mark the slots in regs_ever_live for the hard regs
2288 used by pseudo-reg number REGNO. */
2291 mark_home_live (int regno
)
2293 if (reg_renumber
[regno
] >= 0)
2294 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2297 /* This function handles the tracking of elimination offsets around branches.
2299 X is a piece of RTL being scanned.
2301 INSN is the insn that it came from, if any.
2303 INITIAL_P is nonzero if we are to set the offset to be the initial
2304 offset and zero if we are setting the offset of the label to be the
2308 set_label_offsets (rtx x
, rtx_insn
*insn
, int initial_p
)
2310 enum rtx_code code
= GET_CODE (x
);
2313 struct elim_table
*p
;
2318 if (LABEL_REF_NONLOCAL_P (x
))
2321 x
= label_ref_label (x
);
2326 /* If we know nothing about this label, set the desired offsets. Note
2327 that this sets the offset at a label to be the offset before a label
2328 if we don't know anything about the label. This is not correct for
2329 the label after a BARRIER, but is the best guess we can make. If
2330 we guessed wrong, we will suppress an elimination that might have
2331 been possible had we been able to guess correctly. */
2333 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2335 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2336 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2337 = (initial_p
? reg_eliminate
[i
].initial_offset
2338 : reg_eliminate
[i
].offset
);
2339 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2342 /* Otherwise, if this is the definition of a label and it is
2343 preceded by a BARRIER, set our offsets to the known offset of
2347 && (tem
= prev_nonnote_insn (insn
)) != 0
2349 set_offsets_for_label (insn
);
2351 /* If neither of the above cases is true, compare each offset
2352 with those previously recorded and suppress any eliminations
2353 where the offsets disagree. */
2355 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2356 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2357 != (initial_p
? reg_eliminate
[i
].initial_offset
2358 : reg_eliminate
[i
].offset
))
2359 reg_eliminate
[i
].can_eliminate
= 0;
2363 case JUMP_TABLE_DATA
:
2364 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2368 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2374 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2375 to indirectly and hence must have all eliminations at their
2377 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2378 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2379 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2385 /* Each of the labels in the parallel or address vector must be
2386 at their initial offsets. We want the first field for PARALLEL
2387 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2389 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2390 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2395 /* We only care about setting PC. If the source is not RETURN,
2396 IF_THEN_ELSE, or a label, disable any eliminations not at
2397 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2398 isn't one of those possibilities. For branches to a label,
2399 call ourselves recursively.
2401 Note that this can disable elimination unnecessarily when we have
2402 a non-local goto since it will look like a non-constant jump to
2403 someplace in the current function. This isn't a significant
2404 problem since such jumps will normally be when all elimination
2405 pairs are back to their initial offsets. */
2407 if (SET_DEST (x
) != pc_rtx
)
2410 switch (GET_CODE (SET_SRC (x
)))
2417 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2421 tem
= XEXP (SET_SRC (x
), 1);
2422 if (GET_CODE (tem
) == LABEL_REF
)
2423 set_label_offsets (label_ref_label (tem
), insn
, initial_p
);
2424 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2427 tem
= XEXP (SET_SRC (x
), 2);
2428 if (GET_CODE (tem
) == LABEL_REF
)
2429 set_label_offsets (label_ref_label (tem
), insn
, initial_p
);
2430 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2438 /* If we reach here, all eliminations must be at their initial
2439 offset because we are doing a jump to a variable address. */
2440 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2441 if (p
->offset
!= p
->initial_offset
)
2442 p
->can_eliminate
= 0;
2450 /* This function examines every reg that occurs in X and adjusts the
2451 costs for its elimination which are gathered by IRA. INSN is the
2452 insn in which X occurs. We do not recurse into MEM expressions. */
2455 note_reg_elim_costly (const_rtx x
, rtx insn
)
2457 subrtx_iterator::array_type array
;
2458 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
2460 const_rtx x
= *iter
;
2462 iter
.skip_subrtxes ();
2464 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2465 && reg_equiv_init (REGNO (x
))
2466 && reg_equiv_invariant (REGNO (x
)))
2468 rtx t
= reg_equiv_invariant (REGNO (x
));
2469 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2470 int cost
= set_src_cost (new_rtx
, Pmode
,
2471 optimize_bb_for_speed_p (elim_bb
));
2472 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2475 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2480 /* Scan X and replace any eliminable registers (such as fp) with a
2481 replacement (such as sp), plus an offset.
2483 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2484 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2485 MEM, we are allowed to replace a sum of a register and the constant zero
2486 with the register, which we cannot do outside a MEM. In addition, we need
2487 to record the fact that a register is referenced outside a MEM.
2489 If INSN is an insn, it is the insn containing X. If we replace a REG
2490 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2491 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2492 the REG is being modified.
2494 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2495 That's used when we eliminate in expressions stored in notes.
2496 This means, do not set ref_outside_mem even if the reference
2499 If FOR_COSTS is true, we are being called before reload in order to
2500 estimate the costs of keeping registers with an equivalence unallocated.
2502 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2503 replacements done assuming all offsets are at their initial values. If
2504 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2505 encounter, return the actual location so that find_reloads will do
2506 the proper thing. */
2509 eliminate_regs_1 (rtx x
, machine_mode mem_mode
, rtx insn
,
2510 bool may_use_invariant
, bool for_costs
)
2512 enum rtx_code code
= GET_CODE (x
);
2513 struct elim_table
*ep
;
2520 if (! current_function_decl
)
2540 /* First handle the case where we encounter a bare register that
2541 is eliminable. Replace it with a PLUS. */
2542 if (regno
< FIRST_PSEUDO_REGISTER
)
2544 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2546 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2547 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2550 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2552 && reg_equiv_invariant (regno
))
2554 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2555 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2556 mem_mode
, insn
, true, for_costs
);
2557 /* There exists at least one use of REGNO that cannot be
2558 eliminated. Prevent the defining insn from being deleted. */
2559 reg_equiv_init (regno
) = NULL
;
2561 alter_reg (regno
, -1, true);
2565 /* You might think handling MINUS in a manner similar to PLUS is a
2566 good idea. It is not. It has been tried multiple times and every
2567 time the change has had to have been reverted.
2569 Other parts of reload know a PLUS is special (gen_reload for example)
2570 and require special code to handle code a reloaded PLUS operand.
2572 Also consider backends where the flags register is clobbered by a
2573 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2574 lea instruction comes to mind). If we try to reload a MINUS, we
2575 may kill the flags register that was holding a useful value.
2577 So, please before trying to handle MINUS, consider reload as a
2578 whole instead of this little section as well as the backend issues. */
2580 /* If this is the sum of an eliminable register and a constant, rework
2582 if (REG_P (XEXP (x
, 0))
2583 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2584 && CONSTANT_P (XEXP (x
, 1)))
2586 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2588 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2590 /* The only time we want to replace a PLUS with a REG (this
2591 occurs when the constant operand of the PLUS is the negative
2592 of the offset) is when we are inside a MEM. We won't want
2593 to do so at other times because that would change the
2594 structure of the insn in a way that reload can't handle.
2595 We special-case the commonest situation in
2596 eliminate_regs_in_insn, so just replace a PLUS with a
2597 PLUS here, unless inside a MEM. */
2598 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2599 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2602 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2603 plus_constant (Pmode
, XEXP (x
, 1),
2604 ep
->previous_offset
));
2607 /* If the register is not eliminable, we are done since the other
2608 operand is a constant. */
2612 /* If this is part of an address, we want to bring any constant to the
2613 outermost PLUS. We will do this by doing register replacement in
2614 our operands and seeing if a constant shows up in one of them.
2616 Note that there is no risk of modifying the structure of the insn,
2617 since we only get called for its operands, thus we are either
2618 modifying the address inside a MEM, or something like an address
2619 operand of a load-address insn. */
2622 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2624 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2627 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2629 /* If one side is a PLUS and the other side is a pseudo that
2630 didn't get a hard register but has a reg_equiv_constant,
2631 we must replace the constant here since it may no longer
2632 be in the position of any operand. */
2633 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2634 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2635 && reg_renumber
[REGNO (new1
)] < 0
2637 && reg_equiv_constant (REGNO (new1
)) != 0)
2638 new1
= reg_equiv_constant (REGNO (new1
));
2639 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2640 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2641 && reg_renumber
[REGNO (new0
)] < 0
2642 && reg_equiv_constant (REGNO (new0
)) != 0)
2643 new0
= reg_equiv_constant (REGNO (new0
));
2645 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2647 /* As above, if we are not inside a MEM we do not want to
2648 turn a PLUS into something else. We might try to do so here
2649 for an addition of 0 if we aren't optimizing. */
2650 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2651 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2659 /* If this is the product of an eliminable register and a
2660 constant, apply the distribute law and move the constant out
2661 so that we have (plus (mult ..) ..). This is needed in order
2662 to keep load-address insns valid. This case is pathological.
2663 We ignore the possibility of overflow here. */
2664 if (REG_P (XEXP (x
, 0))
2665 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2666 && CONST_INT_P (XEXP (x
, 1)))
2667 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2669 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2672 /* Refs inside notes or in DEBUG_INSNs don't count for
2674 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2675 || GET_CODE (insn
) == INSN_LIST
2676 || DEBUG_INSN_P (insn
))))
2677 ep
->ref_outside_mem
= 1;
2680 plus_constant (Pmode
,
2681 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2682 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2689 /* See comments before PLUS about handling MINUS. */
2691 case DIV
: case UDIV
:
2692 case MOD
: case UMOD
:
2693 case AND
: case IOR
: case XOR
:
2694 case ROTATERT
: case ROTATE
:
2695 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2697 case GE
: case GT
: case GEU
: case GTU
:
2698 case LE
: case LT
: case LEU
: case LTU
:
2700 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2702 rtx new1
= XEXP (x
, 1)
2703 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2706 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2707 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2712 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2715 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2717 if (new_rtx
!= XEXP (x
, 0))
2719 /* If this is a REG_DEAD note, it is not valid anymore.
2720 Using the eliminated version could result in creating a
2721 REG_DEAD note for the stack or frame pointer. */
2722 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2724 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2728 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2736 /* Now do eliminations in the rest of the chain. If this was
2737 an EXPR_LIST, this might result in allocating more memory than is
2738 strictly needed, but it simplifies the code. */
2741 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2743 if (new_rtx
!= XEXP (x
, 1))
2745 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2753 /* We do not support elimination of a register that is modified.
2754 elimination_effects has already make sure that this does not
2760 /* We do not support elimination of a register that is modified.
2761 elimination_effects has already make sure that this does not
2762 happen. The only remaining case we need to consider here is
2763 that the increment value may be an eliminable register. */
2764 if (GET_CODE (XEXP (x
, 1)) == PLUS
2765 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2767 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2768 insn
, true, for_costs
);
2770 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2771 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2772 gen_rtx_PLUS (GET_MODE (x
),
2773 XEXP (x
, 0), new_rtx
));
2777 case STRICT_LOW_PART
:
2779 case SIGN_EXTEND
: case ZERO_EXTEND
:
2780 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2781 case FLOAT
: case FIX
:
2782 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2791 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2793 if (new_rtx
!= XEXP (x
, 0))
2794 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2798 /* Similar to above processing, but preserve SUBREG_BYTE.
2799 Convert (subreg (mem)) to (mem) if not paradoxical.
2800 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2801 pseudo didn't get a hard reg, we must replace this with the
2802 eliminated version of the memory location because push_reload
2803 may do the replacement in certain circumstances. */
2804 if (REG_P (SUBREG_REG (x
))
2805 && !paradoxical_subreg_p (x
)
2807 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2809 new_rtx
= SUBREG_REG (x
);
2812 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2814 if (new_rtx
!= SUBREG_REG (x
))
2816 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2817 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2820 && ((partial_subreg_p (GET_MODE (x
), GET_MODE (new_rtx
))
2821 /* On RISC machines, combine can create rtl of the form
2822 (set (subreg:m1 (reg:m2 R) 0) ...)
2823 where m1 < m2, and expects something interesting to
2824 happen to the entire word. Moreover, it will use the
2825 (reg:m2 R) later, expecting all bits to be preserved.
2826 So if the number of words is the same, preserve the
2827 subreg so that push_reload can see it. */
2828 && !(WORD_REGISTER_OPERATIONS
2829 && (x_size
- 1) / UNITS_PER_WORD
2830 == (new_size
-1 ) / UNITS_PER_WORD
))
2831 || x_size
== new_size
)
2833 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2834 else if (insn
&& GET_CODE (insn
) == DEBUG_INSN
)
2835 return gen_rtx_raw_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2837 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2843 /* Our only special processing is to pass the mode of the MEM to our
2844 recursive call and copy the flags. While we are here, handle this
2845 case more efficiently. */
2847 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2850 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2851 && !memory_address_p (GET_MODE (x
), new_rtx
))
2852 note_reg_elim_costly (XEXP (x
, 0), insn
);
2854 return replace_equiv_address_nv (x
, new_rtx
);
2857 /* Handle insn_list USE that a call to a pure function may generate. */
2858 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2860 if (new_rtx
!= XEXP (x
, 0))
2861 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2866 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2876 /* Process each of our operands recursively. If any have changed, make a
2878 fmt
= GET_RTX_FORMAT (code
);
2879 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2883 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2885 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2887 x
= shallow_copy_rtx (x
);
2890 XEXP (x
, i
) = new_rtx
;
2892 else if (*fmt
== 'E')
2895 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2897 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2899 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2901 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2905 x
= shallow_copy_rtx (x
);
2908 XVEC (x
, i
) = new_v
;
2911 XVECEXP (x
, i
, j
) = new_rtx
;
2920 eliminate_regs (rtx x
, machine_mode mem_mode
, rtx insn
)
2922 if (reg_eliminate
== NULL
)
2924 gcc_assert (targetm
.no_register_allocation
);
2927 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2930 /* Scan rtx X for modifications of elimination target registers. Update
2931 the table of eliminables to reflect the changed state. MEM_MODE is
2932 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2935 elimination_effects (rtx x
, machine_mode mem_mode
)
2937 enum rtx_code code
= GET_CODE (x
);
2938 struct elim_table
*ep
;
2960 /* First handle the case where we encounter a bare register that
2961 is eliminable. Replace it with a PLUS. */
2962 if (regno
< FIRST_PSEUDO_REGISTER
)
2964 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2966 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2969 ep
->ref_outside_mem
= 1;
2974 else if (reg_renumber
[regno
] < 0
2976 && reg_equiv_constant (regno
)
2977 && ! function_invariant_p (reg_equiv_constant (regno
)))
2978 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
2987 /* If we modify the source of an elimination rule, disable it. */
2988 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2989 if (ep
->from_rtx
== XEXP (x
, 0))
2990 ep
->can_eliminate
= 0;
2992 /* If we modify the target of an elimination rule by adding a constant,
2993 update its offset. If we modify the target in any other way, we'll
2994 have to disable the rule as well. */
2995 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
2996 if (ep
->to_rtx
== XEXP (x
, 0))
2998 int size
= GET_MODE_SIZE (mem_mode
);
3000 /* If more bytes than MEM_MODE are pushed, account for them. */
3001 #ifdef PUSH_ROUNDING
3002 if (ep
->to_rtx
== stack_pointer_rtx
)
3003 size
= PUSH_ROUNDING (size
);
3005 if (code
== PRE_DEC
|| code
== POST_DEC
)
3007 else if (code
== PRE_INC
|| code
== POST_INC
)
3009 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3011 if (GET_CODE (XEXP (x
, 1)) == PLUS
3012 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3013 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3014 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3016 ep
->can_eliminate
= 0;
3020 /* These two aren't unary operators. */
3021 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3024 /* Fall through to generic unary operation case. */
3026 case STRICT_LOW_PART
:
3028 case SIGN_EXTEND
: case ZERO_EXTEND
:
3029 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3030 case FLOAT
: case FIX
:
3031 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3040 elimination_effects (XEXP (x
, 0), mem_mode
);
3044 if (REG_P (SUBREG_REG (x
))
3045 && !paradoxical_subreg_p (x
)
3047 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3050 elimination_effects (SUBREG_REG (x
), mem_mode
);
3054 /* If using a register that is the source of an eliminate we still
3055 think can be performed, note it cannot be performed since we don't
3056 know how this register is used. */
3057 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3058 if (ep
->from_rtx
== XEXP (x
, 0))
3059 ep
->can_eliminate
= 0;
3061 elimination_effects (XEXP (x
, 0), mem_mode
);
3065 /* If clobbering a register that is the replacement register for an
3066 elimination we still think can be performed, note that it cannot
3067 be performed. Otherwise, we need not be concerned about it. */
3068 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3069 if (ep
->to_rtx
== XEXP (x
, 0))
3070 ep
->can_eliminate
= 0;
3072 elimination_effects (XEXP (x
, 0), mem_mode
);
3076 /* Check for setting a register that we know about. */
3077 if (REG_P (SET_DEST (x
)))
3079 /* See if this is setting the replacement register for an
3082 If DEST is the hard frame pointer, we do nothing because we
3083 assume that all assignments to the frame pointer are for
3084 non-local gotos and are being done at a time when they are valid
3085 and do not disturb anything else. Some machines want to
3086 eliminate a fake argument pointer (or even a fake frame pointer)
3087 with either the real frame or the stack pointer. Assignments to
3088 the hard frame pointer must not prevent this elimination. */
3090 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3092 if (ep
->to_rtx
== SET_DEST (x
)
3093 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3095 /* If it is being incremented, adjust the offset. Otherwise,
3096 this elimination can't be done. */
3097 rtx src
= SET_SRC (x
);
3099 if (GET_CODE (src
) == PLUS
3100 && XEXP (src
, 0) == SET_DEST (x
)
3101 && CONST_INT_P (XEXP (src
, 1)))
3102 ep
->offset
-= INTVAL (XEXP (src
, 1));
3104 ep
->can_eliminate
= 0;
3108 elimination_effects (SET_DEST (x
), VOIDmode
);
3109 elimination_effects (SET_SRC (x
), VOIDmode
);
3113 /* Our only special processing is to pass the mode of the MEM to our
3115 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3122 fmt
= GET_RTX_FORMAT (code
);
3123 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3126 elimination_effects (XEXP (x
, i
), mem_mode
);
3127 else if (*fmt
== 'E')
3128 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3129 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3133 /* Descend through rtx X and verify that no references to eliminable registers
3134 remain. If any do remain, mark the involved register as not
3138 check_eliminable_occurrences (rtx x
)
3147 code
= GET_CODE (x
);
3149 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3151 struct elim_table
*ep
;
3153 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3154 if (ep
->from_rtx
== x
)
3155 ep
->can_eliminate
= 0;
3159 fmt
= GET_RTX_FORMAT (code
);
3160 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3163 check_eliminable_occurrences (XEXP (x
, i
));
3164 else if (*fmt
== 'E')
3167 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3168 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3173 /* Scan INSN and eliminate all eliminable registers in it.
3175 If REPLACE is nonzero, do the replacement destructively. Also
3176 delete the insn as dead it if it is setting an eliminable register.
3178 If REPLACE is zero, do all our allocations in reload_obstack.
3180 If no eliminations were done and this insn doesn't require any elimination
3181 processing (these are not identical conditions: it might be updating sp,
3182 but not referencing fp; this needs to be seen during reload_as_needed so
3183 that the offset between fp and sp can be taken into consideration), zero
3184 is returned. Otherwise, 1 is returned. */
3187 eliminate_regs_in_insn (rtx_insn
*insn
, int replace
)
3189 int icode
= recog_memoized (insn
);
3190 rtx old_body
= PATTERN (insn
);
3191 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3192 rtx old_set
= single_set (insn
);
3196 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3197 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3198 struct elim_table
*ep
;
3199 rtx plus_src
, plus_cst_src
;
3201 if (! insn_is_asm
&& icode
< 0)
3203 gcc_assert (DEBUG_INSN_P (insn
)
3204 || GET_CODE (PATTERN (insn
)) == USE
3205 || GET_CODE (PATTERN (insn
)) == CLOBBER
3206 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3207 if (DEBUG_INSN_P (insn
))
3208 INSN_VAR_LOCATION_LOC (insn
)
3209 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3213 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3214 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3216 /* Check for setting an eliminable register. */
3217 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3218 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3220 /* If this is setting the frame pointer register to the
3221 hardware frame pointer register and this is an elimination
3222 that will be done (tested above), this insn is really
3223 adjusting the frame pointer downward to compensate for
3224 the adjustment done before a nonlocal goto. */
3225 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3226 && ep
->from
== FRAME_POINTER_REGNUM
3227 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3229 rtx base
= SET_SRC (old_set
);
3230 rtx_insn
*base_insn
= insn
;
3231 HOST_WIDE_INT offset
= 0;
3233 while (base
!= ep
->to_rtx
)
3235 rtx_insn
*prev_insn
;
3238 if (GET_CODE (base
) == PLUS
3239 && CONST_INT_P (XEXP (base
, 1)))
3241 offset
+= INTVAL (XEXP (base
, 1));
3242 base
= XEXP (base
, 0);
3244 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3245 && (prev_set
= single_set (prev_insn
)) != 0
3246 && rtx_equal_p (SET_DEST (prev_set
), base
))
3248 base
= SET_SRC (prev_set
);
3249 base_insn
= prev_insn
;
3255 if (base
== ep
->to_rtx
)
3257 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3258 offset
- ep
->offset
);
3260 new_body
= old_body
;
3263 new_body
= copy_insn (old_body
);
3264 if (REG_NOTES (insn
))
3265 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3267 PATTERN (insn
) = new_body
;
3268 old_set
= single_set (insn
);
3270 /* First see if this insn remains valid when we
3271 make the change. If not, keep the INSN_CODE
3272 the same and let reload fit it up. */
3273 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3274 validate_change (insn
, &SET_DEST (old_set
),
3276 if (! apply_change_group ())
3278 SET_SRC (old_set
) = src
;
3279 SET_DEST (old_set
) = ep
->to_rtx
;
3287 /* In this case this insn isn't serving a useful purpose. We
3288 will delete it in reload_as_needed once we know that this
3289 elimination is, in fact, being done.
3291 If REPLACE isn't set, we can't delete this insn, but needn't
3292 process it since it won't be used unless something changes. */
3295 delete_dead_insn (insn
);
3303 /* We allow one special case which happens to work on all machines we
3304 currently support: a single set with the source or a REG_EQUAL
3305 note being a PLUS of an eliminable register and a constant. */
3306 plus_src
= plus_cst_src
= 0;
3307 if (old_set
&& REG_P (SET_DEST (old_set
)))
3309 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3310 plus_src
= SET_SRC (old_set
);
3311 /* First see if the source is of the form (plus (...) CST). */
3313 && CONST_INT_P (XEXP (plus_src
, 1)))
3314 plus_cst_src
= plus_src
;
3315 else if (REG_P (SET_SRC (old_set
))
3318 /* Otherwise, see if we have a REG_EQUAL note of the form
3319 (plus (...) CST). */
3321 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3323 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3324 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3325 && GET_CODE (XEXP (links
, 0)) == PLUS
3326 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3328 plus_cst_src
= XEXP (links
, 0);
3334 /* Check that the first operand of the PLUS is a hard reg or
3335 the lowpart subreg of one. */
3338 rtx reg
= XEXP (plus_cst_src
, 0);
3339 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3340 reg
= SUBREG_REG (reg
);
3342 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3348 rtx reg
= XEXP (plus_cst_src
, 0);
3349 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3351 if (GET_CODE (reg
) == SUBREG
)
3352 reg
= SUBREG_REG (reg
);
3354 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3355 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3357 rtx to_rtx
= ep
->to_rtx
;
3358 offset
+= ep
->offset
;
3359 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3361 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3362 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3364 /* If we have a nonzero offset, and the source is already
3365 a simple REG, the following transformation would
3366 increase the cost of the insn by replacing a simple REG
3367 with (plus (reg sp) CST). So try only when we already
3368 had a PLUS before. */
3369 if (offset
== 0 || plus_src
)
3371 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3374 new_body
= old_body
;
3377 new_body
= copy_insn (old_body
);
3378 if (REG_NOTES (insn
))
3379 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3381 PATTERN (insn
) = new_body
;
3382 old_set
= single_set (insn
);
3384 /* First see if this insn remains valid when we make the
3385 change. If not, try to replace the whole pattern with
3386 a simple set (this may help if the original insn was a
3387 PARALLEL that was only recognized as single_set due to
3388 REG_UNUSED notes). If this isn't valid either, keep
3389 the INSN_CODE the same and let reload fix it up. */
3390 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3392 rtx new_pat
= gen_rtx_SET (SET_DEST (old_set
), new_src
);
3394 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3395 SET_SRC (old_set
) = new_src
;
3402 /* This can't have an effect on elimination offsets, so skip right
3408 /* Determine the effects of this insn on elimination offsets. */
3409 elimination_effects (old_body
, VOIDmode
);
3411 /* Eliminate all eliminable registers occurring in operands that
3412 can be handled by reload. */
3413 extract_insn (insn
);
3414 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3416 orig_operand
[i
] = recog_data
.operand
[i
];
3417 substed_operand
[i
] = recog_data
.operand
[i
];
3419 /* For an asm statement, every operand is eliminable. */
3420 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3422 bool is_set_src
, in_plus
;
3424 /* Check for setting a register that we know about. */
3425 if (recog_data
.operand_type
[i
] != OP_IN
3426 && REG_P (orig_operand
[i
]))
3428 /* If we are assigning to a register that can be eliminated, it
3429 must be as part of a PARALLEL, since the code above handles
3430 single SETs. We must indicate that we can no longer
3431 eliminate this reg. */
3432 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3434 if (ep
->from_rtx
== orig_operand
[i
])
3435 ep
->can_eliminate
= 0;
3438 /* Companion to the above plus substitution, we can allow
3439 invariants as the source of a plain move. */
3442 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3446 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3447 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3451 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3452 replace
? insn
: NULL_RTX
,
3453 is_set_src
|| in_plus
, false);
3454 if (substed_operand
[i
] != orig_operand
[i
])
3456 /* Terminate the search in check_eliminable_occurrences at
3458 *recog_data
.operand_loc
[i
] = 0;
3460 /* If an output operand changed from a REG to a MEM and INSN is an
3461 insn, write a CLOBBER insn. */
3462 if (recog_data
.operand_type
[i
] != OP_IN
3463 && REG_P (orig_operand
[i
])
3464 && MEM_P (substed_operand
[i
])
3466 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3470 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3471 *recog_data
.dup_loc
[i
]
3472 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3474 /* If any eliminable remain, they aren't eliminable anymore. */
3475 check_eliminable_occurrences (old_body
);
3477 /* Substitute the operands; the new values are in the substed_operand
3479 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3480 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3481 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3482 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3484 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3485 re-recognize the insn. We do this in case we had a simple addition
3486 but now can do this as a load-address. This saves an insn in this
3488 If re-recognition fails, the old insn code number will still be used,
3489 and some register operands may have changed into PLUS expressions.
3490 These will be handled by find_reloads by loading them into a register
3495 /* If we aren't replacing things permanently and we changed something,
3496 make another copy to ensure that all the RTL is new. Otherwise
3497 things can go wrong if find_reload swaps commutative operands
3498 and one is inside RTL that has been copied while the other is not. */
3499 new_body
= old_body
;
3502 new_body
= copy_insn (old_body
);
3503 if (REG_NOTES (insn
))
3504 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3506 PATTERN (insn
) = new_body
;
3508 /* If we had a move insn but now we don't, rerecognize it. This will
3509 cause spurious re-recognition if the old move had a PARALLEL since
3510 the new one still will, but we can't call single_set without
3511 having put NEW_BODY into the insn and the re-recognition won't
3512 hurt in this rare case. */
3513 /* ??? Why this huge if statement - why don't we just rerecognize the
3517 && ((REG_P (SET_SRC (old_set
))
3518 && (GET_CODE (new_body
) != SET
3519 || !REG_P (SET_SRC (new_body
))))
3520 /* If this was a load from or store to memory, compare
3521 the MEM in recog_data.operand to the one in the insn.
3522 If they are not equal, then rerecognize the insn. */
3524 && ((MEM_P (SET_SRC (old_set
))
3525 && SET_SRC (old_set
) != recog_data
.operand
[1])
3526 || (MEM_P (SET_DEST (old_set
))
3527 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3528 /* If this was an add insn before, rerecognize. */
3529 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3531 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3533 INSN_CODE (insn
) = new_icode
;
3537 /* Restore the old body. If there were any changes to it, we made a copy
3538 of it while the changes were still in place, so we'll correctly return
3539 a modified insn below. */
3542 /* Restore the old body. */
3543 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3544 /* Restoring a top-level match_parallel would clobber the new_body
3545 we installed in the insn. */
3546 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3547 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3548 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3549 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3552 /* Update all elimination pairs to reflect the status after the current
3553 insn. The changes we make were determined by the earlier call to
3554 elimination_effects.
3556 We also detect cases where register elimination cannot be done,
3557 namely, if a register would be both changed and referenced outside a MEM
3558 in the resulting insn since such an insn is often undefined and, even if
3559 not, we cannot know what meaning will be given to it. Note that it is
3560 valid to have a register used in an address in an insn that changes it
3561 (presumably with a pre- or post-increment or decrement).
3563 If anything changes, return nonzero. */
3565 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3567 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3568 ep
->can_eliminate
= 0;
3570 ep
->ref_outside_mem
= 0;
3572 if (ep
->previous_offset
!= ep
->offset
)
3577 /* If we changed something, perform elimination in REG_NOTES. This is
3578 needed even when REPLACE is zero because a REG_DEAD note might refer
3579 to a register that we eliminate and could cause a different number
3580 of spill registers to be needed in the final reload pass than in
3582 if (val
&& REG_NOTES (insn
) != 0)
3584 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3590 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3591 register allocator. INSN is the instruction we need to examine, we perform
3592 eliminations in its operands and record cases where eliminating a reg with
3593 an invariant equivalence would add extra cost. */
3595 #pragma GCC diagnostic push
3596 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3598 elimination_costs_in_insn (rtx_insn
*insn
)
3600 int icode
= recog_memoized (insn
);
3601 rtx old_body
= PATTERN (insn
);
3602 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3603 rtx old_set
= single_set (insn
);
3605 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3606 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3607 struct elim_table
*ep
;
3608 rtx plus_src
, plus_cst_src
;
3611 if (! insn_is_asm
&& icode
< 0)
3613 gcc_assert (DEBUG_INSN_P (insn
)
3614 || GET_CODE (PATTERN (insn
)) == USE
3615 || GET_CODE (PATTERN (insn
)) == CLOBBER
3616 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3620 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3621 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3623 /* Check for setting an eliminable register. */
3624 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3625 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3629 /* We allow one special case which happens to work on all machines we
3630 currently support: a single set with the source or a REG_EQUAL
3631 note being a PLUS of an eliminable register and a constant. */
3632 plus_src
= plus_cst_src
= 0;
3634 if (old_set
&& REG_P (SET_DEST (old_set
)))
3637 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3638 plus_src
= SET_SRC (old_set
);
3639 /* First see if the source is of the form (plus (...) CST). */
3641 && CONST_INT_P (XEXP (plus_src
, 1)))
3642 plus_cst_src
= plus_src
;
3643 else if (REG_P (SET_SRC (old_set
))
3646 /* Otherwise, see if we have a REG_EQUAL note of the form
3647 (plus (...) CST). */
3649 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3651 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3652 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3653 && GET_CODE (XEXP (links
, 0)) == PLUS
3654 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3656 plus_cst_src
= XEXP (links
, 0);
3663 /* Determine the effects of this insn on elimination offsets. */
3664 elimination_effects (old_body
, VOIDmode
);
3666 /* Eliminate all eliminable registers occurring in operands that
3667 can be handled by reload. */
3668 extract_insn (insn
);
3669 int n_dups
= recog_data
.n_dups
;
3670 for (i
= 0; i
< n_dups
; i
++)
3671 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3673 int n_operands
= recog_data
.n_operands
;
3674 for (i
= 0; i
< n_operands
; i
++)
3676 orig_operand
[i
] = recog_data
.operand
[i
];
3678 /* For an asm statement, every operand is eliminable. */
3679 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3681 bool is_set_src
, in_plus
;
3683 /* Check for setting a register that we know about. */
3684 if (recog_data
.operand_type
[i
] != OP_IN
3685 && REG_P (orig_operand
[i
]))
3687 /* If we are assigning to a register that can be eliminated, it
3688 must be as part of a PARALLEL, since the code above handles
3689 single SETs. We must indicate that we can no longer
3690 eliminate this reg. */
3691 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3693 if (ep
->from_rtx
== orig_operand
[i
])
3694 ep
->can_eliminate
= 0;
3697 /* Companion to the above plus substitution, we can allow
3698 invariants as the source of a plain move. */
3700 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3702 if (is_set_src
&& !sets_reg_p
)
3703 note_reg_elim_costly (SET_SRC (old_set
), insn
);
3705 if (plus_src
&& sets_reg_p
3706 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3707 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3710 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3712 is_set_src
|| in_plus
, true);
3713 /* Terminate the search in check_eliminable_occurrences at
3715 *recog_data
.operand_loc
[i
] = 0;
3719 for (i
= 0; i
< n_dups
; i
++)
3720 *recog_data
.dup_loc
[i
]
3721 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3723 /* If any eliminable remain, they aren't eliminable anymore. */
3724 check_eliminable_occurrences (old_body
);
3726 /* Restore the old body. */
3727 for (i
= 0; i
< n_operands
; i
++)
3728 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3729 for (i
= 0; i
< n_dups
; i
++)
3730 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3732 /* Update all elimination pairs to reflect the status after the current
3733 insn. The changes we make were determined by the earlier call to
3734 elimination_effects. */
3736 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3738 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3739 ep
->can_eliminate
= 0;
3741 ep
->ref_outside_mem
= 0;
3746 #pragma GCC diagnostic pop
3748 /* Loop through all elimination pairs.
3749 Recalculate the number not at initial offset.
3751 Compute the maximum offset (minimum offset if the stack does not
3752 grow downward) for each elimination pair. */
3755 update_eliminable_offsets (void)
3757 struct elim_table
*ep
;
3759 num_not_at_initial_offset
= 0;
3760 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3762 ep
->previous_offset
= ep
->offset
;
3763 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3764 num_not_at_initial_offset
++;
3768 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3769 replacement we currently believe is valid, mark it as not eliminable if X
3770 modifies DEST in any way other than by adding a constant integer to it.
3772 If DEST is the frame pointer, we do nothing because we assume that
3773 all assignments to the hard frame pointer are nonlocal gotos and are being
3774 done at a time when they are valid and do not disturb anything else.
3775 Some machines want to eliminate a fake argument pointer with either the
3776 frame or stack pointer. Assignments to the hard frame pointer must not
3777 prevent this elimination.
3779 Called via note_stores from reload before starting its passes to scan
3780 the insns of the function. */
3783 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3787 /* A SUBREG of a hard register here is just changing its mode. We should
3788 not see a SUBREG of an eliminable hard register, but check just in
3790 if (GET_CODE (dest
) == SUBREG
)
3791 dest
= SUBREG_REG (dest
);
3793 if (dest
== hard_frame_pointer_rtx
)
3796 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3797 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3798 && (GET_CODE (x
) != SET
3799 || GET_CODE (SET_SRC (x
)) != PLUS
3800 || XEXP (SET_SRC (x
), 0) != dest
3801 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3803 reg_eliminate
[i
].can_eliminate_previous
3804 = reg_eliminate
[i
].can_eliminate
= 0;
3809 /* Verify that the initial elimination offsets did not change since the
3810 last call to set_initial_elim_offsets. This is used to catch cases
3811 where something illegal happened during reload_as_needed that could
3812 cause incorrect code to be generated if we did not check for it. */
3815 verify_initial_elim_offsets (void)
3818 struct elim_table
*ep
;
3820 if (!num_eliminable
)
3823 targetm
.compute_frame_layout ();
3824 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3826 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3827 if (t
!= ep
->initial_offset
)
3834 /* Reset all offsets on eliminable registers to their initial values. */
3837 set_initial_elim_offsets (void)
3839 struct elim_table
*ep
= reg_eliminate
;
3841 targetm
.compute_frame_layout ();
3842 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3844 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3845 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3848 num_not_at_initial_offset
= 0;
3851 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3854 set_initial_eh_label_offset (rtx label
)
3856 set_label_offsets (label
, NULL
, 1);
3859 /* Initialize the known label offsets.
3860 Set a known offset for each forced label to be at the initial offset
3861 of each elimination. We do this because we assume that all
3862 computed jumps occur from a location where each elimination is
3863 at its initial offset.
3864 For all other labels, show that we don't know the offsets. */
3867 set_initial_label_offsets (void)
3869 memset (offsets_known_at
, 0, num_labels
);
3873 FOR_EACH_VEC_SAFE_ELT (forced_labels
, i
, insn
)
3874 set_label_offsets (insn
, NULL
, 1);
3876 for (rtx_insn_list
*x
= nonlocal_goto_handler_labels
; x
; x
= x
->next ())
3878 set_label_offsets (x
->insn (), NULL
, 1);
3880 for_each_eh_label (set_initial_eh_label_offset
);
3883 /* Set all elimination offsets to the known values for the code label given
3887 set_offsets_for_label (rtx_insn
*insn
)
3890 int label_nr
= CODE_LABEL_NUMBER (insn
);
3891 struct elim_table
*ep
;
3893 num_not_at_initial_offset
= 0;
3894 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3896 ep
->offset
= ep
->previous_offset
3897 = offsets_at
[label_nr
- first_label_num
][i
];
3898 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3899 num_not_at_initial_offset
++;
3903 /* See if anything that happened changes which eliminations are valid.
3904 For example, on the SPARC, whether or not the frame pointer can
3905 be eliminated can depend on what registers have been used. We need
3906 not check some conditions again (such as flag_omit_frame_pointer)
3907 since they can't have changed. */
3910 update_eliminables (HARD_REG_SET
*pset
)
3912 int previous_frame_pointer_needed
= frame_pointer_needed
;
3913 struct elim_table
*ep
;
3915 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3916 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3917 && targetm
.frame_pointer_required ())
3918 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3920 ep
->can_eliminate
= 0;
3922 /* Look for the case where we have discovered that we can't replace
3923 register A with register B and that means that we will now be
3924 trying to replace register A with register C. This means we can
3925 no longer replace register C with register B and we need to disable
3926 such an elimination, if it exists. This occurs often with A == ap,
3927 B == sp, and C == fp. */
3929 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3931 struct elim_table
*op
;
3934 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3936 /* Find the current elimination for ep->from, if there is a
3938 for (op
= reg_eliminate
;
3939 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3940 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3946 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3948 for (op
= reg_eliminate
;
3949 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3950 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3951 op
->can_eliminate
= 0;
3955 /* See if any registers that we thought we could eliminate the previous
3956 time are no longer eliminable. If so, something has changed and we
3957 must spill the register. Also, recompute the number of eliminable
3958 registers and see if the frame pointer is needed; it is if there is
3959 no elimination of the frame pointer that we can perform. */
3961 frame_pointer_needed
= 1;
3962 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3964 if (ep
->can_eliminate
3965 && ep
->from
== FRAME_POINTER_REGNUM
3966 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
3967 && (! SUPPORTS_STACK_ALIGNMENT
3968 || ! crtl
->stack_realign_needed
))
3969 frame_pointer_needed
= 0;
3971 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3973 ep
->can_eliminate_previous
= 0;
3974 SET_HARD_REG_BIT (*pset
, ep
->from
);
3979 /* If we didn't need a frame pointer last time, but we do now, spill
3980 the hard frame pointer. */
3981 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3982 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3985 /* Call update_eliminables an spill any registers we can't eliminate anymore.
3986 Return true iff a register was spilled. */
3989 update_eliminables_and_spill (void)
3992 bool did_spill
= false;
3993 HARD_REG_SET to_spill
;
3994 CLEAR_HARD_REG_SET (to_spill
);
3995 update_eliminables (&to_spill
);
3996 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
3998 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3999 if (TEST_HARD_REG_BIT (to_spill
, i
))
4001 spill_hard_reg (i
, 1);
4004 /* Regardless of the state of spills, if we previously had
4005 a register that we thought we could eliminate, but now can
4006 not eliminate, we must run another pass.
4008 Consider pseudos which have an entry in reg_equiv_* which
4009 reference an eliminable register. We must make another pass
4010 to update reg_equiv_* so that we do not substitute in the
4011 old value from when we thought the elimination could be
4017 /* Return true if X is used as the target register of an elimination. */
4020 elimination_target_reg_p (rtx x
)
4022 struct elim_table
*ep
;
4024 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4025 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4031 /* Initialize the table of registers to eliminate.
4032 Pre-condition: global flag frame_pointer_needed has been set before
4033 calling this function. */
4036 init_elim_table (void)
4038 struct elim_table
*ep
;
4039 const struct elim_table_1
*ep1
;
4042 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4046 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4047 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4049 ep
->from
= ep1
->from
;
4051 ep
->can_eliminate
= ep
->can_eliminate_previous
4052 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4053 && ! (ep
->to
== STACK_POINTER_REGNUM
4054 && frame_pointer_needed
4055 && (! SUPPORTS_STACK_ALIGNMENT
4056 || ! stack_realign_fp
)));
4059 /* Count the number of eliminable registers and build the FROM and TO
4060 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4061 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4062 We depend on this. */
4063 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4065 num_eliminable
+= ep
->can_eliminate
;
4066 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4067 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4071 /* Find all the pseudo registers that didn't get hard regs
4072 but do have known equivalent constants or memory slots.
4073 These include parameters (known equivalent to parameter slots)
4074 and cse'd or loop-moved constant memory addresses.
4076 Record constant equivalents in reg_equiv_constant
4077 so they will be substituted by find_reloads.
4078 Record memory equivalents in reg_mem_equiv so they can
4079 be substituted eventually by altering the REG-rtx's. */
4082 init_eliminable_invariants (rtx_insn
*first
, bool do_subregs
)
4089 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4091 reg_max_ref_width
= NULL
;
4093 num_eliminable_invariants
= 0;
4095 first_label_num
= get_first_label_num ();
4096 num_labels
= max_label_num () - first_label_num
;
4098 /* Allocate the tables used to store offset information at labels. */
4099 offsets_known_at
= XNEWVEC (char, num_labels
);
4100 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4102 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4103 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4104 find largest such for each pseudo. FIRST is the head of the insn
4107 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4109 rtx set
= single_set (insn
);
4111 /* We may introduce USEs that we want to remove at the end, so
4112 we'll mark them with QImode. Make sure there are no
4113 previously-marked insns left by say regmove. */
4114 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4115 && GET_MODE (insn
) != VOIDmode
)
4116 PUT_MODE (insn
, VOIDmode
);
4118 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4119 scan_paradoxical_subregs (PATTERN (insn
));
4121 if (set
!= 0 && REG_P (SET_DEST (set
)))
4123 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4129 i
= REGNO (SET_DEST (set
));
4132 if (i
<= LAST_VIRTUAL_REGISTER
)
4135 /* If flag_pic and we have constant, verify it's legitimate. */
4137 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4139 /* It can happen that a REG_EQUIV note contains a MEM
4140 that is not a legitimate memory operand. As later
4141 stages of reload assume that all addresses found
4142 in the reg_equiv_* arrays were originally legitimate,
4143 we ignore such REG_EQUIV notes. */
4144 if (memory_operand (x
, VOIDmode
))
4146 /* Always unshare the equivalence, so we can
4147 substitute into this insn without touching the
4149 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4151 else if (function_invariant_p (x
))
4155 mode
= GET_MODE (SET_DEST (set
));
4156 if (GET_CODE (x
) == PLUS
)
4158 /* This is PLUS of frame pointer and a constant,
4159 and might be shared. Unshare it. */
4160 reg_equiv_invariant (i
) = copy_rtx (x
);
4161 num_eliminable_invariants
++;
4163 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4165 reg_equiv_invariant (i
) = x
;
4166 num_eliminable_invariants
++;
4168 else if (targetm
.legitimate_constant_p (mode
, x
))
4169 reg_equiv_constant (i
) = x
;
4172 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4173 if (! reg_equiv_memory_loc (i
))
4174 reg_equiv_init (i
) = NULL
;
4179 reg_equiv_init (i
) = NULL
;
4184 reg_equiv_init (i
) = NULL
;
4189 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4190 if (reg_equiv_init (i
))
4192 fprintf (dump_file
, "init_insns for %u: ", i
);
4193 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4194 fprintf (dump_file
, "\n");
4198 /* Indicate that we no longer have known memory locations or constants.
4199 Free all data involved in tracking these. */
4202 free_reg_equiv (void)
4206 free (offsets_known_at
);
4209 offsets_known_at
= 0;
4211 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4212 if (reg_equiv_alt_mem_list (i
))
4213 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4214 vec_free (reg_equivs
);
4217 /* Kick all pseudos out of hard register REGNO.
4219 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4220 because we found we can't eliminate some register. In the case, no pseudos
4221 are allowed to be in the register, even if they are only in a block that
4222 doesn't require spill registers, unlike the case when we are spilling this
4223 hard reg to produce another spill register.
4225 Return nonzero if any pseudos needed to be kicked out. */
4228 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4234 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4235 df_set_regs_ever_live (regno
, true);
4238 /* Spill every pseudo reg that was allocated to this reg
4239 or to something that overlaps this reg. */
4241 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4242 if (reg_renumber
[i
] >= 0
4243 && (unsigned int) reg_renumber
[i
] <= regno
4244 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4245 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4248 /* After spill_hard_reg was called and/or find_reload_regs was run for all
4249 insns that need reloads, this function is used to actually spill pseudo
4250 registers and try to reallocate them. It also sets up the spill_regs
4251 array for use by choose_reload_regs.
4253 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4254 that we displace from hard registers. */
4257 finish_spills (int global
)
4259 struct insn_chain
*chain
;
4260 int something_changed
= 0;
4262 reg_set_iterator rsi
;
4264 /* Build the spill_regs array for the function. */
4265 /* If there are some registers still to eliminate and one of the spill regs
4266 wasn't ever used before, additional stack space may have to be
4267 allocated to store this register. Thus, we may have changed the offset
4268 between the stack and frame pointers, so mark that something has changed.
4270 One might think that we need only set VAL to 1 if this is a call-used
4271 register. However, the set of registers that must be saved by the
4272 prologue is not identical to the call-used set. For example, the
4273 register used by the call insn for the return PC is a call-used register,
4274 but must be saved by the prologue. */
4277 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4278 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4280 spill_reg_order
[i
] = n_spills
;
4281 spill_regs
[n_spills
++] = i
;
4282 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4283 something_changed
= 1;
4284 df_set_regs_ever_live (i
, true);
4287 spill_reg_order
[i
] = -1;
4289 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4290 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4292 /* Record the current hard register the pseudo is allocated to
4293 in pseudo_previous_regs so we avoid reallocating it to the
4294 same hard reg in a later pass. */
4295 gcc_assert (reg_renumber
[i
] >= 0);
4297 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4298 /* Mark it as no longer having a hard register home. */
4299 reg_renumber
[i
] = -1;
4300 if (ira_conflicts_p
)
4301 /* Inform IRA about the change. */
4302 ira_mark_allocation_change (i
);
4303 /* We will need to scan everything again. */
4304 something_changed
= 1;
4307 /* Retry global register allocation if possible. */
4308 if (global
&& ira_conflicts_p
)
4312 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4313 /* For every insn that needs reloads, set the registers used as spill
4314 regs in pseudo_forbidden_regs for every pseudo live across the
4316 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4318 EXECUTE_IF_SET_IN_REG_SET
4319 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4321 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4322 chain
->used_spill_regs
);
4324 EXECUTE_IF_SET_IN_REG_SET
4325 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4327 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4328 chain
->used_spill_regs
);
4332 /* Retry allocating the pseudos spilled in IRA and the
4333 reload. For each reg, merge the various reg sets that
4334 indicate which hard regs can't be used, and call
4335 ira_reassign_pseudos. */
4336 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4337 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4339 if (reg_renumber
[i
] < 0)
4340 temp_pseudo_reg_arr
[n
++] = i
;
4342 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4344 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4345 bad_spill_regs_global
,
4346 pseudo_forbidden_regs
, pseudo_previous_regs
,
4348 something_changed
= 1;
4350 /* Fix up the register information in the insn chain.
4351 This involves deleting those of the spilled pseudos which did not get
4352 a new hard register home from the live_{before,after} sets. */
4353 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4355 HARD_REG_SET used_by_pseudos
;
4356 HARD_REG_SET used_by_pseudos2
;
4358 if (! ira_conflicts_p
)
4360 /* Don't do it for IRA because IRA and the reload still can
4361 assign hard registers to the spilled pseudos on next
4362 reload iterations. */
4363 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4364 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4366 /* Mark any unallocated hard regs as available for spills. That
4367 makes inheritance work somewhat better. */
4368 if (chain
->need_reload
)
4370 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4371 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4372 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4374 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4375 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4376 /* Value of chain->used_spill_regs from previous iteration
4377 may be not included in the value calculated here because
4378 of possible removing caller-saves insns (see function
4379 delete_caller_save_insns. */
4380 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4381 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4385 CLEAR_REG_SET (&changed_allocation_pseudos
);
4386 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4387 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4389 int regno
= reg_renumber
[i
];
4390 if (reg_old_renumber
[i
] == regno
)
4393 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4395 alter_reg (i
, reg_old_renumber
[i
], false);
4396 reg_old_renumber
[i
] = regno
;
4400 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4402 fprintf (dump_file
, " Register %d now in %d.\n\n",
4403 i
, reg_renumber
[i
]);
4407 return something_changed
;
4410 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4413 scan_paradoxical_subregs (rtx x
)
4417 enum rtx_code code
= GET_CODE (x
);
4433 if (REG_P (SUBREG_REG (x
))
4434 && (GET_MODE_SIZE (GET_MODE (x
))
4435 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4437 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4438 = GET_MODE_SIZE (GET_MODE (x
));
4439 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4447 fmt
= GET_RTX_FORMAT (code
);
4448 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4451 scan_paradoxical_subregs (XEXP (x
, i
));
4452 else if (fmt
[i
] == 'E')
4455 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4456 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4461 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4462 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4463 and apply the corresponding narrowing subreg to *OTHER_PTR.
4464 Return true if the operands were changed, false otherwise. */
4467 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4469 rtx op
, inner
, other
, tem
;
4472 if (!paradoxical_subreg_p (op
))
4474 inner
= SUBREG_REG (op
);
4477 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4481 /* If the lowpart operation turned a hard register into a subreg,
4482 rather than simplifying it to another hard register, then the
4483 mode change cannot be properly represented. For example, OTHER
4484 might be valid in its current mode, but not in the new one. */
4485 if (GET_CODE (tem
) == SUBREG
4487 && HARD_REGISTER_P (other
))
4495 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4496 examine all of the reload insns between PREV and NEXT exclusive, and
4497 annotate all that may trap. */
4500 fixup_eh_region_note (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4502 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4505 if (!insn_could_throw_p (insn
))
4506 remove_note (insn
, note
);
4507 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4510 /* Reload pseudo-registers into hard regs around each insn as needed.
4511 Additional register load insns are output before the insn that needs it
4512 and perhaps store insns after insns that modify the reloaded pseudo reg.
4514 reg_last_reload_reg and reg_reloaded_contents keep track of
4515 which registers are already available in reload registers.
4516 We update these for the reloads that we perform,
4517 as the insns are scanned. */
4520 reload_as_needed (int live_known
)
4522 struct insn_chain
*chain
;
4528 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4529 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4530 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4531 INIT_REG_SET (®_has_output_reload
);
4532 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4533 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4535 set_initial_elim_offsets ();
4537 /* Generate a marker insn that we will move around. */
4538 marker
= emit_note (NOTE_INSN_DELETED
);
4539 unlink_insn_chain (marker
, marker
);
4541 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4544 rtx_insn
*insn
= chain
->insn
;
4545 rtx_insn
*old_next
= NEXT_INSN (insn
);
4547 rtx_insn
*old_prev
= PREV_INSN (insn
);
4550 if (will_delete_init_insn_p (insn
))
4553 /* If we pass a label, copy the offsets from the label information
4554 into the current offsets of each elimination. */
4556 set_offsets_for_label (insn
);
4558 else if (INSN_P (insn
))
4560 regset_head regs_to_forget
;
4561 INIT_REG_SET (®s_to_forget
);
4562 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4564 /* If this is a USE and CLOBBER of a MEM, ensure that any
4565 references to eliminable registers have been removed. */
4567 if ((GET_CODE (PATTERN (insn
)) == USE
4568 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4569 && MEM_P (XEXP (PATTERN (insn
), 0)))
4570 XEXP (XEXP (PATTERN (insn
), 0), 0)
4571 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4572 GET_MODE (XEXP (PATTERN (insn
), 0)),
4575 /* If we need to do register elimination processing, do so.
4576 This might delete the insn, in which case we are done. */
4577 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4579 eliminate_regs_in_insn (insn
, 1);
4582 update_eliminable_offsets ();
4583 CLEAR_REG_SET (®s_to_forget
);
4588 /* If need_elim is nonzero but need_reload is zero, one might think
4589 that we could simply set n_reloads to 0. However, find_reloads
4590 could have done some manipulation of the insn (such as swapping
4591 commutative operands), and these manipulations are lost during
4592 the first pass for every insn that needs register elimination.
4593 So the actions of find_reloads must be redone here. */
4595 if (! chain
->need_elim
&& ! chain
->need_reload
4596 && ! chain
->need_operand_change
)
4598 /* First find the pseudo regs that must be reloaded for this insn.
4599 This info is returned in the tables reload_... (see reload.h).
4600 Also modify the body of INSN by substituting RELOAD
4601 rtx's for those pseudo regs. */
4604 CLEAR_REG_SET (®_has_output_reload
);
4605 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4607 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4613 rtx_insn
*next
= NEXT_INSN (insn
);
4615 /* ??? PREV can get deleted by reload inheritance.
4616 Work around this by emitting a marker note. */
4617 prev
= PREV_INSN (insn
);
4618 reorder_insns_nobb (marker
, marker
, prev
);
4620 /* Now compute which reload regs to reload them into. Perhaps
4621 reusing reload regs from previous insns, or else output
4622 load insns to reload them. Maybe output store insns too.
4623 Record the choices of reload reg in reload_reg_rtx. */
4624 choose_reload_regs (chain
);
4626 /* Generate the insns to reload operands into or out of
4627 their reload regs. */
4628 emit_reload_insns (chain
);
4630 /* Substitute the chosen reload regs from reload_reg_rtx
4631 into the insn's body (or perhaps into the bodies of other
4632 load and store insn that we just made for reloading
4633 and that we moved the structure into). */
4634 subst_reloads (insn
);
4636 prev
= PREV_INSN (marker
);
4637 unlink_insn_chain (marker
, marker
);
4639 /* Adjust the exception region notes for loads and stores. */
4640 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4641 fixup_eh_region_note (insn
, prev
, next
);
4643 /* Adjust the location of REG_ARGS_SIZE. */
4644 rtx p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4647 remove_note (insn
, p
);
4648 fixup_args_size_notes (prev
, PREV_INSN (next
),
4649 INTVAL (XEXP (p
, 0)));
4652 /* If this was an ASM, make sure that all the reload insns
4653 we have generated are valid. If not, give an error
4655 if (asm_noperands (PATTERN (insn
)) >= 0)
4656 for (rtx_insn
*p
= NEXT_INSN (prev
);
4659 if (p
!= insn
&& INSN_P (p
)
4660 && GET_CODE (PATTERN (p
)) != USE
4661 && (recog_memoized (p
) < 0
4662 || (extract_insn (p
),
4663 !(constrain_operands (1,
4664 get_enabled_alternatives (p
))))))
4666 error_for_asm (insn
,
4667 "%<asm%> operand requires "
4668 "impossible reload");
4673 if (num_eliminable
&& chain
->need_elim
)
4674 update_eliminable_offsets ();
4676 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4677 is no longer validly lying around to save a future reload.
4678 Note that this does not detect pseudos that were reloaded
4679 for this insn in order to be stored in
4680 (obeying register constraints). That is correct; such reload
4681 registers ARE still valid. */
4682 forget_marked_reloads (®s_to_forget
);
4683 CLEAR_REG_SET (®s_to_forget
);
4685 /* There may have been CLOBBER insns placed after INSN. So scan
4686 between INSN and NEXT and use them to forget old reloads. */
4687 for (rtx_insn
*x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4688 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4689 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4692 /* Likewise for regs altered by auto-increment in this insn.
4693 REG_INC notes have been changed by reloading:
4694 find_reloads_address_1 records substitutions for them,
4695 which have been performed by subst_reloads above. */
4696 for (i
= n_reloads
- 1; i
>= 0; i
--)
4698 rtx in_reg
= rld
[i
].in_reg
;
4701 enum rtx_code code
= GET_CODE (in_reg
);
4702 /* PRE_INC / PRE_DEC will have the reload register ending up
4703 with the same value as the stack slot, but that doesn't
4704 hold true for POST_INC / POST_DEC. Either we have to
4705 convert the memory access to a true POST_INC / POST_DEC,
4706 or we can't use the reload register for inheritance. */
4707 if ((code
== POST_INC
|| code
== POST_DEC
)
4708 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4709 REGNO (rld
[i
].reg_rtx
))
4710 /* Make sure it is the inc/dec pseudo, and not
4711 some other (e.g. output operand) pseudo. */
4712 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4713 == REGNO (XEXP (in_reg
, 0))))
4716 rtx reload_reg
= rld
[i
].reg_rtx
;
4717 machine_mode mode
= GET_MODE (reload_reg
);
4721 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4723 /* We really want to ignore REG_INC notes here, so
4724 use PATTERN (p) as argument to reg_set_p . */
4725 if (reg_set_p (reload_reg
, PATTERN (p
)))
4727 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4733 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4735 validate_replace_rtx_group (reload_reg
,
4737 n
= verify_changes (0);
4739 /* We must also verify that the constraints
4740 are met after the replacement. Make sure
4741 extract_insn is only called for an insn
4742 where the replacements were found to be
4747 n
= constrain_operands (1,
4748 get_enabled_alternatives (p
));
4751 /* If the constraints were not met, then
4752 undo the replacement, else confirm it. */
4756 confirm_change_group ();
4762 add_reg_note (p
, REG_INC
, reload_reg
);
4763 /* Mark this as having an output reload so that the
4764 REG_INC processing code below won't invalidate
4765 the reload for inheritance. */
4766 SET_HARD_REG_BIT (reg_is_output_reload
,
4767 REGNO (reload_reg
));
4768 SET_REGNO_REG_SET (®_has_output_reload
,
4769 REGNO (XEXP (in_reg
, 0)));
4772 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4775 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4776 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4777 REGNO (rld
[i
].reg_rtx
))
4778 /* Make sure it is the inc/dec pseudo, and not
4779 some other (e.g. output operand) pseudo. */
4780 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4781 == REGNO (XEXP (in_reg
, 0))))
4783 SET_HARD_REG_BIT (reg_is_output_reload
,
4784 REGNO (rld
[i
].reg_rtx
));
4785 SET_REGNO_REG_SET (®_has_output_reload
,
4786 REGNO (XEXP (in_reg
, 0)));
4788 else if (code
== PRE_INC
|| code
== PRE_DEC
4789 || code
== POST_INC
|| code
== POST_DEC
)
4791 int in_regno
= REGNO (XEXP (in_reg
, 0));
4793 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4796 bool forget_p
= true;
4798 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4799 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4802 for (rtx_insn
*x
= (old_prev
?
4803 NEXT_INSN (old_prev
) : insn
);
4806 if (x
== reg_reloaded_insn
[in_hard_regno
])
4812 /* If for some reasons, we didn't set up
4813 reg_last_reload_reg in this insn,
4814 invalidate inheritance from previous
4815 insns for the incremented/decremented
4816 register. Such registers will be not in
4817 reg_has_output_reload. Invalidate it
4818 also if the corresponding element in
4819 reg_reloaded_insn is also
4822 forget_old_reloads_1 (XEXP (in_reg
, 0),
4828 /* If a pseudo that got a hard register is auto-incremented,
4829 we must purge records of copying it into pseudos without
4831 for (rtx x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4832 if (REG_NOTE_KIND (x
) == REG_INC
)
4834 /* See if this pseudo reg was reloaded in this insn.
4835 If so, its last-reload info is still valid
4836 because it is based on this insn's reload. */
4837 for (i
= 0; i
< n_reloads
; i
++)
4838 if (rld
[i
].out
== XEXP (x
, 0))
4842 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4846 /* A reload reg's contents are unknown after a label. */
4848 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4850 /* Don't assume a reload reg is still good after a call insn
4851 if it is a call-used reg, or if it contains a value that will
4852 be partially clobbered by the call. */
4853 else if (CALL_P (insn
))
4855 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4856 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4858 /* If this is a call to a setjmp-type function, we must not
4859 reuse any reload reg contents across the call; that will
4860 just be clobbered by other uses of the register in later
4861 code, before the longjmp. */
4862 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4863 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4868 free (reg_last_reload_reg
);
4869 CLEAR_REG_SET (®_has_output_reload
);
4872 /* Discard all record of any value reloaded from X,
4873 or reloaded in X from someplace else;
4874 unless X is an output reload reg of the current insn.
4876 X may be a hard reg (the reload reg)
4877 or it may be a pseudo reg that was reloaded from.
4879 When DATA is non-NULL just mark the registers in regset
4880 to be forgotten later. */
4883 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4888 regset regs
= (regset
) data
;
4890 /* note_stores does give us subregs of hard regs,
4891 subreg_regno_offset requires a hard reg. */
4892 while (GET_CODE (x
) == SUBREG
)
4894 /* We ignore the subreg offset when calculating the regno,
4895 because we are using the entire underlying hard register
4905 if (regno
>= FIRST_PSEUDO_REGISTER
)
4911 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4912 /* Storing into a spilled-reg invalidates its contents.
4913 This can happen if a block-local pseudo is allocated to that reg
4914 and it wasn't spilled because this block's total need is 0.
4915 Then some insn might have an optional reload and use this reg. */
4917 for (i
= 0; i
< nr
; i
++)
4918 /* But don't do this if the reg actually serves as an output
4919 reload reg in the current instruction. */
4921 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4923 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4924 spill_reg_store
[regno
+ i
] = 0;
4930 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4933 /* Since value of X has changed,
4934 forget any value previously copied from it. */
4937 /* But don't forget a copy if this is the output reload
4938 that establishes the copy's validity. */
4940 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4941 reg_last_reload_reg
[regno
+ nr
] = 0;
4945 /* Forget the reloads marked in regset by previous function. */
4947 forget_marked_reloads (regset regs
)
4950 reg_set_iterator rsi
;
4951 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4953 if (reg
< FIRST_PSEUDO_REGISTER
4954 /* But don't do this if the reg actually serves as an output
4955 reload reg in the current instruction. */
4957 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4959 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4960 spill_reg_store
[reg
] = 0;
4963 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4964 reg_last_reload_reg
[reg
] = 0;
4968 /* The following HARD_REG_SETs indicate when each hard register is
4969 used for a reload of various parts of the current insn. */
4971 /* If reg is unavailable for all reloads. */
4972 static HARD_REG_SET reload_reg_unavailable
;
4973 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4974 static HARD_REG_SET reload_reg_used
;
4975 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4976 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4977 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4978 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4979 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4980 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4981 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4982 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4983 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4984 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4985 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4986 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4987 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4988 static HARD_REG_SET reload_reg_used_in_op_addr
;
4989 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4990 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4991 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4992 static HARD_REG_SET reload_reg_used_in_insn
;
4993 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4994 static HARD_REG_SET reload_reg_used_in_other_addr
;
4996 /* If reg is in use as a reload reg for any sort of reload. */
4997 static HARD_REG_SET reload_reg_used_at_all
;
4999 /* If reg is use as an inherited reload. We just mark the first register
5001 static HARD_REG_SET reload_reg_used_for_inherit
;
5003 /* Records which hard regs are used in any way, either as explicit use or
5004 by being allocated to a pseudo during any point of the current insn. */
5005 static HARD_REG_SET reg_used_in_insn
;
5007 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5008 TYPE. MODE is used to indicate how many consecutive regs are
5012 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5018 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5021 case RELOAD_FOR_INPUT_ADDRESS
:
5022 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5025 case RELOAD_FOR_INPADDR_ADDRESS
:
5026 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5029 case RELOAD_FOR_OUTPUT_ADDRESS
:
5030 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5033 case RELOAD_FOR_OUTADDR_ADDRESS
:
5034 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5037 case RELOAD_FOR_OPERAND_ADDRESS
:
5038 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5041 case RELOAD_FOR_OPADDR_ADDR
:
5042 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5045 case RELOAD_FOR_OTHER_ADDRESS
:
5046 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5049 case RELOAD_FOR_INPUT
:
5050 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5053 case RELOAD_FOR_OUTPUT
:
5054 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5057 case RELOAD_FOR_INSN
:
5058 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5062 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5065 /* Similarly, but show REGNO is no longer in use for a reload. */
5068 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5069 enum reload_type type
, machine_mode mode
)
5071 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5072 unsigned int start_regno
, end_regno
, r
;
5074 /* A complication is that for some reload types, inheritance might
5075 allow multiple reloads of the same types to share a reload register.
5076 We set check_opnum if we have to check only reloads with the same
5077 operand number, and check_any if we have to check all reloads. */
5078 int check_opnum
= 0;
5080 HARD_REG_SET
*used_in_set
;
5085 used_in_set
= &reload_reg_used
;
5088 case RELOAD_FOR_INPUT_ADDRESS
:
5089 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5092 case RELOAD_FOR_INPADDR_ADDRESS
:
5094 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5097 case RELOAD_FOR_OUTPUT_ADDRESS
:
5098 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5101 case RELOAD_FOR_OUTADDR_ADDRESS
:
5103 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5106 case RELOAD_FOR_OPERAND_ADDRESS
:
5107 used_in_set
= &reload_reg_used_in_op_addr
;
5110 case RELOAD_FOR_OPADDR_ADDR
:
5112 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5115 case RELOAD_FOR_OTHER_ADDRESS
:
5116 used_in_set
= &reload_reg_used_in_other_addr
;
5120 case RELOAD_FOR_INPUT
:
5121 used_in_set
= &reload_reg_used_in_input
[opnum
];
5124 case RELOAD_FOR_OUTPUT
:
5125 used_in_set
= &reload_reg_used_in_output
[opnum
];
5128 case RELOAD_FOR_INSN
:
5129 used_in_set
= &reload_reg_used_in_insn
;
5134 /* We resolve conflicts with remaining reloads of the same type by
5135 excluding the intervals of reload registers by them from the
5136 interval of freed reload registers. Since we only keep track of
5137 one set of interval bounds, we might have to exclude somewhat
5138 more than what would be necessary if we used a HARD_REG_SET here.
5139 But this should only happen very infrequently, so there should
5140 be no reason to worry about it. */
5142 start_regno
= regno
;
5143 end_regno
= regno
+ nregs
;
5144 if (check_opnum
|| check_any
)
5146 for (i
= n_reloads
- 1; i
>= 0; i
--)
5148 if (rld
[i
].when_needed
== type
5149 && (check_any
|| rld
[i
].opnum
== opnum
)
5152 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5153 unsigned int conflict_end
5154 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5156 /* If there is an overlap with the first to-be-freed register,
5157 adjust the interval start. */
5158 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5159 start_regno
= conflict_end
;
5160 /* Otherwise, if there is a conflict with one of the other
5161 to-be-freed registers, adjust the interval end. */
5162 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5163 end_regno
= conflict_start
;
5168 for (r
= start_regno
; r
< end_regno
; r
++)
5169 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5172 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5173 specified by OPNUM and TYPE. */
5176 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5180 /* In use for a RELOAD_OTHER means it's not available for anything. */
5181 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5182 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5188 /* In use for anything means we can't use it for RELOAD_OTHER. */
5189 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5190 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5191 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5192 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5195 for (i
= 0; i
< reload_n_operands
; i
++)
5196 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5197 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5198 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5199 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5200 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5201 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5206 case RELOAD_FOR_INPUT
:
5207 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5208 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5211 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5214 /* If it is used for some other input, can't use it. */
5215 for (i
= 0; i
< reload_n_operands
; i
++)
5216 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5219 /* If it is used in a later operand's address, can't use it. */
5220 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5221 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5222 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5227 case RELOAD_FOR_INPUT_ADDRESS
:
5228 /* Can't use a register if it is used for an input address for this
5229 operand or used as an input in an earlier one. */
5230 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5231 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5234 for (i
= 0; i
< opnum
; i
++)
5235 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5240 case RELOAD_FOR_INPADDR_ADDRESS
:
5241 /* Can't use a register if it is used for an input address
5242 for this operand or used as an input in an earlier
5244 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5247 for (i
= 0; i
< opnum
; i
++)
5248 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5253 case RELOAD_FOR_OUTPUT_ADDRESS
:
5254 /* Can't use a register if it is used for an output address for this
5255 operand or used as an output in this or a later operand. Note
5256 that multiple output operands are emitted in reverse order, so
5257 the conflicting ones are those with lower indices. */
5258 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5261 for (i
= 0; i
<= opnum
; i
++)
5262 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5267 case RELOAD_FOR_OUTADDR_ADDRESS
:
5268 /* Can't use a register if it is used for an output address
5269 for this operand or used as an output in this or a
5270 later operand. Note that multiple output operands are
5271 emitted in reverse order, so the conflicting ones are
5272 those with lower indices. */
5273 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5276 for (i
= 0; i
<= opnum
; i
++)
5277 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5282 case RELOAD_FOR_OPERAND_ADDRESS
:
5283 for (i
= 0; i
< reload_n_operands
; i
++)
5284 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5287 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5288 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5290 case RELOAD_FOR_OPADDR_ADDR
:
5291 for (i
= 0; i
< reload_n_operands
; i
++)
5292 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5295 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5297 case RELOAD_FOR_OUTPUT
:
5298 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5299 outputs, or an operand address for this or an earlier output.
5300 Note that multiple output operands are emitted in reverse order,
5301 so the conflicting ones are those with higher indices. */
5302 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5305 for (i
= 0; i
< reload_n_operands
; i
++)
5306 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5309 for (i
= opnum
; i
< reload_n_operands
; i
++)
5310 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5311 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5316 case RELOAD_FOR_INSN
:
5317 for (i
= 0; i
< reload_n_operands
; i
++)
5318 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5319 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5322 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5323 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5325 case RELOAD_FOR_OTHER_ADDRESS
:
5326 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5333 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5334 the number RELOADNUM, is still available in REGNO at the end of the insn.
5336 We can assume that the reload reg was already tested for availability
5337 at the time it is needed, and we should not check this again,
5338 in case the reg has already been marked in use. */
5341 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5343 int opnum
= rld
[reloadnum
].opnum
;
5344 enum reload_type type
= rld
[reloadnum
].when_needed
;
5347 /* See if there is a reload with the same type for this operand, using
5348 the same register. This case is not handled by the code below. */
5349 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5354 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5356 reg
= rld
[i
].reg_rtx
;
5357 if (reg
== NULL_RTX
)
5359 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5360 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5367 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5368 its value must reach the end. */
5371 /* If this use is for part of the insn,
5372 its value reaches if no subsequent part uses the same register.
5373 Just like the above function, don't try to do this with lots
5376 case RELOAD_FOR_OTHER_ADDRESS
:
5377 /* Here we check for everything else, since these don't conflict
5378 with anything else and everything comes later. */
5380 for (i
= 0; i
< reload_n_operands
; i
++)
5381 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5382 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5383 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5384 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5385 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5386 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5389 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5390 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5391 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5392 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5394 case RELOAD_FOR_INPUT_ADDRESS
:
5395 case RELOAD_FOR_INPADDR_ADDRESS
:
5396 /* Similar, except that we check only for this and subsequent inputs
5397 and the address of only subsequent inputs and we do not need
5398 to check for RELOAD_OTHER objects since they are known not to
5401 for (i
= opnum
; i
< reload_n_operands
; i
++)
5402 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5405 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5406 could be killed if the register is also used by reload with type
5407 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5408 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5409 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5412 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5413 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5414 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5417 for (i
= 0; i
< reload_n_operands
; i
++)
5418 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5419 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5420 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5423 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5426 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5427 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5428 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5430 case RELOAD_FOR_INPUT
:
5431 /* Similar to input address, except we start at the next operand for
5432 both input and input address and we do not check for
5433 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5436 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5437 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5438 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5439 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5442 /* ... fall through ... */
5444 case RELOAD_FOR_OPERAND_ADDRESS
:
5445 /* Check outputs and their addresses. */
5447 for (i
= 0; i
< reload_n_operands
; i
++)
5448 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5449 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5450 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5453 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5455 case RELOAD_FOR_OPADDR_ADDR
:
5456 for (i
= 0; i
< reload_n_operands
; i
++)
5457 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5458 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5459 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5462 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5463 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5464 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5466 case RELOAD_FOR_INSN
:
5467 /* These conflict with other outputs with RELOAD_OTHER. So
5468 we need only check for output addresses. */
5470 opnum
= reload_n_operands
;
5474 case RELOAD_FOR_OUTPUT
:
5475 case RELOAD_FOR_OUTPUT_ADDRESS
:
5476 case RELOAD_FOR_OUTADDR_ADDRESS
:
5477 /* We already know these can't conflict with a later output. So the
5478 only thing to check are later output addresses.
5479 Note that multiple output operands are emitted in reverse order,
5480 so the conflicting ones are those with lower indices. */
5481 for (i
= 0; i
< opnum
; i
++)
5482 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5483 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5486 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5487 could be killed if the register is also used by reload with type
5488 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5489 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5490 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5500 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5501 every register in REG. */
5504 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5508 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5509 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5515 /* Returns whether R1 and R2 are uniquely chained: the value of one
5516 is used by the other, and that value is not used by any other
5517 reload for this insn. This is used to partially undo the decision
5518 made in find_reloads when in the case of multiple
5519 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5520 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5521 reloads. This code tries to avoid the conflict created by that
5522 change. It might be cleaner to explicitly keep track of which
5523 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5524 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5525 this after the fact. */
5527 reloads_unique_chain_p (int r1
, int r2
)
5531 /* We only check input reloads. */
5532 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5535 /* Avoid anything with output reloads. */
5536 if (rld
[r1
].out
|| rld
[r2
].out
)
5539 /* "chained" means one reload is a component of the other reload,
5540 not the same as the other reload. */
5541 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5542 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5543 || rld
[r1
].optional
|| rld
[r2
].optional
5544 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5545 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5548 /* The following loop assumes that r1 is the reload that feeds r2. */
5552 for (i
= 0; i
< n_reloads
; i
++)
5553 /* Look for input reloads that aren't our two */
5554 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5556 /* If our reload is mentioned at all, it isn't a simple chain. */
5557 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5563 /* The recursive function change all occurrences of WHAT in *WHERE
5566 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5575 if (*where
== what
|| rtx_equal_p (*where
, what
))
5577 /* Record the location of the changed rtx. */
5578 substitute_stack
.safe_push (where
);
5583 code
= GET_CODE (*where
);
5584 fmt
= GET_RTX_FORMAT (code
);
5585 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5591 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5592 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5594 else if (fmt
[i
] == 'e')
5595 substitute (&XEXP (*where
, i
), what
, repl
);
5599 /* The function returns TRUE if chain of reload R1 and R2 (in any
5600 order) can be evaluated without usage of intermediate register for
5601 the reload containing another reload. It is important to see
5602 gen_reload to understand what the function is trying to do. As an
5603 example, let us have reload chain
5606 r1: <something> + const
5608 and reload R2 got reload reg HR. The function returns true if
5609 there is a correct insn HR = HR + <something>. Otherwise,
5610 gen_reload will use intermediate register (and this is the reload
5611 reg for R1) to reload <something>.
5613 We need this function to find a conflict for chain reloads. In our
5614 example, if HR = HR + <something> is incorrect insn, then we cannot
5615 use HR as a reload register for R2. If we do use it then we get a
5624 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5626 /* Assume other cases in gen_reload are not possible for
5627 chain reloads or do need an intermediate hard registers. */
5632 rtx_insn
*last
= get_last_insn ();
5634 /* Make r2 a component of r1. */
5635 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5638 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5639 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5640 gcc_assert (regno
>= 0);
5641 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5643 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5645 /* If IN is a paradoxical SUBREG, remove it and try to put the
5646 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5647 strip_paradoxical_subreg (&in
, &out
);
5649 if (GET_CODE (in
) == PLUS
5650 && (REG_P (XEXP (in
, 0))
5651 || GET_CODE (XEXP (in
, 0)) == SUBREG
5652 || MEM_P (XEXP (in
, 0)))
5653 && (REG_P (XEXP (in
, 1))
5654 || GET_CODE (XEXP (in
, 1)) == SUBREG
5655 || CONSTANT_P (XEXP (in
, 1))
5656 || MEM_P (XEXP (in
, 1))))
5658 insn
= emit_insn (gen_rtx_SET (out
, in
));
5659 code
= recog_memoized (insn
);
5664 extract_insn (insn
);
5665 /* We want constrain operands to treat this insn strictly in
5666 its validity determination, i.e., the way it would after
5667 reload has completed. */
5668 result
= constrain_operands (1, get_enabled_alternatives (insn
));
5671 delete_insns_since (last
);
5674 /* Restore the original value at each changed address within R1. */
5675 while (!substitute_stack
.is_empty ())
5677 rtx
*where
= substitute_stack
.pop ();
5678 *where
= rld
[r2
].in
;
5684 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5687 This function uses the same algorithm as reload_reg_free_p above. */
5690 reloads_conflict (int r1
, int r2
)
5692 enum reload_type r1_type
= rld
[r1
].when_needed
;
5693 enum reload_type r2_type
= rld
[r2
].when_needed
;
5694 int r1_opnum
= rld
[r1
].opnum
;
5695 int r2_opnum
= rld
[r2
].opnum
;
5697 /* RELOAD_OTHER conflicts with everything. */
5698 if (r2_type
== RELOAD_OTHER
)
5701 /* Otherwise, check conflicts differently for each type. */
5705 case RELOAD_FOR_INPUT
:
5706 return (r2_type
== RELOAD_FOR_INSN
5707 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5708 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5709 || r2_type
== RELOAD_FOR_INPUT
5710 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5711 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5712 && r2_opnum
> r1_opnum
));
5714 case RELOAD_FOR_INPUT_ADDRESS
:
5715 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5716 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5718 case RELOAD_FOR_INPADDR_ADDRESS
:
5719 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5720 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5722 case RELOAD_FOR_OUTPUT_ADDRESS
:
5723 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5724 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5726 case RELOAD_FOR_OUTADDR_ADDRESS
:
5727 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5728 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5730 case RELOAD_FOR_OPERAND_ADDRESS
:
5731 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5732 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5733 && (!reloads_unique_chain_p (r1
, r2
)
5734 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5736 case RELOAD_FOR_OPADDR_ADDR
:
5737 return (r2_type
== RELOAD_FOR_INPUT
5738 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5740 case RELOAD_FOR_OUTPUT
:
5741 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5742 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5743 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5744 && r2_opnum
>= r1_opnum
));
5746 case RELOAD_FOR_INSN
:
5747 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5748 || r2_type
== RELOAD_FOR_INSN
5749 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5751 case RELOAD_FOR_OTHER_ADDRESS
:
5752 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5762 /* Indexed by reload number, 1 if incoming value
5763 inherited from previous insns. */
5764 static char reload_inherited
[MAX_RELOADS
];
5766 /* For an inherited reload, this is the insn the reload was inherited from,
5767 if we know it. Otherwise, this is 0. */
5768 static rtx_insn
*reload_inheritance_insn
[MAX_RELOADS
];
5770 /* If nonzero, this is a place to get the value of the reload,
5771 rather than using reload_in. */
5772 static rtx reload_override_in
[MAX_RELOADS
];
5774 /* For each reload, the hard register number of the register used,
5775 or -1 if we did not need a register for this reload. */
5776 static int reload_spill_index
[MAX_RELOADS
];
5778 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5779 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5781 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5782 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5784 /* Subroutine of free_for_value_p, used to check a single register.
5785 START_REGNO is the starting regno of the full reload register
5786 (possibly comprising multiple hard registers) that we are considering. */
5789 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5790 enum reload_type type
, rtx value
, rtx out
,
5791 int reloadnum
, int ignore_address_reloads
)
5794 /* Set if we see an input reload that must not share its reload register
5795 with any new earlyclobber, but might otherwise share the reload
5796 register with an output or input-output reload. */
5797 int check_earlyclobber
= 0;
5801 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5804 if (out
== const0_rtx
)
5810 /* We use some pseudo 'time' value to check if the lifetimes of the
5811 new register use would overlap with the one of a previous reload
5812 that is not read-only or uses a different value.
5813 The 'time' used doesn't have to be linear in any shape or form, just
5815 Some reload types use different 'buckets' for each operand.
5816 So there are MAX_RECOG_OPERANDS different time values for each
5818 We compute TIME1 as the time when the register for the prospective
5819 new reload ceases to be live, and TIME2 for each existing
5820 reload as the time when that the reload register of that reload
5822 Where there is little to be gained by exact lifetime calculations,
5823 we just make conservative assumptions, i.e. a longer lifetime;
5824 this is done in the 'default:' cases. */
5827 case RELOAD_FOR_OTHER_ADDRESS
:
5828 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5829 time1
= copy
? 0 : 1;
5832 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5834 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5835 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5836 respectively, to the time values for these, we get distinct time
5837 values. To get distinct time values for each operand, we have to
5838 multiply opnum by at least three. We round that up to four because
5839 multiply by four is often cheaper. */
5840 case RELOAD_FOR_INPADDR_ADDRESS
:
5841 time1
= opnum
* 4 + 2;
5843 case RELOAD_FOR_INPUT_ADDRESS
:
5844 time1
= opnum
* 4 + 3;
5846 case RELOAD_FOR_INPUT
:
5847 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5848 executes (inclusive). */
5849 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5851 case RELOAD_FOR_OPADDR_ADDR
:
5853 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5854 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5856 case RELOAD_FOR_OPERAND_ADDRESS
:
5857 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5859 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5861 case RELOAD_FOR_OUTADDR_ADDRESS
:
5862 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5864 case RELOAD_FOR_OUTPUT_ADDRESS
:
5865 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5868 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5871 for (i
= 0; i
< n_reloads
; i
++)
5873 rtx reg
= rld
[i
].reg_rtx
;
5874 if (reg
&& REG_P (reg
)
5875 && ((unsigned) regno
- true_regnum (reg
)
5876 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5879 rtx other_input
= rld
[i
].in
;
5881 /* If the other reload loads the same input value, that
5882 will not cause a conflict only if it's loading it into
5883 the same register. */
5884 if (true_regnum (reg
) != start_regno
)
5885 other_input
= NULL_RTX
;
5886 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5887 || rld
[i
].out
|| out
)
5890 switch (rld
[i
].when_needed
)
5892 case RELOAD_FOR_OTHER_ADDRESS
:
5895 case RELOAD_FOR_INPADDR_ADDRESS
:
5896 /* find_reloads makes sure that a
5897 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5898 by at most one - the first -
5899 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5900 address reload is inherited, the address address reload
5901 goes away, so we can ignore this conflict. */
5902 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5903 && ignore_address_reloads
5904 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5905 Then the address address is still needed to store
5906 back the new address. */
5907 && ! rld
[reloadnum
].out
)
5909 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5910 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5912 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5913 && ignore_address_reloads
5914 /* Unless we are reloading an auto_inc expression. */
5915 && ! rld
[reloadnum
].out
)
5917 time2
= rld
[i
].opnum
* 4 + 2;
5919 case RELOAD_FOR_INPUT_ADDRESS
:
5920 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5921 && ignore_address_reloads
5922 && ! rld
[reloadnum
].out
)
5924 time2
= rld
[i
].opnum
* 4 + 3;
5926 case RELOAD_FOR_INPUT
:
5927 time2
= rld
[i
].opnum
* 4 + 4;
5928 check_earlyclobber
= 1;
5930 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5931 == MAX_RECOG_OPERAND * 4 */
5932 case RELOAD_FOR_OPADDR_ADDR
:
5933 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5934 && ignore_address_reloads
5935 && ! rld
[reloadnum
].out
)
5937 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5939 case RELOAD_FOR_OPERAND_ADDRESS
:
5940 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5941 check_earlyclobber
= 1;
5943 case RELOAD_FOR_INSN
:
5944 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5946 case RELOAD_FOR_OUTPUT
:
5947 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5948 instruction is executed. */
5949 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5951 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5952 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5954 case RELOAD_FOR_OUTADDR_ADDRESS
:
5955 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5956 && ignore_address_reloads
5957 && ! rld
[reloadnum
].out
)
5959 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5961 case RELOAD_FOR_OUTPUT_ADDRESS
:
5962 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5965 /* If there is no conflict in the input part, handle this
5966 like an output reload. */
5967 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5969 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5970 /* Earlyclobbered outputs must conflict with inputs. */
5971 if (earlyclobber_operand_p (rld
[i
].out
))
5972 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5977 /* RELOAD_OTHER might be live beyond instruction execution,
5978 but this is not obvious when we set time2 = 1. So check
5979 here if there might be a problem with the new reload
5980 clobbering the register used by the RELOAD_OTHER. */
5988 && (! rld
[i
].in
|| rld
[i
].out
5989 || ! rtx_equal_p (other_input
, value
)))
5990 || (out
&& rld
[reloadnum
].out_reg
5991 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5997 /* Earlyclobbered outputs must conflict with inputs. */
5998 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6004 /* Return 1 if the value in reload reg REGNO, as used by a reload
6005 needed for the part of the insn specified by OPNUM and TYPE,
6006 may be used to load VALUE into it.
6008 MODE is the mode in which the register is used, this is needed to
6009 determine how many hard regs to test.
6011 Other read-only reloads with the same value do not conflict
6012 unless OUT is nonzero and these other reloads have to live while
6013 output reloads live.
6014 If OUT is CONST0_RTX, this is a special case: it means that the
6015 test should not be for using register REGNO as reload register, but
6016 for copying from register REGNO into the reload register.
6018 RELOADNUM is the number of the reload we want to load this value for;
6019 a reload does not conflict with itself.
6021 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6022 reloads that load an address for the very reload we are considering.
6024 The caller has to make sure that there is no conflict with the return
6028 free_for_value_p (int regno
, machine_mode mode
, int opnum
,
6029 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6030 int ignore_address_reloads
)
6032 int nregs
= hard_regno_nregs
[regno
][mode
];
6034 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6035 value
, out
, reloadnum
,
6036 ignore_address_reloads
))
6041 /* Return nonzero if the rtx X is invariant over the current function. */
6042 /* ??? Actually, the places where we use this expect exactly what is
6043 tested here, and not everything that is function invariant. In
6044 particular, the frame pointer and arg pointer are special cased;
6045 pic_offset_table_rtx is not, and we must not spill these things to
6049 function_invariant_p (const_rtx x
)
6053 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6055 if (GET_CODE (x
) == PLUS
6056 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6057 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6062 /* Determine whether the reload reg X overlaps any rtx'es used for
6063 overriding inheritance. Return nonzero if so. */
6066 conflicts_with_override (rtx x
)
6069 for (i
= 0; i
< n_reloads
; i
++)
6070 if (reload_override_in
[i
]
6071 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6076 /* Give an error message saying we failed to find a reload for INSN,
6077 and clear out reload R. */
6079 failed_reload (rtx_insn
*insn
, int r
)
6081 if (asm_noperands (PATTERN (insn
)) < 0)
6082 /* It's the compiler's fault. */
6083 fatal_insn ("could not find a spill register", insn
);
6085 /* It's the user's fault; the operand's mode and constraint
6086 don't match. Disable this reload so we don't crash in final. */
6087 error_for_asm (insn
,
6088 "%<asm%> operand constraint incompatible with operand size");
6092 rld
[r
].optional
= 1;
6093 rld
[r
].secondary_p
= 1;
6096 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6097 for reload R. If it's valid, get an rtx for it. Return nonzero if
6100 set_reload_reg (int i
, int r
)
6102 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6104 int regno ATTRIBUTE_UNUSED
;
6105 rtx reg
= spill_reg_rtx
[i
];
6107 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6108 spill_reg_rtx
[i
] = reg
6109 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6111 regno
= true_regnum (reg
);
6113 /* Detect when the reload reg can't hold the reload mode.
6114 This used to be one `if', but Sequent compiler can't handle that. */
6115 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6117 machine_mode test_mode
= VOIDmode
;
6119 test_mode
= GET_MODE (rld
[r
].in
);
6120 /* If rld[r].in has VOIDmode, it means we will load it
6121 in whatever mode the reload reg has: to wit, rld[r].mode.
6122 We have already tested that for validity. */
6123 /* Aside from that, we need to test that the expressions
6124 to reload from or into have modes which are valid for this
6125 reload register. Otherwise the reload insns would be invalid. */
6126 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6127 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6128 if (! (rld
[r
].out
!= 0
6129 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6131 /* The reg is OK. */
6134 /* Mark as in use for this insn the reload regs we use
6136 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6137 rld
[r
].when_needed
, rld
[r
].mode
);
6139 rld
[r
].reg_rtx
= reg
;
6140 reload_spill_index
[r
] = spill_regs
[i
];
6147 /* Find a spill register to use as a reload register for reload R.
6148 LAST_RELOAD is nonzero if this is the last reload for the insn being
6151 Set rld[R].reg_rtx to the register allocated.
6153 We return 1 if successful, or 0 if we couldn't find a spill reg and
6154 we didn't change anything. */
6157 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6162 /* If we put this reload ahead, thinking it is a group,
6163 then insist on finding a group. Otherwise we can grab a
6164 reg that some other reload needs.
6165 (That can happen when we have a 68000 DATA_OR_FP_REG
6166 which is a group of data regs or one fp reg.)
6167 We need not be so restrictive if there are no more reloads
6170 ??? Really it would be nicer to have smarter handling
6171 for that kind of reg class, where a problem like this is normal.
6172 Perhaps those classes should be avoided for reloading
6173 by use of more alternatives. */
6175 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6177 /* If we want a single register and haven't yet found one,
6178 take any reg in the right class and not in use.
6179 If we want a consecutive group, here is where we look for it.
6181 We use three passes so we can first look for reload regs to
6182 reuse, which are already in use for other reloads in this insn,
6183 and only then use additional registers which are not "bad", then
6184 finally any register.
6186 I think that maximizing reuse is needed to make sure we don't
6187 run out of reload regs. Suppose we have three reloads, and
6188 reloads A and B can share regs. These need two regs.
6189 Suppose A and B are given different regs.
6190 That leaves none for C. */
6191 for (pass
= 0; pass
< 3; pass
++)
6193 /* I is the index in spill_regs.
6194 We advance it round-robin between insns to use all spill regs
6195 equally, so that inherited reloads have a chance
6196 of leapfrogging each other. */
6200 for (count
= 0; count
< n_spills
; count
++)
6202 int rclass
= (int) rld
[r
].rclass
;
6208 regnum
= spill_regs
[i
];
6210 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6213 /* We check reload_reg_used to make sure we
6214 don't clobber the return register. */
6215 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6216 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6217 rld
[r
].when_needed
, rld
[r
].in
,
6219 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6220 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6221 /* Look first for regs to share, then for unshared. But
6222 don't share regs used for inherited reloads; they are
6223 the ones we want to preserve. */
6225 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6227 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6230 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6232 /* During the second pass we want to avoid reload registers
6233 which are "bad" for this reload. */
6235 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6238 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6239 (on 68000) got us two FP regs. If NR is 1,
6240 we would reject both of them. */
6243 /* If we need only one reg, we have already won. */
6246 /* But reject a single reg if we demand a group. */
6251 /* Otherwise check that as many consecutive regs as we need
6252 are available here. */
6255 int regno
= regnum
+ nr
- 1;
6256 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6257 && spill_reg_order
[regno
] >= 0
6258 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6259 rld
[r
].when_needed
)))
6268 /* If we found something on the current pass, omit later passes. */
6269 if (count
< n_spills
)
6273 /* We should have found a spill register by now. */
6274 if (count
>= n_spills
)
6277 /* I is the index in SPILL_REG_RTX of the reload register we are to
6278 allocate. Get an rtx for it and find its register number. */
6280 return set_reload_reg (i
, r
);
6283 /* Initialize all the tables needed to allocate reload registers.
6284 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6285 is the array we use to restore the reg_rtx field for every reload. */
6288 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6292 for (i
= 0; i
< n_reloads
; i
++)
6293 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6295 memset (reload_inherited
, 0, MAX_RELOADS
);
6296 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6297 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6299 CLEAR_HARD_REG_SET (reload_reg_used
);
6300 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6301 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6302 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6303 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6304 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6306 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6309 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6310 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6311 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6312 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6313 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6314 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6317 for (i
= 0; i
< reload_n_operands
; i
++)
6319 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6320 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6321 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6322 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6323 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6324 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6327 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6329 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6331 for (i
= 0; i
< n_reloads
; i
++)
6332 /* If we have already decided to use a certain register,
6333 don't use it in another way. */
6335 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6336 rld
[i
].when_needed
, rld
[i
].mode
);
6339 #ifdef SECONDARY_MEMORY_NEEDED
6340 /* If X is not a subreg, return it unmodified. If it is a subreg,
6341 look up whether we made a replacement for the SUBREG_REG. Return
6342 either the replacement or the SUBREG_REG. */
6345 replaced_subreg (rtx x
)
6347 if (GET_CODE (x
) == SUBREG
)
6348 return find_replacement (&SUBREG_REG (x
));
6353 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6354 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6355 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6356 otherwise it is NULL. */
6359 compute_reload_subreg_offset (machine_mode outermode
,
6361 machine_mode innermode
)
6364 machine_mode middlemode
;
6367 return subreg_lowpart_offset (outermode
, innermode
);
6369 outer_offset
= SUBREG_BYTE (subreg
);
6370 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6372 /* If SUBREG is paradoxical then return the normal lowpart offset
6373 for OUTERMODE and INNERMODE. Our caller has already checked
6374 that OUTERMODE fits in INNERMODE. */
6375 if (paradoxical_subreg_p (outermode
, middlemode
))
6376 return subreg_lowpart_offset (outermode
, innermode
);
6378 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6379 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6380 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6383 /* Assign hard reg targets for the pseudo-registers we must reload
6384 into hard regs for this insn.
6385 Also output the instructions to copy them in and out of the hard regs.
6387 For machines with register classes, we are responsible for
6388 finding a reload reg in the proper class. */
6391 choose_reload_regs (struct insn_chain
*chain
)
6393 rtx_insn
*insn
= chain
->insn
;
6395 unsigned int max_group_size
= 1;
6396 enum reg_class group_class
= NO_REGS
;
6397 int pass
, win
, inheritance
;
6399 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6401 /* In order to be certain of getting the registers we need,
6402 we must sort the reloads into order of increasing register class.
6403 Then our grabbing of reload registers will parallel the process
6404 that provided the reload registers.
6406 Also note whether any of the reloads wants a consecutive group of regs.
6407 If so, record the maximum size of the group desired and what
6408 register class contains all the groups needed by this insn. */
6410 for (j
= 0; j
< n_reloads
; j
++)
6412 reload_order
[j
] = j
;
6413 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6415 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6416 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6417 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6420 reload_spill_index
[j
] = -1;
6422 if (rld
[j
].nregs
> 1)
6424 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6426 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6429 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6433 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6435 /* If -O, try first with inheritance, then turning it off.
6436 If not -O, don't do inheritance.
6437 Using inheritance when not optimizing leads to paradoxes
6438 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6439 because one side of the comparison might be inherited. */
6441 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6443 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6445 /* Process the reloads in order of preference just found.
6446 Beyond this point, subregs can be found in reload_reg_rtx.
6448 This used to look for an existing reloaded home for all of the
6449 reloads, and only then perform any new reloads. But that could lose
6450 if the reloads were done out of reg-class order because a later
6451 reload with a looser constraint might have an old home in a register
6452 needed by an earlier reload with a tighter constraint.
6454 To solve this, we make two passes over the reloads, in the order
6455 described above. In the first pass we try to inherit a reload
6456 from a previous insn. If there is a later reload that needs a
6457 class that is a proper subset of the class being processed, we must
6458 also allocate a spill register during the first pass.
6460 Then make a second pass over the reloads to allocate any reloads
6461 that haven't been given registers yet. */
6463 for (j
= 0; j
< n_reloads
; j
++)
6465 int r
= reload_order
[j
];
6466 rtx search_equiv
= NULL_RTX
;
6468 /* Ignore reloads that got marked inoperative. */
6469 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6470 && ! rld
[r
].secondary_p
)
6473 /* If find_reloads chose to use reload_in or reload_out as a reload
6474 register, we don't need to chose one. Otherwise, try even if it
6475 found one since we might save an insn if we find the value lying
6477 Try also when reload_in is a pseudo without a hard reg. */
6478 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6479 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6480 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6481 && !MEM_P (rld
[r
].in
)
6482 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6485 #if 0 /* No longer needed for correct operation.
6486 It might give better code, or might not; worth an experiment? */
6487 /* If this is an optional reload, we can't inherit from earlier insns
6488 until we are sure that any non-optional reloads have been allocated.
6489 The following code takes advantage of the fact that optional reloads
6490 are at the end of reload_order. */
6491 if (rld
[r
].optional
!= 0)
6492 for (i
= 0; i
< j
; i
++)
6493 if ((rld
[reload_order
[i
]].out
!= 0
6494 || rld
[reload_order
[i
]].in
!= 0
6495 || rld
[reload_order
[i
]].secondary_p
)
6496 && ! rld
[reload_order
[i
]].optional
6497 && rld
[reload_order
[i
]].reg_rtx
== 0)
6498 allocate_reload_reg (chain
, reload_order
[i
], 0);
6501 /* First see if this pseudo is already available as reloaded
6502 for a previous insn. We cannot try to inherit for reloads
6503 that are smaller than the maximum number of registers needed
6504 for groups unless the register we would allocate cannot be used
6507 We could check here to see if this is a secondary reload for
6508 an object that is already in a register of the desired class.
6509 This would avoid the need for the secondary reload register.
6510 But this is complex because we can't easily determine what
6511 objects might want to be loaded via this reload. So let a
6512 register be allocated here. In `emit_reload_insns' we suppress
6513 one of the loads in the case described above. */
6519 machine_mode mode
= VOIDmode
;
6520 rtx subreg
= NULL_RTX
;
6524 else if (REG_P (rld
[r
].in
))
6526 regno
= REGNO (rld
[r
].in
);
6527 mode
= GET_MODE (rld
[r
].in
);
6529 else if (REG_P (rld
[r
].in_reg
))
6531 regno
= REGNO (rld
[r
].in_reg
);
6532 mode
= GET_MODE (rld
[r
].in_reg
);
6534 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6535 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6537 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6538 if (regno
< FIRST_PSEUDO_REGISTER
)
6539 regno
= subreg_regno (rld
[r
].in_reg
);
6542 subreg
= rld
[r
].in_reg
;
6543 byte
= SUBREG_BYTE (subreg
);
6545 mode
= GET_MODE (rld
[r
].in_reg
);
6548 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6549 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6551 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6552 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6553 rld
[r
].out
= rld
[r
].in
;
6557 /* This won't work, since REGNO can be a pseudo reg number.
6558 Also, it takes much more hair to keep track of all the things
6559 that can invalidate an inherited reload of part of a pseudoreg. */
6560 else if (GET_CODE (rld
[r
].in
) == SUBREG
6561 && REG_P (SUBREG_REG (rld
[r
].in
)))
6562 regno
= subreg_regno (rld
[r
].in
);
6566 && reg_last_reload_reg
[regno
] != 0
6567 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6568 >= GET_MODE_SIZE (mode
) + byte
)
6569 #ifdef CANNOT_CHANGE_MODE_CLASS
6570 /* Verify that the register it's in can be used in
6572 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6573 GET_MODE (reg_last_reload_reg
[regno
]),
6578 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6579 rtx last_reg
= reg_last_reload_reg
[regno
];
6581 i
= REGNO (last_reg
);
6582 byte
= compute_reload_subreg_offset (mode
,
6584 GET_MODE (last_reg
));
6585 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6586 last_class
= REGNO_REG_CLASS (i
);
6588 if (reg_reloaded_contents
[i
] == regno
6589 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6590 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6591 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6592 /* Even if we can't use this register as a reload
6593 register, we might use it for reload_override_in,
6594 if copying it to the desired class is cheap
6596 || ((register_move_cost (mode
, last_class
, rclass
)
6597 < memory_move_cost (mode
, rclass
, true))
6598 && (secondary_reload_class (1, rclass
, mode
,
6601 #ifdef SECONDARY_MEMORY_NEEDED
6602 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6607 && (rld
[r
].nregs
== max_group_size
6608 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6610 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6611 rld
[r
].when_needed
, rld
[r
].in
,
6614 /* If a group is needed, verify that all the subsequent
6615 registers still have their values intact. */
6616 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6619 for (k
= 1; k
< nr
; k
++)
6620 if (reg_reloaded_contents
[i
+ k
] != regno
6621 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6629 last_reg
= (GET_MODE (last_reg
) == mode
6630 ? last_reg
: gen_rtx_REG (mode
, i
));
6633 for (k
= 0; k
< nr
; k
++)
6634 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6637 /* We found a register that contains the
6638 value we need. If this register is the
6639 same as an `earlyclobber' operand of the
6640 current insn, just mark it as a place to
6641 reload from since we can't use it as the
6642 reload register itself. */
6644 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6645 if (reg_overlap_mentioned_for_reload_p
6646 (reg_last_reload_reg
[regno
],
6647 reload_earlyclobbers
[i1
]))
6650 if (i1
!= n_earlyclobbers
6651 || ! (free_for_value_p (i
, rld
[r
].mode
,
6653 rld
[r
].when_needed
, rld
[r
].in
,
6655 /* Don't use it if we'd clobber a pseudo reg. */
6656 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6658 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6659 /* Don't clobber the frame pointer. */
6660 || (i
== HARD_FRAME_POINTER_REGNUM
6661 && frame_pointer_needed
6663 /* Don't really use the inherited spill reg
6664 if we need it wider than we've got it. */
6665 || paradoxical_subreg_p (rld
[r
].mode
, mode
)
6668 /* If find_reloads chose reload_out as reload
6669 register, stay with it - that leaves the
6670 inherited register for subsequent reloads. */
6671 || (rld
[r
].out
&& rld
[r
].reg_rtx
6672 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6674 if (! rld
[r
].optional
)
6676 reload_override_in
[r
] = last_reg
;
6677 reload_inheritance_insn
[r
]
6678 = reg_reloaded_insn
[i
];
6684 /* We can use this as a reload reg. */
6685 /* Mark the register as in use for this part of
6687 mark_reload_reg_in_use (i
,
6691 rld
[r
].reg_rtx
= last_reg
;
6692 reload_inherited
[r
] = 1;
6693 reload_inheritance_insn
[r
]
6694 = reg_reloaded_insn
[i
];
6695 reload_spill_index
[r
] = i
;
6696 for (k
= 0; k
< nr
; k
++)
6697 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6705 /* Here's another way to see if the value is already lying around. */
6708 && ! reload_inherited
[r
]
6710 && (CONSTANT_P (rld
[r
].in
)
6711 || GET_CODE (rld
[r
].in
) == PLUS
6712 || REG_P (rld
[r
].in
)
6713 || MEM_P (rld
[r
].in
))
6714 && (rld
[r
].nregs
== max_group_size
6715 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6716 search_equiv
= rld
[r
].in
;
6721 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6722 -1, NULL
, 0, rld
[r
].mode
);
6728 regno
= REGNO (equiv
);
6731 /* This must be a SUBREG of a hard register.
6732 Make a new REG since this might be used in an
6733 address and not all machines support SUBREGs
6735 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6736 regno
= subreg_regno (equiv
);
6737 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6738 /* If we choose EQUIV as the reload register, but the
6739 loop below decides to cancel the inheritance, we'll
6740 end up reloading EQUIV in rld[r].mode, not the mode
6741 it had originally. That isn't safe when EQUIV isn't
6742 available as a spill register since its value might
6743 still be live at this point. */
6744 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6745 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6750 /* If we found a spill reg, reject it unless it is free
6751 and of the desired class. */
6755 int bad_for_class
= 0;
6756 int max_regno
= regno
+ rld
[r
].nregs
;
6758 for (i
= regno
; i
< max_regno
; i
++)
6760 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6762 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6767 && ! free_for_value_p (regno
, rld
[r
].mode
,
6768 rld
[r
].opnum
, rld
[r
].when_needed
,
6769 rld
[r
].in
, rld
[r
].out
, r
, 1))
6774 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6777 /* We found a register that contains the value we need.
6778 If this register is the same as an `earlyclobber' operand
6779 of the current insn, just mark it as a place to reload from
6780 since we can't use it as the reload register itself. */
6783 for (i
= 0; i
< n_earlyclobbers
; i
++)
6784 if (reg_overlap_mentioned_for_reload_p (equiv
,
6785 reload_earlyclobbers
[i
]))
6787 if (! rld
[r
].optional
)
6788 reload_override_in
[r
] = equiv
;
6793 /* If the equiv register we have found is explicitly clobbered
6794 in the current insn, it depends on the reload type if we
6795 can use it, use it for reload_override_in, or not at all.
6796 In particular, we then can't use EQUIV for a
6797 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6801 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6802 switch (rld
[r
].when_needed
)
6804 case RELOAD_FOR_OTHER_ADDRESS
:
6805 case RELOAD_FOR_INPADDR_ADDRESS
:
6806 case RELOAD_FOR_INPUT_ADDRESS
:
6807 case RELOAD_FOR_OPADDR_ADDR
:
6810 case RELOAD_FOR_INPUT
:
6811 case RELOAD_FOR_OPERAND_ADDRESS
:
6812 if (! rld
[r
].optional
)
6813 reload_override_in
[r
] = equiv
;
6819 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6820 switch (rld
[r
].when_needed
)
6822 case RELOAD_FOR_OTHER_ADDRESS
:
6823 case RELOAD_FOR_INPADDR_ADDRESS
:
6824 case RELOAD_FOR_INPUT_ADDRESS
:
6825 case RELOAD_FOR_OPADDR_ADDR
:
6826 case RELOAD_FOR_OPERAND_ADDRESS
:
6827 case RELOAD_FOR_INPUT
:
6830 if (! rld
[r
].optional
)
6831 reload_override_in
[r
] = equiv
;
6839 /* If we found an equivalent reg, say no code need be generated
6840 to load it, and use it as our reload reg. */
6842 && (regno
!= HARD_FRAME_POINTER_REGNUM
6843 || !frame_pointer_needed
))
6845 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6847 rld
[r
].reg_rtx
= equiv
;
6848 reload_spill_index
[r
] = regno
;
6849 reload_inherited
[r
] = 1;
6851 /* If reg_reloaded_valid is not set for this register,
6852 there might be a stale spill_reg_store lying around.
6853 We must clear it, since otherwise emit_reload_insns
6854 might delete the store. */
6855 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6856 spill_reg_store
[regno
] = NULL
;
6857 /* If any of the hard registers in EQUIV are spill
6858 registers, mark them as in use for this insn. */
6859 for (k
= 0; k
< nr
; k
++)
6861 i
= spill_reg_order
[regno
+ k
];
6864 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6867 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6874 /* If we found a register to use already, or if this is an optional
6875 reload, we are done. */
6876 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6880 /* No longer needed for correct operation. Might or might
6881 not give better code on the average. Want to experiment? */
6883 /* See if there is a later reload that has a class different from our
6884 class that intersects our class or that requires less register
6885 than our reload. If so, we must allocate a register to this
6886 reload now, since that reload might inherit a previous reload
6887 and take the only available register in our class. Don't do this
6888 for optional reloads since they will force all previous reloads
6889 to be allocated. Also don't do this for reloads that have been
6892 for (i
= j
+ 1; i
< n_reloads
; i
++)
6894 int s
= reload_order
[i
];
6896 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6897 && ! rld
[s
].secondary_p
)
6901 if ((rld
[s
].rclass
!= rld
[r
].rclass
6902 && reg_classes_intersect_p (rld
[r
].rclass
,
6904 || rld
[s
].nregs
< rld
[r
].nregs
)
6911 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6915 /* Now allocate reload registers for anything non-optional that
6916 didn't get one yet. */
6917 for (j
= 0; j
< n_reloads
; j
++)
6919 int r
= reload_order
[j
];
6921 /* Ignore reloads that got marked inoperative. */
6922 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6925 /* Skip reloads that already have a register allocated or are
6927 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6930 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6934 /* If that loop got all the way, we have won. */
6941 /* Loop around and try without any inheritance. */
6946 /* First undo everything done by the failed attempt
6947 to allocate with inheritance. */
6948 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6950 /* Some sanity tests to verify that the reloads found in the first
6951 pass are identical to the ones we have now. */
6952 gcc_assert (chain
->n_reloads
== n_reloads
);
6954 for (i
= 0; i
< n_reloads
; i
++)
6956 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6958 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6959 for (j
= 0; j
< n_spills
; j
++)
6960 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6961 if (! set_reload_reg (j
, i
))
6962 failed_reload (chain
->insn
, i
);
6966 /* If we thought we could inherit a reload, because it seemed that
6967 nothing else wanted the same reload register earlier in the insn,
6968 verify that assumption, now that all reloads have been assigned.
6969 Likewise for reloads where reload_override_in has been set. */
6971 /* If doing expensive optimizations, do one preliminary pass that doesn't
6972 cancel any inheritance, but removes reloads that have been needed only
6973 for reloads that we know can be inherited. */
6974 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6976 for (j
= 0; j
< n_reloads
; j
++)
6978 int r
= reload_order
[j
];
6980 #ifdef SECONDARY_MEMORY_NEEDED
6983 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6984 check_reg
= rld
[r
].reg_rtx
;
6985 else if (reload_override_in
[r
]
6986 && (REG_P (reload_override_in
[r
])
6987 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6988 check_reg
= reload_override_in
[r
];
6991 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6992 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6993 (reload_inherited
[r
]
6994 ? rld
[r
].out
: const0_rtx
),
6999 reload_inherited
[r
] = 0;
7000 reload_override_in
[r
] = 0;
7002 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7003 reload_override_in, then we do not need its related
7004 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7005 likewise for other reload types.
7006 We handle this by removing a reload when its only replacement
7007 is mentioned in reload_in of the reload we are going to inherit.
7008 A special case are auto_inc expressions; even if the input is
7009 inherited, we still need the address for the output. We can
7010 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7011 If we succeeded removing some reload and we are doing a preliminary
7012 pass just to remove such reloads, make another pass, since the
7013 removal of one reload might allow us to inherit another one. */
7015 && rld
[r
].out
!= rld
[r
].in
7016 && remove_address_replacements (rld
[r
].in
))
7021 #ifdef SECONDARY_MEMORY_NEEDED
7022 /* If we needed a memory location for the reload, we also have to
7023 remove its related reloads. */
7025 && rld
[r
].out
!= rld
[r
].in
7026 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
7027 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
7028 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem
)),
7029 rld
[r
].rclass
, rld
[r
].inmode
)
7030 && remove_address_replacements
7031 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
7032 rld
[r
].when_needed
)))
7041 /* Now that reload_override_in is known valid,
7042 actually override reload_in. */
7043 for (j
= 0; j
< n_reloads
; j
++)
7044 if (reload_override_in
[j
])
7045 rld
[j
].in
= reload_override_in
[j
];
7047 /* If this reload won't be done because it has been canceled or is
7048 optional and not inherited, clear reload_reg_rtx so other
7049 routines (such as subst_reloads) don't get confused. */
7050 for (j
= 0; j
< n_reloads
; j
++)
7051 if (rld
[j
].reg_rtx
!= 0
7052 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7053 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7054 && ! rld
[j
].secondary_p
)))
7056 int regno
= true_regnum (rld
[j
].reg_rtx
);
7058 if (spill_reg_order
[regno
] >= 0)
7059 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7060 rld
[j
].when_needed
, rld
[j
].mode
);
7062 reload_spill_index
[j
] = -1;
7065 /* Record which pseudos and which spill regs have output reloads. */
7066 for (j
= 0; j
< n_reloads
; j
++)
7068 int r
= reload_order
[j
];
7070 i
= reload_spill_index
[r
];
7072 /* I is nonneg if this reload uses a register.
7073 If rld[r].reg_rtx is 0, this is an optional reload
7074 that we opted to ignore. */
7075 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7076 && rld
[r
].reg_rtx
!= 0)
7078 int nregno
= REGNO (rld
[r
].out_reg
);
7081 if (nregno
< FIRST_PSEUDO_REGISTER
)
7082 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7085 SET_REGNO_REG_SET (®_has_output_reload
,
7089 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7091 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7092 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7093 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7098 /* Deallocate the reload register for reload R. This is called from
7099 remove_address_replacements. */
7102 deallocate_reload_reg (int r
)
7106 if (! rld
[r
].reg_rtx
)
7108 regno
= true_regnum (rld
[r
].reg_rtx
);
7110 if (spill_reg_order
[regno
] >= 0)
7111 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7113 reload_spill_index
[r
] = -1;
7116 /* These arrays are filled by emit_reload_insns and its subroutines. */
7117 static rtx_insn
*input_reload_insns
[MAX_RECOG_OPERANDS
];
7118 static rtx_insn
*other_input_address_reload_insns
= 0;
7119 static rtx_insn
*other_input_reload_insns
= 0;
7120 static rtx_insn
*input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7121 static rtx_insn
*inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7122 static rtx_insn
*output_reload_insns
[MAX_RECOG_OPERANDS
];
7123 static rtx_insn
*output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7124 static rtx_insn
*outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7125 static rtx_insn
*operand_reload_insns
= 0;
7126 static rtx_insn
*other_operand_reload_insns
= 0;
7127 static rtx_insn
*other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7129 /* Values to be put in spill_reg_store are put here first. Instructions
7130 must only be placed here if the associated reload register reaches
7131 the end of the instruction's reload sequence. */
7132 static rtx_insn
*new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7133 static HARD_REG_SET reg_reloaded_died
;
7135 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7136 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7137 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7138 adjusted register, and return true. Otherwise, return false. */
7140 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7141 enum reg_class new_class
,
7142 machine_mode new_mode
)
7147 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7149 unsigned regno
= REGNO (reg
);
7151 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7153 if (GET_MODE (reg
) != new_mode
)
7155 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7157 if (hard_regno_nregs
[regno
][new_mode
]
7158 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7160 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7168 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7169 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7170 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7171 adjusted register, and return true. Otherwise, return false. */
7173 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7174 enum insn_code icode
)
7177 enum reg_class new_class
= scratch_reload_class (icode
);
7178 machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7180 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7181 new_class
, new_mode
);
7184 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7185 has the number J. OLD contains the value to be used as input. */
7188 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7191 rtx_insn
*insn
= chain
->insn
;
7193 rtx oldequiv_reg
= 0;
7199 /* delete_output_reload is only invoked properly if old contains
7200 the original pseudo register. Since this is replaced with a
7201 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7202 find the pseudo in RELOAD_IN_REG. This is also used to
7203 determine whether a secondary reload is needed. */
7204 if (reload_override_in
[j
]
7205 && (REG_P (rl
->in_reg
)
7206 || (GET_CODE (rl
->in_reg
) == SUBREG
7207 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7214 else if (REG_P (oldequiv
))
7215 oldequiv_reg
= oldequiv
;
7216 else if (GET_CODE (oldequiv
) == SUBREG
)
7217 oldequiv_reg
= SUBREG_REG (oldequiv
);
7219 reloadreg
= reload_reg_rtx_for_input
[j
];
7220 mode
= GET_MODE (reloadreg
);
7222 /* If we are reloading from a register that was recently stored in
7223 with an output-reload, see if we can prove there was
7224 actually no need to store the old value in it. */
7226 if (optimize
&& REG_P (oldequiv
)
7227 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7228 && spill_reg_store
[REGNO (oldequiv
)]
7230 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7231 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7233 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7235 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7238 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7239 oldequiv
= SUBREG_REG (oldequiv
);
7240 if (GET_MODE (oldequiv
) != VOIDmode
7241 && mode
!= GET_MODE (oldequiv
))
7242 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7244 /* Switch to the right place to emit the reload insns. */
7245 switch (rl
->when_needed
)
7248 where
= &other_input_reload_insns
;
7250 case RELOAD_FOR_INPUT
:
7251 where
= &input_reload_insns
[rl
->opnum
];
7253 case RELOAD_FOR_INPUT_ADDRESS
:
7254 where
= &input_address_reload_insns
[rl
->opnum
];
7256 case RELOAD_FOR_INPADDR_ADDRESS
:
7257 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7259 case RELOAD_FOR_OUTPUT_ADDRESS
:
7260 where
= &output_address_reload_insns
[rl
->opnum
];
7262 case RELOAD_FOR_OUTADDR_ADDRESS
:
7263 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7265 case RELOAD_FOR_OPERAND_ADDRESS
:
7266 where
= &operand_reload_insns
;
7268 case RELOAD_FOR_OPADDR_ADDR
:
7269 where
= &other_operand_reload_insns
;
7271 case RELOAD_FOR_OTHER_ADDRESS
:
7272 where
= &other_input_address_reload_insns
;
7278 push_to_sequence (*where
);
7280 /* Auto-increment addresses must be reloaded in a special way. */
7281 if (rl
->out
&& ! rl
->out_reg
)
7283 /* We are not going to bother supporting the case where a
7284 incremented register can't be copied directly from
7285 OLDEQUIV since this seems highly unlikely. */
7286 gcc_assert (rl
->secondary_in_reload
< 0);
7288 if (reload_inherited
[j
])
7289 oldequiv
= reloadreg
;
7291 old
= XEXP (rl
->in_reg
, 0);
7293 /* Prevent normal processing of this reload. */
7295 /* Output a special code sequence for this case. */
7296 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7299 /* If we are reloading a pseudo-register that was set by the previous
7300 insn, see if we can get rid of that pseudo-register entirely
7301 by redirecting the previous insn into our reload register. */
7303 else if (optimize
&& REG_P (old
)
7304 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7305 && dead_or_set_p (insn
, old
)
7306 /* This is unsafe if some other reload
7307 uses the same reg first. */
7308 && ! conflicts_with_override (reloadreg
)
7309 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7310 rl
->when_needed
, old
, rl
->out
, j
, 0))
7312 rtx_insn
*temp
= PREV_INSN (insn
);
7313 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7314 temp
= PREV_INSN (temp
);
7316 && NONJUMP_INSN_P (temp
)
7317 && GET_CODE (PATTERN (temp
)) == SET
7318 && SET_DEST (PATTERN (temp
)) == old
7319 /* Make sure we can access insn_operand_constraint. */
7320 && asm_noperands (PATTERN (temp
)) < 0
7321 /* This is unsafe if operand occurs more than once in current
7322 insn. Perhaps some occurrences aren't reloaded. */
7323 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7325 rtx old
= SET_DEST (PATTERN (temp
));
7326 /* Store into the reload register instead of the pseudo. */
7327 SET_DEST (PATTERN (temp
)) = reloadreg
;
7329 /* Verify that resulting insn is valid.
7331 Note that we have replaced the destination of TEMP with
7332 RELOADREG. If TEMP references RELOADREG within an
7333 autoincrement addressing mode, then the resulting insn
7334 is ill-formed and we must reject this optimization. */
7335 extract_insn (temp
);
7336 if (constrain_operands (1, get_enabled_alternatives (temp
))
7337 && (!AUTO_INC_DEC
|| ! find_reg_note (temp
, REG_INC
, reloadreg
)))
7339 /* If the previous insn is an output reload, the source is
7340 a reload register, and its spill_reg_store entry will
7341 contain the previous destination. This is now
7343 if (REG_P (SET_SRC (PATTERN (temp
)))
7344 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7346 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7347 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7350 /* If these are the only uses of the pseudo reg,
7351 pretend for GDB it lives in the reload reg we used. */
7352 if (REG_N_DEATHS (REGNO (old
)) == 1
7353 && REG_N_SETS (REGNO (old
)) == 1)
7355 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7356 if (ira_conflicts_p
)
7357 /* Inform IRA about the change. */
7358 ira_mark_allocation_change (REGNO (old
));
7359 alter_reg (REGNO (old
), -1, false);
7363 /* Adjust any debug insns between temp and insn. */
7364 while ((temp
= NEXT_INSN (temp
)) != insn
)
7365 if (DEBUG_INSN_P (temp
))
7366 INSN_VAR_LOCATION_LOC (temp
)
7367 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp
),
7370 gcc_assert (NOTE_P (temp
));
7374 SET_DEST (PATTERN (temp
)) = old
;
7379 /* We can't do that, so output an insn to load RELOADREG. */
7381 /* If we have a secondary reload, pick up the secondary register
7382 and icode, if any. If OLDEQUIV and OLD are different or
7383 if this is an in-out reload, recompute whether or not we
7384 still need a secondary register and what the icode should
7385 be. If we still need a secondary register and the class or
7386 icode is different, go back to reloading from OLD if using
7387 OLDEQUIV means that we got the wrong type of register. We
7388 cannot have different class or icode due to an in-out reload
7389 because we don't make such reloads when both the input and
7390 output need secondary reload registers. */
7392 if (! special
&& rl
->secondary_in_reload
>= 0)
7394 rtx second_reload_reg
= 0;
7395 rtx third_reload_reg
= 0;
7396 int secondary_reload
= rl
->secondary_in_reload
;
7397 rtx real_oldequiv
= oldequiv
;
7400 enum insn_code icode
;
7401 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7403 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7404 and similarly for OLD.
7405 See comments in get_secondary_reload in reload.c. */
7406 /* If it is a pseudo that cannot be replaced with its
7407 equivalent MEM, we must fall back to reload_in, which
7408 will have all the necessary substitutions registered.
7409 Likewise for a pseudo that can't be replaced with its
7410 equivalent constant.
7412 Take extra care for subregs of such pseudos. Note that
7413 we cannot use reg_equiv_mem in this case because it is
7414 not in the right mode. */
7417 if (GET_CODE (tmp
) == SUBREG
)
7418 tmp
= SUBREG_REG (tmp
);
7420 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7421 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7422 || reg_equiv_constant (REGNO (tmp
)) != 0))
7424 if (! reg_equiv_mem (REGNO (tmp
))
7425 || num_not_at_initial_offset
7426 || GET_CODE (oldequiv
) == SUBREG
)
7427 real_oldequiv
= rl
->in
;
7429 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7433 if (GET_CODE (tmp
) == SUBREG
)
7434 tmp
= SUBREG_REG (tmp
);
7436 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7437 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7438 || reg_equiv_constant (REGNO (tmp
)) != 0))
7440 if (! reg_equiv_mem (REGNO (tmp
))
7441 || num_not_at_initial_offset
7442 || GET_CODE (old
) == SUBREG
)
7445 real_old
= reg_equiv_mem (REGNO (tmp
));
7448 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7449 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7451 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7453 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7454 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7455 /* We'd have to add more code for quartary reloads. */
7456 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7458 icode
= rl
->secondary_in_icode
;
7460 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7461 || (rl
->in
!= 0 && rl
->out
!= 0))
7463 secondary_reload_info sri
, sri2
;
7464 enum reg_class new_class
, new_t_class
;
7466 sri
.icode
= CODE_FOR_nothing
;
7467 sri
.prev_sri
= NULL
;
7469 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7473 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7474 second_reload_reg
= 0;
7475 else if (new_class
== NO_REGS
)
7477 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7479 (enum insn_code
) sri
.icode
))
7481 icode
= (enum insn_code
) sri
.icode
;
7482 third_reload_reg
= 0;
7487 real_oldequiv
= real_old
;
7490 else if (sri
.icode
!= CODE_FOR_nothing
)
7491 /* We currently lack a way to express this in reloads. */
7495 sri2
.icode
= CODE_FOR_nothing
;
7496 sri2
.prev_sri
= &sri
;
7498 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7501 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7503 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7507 third_reload_reg
= 0;
7508 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7513 real_oldequiv
= real_old
;
7516 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7518 rtx intermediate
= second_reload_reg
;
7520 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7522 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7526 second_reload_reg
= intermediate
;
7527 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7532 real_oldequiv
= real_old
;
7535 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7537 rtx intermediate
= second_reload_reg
;
7539 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7541 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7544 second_reload_reg
= intermediate
;
7545 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7550 real_oldequiv
= real_old
;
7555 /* This could be handled more intelligently too. */
7557 real_oldequiv
= real_old
;
7562 /* If we still need a secondary reload register, check
7563 to see if it is being used as a scratch or intermediate
7564 register and generate code appropriately. If we need
7565 a scratch register, use REAL_OLDEQUIV since the form of
7566 the insn may depend on the actual address if it is
7569 if (second_reload_reg
)
7571 if (icode
!= CODE_FOR_nothing
)
7573 /* We'd have to add extra code to handle this case. */
7574 gcc_assert (!third_reload_reg
);
7576 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7577 second_reload_reg
));
7582 /* See if we need a scratch register to load the
7583 intermediate register (a tertiary reload). */
7584 if (tertiary_icode
!= CODE_FOR_nothing
)
7586 emit_insn ((GEN_FCN (tertiary_icode
)
7587 (second_reload_reg
, real_oldequiv
,
7588 third_reload_reg
)));
7590 else if (third_reload_reg
)
7592 gen_reload (third_reload_reg
, real_oldequiv
,
7595 gen_reload (second_reload_reg
, third_reload_reg
,
7600 gen_reload (second_reload_reg
, real_oldequiv
,
7604 oldequiv
= second_reload_reg
;
7609 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7611 rtx real_oldequiv
= oldequiv
;
7613 if ((REG_P (oldequiv
)
7614 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7615 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7616 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7617 || (GET_CODE (oldequiv
) == SUBREG
7618 && REG_P (SUBREG_REG (oldequiv
))
7619 && (REGNO (SUBREG_REG (oldequiv
))
7620 >= FIRST_PSEUDO_REGISTER
)
7621 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7622 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7623 || (CONSTANT_P (oldequiv
)
7624 && (targetm
.preferred_reload_class (oldequiv
,
7625 REGNO_REG_CLASS (REGNO (reloadreg
)))
7627 real_oldequiv
= rl
->in
;
7628 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7632 if (cfun
->can_throw_non_call_exceptions
)
7633 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7635 /* End this sequence. */
7636 *where
= get_insns ();
7639 /* Update reload_override_in so that delete_address_reloads_1
7640 can see the actual register usage. */
7642 reload_override_in
[j
] = oldequiv
;
7645 /* Generate insns to for the output reload RL, which is for the insn described
7646 by CHAIN and has the number J. */
7648 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7652 rtx_insn
*insn
= chain
->insn
;
7659 if (rl
->when_needed
== RELOAD_OTHER
)
7662 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7664 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7665 mode
= GET_MODE (rl_reg_rtx
);
7667 reloadreg
= rl_reg_rtx
;
7669 /* If we need two reload regs, set RELOADREG to the intermediate
7670 one, since it will be stored into OLD. We might need a secondary
7671 register only for an input reload, so check again here. */
7673 if (rl
->secondary_out_reload
>= 0)
7676 int secondary_reload
= rl
->secondary_out_reload
;
7677 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7679 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7680 && reg_equiv_mem (REGNO (old
)) != 0)
7681 real_old
= reg_equiv_mem (REGNO (old
));
7683 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7685 rtx second_reloadreg
= reloadreg
;
7686 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7688 /* See if RELOADREG is to be used as a scratch register
7689 or as an intermediate register. */
7690 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7692 /* We'd have to add extra code to handle this case. */
7693 gcc_assert (tertiary_reload
< 0);
7695 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7696 (real_old
, second_reloadreg
, reloadreg
)));
7701 /* See if we need both a scratch and intermediate reload
7704 enum insn_code tertiary_icode
7705 = rld
[secondary_reload
].secondary_out_icode
;
7707 /* We'd have to add more code for quartary reloads. */
7708 gcc_assert (tertiary_reload
< 0
7709 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7711 if (GET_MODE (reloadreg
) != mode
)
7712 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7714 if (tertiary_icode
!= CODE_FOR_nothing
)
7716 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7718 /* Copy primary reload reg to secondary reload reg.
7719 (Note that these have been swapped above, then
7720 secondary reload reg to OLD using our insn.) */
7722 /* If REAL_OLD is a paradoxical SUBREG, remove it
7723 and try to put the opposite SUBREG on
7725 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7727 gen_reload (reloadreg
, second_reloadreg
,
7728 rl
->opnum
, rl
->when_needed
);
7729 emit_insn ((GEN_FCN (tertiary_icode
)
7730 (real_old
, reloadreg
, third_reloadreg
)));
7736 /* Copy between the reload regs here and then to
7739 gen_reload (reloadreg
, second_reloadreg
,
7740 rl
->opnum
, rl
->when_needed
);
7741 if (tertiary_reload
>= 0)
7743 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7745 gen_reload (third_reloadreg
, reloadreg
,
7746 rl
->opnum
, rl
->when_needed
);
7747 reloadreg
= third_reloadreg
;
7754 /* Output the last reload insn. */
7759 /* Don't output the last reload if OLD is not the dest of
7760 INSN and is in the src and is clobbered by INSN. */
7761 if (! flag_expensive_optimizations
7763 || !(set
= single_set (insn
))
7764 || rtx_equal_p (old
, SET_DEST (set
))
7765 || !reg_mentioned_p (old
, SET_SRC (set
))
7766 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7767 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7768 gen_reload (old
, reloadreg
, rl
->opnum
,
7772 /* Look at all insns we emitted, just to be safe. */
7773 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7776 rtx pat
= PATTERN (p
);
7778 /* If this output reload doesn't come from a spill reg,
7779 clear any memory of reloaded copies of the pseudo reg.
7780 If this output reload comes from a spill reg,
7781 reg_has_output_reload will make this do nothing. */
7782 note_stores (pat
, forget_old_reloads_1
, NULL
);
7784 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7786 rtx set
= single_set (insn
);
7787 if (reload_spill_index
[j
] < 0
7789 && SET_SRC (set
) == rl_reg_rtx
)
7791 int src
= REGNO (SET_SRC (set
));
7793 reload_spill_index
[j
] = src
;
7794 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7795 if (find_regno_note (insn
, REG_DEAD
, src
))
7796 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7798 if (HARD_REGISTER_P (rl_reg_rtx
))
7800 int s
= rl
->secondary_out_reload
;
7801 set
= single_set (p
);
7802 /* If this reload copies only to the secondary reload
7803 register, the secondary reload does the actual
7805 if (s
>= 0 && set
== NULL_RTX
)
7806 /* We can't tell what function the secondary reload
7807 has and where the actual store to the pseudo is
7808 made; leave new_spill_reg_store alone. */
7811 && SET_SRC (set
) == rl_reg_rtx
7812 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7814 /* Usually the next instruction will be the
7815 secondary reload insn; if we can confirm
7816 that it is, setting new_spill_reg_store to
7817 that insn will allow an extra optimization. */
7818 rtx s_reg
= rld
[s
].reg_rtx
;
7819 rtx_insn
*next
= NEXT_INSN (p
);
7820 rld
[s
].out
= rl
->out
;
7821 rld
[s
].out_reg
= rl
->out_reg
;
7822 set
= single_set (next
);
7823 if (set
&& SET_SRC (set
) == s_reg
7824 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7826 SET_HARD_REG_BIT (reg_is_output_reload
,
7828 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7831 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7832 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7837 if (rl
->when_needed
== RELOAD_OTHER
)
7839 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7840 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7843 output_reload_insns
[rl
->opnum
] = get_insns ();
7845 if (cfun
->can_throw_non_call_exceptions
)
7846 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7851 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7852 and has the number J. */
7854 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7856 rtx_insn
*insn
= chain
->insn
;
7857 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7858 ? rl
->in_reg
: rl
->in
);
7859 rtx reg_rtx
= rl
->reg_rtx
;
7865 /* Determine the mode to reload in.
7866 This is very tricky because we have three to choose from.
7867 There is the mode the insn operand wants (rl->inmode).
7868 There is the mode of the reload register RELOADREG.
7869 There is the intrinsic mode of the operand, which we could find
7870 by stripping some SUBREGs.
7871 It turns out that RELOADREG's mode is irrelevant:
7872 we can change that arbitrarily.
7874 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7875 then the reload reg may not support QImode moves, so use SImode.
7876 If foo is in memory due to spilling a pseudo reg, this is safe,
7877 because the QImode value is in the least significant part of a
7878 slot big enough for a SImode. If foo is some other sort of
7879 memory reference, then it is impossible to reload this case,
7880 so previous passes had better make sure this never happens.
7882 Then consider a one-word union which has SImode and one of its
7883 members is a float, being fetched as (SUBREG:SF union:SI).
7884 We must fetch that as SFmode because we could be loading into
7885 a float-only register. In this case OLD's mode is correct.
7887 Consider an immediate integer: it has VOIDmode. Here we need
7888 to get a mode from something else.
7890 In some cases, there is a fourth mode, the operand's
7891 containing mode. If the insn specifies a containing mode for
7892 this operand, it overrides all others.
7894 I am not sure whether the algorithm here is always right,
7895 but it does the right things in those cases. */
7897 mode
= GET_MODE (old
);
7898 if (mode
== VOIDmode
)
7901 /* We cannot use gen_lowpart_common since it can do the wrong thing
7902 when REG_RTX has a multi-word mode. Note that REG_RTX must
7903 always be a REG here. */
7904 if (GET_MODE (reg_rtx
) != mode
)
7905 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7907 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7910 /* AUTO_INC reloads need to be handled even if inherited. We got an
7911 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7912 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7913 && ! rtx_equal_p (reg_rtx
, old
)
7915 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7917 /* When inheriting a wider reload, we have a MEM in rl->in,
7918 e.g. inheriting a SImode output reload for
7919 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7920 if (optimize
&& reload_inherited
[j
] && rl
->in
7922 && MEM_P (rl
->in_reg
)
7923 && reload_spill_index
[j
] >= 0
7924 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7925 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7927 /* If we are reloading a register that was recently stored in with an
7928 output-reload, see if we can prove there was
7929 actually no need to store the old value in it. */
7932 && (reload_inherited
[j
] || reload_override_in
[j
])
7935 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7937 /* There doesn't seem to be any reason to restrict this to pseudos
7938 and doing so loses in the case where we are copying from a
7939 register of the wrong class. */
7940 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7942 /* The insn might have already some references to stackslots
7943 replaced by MEMs, while reload_out_reg still names the
7945 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7946 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7947 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7950 /* Do output reloading for reload RL, which is for the insn described by
7951 CHAIN and has the number J.
7952 ??? At some point we need to support handling output reloads of
7953 JUMP_INSNs or insns that set cc0. */
7955 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7958 rtx_insn
*insn
= chain
->insn
;
7959 /* If this is an output reload that stores something that is
7960 not loaded in this same reload, see if we can eliminate a previous
7962 rtx pseudo
= rl
->out_reg
;
7963 rtx reg_rtx
= rl
->reg_rtx
;
7965 if (rl
->out
&& reg_rtx
)
7969 /* Determine the mode to reload in.
7970 See comments above (for input reloading). */
7971 mode
= GET_MODE (rl
->out
);
7972 if (mode
== VOIDmode
)
7974 /* VOIDmode should never happen for an output. */
7975 if (asm_noperands (PATTERN (insn
)) < 0)
7976 /* It's the compiler's fault. */
7977 fatal_insn ("VOIDmode on an output", insn
);
7978 error_for_asm (insn
, "output operand is constant in %<asm%>");
7979 /* Prevent crash--use something we know is valid. */
7981 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7983 if (GET_MODE (reg_rtx
) != mode
)
7984 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7986 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7991 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7992 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7993 && reg_last_reload_reg
[REGNO (pseudo
)])
7995 int pseudo_no
= REGNO (pseudo
);
7996 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7998 /* We don't need to test full validity of last_regno for
7999 inherit here; we only want to know if the store actually
8000 matches the pseudo. */
8001 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
8002 && reg_reloaded_contents
[last_regno
] == pseudo_no
8003 && spill_reg_store
[last_regno
]
8004 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
8005 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
8011 || rtx_equal_p (old
, reg_rtx
))
8014 /* An output operand that dies right away does need a reload,
8015 but need not be copied from it. Show the new location in the
8017 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
8018 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
8020 XEXP (note
, 0) = reg_rtx
;
8023 /* Likewise for a SUBREG of an operand that dies. */
8024 else if (GET_CODE (old
) == SUBREG
8025 && REG_P (SUBREG_REG (old
))
8026 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
8029 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
8032 else if (GET_CODE (old
) == SCRATCH
)
8033 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8034 but we don't want to make an output reload. */
8037 /* If is a JUMP_INSN, we can't support output reloads yet. */
8038 gcc_assert (NONJUMP_INSN_P (insn
));
8040 emit_output_reload_insns (chain
, rld
+ j
, j
);
8043 /* A reload copies values of MODE from register SRC to register DEST.
8044 Return true if it can be treated for inheritance purposes like a
8045 group of reloads, each one reloading a single hard register. The
8046 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8047 occupy the same number of hard registers. */
8050 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8051 int src ATTRIBUTE_UNUSED
,
8052 machine_mode mode ATTRIBUTE_UNUSED
)
8054 #ifdef CANNOT_CHANGE_MODE_CLASS
8055 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8056 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8062 /* Output insns to reload values in and out of the chosen reload regs. */
8065 emit_reload_insns (struct insn_chain
*chain
)
8067 rtx_insn
*insn
= chain
->insn
;
8071 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8073 for (j
= 0; j
< reload_n_operands
; j
++)
8074 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8075 = inpaddr_address_reload_insns
[j
]
8076 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8077 = outaddr_address_reload_insns
[j
]
8078 = other_output_reload_insns
[j
] = 0;
8079 other_input_address_reload_insns
= 0;
8080 other_input_reload_insns
= 0;
8081 operand_reload_insns
= 0;
8082 other_operand_reload_insns
= 0;
8084 /* Dump reloads into the dump file. */
8087 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8088 debug_reload_to_stream (dump_file
);
8091 for (j
= 0; j
< n_reloads
; j
++)
8092 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8096 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8097 new_spill_reg_store
[i
] = 0;
8100 /* Now output the instructions to copy the data into and out of the
8101 reload registers. Do these in the order that the reloads were reported,
8102 since reloads of base and index registers precede reloads of operands
8103 and the operands may need the base and index registers reloaded. */
8105 for (j
= 0; j
< n_reloads
; j
++)
8107 do_input_reload (chain
, rld
+ j
, j
);
8108 do_output_reload (chain
, rld
+ j
, j
);
8111 /* Now write all the insns we made for reloads in the order expected by
8112 the allocation functions. Prior to the insn being reloaded, we write
8113 the following reloads:
8115 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8117 RELOAD_OTHER reloads.
8119 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8120 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8121 RELOAD_FOR_INPUT reload for the operand.
8123 RELOAD_FOR_OPADDR_ADDRS reloads.
8125 RELOAD_FOR_OPERAND_ADDRESS reloads.
8127 After the insn being reloaded, we write the following:
8129 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8130 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8131 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8132 reloads for the operand. The RELOAD_OTHER output reloads are
8133 output in descending order by reload number. */
8135 emit_insn_before (other_input_address_reload_insns
, insn
);
8136 emit_insn_before (other_input_reload_insns
, insn
);
8138 for (j
= 0; j
< reload_n_operands
; j
++)
8140 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8141 emit_insn_before (input_address_reload_insns
[j
], insn
);
8142 emit_insn_before (input_reload_insns
[j
], insn
);
8145 emit_insn_before (other_operand_reload_insns
, insn
);
8146 emit_insn_before (operand_reload_insns
, insn
);
8148 for (j
= 0; j
< reload_n_operands
; j
++)
8150 rtx_insn
*x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8151 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8152 x
= emit_insn_after (output_reload_insns
[j
], x
);
8153 emit_insn_after (other_output_reload_insns
[j
], x
);
8156 /* For all the spill regs newly reloaded in this instruction,
8157 record what they were reloaded from, so subsequent instructions
8158 can inherit the reloads.
8160 Update spill_reg_store for the reloads of this insn.
8161 Copy the elements that were updated in the loop above. */
8163 for (j
= 0; j
< n_reloads
; j
++)
8165 int r
= reload_order
[j
];
8166 int i
= reload_spill_index
[r
];
8168 /* If this is a non-inherited input reload from a pseudo, we must
8169 clear any memory of a previous store to the same pseudo. Only do
8170 something if there will not be an output reload for the pseudo
8172 if (rld
[r
].in_reg
!= 0
8173 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8175 rtx reg
= rld
[r
].in_reg
;
8177 if (GET_CODE (reg
) == SUBREG
)
8178 reg
= SUBREG_REG (reg
);
8181 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8182 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8184 int nregno
= REGNO (reg
);
8186 if (reg_last_reload_reg
[nregno
])
8188 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8190 if (reg_reloaded_contents
[last_regno
] == nregno
)
8191 spill_reg_store
[last_regno
] = 0;
8196 /* I is nonneg if this reload used a register.
8197 If rld[r].reg_rtx is 0, this is an optional reload
8198 that we opted to ignore. */
8200 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8202 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8205 /* For a multi register reload, we need to check if all or part
8206 of the value lives to the end. */
8207 for (k
= 0; k
< nr
; k
++)
8208 if (reload_reg_reaches_end_p (i
+ k
, r
))
8209 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8211 /* Maybe the spill reg contains a copy of reload_out. */
8213 && (REG_P (rld
[r
].out
)
8215 ? REG_P (rld
[r
].out_reg
)
8216 /* The reload value is an auto-modification of
8217 some kind. For PRE_INC, POST_INC, PRE_DEC
8218 and POST_DEC, we record an equivalence
8219 between the reload register and the operand
8220 on the optimistic assumption that we can make
8221 the equivalence hold. reload_as_needed must
8222 then either make it hold or invalidate the
8225 PRE_MODIFY and POST_MODIFY addresses are reloaded
8226 somewhat differently, and allowing them here leads
8228 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8229 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8233 reg
= reload_reg_rtx_for_output
[r
];
8234 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8236 machine_mode mode
= GET_MODE (reg
);
8237 int regno
= REGNO (reg
);
8238 int nregs
= hard_regno_nregs
[regno
][mode
];
8239 rtx out
= (REG_P (rld
[r
].out
)
8243 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8244 int out_regno
= REGNO (out
);
8245 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8246 : hard_regno_nregs
[out_regno
][mode
]);
8249 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8250 spill_reg_stored_to
[regno
] = out
;
8251 reg_last_reload_reg
[out_regno
] = reg
;
8253 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8254 && nregs
== out_nregs
8255 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8257 /* If OUT_REGNO is a hard register, it may occupy more than
8258 one register. If it does, say what is in the
8259 rest of the registers assuming that both registers
8260 agree on how many words the object takes. If not,
8261 invalidate the subsequent registers. */
8263 if (HARD_REGISTER_NUM_P (out_regno
))
8264 for (k
= 1; k
< out_nregs
; k
++)
8265 reg_last_reload_reg
[out_regno
+ k
]
8266 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8268 /* Now do the inverse operation. */
8269 for (k
= 0; k
< nregs
; k
++)
8271 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8272 reg_reloaded_contents
[regno
+ k
]
8273 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8276 reg_reloaded_insn
[regno
+ k
] = insn
;
8277 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8278 if (targetm
.hard_regno_call_part_clobbered (regno
+ k
,
8280 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8283 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8288 /* Maybe the spill reg contains a copy of reload_in. Only do
8289 something if there will not be an output reload for
8290 the register being reloaded. */
8291 else if (rld
[r
].out_reg
== 0
8293 && ((REG_P (rld
[r
].in
)
8294 && !HARD_REGISTER_P (rld
[r
].in
)
8295 && !REGNO_REG_SET_P (®_has_output_reload
,
8297 || (REG_P (rld
[r
].in_reg
)
8298 && !REGNO_REG_SET_P (®_has_output_reload
,
8299 REGNO (rld
[r
].in_reg
))))
8300 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8304 reg
= reload_reg_rtx_for_input
[r
];
8305 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8315 mode
= GET_MODE (reg
);
8316 regno
= REGNO (reg
);
8317 nregs
= hard_regno_nregs
[regno
][mode
];
8318 if (REG_P (rld
[r
].in
)
8319 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8321 else if (REG_P (rld
[r
].in_reg
))
8324 in
= XEXP (rld
[r
].in_reg
, 0);
8325 in_regno
= REGNO (in
);
8327 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8328 : hard_regno_nregs
[in_regno
][mode
]);
8330 reg_last_reload_reg
[in_regno
] = reg
;
8332 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8333 && nregs
== in_nregs
8334 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8336 if (HARD_REGISTER_NUM_P (in_regno
))
8337 for (k
= 1; k
< in_nregs
; k
++)
8338 reg_last_reload_reg
[in_regno
+ k
]
8339 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8341 /* Unless we inherited this reload, show we haven't
8342 recently done a store.
8343 Previous stores of inherited auto_inc expressions
8344 also have to be discarded. */
8345 if (! reload_inherited
[r
]
8346 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8347 spill_reg_store
[regno
] = 0;
8349 for (k
= 0; k
< nregs
; k
++)
8351 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8352 reg_reloaded_contents
[regno
+ k
]
8353 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8356 reg_reloaded_insn
[regno
+ k
] = insn
;
8357 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8358 if (targetm
.hard_regno_call_part_clobbered (regno
+ k
,
8360 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8363 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8370 /* The following if-statement was #if 0'd in 1.34 (or before...).
8371 It's reenabled in 1.35 because supposedly nothing else
8372 deals with this problem. */
8374 /* If a register gets output-reloaded from a non-spill register,
8375 that invalidates any previous reloaded copy of it.
8376 But forget_old_reloads_1 won't get to see it, because
8377 it thinks only about the original insn. So invalidate it here.
8378 Also do the same thing for RELOAD_OTHER constraints where the
8379 output is discarded. */
8381 && ((rld
[r
].out
!= 0
8382 && (REG_P (rld
[r
].out
)
8383 || (MEM_P (rld
[r
].out
)
8384 && REG_P (rld
[r
].out_reg
))))
8385 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8386 && REG_P (rld
[r
].out_reg
))))
8388 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8389 ? rld
[r
].out
: rld
[r
].out_reg
);
8390 int out_regno
= REGNO (out
);
8391 machine_mode mode
= GET_MODE (out
);
8393 /* REG_RTX is now set or clobbered by the main instruction.
8394 As the comment above explains, forget_old_reloads_1 only
8395 sees the original instruction, and there is no guarantee
8396 that the original instruction also clobbered REG_RTX.
8397 For example, if find_reloads sees that the input side of
8398 a matched operand pair dies in this instruction, it may
8399 use the input register as the reload register.
8401 Calling forget_old_reloads_1 is a waste of effort if
8402 REG_RTX is also the output register.
8404 If we know that REG_RTX holds the value of a pseudo
8405 register, the code after the call will record that fact. */
8406 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8407 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8409 if (!HARD_REGISTER_NUM_P (out_regno
))
8412 rtx_insn
*store_insn
= NULL
;
8414 reg_last_reload_reg
[out_regno
] = 0;
8416 /* If we can find a hard register that is stored, record
8417 the storing insn so that we may delete this insn with
8418 delete_output_reload. */
8419 src_reg
= reload_reg_rtx_for_output
[r
];
8423 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8424 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8430 /* If this is an optional reload, try to find the
8431 source reg from an input reload. */
8432 rtx set
= single_set (insn
);
8433 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8437 src_reg
= SET_SRC (set
);
8439 for (k
= 0; k
< n_reloads
; k
++)
8441 if (rld
[k
].in
== src_reg
)
8443 src_reg
= reload_reg_rtx_for_input
[k
];
8449 if (src_reg
&& REG_P (src_reg
)
8450 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8452 int src_regno
, src_nregs
, k
;
8455 gcc_assert (GET_MODE (src_reg
) == mode
);
8456 src_regno
= REGNO (src_reg
);
8457 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8458 /* The place where to find a death note varies with
8459 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8460 necessarily checked exactly in the code that moves
8461 notes, so just check both locations. */
8462 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8463 if (! note
&& store_insn
)
8464 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8465 for (k
= 0; k
< src_nregs
; k
++)
8467 spill_reg_store
[src_regno
+ k
] = store_insn
;
8468 spill_reg_stored_to
[src_regno
+ k
] = out
;
8469 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8470 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8471 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8472 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8473 if (targetm
.hard_regno_call_part_clobbered
8474 (src_regno
+ k
, mode
))
8475 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8478 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8480 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8482 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8484 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8486 reg_last_reload_reg
[out_regno
] = src_reg
;
8487 /* We have to set reg_has_output_reload here, or else
8488 forget_old_reloads_1 will clear reg_last_reload_reg
8490 SET_REGNO_REG_SET (®_has_output_reload
,
8496 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8498 for (k
= 0; k
< out_nregs
; k
++)
8499 reg_last_reload_reg
[out_regno
+ k
] = 0;
8503 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8506 /* Go through the motions to emit INSN and test if it is strictly valid.
8507 Return the emitted insn if valid, else return NULL. */
8510 emit_insn_if_valid_for_reload (rtx pat
)
8512 rtx_insn
*last
= get_last_insn ();
8515 rtx_insn
*insn
= emit_insn (pat
);
8516 code
= recog_memoized (insn
);
8520 extract_insn (insn
);
8521 /* We want constrain operands to treat this insn strictly in its
8522 validity determination, i.e., the way it would after reload has
8524 if (constrain_operands (1, get_enabled_alternatives (insn
)))
8528 delete_insns_since (last
);
8532 /* Emit code to perform a reload from IN (which may be a reload register) to
8533 OUT (which may also be a reload register). IN or OUT is from operand
8534 OPNUM with reload type TYPE.
8536 Returns first insn emitted. */
8539 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8541 rtx_insn
*last
= get_last_insn ();
8543 #ifdef SECONDARY_MEMORY_NEEDED
8547 /* If IN is a paradoxical SUBREG, remove it and try to put the
8548 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8549 if (!strip_paradoxical_subreg (&in
, &out
))
8550 strip_paradoxical_subreg (&out
, &in
);
8552 /* How to do this reload can get quite tricky. Normally, we are being
8553 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8554 register that didn't get a hard register. In that case we can just
8555 call emit_move_insn.
8557 We can also be asked to reload a PLUS that adds a register or a MEM to
8558 another register, constant or MEM. This can occur during frame pointer
8559 elimination and while reloading addresses. This case is handled by
8560 trying to emit a single insn to perform the add. If it is not valid,
8561 we use a two insn sequence.
8563 Or we can be asked to reload an unary operand that was a fragment of
8564 an addressing mode, into a register. If it isn't recognized as-is,
8565 we try making the unop operand and the reload-register the same:
8566 (set reg:X (unop:X expr:Y))
8567 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8569 Finally, we could be called to handle an 'o' constraint by putting
8570 an address into a register. In that case, we first try to do this
8571 with a named pattern of "reload_load_address". If no such pattern
8572 exists, we just emit a SET insn and hope for the best (it will normally
8573 be valid on machines that use 'o').
8575 This entire process is made complex because reload will never
8576 process the insns we generate here and so we must ensure that
8577 they will fit their constraints and also by the fact that parts of
8578 IN might be being reloaded separately and replaced with spill registers.
8579 Because of this, we are, in some sense, just guessing the right approach
8580 here. The one listed above seems to work.
8582 ??? At some point, this whole thing needs to be rethought. */
8584 if (GET_CODE (in
) == PLUS
8585 && (REG_P (XEXP (in
, 0))
8586 || GET_CODE (XEXP (in
, 0)) == SUBREG
8587 || MEM_P (XEXP (in
, 0)))
8588 && (REG_P (XEXP (in
, 1))
8589 || GET_CODE (XEXP (in
, 1)) == SUBREG
8590 || CONSTANT_P (XEXP (in
, 1))
8591 || MEM_P (XEXP (in
, 1))))
8593 /* We need to compute the sum of a register or a MEM and another
8594 register, constant, or MEM, and put it into the reload
8595 register. The best possible way of doing this is if the machine
8596 has a three-operand ADD insn that accepts the required operands.
8598 The simplest approach is to try to generate such an insn and see if it
8599 is recognized and matches its constraints. If so, it can be used.
8601 It might be better not to actually emit the insn unless it is valid,
8602 but we need to pass the insn as an operand to `recog' and
8603 `extract_insn' and it is simpler to emit and then delete the insn if
8604 not valid than to dummy things up. */
8608 enum insn_code code
;
8610 op0
= find_replacement (&XEXP (in
, 0));
8611 op1
= find_replacement (&XEXP (in
, 1));
8613 /* Since constraint checking is strict, commutativity won't be
8614 checked, so we need to do that here to avoid spurious failure
8615 if the add instruction is two-address and the second operand
8616 of the add is the same as the reload reg, which is frequently
8617 the case. If the insn would be A = B + A, rearrange it so
8618 it will be A = A + B as constrain_operands expects. */
8620 if (REG_P (XEXP (in
, 1))
8621 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8622 tem
= op0
, op0
= op1
, op1
= tem
;
8624 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8625 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8627 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8631 /* If that failed, we must use a conservative two-insn sequence.
8633 Use a move to copy one operand into the reload register. Prefer
8634 to reload a constant, MEM or pseudo since the move patterns can
8635 handle an arbitrary operand. If OP1 is not a constant, MEM or
8636 pseudo and OP1 is not a valid operand for an add instruction, then
8639 After reloading one of the operands into the reload register, add
8640 the reload register to the output register.
8642 If there is another way to do this for a specific machine, a
8643 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8646 code
= optab_handler (add_optab
, GET_MODE (out
));
8648 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8650 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8651 || (code
!= CODE_FOR_nothing
8652 && !insn_operand_matches (code
, 2, op1
)))
8653 tem
= op0
, op0
= op1
, op1
= tem
;
8655 gen_reload (out
, op0
, opnum
, type
);
8657 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8658 This fixes a problem on the 32K where the stack pointer cannot
8659 be used as an operand of an add insn. */
8661 if (rtx_equal_p (op0
, op1
))
8664 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8667 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8668 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8672 /* If that failed, copy the address register to the reload register.
8673 Then add the constant to the reload register. */
8675 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8676 gen_reload (out
, op1
, opnum
, type
);
8677 insn
= emit_insn (gen_add2_insn (out
, op0
));
8678 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8681 #ifdef SECONDARY_MEMORY_NEEDED
8682 /* If we need a memory location to do the move, do it that way. */
8683 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8684 (REG_P (tem1
) && REG_P (tem2
)))
8685 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8686 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8687 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8688 REGNO_REG_CLASS (REGNO (tem2
)),
8691 /* Get the memory to use and rewrite both registers to its mode. */
8692 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8694 if (GET_MODE (loc
) != GET_MODE (out
))
8695 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8697 if (GET_MODE (loc
) != GET_MODE (in
))
8698 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8700 gen_reload (loc
, in
, opnum
, type
);
8701 gen_reload (out
, loc
, opnum
, type
);
8704 else if (REG_P (out
) && UNARY_P (in
))
8710 op1
= find_replacement (&XEXP (in
, 0));
8711 if (op1
!= XEXP (in
, 0))
8712 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8714 /* First, try a plain SET. */
8715 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8719 /* If that failed, move the inner operand to the reload
8720 register, and try the same unop with the inner expression
8721 replaced with the reload register. */
8723 if (GET_MODE (op1
) != GET_MODE (out
))
8724 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8728 gen_reload (out_moded
, op1
, opnum
, type
);
8730 rtx temp
= gen_rtx_SET (out
, gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8732 rtx_insn
*insn
= emit_insn_if_valid_for_reload (temp
);
8735 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8739 fatal_insn ("failure trying to reload:", set
);
8741 /* If IN is a simple operand, use gen_move_insn. */
8742 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8744 tem
= emit_insn (gen_move_insn (out
, in
));
8745 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8746 mark_jump_label (in
, tem
, 0);
8749 else if (targetm
.have_reload_load_address ())
8750 emit_insn (targetm
.gen_reload_load_address (out
, in
));
8752 /* Otherwise, just write (set OUT IN) and hope for the best. */
8754 emit_insn (gen_rtx_SET (out
, in
));
8756 /* Return the first insn emitted.
8757 We can not just return get_last_insn, because there may have
8758 been multiple instructions emitted. Also note that gen_move_insn may
8759 emit more than one insn itself, so we can not assume that there is one
8760 insn emitted per emit_insn_before call. */
8762 return last
? NEXT_INSN (last
) : get_insns ();
8765 /* Delete a previously made output-reload whose result we now believe
8766 is not needed. First we double-check.
8768 INSN is the insn now being processed.
8769 LAST_RELOAD_REG is the hard register number for which we want to delete
8770 the last output reload.
8771 J is the reload-number that originally used REG. The caller has made
8772 certain that reload J doesn't use REG any longer for input.
8773 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8776 delete_output_reload (rtx_insn
*insn
, int j
, int last_reload_reg
,
8779 rtx_insn
*output_reload_insn
= spill_reg_store
[last_reload_reg
];
8780 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8783 int n_inherited
= 0;
8788 /* It is possible that this reload has been only used to set another reload
8789 we eliminated earlier and thus deleted this instruction too. */
8790 if (output_reload_insn
->deleted ())
8793 /* Get the raw pseudo-register referred to. */
8795 while (GET_CODE (reg
) == SUBREG
)
8796 reg
= SUBREG_REG (reg
);
8797 substed
= reg_equiv_memory_loc (REGNO (reg
));
8799 /* This is unsafe if the operand occurs more often in the current
8800 insn than it is inherited. */
8801 for (k
= n_reloads
- 1; k
>= 0; k
--)
8803 rtx reg2
= rld
[k
].in
;
8806 if (MEM_P (reg2
) || reload_override_in
[k
])
8807 reg2
= rld
[k
].in_reg
;
8809 if (AUTO_INC_DEC
&& rld
[k
].out
&& ! rld
[k
].out_reg
)
8810 reg2
= XEXP (rld
[k
].in_reg
, 0);
8812 while (GET_CODE (reg2
) == SUBREG
)
8813 reg2
= SUBREG_REG (reg2
);
8814 if (rtx_equal_p (reg2
, reg
))
8816 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8822 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8823 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8824 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8827 n_occurrences
+= count_occurrences (PATTERN (insn
),
8828 eliminate_regs (substed
, VOIDmode
,
8830 for (rtx i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8832 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8833 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8835 if (n_occurrences
> n_inherited
)
8838 regno
= REGNO (reg
);
8839 if (regno
>= FIRST_PSEUDO_REGISTER
)
8842 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8844 /* If the pseudo-reg we are reloading is no longer referenced
8845 anywhere between the store into it and here,
8846 and we're within the same basic block, then the value can only
8847 pass through the reload reg and end up here.
8848 Otherwise, give up--return. */
8849 for (rtx_insn
*i1
= NEXT_INSN (output_reload_insn
);
8850 i1
!= insn
; i1
= NEXT_INSN (i1
))
8852 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8854 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8855 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8857 /* If this is USE in front of INSN, we only have to check that
8858 there are no more references than accounted for by inheritance. */
8859 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8861 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8862 i1
= NEXT_INSN (i1
);
8864 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8870 /* We will be deleting the insn. Remove the spill reg information. */
8871 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8873 spill_reg_store
[last_reload_reg
+ k
] = 0;
8874 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8877 /* The caller has already checked that REG dies or is set in INSN.
8878 It has also checked that we are optimizing, and thus some
8879 inaccuracies in the debugging information are acceptable.
8880 So we could just delete output_reload_insn. But in some cases
8881 we can improve the debugging information without sacrificing
8882 optimization - maybe even improving the code: See if the pseudo
8883 reg has been completely replaced with reload regs. If so, delete
8884 the store insn and forget we had a stack slot for the pseudo. */
8885 if (rld
[j
].out
!= rld
[j
].in
8886 && REG_N_DEATHS (REGNO (reg
)) == 1
8887 && REG_N_SETS (REGNO (reg
)) == 1
8888 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8889 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8893 /* We know that it was used only between here and the beginning of
8894 the current basic block. (We also know that the last use before
8895 INSN was the output reload we are thinking of deleting, but never
8896 mind that.) Search that range; see if any ref remains. */
8897 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8899 rtx set
= single_set (i2
);
8901 /* Uses which just store in the pseudo don't count,
8902 since if they are the only uses, they are dead. */
8903 if (set
!= 0 && SET_DEST (set
) == reg
)
8905 if (LABEL_P (i2
) || JUMP_P (i2
))
8907 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8908 && reg_mentioned_p (reg
, PATTERN (i2
)))
8910 /* Some other ref remains; just delete the output reload we
8912 delete_address_reloads (output_reload_insn
, insn
);
8913 delete_insn (output_reload_insn
);
8918 /* Delete the now-dead stores into this pseudo. Note that this
8919 loop also takes care of deleting output_reload_insn. */
8920 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8922 rtx set
= single_set (i2
);
8924 if (set
!= 0 && SET_DEST (set
) == reg
)
8926 delete_address_reloads (i2
, insn
);
8929 if (LABEL_P (i2
) || JUMP_P (i2
))
8933 /* For the debugging info, say the pseudo lives in this reload reg. */
8934 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8935 if (ira_conflicts_p
)
8936 /* Inform IRA about the change. */
8937 ira_mark_allocation_change (REGNO (reg
));
8938 alter_reg (REGNO (reg
), -1, false);
8942 delete_address_reloads (output_reload_insn
, insn
);
8943 delete_insn (output_reload_insn
);
8947 /* We are going to delete DEAD_INSN. Recursively delete loads of
8948 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8949 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8951 delete_address_reloads (rtx_insn
*dead_insn
, rtx_insn
*current_insn
)
8953 rtx set
= single_set (dead_insn
);
8955 rtx_insn
*prev
, *next
;
8958 rtx dst
= SET_DEST (set
);
8960 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8962 /* If we deleted the store from a reloaded post_{in,de}c expression,
8963 we can delete the matching adds. */
8964 prev
= PREV_INSN (dead_insn
);
8965 next
= NEXT_INSN (dead_insn
);
8966 if (! prev
|| ! next
)
8968 set
= single_set (next
);
8969 set2
= single_set (prev
);
8971 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8972 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8973 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8975 dst
= SET_DEST (set
);
8976 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8977 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8978 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8979 || (INTVAL (XEXP (SET_SRC (set
), 1))
8980 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8982 delete_related_insns (prev
);
8983 delete_related_insns (next
);
8986 /* Subfunction of delete_address_reloads: process registers found in X. */
8988 delete_address_reloads_1 (rtx_insn
*dead_insn
, rtx x
, rtx_insn
*current_insn
)
8990 rtx_insn
*prev
, *i2
;
8993 enum rtx_code code
= GET_CODE (x
);
8997 const char *fmt
= GET_RTX_FORMAT (code
);
8998 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9001 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
9002 else if (fmt
[i
] == 'E')
9004 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9005 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
9012 if (spill_reg_order
[REGNO (x
)] < 0)
9015 /* Scan backwards for the insn that sets x. This might be a way back due
9017 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
9019 code
= GET_CODE (prev
);
9020 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
9024 if (reg_set_p (x
, PATTERN (prev
)))
9026 if (reg_referenced_p (x
, PATTERN (prev
)))
9029 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
9031 /* Check that PREV only sets the reload register. */
9032 set
= single_set (prev
);
9035 dst
= SET_DEST (set
);
9037 || ! rtx_equal_p (dst
, x
))
9039 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9041 /* Check if DST was used in a later insn -
9042 it might have been inherited. */
9043 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9049 if (reg_referenced_p (dst
, PATTERN (i2
)))
9051 /* If there is a reference to the register in the current insn,
9052 it might be loaded in a non-inherited reload. If no other
9053 reload uses it, that means the register is set before
9055 if (i2
== current_insn
)
9057 for (j
= n_reloads
- 1; j
>= 0; j
--)
9058 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9059 || reload_override_in
[j
] == dst
)
9061 for (j
= n_reloads
- 1; j
>= 0; j
--)
9062 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9071 /* If DST is still live at CURRENT_INSN, check if it is used for
9072 any reload. Note that even if CURRENT_INSN sets DST, we still
9073 have to check the reloads. */
9074 if (i2
== current_insn
)
9076 for (j
= n_reloads
- 1; j
>= 0; j
--)
9077 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9078 || reload_override_in
[j
] == dst
)
9080 /* ??? We can't finish the loop here, because dst might be
9081 allocated to a pseudo in this block if no reload in this
9082 block needs any of the classes containing DST - see
9083 spill_hard_reg. There is no easy way to tell this, so we
9084 have to scan till the end of the basic block. */
9086 if (reg_set_p (dst
, PATTERN (i2
)))
9090 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9091 reg_reloaded_contents
[REGNO (dst
)] = -1;
9095 /* Output reload-insns to reload VALUE into RELOADREG.
9096 VALUE is an autoincrement or autodecrement RTX whose operand
9097 is a register or memory location;
9098 so reloading involves incrementing that location.
9099 IN is either identical to VALUE, or some cheaper place to reload from.
9101 INC_AMOUNT is the number to increment or decrement by (always positive).
9102 This cannot be deduced from VALUE. */
9105 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9107 /* REG or MEM to be copied and incremented. */
9108 rtx incloc
= find_replacement (&XEXP (value
, 0));
9109 /* Nonzero if increment after copying. */
9110 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9111 || GET_CODE (value
) == POST_MODIFY
);
9116 rtx real_in
= in
== value
? incloc
: in
;
9118 /* No hard register is equivalent to this register after
9119 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9120 we could inc/dec that register as well (maybe even using it for
9121 the source), but I'm not sure it's worth worrying about. */
9123 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9125 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9127 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9128 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9132 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9133 inc_amount
= -inc_amount
;
9135 inc
= GEN_INT (inc_amount
);
9138 /* If this is post-increment, first copy the location to the reload reg. */
9139 if (post
&& real_in
!= reloadreg
)
9140 emit_insn (gen_move_insn (reloadreg
, real_in
));
9144 /* See if we can directly increment INCLOC. Use a method similar to
9145 that in gen_reload. */
9147 last
= get_last_insn ();
9148 add_insn
= emit_insn (gen_rtx_SET (incloc
,
9149 gen_rtx_PLUS (GET_MODE (incloc
),
9152 code
= recog_memoized (add_insn
);
9155 extract_insn (add_insn
);
9156 if (constrain_operands (1, get_enabled_alternatives (add_insn
)))
9158 /* If this is a pre-increment and we have incremented the value
9159 where it lives, copy the incremented value to RELOADREG to
9160 be used as an address. */
9163 emit_insn (gen_move_insn (reloadreg
, incloc
));
9167 delete_insns_since (last
);
9170 /* If couldn't do the increment directly, must increment in RELOADREG.
9171 The way we do this depends on whether this is pre- or post-increment.
9172 For pre-increment, copy INCLOC to the reload register, increment it
9173 there, then save back. */
9177 if (in
!= reloadreg
)
9178 emit_insn (gen_move_insn (reloadreg
, real_in
));
9179 emit_insn (gen_add2_insn (reloadreg
, inc
));
9180 emit_insn (gen_move_insn (incloc
, reloadreg
));
9185 Because this might be a jump insn or a compare, and because RELOADREG
9186 may not be available after the insn in an input reload, we must do
9187 the incrementation before the insn being reloaded for.
9189 We have already copied IN to RELOADREG. Increment the copy in
9190 RELOADREG, save that back, then decrement RELOADREG so it has
9191 the original value. */
9193 emit_insn (gen_add2_insn (reloadreg
, inc
));
9194 emit_insn (gen_move_insn (incloc
, reloadreg
));
9195 if (CONST_INT_P (inc
))
9196 emit_insn (gen_add2_insn (reloadreg
,
9197 gen_int_mode (-INTVAL (inc
),
9198 GET_MODE (reloadreg
))));
9200 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9205 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
9207 enum rtx_code code
= GET_CODE (x
);
9211 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9213 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9217 /* Scan all the operand sub-expressions. */
9218 fmt
= GET_RTX_FORMAT (code
);
9219 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9222 add_auto_inc_notes (insn
, XEXP (x
, i
));
9223 else if (fmt
[i
] == 'E')
9224 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9225 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));