1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
36 #include "rtl-error.h"
38 #include "addresses.h"
46 /* This file contains the reload pass of the compiler, which is
47 run after register allocation has been done. It checks that
48 each insn is valid (operands required to be in registers really
49 are in registers of the proper class) and fixes up invalid ones
50 by copying values temporarily into registers for the insns
53 The results of register allocation are described by the vector
54 reg_renumber; the insns still contain pseudo regs, but reg_renumber
55 can be used to find which hard reg, if any, a pseudo reg is in.
57 The technique we always use is to free up a few hard regs that are
58 called ``reload regs'', and for each place where a pseudo reg
59 must be in a hard reg, copy it temporarily into one of the reload regs.
61 Reload regs are allocated locally for every instruction that needs
62 reloads. When there are pseudos which are allocated to a register that
63 has been chosen as a reload reg, such pseudos must be ``spilled''.
64 This means that they go to other hard regs, or to stack slots if no other
65 available hard regs can be found. Spilling can invalidate more
66 insns, requiring additional need for reloads, so we must keep checking
67 until the process stabilizes.
69 For machines with different classes of registers, we must keep track
70 of the register class needed for each reload, and make sure that
71 we allocate enough reload registers of each class.
73 The file reload.c contains the code that checks one insn for
74 validity and reports the reloads that it needs. This file
75 is in charge of scanning the entire rtl code, accumulating the
76 reload needs, spilling, assigning reload registers to use for
77 fixing up each insn, and generating the new insns to copy values
78 into the reload registers. */
80 struct target_reload default_target_reload
;
82 struct target_reload
*this_target_reload
= &default_target_reload
;
85 #define spill_indirect_levels \
86 (this_target_reload->x_spill_indirect_levels)
88 /* During reload_as_needed, element N contains a REG rtx for the hard reg
89 into which reg N has been reloaded (perhaps for a previous insn). */
90 static rtx
*reg_last_reload_reg
;
92 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
93 for an output reload that stores into reg N. */
94 static regset_head reg_has_output_reload
;
96 /* Indicates which hard regs are reload-registers for an output reload
97 in the current insn. */
98 static HARD_REG_SET reg_is_output_reload
;
100 /* Widest mode in which each pseudo reg is referred to (via subreg). */
101 static machine_mode
*reg_max_ref_mode
;
103 /* Vector to remember old contents of reg_renumber before spilling. */
104 static short *reg_old_renumber
;
106 /* During reload_as_needed, element N contains the last pseudo regno reloaded
107 into hard register N. If that pseudo reg occupied more than one register,
108 reg_reloaded_contents points to that pseudo for each spill register in
109 use; all of these must remain set for an inheritance to occur. */
110 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
112 /* During reload_as_needed, element N contains the insn for which
113 hard register N was last used. Its contents are significant only
114 when reg_reloaded_valid is set for this register. */
115 static rtx_insn
*reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
117 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
118 static HARD_REG_SET reg_reloaded_valid
;
119 /* Indicate if the register was dead at the end of the reload.
120 This is only valid if reg_reloaded_contents is set and valid. */
121 static HARD_REG_SET reg_reloaded_dead
;
123 /* Indicate whether the register's current value is one that is not
124 safe to retain across a call, even for registers that are normally
125 call-saved. This is only meaningful for members of reg_reloaded_valid. */
126 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
128 /* Number of spill-regs so far; number of valid elements of spill_regs. */
131 /* In parallel with spill_regs, contains REG rtx's for those regs.
132 Holds the last rtx used for any given reg, or 0 if it has never
133 been used for spilling yet. This rtx is reused, provided it has
135 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
137 /* In parallel with spill_regs, contains nonzero for a spill reg
138 that was stored after the last time it was used.
139 The precise value is the insn generated to do the store. */
140 static rtx_insn
*spill_reg_store
[FIRST_PSEUDO_REGISTER
];
142 /* This is the register that was stored with spill_reg_store. This is a
143 copy of reload_out / reload_out_reg when the value was stored; if
144 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
145 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
147 /* This table is the inverse mapping of spill_regs:
148 indexed by hard reg number,
149 it contains the position of that reg in spill_regs,
150 or -1 for something that is not in spill_regs.
152 ?!? This is no longer accurate. */
153 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
155 /* This reg set indicates registers that can't be used as spill registers for
156 the currently processed insn. These are the hard registers which are live
157 during the insn, but not allocated to pseudos, as well as fixed
159 static HARD_REG_SET bad_spill_regs
;
161 /* These are the hard registers that can't be used as spill register for any
162 insn. This includes registers used for user variables and registers that
163 we can't eliminate. A register that appears in this set also can't be used
164 to retry register allocation. */
165 static HARD_REG_SET bad_spill_regs_global
;
167 /* Describes order of use of registers for reloading
168 of spilled pseudo-registers. `n_spills' is the number of
169 elements that are actually valid; new ones are added at the end.
171 Both spill_regs and spill_reg_order are used on two occasions:
172 once during find_reload_regs, where they keep track of the spill registers
173 for a single insn, but also during reload_as_needed where they show all
174 the registers ever used by reload. For the latter case, the information
175 is calculated during finish_spills. */
176 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
178 /* This vector of reg sets indicates, for each pseudo, which hard registers
179 may not be used for retrying global allocation because the register was
180 formerly spilled from one of them. If we allowed reallocating a pseudo to
181 a register that it was already allocated to, reload might not
183 static HARD_REG_SET
*pseudo_previous_regs
;
185 /* This vector of reg sets indicates, for each pseudo, which hard
186 registers may not be used for retrying global allocation because they
187 are used as spill registers during one of the insns in which the
189 static HARD_REG_SET
*pseudo_forbidden_regs
;
191 /* All hard regs that have been used as spill registers for any insn are
192 marked in this set. */
193 static HARD_REG_SET used_spill_regs
;
195 /* Index of last register assigned as a spill register. We allocate in
196 a round-robin fashion. */
197 static int last_spill_reg
;
199 /* Record the stack slot for each spilled hard register. */
200 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
202 /* Width allocated so far for that stack slot. */
203 static poly_uint64_pod spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
205 /* Record which pseudos needed to be spilled. */
206 static regset_head spilled_pseudos
;
208 /* Record which pseudos changed their allocation in finish_spills. */
209 static regset_head changed_allocation_pseudos
;
211 /* Used for communication between order_regs_for_reload and count_pseudo.
212 Used to avoid counting one pseudo twice. */
213 static regset_head pseudos_counted
;
215 /* First uid used by insns created by reload in this function.
216 Used in find_equiv_reg. */
217 int reload_first_uid
;
219 /* Flag set by local-alloc or global-alloc if anything is live in
220 a call-clobbered reg across calls. */
221 int caller_save_needed
;
223 /* Set to 1 while reload_as_needed is operating.
224 Required by some machines to handle any generated moves differently. */
225 int reload_in_progress
= 0;
227 /* This obstack is used for allocation of rtl during register elimination.
228 The allocated storage can be freed once find_reloads has processed the
230 static struct obstack reload_obstack
;
232 /* Points to the beginning of the reload_obstack. All insn_chain structures
233 are allocated first. */
234 static char *reload_startobj
;
236 /* The point after all insn_chain structures. Used to quickly deallocate
237 memory allocated in copy_reloads during calculate_needs_all_insns. */
238 static char *reload_firstobj
;
240 /* This points before all local rtl generated by register elimination.
241 Used to quickly free all memory after processing one insn. */
242 static char *reload_insn_firstobj
;
244 /* List of insn_chain instructions, one for every insn that reload needs to
246 class insn_chain
*reload_insn_chain
;
248 /* TRUE if we potentially left dead insns in the insn stream and want to
249 run DCE immediately after reload, FALSE otherwise. */
250 static bool need_dce
;
252 /* List of all insns needing reloads. */
253 static class insn_chain
*insns_need_reload
;
255 /* This structure is used to record information about register eliminations.
256 Each array entry describes one possible way of eliminating a register
257 in favor of another. If there is more than one way of eliminating a
258 particular register, the most preferred should be specified first. */
262 int from
; /* Register number to be eliminated. */
263 int to
; /* Register number used as replacement. */
264 poly_int64_pod initial_offset
; /* Initial difference between values. */
265 int can_eliminate
; /* Nonzero if this elimination can be done. */
266 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
267 target hook in previous scan over insns
269 poly_int64_pod offset
; /* Current offset between the two regs. */
270 poly_int64_pod previous_offset
; /* Offset at end of previous insn. */
271 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
272 rtx from_rtx
; /* REG rtx for the register to be eliminated.
273 We cannot simply compare the number since
274 we might then spuriously replace a hard
275 register corresponding to a pseudo
276 assigned to the reg to be eliminated. */
277 rtx to_rtx
; /* REG rtx for the replacement. */
280 static struct elim_table
*reg_eliminate
= 0;
282 /* This is an intermediate structure to initialize the table. It has
283 exactly the members provided by ELIMINABLE_REGS. */
284 static const struct elim_table_1
288 } reg_eliminate_1
[] =
292 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
294 /* Record the number of pending eliminations that have an offset not equal
295 to their initial offset. If nonzero, we use a new copy of each
296 replacement result in any insns encountered. */
297 int num_not_at_initial_offset
;
299 /* Count the number of registers that we may be able to eliminate. */
300 static int num_eliminable
;
301 /* And the number of registers that are equivalent to a constant that
302 can be eliminated to frame_pointer / arg_pointer + constant. */
303 static int num_eliminable_invariants
;
305 /* For each label, we record the offset of each elimination. If we reach
306 a label by more than one path and an offset differs, we cannot do the
307 elimination. This information is indexed by the difference of the
308 number of the label and the first label number. We can't offset the
309 pointer itself as this can cause problems on machines with segmented
310 memory. The first table is an array of flags that records whether we
311 have yet encountered a label and the second table is an array of arrays,
312 one entry in the latter array for each elimination. */
314 static int first_label_num
;
315 static char *offsets_known_at
;
316 static poly_int64_pod (*offsets_at
)[NUM_ELIMINABLE_REGS
];
318 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
320 /* Stack of addresses where an rtx has been changed. We can undo the
321 changes by popping items off the stack and restoring the original
322 value at each location.
324 We use this simplistic undo capability rather than copy_rtx as copy_rtx
325 will not make a deep copy of a normally sharable rtx, such as
326 (const (plus (symbol_ref) (const_int))). If such an expression appears
327 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
328 rtx expression would be changed. See PR 42431. */
331 static vec
<rtx_p
> substitute_stack
;
333 /* Number of labels in the current function. */
335 static int num_labels
;
337 static void replace_pseudos_in (rtx
*, machine_mode
, rtx
);
338 static void maybe_fix_stack_asms (void);
339 static void copy_reloads (class insn_chain
*);
340 static void calculate_needs_all_insns (int);
341 static int find_reg (class insn_chain
*, int);
342 static void find_reload_regs (class insn_chain
*);
343 static void select_reload_regs (void);
344 static void delete_caller_save_insns (void);
346 static void spill_failure (rtx_insn
*, enum reg_class
);
347 static void count_spilled_pseudo (int, int, int);
348 static void delete_dead_insn (rtx_insn
*);
349 static void alter_reg (int, int, bool);
350 static void set_label_offsets (rtx
, rtx_insn
*, int);
351 static void check_eliminable_occurrences (rtx
);
352 static void elimination_effects (rtx
, machine_mode
);
353 static rtx
eliminate_regs_1 (rtx
, machine_mode
, rtx
, bool, bool);
354 static int eliminate_regs_in_insn (rtx_insn
*, int);
355 static void update_eliminable_offsets (void);
356 static void mark_not_eliminable (rtx
, const_rtx
, void *);
357 static void set_initial_elim_offsets (void);
358 static bool verify_initial_elim_offsets (void);
359 static void set_initial_label_offsets (void);
360 static void set_offsets_for_label (rtx_insn
*);
361 static void init_eliminable_invariants (rtx_insn
*, bool);
362 static void init_elim_table (void);
363 static void free_reg_equiv (void);
364 static void update_eliminables (HARD_REG_SET
*);
365 static bool update_eliminables_and_spill (void);
366 static void elimination_costs_in_insn (rtx_insn
*);
367 static void spill_hard_reg (unsigned int, int);
368 static int finish_spills (int);
369 static void scan_paradoxical_subregs (rtx
);
370 static void count_pseudo (int);
371 static void order_regs_for_reload (class insn_chain
*);
372 static void reload_as_needed (int);
373 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
374 static void forget_marked_reloads (regset
);
375 static int reload_reg_class_lower (const void *, const void *);
376 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
378 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
380 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
381 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
383 static int free_for_value_p (int, machine_mode
, int, enum reload_type
,
385 static int allocate_reload_reg (class insn_chain
*, int, int);
386 static int conflicts_with_override (rtx
);
387 static void failed_reload (rtx_insn
*, int);
388 static int set_reload_reg (int, int);
389 static void choose_reload_regs_init (class insn_chain
*, rtx
*);
390 static void choose_reload_regs (class insn_chain
*);
391 static void emit_input_reload_insns (class insn_chain
*, struct reload
*,
393 static void emit_output_reload_insns (class insn_chain
*, struct reload
*,
395 static void do_input_reload (class insn_chain
*, struct reload
*, int);
396 static void do_output_reload (class insn_chain
*, struct reload
*, int);
397 static void emit_reload_insns (class insn_chain
*);
398 static void delete_output_reload (rtx_insn
*, int, int, rtx
);
399 static void delete_address_reloads (rtx_insn
*, rtx_insn
*);
400 static void delete_address_reloads_1 (rtx_insn
*, rtx
, rtx_insn
*);
401 static void inc_for_reload (rtx
, rtx
, rtx
, poly_int64
);
402 static void add_auto_inc_notes (rtx_insn
*, rtx
);
403 static void substitute (rtx
*, const_rtx
, rtx
);
404 static bool gen_reload_chain_without_interm_reg_p (int, int);
405 static int reloads_conflict (int, int);
406 static rtx_insn
*gen_reload (rtx
, rtx
, int, enum reload_type
);
407 static rtx_insn
*emit_insn_if_valid_for_reload (rtx
);
409 /* Initialize the reload pass. This is called at the beginning of compilation
410 and may be called again if the target is reinitialized. */
417 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
418 Set spill_indirect_levels to the number of levels such addressing is
419 permitted, zero if it is not permitted at all. */
422 = gen_rtx_MEM (Pmode
,
425 LAST_VIRTUAL_REGISTER
+ 1),
426 gen_int_mode (4, Pmode
)));
427 spill_indirect_levels
= 0;
429 while (memory_address_p (QImode
, tem
))
431 spill_indirect_levels
++;
432 tem
= gen_rtx_MEM (Pmode
, tem
);
435 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
437 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
438 indirect_symref_ok
= memory_address_p (QImode
, tem
);
440 /* See if reg+reg is a valid (and offsettable) address. */
442 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
444 tem
= gen_rtx_PLUS (Pmode
,
445 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
446 gen_rtx_REG (Pmode
, i
));
448 /* This way, we make sure that reg+reg is an offsettable address. */
449 tem
= plus_constant (Pmode
, tem
, 4);
451 for (int mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
452 if (!double_reg_address_ok
[mode
]
453 && memory_address_p ((enum machine_mode
)mode
, tem
))
454 double_reg_address_ok
[mode
] = 1;
457 /* Initialize obstack for our rtl allocation. */
458 if (reload_startobj
== NULL
)
460 gcc_obstack_init (&reload_obstack
);
461 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
464 INIT_REG_SET (&spilled_pseudos
);
465 INIT_REG_SET (&changed_allocation_pseudos
);
466 INIT_REG_SET (&pseudos_counted
);
469 /* List of insn chains that are currently unused. */
470 static class insn_chain
*unused_insn_chains
= 0;
472 /* Allocate an empty insn_chain structure. */
474 new_insn_chain (void)
478 if (unused_insn_chains
== 0)
480 c
= XOBNEW (&reload_obstack
, class insn_chain
);
481 INIT_REG_SET (&c
->live_throughout
);
482 INIT_REG_SET (&c
->dead_or_set
);
486 c
= unused_insn_chains
;
487 unused_insn_chains
= c
->next
;
489 c
->is_caller_save_insn
= 0;
490 c
->need_operand_change
= 0;
496 /* Small utility function to set all regs in hard reg set TO which are
497 allocated to pseudos in regset FROM. */
500 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
503 reg_set_iterator rsi
;
505 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
507 int r
= reg_renumber
[regno
];
511 /* reload_combine uses the information from DF_LIVE_IN,
512 which might still contain registers that have not
513 actually been allocated since they have an
515 gcc_assert (ira_conflicts_p
|| reload_completed
);
518 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
522 /* Replace all pseudos found in LOC with their corresponding
526 replace_pseudos_in (rtx
*loc
, machine_mode mem_mode
, rtx usage
)
539 unsigned int regno
= REGNO (x
);
541 if (regno
< FIRST_PSEUDO_REGISTER
)
544 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
548 replace_pseudos_in (loc
, mem_mode
, usage
);
552 if (reg_equiv_constant (regno
))
553 *loc
= reg_equiv_constant (regno
);
554 else if (reg_equiv_invariant (regno
))
555 *loc
= reg_equiv_invariant (regno
);
556 else if (reg_equiv_mem (regno
))
557 *loc
= reg_equiv_mem (regno
);
558 else if (reg_equiv_address (regno
))
559 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
562 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
563 || REGNO (regno_reg_rtx
[regno
]) != regno
);
564 *loc
= regno_reg_rtx
[regno
];
569 else if (code
== MEM
)
571 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
575 /* Process each of our operands recursively. */
576 fmt
= GET_RTX_FORMAT (code
);
577 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
579 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
580 else if (*fmt
== 'E')
581 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
582 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
585 /* Determine if the current function has an exception receiver block
586 that reaches the exit block via non-exceptional edges */
589 has_nonexceptional_receiver (void)
593 basic_block
*tos
, *worklist
, bb
;
595 /* If we're not optimizing, then just err on the safe side. */
599 /* First determine which blocks can reach exit via normal paths. */
600 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
602 FOR_EACH_BB_FN (bb
, cfun
)
603 bb
->flags
&= ~BB_REACHABLE
;
605 /* Place the exit block on our worklist. */
606 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
607 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
609 /* Iterate: find everything reachable from what we've already seen. */
610 while (tos
!= worklist
)
614 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
615 if (!(e
->flags
& EDGE_ABNORMAL
))
617 basic_block src
= e
->src
;
619 if (!(src
->flags
& BB_REACHABLE
))
621 src
->flags
|= BB_REACHABLE
;
628 /* Now see if there's a reachable block with an exceptional incoming
630 FOR_EACH_BB_FN (bb
, cfun
)
631 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
634 /* No exceptional block reached exit unexceptionally. */
638 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
639 zero elements) to MAX_REG_NUM elements.
641 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
643 grow_reg_equivs (void)
645 int old_size
= vec_safe_length (reg_equivs
);
646 int max_regno
= max_reg_num ();
650 memset (&ze
, 0, sizeof (reg_equivs_t
));
651 vec_safe_reserve (reg_equivs
, max_regno
);
652 for (i
= old_size
; i
< max_regno
; i
++)
653 reg_equivs
->quick_insert (i
, ze
);
657 /* Global variables used by reload and its subroutines. */
659 /* The current basic block while in calculate_elim_costs_all_insns. */
660 static basic_block elim_bb
;
662 /* Set during calculate_needs if an insn needs register elimination. */
663 static int something_needs_elimination
;
664 /* Set during calculate_needs if an insn needs an operand changed. */
665 static int something_needs_operands_changed
;
666 /* Set by alter_regs if we spilled a register to the stack. */
667 static bool something_was_spilled
;
669 /* Nonzero means we couldn't get enough spill regs. */
672 /* Temporary array of pseudo-register number. */
673 static int *temp_pseudo_reg_arr
;
675 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
676 If that insn didn't set the register (i.e., it copied the register to
677 memory), just delete that insn instead of the equivalencing insn plus
678 anything now dead. If we call delete_dead_insn on that insn, we may
679 delete the insn that actually sets the register if the register dies
680 there and that is incorrect. */
684 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
686 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
689 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
691 rtx_insn
*equiv_insn
= as_a
<rtx_insn
*> (XEXP (list
, 0));
693 /* If we already deleted the insn or if it may trap, we can't
694 delete it. The latter case shouldn't happen, but can
695 if an insn has a variable address, gets a REG_EH_REGION
696 note added to it, and then gets converted into a load
697 from a constant address. */
698 if (NOTE_P (equiv_insn
)
699 || can_throw_internal (equiv_insn
))
701 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
702 delete_dead_insn (equiv_insn
);
704 SET_INSN_DELETED (equiv_insn
);
710 /* Return true if remove_init_insns will delete INSN. */
712 will_delete_init_insn_p (rtx_insn
*insn
)
714 rtx set
= single_set (insn
);
715 if (!set
|| !REG_P (SET_DEST (set
)))
717 unsigned regno
= REGNO (SET_DEST (set
));
719 if (can_throw_internal (insn
))
722 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
725 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
727 rtx equiv_insn
= XEXP (list
, 0);
728 if (equiv_insn
== insn
)
734 /* Main entry point for the reload pass.
736 FIRST is the first insn of the function being compiled.
738 GLOBAL nonzero means we were called from global_alloc
739 and should attempt to reallocate any pseudoregs that we
740 displace from hard regs we will use for reloads.
741 If GLOBAL is zero, we do not have enough information to do that,
742 so any pseudo reg that is spilled must go to the stack.
744 Return value is TRUE if reload likely left dead insns in the
745 stream and a DCE pass should be run to elimiante them. Else the
746 return value is FALSE. */
749 reload (rtx_insn
*first
, int global
)
753 struct elim_table
*ep
;
757 /* Make sure even insns with volatile mem refs are recognizable. */
762 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
764 /* Make sure that the last insn in the chain
765 is not something that needs reloading. */
766 emit_note (NOTE_INSN_DELETED
);
768 /* Enable find_equiv_reg to distinguish insns made by reload. */
769 reload_first_uid
= get_max_uid ();
771 /* Initialize the secondary memory table. */
772 clear_secondary_mem ();
774 /* We don't have a stack slot for any spill reg yet. */
775 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
776 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
778 /* Initialize the save area information for caller-save, in case some
782 /* Compute which hard registers are now in use
783 as homes for pseudo registers.
784 This is done here rather than (eg) in global_alloc
785 because this point is reached even if not optimizing. */
786 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
789 /* A function that has a nonlocal label that can reach the exit
790 block via non-exceptional paths must save all call-saved
792 if (cfun
->has_nonlocal_label
793 && has_nonexceptional_receiver ())
794 crtl
->saves_all_registers
= 1;
796 if (crtl
->saves_all_registers
)
797 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
798 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
799 df_set_regs_ever_live (i
, true);
801 /* Find all the pseudo registers that didn't get hard regs
802 but do have known equivalent constants or memory slots.
803 These include parameters (known equivalent to parameter slots)
804 and cse'd or loop-moved constant memory addresses.
806 Record constant equivalents in reg_equiv_constant
807 so they will be substituted by find_reloads.
808 Record memory equivalents in reg_mem_equiv so they can
809 be substituted eventually by altering the REG-rtx's. */
812 reg_old_renumber
= XCNEWVEC (short, max_regno
);
813 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
814 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
815 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
817 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
819 init_eliminable_invariants (first
, true);
822 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
823 stack slots to the pseudos that lack hard regs or equivalents.
824 Do not touch virtual registers. */
826 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
827 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
828 temp_pseudo_reg_arr
[n
++] = i
;
831 /* Ask IRA to order pseudo-registers for better stack slot
833 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_mode
);
835 for (i
= 0; i
< n
; i
++)
836 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
838 /* If we have some registers we think can be eliminated, scan all insns to
839 see if there is an insn that sets one of these registers to something
840 other than itself plus a constant. If so, the register cannot be
841 eliminated. Doing this scan here eliminates an extra pass through the
842 main reload loop in the most common case where register elimination
844 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
846 note_pattern_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
848 maybe_fix_stack_asms ();
850 insns_need_reload
= 0;
851 something_needs_elimination
= 0;
853 /* Initialize to -1, which means take the first spill register. */
856 /* Spill any hard regs that we know we can't eliminate. */
857 CLEAR_HARD_REG_SET (used_spill_regs
);
858 /* There can be multiple ways to eliminate a register;
859 they should be listed adjacently.
860 Elimination for any register fails only if all possible ways fail. */
861 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
864 int can_eliminate
= 0;
867 can_eliminate
|= ep
->can_eliminate
;
870 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
872 spill_hard_reg (from
, 1);
875 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
&& frame_pointer_needed
)
876 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
878 finish_spills (global
);
880 /* From now on, we may need to generate moves differently. We may also
881 allow modifications of insns which cause them to not be recognized.
882 Any such modifications will be cleaned up during reload itself. */
883 reload_in_progress
= 1;
885 /* This loop scans the entire function each go-round
886 and repeats until one repetition spills no additional hard regs. */
889 int something_changed
;
890 poly_int64 starting_frame_size
;
892 starting_frame_size
= get_frame_size ();
893 something_was_spilled
= false;
895 set_initial_elim_offsets ();
896 set_initial_label_offsets ();
898 /* For each pseudo register that has an equivalent location defined,
899 try to eliminate any eliminable registers (such as the frame pointer)
900 assuming initial offsets for the replacement register, which
903 If the resulting location is directly addressable, substitute
904 the MEM we just got directly for the old REG.
906 If it is not addressable but is a constant or the sum of a hard reg
907 and constant, it is probably not addressable because the constant is
908 out of range, in that case record the address; we will generate
909 hairy code to compute the address in a register each time it is
910 needed. Similarly if it is a hard register, but one that is not
911 valid as an address register.
913 If the location is not addressable, but does not have one of the
914 above forms, assign a stack slot. We have to do this to avoid the
915 potential of producing lots of reloads if, e.g., a location involves
916 a pseudo that didn't get a hard register and has an equivalent memory
917 location that also involves a pseudo that didn't get a hard register.
919 Perhaps at some point we will improve reload_when_needed handling
920 so this problem goes away. But that's very hairy. */
922 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
923 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
925 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
928 if (strict_memory_address_addr_space_p
929 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
931 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
932 else if (CONSTANT_P (XEXP (x
, 0))
933 || (REG_P (XEXP (x
, 0))
934 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
935 || (GET_CODE (XEXP (x
, 0)) == PLUS
936 && REG_P (XEXP (XEXP (x
, 0), 0))
937 && (REGNO (XEXP (XEXP (x
, 0), 0))
938 < FIRST_PSEUDO_REGISTER
)
939 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
940 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
943 /* Make a new stack slot. Then indicate that something
944 changed so we go back and recompute offsets for
945 eliminable registers because the allocation of memory
946 below might change some offset. reg_equiv_{mem,address}
947 will be set up for this pseudo on the next pass around
949 reg_equiv_memory_loc (i
) = 0;
950 reg_equiv_init (i
) = 0;
951 alter_reg (i
, -1, true);
955 if (caller_save_needed
)
958 if (maybe_ne (starting_frame_size
, 0) && crtl
->stack_alignment_needed
)
960 /* If we have a stack frame, we must align it now. The
961 stack size may be a part of the offset computation for
962 register elimination. So if this changes the stack size,
963 then repeat the elimination bookkeeping. We don't
964 realign when there is no stack, as that will cause a
965 stack frame when none is needed should
966 TARGET_STARTING_FRAME_OFFSET not be already aligned to
968 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
970 /* If we allocated another stack slot, redo elimination bookkeeping. */
971 if (something_was_spilled
972 || maybe_ne (starting_frame_size
, get_frame_size ()))
974 if (update_eliminables_and_spill ())
979 if (caller_save_needed
)
981 save_call_clobbered_regs ();
982 /* That might have allocated new insn_chain structures. */
983 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
986 calculate_needs_all_insns (global
);
988 if (! ira_conflicts_p
)
989 /* Don't do it for IRA. We need this info because we don't
990 change live_throughout and dead_or_set for chains when IRA
992 CLEAR_REG_SET (&spilled_pseudos
);
994 something_changed
= 0;
996 /* If we allocated any new memory locations, make another pass
997 since it might have changed elimination offsets. */
998 if (something_was_spilled
999 || maybe_ne (starting_frame_size
, get_frame_size ()))
1000 something_changed
= 1;
1002 /* Even if the frame size remained the same, we might still have
1003 changed elimination offsets, e.g. if find_reloads called
1004 force_const_mem requiring the back end to allocate a constant
1005 pool base register that needs to be saved on the stack. */
1006 else if (!verify_initial_elim_offsets ())
1007 something_changed
= 1;
1009 if (update_eliminables_and_spill ())
1012 something_changed
= 1;
1016 select_reload_regs ();
1019 if (insns_need_reload
)
1020 something_changed
|= finish_spills (global
);
1023 if (! something_changed
)
1026 if (caller_save_needed
)
1027 delete_caller_save_insns ();
1029 obstack_free (&reload_obstack
, reload_firstobj
);
1032 /* If global-alloc was run, notify it of any register eliminations we have
1035 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1036 if (ep
->can_eliminate
)
1037 mark_elimination (ep
->from
, ep
->to
);
1039 remove_init_insns ();
1041 /* Use the reload registers where necessary
1042 by generating move instructions to move the must-be-register
1043 values into or out of the reload registers. */
1045 if (insns_need_reload
!= 0 || something_needs_elimination
1046 || something_needs_operands_changed
)
1048 poly_int64 old_frame_size
= get_frame_size ();
1050 reload_as_needed (global
);
1052 gcc_assert (known_eq (old_frame_size
, get_frame_size ()));
1054 gcc_assert (verify_initial_elim_offsets ());
1057 /* If we were able to eliminate the frame pointer, show that it is no
1058 longer live at the start of any basic block. If it ls live by
1059 virtue of being in a pseudo, that pseudo will be marked live
1060 and hence the frame pointer will be known to be live via that
1063 if (! frame_pointer_needed
)
1064 FOR_EACH_BB_FN (bb
, cfun
)
1065 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1067 /* Come here (with failure set nonzero) if we can't get enough spill
1071 CLEAR_REG_SET (&changed_allocation_pseudos
);
1072 CLEAR_REG_SET (&spilled_pseudos
);
1073 reload_in_progress
= 0;
1075 /* Now eliminate all pseudo regs by modifying them into
1076 their equivalent memory references.
1077 The REG-rtx's for the pseudos are modified in place,
1078 so all insns that used to refer to them now refer to memory.
1080 For a reg that has a reg_equiv_address, all those insns
1081 were changed by reloading so that no insns refer to it any longer;
1082 but the DECL_RTL of a variable decl may refer to it,
1083 and if so this causes the debugging info to mention the variable. */
1085 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1089 if (reg_equiv_mem (i
))
1090 addr
= XEXP (reg_equiv_mem (i
), 0);
1092 if (reg_equiv_address (i
))
1093 addr
= reg_equiv_address (i
);
1097 if (reg_renumber
[i
] < 0)
1099 rtx reg
= regno_reg_rtx
[i
];
1101 REG_USERVAR_P (reg
) = 0;
1102 PUT_CODE (reg
, MEM
);
1103 XEXP (reg
, 0) = addr
;
1104 if (reg_equiv_memory_loc (i
))
1105 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1107 MEM_ATTRS (reg
) = 0;
1108 MEM_NOTRAP_P (reg
) = 1;
1110 else if (reg_equiv_mem (i
))
1111 XEXP (reg_equiv_mem (i
), 0) = addr
;
1114 /* We don't want complex addressing modes in debug insns
1115 if simpler ones will do, so delegitimize equivalences
1117 if (MAY_HAVE_DEBUG_BIND_INSNS
&& reg_renumber
[i
] < 0)
1119 rtx reg
= regno_reg_rtx
[i
];
1123 if (reg_equiv_constant (i
))
1124 equiv
= reg_equiv_constant (i
);
1125 else if (reg_equiv_invariant (i
))
1126 equiv
= reg_equiv_invariant (i
);
1127 else if (reg
&& MEM_P (reg
))
1128 equiv
= targetm
.delegitimize_address (reg
);
1129 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1135 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1137 insn
= DF_REF_INSN (use
);
1139 /* Make sure the next ref is for a different instruction,
1140 so that we're not affected by the rescan. */
1141 next
= DF_REF_NEXT_REG (use
);
1142 while (next
&& DF_REF_INSN (next
) == insn
)
1143 next
= DF_REF_NEXT_REG (next
);
1145 if (DEBUG_BIND_INSN_P (insn
))
1149 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1150 df_insn_rescan_debug_internal (insn
);
1153 INSN_VAR_LOCATION_LOC (insn
)
1154 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1161 /* We must set reload_completed now since the cleanup_subreg_operands call
1162 below will re-recognize each insn and reload may have generated insns
1163 which are only valid during and after reload. */
1164 reload_completed
= 1;
1166 /* Make a pass over all the insns and delete all USEs which we inserted
1167 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1168 notes. Delete all CLOBBER insns, except those that refer to the return
1169 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1170 from misarranging variable-array code, and simplify (subreg (reg))
1171 operands. Strip and regenerate REG_INC notes that may have been moved
1174 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1180 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1181 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1183 if ((GET_CODE (PATTERN (insn
)) == USE
1184 /* We mark with QImode USEs introduced by reload itself. */
1185 && (GET_MODE (insn
) == QImode
1186 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1187 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1188 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1189 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1190 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1191 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1192 != stack_pointer_rtx
))
1193 && (!REG_P (XEXP (PATTERN (insn
), 0))
1194 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1200 /* Some CLOBBERs may survive until here and still reference unassigned
1201 pseudos with const equivalent, which may in turn cause ICE in later
1202 passes if the reference remains in place. */
1203 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1204 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1205 VOIDmode
, PATTERN (insn
));
1207 /* Discard obvious no-ops, even without -O. This optimization
1208 is fast and doesn't interfere with debugging. */
1209 if (NONJUMP_INSN_P (insn
)
1210 && GET_CODE (PATTERN (insn
)) == SET
1211 && REG_P (SET_SRC (PATTERN (insn
)))
1212 && REG_P (SET_DEST (PATTERN (insn
)))
1213 && (REGNO (SET_SRC (PATTERN (insn
)))
1214 == REGNO (SET_DEST (PATTERN (insn
)))))
1220 pnote
= ®_NOTES (insn
);
1223 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1224 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1225 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1226 *pnote
= XEXP (*pnote
, 1);
1228 pnote
= &XEXP (*pnote
, 1);
1232 add_auto_inc_notes (insn
, PATTERN (insn
));
1234 /* Simplify (subreg (reg)) if it appears as an operand. */
1235 cleanup_subreg_operands (insn
);
1237 /* Clean up invalid ASMs so that they don't confuse later passes.
1239 if (asm_noperands (PATTERN (insn
)) >= 0)
1241 extract_insn (insn
);
1242 if (!constrain_operands (1, get_enabled_alternatives (insn
)))
1244 error_for_asm (insn
,
1245 "%<asm%> operand has impossible constraints");
1252 free (temp_pseudo_reg_arr
);
1254 /* Indicate that we no longer have known memory locations or constants. */
1257 free (reg_max_ref_mode
);
1258 free (reg_old_renumber
);
1259 free (pseudo_previous_regs
);
1260 free (pseudo_forbidden_regs
);
1262 CLEAR_HARD_REG_SET (used_spill_regs
);
1263 for (i
= 0; i
< n_spills
; i
++)
1264 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1266 /* Free all the insn_chain structures at once. */
1267 obstack_free (&reload_obstack
, reload_startobj
);
1268 unused_insn_chains
= 0;
1270 inserted
= fixup_abnormal_edges ();
1272 /* We've possibly turned single trapping insn into multiple ones. */
1273 if (cfun
->can_throw_non_call_exceptions
)
1275 auto_sbitmap
blocks (last_basic_block_for_fn (cfun
));
1276 bitmap_ones (blocks
);
1277 find_many_sub_basic_blocks (blocks
);
1281 commit_edge_insertions ();
1283 /* Replacing pseudos with their memory equivalents might have
1284 created shared rtx. Subsequent passes would get confused
1285 by this, so unshare everything here. */
1286 unshare_all_rtl_again (first
);
1288 #ifdef STACK_BOUNDARY
1289 /* init_emit has set the alignment of the hard frame pointer
1290 to STACK_BOUNDARY. It is very likely no longer valid if
1291 the hard frame pointer was used for register allocation. */
1292 if (!frame_pointer_needed
)
1293 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1296 substitute_stack
.release ();
1298 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1300 reload_completed
= !failure
;
1305 /* Yet another special case. Unfortunately, reg-stack forces people to
1306 write incorrect clobbers in asm statements. These clobbers must not
1307 cause the register to appear in bad_spill_regs, otherwise we'll call
1308 fatal_insn later. We clear the corresponding regnos in the live
1309 register sets to avoid this.
1310 The whole thing is rather sick, I'm afraid. */
1313 maybe_fix_stack_asms (void)
1316 const char *constraints
[MAX_RECOG_OPERANDS
];
1317 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1318 class insn_chain
*chain
;
1320 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1323 HARD_REG_SET clobbered
, allowed
;
1326 if (! INSN_P (chain
->insn
)
1327 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1329 pat
= PATTERN (chain
->insn
);
1330 if (GET_CODE (pat
) != PARALLEL
)
1333 CLEAR_HARD_REG_SET (clobbered
);
1334 CLEAR_HARD_REG_SET (allowed
);
1336 /* First, make a mask of all stack regs that are clobbered. */
1337 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1339 rtx t
= XVECEXP (pat
, 0, i
);
1340 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1341 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1342 /* CLOBBER_HIGH is only supported for LRA. */
1343 gcc_assert (GET_CODE (t
) != CLOBBER_HIGH
);
1346 /* Get the operand values and constraints out of the insn. */
1347 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1348 constraints
, operand_mode
, NULL
);
1350 /* For every operand, see what registers are allowed. */
1351 for (i
= 0; i
< noperands
; i
++)
1353 const char *p
= constraints
[i
];
1354 /* For every alternative, we compute the class of registers allowed
1355 for reloading in CLS, and merge its contents into the reg set
1357 int cls
= (int) NO_REGS
;
1363 if (c
== '\0' || c
== ',' || c
== '#')
1365 /* End of one alternative - mark the regs in the current
1366 class, and reset the class. */
1367 allowed
|= reg_class_contents
[cls
];
1373 } while (c
!= '\0' && c
!= ',');
1382 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1386 enum constraint_num cn
= lookup_constraint (p
);
1387 if (insn_extra_address_constraint (cn
))
1388 cls
= (int) reg_class_subunion
[cls
]
1389 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1392 cls
= (int) reg_class_subunion
[cls
]
1393 [reg_class_for_constraint (cn
)];
1396 p
+= CONSTRAINT_LEN (c
, p
);
1399 /* Those of the registers which are clobbered, but allowed by the
1400 constraints, must be usable as reload registers. So clear them
1401 out of the life information. */
1402 allowed
&= clobbered
;
1403 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1404 if (TEST_HARD_REG_BIT (allowed
, i
))
1406 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1407 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1414 /* Copy the global variables n_reloads and rld into the corresponding elts
1417 copy_reloads (class insn_chain
*chain
)
1419 chain
->n_reloads
= n_reloads
;
1420 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1421 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1422 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1425 /* Walk the chain of insns, and determine for each whether it needs reloads
1426 and/or eliminations. Build the corresponding insns_need_reload list, and
1427 set something_needs_elimination as appropriate. */
1429 calculate_needs_all_insns (int global
)
1431 class insn_chain
**pprev_reload
= &insns_need_reload
;
1432 class insn_chain
*chain
, *next
= 0;
1434 something_needs_elimination
= 0;
1436 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1437 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1439 rtx_insn
*insn
= chain
->insn
;
1443 /* Clear out the shortcuts. */
1444 chain
->n_reloads
= 0;
1445 chain
->need_elim
= 0;
1446 chain
->need_reload
= 0;
1447 chain
->need_operand_change
= 0;
1449 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1450 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1451 what effects this has on the known offsets at labels. */
1453 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1454 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1455 set_label_offsets (insn
, insn
, 0);
1459 rtx old_body
= PATTERN (insn
);
1460 int old_code
= INSN_CODE (insn
);
1461 rtx old_notes
= REG_NOTES (insn
);
1462 int did_elimination
= 0;
1463 int operands_changed
= 0;
1465 /* Skip insns that only set an equivalence. */
1466 if (will_delete_init_insn_p (insn
))
1469 /* If needed, eliminate any eliminable registers. */
1470 if (num_eliminable
|| num_eliminable_invariants
)
1471 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1473 /* Analyze the instruction. */
1474 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1475 global
, spill_reg_order
);
1477 /* If a no-op set needs more than one reload, this is likely
1478 to be something that needs input address reloads. We
1479 can't get rid of this cleanly later, and it is of no use
1480 anyway, so discard it now.
1481 We only do this when expensive_optimizations is enabled,
1482 since this complements reload inheritance / output
1483 reload deletion, and it can make debugging harder. */
1484 if (flag_expensive_optimizations
&& n_reloads
> 1)
1486 rtx set
= single_set (insn
);
1489 ((SET_SRC (set
) == SET_DEST (set
)
1490 && REG_P (SET_SRC (set
))
1491 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1492 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1493 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1494 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1495 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1496 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1497 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1498 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1500 if (ira_conflicts_p
)
1501 /* Inform IRA about the insn deletion. */
1502 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1503 REGNO (SET_SRC (set
)));
1505 /* Delete it from the reload chain. */
1507 chain
->prev
->next
= next
;
1509 reload_insn_chain
= next
;
1511 next
->prev
= chain
->prev
;
1512 chain
->next
= unused_insn_chains
;
1513 unused_insn_chains
= chain
;
1518 update_eliminable_offsets ();
1520 /* Remember for later shortcuts which insns had any reloads or
1521 register eliminations. */
1522 chain
->need_elim
= did_elimination
;
1523 chain
->need_reload
= n_reloads
> 0;
1524 chain
->need_operand_change
= operands_changed
;
1526 /* Discard any register replacements done. */
1527 if (did_elimination
)
1529 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1530 PATTERN (insn
) = old_body
;
1531 INSN_CODE (insn
) = old_code
;
1532 REG_NOTES (insn
) = old_notes
;
1533 something_needs_elimination
= 1;
1536 something_needs_operands_changed
|= operands_changed
;
1540 copy_reloads (chain
);
1541 *pprev_reload
= chain
;
1542 pprev_reload
= &chain
->next_need_reload
;
1549 /* This function is called from the register allocator to set up estimates
1550 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1551 an invariant. The structure is similar to calculate_needs_all_insns. */
1554 calculate_elim_costs_all_insns (void)
1556 int *reg_equiv_init_cost
;
1560 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1562 init_eliminable_invariants (get_insns (), false);
1564 set_initial_elim_offsets ();
1565 set_initial_label_offsets ();
1567 FOR_EACH_BB_FN (bb
, cfun
)
1572 FOR_BB_INSNS (bb
, insn
)
1574 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1575 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1576 what effects this has on the known offsets at labels. */
1578 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1579 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1580 set_label_offsets (insn
, insn
, 0);
1584 rtx set
= single_set (insn
);
1586 /* Skip insns that only set an equivalence. */
1587 if (set
&& REG_P (SET_DEST (set
))
1588 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1589 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1590 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1592 unsigned regno
= REGNO (SET_DEST (set
));
1593 rtx_insn_list
*init
= reg_equiv_init (regno
);
1596 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1598 machine_mode mode
= GET_MODE (SET_DEST (set
));
1599 int cost
= set_src_cost (t
, mode
,
1600 optimize_bb_for_speed_p (bb
));
1601 int freq
= REG_FREQ_FROM_BB (bb
);
1603 reg_equiv_init_cost
[regno
] = cost
* freq
;
1607 /* If needed, eliminate any eliminable registers. */
1608 if (num_eliminable
|| num_eliminable_invariants
)
1609 elimination_costs_in_insn (insn
);
1612 update_eliminable_offsets ();
1616 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1618 if (reg_equiv_invariant (i
))
1620 if (reg_equiv_init (i
))
1622 int cost
= reg_equiv_init_cost
[i
];
1625 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1627 ira_adjust_equiv_reg_cost (i
, cost
);
1633 "Reg %d had equivalence, but can't be eliminated\n",
1635 ira_adjust_equiv_reg_cost (i
, 0);
1640 free (reg_equiv_init_cost
);
1641 free (offsets_known_at
);
1644 offsets_known_at
= NULL
;
1647 /* Comparison function for qsort to decide which of two reloads
1648 should be handled first. *P1 and *P2 are the reload numbers. */
1651 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1653 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1656 /* Consider required reloads before optional ones. */
1657 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1661 /* Count all solitary classes before non-solitary ones. */
1662 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1663 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1667 /* Aside from solitaires, consider all multi-reg groups first. */
1668 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1672 /* Consider reloads in order of increasing reg-class number. */
1673 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1677 /* If reloads are equally urgent, sort by reload number,
1678 so that the results of qsort leave nothing to chance. */
1682 /* The cost of spilling each hard reg. */
1683 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1685 /* When spilling multiple hard registers, we use SPILL_COST for the first
1686 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1687 only the first hard reg for a multi-reg pseudo. */
1688 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1690 /* Map of hard regno to pseudo regno currently occupying the hard
1692 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1694 /* Update the spill cost arrays, considering that pseudo REG is live. */
1697 count_pseudo (int reg
)
1699 int freq
= REG_FREQ (reg
);
1700 int r
= reg_renumber
[reg
];
1703 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1704 if (ira_conflicts_p
&& r
< 0)
1707 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1708 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1711 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1713 gcc_assert (r
>= 0);
1715 spill_add_cost
[r
] += freq
;
1716 nregs
= hard_regno_nregs (r
, PSEUDO_REGNO_MODE (reg
));
1719 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1720 spill_cost
[r
+ nregs
] += freq
;
1724 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1725 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1728 order_regs_for_reload (class insn_chain
*chain
)
1731 HARD_REG_SET used_by_pseudos
;
1732 HARD_REG_SET used_by_pseudos2
;
1733 reg_set_iterator rsi
;
1735 bad_spill_regs
= fixed_reg_set
;
1737 memset (spill_cost
, 0, sizeof spill_cost
);
1738 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1739 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1740 hard_regno_to_pseudo_regno
[i
] = -1;
1742 /* Count number of uses of each hard reg by pseudo regs allocated to it
1743 and then order them by decreasing use. First exclude hard registers
1744 that are live in or across this insn. */
1746 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1747 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1748 bad_spill_regs
|= used_by_pseudos
;
1749 bad_spill_regs
|= used_by_pseudos2
;
1751 /* Now find out which pseudos are allocated to it, and update
1753 CLEAR_REG_SET (&pseudos_counted
);
1755 EXECUTE_IF_SET_IN_REG_SET
1756 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1760 EXECUTE_IF_SET_IN_REG_SET
1761 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1765 CLEAR_REG_SET (&pseudos_counted
);
1768 /* Vector of reload-numbers showing the order in which the reloads should
1770 static short reload_order
[MAX_RELOADS
];
1772 /* This is used to keep track of the spill regs used in one insn. */
1773 static HARD_REG_SET used_spill_regs_local
;
1775 /* We decided to spill hard register SPILLED, which has a size of
1776 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1777 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1778 update SPILL_COST/SPILL_ADD_COST. */
1781 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1783 int freq
= REG_FREQ (reg
);
1784 int r
= reg_renumber
[reg
];
1787 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1788 if (ira_conflicts_p
&& r
< 0)
1791 gcc_assert (r
>= 0);
1793 nregs
= hard_regno_nregs (r
, PSEUDO_REGNO_MODE (reg
));
1795 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1796 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1799 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1801 spill_add_cost
[r
] -= freq
;
1804 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1805 spill_cost
[r
+ nregs
] -= freq
;
1809 /* Find reload register to use for reload number ORDER. */
1812 find_reg (class insn_chain
*chain
, int order
)
1814 int rnum
= reload_order
[order
];
1815 struct reload
*rl
= rld
+ rnum
;
1816 int best_cost
= INT_MAX
;
1818 unsigned int i
, j
, n
;
1820 HARD_REG_SET not_usable
;
1821 HARD_REG_SET used_by_other_reload
;
1822 reg_set_iterator rsi
;
1823 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1824 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1826 not_usable
= (bad_spill_regs
1827 | bad_spill_regs_global
1828 | ~reg_class_contents
[rl
->rclass
]);
1830 CLEAR_HARD_REG_SET (used_by_other_reload
);
1831 for (k
= 0; k
< order
; k
++)
1833 int other
= reload_order
[k
];
1835 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1836 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1837 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1840 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1842 #ifdef REG_ALLOC_ORDER
1843 unsigned int regno
= reg_alloc_order
[i
];
1845 unsigned int regno
= i
;
1848 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1849 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1850 && targetm
.hard_regno_mode_ok (regno
, rl
->mode
))
1852 int this_cost
= spill_cost
[regno
];
1854 unsigned int this_nregs
= hard_regno_nregs (regno
, rl
->mode
);
1856 for (j
= 1; j
< this_nregs
; j
++)
1858 this_cost
+= spill_add_cost
[regno
+ j
];
1859 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1860 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1866 if (ira_conflicts_p
)
1868 /* Ask IRA to find a better pseudo-register for
1870 for (n
= j
= 0; j
< this_nregs
; j
++)
1872 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1876 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1877 regno_pseudo_regs
[n
++] = r
;
1879 regno_pseudo_regs
[n
++] = -1;
1881 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1882 best_regno_pseudo_regs
,
1889 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1890 if (regno_pseudo_regs
[j
] < 0)
1897 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1899 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1901 if (this_cost
< best_cost
1902 /* Among registers with equal cost, prefer caller-saved ones, or
1903 use REG_ALLOC_ORDER if it is defined. */
1904 || (this_cost
== best_cost
1905 #ifdef REG_ALLOC_ORDER
1906 && (inv_reg_alloc_order
[regno
]
1907 < inv_reg_alloc_order
[best_reg
])
1909 && call_used_regs
[regno
]
1910 && ! call_used_regs
[best_reg
]
1915 best_cost
= this_cost
;
1923 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1925 rl
->nregs
= hard_regno_nregs (best_reg
, rl
->mode
);
1926 rl
->regno
= best_reg
;
1928 EXECUTE_IF_SET_IN_REG_SET
1929 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1931 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1934 EXECUTE_IF_SET_IN_REG_SET
1935 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1937 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1940 for (i
= 0; i
< rl
->nregs
; i
++)
1942 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1943 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1944 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1945 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1950 /* Find more reload regs to satisfy the remaining need of an insn, which
1952 Do it by ascending class number, since otherwise a reg
1953 might be spilled for a big class and might fail to count
1954 for a smaller class even though it belongs to that class. */
1957 find_reload_regs (class insn_chain
*chain
)
1961 /* In order to be certain of getting the registers we need,
1962 we must sort the reloads into order of increasing register class.
1963 Then our grabbing of reload registers will parallel the process
1964 that provided the reload registers. */
1965 for (i
= 0; i
< chain
->n_reloads
; i
++)
1967 /* Show whether this reload already has a hard reg. */
1968 if (chain
->rld
[i
].reg_rtx
)
1970 chain
->rld
[i
].regno
= REGNO (chain
->rld
[i
].reg_rtx
);
1971 chain
->rld
[i
].nregs
= REG_NREGS (chain
->rld
[i
].reg_rtx
);
1974 chain
->rld
[i
].regno
= -1;
1975 reload_order
[i
] = i
;
1978 n_reloads
= chain
->n_reloads
;
1979 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
1981 CLEAR_HARD_REG_SET (used_spill_regs_local
);
1984 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
1986 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
1988 /* Compute the order of preference for hard registers to spill. */
1990 order_regs_for_reload (chain
);
1992 for (i
= 0; i
< n_reloads
; i
++)
1994 int r
= reload_order
[i
];
1996 /* Ignore reloads that got marked inoperative. */
1997 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
1998 && ! rld
[r
].optional
1999 && rld
[r
].regno
== -1)
2000 if (! find_reg (chain
, i
))
2003 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2004 spill_failure (chain
->insn
, rld
[r
].rclass
);
2010 chain
->used_spill_regs
= used_spill_regs_local
;
2011 used_spill_regs
|= used_spill_regs_local
;
2013 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2017 select_reload_regs (void)
2019 class insn_chain
*chain
;
2021 /* Try to satisfy the needs for each insn. */
2022 for (chain
= insns_need_reload
; chain
!= 0;
2023 chain
= chain
->next_need_reload
)
2024 find_reload_regs (chain
);
2027 /* Delete all insns that were inserted by emit_caller_save_insns during
2030 delete_caller_save_insns (void)
2032 class insn_chain
*c
= reload_insn_chain
;
2036 while (c
!= 0 && c
->is_caller_save_insn
)
2038 class insn_chain
*next
= c
->next
;
2039 rtx_insn
*insn
= c
->insn
;
2041 if (c
== reload_insn_chain
)
2042 reload_insn_chain
= next
;
2046 next
->prev
= c
->prev
;
2048 c
->prev
->next
= next
;
2049 c
->next
= unused_insn_chains
;
2050 unused_insn_chains
= c
;
2058 /* Handle the failure to find a register to spill.
2059 INSN should be one of the insns which needed this particular spill reg. */
2062 spill_failure (rtx_insn
*insn
, enum reg_class rclass
)
2064 if (asm_noperands (PATTERN (insn
)) >= 0)
2065 error_for_asm (insn
, "cannot find a register in class %qs while "
2066 "reloading %<asm%>",
2067 reg_class_names
[rclass
]);
2070 error ("unable to find a register to spill in class %qs",
2071 reg_class_names
[rclass
]);
2075 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2076 debug_reload_to_stream (dump_file
);
2078 fatal_insn ("this is the insn:", insn
);
2082 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2083 data that is dead in INSN. */
2086 delete_dead_insn (rtx_insn
*insn
)
2088 rtx_insn
*prev
= prev_active_insn (insn
);
2091 /* If the previous insn sets a register that dies in our insn make
2092 a note that we want to run DCE immediately after reload.
2094 We used to delete the previous insn & recurse, but that's wrong for
2095 block local equivalences. Instead of trying to figure out the exact
2096 circumstances where we can delete the potentially dead insns, just
2097 let DCE do the job. */
2098 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2099 && GET_CODE (PATTERN (prev
)) == SET
2100 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2101 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2102 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2103 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2106 SET_INSN_DELETED (insn
);
2109 /* Modify the home of pseudo-reg I.
2110 The new home is present in reg_renumber[I].
2112 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2113 or it may be -1, meaning there is none or it is not relevant.
2114 This is used so that all pseudos spilled from a given hard reg
2115 can share one stack slot. */
2118 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2120 /* When outputting an inline function, this can happen
2121 for a reg that isn't actually used. */
2122 if (regno_reg_rtx
[i
] == 0)
2125 /* If the reg got changed to a MEM at rtl-generation time,
2127 if (!REG_P (regno_reg_rtx
[i
]))
2130 /* Modify the reg-rtx to contain the new hard reg
2131 number or else to contain its pseudo reg number. */
2132 SET_REGNO (regno_reg_rtx
[i
],
2133 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2135 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2136 allocate a stack slot for it. */
2138 if (reg_renumber
[i
] < 0
2139 && REG_N_REFS (i
) > 0
2140 && reg_equiv_constant (i
) == 0
2141 && (reg_equiv_invariant (i
) == 0
2142 || reg_equiv_init (i
) == 0)
2143 && reg_equiv_memory_loc (i
) == 0)
2146 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2147 poly_uint64 inherent_size
= GET_MODE_SIZE (mode
);
2148 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2149 machine_mode wider_mode
= wider_subreg_mode (mode
, reg_max_ref_mode
[i
]);
2150 poly_uint64 total_size
= GET_MODE_SIZE (wider_mode
);
2151 /* ??? Seems strange to derive the minimum alignment from the size,
2152 but that's the traditional behavior. For polynomial-size modes,
2153 the natural extension is to use the minimum possible size. */
2154 unsigned int min_align
2155 = constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode
[i
]));
2156 poly_int64 adjust
= 0;
2158 something_was_spilled
= true;
2160 if (ira_conflicts_p
)
2162 /* Mark the spill for IRA. */
2163 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2165 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2171 /* Each pseudo reg has an inherent size which comes from its own mode,
2172 and a total size which provides room for paradoxical subregs
2173 which refer to the pseudo reg in wider modes.
2175 We can use a slot already allocated if it provides both
2176 enough inherent space and enough total space.
2177 Otherwise, we allocate a new slot, making sure that it has no less
2178 inherent space, and no less total space, then the previous slot. */
2179 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2183 /* The sizes are taken from a subreg operation, which guarantees
2184 that they're ordered. */
2185 gcc_checking_assert (ordered_p (total_size
, inherent_size
));
2187 /* No known place to spill from => no slot to reuse. */
2188 x
= assign_stack_local (mode
, total_size
,
2189 min_align
> inherent_align
2190 || maybe_gt (total_size
, inherent_size
)
2195 /* Cancel the big-endian correction done in assign_stack_local.
2196 Get the address of the beginning of the slot. This is so we
2197 can do a big-endian correction unconditionally below. */
2198 if (BYTES_BIG_ENDIAN
)
2200 adjust
= inherent_size
- total_size
;
2201 if (maybe_ne (adjust
, 0))
2203 poly_uint64 total_bits
= total_size
* BITS_PER_UNIT
;
2204 machine_mode mem_mode
2205 = int_mode_for_size (total_bits
, 1).else_blk ();
2206 stack_slot
= adjust_address_nv (x
, mem_mode
, adjust
);
2210 if (! dont_share_p
&& ira_conflicts_p
)
2211 /* Inform IRA about allocation a new stack slot. */
2212 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2215 /* Reuse a stack slot if possible. */
2216 else if (spill_stack_slot
[from_reg
] != 0
2217 && known_ge (spill_stack_slot_width
[from_reg
], total_size
)
2218 && known_ge (GET_MODE_SIZE
2219 (GET_MODE (spill_stack_slot
[from_reg
])),
2221 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2222 x
= spill_stack_slot
[from_reg
];
2224 /* Allocate a bigger slot. */
2227 /* Compute maximum size needed, both for inherent size
2228 and for total size. */
2231 if (spill_stack_slot
[from_reg
])
2233 if (partial_subreg_p (mode
,
2234 GET_MODE (spill_stack_slot
[from_reg
])))
2235 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2236 total_size
= ordered_max (total_size
,
2237 spill_stack_slot_width
[from_reg
]);
2238 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2239 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2242 /* The sizes are taken from a subreg operation, which guarantees
2243 that they're ordered. */
2244 gcc_checking_assert (ordered_p (total_size
, inherent_size
));
2246 /* Make a slot with that size. */
2247 x
= assign_stack_local (mode
, total_size
,
2248 min_align
> inherent_align
2249 || maybe_gt (total_size
, inherent_size
)
2253 /* Cancel the big-endian correction done in assign_stack_local.
2254 Get the address of the beginning of the slot. This is so we
2255 can do a big-endian correction unconditionally below. */
2256 if (BYTES_BIG_ENDIAN
)
2258 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2259 if (maybe_ne (adjust
, 0))
2261 poly_uint64 total_bits
= total_size
* BITS_PER_UNIT
;
2262 machine_mode mem_mode
2263 = int_mode_for_size (total_bits
, 1).else_blk ();
2264 stack_slot
= adjust_address_nv (x
, mem_mode
, adjust
);
2268 spill_stack_slot
[from_reg
] = stack_slot
;
2269 spill_stack_slot_width
[from_reg
] = total_size
;
2272 /* On a big endian machine, the "address" of the slot
2273 is the address of the low part that fits its inherent mode. */
2274 adjust
+= subreg_size_lowpart_offset (inherent_size
, total_size
);
2276 /* If we have any adjustment to make, or if the stack slot is the
2277 wrong mode, make a new stack slot. */
2278 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2280 /* Set all of the memory attributes as appropriate for a spill. */
2281 set_mem_attrs_for_spill (x
);
2283 /* Save the stack slot for later. */
2284 reg_equiv_memory_loc (i
) = x
;
2288 /* Mark the slots in regs_ever_live for the hard regs used by
2289 pseudo-reg number REGNO, accessed in MODE. */
2292 mark_home_live_1 (int regno
, machine_mode mode
)
2296 i
= reg_renumber
[regno
];
2299 lim
= end_hard_regno (mode
, i
);
2301 df_set_regs_ever_live (i
++, true);
2304 /* Mark the slots in regs_ever_live for the hard regs
2305 used by pseudo-reg number REGNO. */
2308 mark_home_live (int regno
)
2310 if (reg_renumber
[regno
] >= 0)
2311 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2314 /* This function handles the tracking of elimination offsets around branches.
2316 X is a piece of RTL being scanned.
2318 INSN is the insn that it came from, if any.
2320 INITIAL_P is nonzero if we are to set the offset to be the initial
2321 offset and zero if we are setting the offset of the label to be the
2325 set_label_offsets (rtx x
, rtx_insn
*insn
, int initial_p
)
2327 enum rtx_code code
= GET_CODE (x
);
2330 struct elim_table
*p
;
2335 if (LABEL_REF_NONLOCAL_P (x
))
2338 x
= label_ref_label (x
);
2343 /* If we know nothing about this label, set the desired offsets. Note
2344 that this sets the offset at a label to be the offset before a label
2345 if we don't know anything about the label. This is not correct for
2346 the label after a BARRIER, but is the best guess we can make. If
2347 we guessed wrong, we will suppress an elimination that might have
2348 been possible had we been able to guess correctly. */
2350 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2352 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2353 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2354 = (initial_p
? reg_eliminate
[i
].initial_offset
2355 : reg_eliminate
[i
].offset
);
2356 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2359 /* Otherwise, if this is the definition of a label and it is
2360 preceded by a BARRIER, set our offsets to the known offset of
2364 && (tem
= prev_nonnote_insn (insn
)) != 0
2366 set_offsets_for_label (insn
);
2368 /* If neither of the above cases is true, compare each offset
2369 with those previously recorded and suppress any eliminations
2370 where the offsets disagree. */
2372 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2373 if (maybe_ne (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
],
2374 (initial_p
? reg_eliminate
[i
].initial_offset
2375 : reg_eliminate
[i
].offset
)))
2376 reg_eliminate
[i
].can_eliminate
= 0;
2380 case JUMP_TABLE_DATA
:
2381 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2385 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2391 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2392 to indirectly and hence must have all eliminations at their
2394 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2395 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2396 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2402 /* Each of the labels in the parallel or address vector must be
2403 at their initial offsets. We want the first field for PARALLEL
2404 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2406 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2407 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2412 /* We only care about setting PC. If the source is not RETURN,
2413 IF_THEN_ELSE, or a label, disable any eliminations not at
2414 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2415 isn't one of those possibilities. For branches to a label,
2416 call ourselves recursively.
2418 Note that this can disable elimination unnecessarily when we have
2419 a non-local goto since it will look like a non-constant jump to
2420 someplace in the current function. This isn't a significant
2421 problem since such jumps will normally be when all elimination
2422 pairs are back to their initial offsets. */
2424 if (SET_DEST (x
) != pc_rtx
)
2427 switch (GET_CODE (SET_SRC (x
)))
2434 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2438 tem
= XEXP (SET_SRC (x
), 1);
2439 if (GET_CODE (tem
) == LABEL_REF
)
2440 set_label_offsets (label_ref_label (tem
), insn
, initial_p
);
2441 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2444 tem
= XEXP (SET_SRC (x
), 2);
2445 if (GET_CODE (tem
) == LABEL_REF
)
2446 set_label_offsets (label_ref_label (tem
), insn
, initial_p
);
2447 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2455 /* If we reach here, all eliminations must be at their initial
2456 offset because we are doing a jump to a variable address. */
2457 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2458 if (maybe_ne (p
->offset
, p
->initial_offset
))
2459 p
->can_eliminate
= 0;
2467 /* This function examines every reg that occurs in X and adjusts the
2468 costs for its elimination which are gathered by IRA. INSN is the
2469 insn in which X occurs. We do not recurse into MEM expressions. */
2472 note_reg_elim_costly (const_rtx x
, rtx insn
)
2474 subrtx_iterator::array_type array
;
2475 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
2477 const_rtx x
= *iter
;
2479 iter
.skip_subrtxes ();
2481 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2482 && reg_equiv_init (REGNO (x
))
2483 && reg_equiv_invariant (REGNO (x
)))
2485 rtx t
= reg_equiv_invariant (REGNO (x
));
2486 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2487 int cost
= set_src_cost (new_rtx
, Pmode
,
2488 optimize_bb_for_speed_p (elim_bb
));
2489 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2492 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2497 /* Scan X and replace any eliminable registers (such as fp) with a
2498 replacement (such as sp), plus an offset.
2500 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2501 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2502 MEM, we are allowed to replace a sum of a register and the constant zero
2503 with the register, which we cannot do outside a MEM. In addition, we need
2504 to record the fact that a register is referenced outside a MEM.
2506 If INSN is an insn, it is the insn containing X. If we replace a REG
2507 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2508 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2509 the REG is being modified.
2511 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2512 That's used when we eliminate in expressions stored in notes.
2513 This means, do not set ref_outside_mem even if the reference
2516 If FOR_COSTS is true, we are being called before reload in order to
2517 estimate the costs of keeping registers with an equivalence unallocated.
2519 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2520 replacements done assuming all offsets are at their initial values. If
2521 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2522 encounter, return the actual location so that find_reloads will do
2523 the proper thing. */
2526 eliminate_regs_1 (rtx x
, machine_mode mem_mode
, rtx insn
,
2527 bool may_use_invariant
, bool for_costs
)
2529 enum rtx_code code
= GET_CODE (x
);
2530 struct elim_table
*ep
;
2537 if (! current_function_decl
)
2557 /* First handle the case where we encounter a bare register that
2558 is eliminable. Replace it with a PLUS. */
2559 if (regno
< FIRST_PSEUDO_REGISTER
)
2561 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2563 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2564 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2567 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2569 && reg_equiv_invariant (regno
))
2571 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2572 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2573 mem_mode
, insn
, true, for_costs
);
2574 /* There exists at least one use of REGNO that cannot be
2575 eliminated. Prevent the defining insn from being deleted. */
2576 reg_equiv_init (regno
) = NULL
;
2578 alter_reg (regno
, -1, true);
2582 /* You might think handling MINUS in a manner similar to PLUS is a
2583 good idea. It is not. It has been tried multiple times and every
2584 time the change has had to have been reverted.
2586 Other parts of reload know a PLUS is special (gen_reload for example)
2587 and require special code to handle code a reloaded PLUS operand.
2589 Also consider backends where the flags register is clobbered by a
2590 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2591 lea instruction comes to mind). If we try to reload a MINUS, we
2592 may kill the flags register that was holding a useful value.
2594 So, please before trying to handle MINUS, consider reload as a
2595 whole instead of this little section as well as the backend issues. */
2597 /* If this is the sum of an eliminable register and a constant, rework
2599 if (REG_P (XEXP (x
, 0))
2600 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2601 && CONSTANT_P (XEXP (x
, 1)))
2603 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2605 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2607 /* The only time we want to replace a PLUS with a REG (this
2608 occurs when the constant operand of the PLUS is the negative
2609 of the offset) is when we are inside a MEM. We won't want
2610 to do so at other times because that would change the
2611 structure of the insn in a way that reload can't handle.
2612 We special-case the commonest situation in
2613 eliminate_regs_in_insn, so just replace a PLUS with a
2614 PLUS here, unless inside a MEM. */
2616 && CONST_INT_P (XEXP (x
, 1))
2617 && known_eq (INTVAL (XEXP (x
, 1)), -ep
->previous_offset
))
2620 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2621 plus_constant (Pmode
, XEXP (x
, 1),
2622 ep
->previous_offset
));
2625 /* If the register is not eliminable, we are done since the other
2626 operand is a constant. */
2630 /* If this is part of an address, we want to bring any constant to the
2631 outermost PLUS. We will do this by doing register replacement in
2632 our operands and seeing if a constant shows up in one of them.
2634 Note that there is no risk of modifying the structure of the insn,
2635 since we only get called for its operands, thus we are either
2636 modifying the address inside a MEM, or something like an address
2637 operand of a load-address insn. */
2640 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2642 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2645 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2647 /* If one side is a PLUS and the other side is a pseudo that
2648 didn't get a hard register but has a reg_equiv_constant,
2649 we must replace the constant here since it may no longer
2650 be in the position of any operand. */
2651 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2652 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2653 && reg_renumber
[REGNO (new1
)] < 0
2655 && reg_equiv_constant (REGNO (new1
)) != 0)
2656 new1
= reg_equiv_constant (REGNO (new1
));
2657 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2658 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2659 && reg_renumber
[REGNO (new0
)] < 0
2660 && reg_equiv_constant (REGNO (new0
)) != 0)
2661 new0
= reg_equiv_constant (REGNO (new0
));
2663 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2665 /* As above, if we are not inside a MEM we do not want to
2666 turn a PLUS into something else. We might try to do so here
2667 for an addition of 0 if we aren't optimizing. */
2668 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2669 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2677 /* If this is the product of an eliminable register and a
2678 constant, apply the distribute law and move the constant out
2679 so that we have (plus (mult ..) ..). This is needed in order
2680 to keep load-address insns valid. This case is pathological.
2681 We ignore the possibility of overflow here. */
2682 if (REG_P (XEXP (x
, 0))
2683 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2684 && CONST_INT_P (XEXP (x
, 1)))
2685 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2687 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2690 /* Refs inside notes or in DEBUG_INSNs don't count for
2692 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2693 || GET_CODE (insn
) == INSN_LIST
2694 || DEBUG_INSN_P (insn
))))
2695 ep
->ref_outside_mem
= 1;
2698 plus_constant (Pmode
,
2699 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2700 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2707 /* See comments before PLUS about handling MINUS. */
2709 case DIV
: case UDIV
:
2710 case MOD
: case UMOD
:
2711 case AND
: case IOR
: case XOR
:
2712 case ROTATERT
: case ROTATE
:
2713 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2715 case GE
: case GT
: case GEU
: case GTU
:
2716 case LE
: case LT
: case LEU
: case LTU
:
2718 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2720 rtx new1
= XEXP (x
, 1)
2721 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2724 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2725 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2730 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2733 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2735 if (new_rtx
!= XEXP (x
, 0))
2737 /* If this is a REG_DEAD note, it is not valid anymore.
2738 Using the eliminated version could result in creating a
2739 REG_DEAD note for the stack or frame pointer. */
2740 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2742 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2746 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2754 /* Now do eliminations in the rest of the chain. If this was
2755 an EXPR_LIST, this might result in allocating more memory than is
2756 strictly needed, but it simplifies the code. */
2759 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2761 if (new_rtx
!= XEXP (x
, 1))
2763 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2771 /* We do not support elimination of a register that is modified.
2772 elimination_effects has already make sure that this does not
2778 /* We do not support elimination of a register that is modified.
2779 elimination_effects has already make sure that this does not
2780 happen. The only remaining case we need to consider here is
2781 that the increment value may be an eliminable register. */
2782 if (GET_CODE (XEXP (x
, 1)) == PLUS
2783 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2785 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2786 insn
, true, for_costs
);
2788 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2789 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2790 gen_rtx_PLUS (GET_MODE (x
),
2791 XEXP (x
, 0), new_rtx
));
2795 case STRICT_LOW_PART
:
2797 case SIGN_EXTEND
: case ZERO_EXTEND
:
2798 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2799 case FLOAT
: case FIX
:
2800 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2809 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2811 if (new_rtx
!= XEXP (x
, 0))
2812 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2816 /* Similar to above processing, but preserve SUBREG_BYTE.
2817 Convert (subreg (mem)) to (mem) if not paradoxical.
2818 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2819 pseudo didn't get a hard reg, we must replace this with the
2820 eliminated version of the memory location because push_reload
2821 may do the replacement in certain circumstances. */
2822 if (REG_P (SUBREG_REG (x
))
2823 && !paradoxical_subreg_p (x
)
2825 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2827 new_rtx
= SUBREG_REG (x
);
2830 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2832 if (new_rtx
!= SUBREG_REG (x
))
2834 poly_int64 x_size
= GET_MODE_SIZE (GET_MODE (x
));
2835 poly_int64 new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2838 && ((partial_subreg_p (GET_MODE (x
), GET_MODE (new_rtx
))
2839 /* On RISC machines, combine can create rtl of the form
2840 (set (subreg:m1 (reg:m2 R) 0) ...)
2841 where m1 < m2, and expects something interesting to
2842 happen to the entire word. Moreover, it will use the
2843 (reg:m2 R) later, expecting all bits to be preserved.
2844 So if the number of words is the same, preserve the
2845 subreg so that push_reload can see it. */
2846 && !(WORD_REGISTER_OPERATIONS
2847 && known_equal_after_align_down (x_size
- 1,
2850 || known_eq (x_size
, new_size
))
2852 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2853 else if (insn
&& GET_CODE (insn
) == DEBUG_INSN
)
2854 return gen_rtx_raw_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2856 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2862 /* Our only special processing is to pass the mode of the MEM to our
2863 recursive call and copy the flags. While we are here, handle this
2864 case more efficiently. */
2866 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2869 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2870 && !memory_address_p (GET_MODE (x
), new_rtx
))
2871 note_reg_elim_costly (XEXP (x
, 0), insn
);
2873 return replace_equiv_address_nv (x
, new_rtx
);
2876 /* Handle insn_list USE that a call to a pure function may generate. */
2877 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2879 if (new_rtx
!= XEXP (x
, 0))
2880 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2886 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2896 /* Process each of our operands recursively. If any have changed, make a
2898 fmt
= GET_RTX_FORMAT (code
);
2899 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2903 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2905 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2907 x
= shallow_copy_rtx (x
);
2910 XEXP (x
, i
) = new_rtx
;
2912 else if (*fmt
== 'E')
2915 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2917 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2919 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2921 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2925 x
= shallow_copy_rtx (x
);
2928 XVEC (x
, i
) = new_v
;
2931 XVECEXP (x
, i
, j
) = new_rtx
;
2940 eliminate_regs (rtx x
, machine_mode mem_mode
, rtx insn
)
2942 if (reg_eliminate
== NULL
)
2944 gcc_assert (targetm
.no_register_allocation
);
2947 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2950 /* Scan rtx X for modifications of elimination target registers. Update
2951 the table of eliminables to reflect the changed state. MEM_MODE is
2952 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2955 elimination_effects (rtx x
, machine_mode mem_mode
)
2957 enum rtx_code code
= GET_CODE (x
);
2958 struct elim_table
*ep
;
2980 /* First handle the case where we encounter a bare register that
2981 is eliminable. Replace it with a PLUS. */
2982 if (regno
< FIRST_PSEUDO_REGISTER
)
2984 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2986 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2989 ep
->ref_outside_mem
= 1;
2994 else if (reg_renumber
[regno
] < 0
2996 && reg_equiv_constant (regno
)
2997 && ! function_invariant_p (reg_equiv_constant (regno
)))
2998 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3007 /* If we modify the source of an elimination rule, disable it. */
3008 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3009 if (ep
->from_rtx
== XEXP (x
, 0))
3010 ep
->can_eliminate
= 0;
3012 /* If we modify the target of an elimination rule by adding a constant,
3013 update its offset. If we modify the target in any other way, we'll
3014 have to disable the rule as well. */
3015 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3016 if (ep
->to_rtx
== XEXP (x
, 0))
3018 poly_int64 size
= GET_MODE_SIZE (mem_mode
);
3020 /* If more bytes than MEM_MODE are pushed, account for them. */
3021 #ifdef PUSH_ROUNDING
3022 if (ep
->to_rtx
== stack_pointer_rtx
)
3023 size
= PUSH_ROUNDING (size
);
3025 if (code
== PRE_DEC
|| code
== POST_DEC
)
3027 else if (code
== PRE_INC
|| code
== POST_INC
)
3029 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3031 if (GET_CODE (XEXP (x
, 1)) == PLUS
3032 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3033 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3034 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3036 ep
->can_eliminate
= 0;
3040 /* These two aren't unary operators. */
3041 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3044 /* Fall through to generic unary operation case. */
3046 case STRICT_LOW_PART
:
3048 case SIGN_EXTEND
: case ZERO_EXTEND
:
3049 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3050 case FLOAT
: case FIX
:
3051 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3060 elimination_effects (XEXP (x
, 0), mem_mode
);
3064 if (REG_P (SUBREG_REG (x
))
3065 && !paradoxical_subreg_p (x
)
3067 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3070 elimination_effects (SUBREG_REG (x
), mem_mode
);
3074 /* If using a register that is the source of an eliminate we still
3075 think can be performed, note it cannot be performed since we don't
3076 know how this register is used. */
3077 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3078 if (ep
->from_rtx
== XEXP (x
, 0))
3079 ep
->can_eliminate
= 0;
3081 elimination_effects (XEXP (x
, 0), mem_mode
);
3085 /* If clobbering a register that is the replacement register for an
3086 elimination we still think can be performed, note that it cannot
3087 be performed. Otherwise, we need not be concerned about it. */
3088 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3089 if (ep
->to_rtx
== XEXP (x
, 0))
3090 ep
->can_eliminate
= 0;
3092 elimination_effects (XEXP (x
, 0), mem_mode
);
3096 /* CLOBBER_HIGH is only supported for LRA. */
3100 /* Check for setting a register that we know about. */
3101 if (REG_P (SET_DEST (x
)))
3103 /* See if this is setting the replacement register for an
3106 If DEST is the hard frame pointer, we do nothing because we
3107 assume that all assignments to the frame pointer are for
3108 non-local gotos and are being done at a time when they are valid
3109 and do not disturb anything else. Some machines want to
3110 eliminate a fake argument pointer (or even a fake frame pointer)
3111 with either the real frame or the stack pointer. Assignments to
3112 the hard frame pointer must not prevent this elimination. */
3114 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3116 if (ep
->to_rtx
== SET_DEST (x
)
3117 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3119 /* If it is being incremented, adjust the offset. Otherwise,
3120 this elimination can't be done. */
3121 rtx src
= SET_SRC (x
);
3123 if (GET_CODE (src
) == PLUS
3124 && XEXP (src
, 0) == SET_DEST (x
)
3125 && CONST_INT_P (XEXP (src
, 1)))
3126 ep
->offset
-= INTVAL (XEXP (src
, 1));
3128 ep
->can_eliminate
= 0;
3132 elimination_effects (SET_DEST (x
), VOIDmode
);
3133 elimination_effects (SET_SRC (x
), VOIDmode
);
3137 /* Our only special processing is to pass the mode of the MEM to our
3139 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3146 fmt
= GET_RTX_FORMAT (code
);
3147 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3150 elimination_effects (XEXP (x
, i
), mem_mode
);
3151 else if (*fmt
== 'E')
3152 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3153 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3157 /* Descend through rtx X and verify that no references to eliminable registers
3158 remain. If any do remain, mark the involved register as not
3162 check_eliminable_occurrences (rtx x
)
3171 code
= GET_CODE (x
);
3173 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3175 struct elim_table
*ep
;
3177 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3178 if (ep
->from_rtx
== x
)
3179 ep
->can_eliminate
= 0;
3183 fmt
= GET_RTX_FORMAT (code
);
3184 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3187 check_eliminable_occurrences (XEXP (x
, i
));
3188 else if (*fmt
== 'E')
3191 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3192 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3197 /* Scan INSN and eliminate all eliminable registers in it.
3199 If REPLACE is nonzero, do the replacement destructively. Also
3200 delete the insn as dead it if it is setting an eliminable register.
3202 If REPLACE is zero, do all our allocations in reload_obstack.
3204 If no eliminations were done and this insn doesn't require any elimination
3205 processing (these are not identical conditions: it might be updating sp,
3206 but not referencing fp; this needs to be seen during reload_as_needed so
3207 that the offset between fp and sp can be taken into consideration), zero
3208 is returned. Otherwise, 1 is returned. */
3211 eliminate_regs_in_insn (rtx_insn
*insn
, int replace
)
3213 int icode
= recog_memoized (insn
);
3214 rtx old_body
= PATTERN (insn
);
3215 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3216 rtx old_set
= single_set (insn
);
3220 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3221 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3222 struct elim_table
*ep
;
3223 rtx plus_src
, plus_cst_src
;
3225 if (! insn_is_asm
&& icode
< 0)
3227 gcc_assert (DEBUG_INSN_P (insn
)
3228 || GET_CODE (PATTERN (insn
)) == USE
3229 || GET_CODE (PATTERN (insn
)) == CLOBBER
3230 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3231 if (DEBUG_BIND_INSN_P (insn
))
3232 INSN_VAR_LOCATION_LOC (insn
)
3233 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3237 /* We allow one special case which happens to work on all machines we
3238 currently support: a single set with the source or a REG_EQUAL
3239 note being a PLUS of an eliminable register and a constant. */
3240 plus_src
= plus_cst_src
= 0;
3241 if (old_set
&& REG_P (SET_DEST (old_set
)))
3243 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3244 plus_src
= SET_SRC (old_set
);
3245 /* First see if the source is of the form (plus (...) CST). */
3247 && CONST_INT_P (XEXP (plus_src
, 1)))
3248 plus_cst_src
= plus_src
;
3249 else if (REG_P (SET_SRC (old_set
))
3252 /* Otherwise, see if we have a REG_EQUAL note of the form
3253 (plus (...) CST). */
3255 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3257 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3258 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3259 && GET_CODE (XEXP (links
, 0)) == PLUS
3260 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3262 plus_cst_src
= XEXP (links
, 0);
3268 /* Check that the first operand of the PLUS is a hard reg or
3269 the lowpart subreg of one. */
3272 rtx reg
= XEXP (plus_cst_src
, 0);
3273 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3274 reg
= SUBREG_REG (reg
);
3276 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3282 rtx reg
= XEXP (plus_cst_src
, 0);
3283 poly_int64 offset
= INTVAL (XEXP (plus_cst_src
, 1));
3285 if (GET_CODE (reg
) == SUBREG
)
3286 reg
= SUBREG_REG (reg
);
3288 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3289 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3291 rtx to_rtx
= ep
->to_rtx
;
3292 offset
+= ep
->offset
;
3293 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3295 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3296 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3298 /* If we have a nonzero offset, and the source is already
3299 a simple REG, the following transformation would
3300 increase the cost of the insn by replacing a simple REG
3301 with (plus (reg sp) CST). So try only when we already
3302 had a PLUS before. */
3303 if (known_eq (offset
, 0) || plus_src
)
3305 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3308 new_body
= old_body
;
3311 new_body
= copy_insn (old_body
);
3312 if (REG_NOTES (insn
))
3313 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3315 PATTERN (insn
) = new_body
;
3316 old_set
= single_set (insn
);
3318 /* First see if this insn remains valid when we make the
3319 change. If not, try to replace the whole pattern with
3320 a simple set (this may help if the original insn was a
3321 PARALLEL that was only recognized as single_set due to
3322 REG_UNUSED notes). If this isn't valid either, keep
3323 the INSN_CODE the same and let reload fix it up. */
3324 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3326 rtx new_pat
= gen_rtx_SET (SET_DEST (old_set
), new_src
);
3328 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3329 SET_SRC (old_set
) = new_src
;
3336 /* This can't have an effect on elimination offsets, so skip right
3342 /* Determine the effects of this insn on elimination offsets. */
3343 elimination_effects (old_body
, VOIDmode
);
3345 /* Eliminate all eliminable registers occurring in operands that
3346 can be handled by reload. */
3347 extract_insn (insn
);
3348 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3350 orig_operand
[i
] = recog_data
.operand
[i
];
3351 substed_operand
[i
] = recog_data
.operand
[i
];
3353 /* For an asm statement, every operand is eliminable. */
3354 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3356 bool is_set_src
, in_plus
;
3358 /* Check for setting a register that we know about. */
3359 if (recog_data
.operand_type
[i
] != OP_IN
3360 && REG_P (orig_operand
[i
]))
3362 /* If we are assigning to a register that can be eliminated, it
3363 must be as part of a PARALLEL, since the code above handles
3364 single SETs. We must indicate that we can no longer
3365 eliminate this reg. */
3366 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3368 if (ep
->from_rtx
== orig_operand
[i
])
3369 ep
->can_eliminate
= 0;
3372 /* Companion to the above plus substitution, we can allow
3373 invariants as the source of a plain move. */
3376 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3380 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3381 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3385 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3386 replace
? insn
: NULL_RTX
,
3387 is_set_src
|| in_plus
, false);
3388 if (substed_operand
[i
] != orig_operand
[i
])
3390 /* Terminate the search in check_eliminable_occurrences at
3392 *recog_data
.operand_loc
[i
] = 0;
3394 /* If an output operand changed from a REG to a MEM and INSN is an
3395 insn, write a CLOBBER insn. */
3396 if (recog_data
.operand_type
[i
] != OP_IN
3397 && REG_P (orig_operand
[i
])
3398 && MEM_P (substed_operand
[i
])
3400 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3404 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3405 *recog_data
.dup_loc
[i
]
3406 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3408 /* If any eliminable remain, they aren't eliminable anymore. */
3409 check_eliminable_occurrences (old_body
);
3411 /* Substitute the operands; the new values are in the substed_operand
3413 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3414 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3415 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3416 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3418 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3419 re-recognize the insn. We do this in case we had a simple addition
3420 but now can do this as a load-address. This saves an insn in this
3422 If re-recognition fails, the old insn code number will still be used,
3423 and some register operands may have changed into PLUS expressions.
3424 These will be handled by find_reloads by loading them into a register
3429 /* If we aren't replacing things permanently and we changed something,
3430 make another copy to ensure that all the RTL is new. Otherwise
3431 things can go wrong if find_reload swaps commutative operands
3432 and one is inside RTL that has been copied while the other is not. */
3433 new_body
= old_body
;
3436 new_body
= copy_insn (old_body
);
3437 if (REG_NOTES (insn
))
3438 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3440 PATTERN (insn
) = new_body
;
3442 /* If we had a move insn but now we don't, rerecognize it. This will
3443 cause spurious re-recognition if the old move had a PARALLEL since
3444 the new one still will, but we can't call single_set without
3445 having put NEW_BODY into the insn and the re-recognition won't
3446 hurt in this rare case. */
3447 /* ??? Why this huge if statement - why don't we just rerecognize the
3451 && ((REG_P (SET_SRC (old_set
))
3452 && (GET_CODE (new_body
) != SET
3453 || !REG_P (SET_SRC (new_body
))))
3454 /* If this was a load from or store to memory, compare
3455 the MEM in recog_data.operand to the one in the insn.
3456 If they are not equal, then rerecognize the insn. */
3458 && ((MEM_P (SET_SRC (old_set
))
3459 && SET_SRC (old_set
) != recog_data
.operand
[1])
3460 || (MEM_P (SET_DEST (old_set
))
3461 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3462 /* If this was an add insn before, rerecognize. */
3463 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3465 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3467 INSN_CODE (insn
) = new_icode
;
3471 /* Restore the old body. If there were any changes to it, we made a copy
3472 of it while the changes were still in place, so we'll correctly return
3473 a modified insn below. */
3476 /* Restore the old body. */
3477 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3478 /* Restoring a top-level match_parallel would clobber the new_body
3479 we installed in the insn. */
3480 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3481 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3482 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3483 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3486 /* Update all elimination pairs to reflect the status after the current
3487 insn. The changes we make were determined by the earlier call to
3488 elimination_effects.
3490 We also detect cases where register elimination cannot be done,
3491 namely, if a register would be both changed and referenced outside a MEM
3492 in the resulting insn since such an insn is often undefined and, even if
3493 not, we cannot know what meaning will be given to it. Note that it is
3494 valid to have a register used in an address in an insn that changes it
3495 (presumably with a pre- or post-increment or decrement).
3497 If anything changes, return nonzero. */
3499 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3501 if (maybe_ne (ep
->previous_offset
, ep
->offset
) && ep
->ref_outside_mem
)
3502 ep
->can_eliminate
= 0;
3504 ep
->ref_outside_mem
= 0;
3506 if (maybe_ne (ep
->previous_offset
, ep
->offset
))
3511 /* If we changed something, perform elimination in REG_NOTES. This is
3512 needed even when REPLACE is zero because a REG_DEAD note might refer
3513 to a register that we eliminate and could cause a different number
3514 of spill registers to be needed in the final reload pass than in
3516 if (val
&& REG_NOTES (insn
) != 0)
3518 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3524 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3525 register allocator. INSN is the instruction we need to examine, we perform
3526 eliminations in its operands and record cases where eliminating a reg with
3527 an invariant equivalence would add extra cost. */
3529 #pragma GCC diagnostic push
3530 #pragma GCC diagnostic warning "-Wmaybe-uninitialized"
3532 elimination_costs_in_insn (rtx_insn
*insn
)
3534 int icode
= recog_memoized (insn
);
3535 rtx old_body
= PATTERN (insn
);
3536 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3537 rtx old_set
= single_set (insn
);
3539 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3540 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3541 struct elim_table
*ep
;
3542 rtx plus_src
, plus_cst_src
;
3545 if (! insn_is_asm
&& icode
< 0)
3547 gcc_assert (DEBUG_INSN_P (insn
)
3548 || GET_CODE (PATTERN (insn
)) == USE
3549 || GET_CODE (PATTERN (insn
)) == CLOBBER
3550 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3554 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3555 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3557 /* Check for setting an eliminable register. */
3558 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3559 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3563 /* We allow one special case which happens to work on all machines we
3564 currently support: a single set with the source or a REG_EQUAL
3565 note being a PLUS of an eliminable register and a constant. */
3566 plus_src
= plus_cst_src
= 0;
3568 if (old_set
&& REG_P (SET_DEST (old_set
)))
3571 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3572 plus_src
= SET_SRC (old_set
);
3573 /* First see if the source is of the form (plus (...) CST). */
3575 && CONST_INT_P (XEXP (plus_src
, 1)))
3576 plus_cst_src
= plus_src
;
3577 else if (REG_P (SET_SRC (old_set
))
3580 /* Otherwise, see if we have a REG_EQUAL note of the form
3581 (plus (...) CST). */
3583 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3585 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3586 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3587 && GET_CODE (XEXP (links
, 0)) == PLUS
3588 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3590 plus_cst_src
= XEXP (links
, 0);
3597 /* Determine the effects of this insn on elimination offsets. */
3598 elimination_effects (old_body
, VOIDmode
);
3600 /* Eliminate all eliminable registers occurring in operands that
3601 can be handled by reload. */
3602 extract_insn (insn
);
3603 int n_dups
= recog_data
.n_dups
;
3604 for (i
= 0; i
< n_dups
; i
++)
3605 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3607 int n_operands
= recog_data
.n_operands
;
3608 for (i
= 0; i
< n_operands
; i
++)
3610 orig_operand
[i
] = recog_data
.operand
[i
];
3612 /* For an asm statement, every operand is eliminable. */
3613 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3615 bool is_set_src
, in_plus
;
3617 /* Check for setting a register that we know about. */
3618 if (recog_data
.operand_type
[i
] != OP_IN
3619 && REG_P (orig_operand
[i
]))
3621 /* If we are assigning to a register that can be eliminated, it
3622 must be as part of a PARALLEL, since the code above handles
3623 single SETs. We must indicate that we can no longer
3624 eliminate this reg. */
3625 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3627 if (ep
->from_rtx
== orig_operand
[i
])
3628 ep
->can_eliminate
= 0;
3631 /* Companion to the above plus substitution, we can allow
3632 invariants as the source of a plain move. */
3634 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3636 if (is_set_src
&& !sets_reg_p
)
3637 note_reg_elim_costly (SET_SRC (old_set
), insn
);
3639 if (plus_src
&& sets_reg_p
3640 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3641 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3644 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3646 is_set_src
|| in_plus
, true);
3647 /* Terminate the search in check_eliminable_occurrences at
3649 *recog_data
.operand_loc
[i
] = 0;
3653 for (i
= 0; i
< n_dups
; i
++)
3654 *recog_data
.dup_loc
[i
]
3655 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3657 /* If any eliminable remain, they aren't eliminable anymore. */
3658 check_eliminable_occurrences (old_body
);
3660 /* Restore the old body. */
3661 for (i
= 0; i
< n_operands
; i
++)
3662 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3663 for (i
= 0; i
< n_dups
; i
++)
3664 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3666 /* Update all elimination pairs to reflect the status after the current
3667 insn. The changes we make were determined by the earlier call to
3668 elimination_effects. */
3670 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3672 if (maybe_ne (ep
->previous_offset
, ep
->offset
) && ep
->ref_outside_mem
)
3673 ep
->can_eliminate
= 0;
3675 ep
->ref_outside_mem
= 0;
3680 #pragma GCC diagnostic pop
3682 /* Loop through all elimination pairs.
3683 Recalculate the number not at initial offset.
3685 Compute the maximum offset (minimum offset if the stack does not
3686 grow downward) for each elimination pair. */
3689 update_eliminable_offsets (void)
3691 struct elim_table
*ep
;
3693 num_not_at_initial_offset
= 0;
3694 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3696 ep
->previous_offset
= ep
->offset
;
3697 if (ep
->can_eliminate
&& maybe_ne (ep
->offset
, ep
->initial_offset
))
3698 num_not_at_initial_offset
++;
3702 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3703 replacement we currently believe is valid, mark it as not eliminable if X
3704 modifies DEST in any way other than by adding a constant integer to it.
3706 If DEST is the frame pointer, we do nothing because we assume that
3707 all assignments to the hard frame pointer are nonlocal gotos and are being
3708 done at a time when they are valid and do not disturb anything else.
3709 Some machines want to eliminate a fake argument pointer with either the
3710 frame or stack pointer. Assignments to the hard frame pointer must not
3711 prevent this elimination.
3713 Called via note_stores from reload before starting its passes to scan
3714 the insns of the function. */
3717 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3721 /* A SUBREG of a hard register here is just changing its mode. We should
3722 not see a SUBREG of an eliminable hard register, but check just in
3724 if (GET_CODE (dest
) == SUBREG
)
3725 dest
= SUBREG_REG (dest
);
3727 if (dest
== hard_frame_pointer_rtx
)
3730 /* CLOBBER_HIGH is only supported for LRA. */
3731 gcc_assert (GET_CODE (x
) != CLOBBER_HIGH
);
3733 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3734 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3735 && (GET_CODE (x
) != SET
3736 || GET_CODE (SET_SRC (x
)) != PLUS
3737 || XEXP (SET_SRC (x
), 0) != dest
3738 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3740 reg_eliminate
[i
].can_eliminate_previous
3741 = reg_eliminate
[i
].can_eliminate
= 0;
3746 /* Verify that the initial elimination offsets did not change since the
3747 last call to set_initial_elim_offsets. This is used to catch cases
3748 where something illegal happened during reload_as_needed that could
3749 cause incorrect code to be generated if we did not check for it. */
3752 verify_initial_elim_offsets (void)
3755 struct elim_table
*ep
;
3757 if (!num_eliminable
)
3760 targetm
.compute_frame_layout ();
3761 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3763 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3764 if (maybe_ne (t
, ep
->initial_offset
))
3771 /* Reset all offsets on eliminable registers to their initial values. */
3774 set_initial_elim_offsets (void)
3776 struct elim_table
*ep
= reg_eliminate
;
3778 targetm
.compute_frame_layout ();
3779 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3781 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3782 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3785 num_not_at_initial_offset
= 0;
3788 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3791 set_initial_eh_label_offset (rtx label
)
3793 set_label_offsets (label
, NULL
, 1);
3796 /* Initialize the known label offsets.
3797 Set a known offset for each forced label to be at the initial offset
3798 of each elimination. We do this because we assume that all
3799 computed jumps occur from a location where each elimination is
3800 at its initial offset.
3801 For all other labels, show that we don't know the offsets. */
3804 set_initial_label_offsets (void)
3806 memset (offsets_known_at
, 0, num_labels
);
3810 FOR_EACH_VEC_SAFE_ELT (forced_labels
, i
, insn
)
3811 set_label_offsets (insn
, NULL
, 1);
3813 for (rtx_insn_list
*x
= nonlocal_goto_handler_labels
; x
; x
= x
->next ())
3815 set_label_offsets (x
->insn (), NULL
, 1);
3817 for_each_eh_label (set_initial_eh_label_offset
);
3820 /* Set all elimination offsets to the known values for the code label given
3824 set_offsets_for_label (rtx_insn
*insn
)
3827 int label_nr
= CODE_LABEL_NUMBER (insn
);
3828 struct elim_table
*ep
;
3830 num_not_at_initial_offset
= 0;
3831 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3833 ep
->offset
= ep
->previous_offset
3834 = offsets_at
[label_nr
- first_label_num
][i
];
3835 if (ep
->can_eliminate
&& maybe_ne (ep
->offset
, ep
->initial_offset
))
3836 num_not_at_initial_offset
++;
3840 /* See if anything that happened changes which eliminations are valid.
3841 For example, on the SPARC, whether or not the frame pointer can
3842 be eliminated can depend on what registers have been used. We need
3843 not check some conditions again (such as flag_omit_frame_pointer)
3844 since they can't have changed. */
3847 update_eliminables (HARD_REG_SET
*pset
)
3849 int previous_frame_pointer_needed
= frame_pointer_needed
;
3850 struct elim_table
*ep
;
3852 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3853 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3854 && targetm
.frame_pointer_required ())
3855 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3857 ep
->can_eliminate
= 0;
3859 /* Look for the case where we have discovered that we can't replace
3860 register A with register B and that means that we will now be
3861 trying to replace register A with register C. This means we can
3862 no longer replace register C with register B and we need to disable
3863 such an elimination, if it exists. This occurs often with A == ap,
3864 B == sp, and C == fp. */
3866 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3868 struct elim_table
*op
;
3871 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3873 /* Find the current elimination for ep->from, if there is a
3875 for (op
= reg_eliminate
;
3876 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3877 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3883 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3885 for (op
= reg_eliminate
;
3886 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3887 if (op
->from
== new_to
&& op
->to
== ep
->to
)
3888 op
->can_eliminate
= 0;
3892 /* See if any registers that we thought we could eliminate the previous
3893 time are no longer eliminable. If so, something has changed and we
3894 must spill the register. Also, recompute the number of eliminable
3895 registers and see if the frame pointer is needed; it is if there is
3896 no elimination of the frame pointer that we can perform. */
3898 frame_pointer_needed
= 1;
3899 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3901 if (ep
->can_eliminate
3902 && ep
->from
== FRAME_POINTER_REGNUM
3903 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
3904 && (! SUPPORTS_STACK_ALIGNMENT
3905 || ! crtl
->stack_realign_needed
))
3906 frame_pointer_needed
= 0;
3908 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3910 ep
->can_eliminate_previous
= 0;
3911 SET_HARD_REG_BIT (*pset
, ep
->from
);
3916 /* If we didn't need a frame pointer last time, but we do now, spill
3917 the hard frame pointer. */
3918 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
3919 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
3922 /* Call update_eliminables an spill any registers we can't eliminate anymore.
3923 Return true iff a register was spilled. */
3926 update_eliminables_and_spill (void)
3929 bool did_spill
= false;
3930 HARD_REG_SET to_spill
;
3931 CLEAR_HARD_REG_SET (to_spill
);
3932 update_eliminables (&to_spill
);
3933 used_spill_regs
&= ~to_spill
;
3935 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3936 if (TEST_HARD_REG_BIT (to_spill
, i
))
3938 spill_hard_reg (i
, 1);
3941 /* Regardless of the state of spills, if we previously had
3942 a register that we thought we could eliminate, but now
3943 cannot eliminate, we must run another pass.
3945 Consider pseudos which have an entry in reg_equiv_* which
3946 reference an eliminable register. We must make another pass
3947 to update reg_equiv_* so that we do not substitute in the
3948 old value from when we thought the elimination could be
3954 /* Return true if X is used as the target register of an elimination. */
3957 elimination_target_reg_p (rtx x
)
3959 struct elim_table
*ep
;
3961 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3962 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
3968 /* Initialize the table of registers to eliminate.
3969 Pre-condition: global flag frame_pointer_needed has been set before
3970 calling this function. */
3973 init_elim_table (void)
3975 struct elim_table
*ep
;
3976 const struct elim_table_1
*ep1
;
3979 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
3983 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
3984 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
3986 ep
->from
= ep1
->from
;
3988 ep
->can_eliminate
= ep
->can_eliminate_previous
3989 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
3990 && ! (ep
->to
== STACK_POINTER_REGNUM
3991 && frame_pointer_needed
3992 && (! SUPPORTS_STACK_ALIGNMENT
3993 || ! stack_realign_fp
)));
3996 /* Count the number of eliminable registers and build the FROM and TO
3997 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3998 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3999 We depend on this. */
4000 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4002 num_eliminable
+= ep
->can_eliminate
;
4003 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4004 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4008 /* Find all the pseudo registers that didn't get hard regs
4009 but do have known equivalent constants or memory slots.
4010 These include parameters (known equivalent to parameter slots)
4011 and cse'd or loop-moved constant memory addresses.
4013 Record constant equivalents in reg_equiv_constant
4014 so they will be substituted by find_reloads.
4015 Record memory equivalents in reg_mem_equiv so they can
4016 be substituted eventually by altering the REG-rtx's. */
4019 init_eliminable_invariants (rtx_insn
*first
, bool do_subregs
)
4026 reg_max_ref_mode
= XCNEWVEC (machine_mode
, max_regno
);
4028 reg_max_ref_mode
= NULL
;
4030 num_eliminable_invariants
= 0;
4032 first_label_num
= get_first_label_num ();
4033 num_labels
= max_label_num () - first_label_num
;
4035 /* Allocate the tables used to store offset information at labels. */
4036 offsets_known_at
= XNEWVEC (char, num_labels
);
4037 offsets_at
= (poly_int64_pod (*)[NUM_ELIMINABLE_REGS
])
4038 xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (poly_int64
));
4040 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4041 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4042 find largest such for each pseudo. FIRST is the head of the insn
4045 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4047 rtx set
= single_set (insn
);
4049 /* We may introduce USEs that we want to remove at the end, so
4050 we'll mark them with QImode. Make sure there are no
4051 previously-marked insns left by say regmove. */
4052 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4053 && GET_MODE (insn
) != VOIDmode
)
4054 PUT_MODE (insn
, VOIDmode
);
4056 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4057 scan_paradoxical_subregs (PATTERN (insn
));
4059 if (set
!= 0 && REG_P (SET_DEST (set
)))
4061 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4067 i
= REGNO (SET_DEST (set
));
4070 if (i
<= LAST_VIRTUAL_REGISTER
)
4073 /* If flag_pic and we have constant, verify it's legitimate. */
4075 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4077 /* It can happen that a REG_EQUIV note contains a MEM
4078 that is not a legitimate memory operand. As later
4079 stages of reload assume that all addresses found
4080 in the reg_equiv_* arrays were originally legitimate,
4081 we ignore such REG_EQUIV notes. */
4082 if (memory_operand (x
, VOIDmode
))
4084 /* Always unshare the equivalence, so we can
4085 substitute into this insn without touching the
4087 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4089 else if (function_invariant_p (x
))
4093 mode
= GET_MODE (SET_DEST (set
));
4094 if (GET_CODE (x
) == PLUS
)
4096 /* This is PLUS of frame pointer and a constant,
4097 and might be shared. Unshare it. */
4098 reg_equiv_invariant (i
) = copy_rtx (x
);
4099 num_eliminable_invariants
++;
4101 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4103 reg_equiv_invariant (i
) = x
;
4104 num_eliminable_invariants
++;
4106 else if (targetm
.legitimate_constant_p (mode
, x
))
4107 reg_equiv_constant (i
) = x
;
4110 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4111 if (! reg_equiv_memory_loc (i
))
4112 reg_equiv_init (i
) = NULL
;
4117 reg_equiv_init (i
) = NULL
;
4122 reg_equiv_init (i
) = NULL
;
4127 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4128 if (reg_equiv_init (i
))
4130 fprintf (dump_file
, "init_insns for %u: ", i
);
4131 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4132 fprintf (dump_file
, "\n");
4136 /* Indicate that we no longer have known memory locations or constants.
4137 Free all data involved in tracking these. */
4140 free_reg_equiv (void)
4144 free (offsets_known_at
);
4147 offsets_known_at
= 0;
4149 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4150 if (reg_equiv_alt_mem_list (i
))
4151 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4152 vec_free (reg_equivs
);
4155 /* Kick all pseudos out of hard register REGNO.
4157 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4158 because we found we can't eliminate some register. In the case, no pseudos
4159 are allowed to be in the register, even if they are only in a block that
4160 doesn't require spill registers, unlike the case when we are spilling this
4161 hard reg to produce another spill register.
4163 Return nonzero if any pseudos needed to be kicked out. */
4166 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4172 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4173 df_set_regs_ever_live (regno
, true);
4176 /* Spill every pseudo reg that was allocated to this reg
4177 or to something that overlaps this reg. */
4179 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4180 if (reg_renumber
[i
] >= 0
4181 && (unsigned int) reg_renumber
[i
] <= regno
4182 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4183 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4186 /* After spill_hard_reg was called and/or find_reload_regs was run for all
4187 insns that need reloads, this function is used to actually spill pseudo
4188 registers and try to reallocate them. It also sets up the spill_regs
4189 array for use by choose_reload_regs.
4191 GLOBAL nonzero means we should attempt to reallocate any pseudo registers
4192 that we displace from hard registers. */
4195 finish_spills (int global
)
4197 class insn_chain
*chain
;
4198 int something_changed
= 0;
4200 reg_set_iterator rsi
;
4202 /* Build the spill_regs array for the function. */
4203 /* If there are some registers still to eliminate and one of the spill regs
4204 wasn't ever used before, additional stack space may have to be
4205 allocated to store this register. Thus, we may have changed the offset
4206 between the stack and frame pointers, so mark that something has changed.
4208 One might think that we need only set VAL to 1 if this is a call-used
4209 register. However, the set of registers that must be saved by the
4210 prologue is not identical to the call-used set. For example, the
4211 register used by the call insn for the return PC is a call-used register,
4212 but must be saved by the prologue. */
4215 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4216 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4218 spill_reg_order
[i
] = n_spills
;
4219 spill_regs
[n_spills
++] = i
;
4220 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4221 something_changed
= 1;
4222 df_set_regs_ever_live (i
, true);
4225 spill_reg_order
[i
] = -1;
4227 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4228 if (reg_renumber
[i
] >= 0)
4230 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4231 /* Mark it as no longer having a hard register home. */
4232 reg_renumber
[i
] = -1;
4233 if (ira_conflicts_p
)
4234 /* Inform IRA about the change. */
4235 ira_mark_allocation_change (i
);
4236 /* We will need to scan everything again. */
4237 something_changed
= 1;
4240 /* Retry global register allocation if possible. */
4241 if (global
&& ira_conflicts_p
)
4245 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4246 /* For every insn that needs reloads, set the registers used as spill
4247 regs in pseudo_forbidden_regs for every pseudo live across the
4249 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4251 EXECUTE_IF_SET_IN_REG_SET
4252 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4254 pseudo_forbidden_regs
[i
] |= chain
->used_spill_regs
;
4256 EXECUTE_IF_SET_IN_REG_SET
4257 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4259 pseudo_forbidden_regs
[i
] |= chain
->used_spill_regs
;
4263 /* Retry allocating the pseudos spilled in IRA and the
4264 reload. For each reg, merge the various reg sets that
4265 indicate which hard regs can't be used, and call
4266 ira_reassign_pseudos. */
4267 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4268 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4270 if (reg_renumber
[i
] < 0)
4271 temp_pseudo_reg_arr
[n
++] = i
;
4273 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4275 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4276 bad_spill_regs_global
,
4277 pseudo_forbidden_regs
, pseudo_previous_regs
,
4279 something_changed
= 1;
4281 /* Fix up the register information in the insn chain.
4282 This involves deleting those of the spilled pseudos which did not get
4283 a new hard register home from the live_{before,after} sets. */
4284 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4286 HARD_REG_SET used_by_pseudos
;
4287 HARD_REG_SET used_by_pseudos2
;
4289 if (! ira_conflicts_p
)
4291 /* Don't do it for IRA because IRA and the reload still can
4292 assign hard registers to the spilled pseudos on next
4293 reload iterations. */
4294 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4295 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4297 /* Mark any unallocated hard regs as available for spills. That
4298 makes inheritance work somewhat better. */
4299 if (chain
->need_reload
)
4301 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4302 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4303 used_by_pseudos
|= used_by_pseudos2
;
4305 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4306 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4307 /* Value of chain->used_spill_regs from previous iteration
4308 may be not included in the value calculated here because
4309 of possible removing caller-saves insns (see function
4310 delete_caller_save_insns. */
4311 chain
->used_spill_regs
= ~used_by_pseudos
& used_spill_regs
;
4315 CLEAR_REG_SET (&changed_allocation_pseudos
);
4316 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4317 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4319 int regno
= reg_renumber
[i
];
4320 if (reg_old_renumber
[i
] == regno
)
4323 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4325 alter_reg (i
, reg_old_renumber
[i
], false);
4326 reg_old_renumber
[i
] = regno
;
4330 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4332 fprintf (dump_file
, " Register %d now in %d.\n\n",
4333 i
, reg_renumber
[i
]);
4337 return something_changed
;
4340 /* Find all paradoxical subregs within X and update reg_max_ref_mode. */
4343 scan_paradoxical_subregs (rtx x
)
4347 enum rtx_code code
= GET_CODE (x
);
4364 if (REG_P (SUBREG_REG (x
)))
4366 unsigned int regno
= REGNO (SUBREG_REG (x
));
4367 if (partial_subreg_p (reg_max_ref_mode
[regno
], GET_MODE (x
)))
4369 reg_max_ref_mode
[regno
] = GET_MODE (x
);
4370 mark_home_live_1 (regno
, GET_MODE (x
));
4379 fmt
= GET_RTX_FORMAT (code
);
4380 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4383 scan_paradoxical_subregs (XEXP (x
, i
));
4384 else if (fmt
[i
] == 'E')
4387 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4388 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4393 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4394 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4395 and apply the corresponding narrowing subreg to *OTHER_PTR.
4396 Return true if the operands were changed, false otherwise. */
4399 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4401 rtx op
, inner
, other
, tem
;
4404 if (!paradoxical_subreg_p (op
))
4406 inner
= SUBREG_REG (op
);
4409 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4413 /* If the lowpart operation turned a hard register into a subreg,
4414 rather than simplifying it to another hard register, then the
4415 mode change cannot be properly represented. For example, OTHER
4416 might be valid in its current mode, but not in the new one. */
4417 if (GET_CODE (tem
) == SUBREG
4419 && HARD_REGISTER_P (other
))
4427 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4428 examine all of the reload insns between PREV and NEXT exclusive, and
4429 annotate all that may trap. */
4432 fixup_eh_region_note (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4434 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4437 if (!insn_could_throw_p (insn
))
4438 remove_note (insn
, note
);
4439 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4442 /* Reload pseudo-registers into hard regs around each insn as needed.
4443 Additional register load insns are output before the insn that needs it
4444 and perhaps store insns after insns that modify the reloaded pseudo reg.
4446 reg_last_reload_reg and reg_reloaded_contents keep track of
4447 which registers are already available in reload registers.
4448 We update these for the reloads that we perform,
4449 as the insns are scanned. */
4452 reload_as_needed (int live_known
)
4454 class insn_chain
*chain
;
4460 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4461 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4462 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4463 INIT_REG_SET (®_has_output_reload
);
4464 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4465 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4467 set_initial_elim_offsets ();
4469 /* Generate a marker insn that we will move around. */
4470 marker
= emit_note (NOTE_INSN_DELETED
);
4471 unlink_insn_chain (marker
, marker
);
4473 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4476 rtx_insn
*insn
= chain
->insn
;
4477 rtx_insn
*old_next
= NEXT_INSN (insn
);
4479 rtx_insn
*old_prev
= PREV_INSN (insn
);
4482 if (will_delete_init_insn_p (insn
))
4485 /* If we pass a label, copy the offsets from the label information
4486 into the current offsets of each elimination. */
4488 set_offsets_for_label (insn
);
4490 else if (INSN_P (insn
))
4492 regset_head regs_to_forget
;
4493 INIT_REG_SET (®s_to_forget
);
4494 note_stores (insn
, forget_old_reloads_1
, ®s_to_forget
);
4496 /* If this is a USE and CLOBBER of a MEM, ensure that any
4497 references to eliminable registers have been removed. */
4499 if ((GET_CODE (PATTERN (insn
)) == USE
4500 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4501 && MEM_P (XEXP (PATTERN (insn
), 0)))
4502 XEXP (XEXP (PATTERN (insn
), 0), 0)
4503 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4504 GET_MODE (XEXP (PATTERN (insn
), 0)),
4507 /* If we need to do register elimination processing, do so.
4508 This might delete the insn, in which case we are done. */
4509 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4511 eliminate_regs_in_insn (insn
, 1);
4514 update_eliminable_offsets ();
4515 CLEAR_REG_SET (®s_to_forget
);
4520 /* If need_elim is nonzero but need_reload is zero, one might think
4521 that we could simply set n_reloads to 0. However, find_reloads
4522 could have done some manipulation of the insn (such as swapping
4523 commutative operands), and these manipulations are lost during
4524 the first pass for every insn that needs register elimination.
4525 So the actions of find_reloads must be redone here. */
4527 if (! chain
->need_elim
&& ! chain
->need_reload
4528 && ! chain
->need_operand_change
)
4530 /* First find the pseudo regs that must be reloaded for this insn.
4531 This info is returned in the tables reload_... (see reload.h).
4532 Also modify the body of INSN by substituting RELOAD
4533 rtx's for those pseudo regs. */
4536 CLEAR_REG_SET (®_has_output_reload
);
4537 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4539 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4545 rtx_insn
*next
= NEXT_INSN (insn
);
4547 /* ??? PREV can get deleted by reload inheritance.
4548 Work around this by emitting a marker note. */
4549 prev
= PREV_INSN (insn
);
4550 reorder_insns_nobb (marker
, marker
, prev
);
4552 /* Now compute which reload regs to reload them into. Perhaps
4553 reusing reload regs from previous insns, or else output
4554 load insns to reload them. Maybe output store insns too.
4555 Record the choices of reload reg in reload_reg_rtx. */
4556 choose_reload_regs (chain
);
4558 /* Generate the insns to reload operands into or out of
4559 their reload regs. */
4560 emit_reload_insns (chain
);
4562 /* Substitute the chosen reload regs from reload_reg_rtx
4563 into the insn's body (or perhaps into the bodies of other
4564 load and store insn that we just made for reloading
4565 and that we moved the structure into). */
4566 subst_reloads (insn
);
4568 prev
= PREV_INSN (marker
);
4569 unlink_insn_chain (marker
, marker
);
4571 /* Adjust the exception region notes for loads and stores. */
4572 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4573 fixup_eh_region_note (insn
, prev
, next
);
4575 /* Adjust the location of REG_ARGS_SIZE. */
4576 rtx p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4579 remove_note (insn
, p
);
4580 fixup_args_size_notes (prev
, PREV_INSN (next
),
4584 /* If this was an ASM, make sure that all the reload insns
4585 we have generated are valid. If not, give an error
4587 if (asm_noperands (PATTERN (insn
)) >= 0)
4588 for (rtx_insn
*p
= NEXT_INSN (prev
);
4591 if (p
!= insn
&& INSN_P (p
)
4592 && GET_CODE (PATTERN (p
)) != USE
4593 && (recog_memoized (p
) < 0
4594 || (extract_insn (p
),
4595 !(constrain_operands (1,
4596 get_enabled_alternatives (p
))))))
4598 error_for_asm (insn
,
4599 "%<asm%> operand requires "
4600 "impossible reload");
4605 if (num_eliminable
&& chain
->need_elim
)
4606 update_eliminable_offsets ();
4608 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4609 is no longer validly lying around to save a future reload.
4610 Note that this does not detect pseudos that were reloaded
4611 for this insn in order to be stored in
4612 (obeying register constraints). That is correct; such reload
4613 registers ARE still valid. */
4614 forget_marked_reloads (®s_to_forget
);
4615 CLEAR_REG_SET (®s_to_forget
);
4617 /* There may have been CLOBBER insns placed after INSN. So scan
4618 between INSN and NEXT and use them to forget old reloads. */
4619 for (rtx_insn
*x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4620 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4621 note_stores (x
, forget_old_reloads_1
, NULL
);
4624 /* Likewise for regs altered by auto-increment in this insn.
4625 REG_INC notes have been changed by reloading:
4626 find_reloads_address_1 records substitutions for them,
4627 which have been performed by subst_reloads above. */
4628 for (i
= n_reloads
- 1; i
>= 0; i
--)
4630 rtx in_reg
= rld
[i
].in_reg
;
4633 enum rtx_code code
= GET_CODE (in_reg
);
4634 /* PRE_INC / PRE_DEC will have the reload register ending up
4635 with the same value as the stack slot, but that doesn't
4636 hold true for POST_INC / POST_DEC. Either we have to
4637 convert the memory access to a true POST_INC / POST_DEC,
4638 or we can't use the reload register for inheritance. */
4639 if ((code
== POST_INC
|| code
== POST_DEC
)
4640 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4641 REGNO (rld
[i
].reg_rtx
))
4642 /* Make sure it is the inc/dec pseudo, and not
4643 some other (e.g. output operand) pseudo. */
4644 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4645 == REGNO (XEXP (in_reg
, 0))))
4648 rtx reload_reg
= rld
[i
].reg_rtx
;
4649 machine_mode mode
= GET_MODE (reload_reg
);
4653 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4655 /* We really want to ignore REG_INC notes here, so
4656 use PATTERN (p) as argument to reg_set_p . */
4657 if (reg_set_p (reload_reg
, PATTERN (p
)))
4659 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4665 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4667 validate_replace_rtx_group (reload_reg
,
4669 n
= verify_changes (0);
4671 /* We must also verify that the constraints
4672 are met after the replacement. Make sure
4673 extract_insn is only called for an insn
4674 where the replacements were found to be
4679 n
= constrain_operands (1,
4680 get_enabled_alternatives (p
));
4683 /* If the constraints were not met, then
4684 undo the replacement, else confirm it. */
4688 confirm_change_group ();
4694 add_reg_note (p
, REG_INC
, reload_reg
);
4695 /* Mark this as having an output reload so that the
4696 REG_INC processing code below won't invalidate
4697 the reload for inheritance. */
4698 SET_HARD_REG_BIT (reg_is_output_reload
,
4699 REGNO (reload_reg
));
4700 SET_REGNO_REG_SET (®_has_output_reload
,
4701 REGNO (XEXP (in_reg
, 0)));
4704 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4707 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4708 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4709 REGNO (rld
[i
].reg_rtx
))
4710 /* Make sure it is the inc/dec pseudo, and not
4711 some other (e.g. output operand) pseudo. */
4712 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4713 == REGNO (XEXP (in_reg
, 0))))
4715 SET_HARD_REG_BIT (reg_is_output_reload
,
4716 REGNO (rld
[i
].reg_rtx
));
4717 SET_REGNO_REG_SET (®_has_output_reload
,
4718 REGNO (XEXP (in_reg
, 0)));
4720 else if (code
== PRE_INC
|| code
== PRE_DEC
4721 || code
== POST_INC
|| code
== POST_DEC
)
4723 int in_regno
= REGNO (XEXP (in_reg
, 0));
4725 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4728 bool forget_p
= true;
4730 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4731 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4734 for (rtx_insn
*x
= (old_prev
?
4735 NEXT_INSN (old_prev
) : insn
);
4738 if (x
== reg_reloaded_insn
[in_hard_regno
])
4744 /* If for some reasons, we didn't set up
4745 reg_last_reload_reg in this insn,
4746 invalidate inheritance from previous
4747 insns for the incremented/decremented
4748 register. Such registers will be not in
4749 reg_has_output_reload. Invalidate it
4750 also if the corresponding element in
4751 reg_reloaded_insn is also
4754 forget_old_reloads_1 (XEXP (in_reg
, 0),
4760 /* If a pseudo that got a hard register is auto-incremented,
4761 we must purge records of copying it into pseudos without
4763 for (rtx x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4764 if (REG_NOTE_KIND (x
) == REG_INC
)
4766 /* See if this pseudo reg was reloaded in this insn.
4767 If so, its last-reload info is still valid
4768 because it is based on this insn's reload. */
4769 for (i
= 0; i
< n_reloads
; i
++)
4770 if (rld
[i
].out
== XEXP (x
, 0))
4774 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4778 /* A reload reg's contents are unknown after a label. */
4780 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4782 /* Don't assume a reload reg is still good after a call insn
4783 if it is a call-used reg, or if it contains a value that will
4784 be partially clobbered by the call. */
4785 else if (CALL_P (insn
))
4787 reg_reloaded_valid
&= ~(call_used_or_fixed_regs
4788 | reg_reloaded_call_part_clobbered
);
4790 /* If this is a call to a setjmp-type function, we must not
4791 reuse any reload reg contents across the call; that will
4792 just be clobbered by other uses of the register in later
4793 code, before the longjmp. */
4794 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4795 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4800 free (reg_last_reload_reg
);
4801 CLEAR_REG_SET (®_has_output_reload
);
4804 /* Discard all record of any value reloaded from X,
4805 or reloaded in X from someplace else;
4806 unless X is an output reload reg of the current insn.
4808 X may be a hard reg (the reload reg)
4809 or it may be a pseudo reg that was reloaded from.
4811 When DATA is non-NULL just mark the registers in regset
4812 to be forgotten later. */
4815 forget_old_reloads_1 (rtx x
, const_rtx setter
,
4820 regset regs
= (regset
) data
;
4822 /* note_stores does give us subregs of hard regs,
4823 subreg_regno_offset requires a hard reg. */
4824 while (GET_CODE (x
) == SUBREG
)
4826 /* We ignore the subreg offset when calculating the regno,
4827 because we are using the entire underlying hard register
4835 /* CLOBBER_HIGH is only supported for LRA. */
4836 gcc_assert (setter
== NULL_RTX
|| GET_CODE (setter
) != CLOBBER_HIGH
);
4840 if (regno
>= FIRST_PSEUDO_REGISTER
)
4847 /* Storing into a spilled-reg invalidates its contents.
4848 This can happen if a block-local pseudo is allocated to that reg
4849 and it wasn't spilled because this block's total need is 0.
4850 Then some insn might have an optional reload and use this reg. */
4852 for (i
= 0; i
< nr
; i
++)
4853 /* But don't do this if the reg actually serves as an output
4854 reload reg in the current instruction. */
4856 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4858 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4859 spill_reg_store
[regno
+ i
] = 0;
4865 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4868 /* Since value of X has changed,
4869 forget any value previously copied from it. */
4872 /* But don't forget a copy if this is the output reload
4873 that establishes the copy's validity. */
4875 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4876 reg_last_reload_reg
[regno
+ nr
] = 0;
4880 /* Forget the reloads marked in regset by previous function. */
4882 forget_marked_reloads (regset regs
)
4885 reg_set_iterator rsi
;
4886 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
4888 if (reg
< FIRST_PSEUDO_REGISTER
4889 /* But don't do this if the reg actually serves as an output
4890 reload reg in the current instruction. */
4892 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
4894 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
4895 spill_reg_store
[reg
] = 0;
4898 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
4899 reg_last_reload_reg
[reg
] = 0;
4903 /* The following HARD_REG_SETs indicate when each hard register is
4904 used for a reload of various parts of the current insn. */
4906 /* If reg is unavailable for all reloads. */
4907 static HARD_REG_SET reload_reg_unavailable
;
4908 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4909 static HARD_REG_SET reload_reg_used
;
4910 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4911 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
4912 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4913 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
4914 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4915 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
4916 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4917 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
4918 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4919 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
4920 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4921 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
4922 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4923 static HARD_REG_SET reload_reg_used_in_op_addr
;
4924 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4925 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
4926 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4927 static HARD_REG_SET reload_reg_used_in_insn
;
4928 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4929 static HARD_REG_SET reload_reg_used_in_other_addr
;
4931 /* If reg is in use as a reload reg for any sort of reload. */
4932 static HARD_REG_SET reload_reg_used_at_all
;
4934 /* If reg is use as an inherited reload. We just mark the first register
4936 static HARD_REG_SET reload_reg_used_for_inherit
;
4938 /* Records which hard regs are used in any way, either as explicit use or
4939 by being allocated to a pseudo during any point of the current insn. */
4940 static HARD_REG_SET reg_used_in_insn
;
4942 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4943 TYPE. MODE is used to indicate how many consecutive regs are
4947 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
4953 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
4956 case RELOAD_FOR_INPUT_ADDRESS
:
4957 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
4960 case RELOAD_FOR_INPADDR_ADDRESS
:
4961 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
4964 case RELOAD_FOR_OUTPUT_ADDRESS
:
4965 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
4968 case RELOAD_FOR_OUTADDR_ADDRESS
:
4969 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
4972 case RELOAD_FOR_OPERAND_ADDRESS
:
4973 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
4976 case RELOAD_FOR_OPADDR_ADDR
:
4977 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
4980 case RELOAD_FOR_OTHER_ADDRESS
:
4981 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
4984 case RELOAD_FOR_INPUT
:
4985 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
4988 case RELOAD_FOR_OUTPUT
:
4989 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
4992 case RELOAD_FOR_INSN
:
4993 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
4997 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5000 /* Similarly, but show REGNO is no longer in use for a reload. */
5003 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5004 enum reload_type type
, machine_mode mode
)
5006 unsigned int nregs
= hard_regno_nregs (regno
, mode
);
5007 unsigned int start_regno
, end_regno
, r
;
5009 /* A complication is that for some reload types, inheritance might
5010 allow multiple reloads of the same types to share a reload register.
5011 We set check_opnum if we have to check only reloads with the same
5012 operand number, and check_any if we have to check all reloads. */
5013 int check_opnum
= 0;
5015 HARD_REG_SET
*used_in_set
;
5020 used_in_set
= &reload_reg_used
;
5023 case RELOAD_FOR_INPUT_ADDRESS
:
5024 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5027 case RELOAD_FOR_INPADDR_ADDRESS
:
5029 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5032 case RELOAD_FOR_OUTPUT_ADDRESS
:
5033 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5036 case RELOAD_FOR_OUTADDR_ADDRESS
:
5038 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5041 case RELOAD_FOR_OPERAND_ADDRESS
:
5042 used_in_set
= &reload_reg_used_in_op_addr
;
5045 case RELOAD_FOR_OPADDR_ADDR
:
5047 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5050 case RELOAD_FOR_OTHER_ADDRESS
:
5051 used_in_set
= &reload_reg_used_in_other_addr
;
5055 case RELOAD_FOR_INPUT
:
5056 used_in_set
= &reload_reg_used_in_input
[opnum
];
5059 case RELOAD_FOR_OUTPUT
:
5060 used_in_set
= &reload_reg_used_in_output
[opnum
];
5063 case RELOAD_FOR_INSN
:
5064 used_in_set
= &reload_reg_used_in_insn
;
5069 /* We resolve conflicts with remaining reloads of the same type by
5070 excluding the intervals of reload registers by them from the
5071 interval of freed reload registers. Since we only keep track of
5072 one set of interval bounds, we might have to exclude somewhat
5073 more than what would be necessary if we used a HARD_REG_SET here.
5074 But this should only happen very infrequently, so there should
5075 be no reason to worry about it. */
5077 start_regno
= regno
;
5078 end_regno
= regno
+ nregs
;
5079 if (check_opnum
|| check_any
)
5081 for (i
= n_reloads
- 1; i
>= 0; i
--)
5083 if (rld
[i
].when_needed
== type
5084 && (check_any
|| rld
[i
].opnum
== opnum
)
5087 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5088 unsigned int conflict_end
5089 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5091 /* If there is an overlap with the first to-be-freed register,
5092 adjust the interval start. */
5093 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5094 start_regno
= conflict_end
;
5095 /* Otherwise, if there is a conflict with one of the other
5096 to-be-freed registers, adjust the interval end. */
5097 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5098 end_regno
= conflict_start
;
5103 for (r
= start_regno
; r
< end_regno
; r
++)
5104 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5107 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5108 specified by OPNUM and TYPE. */
5111 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5115 /* In use for a RELOAD_OTHER means it's not available for anything. */
5116 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5117 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5123 /* In use for anything means we can't use it for RELOAD_OTHER. */
5124 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5125 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5126 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5127 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5130 for (i
= 0; i
< reload_n_operands
; i
++)
5131 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5132 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5133 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5134 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5135 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5136 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5141 case RELOAD_FOR_INPUT
:
5142 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5143 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5146 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5149 /* If it is used for some other input, can't use it. */
5150 for (i
= 0; i
< reload_n_operands
; i
++)
5151 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5154 /* If it is used in a later operand's address, can't use it. */
5155 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5156 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5157 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5162 case RELOAD_FOR_INPUT_ADDRESS
:
5163 /* Can't use a register if it is used for an input address for this
5164 operand or used as an input in an earlier one. */
5165 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5166 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5169 for (i
= 0; i
< opnum
; i
++)
5170 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5175 case RELOAD_FOR_INPADDR_ADDRESS
:
5176 /* Can't use a register if it is used for an input address
5177 for this operand or used as an input in an earlier
5179 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5182 for (i
= 0; i
< opnum
; i
++)
5183 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5188 case RELOAD_FOR_OUTPUT_ADDRESS
:
5189 /* Can't use a register if it is used for an output address for this
5190 operand or used as an output in this or a later operand. Note
5191 that multiple output operands are emitted in reverse order, so
5192 the conflicting ones are those with lower indices. */
5193 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5196 for (i
= 0; i
<= opnum
; i
++)
5197 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5202 case RELOAD_FOR_OUTADDR_ADDRESS
:
5203 /* Can't use a register if it is used for an output address
5204 for this operand or used as an output in this or a
5205 later operand. Note that multiple output operands are
5206 emitted in reverse order, so the conflicting ones are
5207 those with lower indices. */
5208 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5211 for (i
= 0; i
<= opnum
; i
++)
5212 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5217 case RELOAD_FOR_OPERAND_ADDRESS
:
5218 for (i
= 0; i
< reload_n_operands
; i
++)
5219 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5222 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5223 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5225 case RELOAD_FOR_OPADDR_ADDR
:
5226 for (i
= 0; i
< reload_n_operands
; i
++)
5227 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5230 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5232 case RELOAD_FOR_OUTPUT
:
5233 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5234 outputs, or an operand address for this or an earlier output.
5235 Note that multiple output operands are emitted in reverse order,
5236 so the conflicting ones are those with higher indices. */
5237 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5240 for (i
= 0; i
< reload_n_operands
; i
++)
5241 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5244 for (i
= opnum
; i
< reload_n_operands
; i
++)
5245 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5246 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5251 case RELOAD_FOR_INSN
:
5252 for (i
= 0; i
< reload_n_operands
; i
++)
5253 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5254 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5257 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5258 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5260 case RELOAD_FOR_OTHER_ADDRESS
:
5261 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5268 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5269 the number RELOADNUM, is still available in REGNO at the end of the insn.
5271 We can assume that the reload reg was already tested for availability
5272 at the time it is needed, and we should not check this again,
5273 in case the reg has already been marked in use. */
5276 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5278 int opnum
= rld
[reloadnum
].opnum
;
5279 enum reload_type type
= rld
[reloadnum
].when_needed
;
5282 /* See if there is a reload with the same type for this operand, using
5283 the same register. This case is not handled by the code below. */
5284 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5288 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5290 reg
= rld
[i
].reg_rtx
;
5291 if (reg
== NULL_RTX
)
5293 if (regno
>= REGNO (reg
) && regno
< END_REGNO (reg
))
5300 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5301 its value must reach the end. */
5304 /* If this use is for part of the insn,
5305 its value reaches if no subsequent part uses the same register.
5306 Just like the above function, don't try to do this with lots
5309 case RELOAD_FOR_OTHER_ADDRESS
:
5310 /* Here we check for everything else, since these don't conflict
5311 with anything else and everything comes later. */
5313 for (i
= 0; i
< reload_n_operands
; i
++)
5314 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5315 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5316 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5317 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5318 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5319 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5322 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5323 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5324 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5325 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5327 case RELOAD_FOR_INPUT_ADDRESS
:
5328 case RELOAD_FOR_INPADDR_ADDRESS
:
5329 /* Similar, except that we check only for this and subsequent inputs
5330 and the address of only subsequent inputs and we do not need
5331 to check for RELOAD_OTHER objects since they are known not to
5334 for (i
= opnum
; i
< reload_n_operands
; i
++)
5335 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5338 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5339 could be killed if the register is also used by reload with type
5340 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5341 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5342 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5345 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5346 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5347 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5350 for (i
= 0; i
< reload_n_operands
; i
++)
5351 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5352 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5353 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5356 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5359 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5360 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5361 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5363 case RELOAD_FOR_INPUT
:
5364 /* Similar to input address, except we start at the next operand for
5365 both input and input address and we do not check for
5366 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5369 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5370 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5371 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5372 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5375 /* ... fall through ... */
5377 case RELOAD_FOR_OPERAND_ADDRESS
:
5378 /* Check outputs and their addresses. */
5380 for (i
= 0; i
< reload_n_operands
; i
++)
5381 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5382 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5383 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5386 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5388 case RELOAD_FOR_OPADDR_ADDR
:
5389 for (i
= 0; i
< reload_n_operands
; i
++)
5390 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5391 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5392 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5395 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5396 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5397 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5399 case RELOAD_FOR_INSN
:
5400 /* These conflict with other outputs with RELOAD_OTHER. So
5401 we need only check for output addresses. */
5403 opnum
= reload_n_operands
;
5407 case RELOAD_FOR_OUTPUT
:
5408 case RELOAD_FOR_OUTPUT_ADDRESS
:
5409 case RELOAD_FOR_OUTADDR_ADDRESS
:
5410 /* We already know these can't conflict with a later output. So the
5411 only thing to check are later output addresses.
5412 Note that multiple output operands are emitted in reverse order,
5413 so the conflicting ones are those with lower indices. */
5414 for (i
= 0; i
< opnum
; i
++)
5415 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5416 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5419 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5420 could be killed if the register is also used by reload with type
5421 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5422 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5423 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5433 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5434 every register in REG. */
5437 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5441 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5442 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5448 /* Returns whether R1 and R2 are uniquely chained: the value of one
5449 is used by the other, and that value is not used by any other
5450 reload for this insn. This is used to partially undo the decision
5451 made in find_reloads when in the case of multiple
5452 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5453 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5454 reloads. This code tries to avoid the conflict created by that
5455 change. It might be cleaner to explicitly keep track of which
5456 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5457 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5458 this after the fact. */
5460 reloads_unique_chain_p (int r1
, int r2
)
5464 /* We only check input reloads. */
5465 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5468 /* Avoid anything with output reloads. */
5469 if (rld
[r1
].out
|| rld
[r2
].out
)
5472 /* "chained" means one reload is a component of the other reload,
5473 not the same as the other reload. */
5474 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5475 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5476 || rld
[r1
].optional
|| rld
[r2
].optional
5477 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5478 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5481 /* The following loop assumes that r1 is the reload that feeds r2. */
5485 for (i
= 0; i
< n_reloads
; i
++)
5486 /* Look for input reloads that aren't our two */
5487 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5489 /* If our reload is mentioned at all, it isn't a simple chain. */
5490 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5496 /* The recursive function change all occurrences of WHAT in *WHERE
5499 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5508 if (*where
== what
|| rtx_equal_p (*where
, what
))
5510 /* Record the location of the changed rtx. */
5511 substitute_stack
.safe_push (where
);
5516 code
= GET_CODE (*where
);
5517 fmt
= GET_RTX_FORMAT (code
);
5518 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5524 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5525 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5527 else if (fmt
[i
] == 'e')
5528 substitute (&XEXP (*where
, i
), what
, repl
);
5532 /* The function returns TRUE if chain of reload R1 and R2 (in any
5533 order) can be evaluated without usage of intermediate register for
5534 the reload containing another reload. It is important to see
5535 gen_reload to understand what the function is trying to do. As an
5536 example, let us have reload chain
5539 r1: <something> + const
5541 and reload R2 got reload reg HR. The function returns true if
5542 there is a correct insn HR = HR + <something>. Otherwise,
5543 gen_reload will use intermediate register (and this is the reload
5544 reg for R1) to reload <something>.
5546 We need this function to find a conflict for chain reloads. In our
5547 example, if HR = HR + <something> is incorrect insn, then we cannot
5548 use HR as a reload register for R2. If we do use it then we get a
5557 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5559 /* Assume other cases in gen_reload are not possible for
5560 chain reloads or do need an intermediate hard registers. */
5565 rtx_insn
*last
= get_last_insn ();
5567 /* Make r2 a component of r1. */
5568 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5571 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5572 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5573 gcc_assert (regno
>= 0);
5574 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5576 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5578 /* If IN is a paradoxical SUBREG, remove it and try to put the
5579 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5580 strip_paradoxical_subreg (&in
, &out
);
5582 if (GET_CODE (in
) == PLUS
5583 && (REG_P (XEXP (in
, 0))
5584 || GET_CODE (XEXP (in
, 0)) == SUBREG
5585 || MEM_P (XEXP (in
, 0)))
5586 && (REG_P (XEXP (in
, 1))
5587 || GET_CODE (XEXP (in
, 1)) == SUBREG
5588 || CONSTANT_P (XEXP (in
, 1))
5589 || MEM_P (XEXP (in
, 1))))
5591 insn
= emit_insn (gen_rtx_SET (out
, in
));
5592 code
= recog_memoized (insn
);
5597 extract_insn (insn
);
5598 /* We want constrain operands to treat this insn strictly in
5599 its validity determination, i.e., the way it would after
5600 reload has completed. */
5601 result
= constrain_operands (1, get_enabled_alternatives (insn
));
5604 delete_insns_since (last
);
5607 /* Restore the original value at each changed address within R1. */
5608 while (!substitute_stack
.is_empty ())
5610 rtx
*where
= substitute_stack
.pop ();
5611 *where
= rld
[r2
].in
;
5617 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5620 This function uses the same algorithm as reload_reg_free_p above. */
5623 reloads_conflict (int r1
, int r2
)
5625 enum reload_type r1_type
= rld
[r1
].when_needed
;
5626 enum reload_type r2_type
= rld
[r2
].when_needed
;
5627 int r1_opnum
= rld
[r1
].opnum
;
5628 int r2_opnum
= rld
[r2
].opnum
;
5630 /* RELOAD_OTHER conflicts with everything. */
5631 if (r2_type
== RELOAD_OTHER
)
5634 /* Otherwise, check conflicts differently for each type. */
5638 case RELOAD_FOR_INPUT
:
5639 return (r2_type
== RELOAD_FOR_INSN
5640 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5641 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5642 || r2_type
== RELOAD_FOR_INPUT
5643 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5644 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5645 && r2_opnum
> r1_opnum
));
5647 case RELOAD_FOR_INPUT_ADDRESS
:
5648 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5649 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5651 case RELOAD_FOR_INPADDR_ADDRESS
:
5652 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5653 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5655 case RELOAD_FOR_OUTPUT_ADDRESS
:
5656 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5657 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5659 case RELOAD_FOR_OUTADDR_ADDRESS
:
5660 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5661 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5663 case RELOAD_FOR_OPERAND_ADDRESS
:
5664 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5665 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5666 && (!reloads_unique_chain_p (r1
, r2
)
5667 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5669 case RELOAD_FOR_OPADDR_ADDR
:
5670 return (r2_type
== RELOAD_FOR_INPUT
5671 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5673 case RELOAD_FOR_OUTPUT
:
5674 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5675 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5676 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5677 && r2_opnum
>= r1_opnum
));
5679 case RELOAD_FOR_INSN
:
5680 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5681 || r2_type
== RELOAD_FOR_INSN
5682 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5684 case RELOAD_FOR_OTHER_ADDRESS
:
5685 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5695 /* Indexed by reload number, 1 if incoming value
5696 inherited from previous insns. */
5697 static char reload_inherited
[MAX_RELOADS
];
5699 /* For an inherited reload, this is the insn the reload was inherited from,
5700 if we know it. Otherwise, this is 0. */
5701 static rtx_insn
*reload_inheritance_insn
[MAX_RELOADS
];
5703 /* If nonzero, this is a place to get the value of the reload,
5704 rather than using reload_in. */
5705 static rtx reload_override_in
[MAX_RELOADS
];
5707 /* For each reload, the hard register number of the register used,
5708 or -1 if we did not need a register for this reload. */
5709 static int reload_spill_index
[MAX_RELOADS
];
5711 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5712 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5714 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5715 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5717 /* Subroutine of free_for_value_p, used to check a single register.
5718 START_REGNO is the starting regno of the full reload register
5719 (possibly comprising multiple hard registers) that we are considering. */
5722 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5723 enum reload_type type
, rtx value
, rtx out
,
5724 int reloadnum
, int ignore_address_reloads
)
5727 /* Set if we see an input reload that must not share its reload register
5728 with any new earlyclobber, but might otherwise share the reload
5729 register with an output or input-output reload. */
5730 int check_earlyclobber
= 0;
5734 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5737 if (out
== const0_rtx
)
5743 /* We use some pseudo 'time' value to check if the lifetimes of the
5744 new register use would overlap with the one of a previous reload
5745 that is not read-only or uses a different value.
5746 The 'time' used doesn't have to be linear in any shape or form, just
5748 Some reload types use different 'buckets' for each operand.
5749 So there are MAX_RECOG_OPERANDS different time values for each
5751 We compute TIME1 as the time when the register for the prospective
5752 new reload ceases to be live, and TIME2 for each existing
5753 reload as the time when that the reload register of that reload
5755 Where there is little to be gained by exact lifetime calculations,
5756 we just make conservative assumptions, i.e. a longer lifetime;
5757 this is done in the 'default:' cases. */
5760 case RELOAD_FOR_OTHER_ADDRESS
:
5761 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5762 time1
= copy
? 0 : 1;
5765 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5767 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5768 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5769 respectively, to the time values for these, we get distinct time
5770 values. To get distinct time values for each operand, we have to
5771 multiply opnum by at least three. We round that up to four because
5772 multiply by four is often cheaper. */
5773 case RELOAD_FOR_INPADDR_ADDRESS
:
5774 time1
= opnum
* 4 + 2;
5776 case RELOAD_FOR_INPUT_ADDRESS
:
5777 time1
= opnum
* 4 + 3;
5779 case RELOAD_FOR_INPUT
:
5780 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5781 executes (inclusive). */
5782 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5784 case RELOAD_FOR_OPADDR_ADDR
:
5786 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5787 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5789 case RELOAD_FOR_OPERAND_ADDRESS
:
5790 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5792 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5794 case RELOAD_FOR_OUTADDR_ADDRESS
:
5795 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5797 case RELOAD_FOR_OUTPUT_ADDRESS
:
5798 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5801 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5804 for (i
= 0; i
< n_reloads
; i
++)
5806 rtx reg
= rld
[i
].reg_rtx
;
5807 if (reg
&& REG_P (reg
)
5808 && (unsigned) regno
- true_regnum (reg
) < REG_NREGS (reg
)
5811 rtx other_input
= rld
[i
].in
;
5813 /* If the other reload loads the same input value, that
5814 will not cause a conflict only if it's loading it into
5815 the same register. */
5816 if (true_regnum (reg
) != start_regno
)
5817 other_input
= NULL_RTX
;
5818 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5819 || rld
[i
].out
|| out
)
5822 switch (rld
[i
].when_needed
)
5824 case RELOAD_FOR_OTHER_ADDRESS
:
5827 case RELOAD_FOR_INPADDR_ADDRESS
:
5828 /* find_reloads makes sure that a
5829 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5830 by at most one - the first -
5831 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5832 address reload is inherited, the address address reload
5833 goes away, so we can ignore this conflict. */
5834 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5835 && ignore_address_reloads
5836 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5837 Then the address address is still needed to store
5838 back the new address. */
5839 && ! rld
[reloadnum
].out
)
5841 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5842 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5844 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5845 && ignore_address_reloads
5846 /* Unless we are reloading an auto_inc expression. */
5847 && ! rld
[reloadnum
].out
)
5849 time2
= rld
[i
].opnum
* 4 + 2;
5851 case RELOAD_FOR_INPUT_ADDRESS
:
5852 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5853 && ignore_address_reloads
5854 && ! rld
[reloadnum
].out
)
5856 time2
= rld
[i
].opnum
* 4 + 3;
5858 case RELOAD_FOR_INPUT
:
5859 time2
= rld
[i
].opnum
* 4 + 4;
5860 check_earlyclobber
= 1;
5862 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5863 == MAX_RECOG_OPERAND * 4 */
5864 case RELOAD_FOR_OPADDR_ADDR
:
5865 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5866 && ignore_address_reloads
5867 && ! rld
[reloadnum
].out
)
5869 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5871 case RELOAD_FOR_OPERAND_ADDRESS
:
5872 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5873 check_earlyclobber
= 1;
5875 case RELOAD_FOR_INSN
:
5876 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5878 case RELOAD_FOR_OUTPUT
:
5879 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5880 instruction is executed. */
5881 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5883 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5884 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5886 case RELOAD_FOR_OUTADDR_ADDRESS
:
5887 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
5888 && ignore_address_reloads
5889 && ! rld
[reloadnum
].out
)
5891 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
5893 case RELOAD_FOR_OUTPUT_ADDRESS
:
5894 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
5897 /* If there is no conflict in the input part, handle this
5898 like an output reload. */
5899 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
5901 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
5902 /* Earlyclobbered outputs must conflict with inputs. */
5903 if (earlyclobber_operand_p (rld
[i
].out
))
5904 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
5909 /* RELOAD_OTHER might be live beyond instruction execution,
5910 but this is not obvious when we set time2 = 1. So check
5911 here if there might be a problem with the new reload
5912 clobbering the register used by the RELOAD_OTHER. */
5920 && (! rld
[i
].in
|| rld
[i
].out
5921 || ! rtx_equal_p (other_input
, value
)))
5922 || (out
&& rld
[reloadnum
].out_reg
5923 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
5929 /* Earlyclobbered outputs must conflict with inputs. */
5930 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
5936 /* Return 1 if the value in reload reg REGNO, as used by a reload
5937 needed for the part of the insn specified by OPNUM and TYPE,
5938 may be used to load VALUE into it.
5940 MODE is the mode in which the register is used, this is needed to
5941 determine how many hard regs to test.
5943 Other read-only reloads with the same value do not conflict
5944 unless OUT is nonzero and these other reloads have to live while
5945 output reloads live.
5946 If OUT is CONST0_RTX, this is a special case: it means that the
5947 test should not be for using register REGNO as reload register, but
5948 for copying from register REGNO into the reload register.
5950 RELOADNUM is the number of the reload we want to load this value for;
5951 a reload does not conflict with itself.
5953 When IGNORE_ADDRESS_RELOADS is set, we cannot have conflicts with
5954 reloads that load an address for the very reload we are considering.
5956 The caller has to make sure that there is no conflict with the return
5960 free_for_value_p (int regno
, machine_mode mode
, int opnum
,
5961 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
5962 int ignore_address_reloads
)
5964 int nregs
= hard_regno_nregs (regno
, mode
);
5966 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
5967 value
, out
, reloadnum
,
5968 ignore_address_reloads
))
5973 /* Return nonzero if the rtx X is invariant over the current function. */
5974 /* ??? Actually, the places where we use this expect exactly what is
5975 tested here, and not everything that is function invariant. In
5976 particular, the frame pointer and arg pointer are special cased;
5977 pic_offset_table_rtx is not, and we must not spill these things to
5981 function_invariant_p (const_rtx x
)
5985 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
5987 if (GET_CODE (x
) == PLUS
5988 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
5989 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
5994 /* Determine whether the reload reg X overlaps any rtx'es used for
5995 overriding inheritance. Return nonzero if so. */
5998 conflicts_with_override (rtx x
)
6001 for (i
= 0; i
< n_reloads
; i
++)
6002 if (reload_override_in
[i
]
6003 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6008 /* Give an error message saying we failed to find a reload for INSN,
6009 and clear out reload R. */
6011 failed_reload (rtx_insn
*insn
, int r
)
6013 if (asm_noperands (PATTERN (insn
)) < 0)
6014 /* It's the compiler's fault. */
6015 fatal_insn ("could not find a spill register", insn
);
6017 /* It's the user's fault; the operand's mode and constraint
6018 don't match. Disable this reload so we don't crash in final. */
6019 error_for_asm (insn
,
6020 "%<asm%> operand constraint incompatible with operand size");
6024 rld
[r
].optional
= 1;
6025 rld
[r
].secondary_p
= 1;
6028 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6029 for reload R. If it's valid, get an rtx for it. Return nonzero if
6032 set_reload_reg (int i
, int r
)
6035 rtx reg
= spill_reg_rtx
[i
];
6037 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6038 spill_reg_rtx
[i
] = reg
6039 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6041 regno
= true_regnum (reg
);
6043 /* Detect when the reload reg can't hold the reload mode.
6044 This used to be one `if', but Sequent compiler can't handle that. */
6045 if (targetm
.hard_regno_mode_ok (regno
, rld
[r
].mode
))
6047 machine_mode test_mode
= VOIDmode
;
6049 test_mode
= GET_MODE (rld
[r
].in
);
6050 /* If rld[r].in has VOIDmode, it means we will load it
6051 in whatever mode the reload reg has: to wit, rld[r].mode.
6052 We have already tested that for validity. */
6053 /* Aside from that, we need to test that the expressions
6054 to reload from or into have modes which are valid for this
6055 reload register. Otherwise the reload insns would be invalid. */
6056 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6057 && !targetm
.hard_regno_mode_ok (regno
, test_mode
)))
6058 if (! (rld
[r
].out
!= 0
6059 && !targetm
.hard_regno_mode_ok (regno
, GET_MODE (rld
[r
].out
))))
6061 /* The reg is OK. */
6064 /* Mark as in use for this insn the reload regs we use
6066 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6067 rld
[r
].when_needed
, rld
[r
].mode
);
6069 rld
[r
].reg_rtx
= reg
;
6070 reload_spill_index
[r
] = spill_regs
[i
];
6077 /* Find a spill register to use as a reload register for reload R.
6078 LAST_RELOAD is nonzero if this is the last reload for the insn being
6081 Set rld[R].reg_rtx to the register allocated.
6083 We return 1 if successful, or 0 if we couldn't find a spill reg and
6084 we didn't change anything. */
6087 allocate_reload_reg (class insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6092 /* If we put this reload ahead, thinking it is a group,
6093 then insist on finding a group. Otherwise we can grab a
6094 reg that some other reload needs.
6095 (That can happen when we have a 68000 DATA_OR_FP_REG
6096 which is a group of data regs or one fp reg.)
6097 We need not be so restrictive if there are no more reloads
6100 ??? Really it would be nicer to have smarter handling
6101 for that kind of reg class, where a problem like this is normal.
6102 Perhaps those classes should be avoided for reloading
6103 by use of more alternatives. */
6105 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6107 /* If we want a single register and haven't yet found one,
6108 take any reg in the right class and not in use.
6109 If we want a consecutive group, here is where we look for it.
6111 We use three passes so we can first look for reload regs to
6112 reuse, which are already in use for other reloads in this insn,
6113 and only then use additional registers which are not "bad", then
6114 finally any register.
6116 I think that maximizing reuse is needed to make sure we don't
6117 run out of reload regs. Suppose we have three reloads, and
6118 reloads A and B can share regs. These need two regs.
6119 Suppose A and B are given different regs.
6120 That leaves none for C. */
6121 for (pass
= 0; pass
< 3; pass
++)
6123 /* I is the index in spill_regs.
6124 We advance it round-robin between insns to use all spill regs
6125 equally, so that inherited reloads have a chance
6126 of leapfrogging each other. */
6130 for (count
= 0; count
< n_spills
; count
++)
6132 int rclass
= (int) rld
[r
].rclass
;
6138 regnum
= spill_regs
[i
];
6140 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6143 /* We check reload_reg_used to make sure we
6144 don't clobber the return register. */
6145 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6146 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6147 rld
[r
].when_needed
, rld
[r
].in
,
6149 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6150 && targetm
.hard_regno_mode_ok (regnum
, rld
[r
].mode
)
6151 /* Look first for regs to share, then for unshared. But
6152 don't share regs used for inherited reloads; they are
6153 the ones we want to preserve. */
6155 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6157 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6160 int nr
= hard_regno_nregs (regnum
, rld
[r
].mode
);
6162 /* During the second pass we want to avoid reload registers
6163 which are "bad" for this reload. */
6165 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6168 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6169 (on 68000) got us two FP regs. If NR is 1,
6170 we would reject both of them. */
6173 /* If we need only one reg, we have already won. */
6176 /* But reject a single reg if we demand a group. */
6181 /* Otherwise check that as many consecutive regs as we need
6182 are available here. */
6185 int regno
= regnum
+ nr
- 1;
6186 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6187 && spill_reg_order
[regno
] >= 0
6188 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6189 rld
[r
].when_needed
)))
6198 /* If we found something on the current pass, omit later passes. */
6199 if (count
< n_spills
)
6203 /* We should have found a spill register by now. */
6204 if (count
>= n_spills
)
6207 /* I is the index in SPILL_REG_RTX of the reload register we are to
6208 allocate. Get an rtx for it and find its register number. */
6210 return set_reload_reg (i
, r
);
6213 /* Initialize all the tables needed to allocate reload registers.
6214 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6215 is the array we use to restore the reg_rtx field for every reload. */
6218 choose_reload_regs_init (class insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6222 for (i
= 0; i
< n_reloads
; i
++)
6223 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6225 memset (reload_inherited
, 0, MAX_RELOADS
);
6226 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6227 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6229 CLEAR_HARD_REG_SET (reload_reg_used
);
6230 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6231 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6232 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6233 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6234 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6236 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6239 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6240 reg_used_in_insn
|= tmp
;
6241 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6242 reg_used_in_insn
|= tmp
;
6243 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6244 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6247 for (i
= 0; i
< reload_n_operands
; i
++)
6249 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6250 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6251 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6252 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6253 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6254 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6257 reload_reg_unavailable
= ~chain
->used_spill_regs
;
6259 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6261 for (i
= 0; i
< n_reloads
; i
++)
6262 /* If we have already decided to use a certain register,
6263 don't use it in another way. */
6265 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6266 rld
[i
].when_needed
, rld
[i
].mode
);
6269 /* If X is not a subreg, return it unmodified. If it is a subreg,
6270 look up whether we made a replacement for the SUBREG_REG. Return
6271 either the replacement or the SUBREG_REG. */
6274 replaced_subreg (rtx x
)
6276 if (GET_CODE (x
) == SUBREG
)
6277 return find_replacement (&SUBREG_REG (x
));
6281 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6282 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6283 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6284 otherwise it is NULL. */
6287 compute_reload_subreg_offset (machine_mode outermode
,
6289 machine_mode innermode
)
6291 poly_int64 outer_offset
;
6292 machine_mode middlemode
;
6295 return subreg_lowpart_offset (outermode
, innermode
);
6297 outer_offset
= SUBREG_BYTE (subreg
);
6298 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6300 /* If SUBREG is paradoxical then return the normal lowpart offset
6301 for OUTERMODE and INNERMODE. Our caller has already checked
6302 that OUTERMODE fits in INNERMODE. */
6303 if (paradoxical_subreg_p (outermode
, middlemode
))
6304 return subreg_lowpart_offset (outermode
, innermode
);
6306 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6307 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6308 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6311 /* Assign hard reg targets for the pseudo-registers we must reload
6312 into hard regs for this insn.
6313 Also output the instructions to copy them in and out of the hard regs.
6315 For machines with register classes, we are responsible for
6316 finding a reload reg in the proper class. */
6319 choose_reload_regs (class insn_chain
*chain
)
6321 rtx_insn
*insn
= chain
->insn
;
6323 unsigned int max_group_size
= 1;
6324 enum reg_class group_class
= NO_REGS
;
6325 int pass
, win
, inheritance
;
6327 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6329 /* In order to be certain of getting the registers we need,
6330 we must sort the reloads into order of increasing register class.
6331 Then our grabbing of reload registers will parallel the process
6332 that provided the reload registers.
6334 Also note whether any of the reloads wants a consecutive group of regs.
6335 If so, record the maximum size of the group desired and what
6336 register class contains all the groups needed by this insn. */
6338 for (j
= 0; j
< n_reloads
; j
++)
6340 reload_order
[j
] = j
;
6341 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6343 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6344 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6345 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6348 reload_spill_index
[j
] = -1;
6350 if (rld
[j
].nregs
> 1)
6352 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6354 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6357 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6361 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6363 /* If -O, try first with inheritance, then turning it off.
6364 If not -O, don't do inheritance.
6365 Using inheritance when not optimizing leads to paradoxes
6366 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6367 because one side of the comparison might be inherited. */
6369 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6371 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6373 /* Process the reloads in order of preference just found.
6374 Beyond this point, subregs can be found in reload_reg_rtx.
6376 This used to look for an existing reloaded home for all of the
6377 reloads, and only then perform any new reloads. But that could lose
6378 if the reloads were done out of reg-class order because a later
6379 reload with a looser constraint might have an old home in a register
6380 needed by an earlier reload with a tighter constraint.
6382 To solve this, we make two passes over the reloads, in the order
6383 described above. In the first pass we try to inherit a reload
6384 from a previous insn. If there is a later reload that needs a
6385 class that is a proper subset of the class being processed, we must
6386 also allocate a spill register during the first pass.
6388 Then make a second pass over the reloads to allocate any reloads
6389 that haven't been given registers yet. */
6391 for (j
= 0; j
< n_reloads
; j
++)
6393 int r
= reload_order
[j
];
6394 rtx search_equiv
= NULL_RTX
;
6396 /* Ignore reloads that got marked inoperative. */
6397 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6398 && ! rld
[r
].secondary_p
)
6401 /* If find_reloads chose to use reload_in or reload_out as a reload
6402 register, we don't need to chose one. Otherwise, try even if it
6403 found one since we might save an insn if we find the value lying
6405 Try also when reload_in is a pseudo without a hard reg. */
6406 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6407 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6408 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6409 && !MEM_P (rld
[r
].in
)
6410 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6413 #if 0 /* No longer needed for correct operation.
6414 It might give better code, or might not; worth an experiment? */
6415 /* If this is an optional reload, we can't inherit from earlier insns
6416 until we are sure that any non-optional reloads have been allocated.
6417 The following code takes advantage of the fact that optional reloads
6418 are at the end of reload_order. */
6419 if (rld
[r
].optional
!= 0)
6420 for (i
= 0; i
< j
; i
++)
6421 if ((rld
[reload_order
[i
]].out
!= 0
6422 || rld
[reload_order
[i
]].in
!= 0
6423 || rld
[reload_order
[i
]].secondary_p
)
6424 && ! rld
[reload_order
[i
]].optional
6425 && rld
[reload_order
[i
]].reg_rtx
== 0)
6426 allocate_reload_reg (chain
, reload_order
[i
], 0);
6429 /* First see if this pseudo is already available as reloaded
6430 for a previous insn. We cannot try to inherit for reloads
6431 that are smaller than the maximum number of registers needed
6432 for groups unless the register we would allocate cannot be used
6435 We could check here to see if this is a secondary reload for
6436 an object that is already in a register of the desired class.
6437 This would avoid the need for the secondary reload register.
6438 But this is complex because we can't easily determine what
6439 objects might want to be loaded via this reload. So let a
6440 register be allocated here. In `emit_reload_insns' we suppress
6441 one of the loads in the case described above. */
6445 poly_int64 byte
= 0;
6447 machine_mode mode
= VOIDmode
;
6448 rtx subreg
= NULL_RTX
;
6452 else if (REG_P (rld
[r
].in
))
6454 regno
= REGNO (rld
[r
].in
);
6455 mode
= GET_MODE (rld
[r
].in
);
6457 else if (REG_P (rld
[r
].in_reg
))
6459 regno
= REGNO (rld
[r
].in_reg
);
6460 mode
= GET_MODE (rld
[r
].in_reg
);
6462 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6463 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6465 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6466 if (regno
< FIRST_PSEUDO_REGISTER
)
6467 regno
= subreg_regno (rld
[r
].in_reg
);
6470 subreg
= rld
[r
].in_reg
;
6471 byte
= SUBREG_BYTE (subreg
);
6473 mode
= GET_MODE (rld
[r
].in_reg
);
6476 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6477 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6479 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6480 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6481 rld
[r
].out
= rld
[r
].in
;
6485 /* This won't work, since REGNO can be a pseudo reg number.
6486 Also, it takes much more hair to keep track of all the things
6487 that can invalidate an inherited reload of part of a pseudoreg. */
6488 else if (GET_CODE (rld
[r
].in
) == SUBREG
6489 && REG_P (SUBREG_REG (rld
[r
].in
)))
6490 regno
= subreg_regno (rld
[r
].in
);
6494 && reg_last_reload_reg
[regno
] != 0
6496 (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
])),
6497 GET_MODE_SIZE (mode
) + byte
))
6498 /* Verify that the register it's in can be used in
6500 && (REG_CAN_CHANGE_MODE_P
6501 (REGNO (reg_last_reload_reg
[regno
]),
6502 GET_MODE (reg_last_reload_reg
[regno
]),
6505 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6506 rtx last_reg
= reg_last_reload_reg
[regno
];
6508 i
= REGNO (last_reg
);
6509 byte
= compute_reload_subreg_offset (mode
,
6511 GET_MODE (last_reg
));
6512 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6513 last_class
= REGNO_REG_CLASS (i
);
6515 if (reg_reloaded_contents
[i
] == regno
6516 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6517 && targetm
.hard_regno_mode_ok (i
, rld
[r
].mode
)
6518 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6519 /* Even if we can't use this register as a reload
6520 register, we might use it for reload_override_in,
6521 if copying it to the desired class is cheap
6523 || ((register_move_cost (mode
, last_class
, rclass
)
6524 < memory_move_cost (mode
, rclass
, true))
6525 && (secondary_reload_class (1, rclass
, mode
,
6528 && !(targetm
.secondary_memory_needed
6529 (mode
, last_class
, rclass
))))
6530 && (rld
[r
].nregs
== max_group_size
6531 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6533 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6534 rld
[r
].when_needed
, rld
[r
].in
,
6537 /* If a group is needed, verify that all the subsequent
6538 registers still have their values intact. */
6539 int nr
= hard_regno_nregs (i
, rld
[r
].mode
);
6542 for (k
= 1; k
< nr
; k
++)
6543 if (reg_reloaded_contents
[i
+ k
] != regno
6544 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6552 last_reg
= (GET_MODE (last_reg
) == mode
6553 ? last_reg
: gen_rtx_REG (mode
, i
));
6556 for (k
= 0; k
< nr
; k
++)
6557 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6560 /* We found a register that contains the
6561 value we need. If this register is the
6562 same as an `earlyclobber' operand of the
6563 current insn, just mark it as a place to
6564 reload from since we can't use it as the
6565 reload register itself. */
6567 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6568 if (reg_overlap_mentioned_for_reload_p
6569 (reg_last_reload_reg
[regno
],
6570 reload_earlyclobbers
[i1
]))
6573 if (i1
!= n_earlyclobbers
6574 || ! (free_for_value_p (i
, rld
[r
].mode
,
6576 rld
[r
].when_needed
, rld
[r
].in
,
6578 /* Don't use it if we'd clobber a pseudo reg. */
6579 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6581 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6582 /* Don't clobber the frame pointer. */
6583 || (i
== HARD_FRAME_POINTER_REGNUM
6584 && frame_pointer_needed
6586 /* Don't really use the inherited spill reg
6587 if we need it wider than we've got it. */
6588 || paradoxical_subreg_p (rld
[r
].mode
, mode
)
6591 /* If find_reloads chose reload_out as reload
6592 register, stay with it - that leaves the
6593 inherited register for subsequent reloads. */
6594 || (rld
[r
].out
&& rld
[r
].reg_rtx
6595 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6597 if (! rld
[r
].optional
)
6599 reload_override_in
[r
] = last_reg
;
6600 reload_inheritance_insn
[r
]
6601 = reg_reloaded_insn
[i
];
6607 /* We can use this as a reload reg. */
6608 /* Mark the register as in use for this part of
6610 mark_reload_reg_in_use (i
,
6614 rld
[r
].reg_rtx
= last_reg
;
6615 reload_inherited
[r
] = 1;
6616 reload_inheritance_insn
[r
]
6617 = reg_reloaded_insn
[i
];
6618 reload_spill_index
[r
] = i
;
6619 for (k
= 0; k
< nr
; k
++)
6620 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6628 /* Here's another way to see if the value is already lying around. */
6631 && ! reload_inherited
[r
]
6633 && (CONSTANT_P (rld
[r
].in
)
6634 || GET_CODE (rld
[r
].in
) == PLUS
6635 || REG_P (rld
[r
].in
)
6636 || MEM_P (rld
[r
].in
))
6637 && (rld
[r
].nregs
== max_group_size
6638 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6639 search_equiv
= rld
[r
].in
;
6644 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6645 -1, NULL
, 0, rld
[r
].mode
);
6651 regno
= REGNO (equiv
);
6654 /* This must be a SUBREG of a hard register.
6655 Make a new REG since this might be used in an
6656 address and not all machines support SUBREGs
6658 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6659 regno
= subreg_regno (equiv
);
6660 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6661 /* If we choose EQUIV as the reload register, but the
6662 loop below decides to cancel the inheritance, we'll
6663 end up reloading EQUIV in rld[r].mode, not the mode
6664 it had originally. That isn't safe when EQUIV isn't
6665 available as a spill register since its value might
6666 still be live at this point. */
6667 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6668 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6673 /* If we found a spill reg, reject it unless it is free
6674 and of the desired class. */
6678 int bad_for_class
= 0;
6679 int max_regno
= regno
+ rld
[r
].nregs
;
6681 for (i
= regno
; i
< max_regno
; i
++)
6683 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6685 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6690 && ! free_for_value_p (regno
, rld
[r
].mode
,
6691 rld
[r
].opnum
, rld
[r
].when_needed
,
6692 rld
[r
].in
, rld
[r
].out
, r
, 1))
6698 && !targetm
.hard_regno_mode_ok (regno
, rld
[r
].mode
))
6701 /* We found a register that contains the value we need.
6702 If this register is the same as an `earlyclobber' operand
6703 of the current insn, just mark it as a place to reload from
6704 since we can't use it as the reload register itself. */
6707 for (i
= 0; i
< n_earlyclobbers
; i
++)
6708 if (reg_overlap_mentioned_for_reload_p (equiv
,
6709 reload_earlyclobbers
[i
]))
6711 if (! rld
[r
].optional
)
6712 reload_override_in
[r
] = equiv
;
6717 /* If the equiv register we have found is explicitly clobbered
6718 in the current insn, it depends on the reload type if we
6719 can use it, use it for reload_override_in, or not at all.
6720 In particular, we then can't use EQUIV for a
6721 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6725 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6726 switch (rld
[r
].when_needed
)
6728 case RELOAD_FOR_OTHER_ADDRESS
:
6729 case RELOAD_FOR_INPADDR_ADDRESS
:
6730 case RELOAD_FOR_INPUT_ADDRESS
:
6731 case RELOAD_FOR_OPADDR_ADDR
:
6734 case RELOAD_FOR_INPUT
:
6735 case RELOAD_FOR_OPERAND_ADDRESS
:
6736 if (! rld
[r
].optional
)
6737 reload_override_in
[r
] = equiv
;
6743 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6744 switch (rld
[r
].when_needed
)
6746 case RELOAD_FOR_OTHER_ADDRESS
:
6747 case RELOAD_FOR_INPADDR_ADDRESS
:
6748 case RELOAD_FOR_INPUT_ADDRESS
:
6749 case RELOAD_FOR_OPADDR_ADDR
:
6750 case RELOAD_FOR_OPERAND_ADDRESS
:
6751 case RELOAD_FOR_INPUT
:
6754 if (! rld
[r
].optional
)
6755 reload_override_in
[r
] = equiv
;
6763 /* If we found an equivalent reg, say no code need be generated
6764 to load it, and use it as our reload reg. */
6766 && (regno
!= HARD_FRAME_POINTER_REGNUM
6767 || !frame_pointer_needed
))
6769 int nr
= hard_regno_nregs (regno
, rld
[r
].mode
);
6771 rld
[r
].reg_rtx
= equiv
;
6772 reload_spill_index
[r
] = regno
;
6773 reload_inherited
[r
] = 1;
6775 /* If reg_reloaded_valid is not set for this register,
6776 there might be a stale spill_reg_store lying around.
6777 We must clear it, since otherwise emit_reload_insns
6778 might delete the store. */
6779 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6780 spill_reg_store
[regno
] = NULL
;
6781 /* If any of the hard registers in EQUIV are spill
6782 registers, mark them as in use for this insn. */
6783 for (k
= 0; k
< nr
; k
++)
6785 i
= spill_reg_order
[regno
+ k
];
6788 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6791 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6798 /* If we found a register to use already, or if this is an optional
6799 reload, we are done. */
6800 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6804 /* No longer needed for correct operation. Might or might
6805 not give better code on the average. Want to experiment? */
6807 /* See if there is a later reload that has a class different from our
6808 class that intersects our class or that requires less register
6809 than our reload. If so, we must allocate a register to this
6810 reload now, since that reload might inherit a previous reload
6811 and take the only available register in our class. Don't do this
6812 for optional reloads since they will force all previous reloads
6813 to be allocated. Also don't do this for reloads that have been
6816 for (i
= j
+ 1; i
< n_reloads
; i
++)
6818 int s
= reload_order
[i
];
6820 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6821 && ! rld
[s
].secondary_p
)
6825 if ((rld
[s
].rclass
!= rld
[r
].rclass
6826 && reg_classes_intersect_p (rld
[r
].rclass
,
6828 || rld
[s
].nregs
< rld
[r
].nregs
)
6835 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6839 /* Now allocate reload registers for anything non-optional that
6840 didn't get one yet. */
6841 for (j
= 0; j
< n_reloads
; j
++)
6843 int r
= reload_order
[j
];
6845 /* Ignore reloads that got marked inoperative. */
6846 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6849 /* Skip reloads that already have a register allocated or are
6851 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6854 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6858 /* If that loop got all the way, we have won. */
6865 /* Loop around and try without any inheritance. */
6870 /* First undo everything done by the failed attempt
6871 to allocate with inheritance. */
6872 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6874 /* Some sanity tests to verify that the reloads found in the first
6875 pass are identical to the ones we have now. */
6876 gcc_assert (chain
->n_reloads
== n_reloads
);
6878 for (i
= 0; i
< n_reloads
; i
++)
6880 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
6882 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
6883 for (j
= 0; j
< n_spills
; j
++)
6884 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
6885 if (! set_reload_reg (j
, i
))
6886 failed_reload (chain
->insn
, i
);
6890 /* If we thought we could inherit a reload, because it seemed that
6891 nothing else wanted the same reload register earlier in the insn,
6892 verify that assumption, now that all reloads have been assigned.
6893 Likewise for reloads where reload_override_in has been set. */
6895 /* If doing expensive optimizations, do one preliminary pass that doesn't
6896 cancel any inheritance, but removes reloads that have been needed only
6897 for reloads that we know can be inherited. */
6898 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
6900 for (j
= 0; j
< n_reloads
; j
++)
6902 int r
= reload_order
[j
];
6905 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
6906 check_reg
= rld
[r
].reg_rtx
;
6907 else if (reload_override_in
[r
]
6908 && (REG_P (reload_override_in
[r
])
6909 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
6910 check_reg
= reload_override_in
[r
];
6913 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
6914 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
6915 (reload_inherited
[r
]
6916 ? rld
[r
].out
: const0_rtx
),
6921 reload_inherited
[r
] = 0;
6922 reload_override_in
[r
] = 0;
6924 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6925 reload_override_in, then we do not need its related
6926 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6927 likewise for other reload types.
6928 We handle this by removing a reload when its only replacement
6929 is mentioned in reload_in of the reload we are going to inherit.
6930 A special case are auto_inc expressions; even if the input is
6931 inherited, we still need the address for the output. We can
6932 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6933 If we succeeded removing some reload and we are doing a preliminary
6934 pass just to remove such reloads, make another pass, since the
6935 removal of one reload might allow us to inherit another one. */
6937 && rld
[r
].out
!= rld
[r
].in
6938 && remove_address_replacements (rld
[r
].in
))
6943 /* If we needed a memory location for the reload, we also have to
6944 remove its related reloads. */
6946 && rld
[r
].out
!= rld
[r
].in
6947 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
6948 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
6949 && (targetm
.secondary_memory_needed
6950 (rld
[r
].inmode
, REGNO_REG_CLASS (REGNO (tem
)),
6952 && remove_address_replacements
6953 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
6954 rld
[r
].when_needed
)))
6962 /* Now that reload_override_in is known valid,
6963 actually override reload_in. */
6964 for (j
= 0; j
< n_reloads
; j
++)
6965 if (reload_override_in
[j
])
6966 rld
[j
].in
= reload_override_in
[j
];
6968 /* If this reload won't be done because it has been canceled or is
6969 optional and not inherited, clear reload_reg_rtx so other
6970 routines (such as subst_reloads) don't get confused. */
6971 for (j
= 0; j
< n_reloads
; j
++)
6972 if (rld
[j
].reg_rtx
!= 0
6973 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
6974 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
6975 && ! rld
[j
].secondary_p
)))
6977 int regno
= true_regnum (rld
[j
].reg_rtx
);
6979 if (spill_reg_order
[regno
] >= 0)
6980 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
6981 rld
[j
].when_needed
, rld
[j
].mode
);
6983 reload_spill_index
[j
] = -1;
6986 /* Record which pseudos and which spill regs have output reloads. */
6987 for (j
= 0; j
< n_reloads
; j
++)
6989 int r
= reload_order
[j
];
6991 i
= reload_spill_index
[r
];
6993 /* I is nonneg if this reload uses a register.
6994 If rld[r].reg_rtx is 0, this is an optional reload
6995 that we opted to ignore. */
6996 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
6997 && rld
[r
].reg_rtx
!= 0)
6999 int nregno
= REGNO (rld
[r
].out_reg
);
7002 if (nregno
< FIRST_PSEUDO_REGISTER
)
7003 nr
= hard_regno_nregs (nregno
, rld
[r
].mode
);
7006 SET_REGNO_REG_SET (®_has_output_reload
,
7010 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7012 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7013 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7014 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7019 /* Deallocate the reload register for reload R. This is called from
7020 remove_address_replacements. */
7023 deallocate_reload_reg (int r
)
7027 if (! rld
[r
].reg_rtx
)
7029 regno
= true_regnum (rld
[r
].reg_rtx
);
7031 if (spill_reg_order
[regno
] >= 0)
7032 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7034 reload_spill_index
[r
] = -1;
7037 /* These arrays are filled by emit_reload_insns and its subroutines. */
7038 static rtx_insn
*input_reload_insns
[MAX_RECOG_OPERANDS
];
7039 static rtx_insn
*other_input_address_reload_insns
= 0;
7040 static rtx_insn
*other_input_reload_insns
= 0;
7041 static rtx_insn
*input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7042 static rtx_insn
*inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7043 static rtx_insn
*output_reload_insns
[MAX_RECOG_OPERANDS
];
7044 static rtx_insn
*output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7045 static rtx_insn
*outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7046 static rtx_insn
*operand_reload_insns
= 0;
7047 static rtx_insn
*other_operand_reload_insns
= 0;
7048 static rtx_insn
*other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7050 /* Values to be put in spill_reg_store are put here first. Instructions
7051 must only be placed here if the associated reload register reaches
7052 the end of the instruction's reload sequence. */
7053 static rtx_insn
*new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7054 static HARD_REG_SET reg_reloaded_died
;
7056 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7057 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7058 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7059 adjusted register, and return true. Otherwise, return false. */
7061 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7062 enum reg_class new_class
,
7063 machine_mode new_mode
)
7068 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7070 unsigned regno
= REGNO (reg
);
7072 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7074 if (GET_MODE (reg
) != new_mode
)
7076 if (!targetm
.hard_regno_mode_ok (regno
, new_mode
))
7078 if (hard_regno_nregs (regno
, new_mode
) > REG_NREGS (reg
))
7080 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7088 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7089 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7090 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7091 adjusted register, and return true. Otherwise, return false. */
7093 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7094 enum insn_code icode
)
7097 enum reg_class new_class
= scratch_reload_class (icode
);
7098 machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7100 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7101 new_class
, new_mode
);
7104 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7105 has the number J. OLD contains the value to be used as input. */
7108 emit_input_reload_insns (class insn_chain
*chain
, struct reload
*rl
,
7111 rtx_insn
*insn
= chain
->insn
;
7113 rtx oldequiv_reg
= 0;
7119 /* delete_output_reload is only invoked properly if old contains
7120 the original pseudo register. Since this is replaced with a
7121 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7122 find the pseudo in RELOAD_IN_REG. This is also used to
7123 determine whether a secondary reload is needed. */
7124 if (reload_override_in
[j
]
7125 && (REG_P (rl
->in_reg
)
7126 || (GET_CODE (rl
->in_reg
) == SUBREG
7127 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7134 else if (REG_P (oldequiv
))
7135 oldequiv_reg
= oldequiv
;
7136 else if (GET_CODE (oldequiv
) == SUBREG
)
7137 oldequiv_reg
= SUBREG_REG (oldequiv
);
7139 reloadreg
= reload_reg_rtx_for_input
[j
];
7140 mode
= GET_MODE (reloadreg
);
7142 /* If we are reloading from a register that was recently stored in
7143 with an output-reload, see if we can prove there was
7144 actually no need to store the old value in it. */
7146 if (optimize
&& REG_P (oldequiv
)
7147 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7148 && spill_reg_store
[REGNO (oldequiv
)]
7150 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7151 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7153 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7155 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7158 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7159 oldequiv
= SUBREG_REG (oldequiv
);
7160 if (GET_MODE (oldequiv
) != VOIDmode
7161 && mode
!= GET_MODE (oldequiv
))
7162 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7164 /* Switch to the right place to emit the reload insns. */
7165 switch (rl
->when_needed
)
7168 where
= &other_input_reload_insns
;
7170 case RELOAD_FOR_INPUT
:
7171 where
= &input_reload_insns
[rl
->opnum
];
7173 case RELOAD_FOR_INPUT_ADDRESS
:
7174 where
= &input_address_reload_insns
[rl
->opnum
];
7176 case RELOAD_FOR_INPADDR_ADDRESS
:
7177 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7179 case RELOAD_FOR_OUTPUT_ADDRESS
:
7180 where
= &output_address_reload_insns
[rl
->opnum
];
7182 case RELOAD_FOR_OUTADDR_ADDRESS
:
7183 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7185 case RELOAD_FOR_OPERAND_ADDRESS
:
7186 where
= &operand_reload_insns
;
7188 case RELOAD_FOR_OPADDR_ADDR
:
7189 where
= &other_operand_reload_insns
;
7191 case RELOAD_FOR_OTHER_ADDRESS
:
7192 where
= &other_input_address_reload_insns
;
7198 push_to_sequence (*where
);
7200 /* Auto-increment addresses must be reloaded in a special way. */
7201 if (rl
->out
&& ! rl
->out_reg
)
7203 /* We are not going to bother supporting the case where a
7204 incremented register can't be copied directly from
7205 OLDEQUIV since this seems highly unlikely. */
7206 gcc_assert (rl
->secondary_in_reload
< 0);
7208 if (reload_inherited
[j
])
7209 oldequiv
= reloadreg
;
7211 old
= XEXP (rl
->in_reg
, 0);
7213 /* Prevent normal processing of this reload. */
7215 /* Output a special code sequence for this case. */
7216 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7219 /* If we are reloading a pseudo-register that was set by the previous
7220 insn, see if we can get rid of that pseudo-register entirely
7221 by redirecting the previous insn into our reload register. */
7223 else if (optimize
&& REG_P (old
)
7224 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7225 && dead_or_set_p (insn
, old
)
7226 /* This is unsafe if some other reload
7227 uses the same reg first. */
7228 && ! conflicts_with_override (reloadreg
)
7229 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7230 rl
->when_needed
, old
, rl
->out
, j
, 0))
7232 rtx_insn
*temp
= PREV_INSN (insn
);
7233 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7234 temp
= PREV_INSN (temp
);
7236 && NONJUMP_INSN_P (temp
)
7237 && GET_CODE (PATTERN (temp
)) == SET
7238 && SET_DEST (PATTERN (temp
)) == old
7239 /* Make sure we can access insn_operand_constraint. */
7240 && asm_noperands (PATTERN (temp
)) < 0
7241 /* This is unsafe if operand occurs more than once in current
7242 insn. Perhaps some occurrences aren't reloaded. */
7243 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7245 rtx old
= SET_DEST (PATTERN (temp
));
7246 /* Store into the reload register instead of the pseudo. */
7247 SET_DEST (PATTERN (temp
)) = reloadreg
;
7249 /* Verify that resulting insn is valid.
7251 Note that we have replaced the destination of TEMP with
7252 RELOADREG. If TEMP references RELOADREG within an
7253 autoincrement addressing mode, then the resulting insn
7254 is ill-formed and we must reject this optimization. */
7255 extract_insn (temp
);
7256 if (constrain_operands (1, get_enabled_alternatives (temp
))
7257 && (!AUTO_INC_DEC
|| ! find_reg_note (temp
, REG_INC
, reloadreg
)))
7259 /* If the previous insn is an output reload, the source is
7260 a reload register, and its spill_reg_store entry will
7261 contain the previous destination. This is now
7263 if (REG_P (SET_SRC (PATTERN (temp
)))
7264 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7266 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7267 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7270 /* If these are the only uses of the pseudo reg,
7271 pretend for GDB it lives in the reload reg we used. */
7272 if (REG_N_DEATHS (REGNO (old
)) == 1
7273 && REG_N_SETS (REGNO (old
)) == 1)
7275 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7276 if (ira_conflicts_p
)
7277 /* Inform IRA about the change. */
7278 ira_mark_allocation_change (REGNO (old
));
7279 alter_reg (REGNO (old
), -1, false);
7283 /* Adjust any debug insns between temp and insn. */
7284 while ((temp
= NEXT_INSN (temp
)) != insn
)
7285 if (DEBUG_BIND_INSN_P (temp
))
7286 INSN_VAR_LOCATION_LOC (temp
)
7287 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp
),
7290 gcc_assert (DEBUG_INSN_P (temp
) || NOTE_P (temp
));
7294 SET_DEST (PATTERN (temp
)) = old
;
7299 /* We can't do that, so output an insn to load RELOADREG. */
7301 /* If we have a secondary reload, pick up the secondary register
7302 and icode, if any. If OLDEQUIV and OLD are different or
7303 if this is an in-out reload, recompute whether or not we
7304 still need a secondary register and what the icode should
7305 be. If we still need a secondary register and the class or
7306 icode is different, go back to reloading from OLD if using
7307 OLDEQUIV means that we got the wrong type of register. We
7308 cannot have different class or icode due to an in-out reload
7309 because we don't make such reloads when both the input and
7310 output need secondary reload registers. */
7312 if (! special
&& rl
->secondary_in_reload
>= 0)
7314 rtx second_reload_reg
= 0;
7315 rtx third_reload_reg
= 0;
7316 int secondary_reload
= rl
->secondary_in_reload
;
7317 rtx real_oldequiv
= oldequiv
;
7320 enum insn_code icode
;
7321 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7323 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7324 and similarly for OLD.
7325 See comments in get_secondary_reload in reload.c. */
7326 /* If it is a pseudo that cannot be replaced with its
7327 equivalent MEM, we must fall back to reload_in, which
7328 will have all the necessary substitutions registered.
7329 Likewise for a pseudo that can't be replaced with its
7330 equivalent constant.
7332 Take extra care for subregs of such pseudos. Note that
7333 we cannot use reg_equiv_mem in this case because it is
7334 not in the right mode. */
7337 if (GET_CODE (tmp
) == SUBREG
)
7338 tmp
= SUBREG_REG (tmp
);
7340 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7341 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7342 || reg_equiv_constant (REGNO (tmp
)) != 0))
7344 if (! reg_equiv_mem (REGNO (tmp
))
7345 || num_not_at_initial_offset
7346 || GET_CODE (oldequiv
) == SUBREG
)
7347 real_oldequiv
= rl
->in
;
7349 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7353 if (GET_CODE (tmp
) == SUBREG
)
7354 tmp
= SUBREG_REG (tmp
);
7356 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7357 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7358 || reg_equiv_constant (REGNO (tmp
)) != 0))
7360 if (! reg_equiv_mem (REGNO (tmp
))
7361 || num_not_at_initial_offset
7362 || GET_CODE (old
) == SUBREG
)
7365 real_old
= reg_equiv_mem (REGNO (tmp
));
7368 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7369 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7371 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7373 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7374 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7375 /* We'd have to add more code for quartary reloads. */
7376 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7378 icode
= rl
->secondary_in_icode
;
7380 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7381 || (rl
->in
!= 0 && rl
->out
!= 0))
7383 secondary_reload_info sri
, sri2
;
7384 enum reg_class new_class
, new_t_class
;
7386 sri
.icode
= CODE_FOR_nothing
;
7387 sri
.prev_sri
= NULL
;
7389 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7393 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7394 second_reload_reg
= 0;
7395 else if (new_class
== NO_REGS
)
7397 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7399 (enum insn_code
) sri
.icode
))
7401 icode
= (enum insn_code
) sri
.icode
;
7402 third_reload_reg
= 0;
7407 real_oldequiv
= real_old
;
7410 else if (sri
.icode
!= CODE_FOR_nothing
)
7411 /* We currently lack a way to express this in reloads. */
7415 sri2
.icode
= CODE_FOR_nothing
;
7416 sri2
.prev_sri
= &sri
;
7418 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7421 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7423 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7427 third_reload_reg
= 0;
7428 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7433 real_oldequiv
= real_old
;
7436 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7438 rtx intermediate
= second_reload_reg
;
7440 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7442 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7446 second_reload_reg
= intermediate
;
7447 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7452 real_oldequiv
= real_old
;
7455 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7457 rtx intermediate
= second_reload_reg
;
7459 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7461 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7464 second_reload_reg
= intermediate
;
7465 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7470 real_oldequiv
= real_old
;
7475 /* This could be handled more intelligently too. */
7477 real_oldequiv
= real_old
;
7482 /* If we still need a secondary reload register, check
7483 to see if it is being used as a scratch or intermediate
7484 register and generate code appropriately. If we need
7485 a scratch register, use REAL_OLDEQUIV since the form of
7486 the insn may depend on the actual address if it is
7489 if (second_reload_reg
)
7491 if (icode
!= CODE_FOR_nothing
)
7493 /* We'd have to add extra code to handle this case. */
7494 gcc_assert (!third_reload_reg
);
7496 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7497 second_reload_reg
));
7502 /* See if we need a scratch register to load the
7503 intermediate register (a tertiary reload). */
7504 if (tertiary_icode
!= CODE_FOR_nothing
)
7506 emit_insn ((GEN_FCN (tertiary_icode
)
7507 (second_reload_reg
, real_oldequiv
,
7508 third_reload_reg
)));
7510 else if (third_reload_reg
)
7512 gen_reload (third_reload_reg
, real_oldequiv
,
7515 gen_reload (second_reload_reg
, third_reload_reg
,
7520 gen_reload (second_reload_reg
, real_oldequiv
,
7524 oldequiv
= second_reload_reg
;
7529 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7531 rtx real_oldequiv
= oldequiv
;
7533 if ((REG_P (oldequiv
)
7534 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7535 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7536 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7537 || (GET_CODE (oldequiv
) == SUBREG
7538 && REG_P (SUBREG_REG (oldequiv
))
7539 && (REGNO (SUBREG_REG (oldequiv
))
7540 >= FIRST_PSEUDO_REGISTER
)
7541 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7542 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7543 || (CONSTANT_P (oldequiv
)
7544 && (targetm
.preferred_reload_class (oldequiv
,
7545 REGNO_REG_CLASS (REGNO (reloadreg
)))
7547 real_oldequiv
= rl
->in
;
7548 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7552 if (cfun
->can_throw_non_call_exceptions
)
7553 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7555 /* End this sequence. */
7556 *where
= get_insns ();
7559 /* Update reload_override_in so that delete_address_reloads_1
7560 can see the actual register usage. */
7562 reload_override_in
[j
] = oldequiv
;
7565 /* Generate insns to for the output reload RL, which is for the insn described
7566 by CHAIN and has the number J. */
7568 emit_output_reload_insns (class insn_chain
*chain
, struct reload
*rl
,
7572 rtx_insn
*insn
= chain
->insn
;
7579 if (rl
->when_needed
== RELOAD_OTHER
)
7582 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7584 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7585 mode
= GET_MODE (rl_reg_rtx
);
7587 reloadreg
= rl_reg_rtx
;
7589 /* If we need two reload regs, set RELOADREG to the intermediate
7590 one, since it will be stored into OLD. We might need a secondary
7591 register only for an input reload, so check again here. */
7593 if (rl
->secondary_out_reload
>= 0)
7596 int secondary_reload
= rl
->secondary_out_reload
;
7597 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7599 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7600 && reg_equiv_mem (REGNO (old
)) != 0)
7601 real_old
= reg_equiv_mem (REGNO (old
));
7603 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7605 rtx second_reloadreg
= reloadreg
;
7606 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7608 /* See if RELOADREG is to be used as a scratch register
7609 or as an intermediate register. */
7610 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7612 /* We'd have to add extra code to handle this case. */
7613 gcc_assert (tertiary_reload
< 0);
7615 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7616 (real_old
, second_reloadreg
, reloadreg
)));
7621 /* See if we need both a scratch and intermediate reload
7624 enum insn_code tertiary_icode
7625 = rld
[secondary_reload
].secondary_out_icode
;
7627 /* We'd have to add more code for quartary reloads. */
7628 gcc_assert (tertiary_reload
< 0
7629 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7631 if (GET_MODE (reloadreg
) != mode
)
7632 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7634 if (tertiary_icode
!= CODE_FOR_nothing
)
7636 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7638 /* Copy primary reload reg to secondary reload reg.
7639 (Note that these have been swapped above, then
7640 secondary reload reg to OLD using our insn.) */
7642 /* If REAL_OLD is a paradoxical SUBREG, remove it
7643 and try to put the opposite SUBREG on
7645 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7647 gen_reload (reloadreg
, second_reloadreg
,
7648 rl
->opnum
, rl
->when_needed
);
7649 emit_insn ((GEN_FCN (tertiary_icode
)
7650 (real_old
, reloadreg
, third_reloadreg
)));
7656 /* Copy between the reload regs here and then to
7659 gen_reload (reloadreg
, second_reloadreg
,
7660 rl
->opnum
, rl
->when_needed
);
7661 if (tertiary_reload
>= 0)
7663 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7665 gen_reload (third_reloadreg
, reloadreg
,
7666 rl
->opnum
, rl
->when_needed
);
7667 reloadreg
= third_reloadreg
;
7674 /* Output the last reload insn. */
7679 /* Don't output the last reload if OLD is not the dest of
7680 INSN and is in the src and is clobbered by INSN. */
7681 if (! flag_expensive_optimizations
7683 || !(set
= single_set (insn
))
7684 || rtx_equal_p (old
, SET_DEST (set
))
7685 || !reg_mentioned_p (old
, SET_SRC (set
))
7686 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7687 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7688 gen_reload (old
, reloadreg
, rl
->opnum
,
7692 /* Look at all insns we emitted, just to be safe. */
7693 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7696 rtx pat
= PATTERN (p
);
7698 /* If this output reload doesn't come from a spill reg,
7699 clear any memory of reloaded copies of the pseudo reg.
7700 If this output reload comes from a spill reg,
7701 reg_has_output_reload will make this do nothing. */
7702 note_stores (p
, forget_old_reloads_1
, NULL
);
7704 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7706 rtx set
= single_set (insn
);
7707 if (reload_spill_index
[j
] < 0
7709 && SET_SRC (set
) == rl_reg_rtx
)
7711 int src
= REGNO (SET_SRC (set
));
7713 reload_spill_index
[j
] = src
;
7714 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7715 if (find_regno_note (insn
, REG_DEAD
, src
))
7716 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7718 if (HARD_REGISTER_P (rl_reg_rtx
))
7720 int s
= rl
->secondary_out_reload
;
7721 set
= single_set (p
);
7722 /* If this reload copies only to the secondary reload
7723 register, the secondary reload does the actual
7725 if (s
>= 0 && set
== NULL_RTX
)
7726 /* We can't tell what function the secondary reload
7727 has and where the actual store to the pseudo is
7728 made; leave new_spill_reg_store alone. */
7731 && SET_SRC (set
) == rl_reg_rtx
7732 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7734 /* Usually the next instruction will be the
7735 secondary reload insn; if we can confirm
7736 that it is, setting new_spill_reg_store to
7737 that insn will allow an extra optimization. */
7738 rtx s_reg
= rld
[s
].reg_rtx
;
7739 rtx_insn
*next
= NEXT_INSN (p
);
7740 rld
[s
].out
= rl
->out
;
7741 rld
[s
].out_reg
= rl
->out_reg
;
7742 set
= single_set (next
);
7743 if (set
&& SET_SRC (set
) == s_reg
7744 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7746 SET_HARD_REG_BIT (reg_is_output_reload
,
7748 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7751 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7752 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7757 if (rl
->when_needed
== RELOAD_OTHER
)
7759 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7760 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7763 output_reload_insns
[rl
->opnum
] = get_insns ();
7765 if (cfun
->can_throw_non_call_exceptions
)
7766 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7771 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7772 and has the number J. */
7774 do_input_reload (class insn_chain
*chain
, struct reload
*rl
, int j
)
7776 rtx_insn
*insn
= chain
->insn
;
7777 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7778 ? rl
->in_reg
: rl
->in
);
7779 rtx reg_rtx
= rl
->reg_rtx
;
7785 /* Determine the mode to reload in.
7786 This is very tricky because we have three to choose from.
7787 There is the mode the insn operand wants (rl->inmode).
7788 There is the mode of the reload register RELOADREG.
7789 There is the intrinsic mode of the operand, which we could find
7790 by stripping some SUBREGs.
7791 It turns out that RELOADREG's mode is irrelevant:
7792 we can change that arbitrarily.
7794 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7795 then the reload reg may not support QImode moves, so use SImode.
7796 If foo is in memory due to spilling a pseudo reg, this is safe,
7797 because the QImode value is in the least significant part of a
7798 slot big enough for a SImode. If foo is some other sort of
7799 memory reference, then it is impossible to reload this case,
7800 so previous passes had better make sure this never happens.
7802 Then consider a one-word union which has SImode and one of its
7803 members is a float, being fetched as (SUBREG:SF union:SI).
7804 We must fetch that as SFmode because we could be loading into
7805 a float-only register. In this case OLD's mode is correct.
7807 Consider an immediate integer: it has VOIDmode. Here we need
7808 to get a mode from something else.
7810 In some cases, there is a fourth mode, the operand's
7811 containing mode. If the insn specifies a containing mode for
7812 this operand, it overrides all others.
7814 I am not sure whether the algorithm here is always right,
7815 but it does the right things in those cases. */
7817 mode
= GET_MODE (old
);
7818 if (mode
== VOIDmode
)
7821 /* We cannot use gen_lowpart_common since it can do the wrong thing
7822 when REG_RTX has a multi-word mode. Note that REG_RTX must
7823 always be a REG here. */
7824 if (GET_MODE (reg_rtx
) != mode
)
7825 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7827 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7830 /* AUTO_INC reloads need to be handled even if inherited. We got an
7831 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7832 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7833 && ! rtx_equal_p (reg_rtx
, old
)
7835 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7837 /* When inheriting a wider reload, we have a MEM in rl->in,
7838 e.g. inheriting a SImode output reload for
7839 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7840 if (optimize
&& reload_inherited
[j
] && rl
->in
7842 && MEM_P (rl
->in_reg
)
7843 && reload_spill_index
[j
] >= 0
7844 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7845 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7847 /* If we are reloading a register that was recently stored in with an
7848 output-reload, see if we can prove there was
7849 actually no need to store the old value in it. */
7852 && (reload_inherited
[j
] || reload_override_in
[j
])
7855 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7857 /* There doesn't seem to be any reason to restrict this to pseudos
7858 and doing so loses in the case where we are copying from a
7859 register of the wrong class. */
7860 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
7862 /* The insn might have already some references to stackslots
7863 replaced by MEMs, while reload_out_reg still names the
7865 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
7866 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
7867 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
7870 /* Do output reloading for reload RL, which is for the insn described by
7871 CHAIN and has the number J.
7872 ??? At some point we need to support handling output reloads of
7873 JUMP_INSNs or insns that set cc0. */
7875 do_output_reload (class insn_chain
*chain
, struct reload
*rl
, int j
)
7878 rtx_insn
*insn
= chain
->insn
;
7879 /* If this is an output reload that stores something that is
7880 not loaded in this same reload, see if we can eliminate a previous
7882 rtx pseudo
= rl
->out_reg
;
7883 rtx reg_rtx
= rl
->reg_rtx
;
7885 if (rl
->out
&& reg_rtx
)
7889 /* Determine the mode to reload in.
7890 See comments above (for input reloading). */
7891 mode
= GET_MODE (rl
->out
);
7892 if (mode
== VOIDmode
)
7894 /* VOIDmode should never happen for an output. */
7895 if (asm_noperands (PATTERN (insn
)) < 0)
7896 /* It's the compiler's fault. */
7897 fatal_insn ("VOIDmode on an output", insn
);
7898 error_for_asm (insn
, "output operand is constant in %<asm%>");
7899 /* Prevent crash--use something we know is valid. */
7901 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
7903 if (GET_MODE (reg_rtx
) != mode
)
7904 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7906 reload_reg_rtx_for_output
[j
] = reg_rtx
;
7911 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
7912 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
7913 && reg_last_reload_reg
[REGNO (pseudo
)])
7915 int pseudo_no
= REGNO (pseudo
);
7916 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
7918 /* We don't need to test full validity of last_regno for
7919 inherit here; we only want to know if the store actually
7920 matches the pseudo. */
7921 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
7922 && reg_reloaded_contents
[last_regno
] == pseudo_no
7923 && spill_reg_store
[last_regno
]
7924 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
7925 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
7931 || rtx_equal_p (old
, reg_rtx
))
7934 /* An output operand that dies right away does need a reload,
7935 but need not be copied from it. Show the new location in the
7937 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
7938 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
7940 XEXP (note
, 0) = reg_rtx
;
7943 /* Likewise for a SUBREG of an operand that dies. */
7944 else if (GET_CODE (old
) == SUBREG
7945 && REG_P (SUBREG_REG (old
))
7946 && (note
= find_reg_note (insn
, REG_UNUSED
,
7947 SUBREG_REG (old
))) != 0)
7949 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
7952 else if (GET_CODE (old
) == SCRATCH
)
7953 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7954 but we don't want to make an output reload. */
7957 /* If is a JUMP_INSN, we can't support output reloads yet. */
7958 gcc_assert (NONJUMP_INSN_P (insn
));
7960 emit_output_reload_insns (chain
, rld
+ j
, j
);
7963 /* A reload copies values of MODE from register SRC to register DEST.
7964 Return true if it can be treated for inheritance purposes like a
7965 group of reloads, each one reloading a single hard register. The
7966 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7967 occupy the same number of hard registers. */
7970 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
7971 int src ATTRIBUTE_UNUSED
,
7972 machine_mode mode ATTRIBUTE_UNUSED
)
7974 return (REG_CAN_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
7975 && REG_CAN_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
7978 /* Output insns to reload values in and out of the chosen reload regs. */
7981 emit_reload_insns (class insn_chain
*chain
)
7983 rtx_insn
*insn
= chain
->insn
;
7987 CLEAR_HARD_REG_SET (reg_reloaded_died
);
7989 for (j
= 0; j
< reload_n_operands
; j
++)
7990 input_reload_insns
[j
] = input_address_reload_insns
[j
]
7991 = inpaddr_address_reload_insns
[j
]
7992 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
7993 = outaddr_address_reload_insns
[j
]
7994 = other_output_reload_insns
[j
] = 0;
7995 other_input_address_reload_insns
= 0;
7996 other_input_reload_insns
= 0;
7997 operand_reload_insns
= 0;
7998 other_operand_reload_insns
= 0;
8000 /* Dump reloads into the dump file. */
8003 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8004 debug_reload_to_stream (dump_file
);
8007 for (j
= 0; j
< n_reloads
; j
++)
8008 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8012 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8013 new_spill_reg_store
[i
] = 0;
8016 /* Now output the instructions to copy the data into and out of the
8017 reload registers. Do these in the order that the reloads were reported,
8018 since reloads of base and index registers precede reloads of operands
8019 and the operands may need the base and index registers reloaded. */
8021 for (j
= 0; j
< n_reloads
; j
++)
8023 do_input_reload (chain
, rld
+ j
, j
);
8024 do_output_reload (chain
, rld
+ j
, j
);
8027 /* Now write all the insns we made for reloads in the order expected by
8028 the allocation functions. Prior to the insn being reloaded, we write
8029 the following reloads:
8031 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8033 RELOAD_OTHER reloads.
8035 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8036 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8037 RELOAD_FOR_INPUT reload for the operand.
8039 RELOAD_FOR_OPADDR_ADDRS reloads.
8041 RELOAD_FOR_OPERAND_ADDRESS reloads.
8043 After the insn being reloaded, we write the following:
8045 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8046 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8047 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8048 reloads for the operand. The RELOAD_OTHER output reloads are
8049 output in descending order by reload number. */
8051 emit_insn_before (other_input_address_reload_insns
, insn
);
8052 emit_insn_before (other_input_reload_insns
, insn
);
8054 for (j
= 0; j
< reload_n_operands
; j
++)
8056 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8057 emit_insn_before (input_address_reload_insns
[j
], insn
);
8058 emit_insn_before (input_reload_insns
[j
], insn
);
8061 emit_insn_before (other_operand_reload_insns
, insn
);
8062 emit_insn_before (operand_reload_insns
, insn
);
8064 for (j
= 0; j
< reload_n_operands
; j
++)
8066 rtx_insn
*x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8067 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8068 x
= emit_insn_after (output_reload_insns
[j
], x
);
8069 emit_insn_after (other_output_reload_insns
[j
], x
);
8072 /* For all the spill regs newly reloaded in this instruction,
8073 record what they were reloaded from, so subsequent instructions
8074 can inherit the reloads.
8076 Update spill_reg_store for the reloads of this insn.
8077 Copy the elements that were updated in the loop above. */
8079 for (j
= 0; j
< n_reloads
; j
++)
8081 int r
= reload_order
[j
];
8082 int i
= reload_spill_index
[r
];
8084 /* If this is a non-inherited input reload from a pseudo, we must
8085 clear any memory of a previous store to the same pseudo. Only do
8086 something if there will not be an output reload for the pseudo
8088 if (rld
[r
].in_reg
!= 0
8089 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8091 rtx reg
= rld
[r
].in_reg
;
8093 if (GET_CODE (reg
) == SUBREG
)
8094 reg
= SUBREG_REG (reg
);
8097 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8098 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8100 int nregno
= REGNO (reg
);
8102 if (reg_last_reload_reg
[nregno
])
8104 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8106 if (reg_reloaded_contents
[last_regno
] == nregno
)
8107 spill_reg_store
[last_regno
] = 0;
8112 /* I is nonneg if this reload used a register.
8113 If rld[r].reg_rtx is 0, this is an optional reload
8114 that we opted to ignore. */
8116 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8118 int nr
= hard_regno_nregs (i
, GET_MODE (rld
[r
].reg_rtx
));
8121 /* For a multi register reload, we need to check if all or part
8122 of the value lives to the end. */
8123 for (k
= 0; k
< nr
; k
++)
8124 if (reload_reg_reaches_end_p (i
+ k
, r
))
8125 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8127 /* Maybe the spill reg contains a copy of reload_out. */
8129 && (REG_P (rld
[r
].out
)
8131 ? REG_P (rld
[r
].out_reg
)
8132 /* The reload value is an auto-modification of
8133 some kind. For PRE_INC, POST_INC, PRE_DEC
8134 and POST_DEC, we record an equivalence
8135 between the reload register and the operand
8136 on the optimistic assumption that we can make
8137 the equivalence hold. reload_as_needed must
8138 then either make it hold or invalidate the
8141 PRE_MODIFY and POST_MODIFY addresses are reloaded
8142 somewhat differently, and allowing them here leads
8144 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8145 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8149 reg
= reload_reg_rtx_for_output
[r
];
8150 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8152 machine_mode mode
= GET_MODE (reg
);
8153 int regno
= REGNO (reg
);
8154 int nregs
= REG_NREGS (reg
);
8155 rtx out
= (REG_P (rld
[r
].out
)
8159 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8160 int out_regno
= REGNO (out
);
8161 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8162 : hard_regno_nregs (out_regno
, mode
));
8165 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8166 spill_reg_stored_to
[regno
] = out
;
8167 reg_last_reload_reg
[out_regno
] = reg
;
8169 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8170 && nregs
== out_nregs
8171 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8173 /* If OUT_REGNO is a hard register, it may occupy more than
8174 one register. If it does, say what is in the
8175 rest of the registers assuming that both registers
8176 agree on how many words the object takes. If not,
8177 invalidate the subsequent registers. */
8179 if (HARD_REGISTER_NUM_P (out_regno
))
8180 for (k
= 1; k
< out_nregs
; k
++)
8181 reg_last_reload_reg
[out_regno
+ k
]
8182 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8184 /* Now do the inverse operation. */
8185 for (k
= 0; k
< nregs
; k
++)
8187 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8188 reg_reloaded_contents
[regno
+ k
]
8189 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8192 reg_reloaded_insn
[regno
+ k
] = insn
;
8193 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8194 if (targetm
.hard_regno_call_part_clobbered (NULL
,
8197 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8200 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8205 /* Maybe the spill reg contains a copy of reload_in. Only do
8206 something if there will not be an output reload for
8207 the register being reloaded. */
8208 else if (rld
[r
].out_reg
== 0
8210 && ((REG_P (rld
[r
].in
)
8211 && !HARD_REGISTER_P (rld
[r
].in
)
8212 && !REGNO_REG_SET_P (®_has_output_reload
,
8214 || (REG_P (rld
[r
].in_reg
)
8215 && !REGNO_REG_SET_P (®_has_output_reload
,
8216 REGNO (rld
[r
].in_reg
))))
8217 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8221 reg
= reload_reg_rtx_for_input
[r
];
8222 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8232 mode
= GET_MODE (reg
);
8233 regno
= REGNO (reg
);
8234 nregs
= REG_NREGS (reg
);
8235 if (REG_P (rld
[r
].in
)
8236 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8238 else if (REG_P (rld
[r
].in_reg
))
8241 in
= XEXP (rld
[r
].in_reg
, 0);
8242 in_regno
= REGNO (in
);
8244 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8245 : hard_regno_nregs (in_regno
, mode
));
8247 reg_last_reload_reg
[in_regno
] = reg
;
8249 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8250 && nregs
== in_nregs
8251 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8253 if (HARD_REGISTER_NUM_P (in_regno
))
8254 for (k
= 1; k
< in_nregs
; k
++)
8255 reg_last_reload_reg
[in_regno
+ k
]
8256 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8258 /* Unless we inherited this reload, show we haven't
8259 recently done a store.
8260 Previous stores of inherited auto_inc expressions
8261 also have to be discarded. */
8262 if (! reload_inherited
[r
]
8263 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8264 spill_reg_store
[regno
] = 0;
8266 for (k
= 0; k
< nregs
; k
++)
8268 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8269 reg_reloaded_contents
[regno
+ k
]
8270 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8273 reg_reloaded_insn
[regno
+ k
] = insn
;
8274 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8275 if (targetm
.hard_regno_call_part_clobbered (NULL
,
8278 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8281 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8288 /* The following if-statement was #if 0'd in 1.34 (or before...).
8289 It's reenabled in 1.35 because supposedly nothing else
8290 deals with this problem. */
8292 /* If a register gets output-reloaded from a non-spill register,
8293 that invalidates any previous reloaded copy of it.
8294 But forget_old_reloads_1 won't get to see it, because
8295 it thinks only about the original insn. So invalidate it here.
8296 Also do the same thing for RELOAD_OTHER constraints where the
8297 output is discarded. */
8299 && ((rld
[r
].out
!= 0
8300 && (REG_P (rld
[r
].out
)
8301 || (MEM_P (rld
[r
].out
)
8302 && REG_P (rld
[r
].out_reg
))))
8303 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8304 && REG_P (rld
[r
].out_reg
))))
8306 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8307 ? rld
[r
].out
: rld
[r
].out_reg
);
8308 int out_regno
= REGNO (out
);
8309 machine_mode mode
= GET_MODE (out
);
8311 /* REG_RTX is now set or clobbered by the main instruction.
8312 As the comment above explains, forget_old_reloads_1 only
8313 sees the original instruction, and there is no guarantee
8314 that the original instruction also clobbered REG_RTX.
8315 For example, if find_reloads sees that the input side of
8316 a matched operand pair dies in this instruction, it may
8317 use the input register as the reload register.
8319 Calling forget_old_reloads_1 is a waste of effort if
8320 REG_RTX is also the output register.
8322 If we know that REG_RTX holds the value of a pseudo
8323 register, the code after the call will record that fact. */
8324 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8325 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8327 if (!HARD_REGISTER_NUM_P (out_regno
))
8330 rtx_insn
*store_insn
= NULL
;
8332 reg_last_reload_reg
[out_regno
] = 0;
8334 /* If we can find a hard register that is stored, record
8335 the storing insn so that we may delete this insn with
8336 delete_output_reload. */
8337 src_reg
= reload_reg_rtx_for_output
[r
];
8341 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8342 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8348 /* If this is an optional reload, try to find the
8349 source reg from an input reload. */
8350 rtx set
= single_set (insn
);
8351 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8355 src_reg
= SET_SRC (set
);
8357 for (k
= 0; k
< n_reloads
; k
++)
8359 if (rld
[k
].in
== src_reg
)
8361 src_reg
= reload_reg_rtx_for_input
[k
];
8367 if (src_reg
&& REG_P (src_reg
)
8368 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8370 int src_regno
, src_nregs
, k
;
8373 gcc_assert (GET_MODE (src_reg
) == mode
);
8374 src_regno
= REGNO (src_reg
);
8375 src_nregs
= hard_regno_nregs (src_regno
, mode
);
8376 /* The place where to find a death note varies with
8377 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8378 necessarily checked exactly in the code that moves
8379 notes, so just check both locations. */
8380 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8381 if (! note
&& store_insn
)
8382 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8383 for (k
= 0; k
< src_nregs
; k
++)
8385 spill_reg_store
[src_regno
+ k
] = store_insn
;
8386 spill_reg_stored_to
[src_regno
+ k
] = out
;
8387 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8388 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8389 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8390 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8391 if (targetm
.hard_regno_call_part_clobbered
8392 (NULL
, src_regno
+ k
, mode
))
8393 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8396 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8398 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8400 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8402 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8404 reg_last_reload_reg
[out_regno
] = src_reg
;
8405 /* We have to set reg_has_output_reload here, or else
8406 forget_old_reloads_1 will clear reg_last_reload_reg
8408 SET_REGNO_REG_SET (®_has_output_reload
,
8414 int k
, out_nregs
= hard_regno_nregs (out_regno
, mode
);
8416 for (k
= 0; k
< out_nregs
; k
++)
8417 reg_last_reload_reg
[out_regno
+ k
] = 0;
8421 reg_reloaded_dead
|= reg_reloaded_died
;
8424 /* Go through the motions to emit INSN and test if it is strictly valid.
8425 Return the emitted insn if valid, else return NULL. */
8428 emit_insn_if_valid_for_reload (rtx pat
)
8430 rtx_insn
*last
= get_last_insn ();
8433 rtx_insn
*insn
= emit_insn (pat
);
8434 code
= recog_memoized (insn
);
8438 extract_insn (insn
);
8439 /* We want constrain operands to treat this insn strictly in its
8440 validity determination, i.e., the way it would after reload has
8442 if (constrain_operands (1, get_enabled_alternatives (insn
)))
8446 delete_insns_since (last
);
8450 /* Emit code to perform a reload from IN (which may be a reload register) to
8451 OUT (which may also be a reload register). IN or OUT is from operand
8452 OPNUM with reload type TYPE.
8454 Returns first insn emitted. */
8457 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8459 rtx_insn
*last
= get_last_insn ();
8463 /* If IN is a paradoxical SUBREG, remove it and try to put the
8464 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8465 if (!strip_paradoxical_subreg (&in
, &out
))
8466 strip_paradoxical_subreg (&out
, &in
);
8468 /* How to do this reload can get quite tricky. Normally, we are being
8469 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8470 register that didn't get a hard register. In that case we can just
8471 call emit_move_insn.
8473 We can also be asked to reload a PLUS that adds a register or a MEM to
8474 another register, constant or MEM. This can occur during frame pointer
8475 elimination and while reloading addresses. This case is handled by
8476 trying to emit a single insn to perform the add. If it is not valid,
8477 we use a two insn sequence.
8479 Or we can be asked to reload an unary operand that was a fragment of
8480 an addressing mode, into a register. If it isn't recognized as-is,
8481 we try making the unop operand and the reload-register the same:
8482 (set reg:X (unop:X expr:Y))
8483 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8485 Finally, we could be called to handle an 'o' constraint by putting
8486 an address into a register. In that case, we first try to do this
8487 with a named pattern of "reload_load_address". If no such pattern
8488 exists, we just emit a SET insn and hope for the best (it will normally
8489 be valid on machines that use 'o').
8491 This entire process is made complex because reload will never
8492 process the insns we generate here and so we must ensure that
8493 they will fit their constraints and also by the fact that parts of
8494 IN might be being reloaded separately and replaced with spill registers.
8495 Because of this, we are, in some sense, just guessing the right approach
8496 here. The one listed above seems to work.
8498 ??? At some point, this whole thing needs to be rethought. */
8500 if (GET_CODE (in
) == PLUS
8501 && (REG_P (XEXP (in
, 0))
8502 || GET_CODE (XEXP (in
, 0)) == SUBREG
8503 || MEM_P (XEXP (in
, 0)))
8504 && (REG_P (XEXP (in
, 1))
8505 || GET_CODE (XEXP (in
, 1)) == SUBREG
8506 || CONSTANT_P (XEXP (in
, 1))
8507 || MEM_P (XEXP (in
, 1))))
8509 /* We need to compute the sum of a register or a MEM and another
8510 register, constant, or MEM, and put it into the reload
8511 register. The best possible way of doing this is if the machine
8512 has a three-operand ADD insn that accepts the required operands.
8514 The simplest approach is to try to generate such an insn and see if it
8515 is recognized and matches its constraints. If so, it can be used.
8517 It might be better not to actually emit the insn unless it is valid,
8518 but we need to pass the insn as an operand to `recog' and
8519 `extract_insn' and it is simpler to emit and then delete the insn if
8520 not valid than to dummy things up. */
8524 enum insn_code code
;
8526 op0
= find_replacement (&XEXP (in
, 0));
8527 op1
= find_replacement (&XEXP (in
, 1));
8529 /* Since constraint checking is strict, commutativity won't be
8530 checked, so we need to do that here to avoid spurious failure
8531 if the add instruction is two-address and the second operand
8532 of the add is the same as the reload reg, which is frequently
8533 the case. If the insn would be A = B + A, rearrange it so
8534 it will be A = A + B as constrain_operands expects. */
8536 if (REG_P (XEXP (in
, 1))
8537 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8538 tem
= op0
, op0
= op1
, op1
= tem
;
8540 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8541 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8543 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8547 /* If that failed, we must use a conservative two-insn sequence.
8549 Use a move to copy one operand into the reload register. Prefer
8550 to reload a constant, MEM or pseudo since the move patterns can
8551 handle an arbitrary operand. If OP1 is not a constant, MEM or
8552 pseudo and OP1 is not a valid operand for an add instruction, then
8555 After reloading one of the operands into the reload register, add
8556 the reload register to the output register.
8558 If there is another way to do this for a specific machine, a
8559 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8562 code
= optab_handler (add_optab
, GET_MODE (out
));
8564 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8566 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8567 || (code
!= CODE_FOR_nothing
8568 && !insn_operand_matches (code
, 2, op1
)))
8569 tem
= op0
, op0
= op1
, op1
= tem
;
8571 gen_reload (out
, op0
, opnum
, type
);
8573 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8574 This fixes a problem on the 32K where the stack pointer cannot
8575 be used as an operand of an add insn. */
8577 if (rtx_equal_p (op0
, op1
))
8580 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8583 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8584 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8588 /* If that failed, copy the address register to the reload register.
8589 Then add the constant to the reload register. */
8591 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8592 gen_reload (out
, op1
, opnum
, type
);
8593 insn
= emit_insn (gen_add2_insn (out
, op0
));
8594 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8597 /* If we need a memory location to do the move, do it that way. */
8598 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8599 (REG_P (tem1
) && REG_P (tem2
)))
8600 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8601 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8602 && targetm
.secondary_memory_needed (GET_MODE (out
),
8603 REGNO_REG_CLASS (REGNO (tem1
)),
8604 REGNO_REG_CLASS (REGNO (tem2
))))
8606 /* Get the memory to use and rewrite both registers to its mode. */
8607 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8609 if (GET_MODE (loc
) != GET_MODE (out
))
8610 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8612 if (GET_MODE (loc
) != GET_MODE (in
))
8613 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8615 gen_reload (loc
, in
, opnum
, type
);
8616 gen_reload (out
, loc
, opnum
, type
);
8618 else if (REG_P (out
) && UNARY_P (in
))
8624 op1
= find_replacement (&XEXP (in
, 0));
8625 if (op1
!= XEXP (in
, 0))
8626 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8628 /* First, try a plain SET. */
8629 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8633 /* If that failed, move the inner operand to the reload
8634 register, and try the same unop with the inner expression
8635 replaced with the reload register. */
8637 if (GET_MODE (op1
) != GET_MODE (out
))
8638 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8642 gen_reload (out_moded
, op1
, opnum
, type
);
8644 rtx temp
= gen_rtx_SET (out
, gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8646 rtx_insn
*insn
= emit_insn_if_valid_for_reload (temp
);
8649 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8653 fatal_insn ("failure trying to reload:", set
);
8655 /* If IN is a simple operand, use gen_move_insn. */
8656 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8658 tem
= emit_insn (gen_move_insn (out
, in
));
8659 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8660 mark_jump_label (in
, tem
, 0);
8663 else if (targetm
.have_reload_load_address ())
8664 emit_insn (targetm
.gen_reload_load_address (out
, in
));
8666 /* Otherwise, just write (set OUT IN) and hope for the best. */
8668 emit_insn (gen_rtx_SET (out
, in
));
8670 /* Return the first insn emitted.
8671 We cannot just return get_last_insn, because there may have
8672 been multiple instructions emitted. Also note that gen_move_insn may
8673 emit more than one insn itself, so we cannot assume that there is one
8674 insn emitted per emit_insn_before call. */
8676 return last
? NEXT_INSN (last
) : get_insns ();
8679 /* Delete a previously made output-reload whose result we now believe
8680 is not needed. First we double-check.
8682 INSN is the insn now being processed.
8683 LAST_RELOAD_REG is the hard register number for which we want to delete
8684 the last output reload.
8685 J is the reload-number that originally used REG. The caller has made
8686 certain that reload J doesn't use REG any longer for input.
8687 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8690 delete_output_reload (rtx_insn
*insn
, int j
, int last_reload_reg
,
8693 rtx_insn
*output_reload_insn
= spill_reg_store
[last_reload_reg
];
8694 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8697 int n_inherited
= 0;
8702 /* It is possible that this reload has been only used to set another reload
8703 we eliminated earlier and thus deleted this instruction too. */
8704 if (output_reload_insn
->deleted ())
8707 /* Get the raw pseudo-register referred to. */
8709 while (GET_CODE (reg
) == SUBREG
)
8710 reg
= SUBREG_REG (reg
);
8711 substed
= reg_equiv_memory_loc (REGNO (reg
));
8713 /* This is unsafe if the operand occurs more often in the current
8714 insn than it is inherited. */
8715 for (k
= n_reloads
- 1; k
>= 0; k
--)
8717 rtx reg2
= rld
[k
].in
;
8720 if (MEM_P (reg2
) || reload_override_in
[k
])
8721 reg2
= rld
[k
].in_reg
;
8723 if (AUTO_INC_DEC
&& rld
[k
].out
&& ! rld
[k
].out_reg
)
8724 reg2
= XEXP (rld
[k
].in_reg
, 0);
8726 while (GET_CODE (reg2
) == SUBREG
)
8727 reg2
= SUBREG_REG (reg2
);
8728 if (rtx_equal_p (reg2
, reg
))
8730 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8736 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8737 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8738 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8741 n_occurrences
+= count_occurrences (PATTERN (insn
),
8742 eliminate_regs (substed
, VOIDmode
,
8744 for (rtx i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8746 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8747 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8749 if (n_occurrences
> n_inherited
)
8752 regno
= REGNO (reg
);
8753 nregs
= REG_NREGS (reg
);
8755 /* If the pseudo-reg we are reloading is no longer referenced
8756 anywhere between the store into it and here,
8757 and we're within the same basic block, then the value can only
8758 pass through the reload reg and end up here.
8759 Otherwise, give up--return. */
8760 for (rtx_insn
*i1
= NEXT_INSN (output_reload_insn
);
8761 i1
!= insn
; i1
= NEXT_INSN (i1
))
8763 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8765 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8766 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8768 /* If this is USE in front of INSN, we only have to check that
8769 there are no more references than accounted for by inheritance. */
8770 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8772 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8773 i1
= NEXT_INSN (i1
);
8775 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8781 /* We will be deleting the insn. Remove the spill reg information. */
8782 for (k
= hard_regno_nregs (last_reload_reg
, GET_MODE (reg
)); k
-- > 0; )
8784 spill_reg_store
[last_reload_reg
+ k
] = 0;
8785 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8788 /* The caller has already checked that REG dies or is set in INSN.
8789 It has also checked that we are optimizing, and thus some
8790 inaccuracies in the debugging information are acceptable.
8791 So we could just delete output_reload_insn. But in some cases
8792 we can improve the debugging information without sacrificing
8793 optimization - maybe even improving the code: See if the pseudo
8794 reg has been completely replaced with reload regs. If so, delete
8795 the store insn and forget we had a stack slot for the pseudo. */
8796 if (rld
[j
].out
!= rld
[j
].in
8797 && REG_N_DEATHS (REGNO (reg
)) == 1
8798 && REG_N_SETS (REGNO (reg
)) == 1
8799 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8800 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8804 /* We know that it was used only between here and the beginning of
8805 the current basic block. (We also know that the last use before
8806 INSN was the output reload we are thinking of deleting, but never
8807 mind that.) Search that range; see if any ref remains. */
8808 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8810 rtx set
= single_set (i2
);
8812 /* Uses which just store in the pseudo don't count,
8813 since if they are the only uses, they are dead. */
8814 if (set
!= 0 && SET_DEST (set
) == reg
)
8816 if (LABEL_P (i2
) || JUMP_P (i2
))
8818 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8819 && reg_mentioned_p (reg
, PATTERN (i2
)))
8821 /* Some other ref remains; just delete the output reload we
8823 delete_address_reloads (output_reload_insn
, insn
);
8824 delete_insn (output_reload_insn
);
8829 /* Delete the now-dead stores into this pseudo. Note that this
8830 loop also takes care of deleting output_reload_insn. */
8831 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8833 rtx set
= single_set (i2
);
8835 if (set
!= 0 && SET_DEST (set
) == reg
)
8837 delete_address_reloads (i2
, insn
);
8840 if (LABEL_P (i2
) || JUMP_P (i2
))
8844 /* For the debugging info, say the pseudo lives in this reload reg. */
8845 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8846 if (ira_conflicts_p
)
8847 /* Inform IRA about the change. */
8848 ira_mark_allocation_change (REGNO (reg
));
8849 alter_reg (REGNO (reg
), -1, false);
8853 delete_address_reloads (output_reload_insn
, insn
);
8854 delete_insn (output_reload_insn
);
8858 /* We are going to delete DEAD_INSN. Recursively delete loads of
8859 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8860 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8862 delete_address_reloads (rtx_insn
*dead_insn
, rtx_insn
*current_insn
)
8864 rtx set
= single_set (dead_insn
);
8866 rtx_insn
*prev
, *next
;
8869 rtx dst
= SET_DEST (set
);
8871 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
8873 /* If we deleted the store from a reloaded post_{in,de}c expression,
8874 we can delete the matching adds. */
8875 prev
= PREV_INSN (dead_insn
);
8876 next
= NEXT_INSN (dead_insn
);
8877 if (! prev
|| ! next
)
8879 set
= single_set (next
);
8880 set2
= single_set (prev
);
8882 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
8883 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
8884 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
8886 dst
= SET_DEST (set
);
8887 if (! rtx_equal_p (dst
, SET_DEST (set2
))
8888 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
8889 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
8890 || (INTVAL (XEXP (SET_SRC (set
), 1))
8891 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
8893 delete_related_insns (prev
);
8894 delete_related_insns (next
);
8897 /* Subfunction of delete_address_reloads: process registers found in X. */
8899 delete_address_reloads_1 (rtx_insn
*dead_insn
, rtx x
, rtx_insn
*current_insn
)
8901 rtx_insn
*prev
, *i2
;
8904 enum rtx_code code
= GET_CODE (x
);
8908 const char *fmt
= GET_RTX_FORMAT (code
);
8909 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8912 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
8913 else if (fmt
[i
] == 'E')
8915 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
8916 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
8923 if (spill_reg_order
[REGNO (x
)] < 0)
8926 /* Scan backwards for the insn that sets x. This might be a way back due
8928 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
8930 code
= GET_CODE (prev
);
8931 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
8935 if (reg_set_p (x
, PATTERN (prev
)))
8937 if (reg_referenced_p (x
, PATTERN (prev
)))
8940 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
8942 /* Check that PREV only sets the reload register. */
8943 set
= single_set (prev
);
8946 dst
= SET_DEST (set
);
8948 || ! rtx_equal_p (dst
, x
))
8950 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
8952 /* Check if DST was used in a later insn -
8953 it might have been inherited. */
8954 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
8960 if (reg_referenced_p (dst
, PATTERN (i2
)))
8962 /* If there is a reference to the register in the current insn,
8963 it might be loaded in a non-inherited reload. If no other
8964 reload uses it, that means the register is set before
8966 if (i2
== current_insn
)
8968 for (j
= n_reloads
- 1; j
>= 0; j
--)
8969 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8970 || reload_override_in
[j
] == dst
)
8972 for (j
= n_reloads
- 1; j
>= 0; j
--)
8973 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
8982 /* If DST is still live at CURRENT_INSN, check if it is used for
8983 any reload. Note that even if CURRENT_INSN sets DST, we still
8984 have to check the reloads. */
8985 if (i2
== current_insn
)
8987 for (j
= n_reloads
- 1; j
>= 0; j
--)
8988 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
8989 || reload_override_in
[j
] == dst
)
8991 /* ??? We can't finish the loop here, because dst might be
8992 allocated to a pseudo in this block if no reload in this
8993 block needs any of the classes containing DST - see
8994 spill_hard_reg. There is no easy way to tell this, so we
8995 have to scan till the end of the basic block. */
8997 if (reg_set_p (dst
, PATTERN (i2
)))
9001 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9002 reg_reloaded_contents
[REGNO (dst
)] = -1;
9006 /* Output reload-insns to reload VALUE into RELOADREG.
9007 VALUE is an autoincrement or autodecrement RTX whose operand
9008 is a register or memory location;
9009 so reloading involves incrementing that location.
9010 IN is either identical to VALUE, or some cheaper place to reload from.
9012 INC_AMOUNT is the number to increment or decrement by (always positive).
9013 This cannot be deduced from VALUE. */
9016 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, poly_int64 inc_amount
)
9018 /* REG or MEM to be copied and incremented. */
9019 rtx incloc
= find_replacement (&XEXP (value
, 0));
9020 /* Nonzero if increment after copying. */
9021 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9022 || GET_CODE (value
) == POST_MODIFY
);
9027 rtx real_in
= in
== value
? incloc
: in
;
9029 /* No hard register is equivalent to this register after
9030 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9031 we could inc/dec that register as well (maybe even using it for
9032 the source), but I'm not sure it's worth worrying about. */
9034 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9036 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9038 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9039 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9043 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9044 inc_amount
= -inc_amount
;
9046 inc
= gen_int_mode (inc_amount
, Pmode
);
9049 /* If this is post-increment, first copy the location to the reload reg. */
9050 if (post
&& real_in
!= reloadreg
)
9051 emit_insn (gen_move_insn (reloadreg
, real_in
));
9055 /* See if we can directly increment INCLOC. Use a method similar to
9056 that in gen_reload. */
9058 last
= get_last_insn ();
9059 add_insn
= emit_insn (gen_rtx_SET (incloc
,
9060 gen_rtx_PLUS (GET_MODE (incloc
),
9063 code
= recog_memoized (add_insn
);
9066 extract_insn (add_insn
);
9067 if (constrain_operands (1, get_enabled_alternatives (add_insn
)))
9069 /* If this is a pre-increment and we have incremented the value
9070 where it lives, copy the incremented value to RELOADREG to
9071 be used as an address. */
9074 emit_insn (gen_move_insn (reloadreg
, incloc
));
9078 delete_insns_since (last
);
9081 /* If couldn't do the increment directly, must increment in RELOADREG.
9082 The way we do this depends on whether this is pre- or post-increment.
9083 For pre-increment, copy INCLOC to the reload register, increment it
9084 there, then save back. */
9088 if (in
!= reloadreg
)
9089 emit_insn (gen_move_insn (reloadreg
, real_in
));
9090 emit_insn (gen_add2_insn (reloadreg
, inc
));
9091 emit_insn (gen_move_insn (incloc
, reloadreg
));
9096 Because this might be a jump insn or a compare, and because RELOADREG
9097 may not be available after the insn in an input reload, we must do
9098 the incrementation before the insn being reloaded for.
9100 We have already copied IN to RELOADREG. Increment the copy in
9101 RELOADREG, save that back, then decrement RELOADREG so it has
9102 the original value. */
9104 emit_insn (gen_add2_insn (reloadreg
, inc
));
9105 emit_insn (gen_move_insn (incloc
, reloadreg
));
9106 if (CONST_INT_P (inc
))
9107 emit_insn (gen_add2_insn (reloadreg
,
9108 gen_int_mode (-INTVAL (inc
),
9109 GET_MODE (reloadreg
))));
9111 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9116 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
9118 enum rtx_code code
= GET_CODE (x
);
9122 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9124 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9128 /* Scan all the operand sub-expressions. */
9129 fmt
= GET_RTX_FORMAT (code
);
9130 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9133 add_auto_inc_notes (insn
, XEXP (x
, i
));
9134 else if (fmt
[i
] == 'E')
9135 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9136 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));