1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
28 #include "rtl-error.h"
31 #include "insn-config.h"
42 #include "insn-codes.h"
45 #include "addresses.h"
56 /* This file contains the reload pass of the compiler, which is
57 run after register allocation has been done. It checks that
58 each insn is valid (operands required to be in registers really
59 are in registers of the proper class) and fixes up invalid ones
60 by copying values temporarily into registers for the insns
63 The results of register allocation are described by the vector
64 reg_renumber; the insns still contain pseudo regs, but reg_renumber
65 can be used to find which hard reg, if any, a pseudo reg is in.
67 The technique we always use is to free up a few hard regs that are
68 called ``reload regs'', and for each place where a pseudo reg
69 must be in a hard reg, copy it temporarily into one of the reload regs.
71 Reload regs are allocated locally for every instruction that needs
72 reloads. When there are pseudos which are allocated to a register that
73 has been chosen as a reload reg, such pseudos must be ``spilled''.
74 This means that they go to other hard regs, or to stack slots if no other
75 available hard regs can be found. Spilling can invalidate more
76 insns, requiring additional need for reloads, so we must keep checking
77 until the process stabilizes.
79 For machines with different classes of registers, we must keep track
80 of the register class needed for each reload, and make sure that
81 we allocate enough reload registers of each class.
83 The file reload.c contains the code that checks one insn for
84 validity and reports the reloads that it needs. This file
85 is in charge of scanning the entire rtl code, accumulating the
86 reload needs, spilling, assigning reload registers to use for
87 fixing up each insn, and generating the new insns to copy values
88 into the reload registers. */
90 struct target_reload default_target_reload
;
92 struct target_reload
*this_target_reload
= &default_target_reload
;
95 #define spill_indirect_levels \
96 (this_target_reload->x_spill_indirect_levels)
98 /* During reload_as_needed, element N contains a REG rtx for the hard reg
99 into which reg N has been reloaded (perhaps for a previous insn). */
100 static rtx
*reg_last_reload_reg
;
102 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
103 for an output reload that stores into reg N. */
104 static regset_head reg_has_output_reload
;
106 /* Indicates which hard regs are reload-registers for an output reload
107 in the current insn. */
108 static HARD_REG_SET reg_is_output_reload
;
110 /* Widest width in which each pseudo reg is referred to (via subreg). */
111 static unsigned int *reg_max_ref_width
;
113 /* Vector to remember old contents of reg_renumber before spilling. */
114 static short *reg_old_renumber
;
116 /* During reload_as_needed, element N contains the last pseudo regno reloaded
117 into hard register N. If that pseudo reg occupied more than one register,
118 reg_reloaded_contents points to that pseudo for each spill register in
119 use; all of these must remain set for an inheritance to occur. */
120 static int reg_reloaded_contents
[FIRST_PSEUDO_REGISTER
];
122 /* During reload_as_needed, element N contains the insn for which
123 hard register N was last used. Its contents are significant only
124 when reg_reloaded_valid is set for this register. */
125 static rtx_insn
*reg_reloaded_insn
[FIRST_PSEUDO_REGISTER
];
127 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
128 static HARD_REG_SET reg_reloaded_valid
;
129 /* Indicate if the register was dead at the end of the reload.
130 This is only valid if reg_reloaded_contents is set and valid. */
131 static HARD_REG_SET reg_reloaded_dead
;
133 /* Indicate whether the register's current value is one that is not
134 safe to retain across a call, even for registers that are normally
135 call-saved. This is only meaningful for members of reg_reloaded_valid. */
136 static HARD_REG_SET reg_reloaded_call_part_clobbered
;
138 /* Number of spill-regs so far; number of valid elements of spill_regs. */
141 /* In parallel with spill_regs, contains REG rtx's for those regs.
142 Holds the last rtx used for any given reg, or 0 if it has never
143 been used for spilling yet. This rtx is reused, provided it has
145 static rtx spill_reg_rtx
[FIRST_PSEUDO_REGISTER
];
147 /* In parallel with spill_regs, contains nonzero for a spill reg
148 that was stored after the last time it was used.
149 The precise value is the insn generated to do the store. */
150 static rtx_insn
*spill_reg_store
[FIRST_PSEUDO_REGISTER
];
152 /* This is the register that was stored with spill_reg_store. This is a
153 copy of reload_out / reload_out_reg when the value was stored; if
154 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
155 static rtx spill_reg_stored_to
[FIRST_PSEUDO_REGISTER
];
157 /* This table is the inverse mapping of spill_regs:
158 indexed by hard reg number,
159 it contains the position of that reg in spill_regs,
160 or -1 for something that is not in spill_regs.
162 ?!? This is no longer accurate. */
163 static short spill_reg_order
[FIRST_PSEUDO_REGISTER
];
165 /* This reg set indicates registers that can't be used as spill registers for
166 the currently processed insn. These are the hard registers which are live
167 during the insn, but not allocated to pseudos, as well as fixed
169 static HARD_REG_SET bad_spill_regs
;
171 /* These are the hard registers that can't be used as spill register for any
172 insn. This includes registers used for user variables and registers that
173 we can't eliminate. A register that appears in this set also can't be used
174 to retry register allocation. */
175 static HARD_REG_SET bad_spill_regs_global
;
177 /* Describes order of use of registers for reloading
178 of spilled pseudo-registers. `n_spills' is the number of
179 elements that are actually valid; new ones are added at the end.
181 Both spill_regs and spill_reg_order are used on two occasions:
182 once during find_reload_regs, where they keep track of the spill registers
183 for a single insn, but also during reload_as_needed where they show all
184 the registers ever used by reload. For the latter case, the information
185 is calculated during finish_spills. */
186 static short spill_regs
[FIRST_PSEUDO_REGISTER
];
188 /* This vector of reg sets indicates, for each pseudo, which hard registers
189 may not be used for retrying global allocation because the register was
190 formerly spilled from one of them. If we allowed reallocating a pseudo to
191 a register that it was already allocated to, reload might not
193 static HARD_REG_SET
*pseudo_previous_regs
;
195 /* This vector of reg sets indicates, for each pseudo, which hard
196 registers may not be used for retrying global allocation because they
197 are used as spill registers during one of the insns in which the
199 static HARD_REG_SET
*pseudo_forbidden_regs
;
201 /* All hard regs that have been used as spill registers for any insn are
202 marked in this set. */
203 static HARD_REG_SET used_spill_regs
;
205 /* Index of last register assigned as a spill register. We allocate in
206 a round-robin fashion. */
207 static int last_spill_reg
;
209 /* Record the stack slot for each spilled hard register. */
210 static rtx spill_stack_slot
[FIRST_PSEUDO_REGISTER
];
212 /* Width allocated so far for that stack slot. */
213 static unsigned int spill_stack_slot_width
[FIRST_PSEUDO_REGISTER
];
215 /* Record which pseudos needed to be spilled. */
216 static regset_head spilled_pseudos
;
218 /* Record which pseudos changed their allocation in finish_spills. */
219 static regset_head changed_allocation_pseudos
;
221 /* Used for communication between order_regs_for_reload and count_pseudo.
222 Used to avoid counting one pseudo twice. */
223 static regset_head pseudos_counted
;
225 /* First uid used by insns created by reload in this function.
226 Used in find_equiv_reg. */
227 int reload_first_uid
;
229 /* Flag set by local-alloc or global-alloc if anything is live in
230 a call-clobbered reg across calls. */
231 int caller_save_needed
;
233 /* Set to 1 while reload_as_needed is operating.
234 Required by some machines to handle any generated moves differently. */
235 int reload_in_progress
= 0;
237 /* This obstack is used for allocation of rtl during register elimination.
238 The allocated storage can be freed once find_reloads has processed the
240 static struct obstack reload_obstack
;
242 /* Points to the beginning of the reload_obstack. All insn_chain structures
243 are allocated first. */
244 static char *reload_startobj
;
246 /* The point after all insn_chain structures. Used to quickly deallocate
247 memory allocated in copy_reloads during calculate_needs_all_insns. */
248 static char *reload_firstobj
;
250 /* This points before all local rtl generated by register elimination.
251 Used to quickly free all memory after processing one insn. */
252 static char *reload_insn_firstobj
;
254 /* List of insn_chain instructions, one for every insn that reload needs to
256 struct insn_chain
*reload_insn_chain
;
258 /* TRUE if we potentially left dead insns in the insn stream and want to
259 run DCE immediately after reload, FALSE otherwise. */
260 static bool need_dce
;
262 /* List of all insns needing reloads. */
263 static struct insn_chain
*insns_need_reload
;
265 /* This structure is used to record information about register eliminations.
266 Each array entry describes one possible way of eliminating a register
267 in favor of another. If there is more than one way of eliminating a
268 particular register, the most preferred should be specified first. */
272 int from
; /* Register number to be eliminated. */
273 int to
; /* Register number used as replacement. */
274 HOST_WIDE_INT initial_offset
; /* Initial difference between values. */
275 int can_eliminate
; /* Nonzero if this elimination can be done. */
276 int can_eliminate_previous
; /* Value returned by TARGET_CAN_ELIMINATE
277 target hook in previous scan over insns
279 HOST_WIDE_INT offset
; /* Current offset between the two regs. */
280 HOST_WIDE_INT previous_offset
;/* Offset at end of previous insn. */
281 int ref_outside_mem
; /* "to" has been referenced outside a MEM. */
282 rtx from_rtx
; /* REG rtx for the register to be eliminated.
283 We cannot simply compare the number since
284 we might then spuriously replace a hard
285 register corresponding to a pseudo
286 assigned to the reg to be eliminated. */
287 rtx to_rtx
; /* REG rtx for the replacement. */
290 static struct elim_table
*reg_eliminate
= 0;
292 /* This is an intermediate structure to initialize the table. It has
293 exactly the members provided by ELIMINABLE_REGS. */
294 static const struct elim_table_1
298 } reg_eliminate_1
[] =
300 /* If a set of eliminable registers was specified, define the table from it.
301 Otherwise, default to the normal case of the frame pointer being
302 replaced by the stack pointer. */
304 #ifdef ELIMINABLE_REGS
307 {{ FRAME_POINTER_REGNUM
, STACK_POINTER_REGNUM
}};
310 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
312 /* Record the number of pending eliminations that have an offset not equal
313 to their initial offset. If nonzero, we use a new copy of each
314 replacement result in any insns encountered. */
315 int num_not_at_initial_offset
;
317 /* Count the number of registers that we may be able to eliminate. */
318 static int num_eliminable
;
319 /* And the number of registers that are equivalent to a constant that
320 can be eliminated to frame_pointer / arg_pointer + constant. */
321 static int num_eliminable_invariants
;
323 /* For each label, we record the offset of each elimination. If we reach
324 a label by more than one path and an offset differs, we cannot do the
325 elimination. This information is indexed by the difference of the
326 number of the label and the first label number. We can't offset the
327 pointer itself as this can cause problems on machines with segmented
328 memory. The first table is an array of flags that records whether we
329 have yet encountered a label and the second table is an array of arrays,
330 one entry in the latter array for each elimination. */
332 static int first_label_num
;
333 static char *offsets_known_at
;
334 static HOST_WIDE_INT (*offsets_at
)[NUM_ELIMINABLE_REGS
];
336 vec
<reg_equivs_t
, va_gc
> *reg_equivs
;
338 /* Stack of addresses where an rtx has been changed. We can undo the
339 changes by popping items off the stack and restoring the original
340 value at each location.
342 We use this simplistic undo capability rather than copy_rtx as copy_rtx
343 will not make a deep copy of a normally sharable rtx, such as
344 (const (plus (symbol_ref) (const_int))). If such an expression appears
345 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
346 rtx expression would be changed. See PR 42431. */
349 static vec
<rtx_p
> substitute_stack
;
351 /* Number of labels in the current function. */
353 static int num_labels
;
355 static void replace_pseudos_in (rtx
*, machine_mode
, rtx
);
356 static void maybe_fix_stack_asms (void);
357 static void copy_reloads (struct insn_chain
*);
358 static void calculate_needs_all_insns (int);
359 static int find_reg (struct insn_chain
*, int);
360 static void find_reload_regs (struct insn_chain
*);
361 static void select_reload_regs (void);
362 static void delete_caller_save_insns (void);
364 static void spill_failure (rtx_insn
*, enum reg_class
);
365 static void count_spilled_pseudo (int, int, int);
366 static void delete_dead_insn (rtx_insn
*);
367 static void alter_reg (int, int, bool);
368 static void set_label_offsets (rtx
, rtx_insn
*, int);
369 static void check_eliminable_occurrences (rtx
);
370 static void elimination_effects (rtx
, machine_mode
);
371 static rtx
eliminate_regs_1 (rtx
, machine_mode
, rtx
, bool, bool);
372 static int eliminate_regs_in_insn (rtx_insn
*, int);
373 static void update_eliminable_offsets (void);
374 static void mark_not_eliminable (rtx
, const_rtx
, void *);
375 static void set_initial_elim_offsets (void);
376 static bool verify_initial_elim_offsets (void);
377 static void set_initial_label_offsets (void);
378 static void set_offsets_for_label (rtx_insn
*);
379 static void init_eliminable_invariants (rtx_insn
*, bool);
380 static void init_elim_table (void);
381 static void free_reg_equiv (void);
382 static void update_eliminables (HARD_REG_SET
*);
383 static bool update_eliminables_and_spill (void);
384 static void elimination_costs_in_insn (rtx_insn
*);
385 static void spill_hard_reg (unsigned int, int);
386 static int finish_spills (int);
387 static void scan_paradoxical_subregs (rtx
);
388 static void count_pseudo (int);
389 static void order_regs_for_reload (struct insn_chain
*);
390 static void reload_as_needed (int);
391 static void forget_old_reloads_1 (rtx
, const_rtx
, void *);
392 static void forget_marked_reloads (regset
);
393 static int reload_reg_class_lower (const void *, const void *);
394 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type
,
396 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type
,
398 static int reload_reg_free_p (unsigned int, int, enum reload_type
);
399 static int reload_reg_free_for_value_p (int, int, int, enum reload_type
,
401 static int free_for_value_p (int, machine_mode
, int, enum reload_type
,
403 static int allocate_reload_reg (struct insn_chain
*, int, int);
404 static int conflicts_with_override (rtx
);
405 static void failed_reload (rtx_insn
*, int);
406 static int set_reload_reg (int, int);
407 static void choose_reload_regs_init (struct insn_chain
*, rtx
*);
408 static void choose_reload_regs (struct insn_chain
*);
409 static void emit_input_reload_insns (struct insn_chain
*, struct reload
*,
411 static void emit_output_reload_insns (struct insn_chain
*, struct reload
*,
413 static void do_input_reload (struct insn_chain
*, struct reload
*, int);
414 static void do_output_reload (struct insn_chain
*, struct reload
*, int);
415 static void emit_reload_insns (struct insn_chain
*);
416 static void delete_output_reload (rtx_insn
*, int, int, rtx
);
417 static void delete_address_reloads (rtx_insn
*, rtx_insn
*);
418 static void delete_address_reloads_1 (rtx_insn
*, rtx
, rtx_insn
*);
419 static void inc_for_reload (rtx
, rtx
, rtx
, int);
421 static void add_auto_inc_notes (rtx_insn
*, rtx
);
423 static void substitute (rtx
*, const_rtx
, rtx
);
424 static bool gen_reload_chain_without_interm_reg_p (int, int);
425 static int reloads_conflict (int, int);
426 static rtx_insn
*gen_reload (rtx
, rtx
, int, enum reload_type
);
427 static rtx_insn
*emit_insn_if_valid_for_reload (rtx
);
429 /* Initialize the reload pass. This is called at the beginning of compilation
430 and may be called again if the target is reinitialized. */
437 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
438 Set spill_indirect_levels to the number of levels such addressing is
439 permitted, zero if it is not permitted at all. */
442 = gen_rtx_MEM (Pmode
,
445 LAST_VIRTUAL_REGISTER
+ 1),
446 gen_int_mode (4, Pmode
)));
447 spill_indirect_levels
= 0;
449 while (memory_address_p (QImode
, tem
))
451 spill_indirect_levels
++;
452 tem
= gen_rtx_MEM (Pmode
, tem
);
455 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
457 tem
= gen_rtx_MEM (Pmode
, gen_rtx_SYMBOL_REF (Pmode
, "foo"));
458 indirect_symref_ok
= memory_address_p (QImode
, tem
);
460 /* See if reg+reg is a valid (and offsettable) address. */
462 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
464 tem
= gen_rtx_PLUS (Pmode
,
465 gen_rtx_REG (Pmode
, HARD_FRAME_POINTER_REGNUM
),
466 gen_rtx_REG (Pmode
, i
));
468 /* This way, we make sure that reg+reg is an offsettable address. */
469 tem
= plus_constant (Pmode
, tem
, 4);
471 if (memory_address_p (QImode
, tem
))
473 double_reg_address_ok
= 1;
478 /* Initialize obstack for our rtl allocation. */
479 if (reload_startobj
== NULL
)
481 gcc_obstack_init (&reload_obstack
);
482 reload_startobj
= XOBNEWVAR (&reload_obstack
, char, 0);
485 INIT_REG_SET (&spilled_pseudos
);
486 INIT_REG_SET (&changed_allocation_pseudos
);
487 INIT_REG_SET (&pseudos_counted
);
490 /* List of insn chains that are currently unused. */
491 static struct insn_chain
*unused_insn_chains
= 0;
493 /* Allocate an empty insn_chain structure. */
495 new_insn_chain (void)
497 struct insn_chain
*c
;
499 if (unused_insn_chains
== 0)
501 c
= XOBNEW (&reload_obstack
, struct insn_chain
);
502 INIT_REG_SET (&c
->live_throughout
);
503 INIT_REG_SET (&c
->dead_or_set
);
507 c
= unused_insn_chains
;
508 unused_insn_chains
= c
->next
;
510 c
->is_caller_save_insn
= 0;
511 c
->need_operand_change
= 0;
517 /* Small utility function to set all regs in hard reg set TO which are
518 allocated to pseudos in regset FROM. */
521 compute_use_by_pseudos (HARD_REG_SET
*to
, regset from
)
524 reg_set_iterator rsi
;
526 EXECUTE_IF_SET_IN_REG_SET (from
, FIRST_PSEUDO_REGISTER
, regno
, rsi
)
528 int r
= reg_renumber
[regno
];
532 /* reload_combine uses the information from DF_LIVE_IN,
533 which might still contain registers that have not
534 actually been allocated since they have an
536 gcc_assert (ira_conflicts_p
|| reload_completed
);
539 add_to_hard_reg_set (to
, PSEUDO_REGNO_MODE (regno
), r
);
543 /* Replace all pseudos found in LOC with their corresponding
547 replace_pseudos_in (rtx
*loc
, machine_mode mem_mode
, rtx usage
)
560 unsigned int regno
= REGNO (x
);
562 if (regno
< FIRST_PSEUDO_REGISTER
)
565 x
= eliminate_regs_1 (x
, mem_mode
, usage
, true, false);
569 replace_pseudos_in (loc
, mem_mode
, usage
);
573 if (reg_equiv_constant (regno
))
574 *loc
= reg_equiv_constant (regno
);
575 else if (reg_equiv_invariant (regno
))
576 *loc
= reg_equiv_invariant (regno
);
577 else if (reg_equiv_mem (regno
))
578 *loc
= reg_equiv_mem (regno
);
579 else if (reg_equiv_address (regno
))
580 *loc
= gen_rtx_MEM (GET_MODE (x
), reg_equiv_address (regno
));
583 gcc_assert (!REG_P (regno_reg_rtx
[regno
])
584 || REGNO (regno_reg_rtx
[regno
]) != regno
);
585 *loc
= regno_reg_rtx
[regno
];
590 else if (code
== MEM
)
592 replace_pseudos_in (& XEXP (x
, 0), GET_MODE (x
), usage
);
596 /* Process each of our operands recursively. */
597 fmt
= GET_RTX_FORMAT (code
);
598 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
600 replace_pseudos_in (&XEXP (x
, i
), mem_mode
, usage
);
601 else if (*fmt
== 'E')
602 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
603 replace_pseudos_in (& XVECEXP (x
, i
, j
), mem_mode
, usage
);
606 /* Determine if the current function has an exception receiver block
607 that reaches the exit block via non-exceptional edges */
610 has_nonexceptional_receiver (void)
614 basic_block
*tos
, *worklist
, bb
;
616 /* If we're not optimizing, then just err on the safe side. */
620 /* First determine which blocks can reach exit via normal paths. */
621 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
623 FOR_EACH_BB_FN (bb
, cfun
)
624 bb
->flags
&= ~BB_REACHABLE
;
626 /* Place the exit block on our worklist. */
627 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
628 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
630 /* Iterate: find everything reachable from what we've already seen. */
631 while (tos
!= worklist
)
635 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
636 if (!(e
->flags
& EDGE_ABNORMAL
))
638 basic_block src
= e
->src
;
640 if (!(src
->flags
& BB_REACHABLE
))
642 src
->flags
|= BB_REACHABLE
;
649 /* Now see if there's a reachable block with an exceptional incoming
651 FOR_EACH_BB_FN (bb
, cfun
)
652 if (bb
->flags
& BB_REACHABLE
&& bb_has_abnormal_pred (bb
))
655 /* No exceptional block reached exit unexceptionally. */
659 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
660 zero elements) to MAX_REG_NUM elements.
662 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
664 grow_reg_equivs (void)
666 int old_size
= vec_safe_length (reg_equivs
);
667 int max_regno
= max_reg_num ();
671 memset (&ze
, 0, sizeof (reg_equivs_t
));
672 vec_safe_reserve (reg_equivs
, max_regno
);
673 for (i
= old_size
; i
< max_regno
; i
++)
674 reg_equivs
->quick_insert (i
, ze
);
678 /* Global variables used by reload and its subroutines. */
680 /* The current basic block while in calculate_elim_costs_all_insns. */
681 static basic_block elim_bb
;
683 /* Set during calculate_needs if an insn needs register elimination. */
684 static int something_needs_elimination
;
685 /* Set during calculate_needs if an insn needs an operand changed. */
686 static int something_needs_operands_changed
;
687 /* Set by alter_regs if we spilled a register to the stack. */
688 static bool something_was_spilled
;
690 /* Nonzero means we couldn't get enough spill regs. */
693 /* Temporary array of pseudo-register number. */
694 static int *temp_pseudo_reg_arr
;
696 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
697 If that insn didn't set the register (i.e., it copied the register to
698 memory), just delete that insn instead of the equivalencing insn plus
699 anything now dead. If we call delete_dead_insn on that insn, we may
700 delete the insn that actually sets the register if the register dies
701 there and that is incorrect. */
705 for (int i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
707 if (reg_renumber
[i
] < 0 && reg_equiv_init (i
) != 0)
710 for (list
= reg_equiv_init (i
); list
; list
= XEXP (list
, 1))
712 rtx_insn
*equiv_insn
= as_a
<rtx_insn
*> (XEXP (list
, 0));
714 /* If we already deleted the insn or if it may trap, we can't
715 delete it. The latter case shouldn't happen, but can
716 if an insn has a variable address, gets a REG_EH_REGION
717 note added to it, and then gets converted into a load
718 from a constant address. */
719 if (NOTE_P (equiv_insn
)
720 || can_throw_internal (equiv_insn
))
722 else if (reg_set_p (regno_reg_rtx
[i
], PATTERN (equiv_insn
)))
723 delete_dead_insn (equiv_insn
);
725 SET_INSN_DELETED (equiv_insn
);
731 /* Return true if remove_init_insns will delete INSN. */
733 will_delete_init_insn_p (rtx_insn
*insn
)
735 rtx set
= single_set (insn
);
736 if (!set
|| !REG_P (SET_DEST (set
)))
738 unsigned regno
= REGNO (SET_DEST (set
));
740 if (can_throw_internal (insn
))
743 if (regno
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[regno
] >= 0)
746 for (rtx list
= reg_equiv_init (regno
); list
; list
= XEXP (list
, 1))
748 rtx equiv_insn
= XEXP (list
, 0);
749 if (equiv_insn
== insn
)
755 /* Main entry point for the reload pass.
757 FIRST is the first insn of the function being compiled.
759 GLOBAL nonzero means we were called from global_alloc
760 and should attempt to reallocate any pseudoregs that we
761 displace from hard regs we will use for reloads.
762 If GLOBAL is zero, we do not have enough information to do that,
763 so any pseudo reg that is spilled must go to the stack.
765 Return value is TRUE if reload likely left dead insns in the
766 stream and a DCE pass should be run to elimiante them. Else the
767 return value is FALSE. */
770 reload (rtx_insn
*first
, int global
)
774 struct elim_table
*ep
;
778 /* Make sure even insns with volatile mem refs are recognizable. */
783 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
785 /* Make sure that the last insn in the chain
786 is not something that needs reloading. */
787 emit_note (NOTE_INSN_DELETED
);
789 /* Enable find_equiv_reg to distinguish insns made by reload. */
790 reload_first_uid
= get_max_uid ();
792 #ifdef SECONDARY_MEMORY_NEEDED
793 /* Initialize the secondary memory table. */
794 clear_secondary_mem ();
797 /* We don't have a stack slot for any spill reg yet. */
798 memset (spill_stack_slot
, 0, sizeof spill_stack_slot
);
799 memset (spill_stack_slot_width
, 0, sizeof spill_stack_slot_width
);
801 /* Initialize the save area information for caller-save, in case some
805 /* Compute which hard registers are now in use
806 as homes for pseudo registers.
807 This is done here rather than (eg) in global_alloc
808 because this point is reached even if not optimizing. */
809 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
812 /* A function that has a nonlocal label that can reach the exit
813 block via non-exceptional paths must save all call-saved
815 if (cfun
->has_nonlocal_label
816 && has_nonexceptional_receiver ())
817 crtl
->saves_all_registers
= 1;
819 if (crtl
->saves_all_registers
)
820 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
821 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
822 df_set_regs_ever_live (i
, true);
824 /* Find all the pseudo registers that didn't get hard regs
825 but do have known equivalent constants or memory slots.
826 These include parameters (known equivalent to parameter slots)
827 and cse'd or loop-moved constant memory addresses.
829 Record constant equivalents in reg_equiv_constant
830 so they will be substituted by find_reloads.
831 Record memory equivalents in reg_mem_equiv so they can
832 be substituted eventually by altering the REG-rtx's. */
835 reg_old_renumber
= XCNEWVEC (short, max_regno
);
836 memcpy (reg_old_renumber
, reg_renumber
, max_regno
* sizeof (short));
837 pseudo_forbidden_regs
= XNEWVEC (HARD_REG_SET
, max_regno
);
838 pseudo_previous_regs
= XCNEWVEC (HARD_REG_SET
, max_regno
);
840 CLEAR_HARD_REG_SET (bad_spill_regs_global
);
842 init_eliminable_invariants (first
, true);
845 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
846 stack slots to the pseudos that lack hard regs or equivalents.
847 Do not touch virtual registers. */
849 temp_pseudo_reg_arr
= XNEWVEC (int, max_regno
- LAST_VIRTUAL_REGISTER
- 1);
850 for (n
= 0, i
= LAST_VIRTUAL_REGISTER
+ 1; i
< max_regno
; i
++)
851 temp_pseudo_reg_arr
[n
++] = i
;
854 /* Ask IRA to order pseudo-registers for better stack slot
856 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr
, n
, reg_max_ref_width
);
858 for (i
= 0; i
< n
; i
++)
859 alter_reg (temp_pseudo_reg_arr
[i
], -1, false);
861 /* If we have some registers we think can be eliminated, scan all insns to
862 see if there is an insn that sets one of these registers to something
863 other than itself plus a constant. If so, the register cannot be
864 eliminated. Doing this scan here eliminates an extra pass through the
865 main reload loop in the most common case where register elimination
867 for (insn
= first
; insn
&& num_eliminable
; insn
= NEXT_INSN (insn
))
869 note_stores (PATTERN (insn
), mark_not_eliminable
, NULL
);
871 maybe_fix_stack_asms ();
873 insns_need_reload
= 0;
874 something_needs_elimination
= 0;
876 /* Initialize to -1, which means take the first spill register. */
879 /* Spill any hard regs that we know we can't eliminate. */
880 CLEAR_HARD_REG_SET (used_spill_regs
);
881 /* There can be multiple ways to eliminate a register;
882 they should be listed adjacently.
883 Elimination for any register fails only if all possible ways fail. */
884 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; )
887 int can_eliminate
= 0;
890 can_eliminate
|= ep
->can_eliminate
;
893 while (ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
] && ep
->from
== from
);
895 spill_hard_reg (from
, 1);
898 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
&& frame_pointer_needed
)
899 spill_hard_reg (HARD_FRAME_POINTER_REGNUM
, 1);
901 finish_spills (global
);
903 /* From now on, we may need to generate moves differently. We may also
904 allow modifications of insns which cause them to not be recognized.
905 Any such modifications will be cleaned up during reload itself. */
906 reload_in_progress
= 1;
908 /* This loop scans the entire function each go-round
909 and repeats until one repetition spills no additional hard regs. */
912 int something_changed
;
914 HOST_WIDE_INT starting_frame_size
;
916 starting_frame_size
= get_frame_size ();
917 something_was_spilled
= false;
919 set_initial_elim_offsets ();
920 set_initial_label_offsets ();
922 /* For each pseudo register that has an equivalent location defined,
923 try to eliminate any eliminable registers (such as the frame pointer)
924 assuming initial offsets for the replacement register, which
927 If the resulting location is directly addressable, substitute
928 the MEM we just got directly for the old REG.
930 If it is not addressable but is a constant or the sum of a hard reg
931 and constant, it is probably not addressable because the constant is
932 out of range, in that case record the address; we will generate
933 hairy code to compute the address in a register each time it is
934 needed. Similarly if it is a hard register, but one that is not
935 valid as an address register.
937 If the location is not addressable, but does not have one of the
938 above forms, assign a stack slot. We have to do this to avoid the
939 potential of producing lots of reloads if, e.g., a location involves
940 a pseudo that didn't get a hard register and has an equivalent memory
941 location that also involves a pseudo that didn't get a hard register.
943 Perhaps at some point we will improve reload_when_needed handling
944 so this problem goes away. But that's very hairy. */
946 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
947 if (reg_renumber
[i
] < 0 && reg_equiv_memory_loc (i
))
949 rtx x
= eliminate_regs (reg_equiv_memory_loc (i
), VOIDmode
,
952 if (strict_memory_address_addr_space_p
953 (GET_MODE (regno_reg_rtx
[i
]), XEXP (x
, 0),
955 reg_equiv_mem (i
) = x
, reg_equiv_address (i
) = 0;
956 else if (CONSTANT_P (XEXP (x
, 0))
957 || (REG_P (XEXP (x
, 0))
958 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
)
959 || (GET_CODE (XEXP (x
, 0)) == PLUS
960 && REG_P (XEXP (XEXP (x
, 0), 0))
961 && (REGNO (XEXP (XEXP (x
, 0), 0))
962 < FIRST_PSEUDO_REGISTER
)
963 && CONSTANT_P (XEXP (XEXP (x
, 0), 1))))
964 reg_equiv_address (i
) = XEXP (x
, 0), reg_equiv_mem (i
) = 0;
967 /* Make a new stack slot. Then indicate that something
968 changed so we go back and recompute offsets for
969 eliminable registers because the allocation of memory
970 below might change some offset. reg_equiv_{mem,address}
971 will be set up for this pseudo on the next pass around
973 reg_equiv_memory_loc (i
) = 0;
974 reg_equiv_init (i
) = 0;
975 alter_reg (i
, -1, true);
979 if (caller_save_needed
)
982 if (starting_frame_size
&& crtl
->stack_alignment_needed
)
984 /* If we have a stack frame, we must align it now. The
985 stack size may be a part of the offset computation for
986 register elimination. So if this changes the stack size,
987 then repeat the elimination bookkeeping. We don't
988 realign when there is no stack, as that will cause a
989 stack frame when none is needed should
990 STARTING_FRAME_OFFSET not be already aligned to
992 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
994 /* If we allocated another stack slot, redo elimination bookkeeping. */
995 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
997 update_eliminables_and_spill ();
1001 if (caller_save_needed
)
1003 save_call_clobbered_regs ();
1004 /* That might have allocated new insn_chain structures. */
1005 reload_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1008 calculate_needs_all_insns (global
);
1010 if (! ira_conflicts_p
)
1011 /* Don't do it for IRA. We need this info because we don't
1012 change live_throughout and dead_or_set for chains when IRA
1014 CLEAR_REG_SET (&spilled_pseudos
);
1018 something_changed
= 0;
1020 /* If we allocated any new memory locations, make another pass
1021 since it might have changed elimination offsets. */
1022 if (something_was_spilled
|| starting_frame_size
!= get_frame_size ())
1023 something_changed
= 1;
1025 /* Even if the frame size remained the same, we might still have
1026 changed elimination offsets, e.g. if find_reloads called
1027 force_const_mem requiring the back end to allocate a constant
1028 pool base register that needs to be saved on the stack. */
1029 else if (!verify_initial_elim_offsets ())
1030 something_changed
= 1;
1032 if (update_eliminables_and_spill ())
1035 something_changed
= 1;
1038 select_reload_regs ();
1042 if (insns_need_reload
!= 0 || did_spill
)
1043 something_changed
|= finish_spills (global
);
1045 if (! something_changed
)
1048 if (caller_save_needed
)
1049 delete_caller_save_insns ();
1051 obstack_free (&reload_obstack
, reload_firstobj
);
1054 /* If global-alloc was run, notify it of any register eliminations we have
1057 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
1058 if (ep
->can_eliminate
)
1059 mark_elimination (ep
->from
, ep
->to
);
1061 remove_init_insns ();
1063 /* Use the reload registers where necessary
1064 by generating move instructions to move the must-be-register
1065 values into or out of the reload registers. */
1067 if (insns_need_reload
!= 0 || something_needs_elimination
1068 || something_needs_operands_changed
)
1070 HOST_WIDE_INT old_frame_size
= get_frame_size ();
1072 reload_as_needed (global
);
1074 gcc_assert (old_frame_size
== get_frame_size ());
1076 gcc_assert (verify_initial_elim_offsets ());
1079 /* If we were able to eliminate the frame pointer, show that it is no
1080 longer live at the start of any basic block. If it ls live by
1081 virtue of being in a pseudo, that pseudo will be marked live
1082 and hence the frame pointer will be known to be live via that
1085 if (! frame_pointer_needed
)
1086 FOR_EACH_BB_FN (bb
, cfun
)
1087 bitmap_clear_bit (df_get_live_in (bb
), HARD_FRAME_POINTER_REGNUM
);
1089 /* Come here (with failure set nonzero) if we can't get enough spill
1093 CLEAR_REG_SET (&changed_allocation_pseudos
);
1094 CLEAR_REG_SET (&spilled_pseudos
);
1095 reload_in_progress
= 0;
1097 /* Now eliminate all pseudo regs by modifying them into
1098 their equivalent memory references.
1099 The REG-rtx's for the pseudos are modified in place,
1100 so all insns that used to refer to them now refer to memory.
1102 For a reg that has a reg_equiv_address, all those insns
1103 were changed by reloading so that no insns refer to it any longer;
1104 but the DECL_RTL of a variable decl may refer to it,
1105 and if so this causes the debugging info to mention the variable. */
1107 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1111 if (reg_equiv_mem (i
))
1112 addr
= XEXP (reg_equiv_mem (i
), 0);
1114 if (reg_equiv_address (i
))
1115 addr
= reg_equiv_address (i
);
1119 if (reg_renumber
[i
] < 0)
1121 rtx reg
= regno_reg_rtx
[i
];
1123 REG_USERVAR_P (reg
) = 0;
1124 PUT_CODE (reg
, MEM
);
1125 XEXP (reg
, 0) = addr
;
1126 if (reg_equiv_memory_loc (i
))
1127 MEM_COPY_ATTRIBUTES (reg
, reg_equiv_memory_loc (i
));
1129 MEM_ATTRS (reg
) = 0;
1130 MEM_NOTRAP_P (reg
) = 1;
1132 else if (reg_equiv_mem (i
))
1133 XEXP (reg_equiv_mem (i
), 0) = addr
;
1136 /* We don't want complex addressing modes in debug insns
1137 if simpler ones will do, so delegitimize equivalences
1139 if (MAY_HAVE_DEBUG_INSNS
&& reg_renumber
[i
] < 0)
1141 rtx reg
= regno_reg_rtx
[i
];
1145 if (reg_equiv_constant (i
))
1146 equiv
= reg_equiv_constant (i
);
1147 else if (reg_equiv_invariant (i
))
1148 equiv
= reg_equiv_invariant (i
);
1149 else if (reg
&& MEM_P (reg
))
1150 equiv
= targetm
.delegitimize_address (reg
);
1151 else if (reg
&& REG_P (reg
) && (int)REGNO (reg
) != i
)
1157 for (use
= DF_REG_USE_CHAIN (i
); use
; use
= next
)
1159 insn
= DF_REF_INSN (use
);
1161 /* Make sure the next ref is for a different instruction,
1162 so that we're not affected by the rescan. */
1163 next
= DF_REF_NEXT_REG (use
);
1164 while (next
&& DF_REF_INSN (next
) == insn
)
1165 next
= DF_REF_NEXT_REG (next
);
1167 if (DEBUG_INSN_P (insn
))
1171 INSN_VAR_LOCATION_LOC (insn
) = gen_rtx_UNKNOWN_VAR_LOC ();
1172 df_insn_rescan_debug_internal (insn
);
1175 INSN_VAR_LOCATION_LOC (insn
)
1176 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn
),
1183 /* We must set reload_completed now since the cleanup_subreg_operands call
1184 below will re-recognize each insn and reload may have generated insns
1185 which are only valid during and after reload. */
1186 reload_completed
= 1;
1188 /* Make a pass over all the insns and delete all USEs which we inserted
1189 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1190 notes. Delete all CLOBBER insns, except those that refer to the return
1191 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1192 from misarranging variable-array code, and simplify (subreg (reg))
1193 operands. Strip and regenerate REG_INC notes that may have been moved
1196 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
1202 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn
),
1203 VOIDmode
, CALL_INSN_FUNCTION_USAGE (insn
));
1205 if ((GET_CODE (PATTERN (insn
)) == USE
1206 /* We mark with QImode USEs introduced by reload itself. */
1207 && (GET_MODE (insn
) == QImode
1208 || find_reg_note (insn
, REG_EQUAL
, NULL_RTX
)))
1209 || (GET_CODE (PATTERN (insn
)) == CLOBBER
1210 && (!MEM_P (XEXP (PATTERN (insn
), 0))
1211 || GET_MODE (XEXP (PATTERN (insn
), 0)) != BLKmode
1212 || (GET_CODE (XEXP (XEXP (PATTERN (insn
), 0), 0)) != SCRATCH
1213 && XEXP (XEXP (PATTERN (insn
), 0), 0)
1214 != stack_pointer_rtx
))
1215 && (!REG_P (XEXP (PATTERN (insn
), 0))
1216 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn
), 0)))))
1222 /* Some CLOBBERs may survive until here and still reference unassigned
1223 pseudos with const equivalent, which may in turn cause ICE in later
1224 passes if the reference remains in place. */
1225 if (GET_CODE (PATTERN (insn
)) == CLOBBER
)
1226 replace_pseudos_in (& XEXP (PATTERN (insn
), 0),
1227 VOIDmode
, PATTERN (insn
));
1229 /* Discard obvious no-ops, even without -O. This optimization
1230 is fast and doesn't interfere with debugging. */
1231 if (NONJUMP_INSN_P (insn
)
1232 && GET_CODE (PATTERN (insn
)) == SET
1233 && REG_P (SET_SRC (PATTERN (insn
)))
1234 && REG_P (SET_DEST (PATTERN (insn
)))
1235 && (REGNO (SET_SRC (PATTERN (insn
)))
1236 == REGNO (SET_DEST (PATTERN (insn
)))))
1242 pnote
= ®_NOTES (insn
);
1245 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
1246 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
1247 || REG_NOTE_KIND (*pnote
) == REG_INC
)
1248 *pnote
= XEXP (*pnote
, 1);
1250 pnote
= &XEXP (*pnote
, 1);
1254 add_auto_inc_notes (insn
, PATTERN (insn
));
1257 /* Simplify (subreg (reg)) if it appears as an operand. */
1258 cleanup_subreg_operands (insn
);
1260 /* Clean up invalid ASMs so that they don't confuse later passes.
1262 if (asm_noperands (PATTERN (insn
)) >= 0)
1264 extract_insn (insn
);
1265 if (!constrain_operands (1, get_enabled_alternatives (insn
)))
1267 error_for_asm (insn
,
1268 "%<asm%> operand has impossible constraints");
1275 /* If we are doing generic stack checking, give a warning if this
1276 function's frame size is larger than we expect. */
1277 if (flag_stack_check
== GENERIC_STACK_CHECK
)
1279 HOST_WIDE_INT size
= get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE
;
1280 static int verbose_warned
= 0;
1282 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1283 if (df_regs_ever_live_p (i
) && ! fixed_regs
[i
] && call_used_regs
[i
])
1284 size
+= UNITS_PER_WORD
;
1286 if (size
> STACK_CHECK_MAX_FRAME_SIZE
)
1288 warning (0, "frame size too large for reliable stack checking");
1289 if (! verbose_warned
)
1291 warning (0, "try reducing the number of local variables");
1297 free (temp_pseudo_reg_arr
);
1299 /* Indicate that we no longer have known memory locations or constants. */
1302 free (reg_max_ref_width
);
1303 free (reg_old_renumber
);
1304 free (pseudo_previous_regs
);
1305 free (pseudo_forbidden_regs
);
1307 CLEAR_HARD_REG_SET (used_spill_regs
);
1308 for (i
= 0; i
< n_spills
; i
++)
1309 SET_HARD_REG_BIT (used_spill_regs
, spill_regs
[i
]);
1311 /* Free all the insn_chain structures at once. */
1312 obstack_free (&reload_obstack
, reload_startobj
);
1313 unused_insn_chains
= 0;
1315 inserted
= fixup_abnormal_edges ();
1317 /* We've possibly turned single trapping insn into multiple ones. */
1318 if (cfun
->can_throw_non_call_exceptions
)
1321 blocks
= sbitmap_alloc (last_basic_block_for_fn (cfun
));
1322 bitmap_ones (blocks
);
1323 find_many_sub_basic_blocks (blocks
);
1324 sbitmap_free (blocks
);
1328 commit_edge_insertions ();
1330 /* Replacing pseudos with their memory equivalents might have
1331 created shared rtx. Subsequent passes would get confused
1332 by this, so unshare everything here. */
1333 unshare_all_rtl_again (first
);
1335 #ifdef STACK_BOUNDARY
1336 /* init_emit has set the alignment of the hard frame pointer
1337 to STACK_BOUNDARY. It is very likely no longer valid if
1338 the hard frame pointer was used for register allocation. */
1339 if (!frame_pointer_needed
)
1340 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM
) = BITS_PER_UNIT
;
1343 substitute_stack
.release ();
1345 gcc_assert (bitmap_empty_p (&spilled_pseudos
));
1347 reload_completed
= !failure
;
1352 /* Yet another special case. Unfortunately, reg-stack forces people to
1353 write incorrect clobbers in asm statements. These clobbers must not
1354 cause the register to appear in bad_spill_regs, otherwise we'll call
1355 fatal_insn later. We clear the corresponding regnos in the live
1356 register sets to avoid this.
1357 The whole thing is rather sick, I'm afraid. */
1360 maybe_fix_stack_asms (void)
1363 const char *constraints
[MAX_RECOG_OPERANDS
];
1364 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1365 struct insn_chain
*chain
;
1367 for (chain
= reload_insn_chain
; chain
!= 0; chain
= chain
->next
)
1370 HARD_REG_SET clobbered
, allowed
;
1373 if (! INSN_P (chain
->insn
)
1374 || (noperands
= asm_noperands (PATTERN (chain
->insn
))) < 0)
1376 pat
= PATTERN (chain
->insn
);
1377 if (GET_CODE (pat
) != PARALLEL
)
1380 CLEAR_HARD_REG_SET (clobbered
);
1381 CLEAR_HARD_REG_SET (allowed
);
1383 /* First, make a mask of all stack regs that are clobbered. */
1384 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
1386 rtx t
= XVECEXP (pat
, 0, i
);
1387 if (GET_CODE (t
) == CLOBBER
&& STACK_REG_P (XEXP (t
, 0)))
1388 SET_HARD_REG_BIT (clobbered
, REGNO (XEXP (t
, 0)));
1391 /* Get the operand values and constraints out of the insn. */
1392 decode_asm_operands (pat
, recog_data
.operand
, recog_data
.operand_loc
,
1393 constraints
, operand_mode
, NULL
);
1395 /* For every operand, see what registers are allowed. */
1396 for (i
= 0; i
< noperands
; i
++)
1398 const char *p
= constraints
[i
];
1399 /* For every alternative, we compute the class of registers allowed
1400 for reloading in CLS, and merge its contents into the reg set
1402 int cls
= (int) NO_REGS
;
1408 if (c
== '\0' || c
== ',' || c
== '#')
1410 /* End of one alternative - mark the regs in the current
1411 class, and reset the class. */
1412 IOR_HARD_REG_SET (allowed
, reg_class_contents
[cls
]);
1418 } while (c
!= '\0' && c
!= ',');
1427 cls
= (int) reg_class_subunion
[cls
][(int) GENERAL_REGS
];
1431 enum constraint_num cn
= lookup_constraint (p
);
1432 if (insn_extra_address_constraint (cn
))
1433 cls
= (int) reg_class_subunion
[cls
]
1434 [(int) base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1437 cls
= (int) reg_class_subunion
[cls
]
1438 [reg_class_for_constraint (cn
)];
1441 p
+= CONSTRAINT_LEN (c
, p
);
1444 /* Those of the registers which are clobbered, but allowed by the
1445 constraints, must be usable as reload registers. So clear them
1446 out of the life information. */
1447 AND_HARD_REG_SET (allowed
, clobbered
);
1448 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1449 if (TEST_HARD_REG_BIT (allowed
, i
))
1451 CLEAR_REGNO_REG_SET (&chain
->live_throughout
, i
);
1452 CLEAR_REGNO_REG_SET (&chain
->dead_or_set
, i
);
1459 /* Copy the global variables n_reloads and rld into the corresponding elts
1462 copy_reloads (struct insn_chain
*chain
)
1464 chain
->n_reloads
= n_reloads
;
1465 chain
->rld
= XOBNEWVEC (&reload_obstack
, struct reload
, n_reloads
);
1466 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
1467 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1470 /* Walk the chain of insns, and determine for each whether it needs reloads
1471 and/or eliminations. Build the corresponding insns_need_reload list, and
1472 set something_needs_elimination as appropriate. */
1474 calculate_needs_all_insns (int global
)
1476 struct insn_chain
**pprev_reload
= &insns_need_reload
;
1477 struct insn_chain
*chain
, *next
= 0;
1479 something_needs_elimination
= 0;
1481 reload_insn_firstobj
= XOBNEWVAR (&reload_obstack
, char, 0);
1482 for (chain
= reload_insn_chain
; chain
!= 0; chain
= next
)
1484 rtx_insn
*insn
= chain
->insn
;
1488 /* Clear out the shortcuts. */
1489 chain
->n_reloads
= 0;
1490 chain
->need_elim
= 0;
1491 chain
->need_reload
= 0;
1492 chain
->need_operand_change
= 0;
1494 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1495 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1496 what effects this has on the known offsets at labels. */
1498 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1499 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1500 set_label_offsets (insn
, insn
, 0);
1504 rtx old_body
= PATTERN (insn
);
1505 int old_code
= INSN_CODE (insn
);
1506 rtx old_notes
= REG_NOTES (insn
);
1507 int did_elimination
= 0;
1508 int operands_changed
= 0;
1510 /* Skip insns that only set an equivalence. */
1511 if (will_delete_init_insn_p (insn
))
1514 /* If needed, eliminate any eliminable registers. */
1515 if (num_eliminable
|| num_eliminable_invariants
)
1516 did_elimination
= eliminate_regs_in_insn (insn
, 0);
1518 /* Analyze the instruction. */
1519 operands_changed
= find_reloads (insn
, 0, spill_indirect_levels
,
1520 global
, spill_reg_order
);
1522 /* If a no-op set needs more than one reload, this is likely
1523 to be something that needs input address reloads. We
1524 can't get rid of this cleanly later, and it is of no use
1525 anyway, so discard it now.
1526 We only do this when expensive_optimizations is enabled,
1527 since this complements reload inheritance / output
1528 reload deletion, and it can make debugging harder. */
1529 if (flag_expensive_optimizations
&& n_reloads
> 1)
1531 rtx set
= single_set (insn
);
1534 ((SET_SRC (set
) == SET_DEST (set
)
1535 && REG_P (SET_SRC (set
))
1536 && REGNO (SET_SRC (set
)) >= FIRST_PSEUDO_REGISTER
)
1537 || (REG_P (SET_SRC (set
)) && REG_P (SET_DEST (set
))
1538 && reg_renumber
[REGNO (SET_SRC (set
))] < 0
1539 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1540 && reg_equiv_memory_loc (REGNO (SET_SRC (set
))) != NULL
1541 && reg_equiv_memory_loc (REGNO (SET_DEST (set
))) != NULL
1542 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set
))),
1543 reg_equiv_memory_loc (REGNO (SET_DEST (set
)))))))
1545 if (ira_conflicts_p
)
1546 /* Inform IRA about the insn deletion. */
1547 ira_mark_memory_move_deletion (REGNO (SET_DEST (set
)),
1548 REGNO (SET_SRC (set
)));
1550 /* Delete it from the reload chain. */
1552 chain
->prev
->next
= next
;
1554 reload_insn_chain
= next
;
1556 next
->prev
= chain
->prev
;
1557 chain
->next
= unused_insn_chains
;
1558 unused_insn_chains
= chain
;
1563 update_eliminable_offsets ();
1565 /* Remember for later shortcuts which insns had any reloads or
1566 register eliminations. */
1567 chain
->need_elim
= did_elimination
;
1568 chain
->need_reload
= n_reloads
> 0;
1569 chain
->need_operand_change
= operands_changed
;
1571 /* Discard any register replacements done. */
1572 if (did_elimination
)
1574 obstack_free (&reload_obstack
, reload_insn_firstobj
);
1575 PATTERN (insn
) = old_body
;
1576 INSN_CODE (insn
) = old_code
;
1577 REG_NOTES (insn
) = old_notes
;
1578 something_needs_elimination
= 1;
1581 something_needs_operands_changed
|= operands_changed
;
1585 copy_reloads (chain
);
1586 *pprev_reload
= chain
;
1587 pprev_reload
= &chain
->next_need_reload
;
1594 /* This function is called from the register allocator to set up estimates
1595 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1596 an invariant. The structure is similar to calculate_needs_all_insns. */
1599 calculate_elim_costs_all_insns (void)
1601 int *reg_equiv_init_cost
;
1605 reg_equiv_init_cost
= XCNEWVEC (int, max_regno
);
1607 init_eliminable_invariants (get_insns (), false);
1609 set_initial_elim_offsets ();
1610 set_initial_label_offsets ();
1612 FOR_EACH_BB_FN (bb
, cfun
)
1617 FOR_BB_INSNS (bb
, insn
)
1619 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1620 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1621 what effects this has on the known offsets at labels. */
1623 if (LABEL_P (insn
) || JUMP_P (insn
) || JUMP_TABLE_DATA_P (insn
)
1624 || (INSN_P (insn
) && REG_NOTES (insn
) != 0))
1625 set_label_offsets (insn
, insn
, 0);
1629 rtx set
= single_set (insn
);
1631 /* Skip insns that only set an equivalence. */
1632 if (set
&& REG_P (SET_DEST (set
))
1633 && reg_renumber
[REGNO (SET_DEST (set
))] < 0
1634 && (reg_equiv_constant (REGNO (SET_DEST (set
)))
1635 || reg_equiv_invariant (REGNO (SET_DEST (set
)))))
1637 unsigned regno
= REGNO (SET_DEST (set
));
1638 rtx_insn_list
*init
= reg_equiv_init (regno
);
1641 rtx t
= eliminate_regs_1 (SET_SRC (set
), VOIDmode
, insn
,
1643 int cost
= set_src_cost (t
, optimize_bb_for_speed_p (bb
));
1644 int freq
= REG_FREQ_FROM_BB (bb
);
1646 reg_equiv_init_cost
[regno
] = cost
* freq
;
1650 /* If needed, eliminate any eliminable registers. */
1651 if (num_eliminable
|| num_eliminable_invariants
)
1652 elimination_costs_in_insn (insn
);
1655 update_eliminable_offsets ();
1659 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
1661 if (reg_equiv_invariant (i
))
1663 if (reg_equiv_init (i
))
1665 int cost
= reg_equiv_init_cost
[i
];
1668 "Reg %d has equivalence, initial gains %d\n", i
, cost
);
1670 ira_adjust_equiv_reg_cost (i
, cost
);
1676 "Reg %d had equivalence, but can't be eliminated\n",
1678 ira_adjust_equiv_reg_cost (i
, 0);
1683 free (reg_equiv_init_cost
);
1684 free (offsets_known_at
);
1687 offsets_known_at
= NULL
;
1690 /* Comparison function for qsort to decide which of two reloads
1691 should be handled first. *P1 and *P2 are the reload numbers. */
1694 reload_reg_class_lower (const void *r1p
, const void *r2p
)
1696 int r1
= *(const short *) r1p
, r2
= *(const short *) r2p
;
1699 /* Consider required reloads before optional ones. */
1700 t
= rld
[r1
].optional
- rld
[r2
].optional
;
1704 /* Count all solitary classes before non-solitary ones. */
1705 t
= ((reg_class_size
[(int) rld
[r2
].rclass
] == 1)
1706 - (reg_class_size
[(int) rld
[r1
].rclass
] == 1));
1710 /* Aside from solitaires, consider all multi-reg groups first. */
1711 t
= rld
[r2
].nregs
- rld
[r1
].nregs
;
1715 /* Consider reloads in order of increasing reg-class number. */
1716 t
= (int) rld
[r1
].rclass
- (int) rld
[r2
].rclass
;
1720 /* If reloads are equally urgent, sort by reload number,
1721 so that the results of qsort leave nothing to chance. */
1725 /* The cost of spilling each hard reg. */
1726 static int spill_cost
[FIRST_PSEUDO_REGISTER
];
1728 /* When spilling multiple hard registers, we use SPILL_COST for the first
1729 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1730 only the first hard reg for a multi-reg pseudo. */
1731 static int spill_add_cost
[FIRST_PSEUDO_REGISTER
];
1733 /* Map of hard regno to pseudo regno currently occupying the hard
1735 static int hard_regno_to_pseudo_regno
[FIRST_PSEUDO_REGISTER
];
1737 /* Update the spill cost arrays, considering that pseudo REG is live. */
1740 count_pseudo (int reg
)
1742 int freq
= REG_FREQ (reg
);
1743 int r
= reg_renumber
[reg
];
1746 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1747 if (ira_conflicts_p
&& r
< 0)
1750 if (REGNO_REG_SET_P (&pseudos_counted
, reg
)
1751 || REGNO_REG_SET_P (&spilled_pseudos
, reg
))
1754 SET_REGNO_REG_SET (&pseudos_counted
, reg
);
1756 gcc_assert (r
>= 0);
1758 spill_add_cost
[r
] += freq
;
1759 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1762 hard_regno_to_pseudo_regno
[r
+ nregs
] = reg
;
1763 spill_cost
[r
+ nregs
] += freq
;
1767 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1768 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1771 order_regs_for_reload (struct insn_chain
*chain
)
1774 HARD_REG_SET used_by_pseudos
;
1775 HARD_REG_SET used_by_pseudos2
;
1776 reg_set_iterator rsi
;
1778 COPY_HARD_REG_SET (bad_spill_regs
, fixed_reg_set
);
1780 memset (spill_cost
, 0, sizeof spill_cost
);
1781 memset (spill_add_cost
, 0, sizeof spill_add_cost
);
1782 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1783 hard_regno_to_pseudo_regno
[i
] = -1;
1785 /* Count number of uses of each hard reg by pseudo regs allocated to it
1786 and then order them by decreasing use. First exclude hard registers
1787 that are live in or across this insn. */
1789 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
1790 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
1791 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos
);
1792 IOR_HARD_REG_SET (bad_spill_regs
, used_by_pseudos2
);
1794 /* Now find out which pseudos are allocated to it, and update
1796 CLEAR_REG_SET (&pseudos_counted
);
1798 EXECUTE_IF_SET_IN_REG_SET
1799 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1803 EXECUTE_IF_SET_IN_REG_SET
1804 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
1808 CLEAR_REG_SET (&pseudos_counted
);
1811 /* Vector of reload-numbers showing the order in which the reloads should
1813 static short reload_order
[MAX_RELOADS
];
1815 /* This is used to keep track of the spill regs used in one insn. */
1816 static HARD_REG_SET used_spill_regs_local
;
1818 /* We decided to spill hard register SPILLED, which has a size of
1819 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1820 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1821 update SPILL_COST/SPILL_ADD_COST. */
1824 count_spilled_pseudo (int spilled
, int spilled_nregs
, int reg
)
1826 int freq
= REG_FREQ (reg
);
1827 int r
= reg_renumber
[reg
];
1830 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1831 if (ira_conflicts_p
&& r
< 0)
1834 gcc_assert (r
>= 0);
1836 nregs
= hard_regno_nregs
[r
][PSEUDO_REGNO_MODE (reg
)];
1838 if (REGNO_REG_SET_P (&spilled_pseudos
, reg
)
1839 || spilled
+ spilled_nregs
<= r
|| r
+ nregs
<= spilled
)
1842 SET_REGNO_REG_SET (&spilled_pseudos
, reg
);
1844 spill_add_cost
[r
] -= freq
;
1847 hard_regno_to_pseudo_regno
[r
+ nregs
] = -1;
1848 spill_cost
[r
+ nregs
] -= freq
;
1852 /* Find reload register to use for reload number ORDER. */
1855 find_reg (struct insn_chain
*chain
, int order
)
1857 int rnum
= reload_order
[order
];
1858 struct reload
*rl
= rld
+ rnum
;
1859 int best_cost
= INT_MAX
;
1861 unsigned int i
, j
, n
;
1863 HARD_REG_SET not_usable
;
1864 HARD_REG_SET used_by_other_reload
;
1865 reg_set_iterator rsi
;
1866 static int regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1867 static int best_regno_pseudo_regs
[FIRST_PSEUDO_REGISTER
];
1869 COPY_HARD_REG_SET (not_usable
, bad_spill_regs
);
1870 IOR_HARD_REG_SET (not_usable
, bad_spill_regs_global
);
1871 IOR_COMPL_HARD_REG_SET (not_usable
, reg_class_contents
[rl
->rclass
]);
1873 CLEAR_HARD_REG_SET (used_by_other_reload
);
1874 for (k
= 0; k
< order
; k
++)
1876 int other
= reload_order
[k
];
1878 if (rld
[other
].regno
>= 0 && reloads_conflict (other
, rnum
))
1879 for (j
= 0; j
< rld
[other
].nregs
; j
++)
1880 SET_HARD_REG_BIT (used_by_other_reload
, rld
[other
].regno
+ j
);
1883 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1885 #ifdef REG_ALLOC_ORDER
1886 unsigned int regno
= reg_alloc_order
[i
];
1888 unsigned int regno
= i
;
1891 if (! TEST_HARD_REG_BIT (not_usable
, regno
)
1892 && ! TEST_HARD_REG_BIT (used_by_other_reload
, regno
)
1893 && HARD_REGNO_MODE_OK (regno
, rl
->mode
))
1895 int this_cost
= spill_cost
[regno
];
1897 unsigned int this_nregs
= hard_regno_nregs
[regno
][rl
->mode
];
1899 for (j
= 1; j
< this_nregs
; j
++)
1901 this_cost
+= spill_add_cost
[regno
+ j
];
1902 if ((TEST_HARD_REG_BIT (not_usable
, regno
+ j
))
1903 || TEST_HARD_REG_BIT (used_by_other_reload
, regno
+ j
))
1909 if (ira_conflicts_p
)
1911 /* Ask IRA to find a better pseudo-register for
1913 for (n
= j
= 0; j
< this_nregs
; j
++)
1915 int r
= hard_regno_to_pseudo_regno
[regno
+ j
];
1919 if (n
== 0 || regno_pseudo_regs
[n
- 1] != r
)
1920 regno_pseudo_regs
[n
++] = r
;
1922 regno_pseudo_regs
[n
++] = -1;
1924 || ira_better_spill_reload_regno_p (regno_pseudo_regs
,
1925 best_regno_pseudo_regs
,
1932 best_regno_pseudo_regs
[j
] = regno_pseudo_regs
[j
];
1933 if (regno_pseudo_regs
[j
] < 0)
1940 if (rl
->in
&& REG_P (rl
->in
) && REGNO (rl
->in
) == regno
)
1942 if (rl
->out
&& REG_P (rl
->out
) && REGNO (rl
->out
) == regno
)
1944 if (this_cost
< best_cost
1945 /* Among registers with equal cost, prefer caller-saved ones, or
1946 use REG_ALLOC_ORDER if it is defined. */
1947 || (this_cost
== best_cost
1948 #ifdef REG_ALLOC_ORDER
1949 && (inv_reg_alloc_order
[regno
]
1950 < inv_reg_alloc_order
[best_reg
])
1952 && call_used_regs
[regno
]
1953 && ! call_used_regs
[best_reg
]
1958 best_cost
= this_cost
;
1966 fprintf (dump_file
, "Using reg %d for reload %d\n", best_reg
, rnum
);
1968 rl
->nregs
= hard_regno_nregs
[best_reg
][rl
->mode
];
1969 rl
->regno
= best_reg
;
1971 EXECUTE_IF_SET_IN_REG_SET
1972 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1974 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1977 EXECUTE_IF_SET_IN_REG_SET
1978 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, j
, rsi
)
1980 count_spilled_pseudo (best_reg
, rl
->nregs
, j
);
1983 for (i
= 0; i
< rl
->nregs
; i
++)
1985 gcc_assert (spill_cost
[best_reg
+ i
] == 0);
1986 gcc_assert (spill_add_cost
[best_reg
+ i
] == 0);
1987 gcc_assert (hard_regno_to_pseudo_regno
[best_reg
+ i
] == -1);
1988 SET_HARD_REG_BIT (used_spill_regs_local
, best_reg
+ i
);
1993 /* Find more reload regs to satisfy the remaining need of an insn, which
1995 Do it by ascending class number, since otherwise a reg
1996 might be spilled for a big class and might fail to count
1997 for a smaller class even though it belongs to that class. */
2000 find_reload_regs (struct insn_chain
*chain
)
2004 /* In order to be certain of getting the registers we need,
2005 we must sort the reloads into order of increasing register class.
2006 Then our grabbing of reload registers will parallel the process
2007 that provided the reload registers. */
2008 for (i
= 0; i
< chain
->n_reloads
; i
++)
2010 /* Show whether this reload already has a hard reg. */
2011 if (chain
->rld
[i
].reg_rtx
)
2013 int regno
= REGNO (chain
->rld
[i
].reg_rtx
);
2014 chain
->rld
[i
].regno
= regno
;
2016 = hard_regno_nregs
[regno
][GET_MODE (chain
->rld
[i
].reg_rtx
)];
2019 chain
->rld
[i
].regno
= -1;
2020 reload_order
[i
] = i
;
2023 n_reloads
= chain
->n_reloads
;
2024 memcpy (rld
, chain
->rld
, n_reloads
* sizeof (struct reload
));
2026 CLEAR_HARD_REG_SET (used_spill_regs_local
);
2029 fprintf (dump_file
, "Spilling for insn %d.\n", INSN_UID (chain
->insn
));
2031 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
2033 /* Compute the order of preference for hard registers to spill. */
2035 order_regs_for_reload (chain
);
2037 for (i
= 0; i
< n_reloads
; i
++)
2039 int r
= reload_order
[i
];
2041 /* Ignore reloads that got marked inoperative. */
2042 if ((rld
[r
].out
!= 0 || rld
[r
].in
!= 0 || rld
[r
].secondary_p
)
2043 && ! rld
[r
].optional
2044 && rld
[r
].regno
== -1)
2045 if (! find_reg (chain
, i
))
2048 fprintf (dump_file
, "reload failure for reload %d\n", r
);
2049 spill_failure (chain
->insn
, rld
[r
].rclass
);
2055 COPY_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs_local
);
2056 IOR_HARD_REG_SET (used_spill_regs
, used_spill_regs_local
);
2058 memcpy (chain
->rld
, rld
, n_reloads
* sizeof (struct reload
));
2062 select_reload_regs (void)
2064 struct insn_chain
*chain
;
2066 /* Try to satisfy the needs for each insn. */
2067 for (chain
= insns_need_reload
; chain
!= 0;
2068 chain
= chain
->next_need_reload
)
2069 find_reload_regs (chain
);
2072 /* Delete all insns that were inserted by emit_caller_save_insns during
2075 delete_caller_save_insns (void)
2077 struct insn_chain
*c
= reload_insn_chain
;
2081 while (c
!= 0 && c
->is_caller_save_insn
)
2083 struct insn_chain
*next
= c
->next
;
2084 rtx_insn
*insn
= c
->insn
;
2086 if (c
== reload_insn_chain
)
2087 reload_insn_chain
= next
;
2091 next
->prev
= c
->prev
;
2093 c
->prev
->next
= next
;
2094 c
->next
= unused_insn_chains
;
2095 unused_insn_chains
= c
;
2103 /* Handle the failure to find a register to spill.
2104 INSN should be one of the insns which needed this particular spill reg. */
2107 spill_failure (rtx_insn
*insn
, enum reg_class rclass
)
2109 if (asm_noperands (PATTERN (insn
)) >= 0)
2110 error_for_asm (insn
, "can%'t find a register in class %qs while "
2111 "reloading %<asm%>",
2112 reg_class_names
[rclass
]);
2115 error ("unable to find a register to spill in class %qs",
2116 reg_class_names
[rclass
]);
2120 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
2121 debug_reload_to_stream (dump_file
);
2123 fatal_insn ("this is the insn:", insn
);
2127 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2128 data that is dead in INSN. */
2131 delete_dead_insn (rtx_insn
*insn
)
2133 rtx_insn
*prev
= prev_active_insn (insn
);
2136 /* If the previous insn sets a register that dies in our insn make
2137 a note that we want to run DCE immediately after reload.
2139 We used to delete the previous insn & recurse, but that's wrong for
2140 block local equivalences. Instead of trying to figure out the exact
2141 circumstances where we can delete the potentially dead insns, just
2142 let DCE do the job. */
2143 if (prev
&& BLOCK_FOR_INSN (prev
) == BLOCK_FOR_INSN (insn
)
2144 && GET_CODE (PATTERN (prev
)) == SET
2145 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
2146 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
2147 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
2148 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
2151 SET_INSN_DELETED (insn
);
2154 /* Modify the home of pseudo-reg I.
2155 The new home is present in reg_renumber[I].
2157 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2158 or it may be -1, meaning there is none or it is not relevant.
2159 This is used so that all pseudos spilled from a given hard reg
2160 can share one stack slot. */
2163 alter_reg (int i
, int from_reg
, bool dont_share_p
)
2165 /* When outputting an inline function, this can happen
2166 for a reg that isn't actually used. */
2167 if (regno_reg_rtx
[i
] == 0)
2170 /* If the reg got changed to a MEM at rtl-generation time,
2172 if (!REG_P (regno_reg_rtx
[i
]))
2175 /* Modify the reg-rtx to contain the new hard reg
2176 number or else to contain its pseudo reg number. */
2177 SET_REGNO (regno_reg_rtx
[i
],
2178 reg_renumber
[i
] >= 0 ? reg_renumber
[i
] : i
);
2180 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2181 allocate a stack slot for it. */
2183 if (reg_renumber
[i
] < 0
2184 && REG_N_REFS (i
) > 0
2185 && reg_equiv_constant (i
) == 0
2186 && (reg_equiv_invariant (i
) == 0
2187 || reg_equiv_init (i
) == 0)
2188 && reg_equiv_memory_loc (i
) == 0)
2191 machine_mode mode
= GET_MODE (regno_reg_rtx
[i
]);
2192 unsigned int inherent_size
= PSEUDO_REGNO_BYTES (i
);
2193 unsigned int inherent_align
= GET_MODE_ALIGNMENT (mode
);
2194 unsigned int total_size
= MAX (inherent_size
, reg_max_ref_width
[i
]);
2195 unsigned int min_align
= reg_max_ref_width
[i
] * BITS_PER_UNIT
;
2198 something_was_spilled
= true;
2200 if (ira_conflicts_p
)
2202 /* Mark the spill for IRA. */
2203 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
2205 x
= ira_reuse_stack_slot (i
, inherent_size
, total_size
);
2211 /* Each pseudo reg has an inherent size which comes from its own mode,
2212 and a total size which provides room for paradoxical subregs
2213 which refer to the pseudo reg in wider modes.
2215 We can use a slot already allocated if it provides both
2216 enough inherent space and enough total space.
2217 Otherwise, we allocate a new slot, making sure that it has no less
2218 inherent space, and no less total space, then the previous slot. */
2219 else if (from_reg
== -1 || (!dont_share_p
&& ira_conflicts_p
))
2223 /* No known place to spill from => no slot to reuse. */
2224 x
= assign_stack_local (mode
, total_size
,
2225 min_align
> inherent_align
2226 || total_size
> inherent_size
? -1 : 0);
2230 /* Cancel the big-endian correction done in assign_stack_local.
2231 Get the address of the beginning of the slot. This is so we
2232 can do a big-endian correction unconditionally below. */
2233 if (BYTES_BIG_ENDIAN
)
2235 adjust
= inherent_size
- total_size
;
2238 = adjust_address_nv (x
, mode_for_size (total_size
2244 if (! dont_share_p
&& ira_conflicts_p
)
2245 /* Inform IRA about allocation a new stack slot. */
2246 ira_mark_new_stack_slot (stack_slot
, i
, total_size
);
2249 /* Reuse a stack slot if possible. */
2250 else if (spill_stack_slot
[from_reg
] != 0
2251 && spill_stack_slot_width
[from_reg
] >= total_size
2252 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2254 && MEM_ALIGN (spill_stack_slot
[from_reg
]) >= min_align
)
2255 x
= spill_stack_slot
[from_reg
];
2257 /* Allocate a bigger slot. */
2260 /* Compute maximum size needed, both for inherent size
2261 and for total size. */
2264 if (spill_stack_slot
[from_reg
])
2266 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot
[from_reg
]))
2268 mode
= GET_MODE (spill_stack_slot
[from_reg
]);
2269 if (spill_stack_slot_width
[from_reg
] > total_size
)
2270 total_size
= spill_stack_slot_width
[from_reg
];
2271 if (MEM_ALIGN (spill_stack_slot
[from_reg
]) > min_align
)
2272 min_align
= MEM_ALIGN (spill_stack_slot
[from_reg
]);
2275 /* Make a slot with that size. */
2276 x
= assign_stack_local (mode
, total_size
,
2277 min_align
> inherent_align
2278 || total_size
> inherent_size
? -1 : 0);
2281 /* Cancel the big-endian correction done in assign_stack_local.
2282 Get the address of the beginning of the slot. This is so we
2283 can do a big-endian correction unconditionally below. */
2284 if (BYTES_BIG_ENDIAN
)
2286 adjust
= GET_MODE_SIZE (mode
) - total_size
;
2289 = adjust_address_nv (x
, mode_for_size (total_size
2295 spill_stack_slot
[from_reg
] = stack_slot
;
2296 spill_stack_slot_width
[from_reg
] = total_size
;
2299 /* On a big endian machine, the "address" of the slot
2300 is the address of the low part that fits its inherent mode. */
2301 if (BYTES_BIG_ENDIAN
&& inherent_size
< total_size
)
2302 adjust
+= (total_size
- inherent_size
);
2304 /* If we have any adjustment to make, or if the stack slot is the
2305 wrong mode, make a new stack slot. */
2306 x
= adjust_address_nv (x
, GET_MODE (regno_reg_rtx
[i
]), adjust
);
2308 /* Set all of the memory attributes as appropriate for a spill. */
2309 set_mem_attrs_for_spill (x
);
2311 /* Save the stack slot for later. */
2312 reg_equiv_memory_loc (i
) = x
;
2316 /* Mark the slots in regs_ever_live for the hard regs used by
2317 pseudo-reg number REGNO, accessed in MODE. */
2320 mark_home_live_1 (int regno
, machine_mode mode
)
2324 i
= reg_renumber
[regno
];
2327 lim
= end_hard_regno (mode
, i
);
2329 df_set_regs_ever_live (i
++, true);
2332 /* Mark the slots in regs_ever_live for the hard regs
2333 used by pseudo-reg number REGNO. */
2336 mark_home_live (int regno
)
2338 if (reg_renumber
[regno
] >= 0)
2339 mark_home_live_1 (regno
, PSEUDO_REGNO_MODE (regno
));
2342 /* This function handles the tracking of elimination offsets around branches.
2344 X is a piece of RTL being scanned.
2346 INSN is the insn that it came from, if any.
2348 INITIAL_P is nonzero if we are to set the offset to be the initial
2349 offset and zero if we are setting the offset of the label to be the
2353 set_label_offsets (rtx x
, rtx_insn
*insn
, int initial_p
)
2355 enum rtx_code code
= GET_CODE (x
);
2358 struct elim_table
*p
;
2363 if (LABEL_REF_NONLOCAL_P (x
))
2366 x
= LABEL_REF_LABEL (x
);
2368 /* ... fall through ... */
2371 /* If we know nothing about this label, set the desired offsets. Note
2372 that this sets the offset at a label to be the offset before a label
2373 if we don't know anything about the label. This is not correct for
2374 the label after a BARRIER, but is the best guess we can make. If
2375 we guessed wrong, we will suppress an elimination that might have
2376 been possible had we been able to guess correctly. */
2378 if (! offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
])
2380 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2381 offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2382 = (initial_p
? reg_eliminate
[i
].initial_offset
2383 : reg_eliminate
[i
].offset
);
2384 offsets_known_at
[CODE_LABEL_NUMBER (x
) - first_label_num
] = 1;
2387 /* Otherwise, if this is the definition of a label and it is
2388 preceded by a BARRIER, set our offsets to the known offset of
2392 && (tem
= prev_nonnote_insn (insn
)) != 0
2394 set_offsets_for_label (insn
);
2396 /* If neither of the above cases is true, compare each offset
2397 with those previously recorded and suppress any eliminations
2398 where the offsets disagree. */
2400 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
2401 if (offsets_at
[CODE_LABEL_NUMBER (x
) - first_label_num
][i
]
2402 != (initial_p
? reg_eliminate
[i
].initial_offset
2403 : reg_eliminate
[i
].offset
))
2404 reg_eliminate
[i
].can_eliminate
= 0;
2408 case JUMP_TABLE_DATA
:
2409 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2413 set_label_offsets (PATTERN (insn
), insn
, initial_p
);
2415 /* ... fall through ... */
2419 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2420 to indirectly and hence must have all eliminations at their
2422 for (tem
= REG_NOTES (x
); tem
; tem
= XEXP (tem
, 1))
2423 if (REG_NOTE_KIND (tem
) == REG_LABEL_OPERAND
)
2424 set_label_offsets (XEXP (tem
, 0), insn
, 1);
2430 /* Each of the labels in the parallel or address vector must be
2431 at their initial offsets. We want the first field for PARALLEL
2432 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2434 for (i
= 0; i
< (unsigned) XVECLEN (x
, code
== ADDR_DIFF_VEC
); i
++)
2435 set_label_offsets (XVECEXP (x
, code
== ADDR_DIFF_VEC
, i
),
2440 /* We only care about setting PC. If the source is not RETURN,
2441 IF_THEN_ELSE, or a label, disable any eliminations not at
2442 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2443 isn't one of those possibilities. For branches to a label,
2444 call ourselves recursively.
2446 Note that this can disable elimination unnecessarily when we have
2447 a non-local goto since it will look like a non-constant jump to
2448 someplace in the current function. This isn't a significant
2449 problem since such jumps will normally be when all elimination
2450 pairs are back to their initial offsets. */
2452 if (SET_DEST (x
) != pc_rtx
)
2455 switch (GET_CODE (SET_SRC (x
)))
2462 set_label_offsets (SET_SRC (x
), insn
, initial_p
);
2466 tem
= XEXP (SET_SRC (x
), 1);
2467 if (GET_CODE (tem
) == LABEL_REF
)
2468 set_label_offsets (LABEL_REF_LABEL (tem
), insn
, initial_p
);
2469 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2472 tem
= XEXP (SET_SRC (x
), 2);
2473 if (GET_CODE (tem
) == LABEL_REF
)
2474 set_label_offsets (LABEL_REF_LABEL (tem
), insn
, initial_p
);
2475 else if (GET_CODE (tem
) != PC
&& GET_CODE (tem
) != RETURN
)
2483 /* If we reach here, all eliminations must be at their initial
2484 offset because we are doing a jump to a variable address. */
2485 for (p
= reg_eliminate
; p
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; p
++)
2486 if (p
->offset
!= p
->initial_offset
)
2487 p
->can_eliminate
= 0;
2495 /* This function examines every reg that occurs in X and adjusts the
2496 costs for its elimination which are gathered by IRA. INSN is the
2497 insn in which X occurs. We do not recurse into MEM expressions. */
2500 note_reg_elim_costly (const_rtx x
, rtx insn
)
2502 subrtx_iterator::array_type array
;
2503 FOR_EACH_SUBRTX (iter
, array
, x
, NONCONST
)
2505 const_rtx x
= *iter
;
2507 iter
.skip_subrtxes ();
2509 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
2510 && reg_equiv_init (REGNO (x
))
2511 && reg_equiv_invariant (REGNO (x
)))
2513 rtx t
= reg_equiv_invariant (REGNO (x
));
2514 rtx new_rtx
= eliminate_regs_1 (t
, Pmode
, insn
, true, true);
2515 int cost
= set_src_cost (new_rtx
, optimize_bb_for_speed_p (elim_bb
));
2516 int freq
= REG_FREQ_FROM_BB (elim_bb
);
2519 ira_adjust_equiv_reg_cost (REGNO (x
), -cost
* freq
);
2524 /* Scan X and replace any eliminable registers (such as fp) with a
2525 replacement (such as sp), plus an offset.
2527 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2528 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2529 MEM, we are allowed to replace a sum of a register and the constant zero
2530 with the register, which we cannot do outside a MEM. In addition, we need
2531 to record the fact that a register is referenced outside a MEM.
2533 If INSN is an insn, it is the insn containing X. If we replace a REG
2534 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2535 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2536 the REG is being modified.
2538 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2539 That's used when we eliminate in expressions stored in notes.
2540 This means, do not set ref_outside_mem even if the reference
2543 If FOR_COSTS is true, we are being called before reload in order to
2544 estimate the costs of keeping registers with an equivalence unallocated.
2546 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2547 replacements done assuming all offsets are at their initial values. If
2548 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2549 encounter, return the actual location so that find_reloads will do
2550 the proper thing. */
2553 eliminate_regs_1 (rtx x
, machine_mode mem_mode
, rtx insn
,
2554 bool may_use_invariant
, bool for_costs
)
2556 enum rtx_code code
= GET_CODE (x
);
2557 struct elim_table
*ep
;
2564 if (! current_function_decl
)
2584 /* First handle the case where we encounter a bare register that
2585 is eliminable. Replace it with a PLUS. */
2586 if (regno
< FIRST_PSEUDO_REGISTER
)
2588 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2590 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
2591 return plus_constant (Pmode
, ep
->to_rtx
, ep
->previous_offset
);
2594 else if (reg_renumber
&& reg_renumber
[regno
] < 0
2596 && reg_equiv_invariant (regno
))
2598 if (may_use_invariant
|| (insn
&& DEBUG_INSN_P (insn
)))
2599 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno
)),
2600 mem_mode
, insn
, true, for_costs
);
2601 /* There exists at least one use of REGNO that cannot be
2602 eliminated. Prevent the defining insn from being deleted. */
2603 reg_equiv_init (regno
) = NULL
;
2605 alter_reg (regno
, -1, true);
2609 /* You might think handling MINUS in a manner similar to PLUS is a
2610 good idea. It is not. It has been tried multiple times and every
2611 time the change has had to have been reverted.
2613 Other parts of reload know a PLUS is special (gen_reload for example)
2614 and require special code to handle code a reloaded PLUS operand.
2616 Also consider backends where the flags register is clobbered by a
2617 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2618 lea instruction comes to mind). If we try to reload a MINUS, we
2619 may kill the flags register that was holding a useful value.
2621 So, please before trying to handle MINUS, consider reload as a
2622 whole instead of this little section as well as the backend issues. */
2624 /* If this is the sum of an eliminable register and a constant, rework
2626 if (REG_P (XEXP (x
, 0))
2627 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2628 && CONSTANT_P (XEXP (x
, 1)))
2630 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2632 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2634 /* The only time we want to replace a PLUS with a REG (this
2635 occurs when the constant operand of the PLUS is the negative
2636 of the offset) is when we are inside a MEM. We won't want
2637 to do so at other times because that would change the
2638 structure of the insn in a way that reload can't handle.
2639 We special-case the commonest situation in
2640 eliminate_regs_in_insn, so just replace a PLUS with a
2641 PLUS here, unless inside a MEM. */
2642 if (mem_mode
!= 0 && CONST_INT_P (XEXP (x
, 1))
2643 && INTVAL (XEXP (x
, 1)) == - ep
->previous_offset
)
2646 return gen_rtx_PLUS (Pmode
, ep
->to_rtx
,
2647 plus_constant (Pmode
, XEXP (x
, 1),
2648 ep
->previous_offset
));
2651 /* If the register is not eliminable, we are done since the other
2652 operand is a constant. */
2656 /* If this is part of an address, we want to bring any constant to the
2657 outermost PLUS. We will do this by doing register replacement in
2658 our operands and seeing if a constant shows up in one of them.
2660 Note that there is no risk of modifying the structure of the insn,
2661 since we only get called for its operands, thus we are either
2662 modifying the address inside a MEM, or something like an address
2663 operand of a load-address insn. */
2666 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2668 rtx new1
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2671 if (reg_renumber
&& (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1)))
2673 /* If one side is a PLUS and the other side is a pseudo that
2674 didn't get a hard register but has a reg_equiv_constant,
2675 we must replace the constant here since it may no longer
2676 be in the position of any operand. */
2677 if (GET_CODE (new0
) == PLUS
&& REG_P (new1
)
2678 && REGNO (new1
) >= FIRST_PSEUDO_REGISTER
2679 && reg_renumber
[REGNO (new1
)] < 0
2681 && reg_equiv_constant (REGNO (new1
)) != 0)
2682 new1
= reg_equiv_constant (REGNO (new1
));
2683 else if (GET_CODE (new1
) == PLUS
&& REG_P (new0
)
2684 && REGNO (new0
) >= FIRST_PSEUDO_REGISTER
2685 && reg_renumber
[REGNO (new0
)] < 0
2686 && reg_equiv_constant (REGNO (new0
)) != 0)
2687 new0
= reg_equiv_constant (REGNO (new0
));
2689 new_rtx
= form_sum (GET_MODE (x
), new0
, new1
);
2691 /* As above, if we are not inside a MEM we do not want to
2692 turn a PLUS into something else. We might try to do so here
2693 for an addition of 0 if we aren't optimizing. */
2694 if (! mem_mode
&& GET_CODE (new_rtx
) != PLUS
)
2695 return gen_rtx_PLUS (GET_MODE (x
), new_rtx
, const0_rtx
);
2703 /* If this is the product of an eliminable register and a
2704 constant, apply the distribute law and move the constant out
2705 so that we have (plus (mult ..) ..). This is needed in order
2706 to keep load-address insns valid. This case is pathological.
2707 We ignore the possibility of overflow here. */
2708 if (REG_P (XEXP (x
, 0))
2709 && REGNO (XEXP (x
, 0)) < FIRST_PSEUDO_REGISTER
2710 && CONST_INT_P (XEXP (x
, 1)))
2711 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
2713 if (ep
->from_rtx
== XEXP (x
, 0) && ep
->can_eliminate
)
2716 /* Refs inside notes or in DEBUG_INSNs don't count for
2718 && ! (insn
!= 0 && (GET_CODE (insn
) == EXPR_LIST
2719 || GET_CODE (insn
) == INSN_LIST
2720 || DEBUG_INSN_P (insn
))))
2721 ep
->ref_outside_mem
= 1;
2724 plus_constant (Pmode
,
2725 gen_rtx_MULT (Pmode
, ep
->to_rtx
, XEXP (x
, 1)),
2726 ep
->previous_offset
* INTVAL (XEXP (x
, 1)));
2729 /* ... fall through ... */
2733 /* See comments before PLUS about handling MINUS. */
2735 case DIV
: case UDIV
:
2736 case MOD
: case UMOD
:
2737 case AND
: case IOR
: case XOR
:
2738 case ROTATERT
: case ROTATE
:
2739 case ASHIFTRT
: case LSHIFTRT
: case ASHIFT
:
2741 case GE
: case GT
: case GEU
: case GTU
:
2742 case LE
: case LT
: case LEU
: case LTU
:
2744 rtx new0
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2746 rtx new1
= XEXP (x
, 1)
2747 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, false,
2750 if (new0
!= XEXP (x
, 0) || new1
!= XEXP (x
, 1))
2751 return gen_rtx_fmt_ee (code
, GET_MODE (x
), new0
, new1
);
2756 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2759 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, true,
2761 if (new_rtx
!= XEXP (x
, 0))
2763 /* If this is a REG_DEAD note, it is not valid anymore.
2764 Using the eliminated version could result in creating a
2765 REG_DEAD note for the stack or frame pointer. */
2766 if (REG_NOTE_KIND (x
) == REG_DEAD
)
2768 ? eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2772 x
= alloc_reg_note (REG_NOTE_KIND (x
), new_rtx
, XEXP (x
, 1));
2776 /* ... fall through ... */
2780 /* Now do eliminations in the rest of the chain. If this was
2781 an EXPR_LIST, this might result in allocating more memory than is
2782 strictly needed, but it simplifies the code. */
2785 new_rtx
= eliminate_regs_1 (XEXP (x
, 1), mem_mode
, insn
, true,
2787 if (new_rtx
!= XEXP (x
, 1))
2789 gen_rtx_fmt_ee (GET_CODE (x
), GET_MODE (x
), XEXP (x
, 0), new_rtx
);
2797 /* We do not support elimination of a register that is modified.
2798 elimination_effects has already make sure that this does not
2804 /* We do not support elimination of a register that is modified.
2805 elimination_effects has already make sure that this does not
2806 happen. The only remaining case we need to consider here is
2807 that the increment value may be an eliminable register. */
2808 if (GET_CODE (XEXP (x
, 1)) == PLUS
2809 && XEXP (XEXP (x
, 1), 0) == XEXP (x
, 0))
2811 rtx new_rtx
= eliminate_regs_1 (XEXP (XEXP (x
, 1), 1), mem_mode
,
2812 insn
, true, for_costs
);
2814 if (new_rtx
!= XEXP (XEXP (x
, 1), 1))
2815 return gen_rtx_fmt_ee (code
, GET_MODE (x
), XEXP (x
, 0),
2816 gen_rtx_PLUS (GET_MODE (x
),
2817 XEXP (x
, 0), new_rtx
));
2821 case STRICT_LOW_PART
:
2823 case SIGN_EXTEND
: case ZERO_EXTEND
:
2824 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
2825 case FLOAT
: case FIX
:
2826 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
2835 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), mem_mode
, insn
, false,
2837 if (new_rtx
!= XEXP (x
, 0))
2838 return gen_rtx_fmt_e (code
, GET_MODE (x
), new_rtx
);
2842 /* Similar to above processing, but preserve SUBREG_BYTE.
2843 Convert (subreg (mem)) to (mem) if not paradoxical.
2844 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2845 pseudo didn't get a hard reg, we must replace this with the
2846 eliminated version of the memory location because push_reload
2847 may do the replacement in certain circumstances. */
2848 if (REG_P (SUBREG_REG (x
))
2849 && !paradoxical_subreg_p (x
)
2851 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
2853 new_rtx
= SUBREG_REG (x
);
2856 new_rtx
= eliminate_regs_1 (SUBREG_REG (x
), mem_mode
, insn
, false, for_costs
);
2858 if (new_rtx
!= SUBREG_REG (x
))
2860 int x_size
= GET_MODE_SIZE (GET_MODE (x
));
2861 int new_size
= GET_MODE_SIZE (GET_MODE (new_rtx
));
2864 && ((x_size
< new_size
2865 #ifdef WORD_REGISTER_OPERATIONS
2866 /* On these machines, combine can create rtl of the form
2867 (set (subreg:m1 (reg:m2 R) 0) ...)
2868 where m1 < m2, and expects something interesting to
2869 happen to the entire word. Moreover, it will use the
2870 (reg:m2 R) later, expecting all bits to be preserved.
2871 So if the number of words is the same, preserve the
2872 subreg so that push_reload can see it. */
2873 && ! ((x_size
- 1) / UNITS_PER_WORD
2874 == (new_size
-1 ) / UNITS_PER_WORD
)
2877 || x_size
== new_size
)
2879 return adjust_address_nv (new_rtx
, GET_MODE (x
), SUBREG_BYTE (x
));
2881 return gen_rtx_SUBREG (GET_MODE (x
), new_rtx
, SUBREG_BYTE (x
));
2887 /* Our only special processing is to pass the mode of the MEM to our
2888 recursive call and copy the flags. While we are here, handle this
2889 case more efficiently. */
2891 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), GET_MODE (x
), insn
, true,
2894 && memory_address_p (GET_MODE (x
), XEXP (x
, 0))
2895 && !memory_address_p (GET_MODE (x
), new_rtx
))
2896 note_reg_elim_costly (XEXP (x
, 0), insn
);
2898 return replace_equiv_address_nv (x
, new_rtx
);
2901 /* Handle insn_list USE that a call to a pure function may generate. */
2902 new_rtx
= eliminate_regs_1 (XEXP (x
, 0), VOIDmode
, insn
, false,
2904 if (new_rtx
!= XEXP (x
, 0))
2905 return gen_rtx_USE (GET_MODE (x
), new_rtx
);
2910 gcc_assert (insn
&& DEBUG_INSN_P (insn
));
2920 /* Process each of our operands recursively. If any have changed, make a
2922 fmt
= GET_RTX_FORMAT (code
);
2923 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
2927 new_rtx
= eliminate_regs_1 (XEXP (x
, i
), mem_mode
, insn
, false,
2929 if (new_rtx
!= XEXP (x
, i
) && ! copied
)
2931 x
= shallow_copy_rtx (x
);
2934 XEXP (x
, i
) = new_rtx
;
2936 else if (*fmt
== 'E')
2939 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
2941 new_rtx
= eliminate_regs_1 (XVECEXP (x
, i
, j
), mem_mode
, insn
, false,
2943 if (new_rtx
!= XVECEXP (x
, i
, j
) && ! copied_vec
)
2945 rtvec new_v
= gen_rtvec_v (XVECLEN (x
, i
),
2949 x
= shallow_copy_rtx (x
);
2952 XVEC (x
, i
) = new_v
;
2955 XVECEXP (x
, i
, j
) = new_rtx
;
2964 eliminate_regs (rtx x
, machine_mode mem_mode
, rtx insn
)
2966 if (reg_eliminate
== NULL
)
2968 gcc_assert (targetm
.no_register_allocation
);
2971 return eliminate_regs_1 (x
, mem_mode
, insn
, false, false);
2974 /* Scan rtx X for modifications of elimination target registers. Update
2975 the table of eliminables to reflect the changed state. MEM_MODE is
2976 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2979 elimination_effects (rtx x
, machine_mode mem_mode
)
2981 enum rtx_code code
= GET_CODE (x
);
2982 struct elim_table
*ep
;
3004 /* First handle the case where we encounter a bare register that
3005 is eliminable. Replace it with a PLUS. */
3006 if (regno
< FIRST_PSEUDO_REGISTER
)
3008 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3010 if (ep
->from_rtx
== x
&& ep
->can_eliminate
)
3013 ep
->ref_outside_mem
= 1;
3018 else if (reg_renumber
[regno
] < 0
3020 && reg_equiv_constant (regno
)
3021 && ! function_invariant_p (reg_equiv_constant (regno
)))
3022 elimination_effects (reg_equiv_constant (regno
), mem_mode
);
3031 /* If we modify the source of an elimination rule, disable it. */
3032 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3033 if (ep
->from_rtx
== XEXP (x
, 0))
3034 ep
->can_eliminate
= 0;
3036 /* If we modify the target of an elimination rule by adding a constant,
3037 update its offset. If we modify the target in any other way, we'll
3038 have to disable the rule as well. */
3039 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3040 if (ep
->to_rtx
== XEXP (x
, 0))
3042 int size
= GET_MODE_SIZE (mem_mode
);
3044 /* If more bytes than MEM_MODE are pushed, account for them. */
3045 #ifdef PUSH_ROUNDING
3046 if (ep
->to_rtx
== stack_pointer_rtx
)
3047 size
= PUSH_ROUNDING (size
);
3049 if (code
== PRE_DEC
|| code
== POST_DEC
)
3051 else if (code
== PRE_INC
|| code
== POST_INC
)
3053 else if (code
== PRE_MODIFY
|| code
== POST_MODIFY
)
3055 if (GET_CODE (XEXP (x
, 1)) == PLUS
3056 && XEXP (x
, 0) == XEXP (XEXP (x
, 1), 0)
3057 && CONST_INT_P (XEXP (XEXP (x
, 1), 1)))
3058 ep
->offset
-= INTVAL (XEXP (XEXP (x
, 1), 1));
3060 ep
->can_eliminate
= 0;
3064 /* These two aren't unary operators. */
3065 if (code
== POST_MODIFY
|| code
== PRE_MODIFY
)
3068 /* Fall through to generic unary operation case. */
3069 case STRICT_LOW_PART
:
3071 case SIGN_EXTEND
: case ZERO_EXTEND
:
3072 case TRUNCATE
: case FLOAT_EXTEND
: case FLOAT_TRUNCATE
:
3073 case FLOAT
: case FIX
:
3074 case UNSIGNED_FIX
: case UNSIGNED_FLOAT
:
3083 elimination_effects (XEXP (x
, 0), mem_mode
);
3087 if (REG_P (SUBREG_REG (x
))
3088 && (GET_MODE_SIZE (GET_MODE (x
))
3089 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
3091 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x
))) != 0)
3094 elimination_effects (SUBREG_REG (x
), mem_mode
);
3098 /* If using a register that is the source of an eliminate we still
3099 think can be performed, note it cannot be performed since we don't
3100 know how this register is used. */
3101 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3102 if (ep
->from_rtx
== XEXP (x
, 0))
3103 ep
->can_eliminate
= 0;
3105 elimination_effects (XEXP (x
, 0), mem_mode
);
3109 /* If clobbering a register that is the replacement register for an
3110 elimination we still think can be performed, note that it cannot
3111 be performed. Otherwise, we need not be concerned about it. */
3112 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3113 if (ep
->to_rtx
== XEXP (x
, 0))
3114 ep
->can_eliminate
= 0;
3116 elimination_effects (XEXP (x
, 0), mem_mode
);
3120 /* Check for setting a register that we know about. */
3121 if (REG_P (SET_DEST (x
)))
3123 /* See if this is setting the replacement register for an
3126 If DEST is the hard frame pointer, we do nothing because we
3127 assume that all assignments to the frame pointer are for
3128 non-local gotos and are being done at a time when they are valid
3129 and do not disturb anything else. Some machines want to
3130 eliminate a fake argument pointer (or even a fake frame pointer)
3131 with either the real frame or the stack pointer. Assignments to
3132 the hard frame pointer must not prevent this elimination. */
3134 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3136 if (ep
->to_rtx
== SET_DEST (x
)
3137 && SET_DEST (x
) != hard_frame_pointer_rtx
)
3139 /* If it is being incremented, adjust the offset. Otherwise,
3140 this elimination can't be done. */
3141 rtx src
= SET_SRC (x
);
3143 if (GET_CODE (src
) == PLUS
3144 && XEXP (src
, 0) == SET_DEST (x
)
3145 && CONST_INT_P (XEXP (src
, 1)))
3146 ep
->offset
-= INTVAL (XEXP (src
, 1));
3148 ep
->can_eliminate
= 0;
3152 elimination_effects (SET_DEST (x
), VOIDmode
);
3153 elimination_effects (SET_SRC (x
), VOIDmode
);
3157 /* Our only special processing is to pass the mode of the MEM to our
3159 elimination_effects (XEXP (x
, 0), GET_MODE (x
));
3166 fmt
= GET_RTX_FORMAT (code
);
3167 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3170 elimination_effects (XEXP (x
, i
), mem_mode
);
3171 else if (*fmt
== 'E')
3172 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3173 elimination_effects (XVECEXP (x
, i
, j
), mem_mode
);
3177 /* Descend through rtx X and verify that no references to eliminable registers
3178 remain. If any do remain, mark the involved register as not
3182 check_eliminable_occurrences (rtx x
)
3191 code
= GET_CODE (x
);
3193 if (code
== REG
&& REGNO (x
) < FIRST_PSEUDO_REGISTER
)
3195 struct elim_table
*ep
;
3197 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3198 if (ep
->from_rtx
== x
)
3199 ep
->can_eliminate
= 0;
3203 fmt
= GET_RTX_FORMAT (code
);
3204 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++, fmt
++)
3207 check_eliminable_occurrences (XEXP (x
, i
));
3208 else if (*fmt
== 'E')
3211 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
3212 check_eliminable_occurrences (XVECEXP (x
, i
, j
));
3217 /* Scan INSN and eliminate all eliminable registers in it.
3219 If REPLACE is nonzero, do the replacement destructively. Also
3220 delete the insn as dead it if it is setting an eliminable register.
3222 If REPLACE is zero, do all our allocations in reload_obstack.
3224 If no eliminations were done and this insn doesn't require any elimination
3225 processing (these are not identical conditions: it might be updating sp,
3226 but not referencing fp; this needs to be seen during reload_as_needed so
3227 that the offset between fp and sp can be taken into consideration), zero
3228 is returned. Otherwise, 1 is returned. */
3231 eliminate_regs_in_insn (rtx_insn
*insn
, int replace
)
3233 int icode
= recog_memoized (insn
);
3234 rtx old_body
= PATTERN (insn
);
3235 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3236 rtx old_set
= single_set (insn
);
3240 rtx substed_operand
[MAX_RECOG_OPERANDS
];
3241 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3242 struct elim_table
*ep
;
3243 rtx plus_src
, plus_cst_src
;
3245 if (! insn_is_asm
&& icode
< 0)
3247 gcc_assert (DEBUG_INSN_P (insn
)
3248 || GET_CODE (PATTERN (insn
)) == USE
3249 || GET_CODE (PATTERN (insn
)) == CLOBBER
3250 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3251 if (DEBUG_INSN_P (insn
))
3252 INSN_VAR_LOCATION_LOC (insn
)
3253 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn
), VOIDmode
, insn
);
3257 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3258 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3260 /* Check for setting an eliminable register. */
3261 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3262 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3264 /* If this is setting the frame pointer register to the
3265 hardware frame pointer register and this is an elimination
3266 that will be done (tested above), this insn is really
3267 adjusting the frame pointer downward to compensate for
3268 the adjustment done before a nonlocal goto. */
3269 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER
3270 && ep
->from
== FRAME_POINTER_REGNUM
3271 && ep
->to
== HARD_FRAME_POINTER_REGNUM
)
3273 rtx base
= SET_SRC (old_set
);
3274 rtx_insn
*base_insn
= insn
;
3275 HOST_WIDE_INT offset
= 0;
3277 while (base
!= ep
->to_rtx
)
3279 rtx_insn
*prev_insn
;
3282 if (GET_CODE (base
) == PLUS
3283 && CONST_INT_P (XEXP (base
, 1)))
3285 offset
+= INTVAL (XEXP (base
, 1));
3286 base
= XEXP (base
, 0);
3288 else if ((prev_insn
= prev_nonnote_insn (base_insn
)) != 0
3289 && (prev_set
= single_set (prev_insn
)) != 0
3290 && rtx_equal_p (SET_DEST (prev_set
), base
))
3292 base
= SET_SRC (prev_set
);
3293 base_insn
= prev_insn
;
3299 if (base
== ep
->to_rtx
)
3301 rtx src
= plus_constant (Pmode
, ep
->to_rtx
,
3302 offset
- ep
->offset
);
3304 new_body
= old_body
;
3307 new_body
= copy_insn (old_body
);
3308 if (REG_NOTES (insn
))
3309 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3311 PATTERN (insn
) = new_body
;
3312 old_set
= single_set (insn
);
3314 /* First see if this insn remains valid when we
3315 make the change. If not, keep the INSN_CODE
3316 the same and let reload fit it up. */
3317 validate_change (insn
, &SET_SRC (old_set
), src
, 1);
3318 validate_change (insn
, &SET_DEST (old_set
),
3320 if (! apply_change_group ())
3322 SET_SRC (old_set
) = src
;
3323 SET_DEST (old_set
) = ep
->to_rtx
;
3331 /* In this case this insn isn't serving a useful purpose. We
3332 will delete it in reload_as_needed once we know that this
3333 elimination is, in fact, being done.
3335 If REPLACE isn't set, we can't delete this insn, but needn't
3336 process it since it won't be used unless something changes. */
3339 delete_dead_insn (insn
);
3347 /* We allow one special case which happens to work on all machines we
3348 currently support: a single set with the source or a REG_EQUAL
3349 note being a PLUS of an eliminable register and a constant. */
3350 plus_src
= plus_cst_src
= 0;
3351 if (old_set
&& REG_P (SET_DEST (old_set
)))
3353 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3354 plus_src
= SET_SRC (old_set
);
3355 /* First see if the source is of the form (plus (...) CST). */
3357 && CONST_INT_P (XEXP (plus_src
, 1)))
3358 plus_cst_src
= plus_src
;
3359 else if (REG_P (SET_SRC (old_set
))
3362 /* Otherwise, see if we have a REG_EQUAL note of the form
3363 (plus (...) CST). */
3365 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3367 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3368 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3369 && GET_CODE (XEXP (links
, 0)) == PLUS
3370 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3372 plus_cst_src
= XEXP (links
, 0);
3378 /* Check that the first operand of the PLUS is a hard reg or
3379 the lowpart subreg of one. */
3382 rtx reg
= XEXP (plus_cst_src
, 0);
3383 if (GET_CODE (reg
) == SUBREG
&& subreg_lowpart_p (reg
))
3384 reg
= SUBREG_REG (reg
);
3386 if (!REG_P (reg
) || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
)
3392 rtx reg
= XEXP (plus_cst_src
, 0);
3393 HOST_WIDE_INT offset
= INTVAL (XEXP (plus_cst_src
, 1));
3395 if (GET_CODE (reg
) == SUBREG
)
3396 reg
= SUBREG_REG (reg
);
3398 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3399 if (ep
->from_rtx
== reg
&& ep
->can_eliminate
)
3401 rtx to_rtx
= ep
->to_rtx
;
3402 offset
+= ep
->offset
;
3403 offset
= trunc_int_for_mode (offset
, GET_MODE (plus_cst_src
));
3405 if (GET_CODE (XEXP (plus_cst_src
, 0)) == SUBREG
)
3406 to_rtx
= gen_lowpart (GET_MODE (XEXP (plus_cst_src
, 0)),
3408 /* If we have a nonzero offset, and the source is already
3409 a simple REG, the following transformation would
3410 increase the cost of the insn by replacing a simple REG
3411 with (plus (reg sp) CST). So try only when we already
3412 had a PLUS before. */
3413 if (offset
== 0 || plus_src
)
3415 rtx new_src
= plus_constant (GET_MODE (to_rtx
),
3418 new_body
= old_body
;
3421 new_body
= copy_insn (old_body
);
3422 if (REG_NOTES (insn
))
3423 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3425 PATTERN (insn
) = new_body
;
3426 old_set
= single_set (insn
);
3428 /* First see if this insn remains valid when we make the
3429 change. If not, try to replace the whole pattern with
3430 a simple set (this may help if the original insn was a
3431 PARALLEL that was only recognized as single_set due to
3432 REG_UNUSED notes). If this isn't valid either, keep
3433 the INSN_CODE the same and let reload fix it up. */
3434 if (!validate_change (insn
, &SET_SRC (old_set
), new_src
, 0))
3436 rtx new_pat
= gen_rtx_SET (SET_DEST (old_set
), new_src
);
3438 if (!validate_change (insn
, &PATTERN (insn
), new_pat
, 0))
3439 SET_SRC (old_set
) = new_src
;
3446 /* This can't have an effect on elimination offsets, so skip right
3452 /* Determine the effects of this insn on elimination offsets. */
3453 elimination_effects (old_body
, VOIDmode
);
3455 /* Eliminate all eliminable registers occurring in operands that
3456 can be handled by reload. */
3457 extract_insn (insn
);
3458 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3460 orig_operand
[i
] = recog_data
.operand
[i
];
3461 substed_operand
[i
] = recog_data
.operand
[i
];
3463 /* For an asm statement, every operand is eliminable. */
3464 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3466 bool is_set_src
, in_plus
;
3468 /* Check for setting a register that we know about. */
3469 if (recog_data
.operand_type
[i
] != OP_IN
3470 && REG_P (orig_operand
[i
]))
3472 /* If we are assigning to a register that can be eliminated, it
3473 must be as part of a PARALLEL, since the code above handles
3474 single SETs. We must indicate that we can no longer
3475 eliminate this reg. */
3476 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3478 if (ep
->from_rtx
== orig_operand
[i
])
3479 ep
->can_eliminate
= 0;
3482 /* Companion to the above plus substitution, we can allow
3483 invariants as the source of a plain move. */
3486 && recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3490 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3491 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3495 = eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3496 replace
? insn
: NULL_RTX
,
3497 is_set_src
|| in_plus
, false);
3498 if (substed_operand
[i
] != orig_operand
[i
])
3500 /* Terminate the search in check_eliminable_occurrences at
3502 *recog_data
.operand_loc
[i
] = 0;
3504 /* If an output operand changed from a REG to a MEM and INSN is an
3505 insn, write a CLOBBER insn. */
3506 if (recog_data
.operand_type
[i
] != OP_IN
3507 && REG_P (orig_operand
[i
])
3508 && MEM_P (substed_operand
[i
])
3510 emit_insn_after (gen_clobber (orig_operand
[i
]), insn
);
3514 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3515 *recog_data
.dup_loc
[i
]
3516 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3518 /* If any eliminable remain, they aren't eliminable anymore. */
3519 check_eliminable_occurrences (old_body
);
3521 /* Substitute the operands; the new values are in the substed_operand
3523 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3524 *recog_data
.operand_loc
[i
] = substed_operand
[i
];
3525 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3526 *recog_data
.dup_loc
[i
] = substed_operand
[(int) recog_data
.dup_num
[i
]];
3528 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3529 re-recognize the insn. We do this in case we had a simple addition
3530 but now can do this as a load-address. This saves an insn in this
3532 If re-recognition fails, the old insn code number will still be used,
3533 and some register operands may have changed into PLUS expressions.
3534 These will be handled by find_reloads by loading them into a register
3539 /* If we aren't replacing things permanently and we changed something,
3540 make another copy to ensure that all the RTL is new. Otherwise
3541 things can go wrong if find_reload swaps commutative operands
3542 and one is inside RTL that has been copied while the other is not. */
3543 new_body
= old_body
;
3546 new_body
= copy_insn (old_body
);
3547 if (REG_NOTES (insn
))
3548 REG_NOTES (insn
) = copy_insn_1 (REG_NOTES (insn
));
3550 PATTERN (insn
) = new_body
;
3552 /* If we had a move insn but now we don't, rerecognize it. This will
3553 cause spurious re-recognition if the old move had a PARALLEL since
3554 the new one still will, but we can't call single_set without
3555 having put NEW_BODY into the insn and the re-recognition won't
3556 hurt in this rare case. */
3557 /* ??? Why this huge if statement - why don't we just rerecognize the
3561 && ((REG_P (SET_SRC (old_set
))
3562 && (GET_CODE (new_body
) != SET
3563 || !REG_P (SET_SRC (new_body
))))
3564 /* If this was a load from or store to memory, compare
3565 the MEM in recog_data.operand to the one in the insn.
3566 If they are not equal, then rerecognize the insn. */
3568 && ((MEM_P (SET_SRC (old_set
))
3569 && SET_SRC (old_set
) != recog_data
.operand
[1])
3570 || (MEM_P (SET_DEST (old_set
))
3571 && SET_DEST (old_set
) != recog_data
.operand
[0])))
3572 /* If this was an add insn before, rerecognize. */
3573 || GET_CODE (SET_SRC (old_set
)) == PLUS
))
3575 int new_icode
= recog (PATTERN (insn
), insn
, 0);
3577 INSN_CODE (insn
) = new_icode
;
3581 /* Restore the old body. If there were any changes to it, we made a copy
3582 of it while the changes were still in place, so we'll correctly return
3583 a modified insn below. */
3586 /* Restore the old body. */
3587 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3588 /* Restoring a top-level match_parallel would clobber the new_body
3589 we installed in the insn. */
3590 if (recog_data
.operand_loc
[i
] != &PATTERN (insn
))
3591 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3592 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3593 *recog_data
.dup_loc
[i
] = orig_operand
[(int) recog_data
.dup_num
[i
]];
3596 /* Update all elimination pairs to reflect the status after the current
3597 insn. The changes we make were determined by the earlier call to
3598 elimination_effects.
3600 We also detect cases where register elimination cannot be done,
3601 namely, if a register would be both changed and referenced outside a MEM
3602 in the resulting insn since such an insn is often undefined and, even if
3603 not, we cannot know what meaning will be given to it. Note that it is
3604 valid to have a register used in an address in an insn that changes it
3605 (presumably with a pre- or post-increment or decrement).
3607 If anything changes, return nonzero. */
3609 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3611 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3612 ep
->can_eliminate
= 0;
3614 ep
->ref_outside_mem
= 0;
3616 if (ep
->previous_offset
!= ep
->offset
)
3621 /* If we changed something, perform elimination in REG_NOTES. This is
3622 needed even when REPLACE is zero because a REG_DEAD note might refer
3623 to a register that we eliminate and could cause a different number
3624 of spill registers to be needed in the final reload pass than in
3626 if (val
&& REG_NOTES (insn
) != 0)
3628 = eliminate_regs_1 (REG_NOTES (insn
), VOIDmode
, REG_NOTES (insn
), true,
3634 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3635 register allocator. INSN is the instruction we need to examine, we perform
3636 eliminations in its operands and record cases where eliminating a reg with
3637 an invariant equivalence would add extra cost. */
3640 elimination_costs_in_insn (rtx_insn
*insn
)
3642 int icode
= recog_memoized (insn
);
3643 rtx old_body
= PATTERN (insn
);
3644 int insn_is_asm
= asm_noperands (old_body
) >= 0;
3645 rtx old_set
= single_set (insn
);
3647 rtx orig_operand
[MAX_RECOG_OPERANDS
];
3648 rtx orig_dup
[MAX_RECOG_OPERANDS
];
3649 struct elim_table
*ep
;
3650 rtx plus_src
, plus_cst_src
;
3653 if (! insn_is_asm
&& icode
< 0)
3655 gcc_assert (DEBUG_INSN_P (insn
)
3656 || GET_CODE (PATTERN (insn
)) == USE
3657 || GET_CODE (PATTERN (insn
)) == CLOBBER
3658 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
3662 if (old_set
!= 0 && REG_P (SET_DEST (old_set
))
3663 && REGNO (SET_DEST (old_set
)) < FIRST_PSEUDO_REGISTER
)
3665 /* Check for setting an eliminable register. */
3666 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3667 if (ep
->from_rtx
== SET_DEST (old_set
) && ep
->can_eliminate
)
3671 /* We allow one special case which happens to work on all machines we
3672 currently support: a single set with the source or a REG_EQUAL
3673 note being a PLUS of an eliminable register and a constant. */
3674 plus_src
= plus_cst_src
= 0;
3676 if (old_set
&& REG_P (SET_DEST (old_set
)))
3679 if (GET_CODE (SET_SRC (old_set
)) == PLUS
)
3680 plus_src
= SET_SRC (old_set
);
3681 /* First see if the source is of the form (plus (...) CST). */
3683 && CONST_INT_P (XEXP (plus_src
, 1)))
3684 plus_cst_src
= plus_src
;
3685 else if (REG_P (SET_SRC (old_set
))
3688 /* Otherwise, see if we have a REG_EQUAL note of the form
3689 (plus (...) CST). */
3691 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
3693 if ((REG_NOTE_KIND (links
) == REG_EQUAL
3694 || REG_NOTE_KIND (links
) == REG_EQUIV
)
3695 && GET_CODE (XEXP (links
, 0)) == PLUS
3696 && CONST_INT_P (XEXP (XEXP (links
, 0), 1)))
3698 plus_cst_src
= XEXP (links
, 0);
3705 /* Determine the effects of this insn on elimination offsets. */
3706 elimination_effects (old_body
, VOIDmode
);
3708 /* Eliminate all eliminable registers occurring in operands that
3709 can be handled by reload. */
3710 extract_insn (insn
);
3711 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3712 orig_dup
[i
] = *recog_data
.dup_loc
[i
];
3714 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3716 orig_operand
[i
] = recog_data
.operand
[i
];
3718 /* For an asm statement, every operand is eliminable. */
3719 if (insn_is_asm
|| insn_data
[icode
].operand
[i
].eliminable
)
3721 bool is_set_src
, in_plus
;
3723 /* Check for setting a register that we know about. */
3724 if (recog_data
.operand_type
[i
] != OP_IN
3725 && REG_P (orig_operand
[i
]))
3727 /* If we are assigning to a register that can be eliminated, it
3728 must be as part of a PARALLEL, since the code above handles
3729 single SETs. We must indicate that we can no longer
3730 eliminate this reg. */
3731 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
];
3733 if (ep
->from_rtx
== orig_operand
[i
])
3734 ep
->can_eliminate
= 0;
3737 /* Companion to the above plus substitution, we can allow
3738 invariants as the source of a plain move. */
3740 if (old_set
&& recog_data
.operand_loc
[i
] == &SET_SRC (old_set
))
3742 if (is_set_src
&& !sets_reg_p
)
3743 note_reg_elim_costly (SET_SRC (old_set
), insn
);
3745 if (plus_src
&& sets_reg_p
3746 && (recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 0)
3747 || recog_data
.operand_loc
[i
] == &XEXP (plus_src
, 1)))
3750 eliminate_regs_1 (recog_data
.operand
[i
], VOIDmode
,
3752 is_set_src
|| in_plus
, true);
3753 /* Terminate the search in check_eliminable_occurrences at
3755 *recog_data
.operand_loc
[i
] = 0;
3759 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3760 *recog_data
.dup_loc
[i
]
3761 = *recog_data
.operand_loc
[(int) recog_data
.dup_num
[i
]];
3763 /* If any eliminable remain, they aren't eliminable anymore. */
3764 check_eliminable_occurrences (old_body
);
3766 /* Restore the old body. */
3767 for (i
= 0; i
< recog_data
.n_operands
; i
++)
3768 *recog_data
.operand_loc
[i
] = orig_operand
[i
];
3769 for (i
= 0; i
< recog_data
.n_dups
; i
++)
3770 *recog_data
.dup_loc
[i
] = orig_dup
[i
];
3772 /* Update all elimination pairs to reflect the status after the current
3773 insn. The changes we make were determined by the earlier call to
3774 elimination_effects. */
3776 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3778 if (ep
->previous_offset
!= ep
->offset
&& ep
->ref_outside_mem
)
3779 ep
->can_eliminate
= 0;
3781 ep
->ref_outside_mem
= 0;
3787 /* Loop through all elimination pairs.
3788 Recalculate the number not at initial offset.
3790 Compute the maximum offset (minimum offset if the stack does not
3791 grow downward) for each elimination pair. */
3794 update_eliminable_offsets (void)
3796 struct elim_table
*ep
;
3798 num_not_at_initial_offset
= 0;
3799 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3801 ep
->previous_offset
= ep
->offset
;
3802 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3803 num_not_at_initial_offset
++;
3807 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3808 replacement we currently believe is valid, mark it as not eliminable if X
3809 modifies DEST in any way other than by adding a constant integer to it.
3811 If DEST is the frame pointer, we do nothing because we assume that
3812 all assignments to the hard frame pointer are nonlocal gotos and are being
3813 done at a time when they are valid and do not disturb anything else.
3814 Some machines want to eliminate a fake argument pointer with either the
3815 frame or stack pointer. Assignments to the hard frame pointer must not
3816 prevent this elimination.
3818 Called via note_stores from reload before starting its passes to scan
3819 the insns of the function. */
3822 mark_not_eliminable (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
3826 /* A SUBREG of a hard register here is just changing its mode. We should
3827 not see a SUBREG of an eliminable hard register, but check just in
3829 if (GET_CODE (dest
) == SUBREG
)
3830 dest
= SUBREG_REG (dest
);
3832 if (dest
== hard_frame_pointer_rtx
)
3835 for (i
= 0; i
< NUM_ELIMINABLE_REGS
; i
++)
3836 if (reg_eliminate
[i
].can_eliminate
&& dest
== reg_eliminate
[i
].to_rtx
3837 && (GET_CODE (x
) != SET
3838 || GET_CODE (SET_SRC (x
)) != PLUS
3839 || XEXP (SET_SRC (x
), 0) != dest
3840 || !CONST_INT_P (XEXP (SET_SRC (x
), 1))))
3842 reg_eliminate
[i
].can_eliminate_previous
3843 = reg_eliminate
[i
].can_eliminate
= 0;
3848 /* Verify that the initial elimination offsets did not change since the
3849 last call to set_initial_elim_offsets. This is used to catch cases
3850 where something illegal happened during reload_as_needed that could
3851 cause incorrect code to be generated if we did not check for it. */
3854 verify_initial_elim_offsets (void)
3858 if (!num_eliminable
)
3861 #ifdef ELIMINABLE_REGS
3863 struct elim_table
*ep
;
3865 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3867 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, t
);
3868 if (t
!= ep
->initial_offset
)
3873 INITIAL_FRAME_POINTER_OFFSET (t
);
3874 if (t
!= reg_eliminate
[0].initial_offset
)
3881 /* Reset all offsets on eliminable registers to their initial values. */
3884 set_initial_elim_offsets (void)
3886 struct elim_table
*ep
= reg_eliminate
;
3888 #ifdef ELIMINABLE_REGS
3889 for (; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3891 INITIAL_ELIMINATION_OFFSET (ep
->from
, ep
->to
, ep
->initial_offset
);
3892 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3895 INITIAL_FRAME_POINTER_OFFSET (ep
->initial_offset
);
3896 ep
->previous_offset
= ep
->offset
= ep
->initial_offset
;
3899 num_not_at_initial_offset
= 0;
3902 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3905 set_initial_eh_label_offset (rtx label
)
3907 set_label_offsets (label
, NULL
, 1);
3910 /* Initialize the known label offsets.
3911 Set a known offset for each forced label to be at the initial offset
3912 of each elimination. We do this because we assume that all
3913 computed jumps occur from a location where each elimination is
3914 at its initial offset.
3915 For all other labels, show that we don't know the offsets. */
3918 set_initial_label_offsets (void)
3920 memset (offsets_known_at
, 0, num_labels
);
3922 for (rtx_insn_list
*x
= forced_labels
; x
; x
= x
->next ())
3924 set_label_offsets (x
->insn (), NULL
, 1);
3926 for (rtx_insn_list
*x
= nonlocal_goto_handler_labels
; x
; x
= x
->next ())
3928 set_label_offsets (x
->insn (), NULL
, 1);
3930 for_each_eh_label (set_initial_eh_label_offset
);
3933 /* Set all elimination offsets to the known values for the code label given
3937 set_offsets_for_label (rtx_insn
*insn
)
3940 int label_nr
= CODE_LABEL_NUMBER (insn
);
3941 struct elim_table
*ep
;
3943 num_not_at_initial_offset
= 0;
3944 for (i
= 0, ep
= reg_eliminate
; i
< NUM_ELIMINABLE_REGS
; ep
++, i
++)
3946 ep
->offset
= ep
->previous_offset
3947 = offsets_at
[label_nr
- first_label_num
][i
];
3948 if (ep
->can_eliminate
&& ep
->offset
!= ep
->initial_offset
)
3949 num_not_at_initial_offset
++;
3953 /* See if anything that happened changes which eliminations are valid.
3954 For example, on the SPARC, whether or not the frame pointer can
3955 be eliminated can depend on what registers have been used. We need
3956 not check some conditions again (such as flag_omit_frame_pointer)
3957 since they can't have changed. */
3960 update_eliminables (HARD_REG_SET
*pset
)
3962 int previous_frame_pointer_needed
= frame_pointer_needed
;
3963 struct elim_table
*ep
;
3965 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3966 if ((ep
->from
== HARD_FRAME_POINTER_REGNUM
3967 && targetm
.frame_pointer_required ())
3968 #ifdef ELIMINABLE_REGS
3969 || ! targetm
.can_eliminate (ep
->from
, ep
->to
)
3972 ep
->can_eliminate
= 0;
3974 /* Look for the case where we have discovered that we can't replace
3975 register A with register B and that means that we will now be
3976 trying to replace register A with register C. This means we can
3977 no longer replace register C with register B and we need to disable
3978 such an elimination, if it exists. This occurs often with A == ap,
3979 B == sp, and C == fp. */
3981 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
3983 struct elim_table
*op
;
3986 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
3988 /* Find the current elimination for ep->from, if there is a
3990 for (op
= reg_eliminate
;
3991 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
3992 if (op
->from
== ep
->from
&& op
->can_eliminate
)
3998 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
4000 for (op
= reg_eliminate
;
4001 op
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; op
++)
4002 if (op
->from
== new_to
&& op
->to
== ep
->to
)
4003 op
->can_eliminate
= 0;
4007 /* See if any registers that we thought we could eliminate the previous
4008 time are no longer eliminable. If so, something has changed and we
4009 must spill the register. Also, recompute the number of eliminable
4010 registers and see if the frame pointer is needed; it is if there is
4011 no elimination of the frame pointer that we can perform. */
4013 frame_pointer_needed
= 1;
4014 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4016 if (ep
->can_eliminate
4017 && ep
->from
== FRAME_POINTER_REGNUM
4018 && ep
->to
!= HARD_FRAME_POINTER_REGNUM
4019 && (! SUPPORTS_STACK_ALIGNMENT
4020 || ! crtl
->stack_realign_needed
))
4021 frame_pointer_needed
= 0;
4023 if (! ep
->can_eliminate
&& ep
->can_eliminate_previous
)
4025 ep
->can_eliminate_previous
= 0;
4026 SET_HARD_REG_BIT (*pset
, ep
->from
);
4031 /* If we didn't need a frame pointer last time, but we do now, spill
4032 the hard frame pointer. */
4033 if (frame_pointer_needed
&& ! previous_frame_pointer_needed
)
4034 SET_HARD_REG_BIT (*pset
, HARD_FRAME_POINTER_REGNUM
);
4037 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4038 Return true iff a register was spilled. */
4041 update_eliminables_and_spill (void)
4044 bool did_spill
= false;
4045 HARD_REG_SET to_spill
;
4046 CLEAR_HARD_REG_SET (to_spill
);
4047 update_eliminables (&to_spill
);
4048 AND_COMPL_HARD_REG_SET (used_spill_regs
, to_spill
);
4050 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4051 if (TEST_HARD_REG_BIT (to_spill
, i
))
4053 spill_hard_reg (i
, 1);
4056 /* Regardless of the state of spills, if we previously had
4057 a register that we thought we could eliminate, but now can
4058 not eliminate, we must run another pass.
4060 Consider pseudos which have an entry in reg_equiv_* which
4061 reference an eliminable register. We must make another pass
4062 to update reg_equiv_* so that we do not substitute in the
4063 old value from when we thought the elimination could be
4069 /* Return true if X is used as the target register of an elimination. */
4072 elimination_target_reg_p (rtx x
)
4074 struct elim_table
*ep
;
4076 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4077 if (ep
->to_rtx
== x
&& ep
->can_eliminate
)
4083 /* Initialize the table of registers to eliminate.
4084 Pre-condition: global flag frame_pointer_needed has been set before
4085 calling this function. */
4088 init_elim_table (void)
4090 struct elim_table
*ep
;
4091 #ifdef ELIMINABLE_REGS
4092 const struct elim_table_1
*ep1
;
4096 reg_eliminate
= XCNEWVEC (struct elim_table
, NUM_ELIMINABLE_REGS
);
4100 #ifdef ELIMINABLE_REGS
4101 for (ep
= reg_eliminate
, ep1
= reg_eliminate_1
;
4102 ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++, ep1
++)
4104 ep
->from
= ep1
->from
;
4106 ep
->can_eliminate
= ep
->can_eliminate_previous
4107 = (targetm
.can_eliminate (ep
->from
, ep
->to
)
4108 && ! (ep
->to
== STACK_POINTER_REGNUM
4109 && frame_pointer_needed
4110 && (! SUPPORTS_STACK_ALIGNMENT
4111 || ! stack_realign_fp
)));
4114 reg_eliminate
[0].from
= reg_eliminate_1
[0].from
;
4115 reg_eliminate
[0].to
= reg_eliminate_1
[0].to
;
4116 reg_eliminate
[0].can_eliminate
= reg_eliminate
[0].can_eliminate_previous
4117 = ! frame_pointer_needed
;
4120 /* Count the number of eliminable registers and build the FROM and TO
4121 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4122 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4123 We depend on this. */
4124 for (ep
= reg_eliminate
; ep
< ®_eliminate
[NUM_ELIMINABLE_REGS
]; ep
++)
4126 num_eliminable
+= ep
->can_eliminate
;
4127 ep
->from_rtx
= gen_rtx_REG (Pmode
, ep
->from
);
4128 ep
->to_rtx
= gen_rtx_REG (Pmode
, ep
->to
);
4132 /* Find all the pseudo registers that didn't get hard regs
4133 but do have known equivalent constants or memory slots.
4134 These include parameters (known equivalent to parameter slots)
4135 and cse'd or loop-moved constant memory addresses.
4137 Record constant equivalents in reg_equiv_constant
4138 so they will be substituted by find_reloads.
4139 Record memory equivalents in reg_mem_equiv so they can
4140 be substituted eventually by altering the REG-rtx's. */
4143 init_eliminable_invariants (rtx_insn
*first
, bool do_subregs
)
4150 reg_max_ref_width
= XCNEWVEC (unsigned int, max_regno
);
4152 reg_max_ref_width
= NULL
;
4154 num_eliminable_invariants
= 0;
4156 first_label_num
= get_first_label_num ();
4157 num_labels
= max_label_num () - first_label_num
;
4159 /* Allocate the tables used to store offset information at labels. */
4160 offsets_known_at
= XNEWVEC (char, num_labels
);
4161 offsets_at
= (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS
]) xmalloc (num_labels
* NUM_ELIMINABLE_REGS
* sizeof (HOST_WIDE_INT
));
4163 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4164 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4165 find largest such for each pseudo. FIRST is the head of the insn
4168 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
4170 rtx set
= single_set (insn
);
4172 /* We may introduce USEs that we want to remove at the end, so
4173 we'll mark them with QImode. Make sure there are no
4174 previously-marked insns left by say regmove. */
4175 if (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == USE
4176 && GET_MODE (insn
) != VOIDmode
)
4177 PUT_MODE (insn
, VOIDmode
);
4179 if (do_subregs
&& NONDEBUG_INSN_P (insn
))
4180 scan_paradoxical_subregs (PATTERN (insn
));
4182 if (set
!= 0 && REG_P (SET_DEST (set
)))
4184 rtx note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
4190 i
= REGNO (SET_DEST (set
));
4193 if (i
<= LAST_VIRTUAL_REGISTER
)
4196 /* If flag_pic and we have constant, verify it's legitimate. */
4198 || !flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
))
4200 /* It can happen that a REG_EQUIV note contains a MEM
4201 that is not a legitimate memory operand. As later
4202 stages of reload assume that all addresses found
4203 in the reg_equiv_* arrays were originally legitimate,
4204 we ignore such REG_EQUIV notes. */
4205 if (memory_operand (x
, VOIDmode
))
4207 /* Always unshare the equivalence, so we can
4208 substitute into this insn without touching the
4210 reg_equiv_memory_loc (i
) = copy_rtx (x
);
4212 else if (function_invariant_p (x
))
4216 mode
= GET_MODE (SET_DEST (set
));
4217 if (GET_CODE (x
) == PLUS
)
4219 /* This is PLUS of frame pointer and a constant,
4220 and might be shared. Unshare it. */
4221 reg_equiv_invariant (i
) = copy_rtx (x
);
4222 num_eliminable_invariants
++;
4224 else if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
4226 reg_equiv_invariant (i
) = x
;
4227 num_eliminable_invariants
++;
4229 else if (targetm
.legitimate_constant_p (mode
, x
))
4230 reg_equiv_constant (i
) = x
;
4233 reg_equiv_memory_loc (i
) = force_const_mem (mode
, x
);
4234 if (! reg_equiv_memory_loc (i
))
4235 reg_equiv_init (i
) = NULL
;
4240 reg_equiv_init (i
) = NULL
;
4245 reg_equiv_init (i
) = NULL
;
4250 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4251 if (reg_equiv_init (i
))
4253 fprintf (dump_file
, "init_insns for %u: ", i
);
4254 print_inline_rtx (dump_file
, reg_equiv_init (i
), 20);
4255 fprintf (dump_file
, "\n");
4259 /* Indicate that we no longer have known memory locations or constants.
4260 Free all data involved in tracking these. */
4263 free_reg_equiv (void)
4267 free (offsets_known_at
);
4270 offsets_known_at
= 0;
4272 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4273 if (reg_equiv_alt_mem_list (i
))
4274 free_EXPR_LIST_list (®_equiv_alt_mem_list (i
));
4275 vec_free (reg_equivs
);
4278 /* Kick all pseudos out of hard register REGNO.
4280 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4281 because we found we can't eliminate some register. In the case, no pseudos
4282 are allowed to be in the register, even if they are only in a block that
4283 doesn't require spill registers, unlike the case when we are spilling this
4284 hard reg to produce another spill register.
4286 Return nonzero if any pseudos needed to be kicked out. */
4289 spill_hard_reg (unsigned int regno
, int cant_eliminate
)
4295 SET_HARD_REG_BIT (bad_spill_regs_global
, regno
);
4296 df_set_regs_ever_live (regno
, true);
4299 /* Spill every pseudo reg that was allocated to this reg
4300 or to something that overlaps this reg. */
4302 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
4303 if (reg_renumber
[i
] >= 0
4304 && (unsigned int) reg_renumber
[i
] <= regno
4305 && end_hard_regno (PSEUDO_REGNO_MODE (i
), reg_renumber
[i
]) > regno
)
4306 SET_REGNO_REG_SET (&spilled_pseudos
, i
);
4309 /* After find_reload_regs has been run for all insn that need reloads,
4310 and/or spill_hard_regs was called, this function is used to actually
4311 spill pseudo registers and try to reallocate them. It also sets up the
4312 spill_regs array for use by choose_reload_regs. */
4315 finish_spills (int global
)
4317 struct insn_chain
*chain
;
4318 int something_changed
= 0;
4320 reg_set_iterator rsi
;
4322 /* Build the spill_regs array for the function. */
4323 /* If there are some registers still to eliminate and one of the spill regs
4324 wasn't ever used before, additional stack space may have to be
4325 allocated to store this register. Thus, we may have changed the offset
4326 between the stack and frame pointers, so mark that something has changed.
4328 One might think that we need only set VAL to 1 if this is a call-used
4329 register. However, the set of registers that must be saved by the
4330 prologue is not identical to the call-used set. For example, the
4331 register used by the call insn for the return PC is a call-used register,
4332 but must be saved by the prologue. */
4335 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
4336 if (TEST_HARD_REG_BIT (used_spill_regs
, i
))
4338 spill_reg_order
[i
] = n_spills
;
4339 spill_regs
[n_spills
++] = i
;
4340 if (num_eliminable
&& ! df_regs_ever_live_p (i
))
4341 something_changed
= 1;
4342 df_set_regs_ever_live (i
, true);
4345 spill_reg_order
[i
] = -1;
4347 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4348 if (! ira_conflicts_p
|| reg_renumber
[i
] >= 0)
4350 /* Record the current hard register the pseudo is allocated to
4351 in pseudo_previous_regs so we avoid reallocating it to the
4352 same hard reg in a later pass. */
4353 gcc_assert (reg_renumber
[i
] >= 0);
4355 SET_HARD_REG_BIT (pseudo_previous_regs
[i
], reg_renumber
[i
]);
4356 /* Mark it as no longer having a hard register home. */
4357 reg_renumber
[i
] = -1;
4358 if (ira_conflicts_p
)
4359 /* Inform IRA about the change. */
4360 ira_mark_allocation_change (i
);
4361 /* We will need to scan everything again. */
4362 something_changed
= 1;
4365 /* Retry global register allocation if possible. */
4366 if (global
&& ira_conflicts_p
)
4370 memset (pseudo_forbidden_regs
, 0, max_regno
* sizeof (HARD_REG_SET
));
4371 /* For every insn that needs reloads, set the registers used as spill
4372 regs in pseudo_forbidden_regs for every pseudo live across the
4374 for (chain
= insns_need_reload
; chain
; chain
= chain
->next_need_reload
)
4376 EXECUTE_IF_SET_IN_REG_SET
4377 (&chain
->live_throughout
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4379 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4380 chain
->used_spill_regs
);
4382 EXECUTE_IF_SET_IN_REG_SET
4383 (&chain
->dead_or_set
, FIRST_PSEUDO_REGISTER
, i
, rsi
)
4385 IOR_HARD_REG_SET (pseudo_forbidden_regs
[i
],
4386 chain
->used_spill_regs
);
4390 /* Retry allocating the pseudos spilled in IRA and the
4391 reload. For each reg, merge the various reg sets that
4392 indicate which hard regs can't be used, and call
4393 ira_reassign_pseudos. */
4394 for (n
= 0, i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned) max_regno
; i
++)
4395 if (reg_old_renumber
[i
] != reg_renumber
[i
])
4397 if (reg_renumber
[i
] < 0)
4398 temp_pseudo_reg_arr
[n
++] = i
;
4400 CLEAR_REGNO_REG_SET (&spilled_pseudos
, i
);
4402 if (ira_reassign_pseudos (temp_pseudo_reg_arr
, n
,
4403 bad_spill_regs_global
,
4404 pseudo_forbidden_regs
, pseudo_previous_regs
,
4406 something_changed
= 1;
4408 /* Fix up the register information in the insn chain.
4409 This involves deleting those of the spilled pseudos which did not get
4410 a new hard register home from the live_{before,after} sets. */
4411 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4413 HARD_REG_SET used_by_pseudos
;
4414 HARD_REG_SET used_by_pseudos2
;
4416 if (! ira_conflicts_p
)
4418 /* Don't do it for IRA because IRA and the reload still can
4419 assign hard registers to the spilled pseudos on next
4420 reload iterations. */
4421 AND_COMPL_REG_SET (&chain
->live_throughout
, &spilled_pseudos
);
4422 AND_COMPL_REG_SET (&chain
->dead_or_set
, &spilled_pseudos
);
4424 /* Mark any unallocated hard regs as available for spills. That
4425 makes inheritance work somewhat better. */
4426 if (chain
->need_reload
)
4428 REG_SET_TO_HARD_REG_SET (used_by_pseudos
, &chain
->live_throughout
);
4429 REG_SET_TO_HARD_REG_SET (used_by_pseudos2
, &chain
->dead_or_set
);
4430 IOR_HARD_REG_SET (used_by_pseudos
, used_by_pseudos2
);
4432 compute_use_by_pseudos (&used_by_pseudos
, &chain
->live_throughout
);
4433 compute_use_by_pseudos (&used_by_pseudos
, &chain
->dead_or_set
);
4434 /* Value of chain->used_spill_regs from previous iteration
4435 may be not included in the value calculated here because
4436 of possible removing caller-saves insns (see function
4437 delete_caller_save_insns. */
4438 COMPL_HARD_REG_SET (chain
->used_spill_regs
, used_by_pseudos
);
4439 AND_HARD_REG_SET (chain
->used_spill_regs
, used_spill_regs
);
4443 CLEAR_REG_SET (&changed_allocation_pseudos
);
4444 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4445 for (i
= FIRST_PSEUDO_REGISTER
; i
< (unsigned)max_regno
; i
++)
4447 int regno
= reg_renumber
[i
];
4448 if (reg_old_renumber
[i
] == regno
)
4451 SET_REGNO_REG_SET (&changed_allocation_pseudos
, i
);
4453 alter_reg (i
, reg_old_renumber
[i
], false);
4454 reg_old_renumber
[i
] = regno
;
4458 fprintf (dump_file
, " Register %d now on stack.\n\n", i
);
4460 fprintf (dump_file
, " Register %d now in %d.\n\n",
4461 i
, reg_renumber
[i
]);
4465 return something_changed
;
4468 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4471 scan_paradoxical_subregs (rtx x
)
4475 enum rtx_code code
= GET_CODE (x
);
4491 if (REG_P (SUBREG_REG (x
))
4492 && (GET_MODE_SIZE (GET_MODE (x
))
4493 > reg_max_ref_width
[REGNO (SUBREG_REG (x
))]))
4495 reg_max_ref_width
[REGNO (SUBREG_REG (x
))]
4496 = GET_MODE_SIZE (GET_MODE (x
));
4497 mark_home_live_1 (REGNO (SUBREG_REG (x
)), GET_MODE (x
));
4505 fmt
= GET_RTX_FORMAT (code
);
4506 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4509 scan_paradoxical_subregs (XEXP (x
, i
));
4510 else if (fmt
[i
] == 'E')
4513 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4514 scan_paradoxical_subregs (XVECEXP (x
, i
, j
));
4519 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4520 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4521 and apply the corresponding narrowing subreg to *OTHER_PTR.
4522 Return true if the operands were changed, false otherwise. */
4525 strip_paradoxical_subreg (rtx
*op_ptr
, rtx
*other_ptr
)
4527 rtx op
, inner
, other
, tem
;
4530 if (!paradoxical_subreg_p (op
))
4532 inner
= SUBREG_REG (op
);
4535 tem
= gen_lowpart_common (GET_MODE (inner
), other
);
4539 /* If the lowpart operation turned a hard register into a subreg,
4540 rather than simplifying it to another hard register, then the
4541 mode change cannot be properly represented. For example, OTHER
4542 might be valid in its current mode, but not in the new one. */
4543 if (GET_CODE (tem
) == SUBREG
4545 && HARD_REGISTER_P (other
))
4553 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4554 examine all of the reload insns between PREV and NEXT exclusive, and
4555 annotate all that may trap. */
4558 fixup_eh_region_note (rtx_insn
*insn
, rtx_insn
*prev
, rtx_insn
*next
)
4560 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
4563 if (!insn_could_throw_p (insn
))
4564 remove_note (insn
, note
);
4565 copy_reg_eh_region_note_forward (note
, NEXT_INSN (prev
), next
);
4568 /* Reload pseudo-registers into hard regs around each insn as needed.
4569 Additional register load insns are output before the insn that needs it
4570 and perhaps store insns after insns that modify the reloaded pseudo reg.
4572 reg_last_reload_reg and reg_reloaded_contents keep track of
4573 which registers are already available in reload registers.
4574 We update these for the reloads that we perform,
4575 as the insns are scanned. */
4578 reload_as_needed (int live_known
)
4580 struct insn_chain
*chain
;
4581 #if defined (AUTO_INC_DEC)
4586 memset (spill_reg_rtx
, 0, sizeof spill_reg_rtx
);
4587 memset (spill_reg_store
, 0, sizeof spill_reg_store
);
4588 reg_last_reload_reg
= XCNEWVEC (rtx
, max_regno
);
4589 INIT_REG_SET (®_has_output_reload
);
4590 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4591 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered
);
4593 set_initial_elim_offsets ();
4595 /* Generate a marker insn that we will move around. */
4596 marker
= emit_note (NOTE_INSN_DELETED
);
4597 unlink_insn_chain (marker
, marker
);
4599 for (chain
= reload_insn_chain
; chain
; chain
= chain
->next
)
4602 rtx_insn
*insn
= chain
->insn
;
4603 rtx_insn
*old_next
= NEXT_INSN (insn
);
4605 rtx_insn
*old_prev
= PREV_INSN (insn
);
4608 if (will_delete_init_insn_p (insn
))
4611 /* If we pass a label, copy the offsets from the label information
4612 into the current offsets of each elimination. */
4614 set_offsets_for_label (insn
);
4616 else if (INSN_P (insn
))
4618 regset_head regs_to_forget
;
4619 INIT_REG_SET (®s_to_forget
);
4620 note_stores (PATTERN (insn
), forget_old_reloads_1
, ®s_to_forget
);
4622 /* If this is a USE and CLOBBER of a MEM, ensure that any
4623 references to eliminable registers have been removed. */
4625 if ((GET_CODE (PATTERN (insn
)) == USE
4626 || GET_CODE (PATTERN (insn
)) == CLOBBER
)
4627 && MEM_P (XEXP (PATTERN (insn
), 0)))
4628 XEXP (XEXP (PATTERN (insn
), 0), 0)
4629 = eliminate_regs (XEXP (XEXP (PATTERN (insn
), 0), 0),
4630 GET_MODE (XEXP (PATTERN (insn
), 0)),
4633 /* If we need to do register elimination processing, do so.
4634 This might delete the insn, in which case we are done. */
4635 if ((num_eliminable
|| num_eliminable_invariants
) && chain
->need_elim
)
4637 eliminate_regs_in_insn (insn
, 1);
4640 update_eliminable_offsets ();
4641 CLEAR_REG_SET (®s_to_forget
);
4646 /* If need_elim is nonzero but need_reload is zero, one might think
4647 that we could simply set n_reloads to 0. However, find_reloads
4648 could have done some manipulation of the insn (such as swapping
4649 commutative operands), and these manipulations are lost during
4650 the first pass for every insn that needs register elimination.
4651 So the actions of find_reloads must be redone here. */
4653 if (! chain
->need_elim
&& ! chain
->need_reload
4654 && ! chain
->need_operand_change
)
4656 /* First find the pseudo regs that must be reloaded for this insn.
4657 This info is returned in the tables reload_... (see reload.h).
4658 Also modify the body of INSN by substituting RELOAD
4659 rtx's for those pseudo regs. */
4662 CLEAR_REG_SET (®_has_output_reload
);
4663 CLEAR_HARD_REG_SET (reg_is_output_reload
);
4665 find_reloads (insn
, 1, spill_indirect_levels
, live_known
,
4671 rtx_insn
*next
= NEXT_INSN (insn
);
4673 /* ??? PREV can get deleted by reload inheritance.
4674 Work around this by emitting a marker note. */
4675 prev
= PREV_INSN (insn
);
4676 reorder_insns_nobb (marker
, marker
, prev
);
4678 /* Now compute which reload regs to reload them into. Perhaps
4679 reusing reload regs from previous insns, or else output
4680 load insns to reload them. Maybe output store insns too.
4681 Record the choices of reload reg in reload_reg_rtx. */
4682 choose_reload_regs (chain
);
4684 /* Generate the insns to reload operands into or out of
4685 their reload regs. */
4686 emit_reload_insns (chain
);
4688 /* Substitute the chosen reload regs from reload_reg_rtx
4689 into the insn's body (or perhaps into the bodies of other
4690 load and store insn that we just made for reloading
4691 and that we moved the structure into). */
4692 subst_reloads (insn
);
4694 prev
= PREV_INSN (marker
);
4695 unlink_insn_chain (marker
, marker
);
4697 /* Adjust the exception region notes for loads and stores. */
4698 if (cfun
->can_throw_non_call_exceptions
&& !CALL_P (insn
))
4699 fixup_eh_region_note (insn
, prev
, next
);
4701 /* Adjust the location of REG_ARGS_SIZE. */
4702 rtx p
= find_reg_note (insn
, REG_ARGS_SIZE
, NULL_RTX
);
4705 remove_note (insn
, p
);
4706 fixup_args_size_notes (prev
, PREV_INSN (next
),
4707 INTVAL (XEXP (p
, 0)));
4710 /* If this was an ASM, make sure that all the reload insns
4711 we have generated are valid. If not, give an error
4713 if (asm_noperands (PATTERN (insn
)) >= 0)
4714 for (rtx_insn
*p
= NEXT_INSN (prev
);
4717 if (p
!= insn
&& INSN_P (p
)
4718 && GET_CODE (PATTERN (p
)) != USE
4719 && (recog_memoized (p
) < 0
4720 || (extract_insn (p
),
4721 !(constrain_operands (1,
4722 get_enabled_alternatives (p
))))))
4724 error_for_asm (insn
,
4725 "%<asm%> operand requires "
4726 "impossible reload");
4731 if (num_eliminable
&& chain
->need_elim
)
4732 update_eliminable_offsets ();
4734 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4735 is no longer validly lying around to save a future reload.
4736 Note that this does not detect pseudos that were reloaded
4737 for this insn in order to be stored in
4738 (obeying register constraints). That is correct; such reload
4739 registers ARE still valid. */
4740 forget_marked_reloads (®s_to_forget
);
4741 CLEAR_REG_SET (®s_to_forget
);
4743 /* There may have been CLOBBER insns placed after INSN. So scan
4744 between INSN and NEXT and use them to forget old reloads. */
4745 for (rtx_insn
*x
= NEXT_INSN (insn
); x
!= old_next
; x
= NEXT_INSN (x
))
4746 if (NONJUMP_INSN_P (x
) && GET_CODE (PATTERN (x
)) == CLOBBER
)
4747 note_stores (PATTERN (x
), forget_old_reloads_1
, NULL
);
4750 /* Likewise for regs altered by auto-increment in this insn.
4751 REG_INC notes have been changed by reloading:
4752 find_reloads_address_1 records substitutions for them,
4753 which have been performed by subst_reloads above. */
4754 for (i
= n_reloads
- 1; i
>= 0; i
--)
4756 rtx in_reg
= rld
[i
].in_reg
;
4759 enum rtx_code code
= GET_CODE (in_reg
);
4760 /* PRE_INC / PRE_DEC will have the reload register ending up
4761 with the same value as the stack slot, but that doesn't
4762 hold true for POST_INC / POST_DEC. Either we have to
4763 convert the memory access to a true POST_INC / POST_DEC,
4764 or we can't use the reload register for inheritance. */
4765 if ((code
== POST_INC
|| code
== POST_DEC
)
4766 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4767 REGNO (rld
[i
].reg_rtx
))
4768 /* Make sure it is the inc/dec pseudo, and not
4769 some other (e.g. output operand) pseudo. */
4770 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4771 == REGNO (XEXP (in_reg
, 0))))
4774 rtx reload_reg
= rld
[i
].reg_rtx
;
4775 machine_mode mode
= GET_MODE (reload_reg
);
4779 for (p
= PREV_INSN (old_next
); p
!= prev
; p
= PREV_INSN (p
))
4781 /* We really want to ignore REG_INC notes here, so
4782 use PATTERN (p) as argument to reg_set_p . */
4783 if (reg_set_p (reload_reg
, PATTERN (p
)))
4785 n
= count_occurrences (PATTERN (p
), reload_reg
, 0);
4791 = gen_rtx_fmt_e (code
, mode
, reload_reg
);
4793 validate_replace_rtx_group (reload_reg
,
4795 n
= verify_changes (0);
4797 /* We must also verify that the constraints
4798 are met after the replacement. Make sure
4799 extract_insn is only called for an insn
4800 where the replacements were found to be
4805 n
= constrain_operands (1,
4806 get_enabled_alternatives (p
));
4809 /* If the constraints were not met, then
4810 undo the replacement, else confirm it. */
4814 confirm_change_group ();
4820 add_reg_note (p
, REG_INC
, reload_reg
);
4821 /* Mark this as having an output reload so that the
4822 REG_INC processing code below won't invalidate
4823 the reload for inheritance. */
4824 SET_HARD_REG_BIT (reg_is_output_reload
,
4825 REGNO (reload_reg
));
4826 SET_REGNO_REG_SET (®_has_output_reload
,
4827 REGNO (XEXP (in_reg
, 0)));
4830 forget_old_reloads_1 (XEXP (in_reg
, 0), NULL_RTX
,
4833 else if ((code
== PRE_INC
|| code
== PRE_DEC
)
4834 && TEST_HARD_REG_BIT (reg_reloaded_valid
,
4835 REGNO (rld
[i
].reg_rtx
))
4836 /* Make sure it is the inc/dec pseudo, and not
4837 some other (e.g. output operand) pseudo. */
4838 && ((unsigned) reg_reloaded_contents
[REGNO (rld
[i
].reg_rtx
)]
4839 == REGNO (XEXP (in_reg
, 0))))
4841 SET_HARD_REG_BIT (reg_is_output_reload
,
4842 REGNO (rld
[i
].reg_rtx
));
4843 SET_REGNO_REG_SET (®_has_output_reload
,
4844 REGNO (XEXP (in_reg
, 0)));
4846 else if (code
== PRE_INC
|| code
== PRE_DEC
4847 || code
== POST_INC
|| code
== POST_DEC
)
4849 int in_regno
= REGNO (XEXP (in_reg
, 0));
4851 if (reg_last_reload_reg
[in_regno
] != NULL_RTX
)
4854 bool forget_p
= true;
4856 in_hard_regno
= REGNO (reg_last_reload_reg
[in_regno
]);
4857 if (TEST_HARD_REG_BIT (reg_reloaded_valid
,
4860 for (rtx_insn
*x
= (old_prev
?
4861 NEXT_INSN (old_prev
) : insn
);
4864 if (x
== reg_reloaded_insn
[in_hard_regno
])
4870 /* If for some reasons, we didn't set up
4871 reg_last_reload_reg in this insn,
4872 invalidate inheritance from previous
4873 insns for the incremented/decremented
4874 register. Such registers will be not in
4875 reg_has_output_reload. Invalidate it
4876 also if the corresponding element in
4877 reg_reloaded_insn is also
4880 forget_old_reloads_1 (XEXP (in_reg
, 0),
4886 /* If a pseudo that got a hard register is auto-incremented,
4887 we must purge records of copying it into pseudos without
4889 for (rtx x
= REG_NOTES (insn
); x
; x
= XEXP (x
, 1))
4890 if (REG_NOTE_KIND (x
) == REG_INC
)
4892 /* See if this pseudo reg was reloaded in this insn.
4893 If so, its last-reload info is still valid
4894 because it is based on this insn's reload. */
4895 for (i
= 0; i
< n_reloads
; i
++)
4896 if (rld
[i
].out
== XEXP (x
, 0))
4900 forget_old_reloads_1 (XEXP (x
, 0), NULL_RTX
, NULL
);
4904 /* A reload reg's contents are unknown after a label. */
4906 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4908 /* Don't assume a reload reg is still good after a call insn
4909 if it is a call-used reg, or if it contains a value that will
4910 be partially clobbered by the call. */
4911 else if (CALL_P (insn
))
4913 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, call_used_reg_set
);
4914 AND_COMPL_HARD_REG_SET (reg_reloaded_valid
, reg_reloaded_call_part_clobbered
);
4916 /* If this is a call to a setjmp-type function, we must not
4917 reuse any reload reg contents across the call; that will
4918 just be clobbered by other uses of the register in later
4919 code, before the longjmp. */
4920 if (find_reg_note (insn
, REG_SETJMP
, NULL_RTX
))
4921 CLEAR_HARD_REG_SET (reg_reloaded_valid
);
4926 free (reg_last_reload_reg
);
4927 CLEAR_REG_SET (®_has_output_reload
);
4930 /* Discard all record of any value reloaded from X,
4931 or reloaded in X from someplace else;
4932 unless X is an output reload reg of the current insn.
4934 X may be a hard reg (the reload reg)
4935 or it may be a pseudo reg that was reloaded from.
4937 When DATA is non-NULL just mark the registers in regset
4938 to be forgotten later. */
4941 forget_old_reloads_1 (rtx x
, const_rtx ignored ATTRIBUTE_UNUSED
,
4946 regset regs
= (regset
) data
;
4948 /* note_stores does give us subregs of hard regs,
4949 subreg_regno_offset requires a hard reg. */
4950 while (GET_CODE (x
) == SUBREG
)
4952 /* We ignore the subreg offset when calculating the regno,
4953 because we are using the entire underlying hard register
4963 if (regno
>= FIRST_PSEUDO_REGISTER
)
4969 nr
= hard_regno_nregs
[regno
][GET_MODE (x
)];
4970 /* Storing into a spilled-reg invalidates its contents.
4971 This can happen if a block-local pseudo is allocated to that reg
4972 and it wasn't spilled because this block's total need is 0.
4973 Then some insn might have an optional reload and use this reg. */
4975 for (i
= 0; i
< nr
; i
++)
4976 /* But don't do this if the reg actually serves as an output
4977 reload reg in the current instruction. */
4979 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, regno
+ i
))
4981 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, regno
+ i
);
4982 spill_reg_store
[regno
+ i
] = 0;
4988 SET_REGNO_REG_SET (regs
, regno
+ nr
);
4991 /* Since value of X has changed,
4992 forget any value previously copied from it. */
4995 /* But don't forget a copy if this is the output reload
4996 that establishes the copy's validity. */
4998 || !REGNO_REG_SET_P (®_has_output_reload
, regno
+ nr
))
4999 reg_last_reload_reg
[regno
+ nr
] = 0;
5003 /* Forget the reloads marked in regset by previous function. */
5005 forget_marked_reloads (regset regs
)
5008 reg_set_iterator rsi
;
5009 EXECUTE_IF_SET_IN_REG_SET (regs
, 0, reg
, rsi
)
5011 if (reg
< FIRST_PSEUDO_REGISTER
5012 /* But don't do this if the reg actually serves as an output
5013 reload reg in the current instruction. */
5015 || ! TEST_HARD_REG_BIT (reg_is_output_reload
, reg
)))
5017 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, reg
);
5018 spill_reg_store
[reg
] = 0;
5021 || !REGNO_REG_SET_P (®_has_output_reload
, reg
))
5022 reg_last_reload_reg
[reg
] = 0;
5026 /* The following HARD_REG_SETs indicate when each hard register is
5027 used for a reload of various parts of the current insn. */
5029 /* If reg is unavailable for all reloads. */
5030 static HARD_REG_SET reload_reg_unavailable
;
5031 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5032 static HARD_REG_SET reload_reg_used
;
5033 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5034 static HARD_REG_SET reload_reg_used_in_input_addr
[MAX_RECOG_OPERANDS
];
5035 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5036 static HARD_REG_SET reload_reg_used_in_inpaddr_addr
[MAX_RECOG_OPERANDS
];
5037 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5038 static HARD_REG_SET reload_reg_used_in_output_addr
[MAX_RECOG_OPERANDS
];
5039 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5040 static HARD_REG_SET reload_reg_used_in_outaddr_addr
[MAX_RECOG_OPERANDS
];
5041 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5042 static HARD_REG_SET reload_reg_used_in_input
[MAX_RECOG_OPERANDS
];
5043 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5044 static HARD_REG_SET reload_reg_used_in_output
[MAX_RECOG_OPERANDS
];
5045 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5046 static HARD_REG_SET reload_reg_used_in_op_addr
;
5047 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5048 static HARD_REG_SET reload_reg_used_in_op_addr_reload
;
5049 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5050 static HARD_REG_SET reload_reg_used_in_insn
;
5051 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5052 static HARD_REG_SET reload_reg_used_in_other_addr
;
5054 /* If reg is in use as a reload reg for any sort of reload. */
5055 static HARD_REG_SET reload_reg_used_at_all
;
5057 /* If reg is use as an inherited reload. We just mark the first register
5059 static HARD_REG_SET reload_reg_used_for_inherit
;
5061 /* Records which hard regs are used in any way, either as explicit use or
5062 by being allocated to a pseudo during any point of the current insn. */
5063 static HARD_REG_SET reg_used_in_insn
;
5065 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5066 TYPE. MODE is used to indicate how many consecutive regs are
5070 mark_reload_reg_in_use (unsigned int regno
, int opnum
, enum reload_type type
,
5076 add_to_hard_reg_set (&reload_reg_used
, mode
, regno
);
5079 case RELOAD_FOR_INPUT_ADDRESS
:
5080 add_to_hard_reg_set (&reload_reg_used_in_input_addr
[opnum
], mode
, regno
);
5083 case RELOAD_FOR_INPADDR_ADDRESS
:
5084 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr
[opnum
], mode
, regno
);
5087 case RELOAD_FOR_OUTPUT_ADDRESS
:
5088 add_to_hard_reg_set (&reload_reg_used_in_output_addr
[opnum
], mode
, regno
);
5091 case RELOAD_FOR_OUTADDR_ADDRESS
:
5092 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr
[opnum
], mode
, regno
);
5095 case RELOAD_FOR_OPERAND_ADDRESS
:
5096 add_to_hard_reg_set (&reload_reg_used_in_op_addr
, mode
, regno
);
5099 case RELOAD_FOR_OPADDR_ADDR
:
5100 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload
, mode
, regno
);
5103 case RELOAD_FOR_OTHER_ADDRESS
:
5104 add_to_hard_reg_set (&reload_reg_used_in_other_addr
, mode
, regno
);
5107 case RELOAD_FOR_INPUT
:
5108 add_to_hard_reg_set (&reload_reg_used_in_input
[opnum
], mode
, regno
);
5111 case RELOAD_FOR_OUTPUT
:
5112 add_to_hard_reg_set (&reload_reg_used_in_output
[opnum
], mode
, regno
);
5115 case RELOAD_FOR_INSN
:
5116 add_to_hard_reg_set (&reload_reg_used_in_insn
, mode
, regno
);
5120 add_to_hard_reg_set (&reload_reg_used_at_all
, mode
, regno
);
5123 /* Similarly, but show REGNO is no longer in use for a reload. */
5126 clear_reload_reg_in_use (unsigned int regno
, int opnum
,
5127 enum reload_type type
, machine_mode mode
)
5129 unsigned int nregs
= hard_regno_nregs
[regno
][mode
];
5130 unsigned int start_regno
, end_regno
, r
;
5132 /* A complication is that for some reload types, inheritance might
5133 allow multiple reloads of the same types to share a reload register.
5134 We set check_opnum if we have to check only reloads with the same
5135 operand number, and check_any if we have to check all reloads. */
5136 int check_opnum
= 0;
5138 HARD_REG_SET
*used_in_set
;
5143 used_in_set
= &reload_reg_used
;
5146 case RELOAD_FOR_INPUT_ADDRESS
:
5147 used_in_set
= &reload_reg_used_in_input_addr
[opnum
];
5150 case RELOAD_FOR_INPADDR_ADDRESS
:
5152 used_in_set
= &reload_reg_used_in_inpaddr_addr
[opnum
];
5155 case RELOAD_FOR_OUTPUT_ADDRESS
:
5156 used_in_set
= &reload_reg_used_in_output_addr
[opnum
];
5159 case RELOAD_FOR_OUTADDR_ADDRESS
:
5161 used_in_set
= &reload_reg_used_in_outaddr_addr
[opnum
];
5164 case RELOAD_FOR_OPERAND_ADDRESS
:
5165 used_in_set
= &reload_reg_used_in_op_addr
;
5168 case RELOAD_FOR_OPADDR_ADDR
:
5170 used_in_set
= &reload_reg_used_in_op_addr_reload
;
5173 case RELOAD_FOR_OTHER_ADDRESS
:
5174 used_in_set
= &reload_reg_used_in_other_addr
;
5178 case RELOAD_FOR_INPUT
:
5179 used_in_set
= &reload_reg_used_in_input
[opnum
];
5182 case RELOAD_FOR_OUTPUT
:
5183 used_in_set
= &reload_reg_used_in_output
[opnum
];
5186 case RELOAD_FOR_INSN
:
5187 used_in_set
= &reload_reg_used_in_insn
;
5192 /* We resolve conflicts with remaining reloads of the same type by
5193 excluding the intervals of reload registers by them from the
5194 interval of freed reload registers. Since we only keep track of
5195 one set of interval bounds, we might have to exclude somewhat
5196 more than what would be necessary if we used a HARD_REG_SET here.
5197 But this should only happen very infrequently, so there should
5198 be no reason to worry about it. */
5200 start_regno
= regno
;
5201 end_regno
= regno
+ nregs
;
5202 if (check_opnum
|| check_any
)
5204 for (i
= n_reloads
- 1; i
>= 0; i
--)
5206 if (rld
[i
].when_needed
== type
5207 && (check_any
|| rld
[i
].opnum
== opnum
)
5210 unsigned int conflict_start
= true_regnum (rld
[i
].reg_rtx
);
5211 unsigned int conflict_end
5212 = end_hard_regno (rld
[i
].mode
, conflict_start
);
5214 /* If there is an overlap with the first to-be-freed register,
5215 adjust the interval start. */
5216 if (conflict_start
<= start_regno
&& conflict_end
> start_regno
)
5217 start_regno
= conflict_end
;
5218 /* Otherwise, if there is a conflict with one of the other
5219 to-be-freed registers, adjust the interval end. */
5220 if (conflict_start
> start_regno
&& conflict_start
< end_regno
)
5221 end_regno
= conflict_start
;
5226 for (r
= start_regno
; r
< end_regno
; r
++)
5227 CLEAR_HARD_REG_BIT (*used_in_set
, r
);
5230 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5231 specified by OPNUM and TYPE. */
5234 reload_reg_free_p (unsigned int regno
, int opnum
, enum reload_type type
)
5238 /* In use for a RELOAD_OTHER means it's not available for anything. */
5239 if (TEST_HARD_REG_BIT (reload_reg_used
, regno
)
5240 || TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5246 /* In use for anything means we can't use it for RELOAD_OTHER. */
5247 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
)
5248 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5249 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5250 || TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5253 for (i
= 0; i
< reload_n_operands
; i
++)
5254 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5255 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5256 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5257 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5258 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5259 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5264 case RELOAD_FOR_INPUT
:
5265 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5266 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
))
5269 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5272 /* If it is used for some other input, can't use it. */
5273 for (i
= 0; i
< reload_n_operands
; i
++)
5274 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5277 /* If it is used in a later operand's address, can't use it. */
5278 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5279 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5280 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5285 case RELOAD_FOR_INPUT_ADDRESS
:
5286 /* Can't use a register if it is used for an input address for this
5287 operand or used as an input in an earlier one. */
5288 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
)
5289 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5292 for (i
= 0; i
< opnum
; i
++)
5293 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5298 case RELOAD_FOR_INPADDR_ADDRESS
:
5299 /* Can't use a register if it is used for an input address
5300 for this operand or used as an input in an earlier
5302 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[opnum
], regno
))
5305 for (i
= 0; i
< opnum
; i
++)
5306 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5311 case RELOAD_FOR_OUTPUT_ADDRESS
:
5312 /* Can't use a register if it is used for an output address for this
5313 operand or used as an output in this or a later operand. Note
5314 that multiple output operands are emitted in reverse order, so
5315 the conflicting ones are those with lower indices. */
5316 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[opnum
], regno
))
5319 for (i
= 0; i
<= opnum
; i
++)
5320 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5325 case RELOAD_FOR_OUTADDR_ADDRESS
:
5326 /* Can't use a register if it is used for an output address
5327 for this operand or used as an output in this or a
5328 later operand. Note that multiple output operands are
5329 emitted in reverse order, so the conflicting ones are
5330 those with lower indices. */
5331 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5334 for (i
= 0; i
<= opnum
; i
++)
5335 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5340 case RELOAD_FOR_OPERAND_ADDRESS
:
5341 for (i
= 0; i
< reload_n_operands
; i
++)
5342 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5345 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5346 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5348 case RELOAD_FOR_OPADDR_ADDR
:
5349 for (i
= 0; i
< reload_n_operands
; i
++)
5350 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5353 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
));
5355 case RELOAD_FOR_OUTPUT
:
5356 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5357 outputs, or an operand address for this or an earlier output.
5358 Note that multiple output operands are emitted in reverse order,
5359 so the conflicting ones are those with higher indices. */
5360 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
))
5363 for (i
= 0; i
< reload_n_operands
; i
++)
5364 if (TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5367 for (i
= opnum
; i
< reload_n_operands
; i
++)
5368 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5369 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5374 case RELOAD_FOR_INSN
:
5375 for (i
= 0; i
< reload_n_operands
; i
++)
5376 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
)
5377 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5380 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5381 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
));
5383 case RELOAD_FOR_OTHER_ADDRESS
:
5384 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr
, regno
);
5391 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5392 the number RELOADNUM, is still available in REGNO at the end of the insn.
5394 We can assume that the reload reg was already tested for availability
5395 at the time it is needed, and we should not check this again,
5396 in case the reg has already been marked in use. */
5399 reload_reg_reaches_end_p (unsigned int regno
, int reloadnum
)
5401 int opnum
= rld
[reloadnum
].opnum
;
5402 enum reload_type type
= rld
[reloadnum
].when_needed
;
5405 /* See if there is a reload with the same type for this operand, using
5406 the same register. This case is not handled by the code below. */
5407 for (i
= reloadnum
+ 1; i
< n_reloads
; i
++)
5412 if (rld
[i
].opnum
!= opnum
|| rld
[i
].when_needed
!= type
)
5414 reg
= rld
[i
].reg_rtx
;
5415 if (reg
== NULL_RTX
)
5417 nregs
= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)];
5418 if (regno
>= REGNO (reg
) && regno
< REGNO (reg
) + nregs
)
5425 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5426 its value must reach the end. */
5429 /* If this use is for part of the insn,
5430 its value reaches if no subsequent part uses the same register.
5431 Just like the above function, don't try to do this with lots
5434 case RELOAD_FOR_OTHER_ADDRESS
:
5435 /* Here we check for everything else, since these don't conflict
5436 with anything else and everything comes later. */
5438 for (i
= 0; i
< reload_n_operands
; i
++)
5439 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5440 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5441 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
)
5442 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5443 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5444 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5447 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5448 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
)
5449 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5450 && ! TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5452 case RELOAD_FOR_INPUT_ADDRESS
:
5453 case RELOAD_FOR_INPADDR_ADDRESS
:
5454 /* Similar, except that we check only for this and subsequent inputs
5455 and the address of only subsequent inputs and we do not need
5456 to check for RELOAD_OTHER objects since they are known not to
5459 for (i
= opnum
; i
< reload_n_operands
; i
++)
5460 if (TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5463 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5464 could be killed if the register is also used by reload with type
5465 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5466 if (type
== RELOAD_FOR_INPADDR_ADDRESS
5467 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[opnum
], regno
))
5470 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5471 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5472 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
))
5475 for (i
= 0; i
< reload_n_operands
; i
++)
5476 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5477 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5478 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5481 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload
, regno
))
5484 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5485 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5486 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5488 case RELOAD_FOR_INPUT
:
5489 /* Similar to input address, except we start at the next operand for
5490 both input and input address and we do not check for
5491 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5494 for (i
= opnum
+ 1; i
< reload_n_operands
; i
++)
5495 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr
[i
], regno
)
5496 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr
[i
], regno
)
5497 || TEST_HARD_REG_BIT (reload_reg_used_in_input
[i
], regno
))
5500 /* ... fall through ... */
5502 case RELOAD_FOR_OPERAND_ADDRESS
:
5503 /* Check outputs and their addresses. */
5505 for (i
= 0; i
< reload_n_operands
; i
++)
5506 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5507 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5508 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5511 return (!TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5513 case RELOAD_FOR_OPADDR_ADDR
:
5514 for (i
= 0; i
< reload_n_operands
; i
++)
5515 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5516 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
)
5517 || TEST_HARD_REG_BIT (reload_reg_used_in_output
[i
], regno
))
5520 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr
, regno
)
5521 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn
, regno
)
5522 && !TEST_HARD_REG_BIT (reload_reg_used
, regno
));
5524 case RELOAD_FOR_INSN
:
5525 /* These conflict with other outputs with RELOAD_OTHER. So
5526 we need only check for output addresses. */
5528 opnum
= reload_n_operands
;
5530 /* ... fall through ... */
5532 case RELOAD_FOR_OUTPUT
:
5533 case RELOAD_FOR_OUTPUT_ADDRESS
:
5534 case RELOAD_FOR_OUTADDR_ADDRESS
:
5535 /* We already know these can't conflict with a later output. So the
5536 only thing to check are later output addresses.
5537 Note that multiple output operands are emitted in reverse order,
5538 so the conflicting ones are those with lower indices. */
5539 for (i
= 0; i
< opnum
; i
++)
5540 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr
[i
], regno
)
5541 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[i
], regno
))
5544 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5545 could be killed if the register is also used by reload with type
5546 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5547 if (type
== RELOAD_FOR_OUTADDR_ADDRESS
5548 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr
[opnum
], regno
))
5558 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5559 every register in REG. */
5562 reload_reg_rtx_reaches_end_p (rtx reg
, int reloadnum
)
5566 for (i
= REGNO (reg
); i
< END_REGNO (reg
); i
++)
5567 if (!reload_reg_reaches_end_p (i
, reloadnum
))
5573 /* Returns whether R1 and R2 are uniquely chained: the value of one
5574 is used by the other, and that value is not used by any other
5575 reload for this insn. This is used to partially undo the decision
5576 made in find_reloads when in the case of multiple
5577 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5578 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5579 reloads. This code tries to avoid the conflict created by that
5580 change. It might be cleaner to explicitly keep track of which
5581 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5582 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5583 this after the fact. */
5585 reloads_unique_chain_p (int r1
, int r2
)
5589 /* We only check input reloads. */
5590 if (! rld
[r1
].in
|| ! rld
[r2
].in
)
5593 /* Avoid anything with output reloads. */
5594 if (rld
[r1
].out
|| rld
[r2
].out
)
5597 /* "chained" means one reload is a component of the other reload,
5598 not the same as the other reload. */
5599 if (rld
[r1
].opnum
!= rld
[r2
].opnum
5600 || rtx_equal_p (rld
[r1
].in
, rld
[r2
].in
)
5601 || rld
[r1
].optional
|| rld
[r2
].optional
5602 || ! (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
)
5603 || reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
)))
5606 /* The following loop assumes that r1 is the reload that feeds r2. */
5610 for (i
= 0; i
< n_reloads
; i
++)
5611 /* Look for input reloads that aren't our two */
5612 if (i
!= r1
&& i
!= r2
&& rld
[i
].in
)
5614 /* If our reload is mentioned at all, it isn't a simple chain. */
5615 if (reg_mentioned_p (rld
[r1
].in
, rld
[i
].in
))
5621 /* The recursive function change all occurrences of WHAT in *WHERE
5624 substitute (rtx
*where
, const_rtx what
, rtx repl
)
5633 if (*where
== what
|| rtx_equal_p (*where
, what
))
5635 /* Record the location of the changed rtx. */
5636 substitute_stack
.safe_push (where
);
5641 code
= GET_CODE (*where
);
5642 fmt
= GET_RTX_FORMAT (code
);
5643 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
5649 for (j
= XVECLEN (*where
, i
) - 1; j
>= 0; j
--)
5650 substitute (&XVECEXP (*where
, i
, j
), what
, repl
);
5652 else if (fmt
[i
] == 'e')
5653 substitute (&XEXP (*where
, i
), what
, repl
);
5657 /* The function returns TRUE if chain of reload R1 and R2 (in any
5658 order) can be evaluated without usage of intermediate register for
5659 the reload containing another reload. It is important to see
5660 gen_reload to understand what the function is trying to do. As an
5661 example, let us have reload chain
5664 r1: <something> + const
5666 and reload R2 got reload reg HR. The function returns true if
5667 there is a correct insn HR = HR + <something>. Otherwise,
5668 gen_reload will use intermediate register (and this is the reload
5669 reg for R1) to reload <something>.
5671 We need this function to find a conflict for chain reloads. In our
5672 example, if HR = HR + <something> is incorrect insn, then we cannot
5673 use HR as a reload register for R2. If we do use it then we get a
5682 gen_reload_chain_without_interm_reg_p (int r1
, int r2
)
5684 /* Assume other cases in gen_reload are not possible for
5685 chain reloads or do need an intermediate hard registers. */
5690 rtx_insn
*last
= get_last_insn ();
5692 /* Make r2 a component of r1. */
5693 if (reg_mentioned_p (rld
[r1
].in
, rld
[r2
].in
))
5696 gcc_assert (reg_mentioned_p (rld
[r2
].in
, rld
[r1
].in
));
5697 regno
= rld
[r1
].regno
>= 0 ? rld
[r1
].regno
: rld
[r2
].regno
;
5698 gcc_assert (regno
>= 0);
5699 out
= gen_rtx_REG (rld
[r1
].mode
, regno
);
5701 substitute (&in
, rld
[r2
].in
, gen_rtx_REG (rld
[r2
].mode
, regno
));
5703 /* If IN is a paradoxical SUBREG, remove it and try to put the
5704 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5705 strip_paradoxical_subreg (&in
, &out
);
5707 if (GET_CODE (in
) == PLUS
5708 && (REG_P (XEXP (in
, 0))
5709 || GET_CODE (XEXP (in
, 0)) == SUBREG
5710 || MEM_P (XEXP (in
, 0)))
5711 && (REG_P (XEXP (in
, 1))
5712 || GET_CODE (XEXP (in
, 1)) == SUBREG
5713 || CONSTANT_P (XEXP (in
, 1))
5714 || MEM_P (XEXP (in
, 1))))
5716 insn
= emit_insn (gen_rtx_SET (out
, in
));
5717 code
= recog_memoized (insn
);
5722 extract_insn (insn
);
5723 /* We want constrain operands to treat this insn strictly in
5724 its validity determination, i.e., the way it would after
5725 reload has completed. */
5726 result
= constrain_operands (1, get_enabled_alternatives (insn
));
5729 delete_insns_since (last
);
5732 /* Restore the original value at each changed address within R1. */
5733 while (!substitute_stack
.is_empty ())
5735 rtx
*where
= substitute_stack
.pop ();
5736 *where
= rld
[r2
].in
;
5742 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5745 This function uses the same algorithm as reload_reg_free_p above. */
5748 reloads_conflict (int r1
, int r2
)
5750 enum reload_type r1_type
= rld
[r1
].when_needed
;
5751 enum reload_type r2_type
= rld
[r2
].when_needed
;
5752 int r1_opnum
= rld
[r1
].opnum
;
5753 int r2_opnum
= rld
[r2
].opnum
;
5755 /* RELOAD_OTHER conflicts with everything. */
5756 if (r2_type
== RELOAD_OTHER
)
5759 /* Otherwise, check conflicts differently for each type. */
5763 case RELOAD_FOR_INPUT
:
5764 return (r2_type
== RELOAD_FOR_INSN
5765 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5766 || r2_type
== RELOAD_FOR_OPADDR_ADDR
5767 || r2_type
== RELOAD_FOR_INPUT
5768 || ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
5769 || r2_type
== RELOAD_FOR_INPADDR_ADDRESS
)
5770 && r2_opnum
> r1_opnum
));
5772 case RELOAD_FOR_INPUT_ADDRESS
:
5773 return ((r2_type
== RELOAD_FOR_INPUT_ADDRESS
&& r1_opnum
== r2_opnum
)
5774 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5776 case RELOAD_FOR_INPADDR_ADDRESS
:
5777 return ((r2_type
== RELOAD_FOR_INPADDR_ADDRESS
&& r1_opnum
== r2_opnum
)
5778 || (r2_type
== RELOAD_FOR_INPUT
&& r2_opnum
< r1_opnum
));
5780 case RELOAD_FOR_OUTPUT_ADDRESS
:
5781 return ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
&& r2_opnum
== r1_opnum
)
5782 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5784 case RELOAD_FOR_OUTADDR_ADDRESS
:
5785 return ((r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
&& r2_opnum
== r1_opnum
)
5786 || (r2_type
== RELOAD_FOR_OUTPUT
&& r2_opnum
<= r1_opnum
));
5788 case RELOAD_FOR_OPERAND_ADDRESS
:
5789 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_INSN
5790 || (r2_type
== RELOAD_FOR_OPERAND_ADDRESS
5791 && (!reloads_unique_chain_p (r1
, r2
)
5792 || !gen_reload_chain_without_interm_reg_p (r1
, r2
))));
5794 case RELOAD_FOR_OPADDR_ADDR
:
5795 return (r2_type
== RELOAD_FOR_INPUT
5796 || r2_type
== RELOAD_FOR_OPADDR_ADDR
);
5798 case RELOAD_FOR_OUTPUT
:
5799 return (r2_type
== RELOAD_FOR_INSN
|| r2_type
== RELOAD_FOR_OUTPUT
5800 || ((r2_type
== RELOAD_FOR_OUTPUT_ADDRESS
5801 || r2_type
== RELOAD_FOR_OUTADDR_ADDRESS
)
5802 && r2_opnum
>= r1_opnum
));
5804 case RELOAD_FOR_INSN
:
5805 return (r2_type
== RELOAD_FOR_INPUT
|| r2_type
== RELOAD_FOR_OUTPUT
5806 || r2_type
== RELOAD_FOR_INSN
5807 || r2_type
== RELOAD_FOR_OPERAND_ADDRESS
);
5809 case RELOAD_FOR_OTHER_ADDRESS
:
5810 return r2_type
== RELOAD_FOR_OTHER_ADDRESS
;
5820 /* Indexed by reload number, 1 if incoming value
5821 inherited from previous insns. */
5822 static char reload_inherited
[MAX_RELOADS
];
5824 /* For an inherited reload, this is the insn the reload was inherited from,
5825 if we know it. Otherwise, this is 0. */
5826 static rtx_insn
*reload_inheritance_insn
[MAX_RELOADS
];
5828 /* If nonzero, this is a place to get the value of the reload,
5829 rather than using reload_in. */
5830 static rtx reload_override_in
[MAX_RELOADS
];
5832 /* For each reload, the hard register number of the register used,
5833 or -1 if we did not need a register for this reload. */
5834 static int reload_spill_index
[MAX_RELOADS
];
5836 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5837 static rtx reload_reg_rtx_for_input
[MAX_RELOADS
];
5839 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5840 static rtx reload_reg_rtx_for_output
[MAX_RELOADS
];
5842 /* Subroutine of free_for_value_p, used to check a single register.
5843 START_REGNO is the starting regno of the full reload register
5844 (possibly comprising multiple hard registers) that we are considering. */
5847 reload_reg_free_for_value_p (int start_regno
, int regno
, int opnum
,
5848 enum reload_type type
, rtx value
, rtx out
,
5849 int reloadnum
, int ignore_address_reloads
)
5852 /* Set if we see an input reload that must not share its reload register
5853 with any new earlyclobber, but might otherwise share the reload
5854 register with an output or input-output reload. */
5855 int check_earlyclobber
= 0;
5859 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, regno
))
5862 if (out
== const0_rtx
)
5868 /* We use some pseudo 'time' value to check if the lifetimes of the
5869 new register use would overlap with the one of a previous reload
5870 that is not read-only or uses a different value.
5871 The 'time' used doesn't have to be linear in any shape or form, just
5873 Some reload types use different 'buckets' for each operand.
5874 So there are MAX_RECOG_OPERANDS different time values for each
5876 We compute TIME1 as the time when the register for the prospective
5877 new reload ceases to be live, and TIME2 for each existing
5878 reload as the time when that the reload register of that reload
5880 Where there is little to be gained by exact lifetime calculations,
5881 we just make conservative assumptions, i.e. a longer lifetime;
5882 this is done in the 'default:' cases. */
5885 case RELOAD_FOR_OTHER_ADDRESS
:
5886 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5887 time1
= copy
? 0 : 1;
5890 time1
= copy
? 1 : MAX_RECOG_OPERANDS
* 5 + 5;
5892 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5893 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5894 respectively, to the time values for these, we get distinct time
5895 values. To get distinct time values for each operand, we have to
5896 multiply opnum by at least three. We round that up to four because
5897 multiply by four is often cheaper. */
5898 case RELOAD_FOR_INPADDR_ADDRESS
:
5899 time1
= opnum
* 4 + 2;
5901 case RELOAD_FOR_INPUT_ADDRESS
:
5902 time1
= opnum
* 4 + 3;
5904 case RELOAD_FOR_INPUT
:
5905 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5906 executes (inclusive). */
5907 time1
= copy
? opnum
* 4 + 4 : MAX_RECOG_OPERANDS
* 4 + 3;
5909 case RELOAD_FOR_OPADDR_ADDR
:
5911 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5912 time1
= MAX_RECOG_OPERANDS
* 4 + 1;
5914 case RELOAD_FOR_OPERAND_ADDRESS
:
5915 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5917 time1
= copy
? MAX_RECOG_OPERANDS
* 4 + 2 : MAX_RECOG_OPERANDS
* 4 + 3;
5919 case RELOAD_FOR_OUTADDR_ADDRESS
:
5920 time1
= MAX_RECOG_OPERANDS
* 4 + 4 + opnum
;
5922 case RELOAD_FOR_OUTPUT_ADDRESS
:
5923 time1
= MAX_RECOG_OPERANDS
* 4 + 5 + opnum
;
5926 time1
= MAX_RECOG_OPERANDS
* 5 + 5;
5929 for (i
= 0; i
< n_reloads
; i
++)
5931 rtx reg
= rld
[i
].reg_rtx
;
5932 if (reg
&& REG_P (reg
)
5933 && ((unsigned) regno
- true_regnum (reg
)
5934 <= hard_regno_nregs
[REGNO (reg
)][GET_MODE (reg
)] - (unsigned) 1)
5937 rtx other_input
= rld
[i
].in
;
5939 /* If the other reload loads the same input value, that
5940 will not cause a conflict only if it's loading it into
5941 the same register. */
5942 if (true_regnum (reg
) != start_regno
)
5943 other_input
= NULL_RTX
;
5944 if (! other_input
|| ! rtx_equal_p (other_input
, value
)
5945 || rld
[i
].out
|| out
)
5948 switch (rld
[i
].when_needed
)
5950 case RELOAD_FOR_OTHER_ADDRESS
:
5953 case RELOAD_FOR_INPADDR_ADDRESS
:
5954 /* find_reloads makes sure that a
5955 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5956 by at most one - the first -
5957 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5958 address reload is inherited, the address address reload
5959 goes away, so we can ignore this conflict. */
5960 if (type
== RELOAD_FOR_INPUT_ADDRESS
&& reloadnum
== i
+ 1
5961 && ignore_address_reloads
5962 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5963 Then the address address is still needed to store
5964 back the new address. */
5965 && ! rld
[reloadnum
].out
)
5967 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5968 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5970 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5971 && ignore_address_reloads
5972 /* Unless we are reloading an auto_inc expression. */
5973 && ! rld
[reloadnum
].out
)
5975 time2
= rld
[i
].opnum
* 4 + 2;
5977 case RELOAD_FOR_INPUT_ADDRESS
:
5978 if (type
== RELOAD_FOR_INPUT
&& opnum
== rld
[i
].opnum
5979 && ignore_address_reloads
5980 && ! rld
[reloadnum
].out
)
5982 time2
= rld
[i
].opnum
* 4 + 3;
5984 case RELOAD_FOR_INPUT
:
5985 time2
= rld
[i
].opnum
* 4 + 4;
5986 check_earlyclobber
= 1;
5988 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5989 == MAX_RECOG_OPERAND * 4 */
5990 case RELOAD_FOR_OPADDR_ADDR
:
5991 if (type
== RELOAD_FOR_OPERAND_ADDRESS
&& reloadnum
== i
+ 1
5992 && ignore_address_reloads
5993 && ! rld
[reloadnum
].out
)
5995 time2
= MAX_RECOG_OPERANDS
* 4 + 1;
5997 case RELOAD_FOR_OPERAND_ADDRESS
:
5998 time2
= MAX_RECOG_OPERANDS
* 4 + 2;
5999 check_earlyclobber
= 1;
6001 case RELOAD_FOR_INSN
:
6002 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6004 case RELOAD_FOR_OUTPUT
:
6005 /* All RELOAD_FOR_OUTPUT reloads become live just after the
6006 instruction is executed. */
6007 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6009 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
6010 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
6012 case RELOAD_FOR_OUTADDR_ADDRESS
:
6013 if (type
== RELOAD_FOR_OUTPUT_ADDRESS
&& reloadnum
== i
+ 1
6014 && ignore_address_reloads
6015 && ! rld
[reloadnum
].out
)
6017 time2
= MAX_RECOG_OPERANDS
* 4 + 4 + rld
[i
].opnum
;
6019 case RELOAD_FOR_OUTPUT_ADDRESS
:
6020 time2
= MAX_RECOG_OPERANDS
* 4 + 5 + rld
[i
].opnum
;
6023 /* If there is no conflict in the input part, handle this
6024 like an output reload. */
6025 if (! rld
[i
].in
|| rtx_equal_p (other_input
, value
))
6027 time2
= MAX_RECOG_OPERANDS
* 4 + 4;
6028 /* Earlyclobbered outputs must conflict with inputs. */
6029 if (earlyclobber_operand_p (rld
[i
].out
))
6030 time2
= MAX_RECOG_OPERANDS
* 4 + 3;
6035 /* RELOAD_OTHER might be live beyond instruction execution,
6036 but this is not obvious when we set time2 = 1. So check
6037 here if there might be a problem with the new reload
6038 clobbering the register used by the RELOAD_OTHER. */
6046 && (! rld
[i
].in
|| rld
[i
].out
6047 || ! rtx_equal_p (other_input
, value
)))
6048 || (out
&& rld
[reloadnum
].out_reg
6049 && time2
>= MAX_RECOG_OPERANDS
* 4 + 3))
6055 /* Earlyclobbered outputs must conflict with inputs. */
6056 if (check_earlyclobber
&& out
&& earlyclobber_operand_p (out
))
6062 /* Return 1 if the value in reload reg REGNO, as used by a reload
6063 needed for the part of the insn specified by OPNUM and TYPE,
6064 may be used to load VALUE into it.
6066 MODE is the mode in which the register is used, this is needed to
6067 determine how many hard regs to test.
6069 Other read-only reloads with the same value do not conflict
6070 unless OUT is nonzero and these other reloads have to live while
6071 output reloads live.
6072 If OUT is CONST0_RTX, this is a special case: it means that the
6073 test should not be for using register REGNO as reload register, but
6074 for copying from register REGNO into the reload register.
6076 RELOADNUM is the number of the reload we want to load this value for;
6077 a reload does not conflict with itself.
6079 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6080 reloads that load an address for the very reload we are considering.
6082 The caller has to make sure that there is no conflict with the return
6086 free_for_value_p (int regno
, machine_mode mode
, int opnum
,
6087 enum reload_type type
, rtx value
, rtx out
, int reloadnum
,
6088 int ignore_address_reloads
)
6090 int nregs
= hard_regno_nregs
[regno
][mode
];
6092 if (! reload_reg_free_for_value_p (regno
, regno
+ nregs
, opnum
, type
,
6093 value
, out
, reloadnum
,
6094 ignore_address_reloads
))
6099 /* Return nonzero if the rtx X is invariant over the current function. */
6100 /* ??? Actually, the places where we use this expect exactly what is
6101 tested here, and not everything that is function invariant. In
6102 particular, the frame pointer and arg pointer are special cased;
6103 pic_offset_table_rtx is not, and we must not spill these things to
6107 function_invariant_p (const_rtx x
)
6111 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
6113 if (GET_CODE (x
) == PLUS
6114 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
6115 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6120 /* Determine whether the reload reg X overlaps any rtx'es used for
6121 overriding inheritance. Return nonzero if so. */
6124 conflicts_with_override (rtx x
)
6127 for (i
= 0; i
< n_reloads
; i
++)
6128 if (reload_override_in
[i
]
6129 && reg_overlap_mentioned_p (x
, reload_override_in
[i
]))
6134 /* Give an error message saying we failed to find a reload for INSN,
6135 and clear out reload R. */
6137 failed_reload (rtx_insn
*insn
, int r
)
6139 if (asm_noperands (PATTERN (insn
)) < 0)
6140 /* It's the compiler's fault. */
6141 fatal_insn ("could not find a spill register", insn
);
6143 /* It's the user's fault; the operand's mode and constraint
6144 don't match. Disable this reload so we don't crash in final. */
6145 error_for_asm (insn
,
6146 "%<asm%> operand constraint incompatible with operand size");
6150 rld
[r
].optional
= 1;
6151 rld
[r
].secondary_p
= 1;
6154 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6155 for reload R. If it's valid, get an rtx for it. Return nonzero if
6158 set_reload_reg (int i
, int r
)
6160 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6162 int regno ATTRIBUTE_UNUSED
;
6163 rtx reg
= spill_reg_rtx
[i
];
6165 if (reg
== 0 || GET_MODE (reg
) != rld
[r
].mode
)
6166 spill_reg_rtx
[i
] = reg
6167 = gen_rtx_REG (rld
[r
].mode
, spill_regs
[i
]);
6169 regno
= true_regnum (reg
);
6171 /* Detect when the reload reg can't hold the reload mode.
6172 This used to be one `if', but Sequent compiler can't handle that. */
6173 if (HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6175 machine_mode test_mode
= VOIDmode
;
6177 test_mode
= GET_MODE (rld
[r
].in
);
6178 /* If rld[r].in has VOIDmode, it means we will load it
6179 in whatever mode the reload reg has: to wit, rld[r].mode.
6180 We have already tested that for validity. */
6181 /* Aside from that, we need to test that the expressions
6182 to reload from or into have modes which are valid for this
6183 reload register. Otherwise the reload insns would be invalid. */
6184 if (! (rld
[r
].in
!= 0 && test_mode
!= VOIDmode
6185 && ! HARD_REGNO_MODE_OK (regno
, test_mode
)))
6186 if (! (rld
[r
].out
!= 0
6187 && ! HARD_REGNO_MODE_OK (regno
, GET_MODE (rld
[r
].out
))))
6189 /* The reg is OK. */
6192 /* Mark as in use for this insn the reload regs we use
6194 mark_reload_reg_in_use (spill_regs
[i
], rld
[r
].opnum
,
6195 rld
[r
].when_needed
, rld
[r
].mode
);
6197 rld
[r
].reg_rtx
= reg
;
6198 reload_spill_index
[r
] = spill_regs
[i
];
6205 /* Find a spill register to use as a reload register for reload R.
6206 LAST_RELOAD is nonzero if this is the last reload for the insn being
6209 Set rld[R].reg_rtx to the register allocated.
6211 We return 1 if successful, or 0 if we couldn't find a spill reg and
6212 we didn't change anything. */
6215 allocate_reload_reg (struct insn_chain
*chain ATTRIBUTE_UNUSED
, int r
,
6220 /* If we put this reload ahead, thinking it is a group,
6221 then insist on finding a group. Otherwise we can grab a
6222 reg that some other reload needs.
6223 (That can happen when we have a 68000 DATA_OR_FP_REG
6224 which is a group of data regs or one fp reg.)
6225 We need not be so restrictive if there are no more reloads
6228 ??? Really it would be nicer to have smarter handling
6229 for that kind of reg class, where a problem like this is normal.
6230 Perhaps those classes should be avoided for reloading
6231 by use of more alternatives. */
6233 int force_group
= rld
[r
].nregs
> 1 && ! last_reload
;
6235 /* If we want a single register and haven't yet found one,
6236 take any reg in the right class and not in use.
6237 If we want a consecutive group, here is where we look for it.
6239 We use three passes so we can first look for reload regs to
6240 reuse, which are already in use for other reloads in this insn,
6241 and only then use additional registers which are not "bad", then
6242 finally any register.
6244 I think that maximizing reuse is needed to make sure we don't
6245 run out of reload regs. Suppose we have three reloads, and
6246 reloads A and B can share regs. These need two regs.
6247 Suppose A and B are given different regs.
6248 That leaves none for C. */
6249 for (pass
= 0; pass
< 3; pass
++)
6251 /* I is the index in spill_regs.
6252 We advance it round-robin between insns to use all spill regs
6253 equally, so that inherited reloads have a chance
6254 of leapfrogging each other. */
6258 for (count
= 0; count
< n_spills
; count
++)
6260 int rclass
= (int) rld
[r
].rclass
;
6266 regnum
= spill_regs
[i
];
6268 if ((reload_reg_free_p (regnum
, rld
[r
].opnum
,
6271 /* We check reload_reg_used to make sure we
6272 don't clobber the return register. */
6273 && ! TEST_HARD_REG_BIT (reload_reg_used
, regnum
)
6274 && free_for_value_p (regnum
, rld
[r
].mode
, rld
[r
].opnum
,
6275 rld
[r
].when_needed
, rld
[r
].in
,
6277 && TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regnum
)
6278 && HARD_REGNO_MODE_OK (regnum
, rld
[r
].mode
)
6279 /* Look first for regs to share, then for unshared. But
6280 don't share regs used for inherited reloads; they are
6281 the ones we want to preserve. */
6283 || (TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6285 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit
,
6288 int nr
= hard_regno_nregs
[regnum
][rld
[r
].mode
];
6290 /* During the second pass we want to avoid reload registers
6291 which are "bad" for this reload. */
6293 && ira_bad_reload_regno (regnum
, rld
[r
].in
, rld
[r
].out
))
6296 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6297 (on 68000) got us two FP regs. If NR is 1,
6298 we would reject both of them. */
6301 /* If we need only one reg, we have already won. */
6304 /* But reject a single reg if we demand a group. */
6309 /* Otherwise check that as many consecutive regs as we need
6310 are available here. */
6313 int regno
= regnum
+ nr
- 1;
6314 if (!(TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
)
6315 && spill_reg_order
[regno
] >= 0
6316 && reload_reg_free_p (regno
, rld
[r
].opnum
,
6317 rld
[r
].when_needed
)))
6326 /* If we found something on the current pass, omit later passes. */
6327 if (count
< n_spills
)
6331 /* We should have found a spill register by now. */
6332 if (count
>= n_spills
)
6335 /* I is the index in SPILL_REG_RTX of the reload register we are to
6336 allocate. Get an rtx for it and find its register number. */
6338 return set_reload_reg (i
, r
);
6341 /* Initialize all the tables needed to allocate reload registers.
6342 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6343 is the array we use to restore the reg_rtx field for every reload. */
6346 choose_reload_regs_init (struct insn_chain
*chain
, rtx
*save_reload_reg_rtx
)
6350 for (i
= 0; i
< n_reloads
; i
++)
6351 rld
[i
].reg_rtx
= save_reload_reg_rtx
[i
];
6353 memset (reload_inherited
, 0, MAX_RELOADS
);
6354 memset (reload_inheritance_insn
, 0, MAX_RELOADS
* sizeof (rtx
));
6355 memset (reload_override_in
, 0, MAX_RELOADS
* sizeof (rtx
));
6357 CLEAR_HARD_REG_SET (reload_reg_used
);
6358 CLEAR_HARD_REG_SET (reload_reg_used_at_all
);
6359 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr
);
6360 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload
);
6361 CLEAR_HARD_REG_SET (reload_reg_used_in_insn
);
6362 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr
);
6364 CLEAR_HARD_REG_SET (reg_used_in_insn
);
6367 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->live_throughout
);
6368 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6369 REG_SET_TO_HARD_REG_SET (tmp
, &chain
->dead_or_set
);
6370 IOR_HARD_REG_SET (reg_used_in_insn
, tmp
);
6371 compute_use_by_pseudos (®_used_in_insn
, &chain
->live_throughout
);
6372 compute_use_by_pseudos (®_used_in_insn
, &chain
->dead_or_set
);
6375 for (i
= 0; i
< reload_n_operands
; i
++)
6377 CLEAR_HARD_REG_SET (reload_reg_used_in_output
[i
]);
6378 CLEAR_HARD_REG_SET (reload_reg_used_in_input
[i
]);
6379 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr
[i
]);
6380 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr
[i
]);
6381 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr
[i
]);
6382 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr
[i
]);
6385 COMPL_HARD_REG_SET (reload_reg_unavailable
, chain
->used_spill_regs
);
6387 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit
);
6389 for (i
= 0; i
< n_reloads
; i
++)
6390 /* If we have already decided to use a certain register,
6391 don't use it in another way. */
6393 mark_reload_reg_in_use (REGNO (rld
[i
].reg_rtx
), rld
[i
].opnum
,
6394 rld
[i
].when_needed
, rld
[i
].mode
);
6397 #ifdef SECONDARY_MEMORY_NEEDED
6398 /* If X is not a subreg, return it unmodified. If it is a subreg,
6399 look up whether we made a replacement for the SUBREG_REG. Return
6400 either the replacement or the SUBREG_REG. */
6403 replaced_subreg (rtx x
)
6405 if (GET_CODE (x
) == SUBREG
)
6406 return find_replacement (&SUBREG_REG (x
));
6411 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6412 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6413 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6414 otherwise it is NULL. */
6417 compute_reload_subreg_offset (machine_mode outermode
,
6419 machine_mode innermode
)
6422 machine_mode middlemode
;
6425 return subreg_lowpart_offset (outermode
, innermode
);
6427 outer_offset
= SUBREG_BYTE (subreg
);
6428 middlemode
= GET_MODE (SUBREG_REG (subreg
));
6430 /* If SUBREG is paradoxical then return the normal lowpart offset
6431 for OUTERMODE and INNERMODE. Our caller has already checked
6432 that OUTERMODE fits in INNERMODE. */
6433 if (outer_offset
== 0
6434 && GET_MODE_SIZE (outermode
) > GET_MODE_SIZE (middlemode
))
6435 return subreg_lowpart_offset (outermode
, innermode
);
6437 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6438 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6439 return outer_offset
+ subreg_lowpart_offset (middlemode
, innermode
);
6442 /* Assign hard reg targets for the pseudo-registers we must reload
6443 into hard regs for this insn.
6444 Also output the instructions to copy them in and out of the hard regs.
6446 For machines with register classes, we are responsible for
6447 finding a reload reg in the proper class. */
6450 choose_reload_regs (struct insn_chain
*chain
)
6452 rtx_insn
*insn
= chain
->insn
;
6454 unsigned int max_group_size
= 1;
6455 enum reg_class group_class
= NO_REGS
;
6456 int pass
, win
, inheritance
;
6458 rtx save_reload_reg_rtx
[MAX_RELOADS
];
6460 /* In order to be certain of getting the registers we need,
6461 we must sort the reloads into order of increasing register class.
6462 Then our grabbing of reload registers will parallel the process
6463 that provided the reload registers.
6465 Also note whether any of the reloads wants a consecutive group of regs.
6466 If so, record the maximum size of the group desired and what
6467 register class contains all the groups needed by this insn. */
6469 for (j
= 0; j
< n_reloads
; j
++)
6471 reload_order
[j
] = j
;
6472 if (rld
[j
].reg_rtx
!= NULL_RTX
)
6474 gcc_assert (REG_P (rld
[j
].reg_rtx
)
6475 && HARD_REGISTER_P (rld
[j
].reg_rtx
));
6476 reload_spill_index
[j
] = REGNO (rld
[j
].reg_rtx
);
6479 reload_spill_index
[j
] = -1;
6481 if (rld
[j
].nregs
> 1)
6483 max_group_size
= MAX (rld
[j
].nregs
, max_group_size
);
6485 = reg_class_superunion
[(int) rld
[j
].rclass
][(int) group_class
];
6488 save_reload_reg_rtx
[j
] = rld
[j
].reg_rtx
;
6492 qsort (reload_order
, n_reloads
, sizeof (short), reload_reg_class_lower
);
6494 /* If -O, try first with inheritance, then turning it off.
6495 If not -O, don't do inheritance.
6496 Using inheritance when not optimizing leads to paradoxes
6497 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6498 because one side of the comparison might be inherited. */
6500 for (inheritance
= optimize
> 0; inheritance
>= 0; inheritance
--)
6502 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
6504 /* Process the reloads in order of preference just found.
6505 Beyond this point, subregs can be found in reload_reg_rtx.
6507 This used to look for an existing reloaded home for all of the
6508 reloads, and only then perform any new reloads. But that could lose
6509 if the reloads were done out of reg-class order because a later
6510 reload with a looser constraint might have an old home in a register
6511 needed by an earlier reload with a tighter constraint.
6513 To solve this, we make two passes over the reloads, in the order
6514 described above. In the first pass we try to inherit a reload
6515 from a previous insn. If there is a later reload that needs a
6516 class that is a proper subset of the class being processed, we must
6517 also allocate a spill register during the first pass.
6519 Then make a second pass over the reloads to allocate any reloads
6520 that haven't been given registers yet. */
6522 for (j
= 0; j
< n_reloads
; j
++)
6524 int r
= reload_order
[j
];
6525 rtx search_equiv
= NULL_RTX
;
6527 /* Ignore reloads that got marked inoperative. */
6528 if (rld
[r
].out
== 0 && rld
[r
].in
== 0
6529 && ! rld
[r
].secondary_p
)
6532 /* If find_reloads chose to use reload_in or reload_out as a reload
6533 register, we don't need to chose one. Otherwise, try even if it
6534 found one since we might save an insn if we find the value lying
6536 Try also when reload_in is a pseudo without a hard reg. */
6537 if (rld
[r
].in
!= 0 && rld
[r
].reg_rtx
!= 0
6538 && (rtx_equal_p (rld
[r
].in
, rld
[r
].reg_rtx
)
6539 || (rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)
6540 && !MEM_P (rld
[r
].in
)
6541 && true_regnum (rld
[r
].in
) < FIRST_PSEUDO_REGISTER
)))
6544 #if 0 /* No longer needed for correct operation.
6545 It might give better code, or might not; worth an experiment? */
6546 /* If this is an optional reload, we can't inherit from earlier insns
6547 until we are sure that any non-optional reloads have been allocated.
6548 The following code takes advantage of the fact that optional reloads
6549 are at the end of reload_order. */
6550 if (rld
[r
].optional
!= 0)
6551 for (i
= 0; i
< j
; i
++)
6552 if ((rld
[reload_order
[i
]].out
!= 0
6553 || rld
[reload_order
[i
]].in
!= 0
6554 || rld
[reload_order
[i
]].secondary_p
)
6555 && ! rld
[reload_order
[i
]].optional
6556 && rld
[reload_order
[i
]].reg_rtx
== 0)
6557 allocate_reload_reg (chain
, reload_order
[i
], 0);
6560 /* First see if this pseudo is already available as reloaded
6561 for a previous insn. We cannot try to inherit for reloads
6562 that are smaller than the maximum number of registers needed
6563 for groups unless the register we would allocate cannot be used
6566 We could check here to see if this is a secondary reload for
6567 an object that is already in a register of the desired class.
6568 This would avoid the need for the secondary reload register.
6569 But this is complex because we can't easily determine what
6570 objects might want to be loaded via this reload. So let a
6571 register be allocated here. In `emit_reload_insns' we suppress
6572 one of the loads in the case described above. */
6578 machine_mode mode
= VOIDmode
;
6579 rtx subreg
= NULL_RTX
;
6583 else if (REG_P (rld
[r
].in
))
6585 regno
= REGNO (rld
[r
].in
);
6586 mode
= GET_MODE (rld
[r
].in
);
6588 else if (REG_P (rld
[r
].in_reg
))
6590 regno
= REGNO (rld
[r
].in_reg
);
6591 mode
= GET_MODE (rld
[r
].in_reg
);
6593 else if (GET_CODE (rld
[r
].in_reg
) == SUBREG
6594 && REG_P (SUBREG_REG (rld
[r
].in_reg
)))
6596 regno
= REGNO (SUBREG_REG (rld
[r
].in_reg
));
6597 if (regno
< FIRST_PSEUDO_REGISTER
)
6598 regno
= subreg_regno (rld
[r
].in_reg
);
6601 subreg
= rld
[r
].in_reg
;
6602 byte
= SUBREG_BYTE (subreg
);
6604 mode
= GET_MODE (rld
[r
].in_reg
);
6607 else if (GET_RTX_CLASS (GET_CODE (rld
[r
].in_reg
)) == RTX_AUTOINC
6608 && REG_P (XEXP (rld
[r
].in_reg
, 0)))
6610 regno
= REGNO (XEXP (rld
[r
].in_reg
, 0));
6611 mode
= GET_MODE (XEXP (rld
[r
].in_reg
, 0));
6612 rld
[r
].out
= rld
[r
].in
;
6616 /* This won't work, since REGNO can be a pseudo reg number.
6617 Also, it takes much more hair to keep track of all the things
6618 that can invalidate an inherited reload of part of a pseudoreg. */
6619 else if (GET_CODE (rld
[r
].in
) == SUBREG
6620 && REG_P (SUBREG_REG (rld
[r
].in
)))
6621 regno
= subreg_regno (rld
[r
].in
);
6625 && reg_last_reload_reg
[regno
] != 0
6626 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg
[regno
]))
6627 >= GET_MODE_SIZE (mode
) + byte
)
6628 #ifdef CANNOT_CHANGE_MODE_CLASS
6629 /* Verify that the register it's in can be used in
6631 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg
[regno
]),
6632 GET_MODE (reg_last_reload_reg
[regno
]),
6637 enum reg_class rclass
= rld
[r
].rclass
, last_class
;
6638 rtx last_reg
= reg_last_reload_reg
[regno
];
6640 i
= REGNO (last_reg
);
6641 byte
= compute_reload_subreg_offset (mode
,
6643 GET_MODE (last_reg
));
6644 i
+= subreg_regno_offset (i
, GET_MODE (last_reg
), byte
, mode
);
6645 last_class
= REGNO_REG_CLASS (i
);
6647 if (reg_reloaded_contents
[i
] == regno
6648 && TEST_HARD_REG_BIT (reg_reloaded_valid
, i
)
6649 && HARD_REGNO_MODE_OK (i
, rld
[r
].mode
)
6650 && (TEST_HARD_REG_BIT (reg_class_contents
[(int) rclass
], i
)
6651 /* Even if we can't use this register as a reload
6652 register, we might use it for reload_override_in,
6653 if copying it to the desired class is cheap
6655 || ((register_move_cost (mode
, last_class
, rclass
)
6656 < memory_move_cost (mode
, rclass
, true))
6657 && (secondary_reload_class (1, rclass
, mode
,
6660 #ifdef SECONDARY_MEMORY_NEEDED
6661 && ! SECONDARY_MEMORY_NEEDED (last_class
, rclass
,
6666 && (rld
[r
].nregs
== max_group_size
6667 || ! TEST_HARD_REG_BIT (reg_class_contents
[(int) group_class
],
6669 && free_for_value_p (i
, rld
[r
].mode
, rld
[r
].opnum
,
6670 rld
[r
].when_needed
, rld
[r
].in
,
6673 /* If a group is needed, verify that all the subsequent
6674 registers still have their values intact. */
6675 int nr
= hard_regno_nregs
[i
][rld
[r
].mode
];
6678 for (k
= 1; k
< nr
; k
++)
6679 if (reg_reloaded_contents
[i
+ k
] != regno
6680 || ! TEST_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
))
6688 last_reg
= (GET_MODE (last_reg
) == mode
6689 ? last_reg
: gen_rtx_REG (mode
, i
));
6692 for (k
= 0; k
< nr
; k
++)
6693 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6696 /* We found a register that contains the
6697 value we need. If this register is the
6698 same as an `earlyclobber' operand of the
6699 current insn, just mark it as a place to
6700 reload from since we can't use it as the
6701 reload register itself. */
6703 for (i1
= 0; i1
< n_earlyclobbers
; i1
++)
6704 if (reg_overlap_mentioned_for_reload_p
6705 (reg_last_reload_reg
[regno
],
6706 reload_earlyclobbers
[i1
]))
6709 if (i1
!= n_earlyclobbers
6710 || ! (free_for_value_p (i
, rld
[r
].mode
,
6712 rld
[r
].when_needed
, rld
[r
].in
,
6714 /* Don't use it if we'd clobber a pseudo reg. */
6715 || (TEST_HARD_REG_BIT (reg_used_in_insn
, i
)
6717 && ! TEST_HARD_REG_BIT (reg_reloaded_dead
, i
))
6718 /* Don't clobber the frame pointer. */
6719 || (i
== HARD_FRAME_POINTER_REGNUM
6720 && frame_pointer_needed
6722 /* Don't really use the inherited spill reg
6723 if we need it wider than we've got it. */
6724 || (GET_MODE_SIZE (rld
[r
].mode
)
6725 > GET_MODE_SIZE (mode
))
6728 /* If find_reloads chose reload_out as reload
6729 register, stay with it - that leaves the
6730 inherited register for subsequent reloads. */
6731 || (rld
[r
].out
&& rld
[r
].reg_rtx
6732 && rtx_equal_p (rld
[r
].out
, rld
[r
].reg_rtx
)))
6734 if (! rld
[r
].optional
)
6736 reload_override_in
[r
] = last_reg
;
6737 reload_inheritance_insn
[r
]
6738 = reg_reloaded_insn
[i
];
6744 /* We can use this as a reload reg. */
6745 /* Mark the register as in use for this part of
6747 mark_reload_reg_in_use (i
,
6751 rld
[r
].reg_rtx
= last_reg
;
6752 reload_inherited
[r
] = 1;
6753 reload_inheritance_insn
[r
]
6754 = reg_reloaded_insn
[i
];
6755 reload_spill_index
[r
] = i
;
6756 for (k
= 0; k
< nr
; k
++)
6757 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6765 /* Here's another way to see if the value is already lying around. */
6768 && ! reload_inherited
[r
]
6770 && (CONSTANT_P (rld
[r
].in
)
6771 || GET_CODE (rld
[r
].in
) == PLUS
6772 || REG_P (rld
[r
].in
)
6773 || MEM_P (rld
[r
].in
))
6774 && (rld
[r
].nregs
== max_group_size
6775 || ! reg_classes_intersect_p (rld
[r
].rclass
, group_class
)))
6776 search_equiv
= rld
[r
].in
;
6781 = find_equiv_reg (search_equiv
, insn
, rld
[r
].rclass
,
6782 -1, NULL
, 0, rld
[r
].mode
);
6788 regno
= REGNO (equiv
);
6791 /* This must be a SUBREG of a hard register.
6792 Make a new REG since this might be used in an
6793 address and not all machines support SUBREGs
6795 gcc_assert (GET_CODE (equiv
) == SUBREG
);
6796 regno
= subreg_regno (equiv
);
6797 equiv
= gen_rtx_REG (rld
[r
].mode
, regno
);
6798 /* If we choose EQUIV as the reload register, but the
6799 loop below decides to cancel the inheritance, we'll
6800 end up reloading EQUIV in rld[r].mode, not the mode
6801 it had originally. That isn't safe when EQUIV isn't
6802 available as a spill register since its value might
6803 still be live at this point. */
6804 for (i
= regno
; i
< regno
+ (int) rld
[r
].nregs
; i
++)
6805 if (TEST_HARD_REG_BIT (reload_reg_unavailable
, i
))
6810 /* If we found a spill reg, reject it unless it is free
6811 and of the desired class. */
6815 int bad_for_class
= 0;
6816 int max_regno
= regno
+ rld
[r
].nregs
;
6818 for (i
= regno
; i
< max_regno
; i
++)
6820 regs_used
|= TEST_HARD_REG_BIT (reload_reg_used_at_all
,
6822 bad_for_class
|= ! TEST_HARD_REG_BIT (reg_class_contents
[(int) rld
[r
].rclass
],
6827 && ! free_for_value_p (regno
, rld
[r
].mode
,
6828 rld
[r
].opnum
, rld
[r
].when_needed
,
6829 rld
[r
].in
, rld
[r
].out
, r
, 1))
6834 if (equiv
!= 0 && ! HARD_REGNO_MODE_OK (regno
, rld
[r
].mode
))
6837 /* We found a register that contains the value we need.
6838 If this register is the same as an `earlyclobber' operand
6839 of the current insn, just mark it as a place to reload from
6840 since we can't use it as the reload register itself. */
6843 for (i
= 0; i
< n_earlyclobbers
; i
++)
6844 if (reg_overlap_mentioned_for_reload_p (equiv
,
6845 reload_earlyclobbers
[i
]))
6847 if (! rld
[r
].optional
)
6848 reload_override_in
[r
] = equiv
;
6853 /* If the equiv register we have found is explicitly clobbered
6854 in the current insn, it depends on the reload type if we
6855 can use it, use it for reload_override_in, or not at all.
6856 In particular, we then can't use EQUIV for a
6857 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6861 if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 2))
6862 switch (rld
[r
].when_needed
)
6864 case RELOAD_FOR_OTHER_ADDRESS
:
6865 case RELOAD_FOR_INPADDR_ADDRESS
:
6866 case RELOAD_FOR_INPUT_ADDRESS
:
6867 case RELOAD_FOR_OPADDR_ADDR
:
6870 case RELOAD_FOR_INPUT
:
6871 case RELOAD_FOR_OPERAND_ADDRESS
:
6872 if (! rld
[r
].optional
)
6873 reload_override_in
[r
] = equiv
;
6879 else if (regno_clobbered_p (regno
, insn
, rld
[r
].mode
, 1))
6880 switch (rld
[r
].when_needed
)
6882 case RELOAD_FOR_OTHER_ADDRESS
:
6883 case RELOAD_FOR_INPADDR_ADDRESS
:
6884 case RELOAD_FOR_INPUT_ADDRESS
:
6885 case RELOAD_FOR_OPADDR_ADDR
:
6886 case RELOAD_FOR_OPERAND_ADDRESS
:
6887 case RELOAD_FOR_INPUT
:
6890 if (! rld
[r
].optional
)
6891 reload_override_in
[r
] = equiv
;
6899 /* If we found an equivalent reg, say no code need be generated
6900 to load it, and use it as our reload reg. */
6902 && (regno
!= HARD_FRAME_POINTER_REGNUM
6903 || !frame_pointer_needed
))
6905 int nr
= hard_regno_nregs
[regno
][rld
[r
].mode
];
6907 rld
[r
].reg_rtx
= equiv
;
6908 reload_spill_index
[r
] = regno
;
6909 reload_inherited
[r
] = 1;
6911 /* If reg_reloaded_valid is not set for this register,
6912 there might be a stale spill_reg_store lying around.
6913 We must clear it, since otherwise emit_reload_insns
6914 might delete the store. */
6915 if (! TEST_HARD_REG_BIT (reg_reloaded_valid
, regno
))
6916 spill_reg_store
[regno
] = NULL
;
6917 /* If any of the hard registers in EQUIV are spill
6918 registers, mark them as in use for this insn. */
6919 for (k
= 0; k
< nr
; k
++)
6921 i
= spill_reg_order
[regno
+ k
];
6924 mark_reload_reg_in_use (regno
, rld
[r
].opnum
,
6927 SET_HARD_REG_BIT (reload_reg_used_for_inherit
,
6934 /* If we found a register to use already, or if this is an optional
6935 reload, we are done. */
6936 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
!= 0)
6940 /* No longer needed for correct operation. Might or might
6941 not give better code on the average. Want to experiment? */
6943 /* See if there is a later reload that has a class different from our
6944 class that intersects our class or that requires less register
6945 than our reload. If so, we must allocate a register to this
6946 reload now, since that reload might inherit a previous reload
6947 and take the only available register in our class. Don't do this
6948 for optional reloads since they will force all previous reloads
6949 to be allocated. Also don't do this for reloads that have been
6952 for (i
= j
+ 1; i
< n_reloads
; i
++)
6954 int s
= reload_order
[i
];
6956 if ((rld
[s
].in
== 0 && rld
[s
].out
== 0
6957 && ! rld
[s
].secondary_p
)
6961 if ((rld
[s
].rclass
!= rld
[r
].rclass
6962 && reg_classes_intersect_p (rld
[r
].rclass
,
6964 || rld
[s
].nregs
< rld
[r
].nregs
)
6971 allocate_reload_reg (chain
, r
, j
== n_reloads
- 1);
6975 /* Now allocate reload registers for anything non-optional that
6976 didn't get one yet. */
6977 for (j
= 0; j
< n_reloads
; j
++)
6979 int r
= reload_order
[j
];
6981 /* Ignore reloads that got marked inoperative. */
6982 if (rld
[r
].out
== 0 && rld
[r
].in
== 0 && ! rld
[r
].secondary_p
)
6985 /* Skip reloads that already have a register allocated or are
6987 if (rld
[r
].reg_rtx
!= 0 || rld
[r
].optional
)
6990 if (! allocate_reload_reg (chain
, r
, j
== n_reloads
- 1))
6994 /* If that loop got all the way, we have won. */
7001 /* Loop around and try without any inheritance. */
7006 /* First undo everything done by the failed attempt
7007 to allocate with inheritance. */
7008 choose_reload_regs_init (chain
, save_reload_reg_rtx
);
7010 /* Some sanity tests to verify that the reloads found in the first
7011 pass are identical to the ones we have now. */
7012 gcc_assert (chain
->n_reloads
== n_reloads
);
7014 for (i
= 0; i
< n_reloads
; i
++)
7016 if (chain
->rld
[i
].regno
< 0 || chain
->rld
[i
].reg_rtx
!= 0)
7018 gcc_assert (chain
->rld
[i
].when_needed
== rld
[i
].when_needed
);
7019 for (j
= 0; j
< n_spills
; j
++)
7020 if (spill_regs
[j
] == chain
->rld
[i
].regno
)
7021 if (! set_reload_reg (j
, i
))
7022 failed_reload (chain
->insn
, i
);
7026 /* If we thought we could inherit a reload, because it seemed that
7027 nothing else wanted the same reload register earlier in the insn,
7028 verify that assumption, now that all reloads have been assigned.
7029 Likewise for reloads where reload_override_in has been set. */
7031 /* If doing expensive optimizations, do one preliminary pass that doesn't
7032 cancel any inheritance, but removes reloads that have been needed only
7033 for reloads that we know can be inherited. */
7034 for (pass
= flag_expensive_optimizations
; pass
>= 0; pass
--)
7036 for (j
= 0; j
< n_reloads
; j
++)
7038 int r
= reload_order
[j
];
7040 #ifdef SECONDARY_MEMORY_NEEDED
7043 if (reload_inherited
[r
] && rld
[r
].reg_rtx
)
7044 check_reg
= rld
[r
].reg_rtx
;
7045 else if (reload_override_in
[r
]
7046 && (REG_P (reload_override_in
[r
])
7047 || GET_CODE (reload_override_in
[r
]) == SUBREG
))
7048 check_reg
= reload_override_in
[r
];
7051 if (! free_for_value_p (true_regnum (check_reg
), rld
[r
].mode
,
7052 rld
[r
].opnum
, rld
[r
].when_needed
, rld
[r
].in
,
7053 (reload_inherited
[r
]
7054 ? rld
[r
].out
: const0_rtx
),
7059 reload_inherited
[r
] = 0;
7060 reload_override_in
[r
] = 0;
7062 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7063 reload_override_in, then we do not need its related
7064 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7065 likewise for other reload types.
7066 We handle this by removing a reload when its only replacement
7067 is mentioned in reload_in of the reload we are going to inherit.
7068 A special case are auto_inc expressions; even if the input is
7069 inherited, we still need the address for the output. We can
7070 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7071 If we succeeded removing some reload and we are doing a preliminary
7072 pass just to remove such reloads, make another pass, since the
7073 removal of one reload might allow us to inherit another one. */
7075 && rld
[r
].out
!= rld
[r
].in
7076 && remove_address_replacements (rld
[r
].in
))
7081 #ifdef SECONDARY_MEMORY_NEEDED
7082 /* If we needed a memory location for the reload, we also have to
7083 remove its related reloads. */
7085 && rld
[r
].out
!= rld
[r
].in
7086 && (tem
= replaced_subreg (rld
[r
].in
), REG_P (tem
))
7087 && REGNO (tem
) < FIRST_PSEUDO_REGISTER
7088 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem
)),
7089 rld
[r
].rclass
, rld
[r
].inmode
)
7090 && remove_address_replacements
7091 (get_secondary_mem (tem
, rld
[r
].inmode
, rld
[r
].opnum
,
7092 rld
[r
].when_needed
)))
7101 /* Now that reload_override_in is known valid,
7102 actually override reload_in. */
7103 for (j
= 0; j
< n_reloads
; j
++)
7104 if (reload_override_in
[j
])
7105 rld
[j
].in
= reload_override_in
[j
];
7107 /* If this reload won't be done because it has been canceled or is
7108 optional and not inherited, clear reload_reg_rtx so other
7109 routines (such as subst_reloads) don't get confused. */
7110 for (j
= 0; j
< n_reloads
; j
++)
7111 if (rld
[j
].reg_rtx
!= 0
7112 && ((rld
[j
].optional
&& ! reload_inherited
[j
])
7113 || (rld
[j
].in
== 0 && rld
[j
].out
== 0
7114 && ! rld
[j
].secondary_p
)))
7116 int regno
= true_regnum (rld
[j
].reg_rtx
);
7118 if (spill_reg_order
[regno
] >= 0)
7119 clear_reload_reg_in_use (regno
, rld
[j
].opnum
,
7120 rld
[j
].when_needed
, rld
[j
].mode
);
7122 reload_spill_index
[j
] = -1;
7125 /* Record which pseudos and which spill regs have output reloads. */
7126 for (j
= 0; j
< n_reloads
; j
++)
7128 int r
= reload_order
[j
];
7130 i
= reload_spill_index
[r
];
7132 /* I is nonneg if this reload uses a register.
7133 If rld[r].reg_rtx is 0, this is an optional reload
7134 that we opted to ignore. */
7135 if (rld
[r
].out_reg
!= 0 && REG_P (rld
[r
].out_reg
)
7136 && rld
[r
].reg_rtx
!= 0)
7138 int nregno
= REGNO (rld
[r
].out_reg
);
7141 if (nregno
< FIRST_PSEUDO_REGISTER
)
7142 nr
= hard_regno_nregs
[nregno
][rld
[r
].mode
];
7145 SET_REGNO_REG_SET (®_has_output_reload
,
7149 add_to_hard_reg_set (®_is_output_reload
, rld
[r
].mode
, i
);
7151 gcc_assert (rld
[r
].when_needed
== RELOAD_OTHER
7152 || rld
[r
].when_needed
== RELOAD_FOR_OUTPUT
7153 || rld
[r
].when_needed
== RELOAD_FOR_INSN
);
7158 /* Deallocate the reload register for reload R. This is called from
7159 remove_address_replacements. */
7162 deallocate_reload_reg (int r
)
7166 if (! rld
[r
].reg_rtx
)
7168 regno
= true_regnum (rld
[r
].reg_rtx
);
7170 if (spill_reg_order
[regno
] >= 0)
7171 clear_reload_reg_in_use (regno
, rld
[r
].opnum
, rld
[r
].when_needed
,
7173 reload_spill_index
[r
] = -1;
7176 /* These arrays are filled by emit_reload_insns and its subroutines. */
7177 static rtx_insn
*input_reload_insns
[MAX_RECOG_OPERANDS
];
7178 static rtx_insn
*other_input_address_reload_insns
= 0;
7179 static rtx_insn
*other_input_reload_insns
= 0;
7180 static rtx_insn
*input_address_reload_insns
[MAX_RECOG_OPERANDS
];
7181 static rtx_insn
*inpaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7182 static rtx_insn
*output_reload_insns
[MAX_RECOG_OPERANDS
];
7183 static rtx_insn
*output_address_reload_insns
[MAX_RECOG_OPERANDS
];
7184 static rtx_insn
*outaddr_address_reload_insns
[MAX_RECOG_OPERANDS
];
7185 static rtx_insn
*operand_reload_insns
= 0;
7186 static rtx_insn
*other_operand_reload_insns
= 0;
7187 static rtx_insn
*other_output_reload_insns
[MAX_RECOG_OPERANDS
];
7189 /* Values to be put in spill_reg_store are put here first. Instructions
7190 must only be placed here if the associated reload register reaches
7191 the end of the instruction's reload sequence. */
7192 static rtx_insn
*new_spill_reg_store
[FIRST_PSEUDO_REGISTER
];
7193 static HARD_REG_SET reg_reloaded_died
;
7195 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7196 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7197 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7198 adjusted register, and return true. Otherwise, return false. */
7200 reload_adjust_reg_for_temp (rtx
*reload_reg
, rtx alt_reload_reg
,
7201 enum reg_class new_class
,
7202 machine_mode new_mode
)
7207 for (reg
= *reload_reg
; reg
; reg
= alt_reload_reg
, alt_reload_reg
= 0)
7209 unsigned regno
= REGNO (reg
);
7211 if (!TEST_HARD_REG_BIT (reg_class_contents
[(int) new_class
], regno
))
7213 if (GET_MODE (reg
) != new_mode
)
7215 if (!HARD_REGNO_MODE_OK (regno
, new_mode
))
7217 if (hard_regno_nregs
[regno
][new_mode
]
7218 > hard_regno_nregs
[regno
][GET_MODE (reg
)])
7220 reg
= reload_adjust_reg_for_mode (reg
, new_mode
);
7228 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7229 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7230 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7231 adjusted register, and return true. Otherwise, return false. */
7233 reload_adjust_reg_for_icode (rtx
*reload_reg
, rtx alt_reload_reg
,
7234 enum insn_code icode
)
7237 enum reg_class new_class
= scratch_reload_class (icode
);
7238 machine_mode new_mode
= insn_data
[(int) icode
].operand
[2].mode
;
7240 return reload_adjust_reg_for_temp (reload_reg
, alt_reload_reg
,
7241 new_class
, new_mode
);
7244 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7245 has the number J. OLD contains the value to be used as input. */
7248 emit_input_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7251 rtx_insn
*insn
= chain
->insn
;
7253 rtx oldequiv_reg
= 0;
7259 /* delete_output_reload is only invoked properly if old contains
7260 the original pseudo register. Since this is replaced with a
7261 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7262 find the pseudo in RELOAD_IN_REG. This is also used to
7263 determine whether a secondary reload is needed. */
7264 if (reload_override_in
[j
]
7265 && (REG_P (rl
->in_reg
)
7266 || (GET_CODE (rl
->in_reg
) == SUBREG
7267 && REG_P (SUBREG_REG (rl
->in_reg
)))))
7274 else if (REG_P (oldequiv
))
7275 oldequiv_reg
= oldequiv
;
7276 else if (GET_CODE (oldequiv
) == SUBREG
)
7277 oldequiv_reg
= SUBREG_REG (oldequiv
);
7279 reloadreg
= reload_reg_rtx_for_input
[j
];
7280 mode
= GET_MODE (reloadreg
);
7282 /* If we are reloading from a register that was recently stored in
7283 with an output-reload, see if we can prove there was
7284 actually no need to store the old value in it. */
7286 if (optimize
&& REG_P (oldequiv
)
7287 && REGNO (oldequiv
) < FIRST_PSEUDO_REGISTER
7288 && spill_reg_store
[REGNO (oldequiv
)]
7290 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (oldequiv
)])
7291 || rtx_equal_p (spill_reg_stored_to
[REGNO (oldequiv
)],
7293 delete_output_reload (insn
, j
, REGNO (oldequiv
), reloadreg
);
7295 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7298 while (GET_CODE (oldequiv
) == SUBREG
&& GET_MODE (oldequiv
) != mode
)
7299 oldequiv
= SUBREG_REG (oldequiv
);
7300 if (GET_MODE (oldequiv
) != VOIDmode
7301 && mode
!= GET_MODE (oldequiv
))
7302 oldequiv
= gen_lowpart_SUBREG (mode
, oldequiv
);
7304 /* Switch to the right place to emit the reload insns. */
7305 switch (rl
->when_needed
)
7308 where
= &other_input_reload_insns
;
7310 case RELOAD_FOR_INPUT
:
7311 where
= &input_reload_insns
[rl
->opnum
];
7313 case RELOAD_FOR_INPUT_ADDRESS
:
7314 where
= &input_address_reload_insns
[rl
->opnum
];
7316 case RELOAD_FOR_INPADDR_ADDRESS
:
7317 where
= &inpaddr_address_reload_insns
[rl
->opnum
];
7319 case RELOAD_FOR_OUTPUT_ADDRESS
:
7320 where
= &output_address_reload_insns
[rl
->opnum
];
7322 case RELOAD_FOR_OUTADDR_ADDRESS
:
7323 where
= &outaddr_address_reload_insns
[rl
->opnum
];
7325 case RELOAD_FOR_OPERAND_ADDRESS
:
7326 where
= &operand_reload_insns
;
7328 case RELOAD_FOR_OPADDR_ADDR
:
7329 where
= &other_operand_reload_insns
;
7331 case RELOAD_FOR_OTHER_ADDRESS
:
7332 where
= &other_input_address_reload_insns
;
7338 push_to_sequence (*where
);
7340 /* Auto-increment addresses must be reloaded in a special way. */
7341 if (rl
->out
&& ! rl
->out_reg
)
7343 /* We are not going to bother supporting the case where a
7344 incremented register can't be copied directly from
7345 OLDEQUIV since this seems highly unlikely. */
7346 gcc_assert (rl
->secondary_in_reload
< 0);
7348 if (reload_inherited
[j
])
7349 oldequiv
= reloadreg
;
7351 old
= XEXP (rl
->in_reg
, 0);
7353 /* Prevent normal processing of this reload. */
7355 /* Output a special code sequence for this case. */
7356 inc_for_reload (reloadreg
, oldequiv
, rl
->out
, rl
->inc
);
7359 /* If we are reloading a pseudo-register that was set by the previous
7360 insn, see if we can get rid of that pseudo-register entirely
7361 by redirecting the previous insn into our reload register. */
7363 else if (optimize
&& REG_P (old
)
7364 && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7365 && dead_or_set_p (insn
, old
)
7366 /* This is unsafe if some other reload
7367 uses the same reg first. */
7368 && ! conflicts_with_override (reloadreg
)
7369 && free_for_value_p (REGNO (reloadreg
), rl
->mode
, rl
->opnum
,
7370 rl
->when_needed
, old
, rl
->out
, j
, 0))
7372 rtx_insn
*temp
= PREV_INSN (insn
);
7373 while (temp
&& (NOTE_P (temp
) || DEBUG_INSN_P (temp
)))
7374 temp
= PREV_INSN (temp
);
7376 && NONJUMP_INSN_P (temp
)
7377 && GET_CODE (PATTERN (temp
)) == SET
7378 && SET_DEST (PATTERN (temp
)) == old
7379 /* Make sure we can access insn_operand_constraint. */
7380 && asm_noperands (PATTERN (temp
)) < 0
7381 /* This is unsafe if operand occurs more than once in current
7382 insn. Perhaps some occurrences aren't reloaded. */
7383 && count_occurrences (PATTERN (insn
), old
, 0) == 1)
7385 rtx old
= SET_DEST (PATTERN (temp
));
7386 /* Store into the reload register instead of the pseudo. */
7387 SET_DEST (PATTERN (temp
)) = reloadreg
;
7389 /* Verify that resulting insn is valid.
7391 Note that we have replaced the destination of TEMP with
7392 RELOADREG. If TEMP references RELOADREG within an
7393 autoincrement addressing mode, then the resulting insn
7394 is ill-formed and we must reject this optimization. */
7395 extract_insn (temp
);
7396 if (constrain_operands (1, get_enabled_alternatives (temp
))
7398 && ! find_reg_note (temp
, REG_INC
, reloadreg
)
7402 /* If the previous insn is an output reload, the source is
7403 a reload register, and its spill_reg_store entry will
7404 contain the previous destination. This is now
7406 if (REG_P (SET_SRC (PATTERN (temp
)))
7407 && REGNO (SET_SRC (PATTERN (temp
))) < FIRST_PSEUDO_REGISTER
)
7409 spill_reg_store
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7410 spill_reg_stored_to
[REGNO (SET_SRC (PATTERN (temp
)))] = 0;
7413 /* If these are the only uses of the pseudo reg,
7414 pretend for GDB it lives in the reload reg we used. */
7415 if (REG_N_DEATHS (REGNO (old
)) == 1
7416 && REG_N_SETS (REGNO (old
)) == 1)
7418 reg_renumber
[REGNO (old
)] = REGNO (reloadreg
);
7419 if (ira_conflicts_p
)
7420 /* Inform IRA about the change. */
7421 ira_mark_allocation_change (REGNO (old
));
7422 alter_reg (REGNO (old
), -1, false);
7426 /* Adjust any debug insns between temp and insn. */
7427 while ((temp
= NEXT_INSN (temp
)) != insn
)
7428 if (DEBUG_INSN_P (temp
))
7429 replace_rtx (PATTERN (temp
), old
, reloadreg
);
7431 gcc_assert (NOTE_P (temp
));
7435 SET_DEST (PATTERN (temp
)) = old
;
7440 /* We can't do that, so output an insn to load RELOADREG. */
7442 /* If we have a secondary reload, pick up the secondary register
7443 and icode, if any. If OLDEQUIV and OLD are different or
7444 if this is an in-out reload, recompute whether or not we
7445 still need a secondary register and what the icode should
7446 be. If we still need a secondary register and the class or
7447 icode is different, go back to reloading from OLD if using
7448 OLDEQUIV means that we got the wrong type of register. We
7449 cannot have different class or icode due to an in-out reload
7450 because we don't make such reloads when both the input and
7451 output need secondary reload registers. */
7453 if (! special
&& rl
->secondary_in_reload
>= 0)
7455 rtx second_reload_reg
= 0;
7456 rtx third_reload_reg
= 0;
7457 int secondary_reload
= rl
->secondary_in_reload
;
7458 rtx real_oldequiv
= oldequiv
;
7461 enum insn_code icode
;
7462 enum insn_code tertiary_icode
= CODE_FOR_nothing
;
7464 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7465 and similarly for OLD.
7466 See comments in get_secondary_reload in reload.c. */
7467 /* If it is a pseudo that cannot be replaced with its
7468 equivalent MEM, we must fall back to reload_in, which
7469 will have all the necessary substitutions registered.
7470 Likewise for a pseudo that can't be replaced with its
7471 equivalent constant.
7473 Take extra care for subregs of such pseudos. Note that
7474 we cannot use reg_equiv_mem in this case because it is
7475 not in the right mode. */
7478 if (GET_CODE (tmp
) == SUBREG
)
7479 tmp
= SUBREG_REG (tmp
);
7481 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7482 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7483 || reg_equiv_constant (REGNO (tmp
)) != 0))
7485 if (! reg_equiv_mem (REGNO (tmp
))
7486 || num_not_at_initial_offset
7487 || GET_CODE (oldequiv
) == SUBREG
)
7488 real_oldequiv
= rl
->in
;
7490 real_oldequiv
= reg_equiv_mem (REGNO (tmp
));
7494 if (GET_CODE (tmp
) == SUBREG
)
7495 tmp
= SUBREG_REG (tmp
);
7497 && REGNO (tmp
) >= FIRST_PSEUDO_REGISTER
7498 && (reg_equiv_memory_loc (REGNO (tmp
)) != 0
7499 || reg_equiv_constant (REGNO (tmp
)) != 0))
7501 if (! reg_equiv_mem (REGNO (tmp
))
7502 || num_not_at_initial_offset
7503 || GET_CODE (old
) == SUBREG
)
7506 real_old
= reg_equiv_mem (REGNO (tmp
));
7509 second_reload_reg
= rld
[secondary_reload
].reg_rtx
;
7510 if (rld
[secondary_reload
].secondary_in_reload
>= 0)
7512 int tertiary_reload
= rld
[secondary_reload
].secondary_in_reload
;
7514 third_reload_reg
= rld
[tertiary_reload
].reg_rtx
;
7515 tertiary_icode
= rld
[secondary_reload
].secondary_in_icode
;
7516 /* We'd have to add more code for quartary reloads. */
7517 gcc_assert (rld
[tertiary_reload
].secondary_in_reload
< 0);
7519 icode
= rl
->secondary_in_icode
;
7521 if ((old
!= oldequiv
&& ! rtx_equal_p (old
, oldequiv
))
7522 || (rl
->in
!= 0 && rl
->out
!= 0))
7524 secondary_reload_info sri
, sri2
;
7525 enum reg_class new_class
, new_t_class
;
7527 sri
.icode
= CODE_FOR_nothing
;
7528 sri
.prev_sri
= NULL
;
7530 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7534 if (new_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
7535 second_reload_reg
= 0;
7536 else if (new_class
== NO_REGS
)
7538 if (reload_adjust_reg_for_icode (&second_reload_reg
,
7540 (enum insn_code
) sri
.icode
))
7542 icode
= (enum insn_code
) sri
.icode
;
7543 third_reload_reg
= 0;
7548 real_oldequiv
= real_old
;
7551 else if (sri
.icode
!= CODE_FOR_nothing
)
7552 /* We currently lack a way to express this in reloads. */
7556 sri2
.icode
= CODE_FOR_nothing
;
7557 sri2
.prev_sri
= &sri
;
7559 = (enum reg_class
) targetm
.secondary_reload (1, real_oldequiv
,
7562 if (new_t_class
== NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7564 if (reload_adjust_reg_for_temp (&second_reload_reg
,
7568 third_reload_reg
= 0;
7569 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7574 real_oldequiv
= real_old
;
7577 else if (new_t_class
== NO_REGS
&& sri2
.icode
!= CODE_FOR_nothing
)
7579 rtx intermediate
= second_reload_reg
;
7581 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7583 && reload_adjust_reg_for_icode (&third_reload_reg
, NULL
,
7587 second_reload_reg
= intermediate
;
7588 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7593 real_oldequiv
= real_old
;
7596 else if (new_t_class
!= NO_REGS
&& sri2
.icode
== CODE_FOR_nothing
)
7598 rtx intermediate
= second_reload_reg
;
7600 if (reload_adjust_reg_for_temp (&intermediate
, NULL
,
7602 && reload_adjust_reg_for_temp (&third_reload_reg
, NULL
,
7605 second_reload_reg
= intermediate
;
7606 tertiary_icode
= (enum insn_code
) sri2
.icode
;
7611 real_oldequiv
= real_old
;
7616 /* This could be handled more intelligently too. */
7618 real_oldequiv
= real_old
;
7623 /* If we still need a secondary reload register, check
7624 to see if it is being used as a scratch or intermediate
7625 register and generate code appropriately. If we need
7626 a scratch register, use REAL_OLDEQUIV since the form of
7627 the insn may depend on the actual address if it is
7630 if (second_reload_reg
)
7632 if (icode
!= CODE_FOR_nothing
)
7634 /* We'd have to add extra code to handle this case. */
7635 gcc_assert (!third_reload_reg
);
7637 emit_insn (GEN_FCN (icode
) (reloadreg
, real_oldequiv
,
7638 second_reload_reg
));
7643 /* See if we need a scratch register to load the
7644 intermediate register (a tertiary reload). */
7645 if (tertiary_icode
!= CODE_FOR_nothing
)
7647 emit_insn ((GEN_FCN (tertiary_icode
)
7648 (second_reload_reg
, real_oldequiv
,
7649 third_reload_reg
)));
7651 else if (third_reload_reg
)
7653 gen_reload (third_reload_reg
, real_oldequiv
,
7656 gen_reload (second_reload_reg
, third_reload_reg
,
7661 gen_reload (second_reload_reg
, real_oldequiv
,
7665 oldequiv
= second_reload_reg
;
7670 if (! special
&& ! rtx_equal_p (reloadreg
, oldequiv
))
7672 rtx real_oldequiv
= oldequiv
;
7674 if ((REG_P (oldequiv
)
7675 && REGNO (oldequiv
) >= FIRST_PSEUDO_REGISTER
7676 && (reg_equiv_memory_loc (REGNO (oldequiv
)) != 0
7677 || reg_equiv_constant (REGNO (oldequiv
)) != 0))
7678 || (GET_CODE (oldequiv
) == SUBREG
7679 && REG_P (SUBREG_REG (oldequiv
))
7680 && (REGNO (SUBREG_REG (oldequiv
))
7681 >= FIRST_PSEUDO_REGISTER
)
7682 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv
))) != 0)
7683 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv
))) != 0)))
7684 || (CONSTANT_P (oldequiv
)
7685 && (targetm
.preferred_reload_class (oldequiv
,
7686 REGNO_REG_CLASS (REGNO (reloadreg
)))
7688 real_oldequiv
= rl
->in
;
7689 gen_reload (reloadreg
, real_oldequiv
, rl
->opnum
,
7693 if (cfun
->can_throw_non_call_exceptions
)
7694 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7696 /* End this sequence. */
7697 *where
= get_insns ();
7700 /* Update reload_override_in so that delete_address_reloads_1
7701 can see the actual register usage. */
7703 reload_override_in
[j
] = oldequiv
;
7706 /* Generate insns to for the output reload RL, which is for the insn described
7707 by CHAIN and has the number J. */
7709 emit_output_reload_insns (struct insn_chain
*chain
, struct reload
*rl
,
7713 rtx_insn
*insn
= chain
->insn
;
7720 if (rl
->when_needed
== RELOAD_OTHER
)
7723 push_to_sequence (output_reload_insns
[rl
->opnum
]);
7725 rl_reg_rtx
= reload_reg_rtx_for_output
[j
];
7726 mode
= GET_MODE (rl_reg_rtx
);
7728 reloadreg
= rl_reg_rtx
;
7730 /* If we need two reload regs, set RELOADREG to the intermediate
7731 one, since it will be stored into OLD. We might need a secondary
7732 register only for an input reload, so check again here. */
7734 if (rl
->secondary_out_reload
>= 0)
7737 int secondary_reload
= rl
->secondary_out_reload
;
7738 int tertiary_reload
= rld
[secondary_reload
].secondary_out_reload
;
7740 if (REG_P (old
) && REGNO (old
) >= FIRST_PSEUDO_REGISTER
7741 && reg_equiv_mem (REGNO (old
)) != 0)
7742 real_old
= reg_equiv_mem (REGNO (old
));
7744 if (secondary_reload_class (0, rl
->rclass
, mode
, real_old
) != NO_REGS
)
7746 rtx second_reloadreg
= reloadreg
;
7747 reloadreg
= rld
[secondary_reload
].reg_rtx
;
7749 /* See if RELOADREG is to be used as a scratch register
7750 or as an intermediate register. */
7751 if (rl
->secondary_out_icode
!= CODE_FOR_nothing
)
7753 /* We'd have to add extra code to handle this case. */
7754 gcc_assert (tertiary_reload
< 0);
7756 emit_insn ((GEN_FCN (rl
->secondary_out_icode
)
7757 (real_old
, second_reloadreg
, reloadreg
)));
7762 /* See if we need both a scratch and intermediate reload
7765 enum insn_code tertiary_icode
7766 = rld
[secondary_reload
].secondary_out_icode
;
7768 /* We'd have to add more code for quartary reloads. */
7769 gcc_assert (tertiary_reload
< 0
7770 || rld
[tertiary_reload
].secondary_out_reload
< 0);
7772 if (GET_MODE (reloadreg
) != mode
)
7773 reloadreg
= reload_adjust_reg_for_mode (reloadreg
, mode
);
7775 if (tertiary_icode
!= CODE_FOR_nothing
)
7777 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7779 /* Copy primary reload reg to secondary reload reg.
7780 (Note that these have been swapped above, then
7781 secondary reload reg to OLD using our insn.) */
7783 /* If REAL_OLD is a paradoxical SUBREG, remove it
7784 and try to put the opposite SUBREG on
7786 strip_paradoxical_subreg (&real_old
, &reloadreg
);
7788 gen_reload (reloadreg
, second_reloadreg
,
7789 rl
->opnum
, rl
->when_needed
);
7790 emit_insn ((GEN_FCN (tertiary_icode
)
7791 (real_old
, reloadreg
, third_reloadreg
)));
7797 /* Copy between the reload regs here and then to
7800 gen_reload (reloadreg
, second_reloadreg
,
7801 rl
->opnum
, rl
->when_needed
);
7802 if (tertiary_reload
>= 0)
7804 rtx third_reloadreg
= rld
[tertiary_reload
].reg_rtx
;
7806 gen_reload (third_reloadreg
, reloadreg
,
7807 rl
->opnum
, rl
->when_needed
);
7808 reloadreg
= third_reloadreg
;
7815 /* Output the last reload insn. */
7820 /* Don't output the last reload if OLD is not the dest of
7821 INSN and is in the src and is clobbered by INSN. */
7822 if (! flag_expensive_optimizations
7824 || !(set
= single_set (insn
))
7825 || rtx_equal_p (old
, SET_DEST (set
))
7826 || !reg_mentioned_p (old
, SET_SRC (set
))
7827 || !((REGNO (old
) < FIRST_PSEUDO_REGISTER
)
7828 && regno_clobbered_p (REGNO (old
), insn
, rl
->mode
, 0)))
7829 gen_reload (old
, reloadreg
, rl
->opnum
,
7833 /* Look at all insns we emitted, just to be safe. */
7834 for (p
= get_insns (); p
; p
= NEXT_INSN (p
))
7837 rtx pat
= PATTERN (p
);
7839 /* If this output reload doesn't come from a spill reg,
7840 clear any memory of reloaded copies of the pseudo reg.
7841 If this output reload comes from a spill reg,
7842 reg_has_output_reload will make this do nothing. */
7843 note_stores (pat
, forget_old_reloads_1
, NULL
);
7845 if (reg_mentioned_p (rl_reg_rtx
, pat
))
7847 rtx set
= single_set (insn
);
7848 if (reload_spill_index
[j
] < 0
7850 && SET_SRC (set
) == rl_reg_rtx
)
7852 int src
= REGNO (SET_SRC (set
));
7854 reload_spill_index
[j
] = src
;
7855 SET_HARD_REG_BIT (reg_is_output_reload
, src
);
7856 if (find_regno_note (insn
, REG_DEAD
, src
))
7857 SET_HARD_REG_BIT (reg_reloaded_died
, src
);
7859 if (HARD_REGISTER_P (rl_reg_rtx
))
7861 int s
= rl
->secondary_out_reload
;
7862 set
= single_set (p
);
7863 /* If this reload copies only to the secondary reload
7864 register, the secondary reload does the actual
7866 if (s
>= 0 && set
== NULL_RTX
)
7867 /* We can't tell what function the secondary reload
7868 has and where the actual store to the pseudo is
7869 made; leave new_spill_reg_store alone. */
7872 && SET_SRC (set
) == rl_reg_rtx
7873 && SET_DEST (set
) == rld
[s
].reg_rtx
)
7875 /* Usually the next instruction will be the
7876 secondary reload insn; if we can confirm
7877 that it is, setting new_spill_reg_store to
7878 that insn will allow an extra optimization. */
7879 rtx s_reg
= rld
[s
].reg_rtx
;
7880 rtx_insn
*next
= NEXT_INSN (p
);
7881 rld
[s
].out
= rl
->out
;
7882 rld
[s
].out_reg
= rl
->out_reg
;
7883 set
= single_set (next
);
7884 if (set
&& SET_SRC (set
) == s_reg
7885 && reload_reg_rtx_reaches_end_p (s_reg
, s
))
7887 SET_HARD_REG_BIT (reg_is_output_reload
,
7889 new_spill_reg_store
[REGNO (s_reg
)] = next
;
7892 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx
, j
))
7893 new_spill_reg_store
[REGNO (rl_reg_rtx
)] = p
;
7898 if (rl
->when_needed
== RELOAD_OTHER
)
7900 emit_insn (other_output_reload_insns
[rl
->opnum
]);
7901 other_output_reload_insns
[rl
->opnum
] = get_insns ();
7904 output_reload_insns
[rl
->opnum
] = get_insns ();
7906 if (cfun
->can_throw_non_call_exceptions
)
7907 copy_reg_eh_region_note_forward (insn
, get_insns (), NULL
);
7912 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7913 and has the number J. */
7915 do_input_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
7917 rtx_insn
*insn
= chain
->insn
;
7918 rtx old
= (rl
->in
&& MEM_P (rl
->in
)
7919 ? rl
->in_reg
: rl
->in
);
7920 rtx reg_rtx
= rl
->reg_rtx
;
7926 /* Determine the mode to reload in.
7927 This is very tricky because we have three to choose from.
7928 There is the mode the insn operand wants (rl->inmode).
7929 There is the mode of the reload register RELOADREG.
7930 There is the intrinsic mode of the operand, which we could find
7931 by stripping some SUBREGs.
7932 It turns out that RELOADREG's mode is irrelevant:
7933 we can change that arbitrarily.
7935 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7936 then the reload reg may not support QImode moves, so use SImode.
7937 If foo is in memory due to spilling a pseudo reg, this is safe,
7938 because the QImode value is in the least significant part of a
7939 slot big enough for a SImode. If foo is some other sort of
7940 memory reference, then it is impossible to reload this case,
7941 so previous passes had better make sure this never happens.
7943 Then consider a one-word union which has SImode and one of its
7944 members is a float, being fetched as (SUBREG:SF union:SI).
7945 We must fetch that as SFmode because we could be loading into
7946 a float-only register. In this case OLD's mode is correct.
7948 Consider an immediate integer: it has VOIDmode. Here we need
7949 to get a mode from something else.
7951 In some cases, there is a fourth mode, the operand's
7952 containing mode. If the insn specifies a containing mode for
7953 this operand, it overrides all others.
7955 I am not sure whether the algorithm here is always right,
7956 but it does the right things in those cases. */
7958 mode
= GET_MODE (old
);
7959 if (mode
== VOIDmode
)
7962 /* We cannot use gen_lowpart_common since it can do the wrong thing
7963 when REG_RTX has a multi-word mode. Note that REG_RTX must
7964 always be a REG here. */
7965 if (GET_MODE (reg_rtx
) != mode
)
7966 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
7968 reload_reg_rtx_for_input
[j
] = reg_rtx
;
7971 /* AUTO_INC reloads need to be handled even if inherited. We got an
7972 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7973 && (! reload_inherited
[j
] || (rl
->out
&& ! rl
->out_reg
))
7974 && ! rtx_equal_p (reg_rtx
, old
)
7976 emit_input_reload_insns (chain
, rld
+ j
, old
, j
);
7978 /* When inheriting a wider reload, we have a MEM in rl->in,
7979 e.g. inheriting a SImode output reload for
7980 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7981 if (optimize
&& reload_inherited
[j
] && rl
->in
7983 && MEM_P (rl
->in_reg
)
7984 && reload_spill_index
[j
] >= 0
7985 && TEST_HARD_REG_BIT (reg_reloaded_valid
, reload_spill_index
[j
]))
7986 rl
->in
= regno_reg_rtx
[reg_reloaded_contents
[reload_spill_index
[j
]]];
7988 /* If we are reloading a register that was recently stored in with an
7989 output-reload, see if we can prove there was
7990 actually no need to store the old value in it. */
7993 && (reload_inherited
[j
] || reload_override_in
[j
])
7996 && spill_reg_store
[REGNO (reg_rtx
)] != 0
7998 /* There doesn't seem to be any reason to restrict this to pseudos
7999 and doing so loses in the case where we are copying from a
8000 register of the wrong class. */
8001 && !HARD_REGISTER_P (spill_reg_stored_to
[REGNO (reg_rtx
)])
8003 /* The insn might have already some references to stackslots
8004 replaced by MEMs, while reload_out_reg still names the
8006 && (dead_or_set_p (insn
, spill_reg_stored_to
[REGNO (reg_rtx
)])
8007 || rtx_equal_p (spill_reg_stored_to
[REGNO (reg_rtx
)], rl
->out_reg
)))
8008 delete_output_reload (insn
, j
, REGNO (reg_rtx
), reg_rtx
);
8011 /* Do output reloading for reload RL, which is for the insn described by
8012 CHAIN and has the number J.
8013 ??? At some point we need to support handling output reloads of
8014 JUMP_INSNs or insns that set cc0. */
8016 do_output_reload (struct insn_chain
*chain
, struct reload
*rl
, int j
)
8019 rtx_insn
*insn
= chain
->insn
;
8020 /* If this is an output reload that stores something that is
8021 not loaded in this same reload, see if we can eliminate a previous
8023 rtx pseudo
= rl
->out_reg
;
8024 rtx reg_rtx
= rl
->reg_rtx
;
8026 if (rl
->out
&& reg_rtx
)
8030 /* Determine the mode to reload in.
8031 See comments above (for input reloading). */
8032 mode
= GET_MODE (rl
->out
);
8033 if (mode
== VOIDmode
)
8035 /* VOIDmode should never happen for an output. */
8036 if (asm_noperands (PATTERN (insn
)) < 0)
8037 /* It's the compiler's fault. */
8038 fatal_insn ("VOIDmode on an output", insn
);
8039 error_for_asm (insn
, "output operand is constant in %<asm%>");
8040 /* Prevent crash--use something we know is valid. */
8042 rl
->out
= gen_rtx_REG (mode
, REGNO (reg_rtx
));
8044 if (GET_MODE (reg_rtx
) != mode
)
8045 reg_rtx
= reload_adjust_reg_for_mode (reg_rtx
, mode
);
8047 reload_reg_rtx_for_output
[j
] = reg_rtx
;
8052 && ! rtx_equal_p (rl
->in_reg
, pseudo
)
8053 && REGNO (pseudo
) >= FIRST_PSEUDO_REGISTER
8054 && reg_last_reload_reg
[REGNO (pseudo
)])
8056 int pseudo_no
= REGNO (pseudo
);
8057 int last_regno
= REGNO (reg_last_reload_reg
[pseudo_no
]);
8059 /* We don't need to test full validity of last_regno for
8060 inherit here; we only want to know if the store actually
8061 matches the pseudo. */
8062 if (TEST_HARD_REG_BIT (reg_reloaded_valid
, last_regno
)
8063 && reg_reloaded_contents
[last_regno
] == pseudo_no
8064 && spill_reg_store
[last_regno
]
8065 && rtx_equal_p (pseudo
, spill_reg_stored_to
[last_regno
]))
8066 delete_output_reload (insn
, j
, last_regno
, reg_rtx
);
8072 || rtx_equal_p (old
, reg_rtx
))
8075 /* An output operand that dies right away does need a reload,
8076 but need not be copied from it. Show the new location in the
8078 if ((REG_P (old
) || GET_CODE (old
) == SCRATCH
)
8079 && (note
= find_reg_note (insn
, REG_UNUSED
, old
)) != 0)
8081 XEXP (note
, 0) = reg_rtx
;
8084 /* Likewise for a SUBREG of an operand that dies. */
8085 else if (GET_CODE (old
) == SUBREG
8086 && REG_P (SUBREG_REG (old
))
8087 && 0 != (note
= find_reg_note (insn
, REG_UNUSED
,
8090 XEXP (note
, 0) = gen_lowpart_common (GET_MODE (old
), reg_rtx
);
8093 else if (GET_CODE (old
) == SCRATCH
)
8094 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8095 but we don't want to make an output reload. */
8098 /* If is a JUMP_INSN, we can't support output reloads yet. */
8099 gcc_assert (NONJUMP_INSN_P (insn
));
8101 emit_output_reload_insns (chain
, rld
+ j
, j
);
8104 /* A reload copies values of MODE from register SRC to register DEST.
8105 Return true if it can be treated for inheritance purposes like a
8106 group of reloads, each one reloading a single hard register. The
8107 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8108 occupy the same number of hard registers. */
8111 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED
,
8112 int src ATTRIBUTE_UNUSED
,
8113 machine_mode mode ATTRIBUTE_UNUSED
)
8115 #ifdef CANNOT_CHANGE_MODE_CLASS
8116 return (!REG_CANNOT_CHANGE_MODE_P (dest
, mode
, reg_raw_mode
[dest
])
8117 && !REG_CANNOT_CHANGE_MODE_P (src
, mode
, reg_raw_mode
[src
]));
8123 /* Output insns to reload values in and out of the chosen reload regs. */
8126 emit_reload_insns (struct insn_chain
*chain
)
8128 rtx_insn
*insn
= chain
->insn
;
8132 CLEAR_HARD_REG_SET (reg_reloaded_died
);
8134 for (j
= 0; j
< reload_n_operands
; j
++)
8135 input_reload_insns
[j
] = input_address_reload_insns
[j
]
8136 = inpaddr_address_reload_insns
[j
]
8137 = output_reload_insns
[j
] = output_address_reload_insns
[j
]
8138 = outaddr_address_reload_insns
[j
]
8139 = other_output_reload_insns
[j
] = 0;
8140 other_input_address_reload_insns
= 0;
8141 other_input_reload_insns
= 0;
8142 operand_reload_insns
= 0;
8143 other_operand_reload_insns
= 0;
8145 /* Dump reloads into the dump file. */
8148 fprintf (dump_file
, "\nReloads for insn # %d\n", INSN_UID (insn
));
8149 debug_reload_to_stream (dump_file
);
8152 for (j
= 0; j
< n_reloads
; j
++)
8153 if (rld
[j
].reg_rtx
&& HARD_REGISTER_P (rld
[j
].reg_rtx
))
8157 for (i
= REGNO (rld
[j
].reg_rtx
); i
< END_REGNO (rld
[j
].reg_rtx
); i
++)
8158 new_spill_reg_store
[i
] = 0;
8161 /* Now output the instructions to copy the data into and out of the
8162 reload registers. Do these in the order that the reloads were reported,
8163 since reloads of base and index registers precede reloads of operands
8164 and the operands may need the base and index registers reloaded. */
8166 for (j
= 0; j
< n_reloads
; j
++)
8168 do_input_reload (chain
, rld
+ j
, j
);
8169 do_output_reload (chain
, rld
+ j
, j
);
8172 /* Now write all the insns we made for reloads in the order expected by
8173 the allocation functions. Prior to the insn being reloaded, we write
8174 the following reloads:
8176 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8178 RELOAD_OTHER reloads.
8180 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8181 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8182 RELOAD_FOR_INPUT reload for the operand.
8184 RELOAD_FOR_OPADDR_ADDRS reloads.
8186 RELOAD_FOR_OPERAND_ADDRESS reloads.
8188 After the insn being reloaded, we write the following:
8190 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8191 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8192 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8193 reloads for the operand. The RELOAD_OTHER output reloads are
8194 output in descending order by reload number. */
8196 emit_insn_before (other_input_address_reload_insns
, insn
);
8197 emit_insn_before (other_input_reload_insns
, insn
);
8199 for (j
= 0; j
< reload_n_operands
; j
++)
8201 emit_insn_before (inpaddr_address_reload_insns
[j
], insn
);
8202 emit_insn_before (input_address_reload_insns
[j
], insn
);
8203 emit_insn_before (input_reload_insns
[j
], insn
);
8206 emit_insn_before (other_operand_reload_insns
, insn
);
8207 emit_insn_before (operand_reload_insns
, insn
);
8209 for (j
= 0; j
< reload_n_operands
; j
++)
8211 rtx_insn
*x
= emit_insn_after (outaddr_address_reload_insns
[j
], insn
);
8212 x
= emit_insn_after (output_address_reload_insns
[j
], x
);
8213 x
= emit_insn_after (output_reload_insns
[j
], x
);
8214 emit_insn_after (other_output_reload_insns
[j
], x
);
8217 /* For all the spill regs newly reloaded in this instruction,
8218 record what they were reloaded from, so subsequent instructions
8219 can inherit the reloads.
8221 Update spill_reg_store for the reloads of this insn.
8222 Copy the elements that were updated in the loop above. */
8224 for (j
= 0; j
< n_reloads
; j
++)
8226 int r
= reload_order
[j
];
8227 int i
= reload_spill_index
[r
];
8229 /* If this is a non-inherited input reload from a pseudo, we must
8230 clear any memory of a previous store to the same pseudo. Only do
8231 something if there will not be an output reload for the pseudo
8233 if (rld
[r
].in_reg
!= 0
8234 && ! (reload_inherited
[r
] || reload_override_in
[r
]))
8236 rtx reg
= rld
[r
].in_reg
;
8238 if (GET_CODE (reg
) == SUBREG
)
8239 reg
= SUBREG_REG (reg
);
8242 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
8243 && !REGNO_REG_SET_P (®_has_output_reload
, REGNO (reg
)))
8245 int nregno
= REGNO (reg
);
8247 if (reg_last_reload_reg
[nregno
])
8249 int last_regno
= REGNO (reg_last_reload_reg
[nregno
]);
8251 if (reg_reloaded_contents
[last_regno
] == nregno
)
8252 spill_reg_store
[last_regno
] = 0;
8257 /* I is nonneg if this reload used a register.
8258 If rld[r].reg_rtx is 0, this is an optional reload
8259 that we opted to ignore. */
8261 if (i
>= 0 && rld
[r
].reg_rtx
!= 0)
8263 int nr
= hard_regno_nregs
[i
][GET_MODE (rld
[r
].reg_rtx
)];
8266 /* For a multi register reload, we need to check if all or part
8267 of the value lives to the end. */
8268 for (k
= 0; k
< nr
; k
++)
8269 if (reload_reg_reaches_end_p (i
+ k
, r
))
8270 CLEAR_HARD_REG_BIT (reg_reloaded_valid
, i
+ k
);
8272 /* Maybe the spill reg contains a copy of reload_out. */
8274 && (REG_P (rld
[r
].out
)
8276 ? REG_P (rld
[r
].out_reg
)
8277 /* The reload value is an auto-modification of
8278 some kind. For PRE_INC, POST_INC, PRE_DEC
8279 and POST_DEC, we record an equivalence
8280 between the reload register and the operand
8281 on the optimistic assumption that we can make
8282 the equivalence hold. reload_as_needed must
8283 then either make it hold or invalidate the
8286 PRE_MODIFY and POST_MODIFY addresses are reloaded
8287 somewhat differently, and allowing them here leads
8289 : (GET_CODE (rld
[r
].out
) != POST_MODIFY
8290 && GET_CODE (rld
[r
].out
) != PRE_MODIFY
))))
8294 reg
= reload_reg_rtx_for_output
[r
];
8295 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8297 machine_mode mode
= GET_MODE (reg
);
8298 int regno
= REGNO (reg
);
8299 int nregs
= hard_regno_nregs
[regno
][mode
];
8300 rtx out
= (REG_P (rld
[r
].out
)
8304 /* AUTO_INC */ : XEXP (rld
[r
].in_reg
, 0));
8305 int out_regno
= REGNO (out
);
8306 int out_nregs
= (!HARD_REGISTER_NUM_P (out_regno
) ? 1
8307 : hard_regno_nregs
[out_regno
][mode
]);
8310 spill_reg_store
[regno
] = new_spill_reg_store
[regno
];
8311 spill_reg_stored_to
[regno
] = out
;
8312 reg_last_reload_reg
[out_regno
] = reg
;
8314 piecemeal
= (HARD_REGISTER_NUM_P (out_regno
)
8315 && nregs
== out_nregs
8316 && inherit_piecemeal_p (out_regno
, regno
, mode
));
8318 /* If OUT_REGNO is a hard register, it may occupy more than
8319 one register. If it does, say what is in the
8320 rest of the registers assuming that both registers
8321 agree on how many words the object takes. If not,
8322 invalidate the subsequent registers. */
8324 if (HARD_REGISTER_NUM_P (out_regno
))
8325 for (k
= 1; k
< out_nregs
; k
++)
8326 reg_last_reload_reg
[out_regno
+ k
]
8327 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8329 /* Now do the inverse operation. */
8330 for (k
= 0; k
< nregs
; k
++)
8332 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8333 reg_reloaded_contents
[regno
+ k
]
8334 = (!HARD_REGISTER_NUM_P (out_regno
) || !piecemeal
8337 reg_reloaded_insn
[regno
+ k
] = insn
;
8338 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8339 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8340 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8343 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8348 /* Maybe the spill reg contains a copy of reload_in. Only do
8349 something if there will not be an output reload for
8350 the register being reloaded. */
8351 else if (rld
[r
].out_reg
== 0
8353 && ((REG_P (rld
[r
].in
)
8354 && !HARD_REGISTER_P (rld
[r
].in
)
8355 && !REGNO_REG_SET_P (®_has_output_reload
,
8357 || (REG_P (rld
[r
].in_reg
)
8358 && !REGNO_REG_SET_P (®_has_output_reload
,
8359 REGNO (rld
[r
].in_reg
))))
8360 && !reg_set_p (reload_reg_rtx_for_input
[r
], PATTERN (insn
)))
8364 reg
= reload_reg_rtx_for_input
[r
];
8365 if (reload_reg_rtx_reaches_end_p (reg
, r
))
8375 mode
= GET_MODE (reg
);
8376 regno
= REGNO (reg
);
8377 nregs
= hard_regno_nregs
[regno
][mode
];
8378 if (REG_P (rld
[r
].in
)
8379 && REGNO (rld
[r
].in
) >= FIRST_PSEUDO_REGISTER
)
8381 else if (REG_P (rld
[r
].in_reg
))
8384 in
= XEXP (rld
[r
].in_reg
, 0);
8385 in_regno
= REGNO (in
);
8387 in_nregs
= (!HARD_REGISTER_NUM_P (in_regno
) ? 1
8388 : hard_regno_nregs
[in_regno
][mode
]);
8390 reg_last_reload_reg
[in_regno
] = reg
;
8392 piecemeal
= (HARD_REGISTER_NUM_P (in_regno
)
8393 && nregs
== in_nregs
8394 && inherit_piecemeal_p (regno
, in_regno
, mode
));
8396 if (HARD_REGISTER_NUM_P (in_regno
))
8397 for (k
= 1; k
< in_nregs
; k
++)
8398 reg_last_reload_reg
[in_regno
+ k
]
8399 = (piecemeal
? regno_reg_rtx
[regno
+ k
] : 0);
8401 /* Unless we inherited this reload, show we haven't
8402 recently done a store.
8403 Previous stores of inherited auto_inc expressions
8404 also have to be discarded. */
8405 if (! reload_inherited
[r
]
8406 || (rld
[r
].out
&& ! rld
[r
].out_reg
))
8407 spill_reg_store
[regno
] = 0;
8409 for (k
= 0; k
< nregs
; k
++)
8411 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, regno
+ k
);
8412 reg_reloaded_contents
[regno
+ k
]
8413 = (!HARD_REGISTER_NUM_P (in_regno
) || !piecemeal
8416 reg_reloaded_insn
[regno
+ k
] = insn
;
8417 SET_HARD_REG_BIT (reg_reloaded_valid
, regno
+ k
);
8418 if (HARD_REGNO_CALL_PART_CLOBBERED (regno
+ k
, mode
))
8419 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8422 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8429 /* The following if-statement was #if 0'd in 1.34 (or before...).
8430 It's reenabled in 1.35 because supposedly nothing else
8431 deals with this problem. */
8433 /* If a register gets output-reloaded from a non-spill register,
8434 that invalidates any previous reloaded copy of it.
8435 But forget_old_reloads_1 won't get to see it, because
8436 it thinks only about the original insn. So invalidate it here.
8437 Also do the same thing for RELOAD_OTHER constraints where the
8438 output is discarded. */
8440 && ((rld
[r
].out
!= 0
8441 && (REG_P (rld
[r
].out
)
8442 || (MEM_P (rld
[r
].out
)
8443 && REG_P (rld
[r
].out_reg
))))
8444 || (rld
[r
].out
== 0 && rld
[r
].out_reg
8445 && REG_P (rld
[r
].out_reg
))))
8447 rtx out
= ((rld
[r
].out
&& REG_P (rld
[r
].out
))
8448 ? rld
[r
].out
: rld
[r
].out_reg
);
8449 int out_regno
= REGNO (out
);
8450 machine_mode mode
= GET_MODE (out
);
8452 /* REG_RTX is now set or clobbered by the main instruction.
8453 As the comment above explains, forget_old_reloads_1 only
8454 sees the original instruction, and there is no guarantee
8455 that the original instruction also clobbered REG_RTX.
8456 For example, if find_reloads sees that the input side of
8457 a matched operand pair dies in this instruction, it may
8458 use the input register as the reload register.
8460 Calling forget_old_reloads_1 is a waste of effort if
8461 REG_RTX is also the output register.
8463 If we know that REG_RTX holds the value of a pseudo
8464 register, the code after the call will record that fact. */
8465 if (rld
[r
].reg_rtx
&& rld
[r
].reg_rtx
!= out
)
8466 forget_old_reloads_1 (rld
[r
].reg_rtx
, NULL_RTX
, NULL
);
8468 if (!HARD_REGISTER_NUM_P (out_regno
))
8471 rtx_insn
*store_insn
= NULL
;
8473 reg_last_reload_reg
[out_regno
] = 0;
8475 /* If we can find a hard register that is stored, record
8476 the storing insn so that we may delete this insn with
8477 delete_output_reload. */
8478 src_reg
= reload_reg_rtx_for_output
[r
];
8482 if (reload_reg_rtx_reaches_end_p (src_reg
, r
))
8483 store_insn
= new_spill_reg_store
[REGNO (src_reg
)];
8489 /* If this is an optional reload, try to find the
8490 source reg from an input reload. */
8491 rtx set
= single_set (insn
);
8492 if (set
&& SET_DEST (set
) == rld
[r
].out
)
8496 src_reg
= SET_SRC (set
);
8498 for (k
= 0; k
< n_reloads
; k
++)
8500 if (rld
[k
].in
== src_reg
)
8502 src_reg
= reload_reg_rtx_for_input
[k
];
8508 if (src_reg
&& REG_P (src_reg
)
8509 && REGNO (src_reg
) < FIRST_PSEUDO_REGISTER
)
8511 int src_regno
, src_nregs
, k
;
8514 gcc_assert (GET_MODE (src_reg
) == mode
);
8515 src_regno
= REGNO (src_reg
);
8516 src_nregs
= hard_regno_nregs
[src_regno
][mode
];
8517 /* The place where to find a death note varies with
8518 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8519 necessarily checked exactly in the code that moves
8520 notes, so just check both locations. */
8521 note
= find_regno_note (insn
, REG_DEAD
, src_regno
);
8522 if (! note
&& store_insn
)
8523 note
= find_regno_note (store_insn
, REG_DEAD
, src_regno
);
8524 for (k
= 0; k
< src_nregs
; k
++)
8526 spill_reg_store
[src_regno
+ k
] = store_insn
;
8527 spill_reg_stored_to
[src_regno
+ k
] = out
;
8528 reg_reloaded_contents
[src_regno
+ k
] = out_regno
;
8529 reg_reloaded_insn
[src_regno
+ k
] = store_insn
;
8530 CLEAR_HARD_REG_BIT (reg_reloaded_dead
, src_regno
+ k
);
8531 SET_HARD_REG_BIT (reg_reloaded_valid
, src_regno
+ k
);
8532 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno
+ k
,
8534 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8537 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered
,
8539 SET_HARD_REG_BIT (reg_is_output_reload
, src_regno
+ k
);
8541 SET_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8543 CLEAR_HARD_REG_BIT (reg_reloaded_died
, src_regno
);
8545 reg_last_reload_reg
[out_regno
] = src_reg
;
8546 /* We have to set reg_has_output_reload here, or else
8547 forget_old_reloads_1 will clear reg_last_reload_reg
8549 SET_REGNO_REG_SET (®_has_output_reload
,
8555 int k
, out_nregs
= hard_regno_nregs
[out_regno
][mode
];
8557 for (k
= 0; k
< out_nregs
; k
++)
8558 reg_last_reload_reg
[out_regno
+ k
] = 0;
8562 IOR_HARD_REG_SET (reg_reloaded_dead
, reg_reloaded_died
);
8565 /* Go through the motions to emit INSN and test if it is strictly valid.
8566 Return the emitted insn if valid, else return NULL. */
8569 emit_insn_if_valid_for_reload (rtx pat
)
8571 rtx_insn
*last
= get_last_insn ();
8574 rtx_insn
*insn
= emit_insn (pat
);
8575 code
= recog_memoized (insn
);
8579 extract_insn (insn
);
8580 /* We want constrain operands to treat this insn strictly in its
8581 validity determination, i.e., the way it would after reload has
8583 if (constrain_operands (1, get_enabled_alternatives (insn
)))
8587 delete_insns_since (last
);
8591 /* Emit code to perform a reload from IN (which may be a reload register) to
8592 OUT (which may also be a reload register). IN or OUT is from operand
8593 OPNUM with reload type TYPE.
8595 Returns first insn emitted. */
8598 gen_reload (rtx out
, rtx in
, int opnum
, enum reload_type type
)
8600 rtx_insn
*last
= get_last_insn ();
8602 #ifdef SECONDARY_MEMORY_NEEDED
8606 /* If IN is a paradoxical SUBREG, remove it and try to put the
8607 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8608 if (!strip_paradoxical_subreg (&in
, &out
))
8609 strip_paradoxical_subreg (&out
, &in
);
8611 /* How to do this reload can get quite tricky. Normally, we are being
8612 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8613 register that didn't get a hard register. In that case we can just
8614 call emit_move_insn.
8616 We can also be asked to reload a PLUS that adds a register or a MEM to
8617 another register, constant or MEM. This can occur during frame pointer
8618 elimination and while reloading addresses. This case is handled by
8619 trying to emit a single insn to perform the add. If it is not valid,
8620 we use a two insn sequence.
8622 Or we can be asked to reload an unary operand that was a fragment of
8623 an addressing mode, into a register. If it isn't recognized as-is,
8624 we try making the unop operand and the reload-register the same:
8625 (set reg:X (unop:X expr:Y))
8626 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8628 Finally, we could be called to handle an 'o' constraint by putting
8629 an address into a register. In that case, we first try to do this
8630 with a named pattern of "reload_load_address". If no such pattern
8631 exists, we just emit a SET insn and hope for the best (it will normally
8632 be valid on machines that use 'o').
8634 This entire process is made complex because reload will never
8635 process the insns we generate here and so we must ensure that
8636 they will fit their constraints and also by the fact that parts of
8637 IN might be being reloaded separately and replaced with spill registers.
8638 Because of this, we are, in some sense, just guessing the right approach
8639 here. The one listed above seems to work.
8641 ??? At some point, this whole thing needs to be rethought. */
8643 if (GET_CODE (in
) == PLUS
8644 && (REG_P (XEXP (in
, 0))
8645 || GET_CODE (XEXP (in
, 0)) == SUBREG
8646 || MEM_P (XEXP (in
, 0)))
8647 && (REG_P (XEXP (in
, 1))
8648 || GET_CODE (XEXP (in
, 1)) == SUBREG
8649 || CONSTANT_P (XEXP (in
, 1))
8650 || MEM_P (XEXP (in
, 1))))
8652 /* We need to compute the sum of a register or a MEM and another
8653 register, constant, or MEM, and put it into the reload
8654 register. The best possible way of doing this is if the machine
8655 has a three-operand ADD insn that accepts the required operands.
8657 The simplest approach is to try to generate such an insn and see if it
8658 is recognized and matches its constraints. If so, it can be used.
8660 It might be better not to actually emit the insn unless it is valid,
8661 but we need to pass the insn as an operand to `recog' and
8662 `extract_insn' and it is simpler to emit and then delete the insn if
8663 not valid than to dummy things up. */
8667 enum insn_code code
;
8669 op0
= find_replacement (&XEXP (in
, 0));
8670 op1
= find_replacement (&XEXP (in
, 1));
8672 /* Since constraint checking is strict, commutativity won't be
8673 checked, so we need to do that here to avoid spurious failure
8674 if the add instruction is two-address and the second operand
8675 of the add is the same as the reload reg, which is frequently
8676 the case. If the insn would be A = B + A, rearrange it so
8677 it will be A = A + B as constrain_operands expects. */
8679 if (REG_P (XEXP (in
, 1))
8680 && REGNO (out
) == REGNO (XEXP (in
, 1)))
8681 tem
= op0
, op0
= op1
, op1
= tem
;
8683 if (op0
!= XEXP (in
, 0) || op1
!= XEXP (in
, 1))
8684 in
= gen_rtx_PLUS (GET_MODE (in
), op0
, op1
);
8686 insn
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8690 /* If that failed, we must use a conservative two-insn sequence.
8692 Use a move to copy one operand into the reload register. Prefer
8693 to reload a constant, MEM or pseudo since the move patterns can
8694 handle an arbitrary operand. If OP1 is not a constant, MEM or
8695 pseudo and OP1 is not a valid operand for an add instruction, then
8698 After reloading one of the operands into the reload register, add
8699 the reload register to the output register.
8701 If there is another way to do this for a specific machine, a
8702 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8705 code
= optab_handler (add_optab
, GET_MODE (out
));
8707 if (CONSTANT_P (op1
) || MEM_P (op1
) || GET_CODE (op1
) == SUBREG
8709 && REGNO (op1
) >= FIRST_PSEUDO_REGISTER
)
8710 || (code
!= CODE_FOR_nothing
8711 && !insn_operand_matches (code
, 2, op1
)))
8712 tem
= op0
, op0
= op1
, op1
= tem
;
8714 gen_reload (out
, op0
, opnum
, type
);
8716 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8717 This fixes a problem on the 32K where the stack pointer cannot
8718 be used as an operand of an add insn. */
8720 if (rtx_equal_p (op0
, op1
))
8723 insn
= emit_insn_if_valid_for_reload (gen_add2_insn (out
, op1
));
8726 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8727 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8731 /* If that failed, copy the address register to the reload register.
8732 Then add the constant to the reload register. */
8734 gcc_assert (!reg_overlap_mentioned_p (out
, op0
));
8735 gen_reload (out
, op1
, opnum
, type
);
8736 insn
= emit_insn (gen_add2_insn (out
, op0
));
8737 set_dst_reg_note (insn
, REG_EQUIV
, in
, out
);
8740 #ifdef SECONDARY_MEMORY_NEEDED
8741 /* If we need a memory location to do the move, do it that way. */
8742 else if ((tem1
= replaced_subreg (in
), tem2
= replaced_subreg (out
),
8743 (REG_P (tem1
) && REG_P (tem2
)))
8744 && REGNO (tem1
) < FIRST_PSEUDO_REGISTER
8745 && REGNO (tem2
) < FIRST_PSEUDO_REGISTER
8746 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1
)),
8747 REGNO_REG_CLASS (REGNO (tem2
)),
8750 /* Get the memory to use and rewrite both registers to its mode. */
8751 rtx loc
= get_secondary_mem (in
, GET_MODE (out
), opnum
, type
);
8753 if (GET_MODE (loc
) != GET_MODE (out
))
8754 out
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (out
));
8756 if (GET_MODE (loc
) != GET_MODE (in
))
8757 in
= gen_rtx_REG (GET_MODE (loc
), reg_or_subregno (in
));
8759 gen_reload (loc
, in
, opnum
, type
);
8760 gen_reload (out
, loc
, opnum
, type
);
8763 else if (REG_P (out
) && UNARY_P (in
))
8770 op1
= find_replacement (&XEXP (in
, 0));
8771 if (op1
!= XEXP (in
, 0))
8772 in
= gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
), op1
);
8774 /* First, try a plain SET. */
8775 set
= emit_insn_if_valid_for_reload (gen_rtx_SET (out
, in
));
8779 /* If that failed, move the inner operand to the reload
8780 register, and try the same unop with the inner expression
8781 replaced with the reload register. */
8783 if (GET_MODE (op1
) != GET_MODE (out
))
8784 out_moded
= gen_rtx_REG (GET_MODE (op1
), REGNO (out
));
8788 gen_reload (out_moded
, op1
, opnum
, type
);
8790 insn
= gen_rtx_SET (out
, gen_rtx_fmt_e (GET_CODE (in
), GET_MODE (in
),
8792 insn
= emit_insn_if_valid_for_reload (insn
);
8795 set_unique_reg_note (insn
, REG_EQUIV
, in
);
8796 return as_a
<rtx_insn
*> (insn
);
8799 fatal_insn ("failure trying to reload:", set
);
8801 /* If IN is a simple operand, use gen_move_insn. */
8802 else if (OBJECT_P (in
) || GET_CODE (in
) == SUBREG
)
8804 tem
= emit_insn (gen_move_insn (out
, in
));
8805 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8806 mark_jump_label (in
, tem
, 0);
8809 #ifdef HAVE_reload_load_address
8810 else if (HAVE_reload_load_address
)
8811 emit_insn (gen_reload_load_address (out
, in
));
8814 /* Otherwise, just write (set OUT IN) and hope for the best. */
8816 emit_insn (gen_rtx_SET (out
, in
));
8818 /* Return the first insn emitted.
8819 We can not just return get_last_insn, because there may have
8820 been multiple instructions emitted. Also note that gen_move_insn may
8821 emit more than one insn itself, so we can not assume that there is one
8822 insn emitted per emit_insn_before call. */
8824 return last
? NEXT_INSN (last
) : get_insns ();
8827 /* Delete a previously made output-reload whose result we now believe
8828 is not needed. First we double-check.
8830 INSN is the insn now being processed.
8831 LAST_RELOAD_REG is the hard register number for which we want to delete
8832 the last output reload.
8833 J is the reload-number that originally used REG. The caller has made
8834 certain that reload J doesn't use REG any longer for input.
8835 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8838 delete_output_reload (rtx_insn
*insn
, int j
, int last_reload_reg
,
8841 rtx_insn
*output_reload_insn
= spill_reg_store
[last_reload_reg
];
8842 rtx reg
= spill_reg_stored_to
[last_reload_reg
];
8845 int n_inherited
= 0;
8850 /* It is possible that this reload has been only used to set another reload
8851 we eliminated earlier and thus deleted this instruction too. */
8852 if (output_reload_insn
->deleted ())
8855 /* Get the raw pseudo-register referred to. */
8857 while (GET_CODE (reg
) == SUBREG
)
8858 reg
= SUBREG_REG (reg
);
8859 substed
= reg_equiv_memory_loc (REGNO (reg
));
8861 /* This is unsafe if the operand occurs more often in the current
8862 insn than it is inherited. */
8863 for (k
= n_reloads
- 1; k
>= 0; k
--)
8865 rtx reg2
= rld
[k
].in
;
8868 if (MEM_P (reg2
) || reload_override_in
[k
])
8869 reg2
= rld
[k
].in_reg
;
8871 if (rld
[k
].out
&& ! rld
[k
].out_reg
)
8872 reg2
= XEXP (rld
[k
].in_reg
, 0);
8874 while (GET_CODE (reg2
) == SUBREG
)
8875 reg2
= SUBREG_REG (reg2
);
8876 if (rtx_equal_p (reg2
, reg
))
8878 if (reload_inherited
[k
] || reload_override_in
[k
] || k
== j
)
8884 n_occurrences
= count_occurrences (PATTERN (insn
), reg
, 0);
8885 if (CALL_P (insn
) && CALL_INSN_FUNCTION_USAGE (insn
))
8886 n_occurrences
+= count_occurrences (CALL_INSN_FUNCTION_USAGE (insn
),
8889 n_occurrences
+= count_occurrences (PATTERN (insn
),
8890 eliminate_regs (substed
, VOIDmode
,
8892 for (rtx i1
= reg_equiv_alt_mem_list (REGNO (reg
)); i1
; i1
= XEXP (i1
, 1))
8894 gcc_assert (!rtx_equal_p (XEXP (i1
, 0), substed
));
8895 n_occurrences
+= count_occurrences (PATTERN (insn
), XEXP (i1
, 0), 0);
8897 if (n_occurrences
> n_inherited
)
8900 regno
= REGNO (reg
);
8901 if (regno
>= FIRST_PSEUDO_REGISTER
)
8904 nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
8906 /* If the pseudo-reg we are reloading is no longer referenced
8907 anywhere between the store into it and here,
8908 and we're within the same basic block, then the value can only
8909 pass through the reload reg and end up here.
8910 Otherwise, give up--return. */
8911 for (rtx_insn
*i1
= NEXT_INSN (output_reload_insn
);
8912 i1
!= insn
; i1
= NEXT_INSN (i1
))
8914 if (NOTE_INSN_BASIC_BLOCK_P (i1
))
8916 if ((NONJUMP_INSN_P (i1
) || CALL_P (i1
))
8917 && refers_to_regno_p (regno
, regno
+ nregs
, PATTERN (i1
), NULL
))
8919 /* If this is USE in front of INSN, we only have to check that
8920 there are no more references than accounted for by inheritance. */
8921 while (NONJUMP_INSN_P (i1
) && GET_CODE (PATTERN (i1
)) == USE
)
8923 n_occurrences
+= rtx_equal_p (reg
, XEXP (PATTERN (i1
), 0)) != 0;
8924 i1
= NEXT_INSN (i1
);
8926 if (n_occurrences
<= n_inherited
&& i1
== insn
)
8932 /* We will be deleting the insn. Remove the spill reg information. */
8933 for (k
= hard_regno_nregs
[last_reload_reg
][GET_MODE (reg
)]; k
-- > 0; )
8935 spill_reg_store
[last_reload_reg
+ k
] = 0;
8936 spill_reg_stored_to
[last_reload_reg
+ k
] = 0;
8939 /* The caller has already checked that REG dies or is set in INSN.
8940 It has also checked that we are optimizing, and thus some
8941 inaccuracies in the debugging information are acceptable.
8942 So we could just delete output_reload_insn. But in some cases
8943 we can improve the debugging information without sacrificing
8944 optimization - maybe even improving the code: See if the pseudo
8945 reg has been completely replaced with reload regs. If so, delete
8946 the store insn and forget we had a stack slot for the pseudo. */
8947 if (rld
[j
].out
!= rld
[j
].in
8948 && REG_N_DEATHS (REGNO (reg
)) == 1
8949 && REG_N_SETS (REGNO (reg
)) == 1
8950 && REG_BASIC_BLOCK (REGNO (reg
)) >= NUM_FIXED_BLOCKS
8951 && find_regno_note (insn
, REG_DEAD
, REGNO (reg
)))
8955 /* We know that it was used only between here and the beginning of
8956 the current basic block. (We also know that the last use before
8957 INSN was the output reload we are thinking of deleting, but never
8958 mind that.) Search that range; see if any ref remains. */
8959 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8961 rtx set
= single_set (i2
);
8963 /* Uses which just store in the pseudo don't count,
8964 since if they are the only uses, they are dead. */
8965 if (set
!= 0 && SET_DEST (set
) == reg
)
8967 if (LABEL_P (i2
) || JUMP_P (i2
))
8969 if ((NONJUMP_INSN_P (i2
) || CALL_P (i2
))
8970 && reg_mentioned_p (reg
, PATTERN (i2
)))
8972 /* Some other ref remains; just delete the output reload we
8974 delete_address_reloads (output_reload_insn
, insn
);
8975 delete_insn (output_reload_insn
);
8980 /* Delete the now-dead stores into this pseudo. Note that this
8981 loop also takes care of deleting output_reload_insn. */
8982 for (i2
= PREV_INSN (insn
); i2
; i2
= PREV_INSN (i2
))
8984 rtx set
= single_set (i2
);
8986 if (set
!= 0 && SET_DEST (set
) == reg
)
8988 delete_address_reloads (i2
, insn
);
8991 if (LABEL_P (i2
) || JUMP_P (i2
))
8995 /* For the debugging info, say the pseudo lives in this reload reg. */
8996 reg_renumber
[REGNO (reg
)] = REGNO (new_reload_reg
);
8997 if (ira_conflicts_p
)
8998 /* Inform IRA about the change. */
8999 ira_mark_allocation_change (REGNO (reg
));
9000 alter_reg (REGNO (reg
), -1, false);
9004 delete_address_reloads (output_reload_insn
, insn
);
9005 delete_insn (output_reload_insn
);
9009 /* We are going to delete DEAD_INSN. Recursively delete loads of
9010 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
9011 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
9013 delete_address_reloads (rtx_insn
*dead_insn
, rtx_insn
*current_insn
)
9015 rtx set
= single_set (dead_insn
);
9017 rtx_insn
*prev
, *next
;
9020 rtx dst
= SET_DEST (set
);
9022 delete_address_reloads_1 (dead_insn
, XEXP (dst
, 0), current_insn
);
9024 /* If we deleted the store from a reloaded post_{in,de}c expression,
9025 we can delete the matching adds. */
9026 prev
= PREV_INSN (dead_insn
);
9027 next
= NEXT_INSN (dead_insn
);
9028 if (! prev
|| ! next
)
9030 set
= single_set (next
);
9031 set2
= single_set (prev
);
9033 || GET_CODE (SET_SRC (set
)) != PLUS
|| GET_CODE (SET_SRC (set2
)) != PLUS
9034 || !CONST_INT_P (XEXP (SET_SRC (set
), 1))
9035 || !CONST_INT_P (XEXP (SET_SRC (set2
), 1)))
9037 dst
= SET_DEST (set
);
9038 if (! rtx_equal_p (dst
, SET_DEST (set2
))
9039 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set
), 0))
9040 || ! rtx_equal_p (dst
, XEXP (SET_SRC (set2
), 0))
9041 || (INTVAL (XEXP (SET_SRC (set
), 1))
9042 != -INTVAL (XEXP (SET_SRC (set2
), 1))))
9044 delete_related_insns (prev
);
9045 delete_related_insns (next
);
9048 /* Subfunction of delete_address_reloads: process registers found in X. */
9050 delete_address_reloads_1 (rtx_insn
*dead_insn
, rtx x
, rtx_insn
*current_insn
)
9052 rtx_insn
*prev
, *i2
;
9055 enum rtx_code code
= GET_CODE (x
);
9059 const char *fmt
= GET_RTX_FORMAT (code
);
9060 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9063 delete_address_reloads_1 (dead_insn
, XEXP (x
, i
), current_insn
);
9064 else if (fmt
[i
] == 'E')
9066 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9067 delete_address_reloads_1 (dead_insn
, XVECEXP (x
, i
, j
),
9074 if (spill_reg_order
[REGNO (x
)] < 0)
9077 /* Scan backwards for the insn that sets x. This might be a way back due
9079 for (prev
= PREV_INSN (dead_insn
); prev
; prev
= PREV_INSN (prev
))
9081 code
= GET_CODE (prev
);
9082 if (code
== CODE_LABEL
|| code
== JUMP_INSN
)
9086 if (reg_set_p (x
, PATTERN (prev
)))
9088 if (reg_referenced_p (x
, PATTERN (prev
)))
9091 if (! prev
|| INSN_UID (prev
) < reload_first_uid
)
9093 /* Check that PREV only sets the reload register. */
9094 set
= single_set (prev
);
9097 dst
= SET_DEST (set
);
9099 || ! rtx_equal_p (dst
, x
))
9101 if (! reg_set_p (dst
, PATTERN (dead_insn
)))
9103 /* Check if DST was used in a later insn -
9104 it might have been inherited. */
9105 for (i2
= NEXT_INSN (dead_insn
); i2
; i2
= NEXT_INSN (i2
))
9111 if (reg_referenced_p (dst
, PATTERN (i2
)))
9113 /* If there is a reference to the register in the current insn,
9114 it might be loaded in a non-inherited reload. If no other
9115 reload uses it, that means the register is set before
9117 if (i2
== current_insn
)
9119 for (j
= n_reloads
- 1; j
>= 0; j
--)
9120 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9121 || reload_override_in
[j
] == dst
)
9123 for (j
= n_reloads
- 1; j
>= 0; j
--)
9124 if (rld
[j
].in
&& rld
[j
].reg_rtx
== dst
)
9133 /* If DST is still live at CURRENT_INSN, check if it is used for
9134 any reload. Note that even if CURRENT_INSN sets DST, we still
9135 have to check the reloads. */
9136 if (i2
== current_insn
)
9138 for (j
= n_reloads
- 1; j
>= 0; j
--)
9139 if ((rld
[j
].reg_rtx
== dst
&& reload_inherited
[j
])
9140 || reload_override_in
[j
] == dst
)
9142 /* ??? We can't finish the loop here, because dst might be
9143 allocated to a pseudo in this block if no reload in this
9144 block needs any of the classes containing DST - see
9145 spill_hard_reg. There is no easy way to tell this, so we
9146 have to scan till the end of the basic block. */
9148 if (reg_set_p (dst
, PATTERN (i2
)))
9152 delete_address_reloads_1 (prev
, SET_SRC (set
), current_insn
);
9153 reg_reloaded_contents
[REGNO (dst
)] = -1;
9157 /* Output reload-insns to reload VALUE into RELOADREG.
9158 VALUE is an autoincrement or autodecrement RTX whose operand
9159 is a register or memory location;
9160 so reloading involves incrementing that location.
9161 IN is either identical to VALUE, or some cheaper place to reload from.
9163 INC_AMOUNT is the number to increment or decrement by (always positive).
9164 This cannot be deduced from VALUE. */
9167 inc_for_reload (rtx reloadreg
, rtx in
, rtx value
, int inc_amount
)
9169 /* REG or MEM to be copied and incremented. */
9170 rtx incloc
= find_replacement (&XEXP (value
, 0));
9171 /* Nonzero if increment after copying. */
9172 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
9173 || GET_CODE (value
) == POST_MODIFY
);
9178 rtx real_in
= in
== value
? incloc
: in
;
9180 /* No hard register is equivalent to this register after
9181 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9182 we could inc/dec that register as well (maybe even using it for
9183 the source), but I'm not sure it's worth worrying about. */
9185 reg_last_reload_reg
[REGNO (incloc
)] = 0;
9187 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
9189 gcc_assert (GET_CODE (XEXP (value
, 1)) == PLUS
);
9190 inc
= find_replacement (&XEXP (XEXP (value
, 1), 1));
9194 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
9195 inc_amount
= -inc_amount
;
9197 inc
= GEN_INT (inc_amount
);
9200 /* If this is post-increment, first copy the location to the reload reg. */
9201 if (post
&& real_in
!= reloadreg
)
9202 emit_insn (gen_move_insn (reloadreg
, real_in
));
9206 /* See if we can directly increment INCLOC. Use a method similar to
9207 that in gen_reload. */
9209 last
= get_last_insn ();
9210 add_insn
= emit_insn (gen_rtx_SET (incloc
,
9211 gen_rtx_PLUS (GET_MODE (incloc
),
9214 code
= recog_memoized (add_insn
);
9217 extract_insn (add_insn
);
9218 if (constrain_operands (1, get_enabled_alternatives (add_insn
)))
9220 /* If this is a pre-increment and we have incremented the value
9221 where it lives, copy the incremented value to RELOADREG to
9222 be used as an address. */
9225 emit_insn (gen_move_insn (reloadreg
, incloc
));
9229 delete_insns_since (last
);
9232 /* If couldn't do the increment directly, must increment in RELOADREG.
9233 The way we do this depends on whether this is pre- or post-increment.
9234 For pre-increment, copy INCLOC to the reload register, increment it
9235 there, then save back. */
9239 if (in
!= reloadreg
)
9240 emit_insn (gen_move_insn (reloadreg
, real_in
));
9241 emit_insn (gen_add2_insn (reloadreg
, inc
));
9242 emit_insn (gen_move_insn (incloc
, reloadreg
));
9247 Because this might be a jump insn or a compare, and because RELOADREG
9248 may not be available after the insn in an input reload, we must do
9249 the incrementation before the insn being reloaded for.
9251 We have already copied IN to RELOADREG. Increment the copy in
9252 RELOADREG, save that back, then decrement RELOADREG so it has
9253 the original value. */
9255 emit_insn (gen_add2_insn (reloadreg
, inc
));
9256 emit_insn (gen_move_insn (incloc
, reloadreg
));
9257 if (CONST_INT_P (inc
))
9258 emit_insn (gen_add2_insn (reloadreg
,
9259 gen_int_mode (-INTVAL (inc
),
9260 GET_MODE (reloadreg
))));
9262 emit_insn (gen_sub2_insn (reloadreg
, inc
));
9268 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
9270 enum rtx_code code
= GET_CODE (x
);
9274 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
9276 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
9280 /* Scan all the operand sub-expressions. */
9281 fmt
= GET_RTX_FORMAT (code
);
9282 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9285 add_auto_inc_notes (insn
, XEXP (x
, i
));
9286 else if (fmt
[i
] == 'E')
9287 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9288 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));