1 /* RTL simplification functions for GNU compiler.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
35 #include "diagnostic-core.h"
39 /* Simplification and canonicalization of RTL. */
41 /* Much code operates on (low, high) pairs; the low value is an
42 unsigned wide int, the high value a signed wide int. We
43 occasionally need to sign extend from low to high as if low were a
45 #define HWI_SIGN_EXTEND(low) \
46 ((((HOST_WIDE_INT) low) < 0) ? ((HOST_WIDE_INT) -1) : ((HOST_WIDE_INT) 0))
48 static rtx
neg_const_int (enum machine_mode
, const_rtx
);
49 static bool plus_minus_operand_p (const_rtx
);
50 static bool simplify_plus_minus_op_data_cmp (rtx
, rtx
);
51 static rtx
simplify_plus_minus (enum rtx_code
, enum machine_mode
, rtx
, rtx
);
52 static rtx
simplify_immed_subreg (enum machine_mode
, rtx
, enum machine_mode
,
54 static rtx
simplify_associative_operation (enum rtx_code
, enum machine_mode
,
56 static rtx
simplify_relational_operation_1 (enum rtx_code
, enum machine_mode
,
57 enum machine_mode
, rtx
, rtx
);
58 static rtx
simplify_unary_operation_1 (enum rtx_code
, enum machine_mode
, rtx
);
59 static rtx
simplify_binary_operation_1 (enum rtx_code
, enum machine_mode
,
62 /* Negate a CONST_INT rtx, truncating (because a conversion from a
63 maximally negative number can overflow). */
65 neg_const_int (enum machine_mode mode
, const_rtx i
)
67 return gen_int_mode (-(unsigned HOST_WIDE_INT
) INTVAL (i
), mode
);
70 /* Test whether expression, X, is an immediate constant that represents
71 the most significant bit of machine mode MODE. */
74 mode_signbit_p (enum machine_mode mode
, const_rtx x
)
76 unsigned HOST_WIDE_INT val
;
79 if (GET_MODE_CLASS (mode
) != MODE_INT
)
82 width
= GET_MODE_PRECISION (mode
);
86 if (width
<= HOST_BITS_PER_WIDE_INT
89 #if TARGET_SUPPORTS_WIDE_INT
90 else if (CONST_WIDE_INT_P (x
))
93 unsigned int elts
= CONST_WIDE_INT_NUNITS (x
);
94 if (elts
!= (width
+ HOST_BITS_PER_WIDE_INT
- 1) / HOST_BITS_PER_WIDE_INT
)
96 for (i
= 0; i
< elts
- 1; i
++)
97 if (CONST_WIDE_INT_ELT (x
, i
) != 0)
99 val
= CONST_WIDE_INT_ELT (x
, elts
- 1);
100 width
%= HOST_BITS_PER_WIDE_INT
;
102 width
= HOST_BITS_PER_WIDE_INT
;
105 else if (width
<= HOST_BITS_PER_DOUBLE_INT
106 && CONST_DOUBLE_AS_INT_P (x
)
107 && CONST_DOUBLE_LOW (x
) == 0)
109 val
= CONST_DOUBLE_HIGH (x
);
110 width
-= HOST_BITS_PER_WIDE_INT
;
114 /* X is not an integer constant. */
117 if (width
< HOST_BITS_PER_WIDE_INT
)
118 val
&= ((unsigned HOST_WIDE_INT
) 1 << width
) - 1;
119 return val
== ((unsigned HOST_WIDE_INT
) 1 << (width
- 1));
122 /* Test whether VAL is equal to the most significant bit of mode MODE
123 (after masking with the mode mask of MODE). Returns false if the
124 precision of MODE is too large to handle. */
127 val_signbit_p (enum machine_mode mode
, unsigned HOST_WIDE_INT val
)
131 if (GET_MODE_CLASS (mode
) != MODE_INT
)
134 width
= GET_MODE_PRECISION (mode
);
135 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
138 val
&= GET_MODE_MASK (mode
);
139 return val
== ((unsigned HOST_WIDE_INT
) 1 << (width
- 1));
142 /* Test whether the most significant bit of mode MODE is set in VAL.
143 Returns false if the precision of MODE is too large to handle. */
145 val_signbit_known_set_p (enum machine_mode mode
, unsigned HOST_WIDE_INT val
)
149 if (GET_MODE_CLASS (mode
) != MODE_INT
)
152 width
= GET_MODE_PRECISION (mode
);
153 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
156 val
&= (unsigned HOST_WIDE_INT
) 1 << (width
- 1);
160 /* Test whether the most significant bit of mode MODE is clear in VAL.
161 Returns false if the precision of MODE is too large to handle. */
163 val_signbit_known_clear_p (enum machine_mode mode
, unsigned HOST_WIDE_INT val
)
167 if (GET_MODE_CLASS (mode
) != MODE_INT
)
170 width
= GET_MODE_PRECISION (mode
);
171 if (width
== 0 || width
> HOST_BITS_PER_WIDE_INT
)
174 val
&= (unsigned HOST_WIDE_INT
) 1 << (width
- 1);
178 /* Make a binary operation by properly ordering the operands and
179 seeing if the expression folds. */
182 simplify_gen_binary (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
187 /* If this simplifies, do it. */
188 tem
= simplify_binary_operation (code
, mode
, op0
, op1
);
192 /* Put complex operands first and constants second if commutative. */
193 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
194 && swap_commutative_operands_p (op0
, op1
))
195 tem
= op0
, op0
= op1
, op1
= tem
;
197 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
200 /* If X is a MEM referencing the constant pool, return the real value.
201 Otherwise return X. */
203 avoid_constant_pool_reference (rtx x
)
206 enum machine_mode cmode
;
207 HOST_WIDE_INT offset
= 0;
209 switch (GET_CODE (x
))
215 /* Handle float extensions of constant pool references. */
217 c
= avoid_constant_pool_reference (tmp
);
218 if (c
!= tmp
&& CONST_DOUBLE_AS_FLOAT_P (c
))
222 REAL_VALUE_FROM_CONST_DOUBLE (d
, c
);
223 return CONST_DOUBLE_FROM_REAL_VALUE (d
, GET_MODE (x
));
231 if (GET_MODE (x
) == BLKmode
)
236 /* Call target hook to avoid the effects of -fpic etc.... */
237 addr
= targetm
.delegitimize_address (addr
);
239 /* Split the address into a base and integer offset. */
240 if (GET_CODE (addr
) == CONST
241 && GET_CODE (XEXP (addr
, 0)) == PLUS
242 && CONST_INT_P (XEXP (XEXP (addr
, 0), 1)))
244 offset
= INTVAL (XEXP (XEXP (addr
, 0), 1));
245 addr
= XEXP (XEXP (addr
, 0), 0);
248 if (GET_CODE (addr
) == LO_SUM
)
249 addr
= XEXP (addr
, 1);
251 /* If this is a constant pool reference, we can turn it into its
252 constant and hope that simplifications happen. */
253 if (GET_CODE (addr
) == SYMBOL_REF
254 && CONSTANT_POOL_ADDRESS_P (addr
))
256 c
= get_pool_constant (addr
);
257 cmode
= get_pool_mode (addr
);
259 /* If we're accessing the constant in a different mode than it was
260 originally stored, attempt to fix that up via subreg simplifications.
261 If that fails we have no choice but to return the original memory. */
262 if ((offset
!= 0 || cmode
!= GET_MODE (x
))
263 && offset
>= 0 && offset
< GET_MODE_SIZE (cmode
))
265 rtx tem
= simplify_subreg (GET_MODE (x
), c
, cmode
, offset
);
266 if (tem
&& CONSTANT_P (tem
))
276 /* Simplify a MEM based on its attributes. This is the default
277 delegitimize_address target hook, and it's recommended that every
278 overrider call it. */
281 delegitimize_mem_from_attrs (rtx x
)
283 /* MEMs without MEM_OFFSETs may have been offset, so we can't just
284 use their base addresses as equivalent. */
287 && MEM_OFFSET_KNOWN_P (x
))
289 tree decl
= MEM_EXPR (x
);
290 enum machine_mode mode
= GET_MODE (x
);
291 HOST_WIDE_INT offset
= 0;
293 switch (TREE_CODE (decl
))
303 case ARRAY_RANGE_REF
:
308 case VIEW_CONVERT_EXPR
:
310 HOST_WIDE_INT bitsize
, bitpos
;
312 int unsignedp
, volatilep
= 0;
314 decl
= get_inner_reference (decl
, &bitsize
, &bitpos
, &toffset
,
315 &mode
, &unsignedp
, &volatilep
, false);
316 if (bitsize
!= GET_MODE_BITSIZE (mode
)
317 || (bitpos
% BITS_PER_UNIT
)
318 || (toffset
&& !tree_fits_shwi_p (toffset
)))
322 offset
+= bitpos
/ BITS_PER_UNIT
;
324 offset
+= tree_to_hwi (toffset
);
331 && mode
== GET_MODE (x
)
332 && TREE_CODE (decl
) == VAR_DECL
333 && (TREE_STATIC (decl
)
334 || DECL_THREAD_LOCAL_P (decl
))
335 && DECL_RTL_SET_P (decl
)
336 && MEM_P (DECL_RTL (decl
)))
340 offset
+= MEM_OFFSET (x
);
342 newx
= DECL_RTL (decl
);
346 rtx n
= XEXP (newx
, 0), o
= XEXP (x
, 0);
348 /* Avoid creating a new MEM needlessly if we already had
349 the same address. We do if there's no OFFSET and the
350 old address X is identical to NEWX, or if X is of the
351 form (plus NEWX OFFSET), or the NEWX is of the form
352 (plus Y (const_int Z)) and X is that with the offset
353 added: (plus Y (const_int Z+OFFSET)). */
355 || (GET_CODE (o
) == PLUS
356 && GET_CODE (XEXP (o
, 1)) == CONST_INT
357 && (offset
== INTVAL (XEXP (o
, 1))
358 || (GET_CODE (n
) == PLUS
359 && GET_CODE (XEXP (n
, 1)) == CONST_INT
360 && (INTVAL (XEXP (n
, 1)) + offset
361 == INTVAL (XEXP (o
, 1)))
362 && (n
= XEXP (n
, 0))))
363 && (o
= XEXP (o
, 0))))
364 && rtx_equal_p (o
, n
)))
365 x
= adjust_address_nv (newx
, mode
, offset
);
367 else if (GET_MODE (x
) == GET_MODE (newx
)
376 /* Make a unary operation by first seeing if it folds and otherwise making
377 the specified operation. */
380 simplify_gen_unary (enum rtx_code code
, enum machine_mode mode
, rtx op
,
381 enum machine_mode op_mode
)
385 /* If this simplifies, use it. */
386 if ((tem
= simplify_unary_operation (code
, mode
, op
, op_mode
)) != 0)
389 return gen_rtx_fmt_e (code
, mode
, op
);
392 /* Likewise for ternary operations. */
395 simplify_gen_ternary (enum rtx_code code
, enum machine_mode mode
,
396 enum machine_mode op0_mode
, rtx op0
, rtx op1
, rtx op2
)
400 /* If this simplifies, use it. */
401 if (0 != (tem
= simplify_ternary_operation (code
, mode
, op0_mode
,
405 return gen_rtx_fmt_eee (code
, mode
, op0
, op1
, op2
);
408 /* Likewise, for relational operations.
409 CMP_MODE specifies mode comparison is done in. */
412 simplify_gen_relational (enum rtx_code code
, enum machine_mode mode
,
413 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
417 if (0 != (tem
= simplify_relational_operation (code
, mode
, cmp_mode
,
421 return gen_rtx_fmt_ee (code
, mode
, op0
, op1
);
424 /* If FN is NULL, replace all occurrences of OLD_RTX in X with copy_rtx (DATA)
425 and simplify the result. If FN is non-NULL, call this callback on each
426 X, if it returns non-NULL, replace X with its return value and simplify the
430 simplify_replace_fn_rtx (rtx x
, const_rtx old_rtx
,
431 rtx (*fn
) (rtx
, const_rtx
, void *), void *data
)
433 enum rtx_code code
= GET_CODE (x
);
434 enum machine_mode mode
= GET_MODE (x
);
435 enum machine_mode op_mode
;
437 rtx op0
, op1
, op2
, newx
, op
;
441 if (__builtin_expect (fn
!= NULL
, 0))
443 newx
= fn (x
, old_rtx
, data
);
447 else if (rtx_equal_p (x
, old_rtx
))
448 return copy_rtx ((rtx
) data
);
450 switch (GET_RTX_CLASS (code
))
454 op_mode
= GET_MODE (op0
);
455 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
456 if (op0
== XEXP (x
, 0))
458 return simplify_gen_unary (code
, mode
, op0
, op_mode
);
462 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
463 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
464 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
466 return simplify_gen_binary (code
, mode
, op0
, op1
);
469 case RTX_COMM_COMPARE
:
472 op_mode
= GET_MODE (op0
) != VOIDmode
? GET_MODE (op0
) : GET_MODE (op1
);
473 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
474 op1
= simplify_replace_fn_rtx (op1
, old_rtx
, fn
, data
);
475 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
477 return simplify_gen_relational (code
, mode
, op_mode
, op0
, op1
);
480 case RTX_BITFIELD_OPS
:
482 op_mode
= GET_MODE (op0
);
483 op0
= simplify_replace_fn_rtx (op0
, old_rtx
, fn
, data
);
484 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
485 op2
= simplify_replace_fn_rtx (XEXP (x
, 2), old_rtx
, fn
, data
);
486 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1) && op2
== XEXP (x
, 2))
488 if (op_mode
== VOIDmode
)
489 op_mode
= GET_MODE (op0
);
490 return simplify_gen_ternary (code
, mode
, op_mode
, op0
, op1
, op2
);
495 op0
= simplify_replace_fn_rtx (SUBREG_REG (x
), old_rtx
, fn
, data
);
496 if (op0
== SUBREG_REG (x
))
498 op0
= simplify_gen_subreg (GET_MODE (x
), op0
,
499 GET_MODE (SUBREG_REG (x
)),
501 return op0
? op0
: x
;
508 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
509 if (op0
== XEXP (x
, 0))
511 return replace_equiv_address_nv (x
, op0
);
513 else if (code
== LO_SUM
)
515 op0
= simplify_replace_fn_rtx (XEXP (x
, 0), old_rtx
, fn
, data
);
516 op1
= simplify_replace_fn_rtx (XEXP (x
, 1), old_rtx
, fn
, data
);
518 /* (lo_sum (high x) x) -> x */
519 if (GET_CODE (op0
) == HIGH
&& rtx_equal_p (XEXP (op0
, 0), op1
))
522 if (op0
== XEXP (x
, 0) && op1
== XEXP (x
, 1))
524 return gen_rtx_LO_SUM (mode
, op0
, op1
);
533 fmt
= GET_RTX_FORMAT (code
);
534 for (i
= 0; fmt
[i
]; i
++)
539 newvec
= XVEC (newx
, i
);
540 for (j
= 0; j
< GET_NUM_ELEM (vec
); j
++)
542 op
= simplify_replace_fn_rtx (RTVEC_ELT (vec
, j
),
544 if (op
!= RTVEC_ELT (vec
, j
))
548 newvec
= shallow_copy_rtvec (vec
);
550 newx
= shallow_copy_rtx (x
);
551 XVEC (newx
, i
) = newvec
;
553 RTVEC_ELT (newvec
, j
) = op
;
561 op
= simplify_replace_fn_rtx (XEXP (x
, i
), old_rtx
, fn
, data
);
562 if (op
!= XEXP (x
, i
))
565 newx
= shallow_copy_rtx (x
);
574 /* Replace all occurrences of OLD_RTX in X with NEW_RTX and try to simplify the
575 resulting RTX. Return a new RTX which is as simplified as possible. */
578 simplify_replace_rtx (rtx x
, const_rtx old_rtx
, rtx new_rtx
)
580 return simplify_replace_fn_rtx (x
, old_rtx
, 0, new_rtx
);
583 /* Try to simplify a MODE truncation of OP, which has OP_MODE.
584 Only handle cases where the truncated value is inherently an rvalue.
586 RTL provides two ways of truncating a value:
588 1. a lowpart subreg. This form is only a truncation when both
589 the outer and inner modes (here MODE and OP_MODE respectively)
590 are scalar integers, and only then when the subreg is used as
593 It is only valid to form such truncating subregs if the
594 truncation requires no action by the target. The onus for
595 proving this is on the creator of the subreg -- e.g. the
596 caller to simplify_subreg or simplify_gen_subreg -- and typically
597 involves either TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode.
599 2. a TRUNCATE. This form handles both scalar and compound integers.
601 The first form is preferred where valid. However, the TRUNCATE
602 handling in simplify_unary_operation turns the second form into the
603 first form when TRULY_NOOP_TRUNCATION_MODES_P or truncated_to_mode allow,
604 so it is generally safe to form rvalue truncations using:
606 simplify_gen_unary (TRUNCATE, ...)
608 and leave simplify_unary_operation to work out which representation
611 Because of the proof requirements on (1), simplify_truncation must
612 also use simplify_gen_unary (TRUNCATE, ...) to truncate parts of OP,
613 regardless of whether the outer truncation came from a SUBREG or a
614 TRUNCATE. For example, if the caller has proven that an SImode
619 is a no-op and can be represented as a subreg, it does not follow
620 that SImode truncations of X and Y are also no-ops. On a target
621 like 64-bit MIPS that requires SImode values to be stored in
622 sign-extended form, an SImode truncation of:
624 (and:DI (reg:DI X) (const_int 63))
626 is trivially a no-op because only the lower 6 bits can be set.
627 However, X is still an arbitrary 64-bit number and so we cannot
628 assume that truncating it too is a no-op. */
631 simplify_truncation (enum machine_mode mode
, rtx op
,
632 enum machine_mode op_mode
)
634 unsigned int precision
= GET_MODE_UNIT_PRECISION (mode
);
635 unsigned int op_precision
= GET_MODE_UNIT_PRECISION (op_mode
);
636 gcc_assert (precision
<= op_precision
);
638 /* Optimize truncations of zero and sign extended values. */
639 if (GET_CODE (op
) == ZERO_EXTEND
640 || GET_CODE (op
) == SIGN_EXTEND
)
642 /* There are three possibilities. If MODE is the same as the
643 origmode, we can omit both the extension and the subreg.
644 If MODE is not larger than the origmode, we can apply the
645 truncation without the extension. Finally, if the outermode
646 is larger than the origmode, we can just extend to the appropriate
648 enum machine_mode origmode
= GET_MODE (XEXP (op
, 0));
649 if (mode
== origmode
)
651 else if (precision
<= GET_MODE_UNIT_PRECISION (origmode
))
652 return simplify_gen_unary (TRUNCATE
, mode
,
653 XEXP (op
, 0), origmode
);
655 return simplify_gen_unary (GET_CODE (op
), mode
,
656 XEXP (op
, 0), origmode
);
659 /* Simplify (truncate:SI (op:DI (x:DI) (y:DI)))
660 to (op:SI (truncate:SI (x:DI)) (truncate:SI (x:DI))). */
661 if (GET_CODE (op
) == PLUS
662 || GET_CODE (op
) == MINUS
663 || GET_CODE (op
) == MULT
)
665 rtx op0
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0), op_mode
);
668 rtx op1
= simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 1), op_mode
);
670 return simplify_gen_binary (GET_CODE (op
), mode
, op0
, op1
);
674 /* Simplify (truncate:QI (lshiftrt:SI (sign_extend:SI (x:QI)) C)) into
675 to (ashiftrt:QI (x:QI) C), where C is a suitable small constant and
676 the outer subreg is effectively a truncation to the original mode. */
677 if ((GET_CODE (op
) == LSHIFTRT
678 || GET_CODE (op
) == ASHIFTRT
)
679 /* Ensure that OP_MODE is at least twice as wide as MODE
680 to avoid the possibility that an outer LSHIFTRT shifts by more
681 than the sign extension's sign_bit_copies and introduces zeros
682 into the high bits of the result. */
683 && 2 * precision
<= op_precision
684 && CONST_INT_P (XEXP (op
, 1))
685 && GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
686 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
687 && UINTVAL (XEXP (op
, 1)) < precision
)
688 return simplify_gen_binary (ASHIFTRT
, mode
,
689 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
691 /* Likewise (truncate:QI (lshiftrt:SI (zero_extend:SI (x:QI)) C)) into
692 to (lshiftrt:QI (x:QI) C), where C is a suitable small constant and
693 the outer subreg is effectively a truncation to the original mode. */
694 if ((GET_CODE (op
) == LSHIFTRT
695 || GET_CODE (op
) == ASHIFTRT
)
696 && CONST_INT_P (XEXP (op
, 1))
697 && GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
698 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
699 && UINTVAL (XEXP (op
, 1)) < precision
)
700 return simplify_gen_binary (LSHIFTRT
, mode
,
701 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
703 /* Likewise (truncate:QI (ashift:SI (zero_extend:SI (x:QI)) C)) into
704 to (ashift:QI (x:QI) C), where C is a suitable small constant and
705 the outer subreg is effectively a truncation to the original mode. */
706 if (GET_CODE (op
) == ASHIFT
707 && CONST_INT_P (XEXP (op
, 1))
708 && (GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
709 || GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
)
710 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
711 && UINTVAL (XEXP (op
, 1)) < precision
)
712 return simplify_gen_binary (ASHIFT
, mode
,
713 XEXP (XEXP (op
, 0), 0), XEXP (op
, 1));
715 /* Recognize a word extraction from a multi-word subreg. */
716 if ((GET_CODE (op
) == LSHIFTRT
717 || GET_CODE (op
) == ASHIFTRT
)
718 && SCALAR_INT_MODE_P (mode
)
719 && SCALAR_INT_MODE_P (op_mode
)
720 && precision
>= BITS_PER_WORD
721 && 2 * precision
<= op_precision
722 && CONST_INT_P (XEXP (op
, 1))
723 && (INTVAL (XEXP (op
, 1)) & (precision
- 1)) == 0
724 && UINTVAL (XEXP (op
, 1)) < op_precision
)
726 int byte
= subreg_lowpart_offset (mode
, op_mode
);
727 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
728 return simplify_gen_subreg (mode
, XEXP (op
, 0), op_mode
,
730 ? byte
- shifted_bytes
731 : byte
+ shifted_bytes
));
734 /* If we have a TRUNCATE of a right shift of MEM, make a new MEM
735 and try replacing the TRUNCATE and shift with it. Don't do this
736 if the MEM has a mode-dependent address. */
737 if ((GET_CODE (op
) == LSHIFTRT
738 || GET_CODE (op
) == ASHIFTRT
)
739 && SCALAR_INT_MODE_P (op_mode
)
740 && MEM_P (XEXP (op
, 0))
741 && CONST_INT_P (XEXP (op
, 1))
742 && (INTVAL (XEXP (op
, 1)) % GET_MODE_BITSIZE (mode
)) == 0
743 && INTVAL (XEXP (op
, 1)) > 0
744 && INTVAL (XEXP (op
, 1)) < GET_MODE_BITSIZE (op_mode
)
745 && ! mode_dependent_address_p (XEXP (XEXP (op
, 0), 0),
746 MEM_ADDR_SPACE (XEXP (op
, 0)))
747 && ! MEM_VOLATILE_P (XEXP (op
, 0))
748 && (GET_MODE_SIZE (mode
) >= UNITS_PER_WORD
749 || WORDS_BIG_ENDIAN
== BYTES_BIG_ENDIAN
))
751 int byte
= subreg_lowpart_offset (mode
, op_mode
);
752 int shifted_bytes
= INTVAL (XEXP (op
, 1)) / BITS_PER_UNIT
;
753 return adjust_address_nv (XEXP (op
, 0), mode
,
755 ? byte
- shifted_bytes
756 : byte
+ shifted_bytes
));
759 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
760 (OP:SI foo:SI) if OP is NEG or ABS. */
761 if ((GET_CODE (op
) == ABS
762 || GET_CODE (op
) == NEG
)
763 && (GET_CODE (XEXP (op
, 0)) == SIGN_EXTEND
764 || GET_CODE (XEXP (op
, 0)) == ZERO_EXTEND
)
765 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
766 return simplify_gen_unary (GET_CODE (op
), mode
,
767 XEXP (XEXP (op
, 0), 0), mode
);
769 /* (truncate:A (subreg:B (truncate:C X) 0)) is
771 if (GET_CODE (op
) == SUBREG
772 && SCALAR_INT_MODE_P (mode
)
773 && SCALAR_INT_MODE_P (op_mode
)
774 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op
)))
775 && GET_CODE (SUBREG_REG (op
)) == TRUNCATE
776 && subreg_lowpart_p (op
))
778 rtx inner
= XEXP (SUBREG_REG (op
), 0);
779 if (GET_MODE_PRECISION (mode
)
780 <= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op
))))
781 return simplify_gen_unary (TRUNCATE
, mode
, inner
, GET_MODE (inner
));
783 /* If subreg above is paradoxical and C is narrower
784 than A, return (subreg:A (truncate:C X) 0). */
785 return simplify_gen_subreg (mode
, SUBREG_REG (op
),
786 GET_MODE (SUBREG_REG (op
)), 0);
789 /* (truncate:A (truncate:B X)) is (truncate:A X). */
790 if (GET_CODE (op
) == TRUNCATE
)
791 return simplify_gen_unary (TRUNCATE
, mode
, XEXP (op
, 0),
792 GET_MODE (XEXP (op
, 0)));
797 /* Try to simplify a unary operation CODE whose output mode is to be
798 MODE with input operand OP whose mode was originally OP_MODE.
799 Return zero if no simplification can be made. */
801 simplify_unary_operation (enum rtx_code code
, enum machine_mode mode
,
802 rtx op
, enum machine_mode op_mode
)
806 trueop
= avoid_constant_pool_reference (op
);
808 tem
= simplify_const_unary_operation (code
, mode
, trueop
, op_mode
);
812 return simplify_unary_operation_1 (code
, mode
, op
);
815 /* Perform some simplifications we can do even if the operands
818 simplify_unary_operation_1 (enum rtx_code code
, enum machine_mode mode
, rtx op
)
820 enum rtx_code reversed
;
826 /* (not (not X)) == X. */
827 if (GET_CODE (op
) == NOT
)
830 /* (not (eq X Y)) == (ne X Y), etc. if BImode or the result of the
831 comparison is all ones. */
832 if (COMPARISON_P (op
)
833 && (mode
== BImode
|| STORE_FLAG_VALUE
== -1)
834 && ((reversed
= reversed_comparison_code (op
, NULL_RTX
)) != UNKNOWN
))
835 return simplify_gen_relational (reversed
, mode
, VOIDmode
,
836 XEXP (op
, 0), XEXP (op
, 1));
838 /* (not (plus X -1)) can become (neg X). */
839 if (GET_CODE (op
) == PLUS
840 && XEXP (op
, 1) == constm1_rtx
)
841 return simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
843 /* Similarly, (not (neg X)) is (plus X -1). */
844 if (GET_CODE (op
) == NEG
)
845 return simplify_gen_binary (PLUS
, mode
, XEXP (op
, 0),
848 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
849 if (GET_CODE (op
) == XOR
850 && CONST_INT_P (XEXP (op
, 1))
851 && (temp
= simplify_unary_operation (NOT
, mode
,
852 XEXP (op
, 1), mode
)) != 0)
853 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
855 /* (not (plus X C)) for signbit C is (xor X D) with D = ~C. */
856 if (GET_CODE (op
) == PLUS
857 && CONST_INT_P (XEXP (op
, 1))
858 && mode_signbit_p (mode
, XEXP (op
, 1))
859 && (temp
= simplify_unary_operation (NOT
, mode
,
860 XEXP (op
, 1), mode
)) != 0)
861 return simplify_gen_binary (XOR
, mode
, XEXP (op
, 0), temp
);
864 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for
865 operands other than 1, but that is not valid. We could do a
866 similar simplification for (not (lshiftrt C X)) where C is
867 just the sign bit, but this doesn't seem common enough to
869 if (GET_CODE (op
) == ASHIFT
870 && XEXP (op
, 0) == const1_rtx
)
872 temp
= simplify_gen_unary (NOT
, mode
, const1_rtx
, mode
);
873 return simplify_gen_binary (ROTATE
, mode
, temp
, XEXP (op
, 1));
876 /* (not (ashiftrt foo C)) where C is the number of bits in FOO
877 minus 1 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1,
878 so we can perform the above simplification. */
879 if (STORE_FLAG_VALUE
== -1
880 && GET_CODE (op
) == ASHIFTRT
881 && GET_CODE (XEXP (op
, 1))
882 && INTVAL (XEXP (op
, 1)) == GET_MODE_PRECISION (mode
) - 1)
883 return simplify_gen_relational (GE
, mode
, VOIDmode
,
884 XEXP (op
, 0), const0_rtx
);
887 if (GET_CODE (op
) == SUBREG
888 && subreg_lowpart_p (op
)
889 && (GET_MODE_SIZE (GET_MODE (op
))
890 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (op
))))
891 && GET_CODE (SUBREG_REG (op
)) == ASHIFT
892 && XEXP (SUBREG_REG (op
), 0) == const1_rtx
)
894 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (op
));
897 x
= gen_rtx_ROTATE (inner_mode
,
898 simplify_gen_unary (NOT
, inner_mode
, const1_rtx
,
900 XEXP (SUBREG_REG (op
), 1));
901 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, x
);
906 /* Apply De Morgan's laws to reduce number of patterns for machines
907 with negating logical insns (and-not, nand, etc.). If result has
908 only one NOT, put it first, since that is how the patterns are
910 if (GET_CODE (op
) == IOR
|| GET_CODE (op
) == AND
)
912 rtx in1
= XEXP (op
, 0), in2
= XEXP (op
, 1);
913 enum machine_mode op_mode
;
915 op_mode
= GET_MODE (in1
);
916 in1
= simplify_gen_unary (NOT
, op_mode
, in1
, op_mode
);
918 op_mode
= GET_MODE (in2
);
919 if (op_mode
== VOIDmode
)
921 in2
= simplify_gen_unary (NOT
, op_mode
, in2
, op_mode
);
923 if (GET_CODE (in2
) == NOT
&& GET_CODE (in1
) != NOT
)
926 in2
= in1
; in1
= tem
;
929 return gen_rtx_fmt_ee (GET_CODE (op
) == IOR
? AND
: IOR
,
933 /* (not (bswap x)) -> (bswap (not x)). */
934 if (GET_CODE (op
) == BSWAP
)
936 rtx x
= simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
937 return simplify_gen_unary (BSWAP
, mode
, x
, mode
);
942 /* (neg (neg X)) == X. */
943 if (GET_CODE (op
) == NEG
)
946 /* (neg (plus X 1)) can become (not X). */
947 if (GET_CODE (op
) == PLUS
948 && XEXP (op
, 1) == const1_rtx
)
949 return simplify_gen_unary (NOT
, mode
, XEXP (op
, 0), mode
);
951 /* Similarly, (neg (not X)) is (plus X 1). */
952 if (GET_CODE (op
) == NOT
)
953 return simplify_gen_binary (PLUS
, mode
, XEXP (op
, 0),
956 /* (neg (minus X Y)) can become (minus Y X). This transformation
957 isn't safe for modes with signed zeros, since if X and Y are
958 both +0, (minus Y X) is the same as (minus X Y). If the
959 rounding mode is towards +infinity (or -infinity) then the two
960 expressions will be rounded differently. */
961 if (GET_CODE (op
) == MINUS
962 && !HONOR_SIGNED_ZEROS (mode
)
963 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
964 return simplify_gen_binary (MINUS
, mode
, XEXP (op
, 1), XEXP (op
, 0));
966 if (GET_CODE (op
) == PLUS
967 && !HONOR_SIGNED_ZEROS (mode
)
968 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
970 /* (neg (plus A C)) is simplified to (minus -C A). */
971 if (CONST_SCALAR_INT_P (XEXP (op
, 1))
972 || CONST_DOUBLE_AS_FLOAT_P (XEXP (op
, 1)))
974 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 1), mode
);
976 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 0));
979 /* (neg (plus A B)) is canonicalized to (minus (neg A) B). */
980 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 0), mode
);
981 return simplify_gen_binary (MINUS
, mode
, temp
, XEXP (op
, 1));
984 /* (neg (mult A B)) becomes (mult A (neg B)).
985 This works even for floating-point values. */
986 if (GET_CODE (op
) == MULT
987 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
989 temp
= simplify_gen_unary (NEG
, mode
, XEXP (op
, 1), mode
);
990 return simplify_gen_binary (MULT
, mode
, XEXP (op
, 0), temp
);
993 /* NEG commutes with ASHIFT since it is multiplication. Only do
994 this if we can then eliminate the NEG (e.g., if the operand
996 if (GET_CODE (op
) == ASHIFT
)
998 temp
= simplify_unary_operation (NEG
, mode
, XEXP (op
, 0), mode
);
1000 return simplify_gen_binary (ASHIFT
, mode
, temp
, XEXP (op
, 1));
1003 /* (neg (ashiftrt X C)) can be replaced by (lshiftrt X C) when
1004 C is equal to the width of MODE minus 1. */
1005 if (GET_CODE (op
) == ASHIFTRT
1006 && CONST_INT_P (XEXP (op
, 1))
1007 && INTVAL (XEXP (op
, 1)) == GET_MODE_PRECISION (mode
) - 1)
1008 return simplify_gen_binary (LSHIFTRT
, mode
,
1009 XEXP (op
, 0), XEXP (op
, 1));
1011 /* (neg (lshiftrt X C)) can be replaced by (ashiftrt X C) when
1012 C is equal to the width of MODE minus 1. */
1013 if (GET_CODE (op
) == LSHIFTRT
1014 && CONST_INT_P (XEXP (op
, 1))
1015 && INTVAL (XEXP (op
, 1)) == GET_MODE_PRECISION (mode
) - 1)
1016 return simplify_gen_binary (ASHIFTRT
, mode
,
1017 XEXP (op
, 0), XEXP (op
, 1));
1019 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
1020 if (GET_CODE (op
) == XOR
1021 && XEXP (op
, 1) == const1_rtx
1022 && nonzero_bits (XEXP (op
, 0), mode
) == 1)
1023 return plus_constant (mode
, XEXP (op
, 0), -1);
1025 /* (neg (lt x 0)) is (ashiftrt X C) if STORE_FLAG_VALUE is 1. */
1026 /* (neg (lt x 0)) is (lshiftrt X C) if STORE_FLAG_VALUE is -1. */
1027 if (GET_CODE (op
) == LT
1028 && XEXP (op
, 1) == const0_rtx
1029 && SCALAR_INT_MODE_P (GET_MODE (XEXP (op
, 0))))
1031 enum machine_mode inner
= GET_MODE (XEXP (op
, 0));
1032 int isize
= GET_MODE_PRECISION (inner
);
1033 if (STORE_FLAG_VALUE
== 1)
1035 temp
= simplify_gen_binary (ASHIFTRT
, inner
, XEXP (op
, 0),
1036 GEN_INT (isize
- 1));
1039 if (GET_MODE_PRECISION (mode
) > isize
)
1040 return simplify_gen_unary (SIGN_EXTEND
, mode
, temp
, inner
);
1041 return simplify_gen_unary (TRUNCATE
, mode
, temp
, inner
);
1043 else if (STORE_FLAG_VALUE
== -1)
1045 temp
= simplify_gen_binary (LSHIFTRT
, inner
, XEXP (op
, 0),
1046 GEN_INT (isize
- 1));
1049 if (GET_MODE_PRECISION (mode
) > isize
)
1050 return simplify_gen_unary (ZERO_EXTEND
, mode
, temp
, inner
);
1051 return simplify_gen_unary (TRUNCATE
, mode
, temp
, inner
);
1057 /* Don't optimize (lshiftrt (mult ...)) as it would interfere
1058 with the umulXi3_highpart patterns. */
1059 if (GET_CODE (op
) == LSHIFTRT
1060 && GET_CODE (XEXP (op
, 0)) == MULT
)
1063 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
1065 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
)))
1067 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1071 /* We can't handle truncation to a partial integer mode here
1072 because we don't know the real bitsize of the partial
1077 if (GET_MODE (op
) != VOIDmode
)
1079 temp
= simplify_truncation (mode
, op
, GET_MODE (op
));
1084 /* If we know that the value is already truncated, we can
1085 replace the TRUNCATE with a SUBREG. */
1086 if (GET_MODE_NUNITS (mode
) == 1
1087 && (TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op
))
1088 || truncated_to_mode (mode
, op
)))
1090 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1095 /* A truncate of a comparison can be replaced with a subreg if
1096 STORE_FLAG_VALUE permits. This is like the previous test,
1097 but it works even if the comparison is done in a mode larger
1098 than HOST_BITS_PER_WIDE_INT. */
1099 if (HWI_COMPUTABLE_MODE_P (mode
)
1100 && COMPARISON_P (op
)
1101 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0)
1103 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1108 /* A truncate of a memory is just loading the low part of the memory
1109 if we are not changing the meaning of the address. */
1110 if (GET_CODE (op
) == MEM
1111 && !VECTOR_MODE_P (mode
)
1112 && !MEM_VOLATILE_P (op
)
1113 && !mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
)))
1115 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1122 case FLOAT_TRUNCATE
:
1123 if (DECIMAL_FLOAT_MODE_P (mode
))
1126 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
1127 if (GET_CODE (op
) == FLOAT_EXTEND
1128 && GET_MODE (XEXP (op
, 0)) == mode
)
1129 return XEXP (op
, 0);
1131 /* (float_truncate:SF (float_truncate:DF foo:XF))
1132 = (float_truncate:SF foo:XF).
1133 This may eliminate double rounding, so it is unsafe.
1135 (float_truncate:SF (float_extend:XF foo:DF))
1136 = (float_truncate:SF foo:DF).
1138 (float_truncate:DF (float_extend:XF foo:SF))
1139 = (float_extend:SF foo:DF). */
1140 if ((GET_CODE (op
) == FLOAT_TRUNCATE
1141 && flag_unsafe_math_optimizations
)
1142 || GET_CODE (op
) == FLOAT_EXTEND
)
1143 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (op
,
1145 > GET_MODE_SIZE (mode
)
1146 ? FLOAT_TRUNCATE
: FLOAT_EXTEND
,
1148 XEXP (op
, 0), mode
);
1150 /* (float_truncate (float x)) is (float x) */
1151 if (GET_CODE (op
) == FLOAT
1152 && (flag_unsafe_math_optimizations
1153 || (SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1154 && ((unsigned)significand_size (GET_MODE (op
))
1155 >= (GET_MODE_PRECISION (GET_MODE (XEXP (op
, 0)))
1156 - num_sign_bit_copies (XEXP (op
, 0),
1157 GET_MODE (XEXP (op
, 0))))))))
1158 return simplify_gen_unary (FLOAT
, mode
,
1160 GET_MODE (XEXP (op
, 0)));
1162 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
1163 (OP:SF foo:SF) if OP is NEG or ABS. */
1164 if ((GET_CODE (op
) == ABS
1165 || GET_CODE (op
) == NEG
)
1166 && GET_CODE (XEXP (op
, 0)) == FLOAT_EXTEND
1167 && GET_MODE (XEXP (XEXP (op
, 0), 0)) == mode
)
1168 return simplify_gen_unary (GET_CODE (op
), mode
,
1169 XEXP (XEXP (op
, 0), 0), mode
);
1171 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
1172 is (float_truncate:SF x). */
1173 if (GET_CODE (op
) == SUBREG
1174 && subreg_lowpart_p (op
)
1175 && GET_CODE (SUBREG_REG (op
)) == FLOAT_TRUNCATE
)
1176 return SUBREG_REG (op
);
1180 if (DECIMAL_FLOAT_MODE_P (mode
))
1183 /* (float_extend (float_extend x)) is (float_extend x)
1185 (float_extend (float x)) is (float x) assuming that double
1186 rounding can't happen.
1188 if (GET_CODE (op
) == FLOAT_EXTEND
1189 || (GET_CODE (op
) == FLOAT
1190 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1191 && ((unsigned)significand_size (GET_MODE (op
))
1192 >= (GET_MODE_PRECISION (GET_MODE (XEXP (op
, 0)))
1193 - num_sign_bit_copies (XEXP (op
, 0),
1194 GET_MODE (XEXP (op
, 0)))))))
1195 return simplify_gen_unary (GET_CODE (op
), mode
,
1197 GET_MODE (XEXP (op
, 0)));
1202 /* (abs (neg <foo>)) -> (abs <foo>) */
1203 if (GET_CODE (op
) == NEG
)
1204 return simplify_gen_unary (ABS
, mode
, XEXP (op
, 0),
1205 GET_MODE (XEXP (op
, 0)));
1207 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
1209 if (GET_MODE (op
) == VOIDmode
)
1212 /* If operand is something known to be positive, ignore the ABS. */
1213 if (GET_CODE (op
) == FFS
|| GET_CODE (op
) == ABS
1214 || val_signbit_known_clear_p (GET_MODE (op
),
1215 nonzero_bits (op
, GET_MODE (op
))))
1218 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
1219 if (num_sign_bit_copies (op
, mode
) == GET_MODE_PRECISION (mode
))
1220 return gen_rtx_NEG (mode
, op
);
1225 /* (ffs (*_extend <X>)) = (ffs <X>) */
1226 if (GET_CODE (op
) == SIGN_EXTEND
1227 || GET_CODE (op
) == ZERO_EXTEND
)
1228 return simplify_gen_unary (FFS
, mode
, XEXP (op
, 0),
1229 GET_MODE (XEXP (op
, 0)));
1233 switch (GET_CODE (op
))
1237 /* (popcount (zero_extend <X>)) = (popcount <X>) */
1238 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1239 GET_MODE (XEXP (op
, 0)));
1243 /* Rotations don't affect popcount. */
1244 if (!side_effects_p (XEXP (op
, 1)))
1245 return simplify_gen_unary (POPCOUNT
, mode
, XEXP (op
, 0),
1246 GET_MODE (XEXP (op
, 0)));
1255 switch (GET_CODE (op
))
1261 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1262 GET_MODE (XEXP (op
, 0)));
1266 /* Rotations don't affect parity. */
1267 if (!side_effects_p (XEXP (op
, 1)))
1268 return simplify_gen_unary (PARITY
, mode
, XEXP (op
, 0),
1269 GET_MODE (XEXP (op
, 0)));
1278 /* (bswap (bswap x)) -> x. */
1279 if (GET_CODE (op
) == BSWAP
)
1280 return XEXP (op
, 0);
1284 /* (float (sign_extend <X>)) = (float <X>). */
1285 if (GET_CODE (op
) == SIGN_EXTEND
)
1286 return simplify_gen_unary (FLOAT
, mode
, XEXP (op
, 0),
1287 GET_MODE (XEXP (op
, 0)));
1291 /* (sign_extend (truncate (minus (label_ref L1) (label_ref L2))))
1292 becomes just the MINUS if its mode is MODE. This allows
1293 folding switch statements on machines using casesi (such as
1295 if (GET_CODE (op
) == TRUNCATE
1296 && GET_MODE (XEXP (op
, 0)) == mode
1297 && GET_CODE (XEXP (op
, 0)) == MINUS
1298 && GET_CODE (XEXP (XEXP (op
, 0), 0)) == LABEL_REF
1299 && GET_CODE (XEXP (XEXP (op
, 0), 1)) == LABEL_REF
)
1300 return XEXP (op
, 0);
1302 /* Extending a widening multiplication should be canonicalized to
1303 a wider widening multiplication. */
1304 if (GET_CODE (op
) == MULT
)
1306 rtx lhs
= XEXP (op
, 0);
1307 rtx rhs
= XEXP (op
, 1);
1308 enum rtx_code lcode
= GET_CODE (lhs
);
1309 enum rtx_code rcode
= GET_CODE (rhs
);
1311 /* Widening multiplies usually extend both operands, but sometimes
1312 they use a shift to extract a portion of a register. */
1313 if ((lcode
== SIGN_EXTEND
1314 || (lcode
== ASHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1315 && (rcode
== SIGN_EXTEND
1316 || (rcode
== ASHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1318 enum machine_mode lmode
= GET_MODE (lhs
);
1319 enum machine_mode rmode
= GET_MODE (rhs
);
1322 if (lcode
== ASHIFTRT
)
1323 /* Number of bits not shifted off the end. */
1324 bits
= GET_MODE_PRECISION (lmode
) - INTVAL (XEXP (lhs
, 1));
1325 else /* lcode == SIGN_EXTEND */
1326 /* Size of inner mode. */
1327 bits
= GET_MODE_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1329 if (rcode
== ASHIFTRT
)
1330 bits
+= GET_MODE_PRECISION (rmode
) - INTVAL (XEXP (rhs
, 1));
1331 else /* rcode == SIGN_EXTEND */
1332 bits
+= GET_MODE_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1334 /* We can only widen multiplies if the result is mathematiclly
1335 equivalent. I.e. if overflow was impossible. */
1336 if (bits
<= GET_MODE_PRECISION (GET_MODE (op
)))
1337 return simplify_gen_binary
1339 simplify_gen_unary (SIGN_EXTEND
, mode
, lhs
, lmode
),
1340 simplify_gen_unary (SIGN_EXTEND
, mode
, rhs
, rmode
));
1344 /* Check for a sign extension of a subreg of a promoted
1345 variable, where the promotion is sign-extended, and the
1346 target mode is the same as the variable's promotion. */
1347 if (GET_CODE (op
) == SUBREG
1348 && SUBREG_PROMOTED_VAR_P (op
)
1349 && ! SUBREG_PROMOTED_UNSIGNED_P (op
)
1350 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (XEXP (op
, 0))))
1352 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1357 /* (sign_extend:M (sign_extend:N <X>)) is (sign_extend:M <X>).
1358 (sign_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1359 if (GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
)
1361 gcc_assert (GET_MODE_BITSIZE (mode
)
1362 > GET_MODE_BITSIZE (GET_MODE (op
)));
1363 return simplify_gen_unary (GET_CODE (op
), mode
, XEXP (op
, 0),
1364 GET_MODE (XEXP (op
, 0)));
1367 /* (sign_extend:M (ashiftrt:N (ashift <X> (const_int I)) (const_int I)))
1368 is (sign_extend:M (subreg:O <X>)) if there is mode with
1369 GET_MODE_BITSIZE (N) - I bits.
1370 (sign_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1371 is similarly (zero_extend:M (subreg:O <X>)). */
1372 if ((GET_CODE (op
) == ASHIFTRT
|| GET_CODE (op
) == LSHIFTRT
)
1373 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1374 && CONST_INT_P (XEXP (op
, 1))
1375 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1376 && GET_MODE_BITSIZE (GET_MODE (op
)) > INTVAL (XEXP (op
, 1)))
1378 enum machine_mode tmode
1379 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (op
))
1380 - INTVAL (XEXP (op
, 1)), MODE_INT
, 1);
1381 gcc_assert (GET_MODE_BITSIZE (mode
)
1382 > GET_MODE_BITSIZE (GET_MODE (op
)));
1383 if (tmode
!= BLKmode
)
1386 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1388 return simplify_gen_unary (GET_CODE (op
) == ASHIFTRT
1389 ? SIGN_EXTEND
: ZERO_EXTEND
,
1390 mode
, inner
, tmode
);
1394 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1395 /* As we do not know which address space the pointer is referring to,
1396 we can do this only if the target does not support different pointer
1397 or address modes depending on the address space. */
1398 if (target_default_pointer_address_modes_p ()
1399 && ! POINTERS_EXTEND_UNSIGNED
1400 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1402 || (GET_CODE (op
) == SUBREG
1403 && REG_P (SUBREG_REG (op
))
1404 && REG_POINTER (SUBREG_REG (op
))
1405 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
1406 return convert_memory_address (Pmode
, op
);
1411 /* Check for a zero extension of a subreg of a promoted
1412 variable, where the promotion is zero-extended, and the
1413 target mode is the same as the variable's promotion. */
1414 if (GET_CODE (op
) == SUBREG
1415 && SUBREG_PROMOTED_VAR_P (op
)
1416 && SUBREG_PROMOTED_UNSIGNED_P (op
) > 0
1417 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (XEXP (op
, 0))))
1419 temp
= rtl_hooks
.gen_lowpart_no_emit (mode
, op
);
1424 /* Extending a widening multiplication should be canonicalized to
1425 a wider widening multiplication. */
1426 if (GET_CODE (op
) == MULT
)
1428 rtx lhs
= XEXP (op
, 0);
1429 rtx rhs
= XEXP (op
, 1);
1430 enum rtx_code lcode
= GET_CODE (lhs
);
1431 enum rtx_code rcode
= GET_CODE (rhs
);
1433 /* Widening multiplies usually extend both operands, but sometimes
1434 they use a shift to extract a portion of a register. */
1435 if ((lcode
== ZERO_EXTEND
1436 || (lcode
== LSHIFTRT
&& CONST_INT_P (XEXP (lhs
, 1))))
1437 && (rcode
== ZERO_EXTEND
1438 || (rcode
== LSHIFTRT
&& CONST_INT_P (XEXP (rhs
, 1)))))
1440 enum machine_mode lmode
= GET_MODE (lhs
);
1441 enum machine_mode rmode
= GET_MODE (rhs
);
1444 if (lcode
== LSHIFTRT
)
1445 /* Number of bits not shifted off the end. */
1446 bits
= GET_MODE_PRECISION (lmode
) - INTVAL (XEXP (lhs
, 1));
1447 else /* lcode == ZERO_EXTEND */
1448 /* Size of inner mode. */
1449 bits
= GET_MODE_PRECISION (GET_MODE (XEXP (lhs
, 0)));
1451 if (rcode
== LSHIFTRT
)
1452 bits
+= GET_MODE_PRECISION (rmode
) - INTVAL (XEXP (rhs
, 1));
1453 else /* rcode == ZERO_EXTEND */
1454 bits
+= GET_MODE_PRECISION (GET_MODE (XEXP (rhs
, 0)));
1456 /* We can only widen multiplies if the result is mathematiclly
1457 equivalent. I.e. if overflow was impossible. */
1458 if (bits
<= GET_MODE_PRECISION (GET_MODE (op
)))
1459 return simplify_gen_binary
1461 simplify_gen_unary (ZERO_EXTEND
, mode
, lhs
, lmode
),
1462 simplify_gen_unary (ZERO_EXTEND
, mode
, rhs
, rmode
));
1466 /* (zero_extend:M (zero_extend:N <X>)) is (zero_extend:M <X>). */
1467 if (GET_CODE (op
) == ZERO_EXTEND
)
1468 return simplify_gen_unary (ZERO_EXTEND
, mode
, XEXP (op
, 0),
1469 GET_MODE (XEXP (op
, 0)));
1471 /* (zero_extend:M (lshiftrt:N (ashift <X> (const_int I)) (const_int I)))
1472 is (zero_extend:M (subreg:O <X>)) if there is mode with
1473 GET_MODE_BITSIZE (N) - I bits. */
1474 if (GET_CODE (op
) == LSHIFTRT
1475 && GET_CODE (XEXP (op
, 0)) == ASHIFT
1476 && CONST_INT_P (XEXP (op
, 1))
1477 && XEXP (XEXP (op
, 0), 1) == XEXP (op
, 1)
1478 && GET_MODE_BITSIZE (GET_MODE (op
)) > INTVAL (XEXP (op
, 1)))
1480 enum machine_mode tmode
1481 = mode_for_size (GET_MODE_BITSIZE (GET_MODE (op
))
1482 - INTVAL (XEXP (op
, 1)), MODE_INT
, 1);
1483 if (tmode
!= BLKmode
)
1486 rtl_hooks
.gen_lowpart_no_emit (tmode
, XEXP (XEXP (op
, 0), 0));
1488 return simplify_gen_unary (ZERO_EXTEND
, mode
, inner
, tmode
);
1492 /* (zero_extend:M (subreg:N <X:O>)) is <X:O> (for M == O) or
1493 (zero_extend:M <X:O>), if X doesn't have any non-zero bits outside
1495 (zero_extend:SI (subreg:QI (and:SI (reg:SI) (const_int 63)) 0)) is
1496 (and:SI (reg:SI) (const_int 63)). */
1497 if (GET_CODE (op
) == SUBREG
1498 && GET_MODE_PRECISION (GET_MODE (op
))
1499 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op
)))
1500 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op
)))
1501 <= HOST_BITS_PER_WIDE_INT
1502 && GET_MODE_PRECISION (mode
)
1503 >= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op
)))
1504 && subreg_lowpart_p (op
)
1505 && (nonzero_bits (SUBREG_REG (op
), GET_MODE (SUBREG_REG (op
)))
1506 & ~GET_MODE_MASK (GET_MODE (op
))) == 0)
1508 if (GET_MODE_PRECISION (mode
)
1509 == GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op
))))
1510 return SUBREG_REG (op
);
1511 return simplify_gen_unary (ZERO_EXTEND
, mode
, SUBREG_REG (op
),
1512 GET_MODE (SUBREG_REG (op
)));
1515 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
1516 /* As we do not know which address space the pointer is referring to,
1517 we can do this only if the target does not support different pointer
1518 or address modes depending on the address space. */
1519 if (target_default_pointer_address_modes_p ()
1520 && POINTERS_EXTEND_UNSIGNED
> 0
1521 && mode
== Pmode
&& GET_MODE (op
) == ptr_mode
1523 || (GET_CODE (op
) == SUBREG
1524 && REG_P (SUBREG_REG (op
))
1525 && REG_POINTER (SUBREG_REG (op
))
1526 && GET_MODE (SUBREG_REG (op
)) == Pmode
)))
1527 return convert_memory_address (Pmode
, op
);
1538 /* Try to compute the value of a unary operation CODE whose output mode is to
1539 be MODE with input operand OP whose mode was originally OP_MODE.
1540 Return zero if the value cannot be computed. */
1542 simplify_const_unary_operation (enum rtx_code code
, enum machine_mode mode
,
1543 rtx op
, enum machine_mode op_mode
)
1545 unsigned int width
= GET_MODE_PRECISION (mode
);
1547 if (code
== VEC_DUPLICATE
)
1549 gcc_assert (VECTOR_MODE_P (mode
));
1550 if (GET_MODE (op
) != VOIDmode
)
1552 if (!VECTOR_MODE_P (GET_MODE (op
)))
1553 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE (op
));
1555 gcc_assert (GET_MODE_INNER (mode
) == GET_MODE_INNER
1558 if (CONST_SCALAR_INT_P (op
) || CONST_DOUBLE_AS_FLOAT_P (op
)
1559 || GET_CODE (op
) == CONST_VECTOR
)
1561 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
1562 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
1563 rtvec v
= rtvec_alloc (n_elts
);
1566 if (GET_CODE (op
) != CONST_VECTOR
)
1567 for (i
= 0; i
< n_elts
; i
++)
1568 RTVEC_ELT (v
, i
) = op
;
1571 enum machine_mode inmode
= GET_MODE (op
);
1572 int in_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (inmode
));
1573 unsigned in_n_elts
= (GET_MODE_SIZE (inmode
) / in_elt_size
);
1575 gcc_assert (in_n_elts
< n_elts
);
1576 gcc_assert ((n_elts
% in_n_elts
) == 0);
1577 for (i
= 0; i
< n_elts
; i
++)
1578 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (op
, i
% in_n_elts
);
1580 return gen_rtx_CONST_VECTOR (mode
, v
);
1584 if (VECTOR_MODE_P (mode
) && GET_CODE (op
) == CONST_VECTOR
)
1586 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
1587 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
1588 enum machine_mode opmode
= GET_MODE (op
);
1589 int op_elt_size
= GET_MODE_SIZE (GET_MODE_INNER (opmode
));
1590 unsigned op_n_elts
= (GET_MODE_SIZE (opmode
) / op_elt_size
);
1591 rtvec v
= rtvec_alloc (n_elts
);
1594 gcc_assert (op_n_elts
== n_elts
);
1595 for (i
= 0; i
< n_elts
; i
++)
1597 rtx x
= simplify_unary_operation (code
, GET_MODE_INNER (mode
),
1598 CONST_VECTOR_ELT (op
, i
),
1599 GET_MODE_INNER (opmode
));
1602 RTVEC_ELT (v
, i
) = x
;
1604 return gen_rtx_CONST_VECTOR (mode
, v
);
1607 /* The order of these tests is critical so that, for example, we don't
1608 check the wrong mode (input vs. output) for a conversion operation,
1609 such as FIX. At some point, this should be simplified. */
1611 if (code
== FLOAT
&& CONST_SCALAR_INT_P (op
))
1615 if (op_mode
== VOIDmode
)
1617 /* CONST_INT have VOIDmode as the mode. We assume that all
1618 the bits of the constant are significant, though, this is
1619 a dangerous assumption as many times CONST_INTs are
1620 created and used with garbage in the bits outside of the
1621 precision of the implied mode of the const_int. */
1622 op_mode
= mode_for_size (MAX_BITSIZE_MODE_ANY_INT
, MODE_INT
, 0);
1625 real_from_integer (&d
, mode
, std::make_pair (op
, op_mode
), SIGNED
);
1626 d
= real_value_truncate (mode
, d
);
1627 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1629 else if (code
== UNSIGNED_FLOAT
&& CONST_SCALAR_INT_P (op
))
1633 if (op_mode
== VOIDmode
)
1635 /* CONST_INT have VOIDmode as the mode. We assume that all
1636 the bits of the constant are significant, though, this is
1637 a dangerous assumption as many times CONST_INTs are
1638 created and used with garbage in the bits outside of the
1639 precision of the implied mode of the const_int. */
1640 op_mode
= mode_for_size (MAX_BITSIZE_MODE_ANY_INT
, MODE_INT
, 0);
1643 real_from_integer (&d
, mode
, std::make_pair (op
, op_mode
), UNSIGNED
);
1644 d
= real_value_truncate (mode
, d
);
1645 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1648 if (CONST_SCALAR_INT_P (op
) && width
> 0)
1651 enum machine_mode imode
= op_mode
== VOIDmode
? mode
: op_mode
;
1652 rtx_mode_t op0
= std::make_pair (op
, imode
);
1654 #if TARGET_SUPPORTS_WIDE_INT == 0
1655 /* This assert keeps the simplification from producing a result
1656 that cannot be represented in a CONST_DOUBLE but a lot of
1657 upstream callers expect that this function never fails to
1658 simplify something and so you if you added this to the test
1659 above the code would die later anyway. If this assert
1660 happens, you just need to make the port support wide int. */
1661 gcc_assert (width
<= HOST_BITS_PER_DOUBLE_INT
);
1667 result
= wi::bit_not (op0
);
1671 result
= wi::neg (op0
);
1675 result
= wi::abs (op0
);
1679 result
= wi::shwi (wi::ffs (op0
), mode
);
1683 result
= wi::shwi (wi::clz (op0
), mode
);
1687 result
= wi::shwi (wi::clrsb (op0
), mode
);
1691 result
= wi::shwi (wi::ctz (op0
), mode
);
1695 result
= wi::shwi (wi::popcount (op0
), mode
);
1699 result
= wi::shwi (wi::parity (op0
), mode
);
1703 result
= wide_int (op0
).bswap ();
1708 result
= wide_int::from (op0
, width
, UNSIGNED
);
1712 result
= wide_int::from (op0
, width
, SIGNED
);
1720 return immed_wide_int_const (result
, mode
);
1723 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
1724 && SCALAR_FLOAT_MODE_P (mode
)
1725 && SCALAR_FLOAT_MODE_P (GET_MODE (op
)))
1727 REAL_VALUE_TYPE d
, t
;
1728 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
1733 if (HONOR_SNANS (mode
) && real_isnan (&d
))
1735 real_sqrt (&t
, mode
, &d
);
1739 d
= real_value_abs (&d
);
1742 d
= real_value_negate (&d
);
1744 case FLOAT_TRUNCATE
:
1745 d
= real_value_truncate (mode
, d
);
1748 /* All this does is change the mode, unless changing
1750 if (GET_MODE_CLASS (mode
) != GET_MODE_CLASS (GET_MODE (op
)))
1751 real_convert (&d
, mode
, &d
);
1754 real_arithmetic (&d
, FIX_TRUNC_EXPR
, &d
, NULL
);
1761 real_to_target (tmp
, &d
, GET_MODE (op
));
1762 for (i
= 0; i
< 4; i
++)
1764 real_from_target (&d
, tmp
, mode
);
1770 return CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
1772 else if (CONST_DOUBLE_AS_FLOAT_P (op
)
1773 && SCALAR_FLOAT_MODE_P (GET_MODE (op
))
1774 && GET_MODE_CLASS (mode
) == MODE_INT
1777 /* Although the overflow semantics of RTL's FIX and UNSIGNED_FIX
1778 operators are intentionally left unspecified (to ease implementation
1779 by target backends), for consistency, this routine implements the
1780 same semantics for constant folding as used by the middle-end. */
1782 /* This was formerly used only for non-IEEE float.
1783 eggert@twinsun.com says it is safe for IEEE also. */
1784 REAL_VALUE_TYPE x
, t
;
1785 REAL_VALUE_FROM_CONST_DOUBLE (x
, op
);
1786 wide_int wmax
, wmin
;
1787 /* This is part of the abi to real_to_integer, but we check
1788 things before making this call. */
1794 if (REAL_VALUE_ISNAN (x
))
1797 /* Test against the signed upper bound. */
1798 wmax
= wi::max_value (width
, SIGNED
);
1799 real_from_integer (&t
, VOIDmode
, wmax
, SIGNED
);
1800 if (REAL_VALUES_LESS (t
, x
))
1801 return immed_wide_int_const (wmax
, mode
);
1803 /* Test against the signed lower bound. */
1804 wmin
= wi::min_value (width
, SIGNED
);
1805 real_from_integer (&t
, VOIDmode
, wmin
, SIGNED
);
1806 if (REAL_VALUES_LESS (x
, t
))
1807 return immed_wide_int_const (wmin
, mode
);
1809 return immed_wide_int_const (real_to_integer (&x
, &fail
, width
), mode
);
1813 if (REAL_VALUE_ISNAN (x
) || REAL_VALUE_NEGATIVE (x
))
1816 /* Test against the unsigned upper bound. */
1817 wmax
= wi::max_value (width
, UNSIGNED
);
1818 real_from_integer (&t
, VOIDmode
, wmax
, UNSIGNED
);
1819 if (REAL_VALUES_LESS (t
, x
))
1820 return immed_wide_int_const (wmax
, mode
);
1822 return immed_wide_int_const (real_to_integer (&t
, &fail
, width
), mode
);
1833 /* Subroutine of simplify_binary_operation to simplify a binary operation
1834 CODE that can commute with byte swapping, with result mode MODE and
1835 operating on OP0 and OP1. CODE is currently one of AND, IOR or XOR.
1836 Return zero if no simplification or canonicalization is possible. */
1839 simplify_byte_swapping_operation (enum rtx_code code
, enum machine_mode mode
,
1844 /* (op (bswap x) C1)) -> (bswap (op x C2)) with C2 swapped. */
1845 if (GET_CODE (op0
) == BSWAP
&& CONST_SCALAR_INT_P (op1
))
1847 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0),
1848 simplify_gen_unary (BSWAP
, mode
, op1
, mode
));
1849 return simplify_gen_unary (BSWAP
, mode
, tem
, mode
);
1852 /* (op (bswap x) (bswap y)) -> (bswap (op x y)). */
1853 if (GET_CODE (op0
) == BSWAP
&& GET_CODE (op1
) == BSWAP
)
1855 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
1856 return simplify_gen_unary (BSWAP
, mode
, tem
, mode
);
1862 /* Subroutine of simplify_binary_operation to simplify a commutative,
1863 associative binary operation CODE with result mode MODE, operating
1864 on OP0 and OP1. CODE is currently one of PLUS, MULT, AND, IOR, XOR,
1865 SMIN, SMAX, UMIN or UMAX. Return zero if no simplification or
1866 canonicalization is possible. */
1869 simplify_associative_operation (enum rtx_code code
, enum machine_mode mode
,
1874 /* Linearize the operator to the left. */
1875 if (GET_CODE (op1
) == code
)
1877 /* "(a op b) op (c op d)" becomes "((a op b) op c) op d)". */
1878 if (GET_CODE (op0
) == code
)
1880 tem
= simplify_gen_binary (code
, mode
, op0
, XEXP (op1
, 0));
1881 return simplify_gen_binary (code
, mode
, tem
, XEXP (op1
, 1));
1884 /* "a op (b op c)" becomes "(b op c) op a". */
1885 if (! swap_commutative_operands_p (op1
, op0
))
1886 return simplify_gen_binary (code
, mode
, op1
, op0
);
1893 if (GET_CODE (op0
) == code
)
1895 /* Canonicalize "(x op c) op y" as "(x op y) op c". */
1896 if (swap_commutative_operands_p (XEXP (op0
, 1), op1
))
1898 tem
= simplify_gen_binary (code
, mode
, XEXP (op0
, 0), op1
);
1899 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
1902 /* Attempt to simplify "(a op b) op c" as "a op (b op c)". */
1903 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 1), op1
);
1905 return simplify_gen_binary (code
, mode
, XEXP (op0
, 0), tem
);
1907 /* Attempt to simplify "(a op b) op c" as "(a op c) op b". */
1908 tem
= simplify_binary_operation (code
, mode
, XEXP (op0
, 0), op1
);
1910 return simplify_gen_binary (code
, mode
, tem
, XEXP (op0
, 1));
1917 /* Simplify a binary operation CODE with result mode MODE, operating on OP0
1918 and OP1. Return 0 if no simplification is possible.
1920 Don't use this for relational operations such as EQ or LT.
1921 Use simplify_relational_operation instead. */
1923 simplify_binary_operation (enum rtx_code code
, enum machine_mode mode
,
1926 rtx trueop0
, trueop1
;
1929 /* Relational operations don't work here. We must know the mode
1930 of the operands in order to do the comparison correctly.
1931 Assuming a full word can give incorrect results.
1932 Consider comparing 128 with -128 in QImode. */
1933 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMPARE
);
1934 gcc_assert (GET_RTX_CLASS (code
) != RTX_COMM_COMPARE
);
1936 /* Make sure the constant is second. */
1937 if (GET_RTX_CLASS (code
) == RTX_COMM_ARITH
1938 && swap_commutative_operands_p (op0
, op1
))
1940 tem
= op0
, op0
= op1
, op1
= tem
;
1943 trueop0
= avoid_constant_pool_reference (op0
);
1944 trueop1
= avoid_constant_pool_reference (op1
);
1946 tem
= simplify_const_binary_operation (code
, mode
, trueop0
, trueop1
);
1949 return simplify_binary_operation_1 (code
, mode
, op0
, op1
, trueop0
, trueop1
);
1952 /* Subroutine of simplify_binary_operation. Simplify a binary operation
1953 CODE with result mode MODE, operating on OP0 and OP1. If OP0 and/or
1954 OP1 are constant pool references, TRUEOP0 and TRUEOP1 represent the
1955 actual constants. */
1958 simplify_binary_operation_1 (enum rtx_code code
, enum machine_mode mode
,
1959 rtx op0
, rtx op1
, rtx trueop0
, rtx trueop1
)
1961 rtx tem
, reversed
, opleft
, opright
;
1963 unsigned int width
= GET_MODE_PRECISION (mode
);
1965 /* Even if we can't compute a constant result,
1966 there are some cases worth simplifying. */
1971 /* Maybe simplify x + 0 to x. The two expressions are equivalent
1972 when x is NaN, infinite, or finite and nonzero. They aren't
1973 when x is -0 and the rounding mode is not towards -infinity,
1974 since (-0) + 0 is then 0. */
1975 if (!HONOR_SIGNED_ZEROS (mode
) && trueop1
== CONST0_RTX (mode
))
1978 /* ((-a) + b) -> (b - a) and similarly for (a + (-b)). These
1979 transformations are safe even for IEEE. */
1980 if (GET_CODE (op0
) == NEG
)
1981 return simplify_gen_binary (MINUS
, mode
, op1
, XEXP (op0
, 0));
1982 else if (GET_CODE (op1
) == NEG
)
1983 return simplify_gen_binary (MINUS
, mode
, op0
, XEXP (op1
, 0));
1985 /* (~a) + 1 -> -a */
1986 if (INTEGRAL_MODE_P (mode
)
1987 && GET_CODE (op0
) == NOT
1988 && trueop1
== const1_rtx
)
1989 return simplify_gen_unary (NEG
, mode
, XEXP (op0
, 0), mode
);
1991 /* Handle both-operands-constant cases. We can only add
1992 CONST_INTs to constants since the sum of relocatable symbols
1993 can't be handled by most assemblers. Don't add CONST_INT
1994 to CONST_INT since overflow won't be computed properly if wider
1995 than HOST_BITS_PER_WIDE_INT. */
1997 if ((GET_CODE (op0
) == CONST
1998 || GET_CODE (op0
) == SYMBOL_REF
1999 || GET_CODE (op0
) == LABEL_REF
)
2000 && CONST_INT_P (op1
))
2001 return plus_constant (mode
, op0
, INTVAL (op1
));
2002 else if ((GET_CODE (op1
) == CONST
2003 || GET_CODE (op1
) == SYMBOL_REF
2004 || GET_CODE (op1
) == LABEL_REF
)
2005 && CONST_INT_P (op0
))
2006 return plus_constant (mode
, op1
, INTVAL (op0
));
2008 /* See if this is something like X * C - X or vice versa or
2009 if the multiplication is written as a shift. If so, we can
2010 distribute and make a new multiply, shift, or maybe just
2011 have X (if C is 2 in the example above). But don't make
2012 something more expensive than we had before. */
2014 if (SCALAR_INT_MODE_P (mode
))
2016 rtx lhs
= op0
, rhs
= op1
;
2018 wide_int coeff0
= wi::one (GET_MODE_PRECISION (mode
));
2019 wide_int coeff1
= wi::one (GET_MODE_PRECISION (mode
));
2021 if (GET_CODE (lhs
) == NEG
)
2023 coeff0
= wi::minus_one (GET_MODE_PRECISION (mode
));
2024 lhs
= XEXP (lhs
, 0);
2026 else if (GET_CODE (lhs
) == MULT
2027 && CONST_SCALAR_INT_P (XEXP (lhs
, 1)))
2029 coeff0
= std::make_pair (XEXP (lhs
, 1), mode
);
2030 lhs
= XEXP (lhs
, 0);
2032 else if (GET_CODE (lhs
) == ASHIFT
2033 && CONST_INT_P (XEXP (lhs
, 1))
2034 && INTVAL (XEXP (lhs
, 1)) >= 0
2035 && INTVAL (XEXP (lhs
, 1)) < GET_MODE_PRECISION (mode
))
2037 coeff0
= wi::set_bit_in_zero (INTVAL (XEXP (lhs
, 1)),
2038 GET_MODE_PRECISION (mode
));
2039 lhs
= XEXP (lhs
, 0);
2042 if (GET_CODE (rhs
) == NEG
)
2044 coeff1
= wi::minus_one (GET_MODE_PRECISION (mode
));
2045 rhs
= XEXP (rhs
, 0);
2047 else if (GET_CODE (rhs
) == MULT
2048 && CONST_INT_P (XEXP (rhs
, 1)))
2050 coeff1
= std::make_pair (XEXP (rhs
, 1), mode
);
2051 rhs
= XEXP (rhs
, 0);
2053 else if (GET_CODE (rhs
) == ASHIFT
2054 && CONST_INT_P (XEXP (rhs
, 1))
2055 && INTVAL (XEXP (rhs
, 1)) >= 0
2056 && INTVAL (XEXP (rhs
, 1)) < GET_MODE_PRECISION (mode
))
2058 coeff1
= wi::set_bit_in_zero (INTVAL (XEXP (rhs
, 1)),
2059 GET_MODE_PRECISION (mode
));
2060 rhs
= XEXP (rhs
, 0);
2063 if (rtx_equal_p (lhs
, rhs
))
2065 rtx orig
= gen_rtx_PLUS (mode
, op0
, op1
);
2067 bool speed
= optimize_function_for_speed_p (cfun
);
2069 coeff
= immed_wide_int_const (coeff0
+ coeff1
, mode
);
2071 tem
= simplify_gen_binary (MULT
, mode
, lhs
, coeff
);
2072 return set_src_cost (tem
, speed
) <= set_src_cost (orig
, speed
)
2077 /* (plus (xor X C1) C2) is (xor X (C1^C2)) if C2 is signbit. */
2078 if (CONST_SCALAR_INT_P (op1
)
2079 && GET_CODE (op0
) == XOR
2080 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
2081 && mode_signbit_p (mode
, op1
))
2082 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
2083 simplify_gen_binary (XOR
, mode
, op1
,
2086 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)). */
2087 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2088 && GET_CODE (op0
) == MULT
2089 && GET_CODE (XEXP (op0
, 0)) == NEG
)
2093 in1
= XEXP (XEXP (op0
, 0), 0);
2094 in2
= XEXP (op0
, 1);
2095 return simplify_gen_binary (MINUS
, mode
, op1
,
2096 simplify_gen_binary (MULT
, mode
,
2100 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
2101 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
2103 if (COMPARISON_P (op0
)
2104 && ((STORE_FLAG_VALUE
== -1 && trueop1
== const1_rtx
)
2105 || (STORE_FLAG_VALUE
== 1 && trueop1
== constm1_rtx
))
2106 && (reversed
= reversed_comparison (op0
, mode
)))
2108 simplify_gen_unary (NEG
, mode
, reversed
, mode
);
2110 /* If one of the operands is a PLUS or a MINUS, see if we can
2111 simplify this by the associative law.
2112 Don't use the associative law for floating point.
2113 The inaccuracy makes it nonassociative,
2114 and subtle programs can break if operations are associated. */
2116 if (INTEGRAL_MODE_P (mode
)
2117 && (plus_minus_operand_p (op0
)
2118 || plus_minus_operand_p (op1
))
2119 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
2122 /* Reassociate floating point addition only when the user
2123 specifies associative math operations. */
2124 if (FLOAT_MODE_P (mode
)
2125 && flag_associative_math
)
2127 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2134 /* Convert (compare (gt (flags) 0) (lt (flags) 0)) to (flags). */
2135 if (((GET_CODE (op0
) == GT
&& GET_CODE (op1
) == LT
)
2136 || (GET_CODE (op0
) == GTU
&& GET_CODE (op1
) == LTU
))
2137 && XEXP (op0
, 1) == const0_rtx
&& XEXP (op1
, 1) == const0_rtx
)
2139 rtx xop00
= XEXP (op0
, 0);
2140 rtx xop10
= XEXP (op1
, 0);
2143 if (GET_CODE (xop00
) == CC0
&& GET_CODE (xop10
) == CC0
)
2145 if (REG_P (xop00
) && REG_P (xop10
)
2146 && GET_MODE (xop00
) == GET_MODE (xop10
)
2147 && REGNO (xop00
) == REGNO (xop10
)
2148 && GET_MODE_CLASS (GET_MODE (xop00
)) == MODE_CC
2149 && GET_MODE_CLASS (GET_MODE (xop10
)) == MODE_CC
)
2156 /* We can't assume x-x is 0 even with non-IEEE floating point,
2157 but since it is zero except in very strange circumstances, we
2158 will treat it as zero with -ffinite-math-only. */
2159 if (rtx_equal_p (trueop0
, trueop1
)
2160 && ! side_effects_p (op0
)
2161 && (!FLOAT_MODE_P (mode
) || !HONOR_NANS (mode
)))
2162 return CONST0_RTX (mode
);
2164 /* Change subtraction from zero into negation. (0 - x) is the
2165 same as -x when x is NaN, infinite, or finite and nonzero.
2166 But if the mode has signed zeros, and does not round towards
2167 -infinity, then 0 - 0 is 0, not -0. */
2168 if (!HONOR_SIGNED_ZEROS (mode
) && trueop0
== CONST0_RTX (mode
))
2169 return simplify_gen_unary (NEG
, mode
, op1
, mode
);
2171 /* (-1 - a) is ~a. */
2172 if (trueop0
== constm1_rtx
)
2173 return simplify_gen_unary (NOT
, mode
, op1
, mode
);
2175 /* Subtracting 0 has no effect unless the mode has signed zeros
2176 and supports rounding towards -infinity. In such a case,
2178 if (!(HONOR_SIGNED_ZEROS (mode
)
2179 && HONOR_SIGN_DEPENDENT_ROUNDING (mode
))
2180 && trueop1
== CONST0_RTX (mode
))
2183 /* See if this is something like X * C - X or vice versa or
2184 if the multiplication is written as a shift. If so, we can
2185 distribute and make a new multiply, shift, or maybe just
2186 have X (if C is 2 in the example above). But don't make
2187 something more expensive than we had before. */
2189 if (SCALAR_INT_MODE_P (mode
))
2191 rtx lhs
= op0
, rhs
= op1
;
2193 wide_int coeff0
= wi::one (GET_MODE_PRECISION (mode
));
2194 wide_int negcoeff1
= wi::minus_one (GET_MODE_PRECISION (mode
));
2196 if (GET_CODE (lhs
) == NEG
)
2198 coeff0
= wi::minus_one (GET_MODE_PRECISION (mode
));
2199 lhs
= XEXP (lhs
, 0);
2201 else if (GET_CODE (lhs
) == MULT
2202 && CONST_SCALAR_INT_P (XEXP (lhs
, 1)))
2204 coeff0
= std::make_pair (XEXP (lhs
, 1), mode
);
2205 lhs
= XEXP (lhs
, 0);
2207 else if (GET_CODE (lhs
) == ASHIFT
2208 && CONST_INT_P (XEXP (lhs
, 1))
2209 && INTVAL (XEXP (lhs
, 1)) >= 0
2210 && INTVAL (XEXP (lhs
, 1)) < GET_MODE_PRECISION (mode
))
2212 coeff0
= wi::set_bit_in_zero (INTVAL (XEXP (lhs
, 1)),
2213 GET_MODE_PRECISION (mode
));
2214 lhs
= XEXP (lhs
, 0);
2217 if (GET_CODE (rhs
) == NEG
)
2219 negcoeff1
= wi::one (GET_MODE_PRECISION (mode
));
2220 rhs
= XEXP (rhs
, 0);
2222 else if (GET_CODE (rhs
) == MULT
2223 && CONST_INT_P (XEXP (rhs
, 1)))
2225 negcoeff1
= -wide_int (std::make_pair (XEXP (rhs
, 1), mode
));
2226 rhs
= XEXP (rhs
, 0);
2228 else if (GET_CODE (rhs
) == ASHIFT
2229 && CONST_INT_P (XEXP (rhs
, 1))
2230 && INTVAL (XEXP (rhs
, 1)) >= 0
2231 && INTVAL (XEXP (rhs
, 1)) < GET_MODE_PRECISION (mode
))
2233 negcoeff1
= wi::set_bit_in_zero (INTVAL (XEXP (rhs
, 1)),
2234 GET_MODE_PRECISION (mode
));
2235 negcoeff1
= -negcoeff1
;
2236 rhs
= XEXP (rhs
, 0);
2239 if (rtx_equal_p (lhs
, rhs
))
2241 rtx orig
= gen_rtx_MINUS (mode
, op0
, op1
);
2243 bool speed
= optimize_function_for_speed_p (cfun
);
2245 coeff
= immed_wide_int_const (coeff0
+ negcoeff1
, mode
);
2247 tem
= simplify_gen_binary (MULT
, mode
, lhs
, coeff
);
2248 return set_src_cost (tem
, speed
) <= set_src_cost (orig
, speed
)
2253 /* (a - (-b)) -> (a + b). True even for IEEE. */
2254 if (GET_CODE (op1
) == NEG
)
2255 return simplify_gen_binary (PLUS
, mode
, op0
, XEXP (op1
, 0));
2257 /* (-x - c) may be simplified as (-c - x). */
2258 if (GET_CODE (op0
) == NEG
2259 && (CONST_SCALAR_INT_P (op1
) || CONST_DOUBLE_AS_FLOAT_P (op1
)))
2261 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
2263 return simplify_gen_binary (MINUS
, mode
, tem
, XEXP (op0
, 0));
2266 /* Don't let a relocatable value get a negative coeff. */
2267 if (CONST_INT_P (op1
) && GET_MODE (op0
) != VOIDmode
)
2268 return simplify_gen_binary (PLUS
, mode
,
2270 neg_const_int (mode
, op1
));
2272 /* (x - (x & y)) -> (x & ~y) */
2273 if (INTEGRAL_MODE_P (mode
) && GET_CODE (op1
) == AND
)
2275 if (rtx_equal_p (op0
, XEXP (op1
, 0)))
2277 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 1),
2278 GET_MODE (XEXP (op1
, 1)));
2279 return simplify_gen_binary (AND
, mode
, op0
, tem
);
2281 if (rtx_equal_p (op0
, XEXP (op1
, 1)))
2283 tem
= simplify_gen_unary (NOT
, mode
, XEXP (op1
, 0),
2284 GET_MODE (XEXP (op1
, 0)));
2285 return simplify_gen_binary (AND
, mode
, op0
, tem
);
2289 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
2290 by reversing the comparison code if valid. */
2291 if (STORE_FLAG_VALUE
== 1
2292 && trueop0
== const1_rtx
2293 && COMPARISON_P (op1
)
2294 && (reversed
= reversed_comparison (op1
, mode
)))
2297 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A). */
2298 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2299 && GET_CODE (op1
) == MULT
2300 && GET_CODE (XEXP (op1
, 0)) == NEG
)
2304 in1
= XEXP (XEXP (op1
, 0), 0);
2305 in2
= XEXP (op1
, 1);
2306 return simplify_gen_binary (PLUS
, mode
,
2307 simplify_gen_binary (MULT
, mode
,
2312 /* Canonicalize (minus (neg A) (mult B C)) to
2313 (minus (mult (neg B) C) A). */
2314 if (!HONOR_SIGN_DEPENDENT_ROUNDING (mode
)
2315 && GET_CODE (op1
) == MULT
2316 && GET_CODE (op0
) == NEG
)
2320 in1
= simplify_gen_unary (NEG
, mode
, XEXP (op1
, 0), mode
);
2321 in2
= XEXP (op1
, 1);
2322 return simplify_gen_binary (MINUS
, mode
,
2323 simplify_gen_binary (MULT
, mode
,
2328 /* If one of the operands is a PLUS or a MINUS, see if we can
2329 simplify this by the associative law. This will, for example,
2330 canonicalize (minus A (plus B C)) to (minus (minus A B) C).
2331 Don't use the associative law for floating point.
2332 The inaccuracy makes it nonassociative,
2333 and subtle programs can break if operations are associated. */
2335 if (INTEGRAL_MODE_P (mode
)
2336 && (plus_minus_operand_p (op0
)
2337 || plus_minus_operand_p (op1
))
2338 && (tem
= simplify_plus_minus (code
, mode
, op0
, op1
)) != 0)
2343 if (trueop1
== constm1_rtx
)
2344 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2346 if (GET_CODE (op0
) == NEG
)
2348 rtx temp
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
2349 /* If op1 is a MULT as well and simplify_unary_operation
2350 just moved the NEG to the second operand, simplify_gen_binary
2351 below could through simplify_associative_operation move
2352 the NEG around again and recurse endlessly. */
2354 && GET_CODE (op1
) == MULT
2355 && GET_CODE (temp
) == MULT
2356 && XEXP (op1
, 0) == XEXP (temp
, 0)
2357 && GET_CODE (XEXP (temp
, 1)) == NEG
2358 && XEXP (op1
, 1) == XEXP (XEXP (temp
, 1), 0))
2361 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), temp
);
2363 if (GET_CODE (op1
) == NEG
)
2365 rtx temp
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
2366 /* If op0 is a MULT as well and simplify_unary_operation
2367 just moved the NEG to the second operand, simplify_gen_binary
2368 below could through simplify_associative_operation move
2369 the NEG around again and recurse endlessly. */
2371 && GET_CODE (op0
) == MULT
2372 && GET_CODE (temp
) == MULT
2373 && XEXP (op0
, 0) == XEXP (temp
, 0)
2374 && GET_CODE (XEXP (temp
, 1)) == NEG
2375 && XEXP (op0
, 1) == XEXP (XEXP (temp
, 1), 0))
2378 return simplify_gen_binary (MULT
, mode
, temp
, XEXP (op1
, 0));
2381 /* Maybe simplify x * 0 to 0. The reduction is not valid if
2382 x is NaN, since x * 0 is then also NaN. Nor is it valid
2383 when the mode has signed zeros, since multiplying a negative
2384 number by 0 will give -0, not 0. */
2385 if (!HONOR_NANS (mode
)
2386 && !HONOR_SIGNED_ZEROS (mode
)
2387 && trueop1
== CONST0_RTX (mode
)
2388 && ! side_effects_p (op0
))
2391 /* In IEEE floating point, x*1 is not equivalent to x for
2393 if (!HONOR_SNANS (mode
)
2394 && trueop1
== CONST1_RTX (mode
))
2397 /* Convert multiply by constant power of two into shift. */
2398 if (CONST_SCALAR_INT_P (trueop1
))
2400 val
= wi::exact_log2 (std::make_pair (trueop1
, mode
));
2401 if (val
>= 0 && val
< GET_MODE_BITSIZE (mode
))
2402 return simplify_gen_binary (ASHIFT
, mode
, op0
, GEN_INT (val
));
2405 /* x*2 is x+x and x*(-1) is -x */
2406 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
2407 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop1
))
2408 && !DECIMAL_FLOAT_MODE_P (GET_MODE (trueop1
))
2409 && GET_MODE (op0
) == mode
)
2412 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
2414 if (REAL_VALUES_EQUAL (d
, dconst2
))
2415 return simplify_gen_binary (PLUS
, mode
, op0
, copy_rtx (op0
));
2417 if (!HONOR_SNANS (mode
)
2418 && REAL_VALUES_EQUAL (d
, dconstm1
))
2419 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2422 /* Optimize -x * -x as x * x. */
2423 if (FLOAT_MODE_P (mode
)
2424 && GET_CODE (op0
) == NEG
2425 && GET_CODE (op1
) == NEG
2426 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2427 && !side_effects_p (XEXP (op0
, 0)))
2428 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2430 /* Likewise, optimize abs(x) * abs(x) as x * x. */
2431 if (SCALAR_FLOAT_MODE_P (mode
)
2432 && GET_CODE (op0
) == ABS
2433 && GET_CODE (op1
) == ABS
2434 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
2435 && !side_effects_p (XEXP (op0
, 0)))
2436 return simplify_gen_binary (MULT
, mode
, XEXP (op0
, 0), XEXP (op1
, 0));
2438 /* Reassociate multiplication, but for floating point MULTs
2439 only when the user specifies unsafe math optimizations. */
2440 if (! FLOAT_MODE_P (mode
)
2441 || flag_unsafe_math_optimizations
)
2443 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2450 if (trueop1
== CONST0_RTX (mode
))
2452 if (INTEGRAL_MODE_P (mode
)
2453 && trueop1
== CONSTM1_RTX (mode
)
2454 && !side_effects_p (op0
))
2456 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
2458 /* A | (~A) -> -1 */
2459 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
2460 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
2461 && ! side_effects_p (op0
)
2462 && SCALAR_INT_MODE_P (mode
))
2465 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
2466 if (CONST_INT_P (op1
)
2467 && HWI_COMPUTABLE_MODE_P (mode
)
2468 && (nonzero_bits (op0
, mode
) & ~UINTVAL (op1
)) == 0
2469 && !side_effects_p (op0
))
2472 /* Canonicalize (X & C1) | C2. */
2473 if (GET_CODE (op0
) == AND
2474 && CONST_INT_P (trueop1
)
2475 && CONST_INT_P (XEXP (op0
, 1)))
2477 HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
2478 HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
2479 HOST_WIDE_INT c2
= INTVAL (trueop1
);
2481 /* If (C1&C2) == C1, then (X&C1)|C2 becomes X. */
2483 && !side_effects_p (XEXP (op0
, 0)))
2486 /* If (C1|C2) == ~0 then (X&C1)|C2 becomes X|C2. */
2487 if (((c1
|c2
) & mask
) == mask
)
2488 return simplify_gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
);
2490 /* Minimize the number of bits set in C1, i.e. C1 := C1 & ~C2. */
2491 if (((c1
& ~c2
) & mask
) != (c1
& mask
))
2493 tem
= simplify_gen_binary (AND
, mode
, XEXP (op0
, 0),
2494 gen_int_mode (c1
& ~c2
, mode
));
2495 return simplify_gen_binary (IOR
, mode
, tem
, op1
);
2499 /* Convert (A & B) | A to A. */
2500 if (GET_CODE (op0
) == AND
2501 && (rtx_equal_p (XEXP (op0
, 0), op1
)
2502 || rtx_equal_p (XEXP (op0
, 1), op1
))
2503 && ! side_effects_p (XEXP (op0
, 0))
2504 && ! side_effects_p (XEXP (op0
, 1)))
2507 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
2508 mode size to (rotate A CX). */
2510 if (GET_CODE (op1
) == ASHIFT
2511 || GET_CODE (op1
) == SUBREG
)
2522 if (GET_CODE (opleft
) == ASHIFT
&& GET_CODE (opright
) == LSHIFTRT
2523 && rtx_equal_p (XEXP (opleft
, 0), XEXP (opright
, 0))
2524 && CONST_INT_P (XEXP (opleft
, 1))
2525 && CONST_INT_P (XEXP (opright
, 1))
2526 && (INTVAL (XEXP (opleft
, 1)) + INTVAL (XEXP (opright
, 1))
2527 == GET_MODE_PRECISION (mode
)))
2528 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0), XEXP (opleft
, 1));
2530 /* Same, but for ashift that has been "simplified" to a wider mode
2531 by simplify_shift_const. */
2533 if (GET_CODE (opleft
) == SUBREG
2534 && GET_CODE (SUBREG_REG (opleft
)) == ASHIFT
2535 && GET_CODE (opright
) == LSHIFTRT
2536 && GET_CODE (XEXP (opright
, 0)) == SUBREG
2537 && GET_MODE (opleft
) == GET_MODE (XEXP (opright
, 0))
2538 && SUBREG_BYTE (opleft
) == SUBREG_BYTE (XEXP (opright
, 0))
2539 && (GET_MODE_SIZE (GET_MODE (opleft
))
2540 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (opleft
))))
2541 && rtx_equal_p (XEXP (SUBREG_REG (opleft
), 0),
2542 SUBREG_REG (XEXP (opright
, 0)))
2543 && CONST_INT_P (XEXP (SUBREG_REG (opleft
), 1))
2544 && CONST_INT_P (XEXP (opright
, 1))
2545 && (INTVAL (XEXP (SUBREG_REG (opleft
), 1)) + INTVAL (XEXP (opright
, 1))
2546 == GET_MODE_PRECISION (mode
)))
2547 return gen_rtx_ROTATE (mode
, XEXP (opright
, 0),
2548 XEXP (SUBREG_REG (opleft
), 1));
2550 /* If we have (ior (and (X C1) C2)), simplify this by making
2551 C1 as small as possible if C1 actually changes. */
2552 if (CONST_INT_P (op1
)
2553 && (HWI_COMPUTABLE_MODE_P (mode
)
2554 || INTVAL (op1
) > 0)
2555 && GET_CODE (op0
) == AND
2556 && CONST_INT_P (XEXP (op0
, 1))
2557 && CONST_INT_P (op1
)
2558 && (UINTVAL (XEXP (op0
, 1)) & UINTVAL (op1
)) != 0)
2560 rtx tmp
= simplify_gen_binary (AND
, mode
, XEXP (op0
, 0),
2561 gen_int_mode (UINTVAL (XEXP (op0
, 1))
2564 return simplify_gen_binary (IOR
, mode
, tmp
, op1
);
2567 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
2568 a (sign_extend (plus ...)). Then check if OP1 is a CONST_INT and
2569 the PLUS does not affect any of the bits in OP1: then we can do
2570 the IOR as a PLUS and we can associate. This is valid if OP1
2571 can be safely shifted left C bits. */
2572 if (CONST_INT_P (trueop1
) && GET_CODE (op0
) == ASHIFTRT
2573 && GET_CODE (XEXP (op0
, 0)) == PLUS
2574 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
2575 && CONST_INT_P (XEXP (op0
, 1))
2576 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
2578 int count
= INTVAL (XEXP (op0
, 1));
2579 HOST_WIDE_INT mask
= INTVAL (trueop1
) << count
;
2581 if (mask
>> count
== INTVAL (trueop1
)
2582 && trunc_int_for_mode (mask
, mode
) == mask
2583 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
2584 return simplify_gen_binary (ASHIFTRT
, mode
,
2585 plus_constant (mode
, XEXP (op0
, 0),
2590 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
2594 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2600 if (trueop1
== CONST0_RTX (mode
))
2602 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
2603 return simplify_gen_unary (NOT
, mode
, op0
, mode
);
2604 if (rtx_equal_p (trueop0
, trueop1
)
2605 && ! side_effects_p (op0
)
2606 && GET_MODE_CLASS (mode
) != MODE_CC
)
2607 return CONST0_RTX (mode
);
2609 /* Canonicalize XOR of the most significant bit to PLUS. */
2610 if (CONST_SCALAR_INT_P (op1
)
2611 && mode_signbit_p (mode
, op1
))
2612 return simplify_gen_binary (PLUS
, mode
, op0
, op1
);
2613 /* (xor (plus X C1) C2) is (xor X (C1^C2)) if C1 is signbit. */
2614 if (CONST_SCALAR_INT_P (op1
)
2615 && GET_CODE (op0
) == PLUS
2616 && CONST_SCALAR_INT_P (XEXP (op0
, 1))
2617 && mode_signbit_p (mode
, XEXP (op0
, 1)))
2618 return simplify_gen_binary (XOR
, mode
, XEXP (op0
, 0),
2619 simplify_gen_binary (XOR
, mode
, op1
,
2622 /* If we are XORing two things that have no bits in common,
2623 convert them into an IOR. This helps to detect rotation encoded
2624 using those methods and possibly other simplifications. */
2626 if (HWI_COMPUTABLE_MODE_P (mode
)
2627 && (nonzero_bits (op0
, mode
)
2628 & nonzero_bits (op1
, mode
)) == 0)
2629 return (simplify_gen_binary (IOR
, mode
, op0
, op1
));
2631 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
2632 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
2635 int num_negated
= 0;
2637 if (GET_CODE (op0
) == NOT
)
2638 num_negated
++, op0
= XEXP (op0
, 0);
2639 if (GET_CODE (op1
) == NOT
)
2640 num_negated
++, op1
= XEXP (op1
, 0);
2642 if (num_negated
== 2)
2643 return simplify_gen_binary (XOR
, mode
, op0
, op1
);
2644 else if (num_negated
== 1)
2645 return simplify_gen_unary (NOT
, mode
,
2646 simplify_gen_binary (XOR
, mode
, op0
, op1
),
2650 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
2651 correspond to a machine insn or result in further simplifications
2652 if B is a constant. */
2654 if (GET_CODE (op0
) == AND
2655 && rtx_equal_p (XEXP (op0
, 1), op1
)
2656 && ! side_effects_p (op1
))
2657 return simplify_gen_binary (AND
, mode
,
2658 simplify_gen_unary (NOT
, mode
,
2659 XEXP (op0
, 0), mode
),
2662 else if (GET_CODE (op0
) == AND
2663 && rtx_equal_p (XEXP (op0
, 0), op1
)
2664 && ! side_effects_p (op1
))
2665 return simplify_gen_binary (AND
, mode
,
2666 simplify_gen_unary (NOT
, mode
,
2667 XEXP (op0
, 1), mode
),
2670 /* Given (xor (and A B) C), using P^Q == (~P&Q) | (~Q&P),
2671 we can transform like this:
2672 (A&B)^C == ~(A&B)&C | ~C&(A&B)
2673 == (~A|~B)&C | ~C&(A&B) * DeMorgan's Law
2674 == ~A&C | ~B&C | A&(~C&B) * Distribute and re-order
2675 Attempt a few simplifications when B and C are both constants. */
2676 if (GET_CODE (op0
) == AND
2677 && CONST_INT_P (op1
)
2678 && CONST_INT_P (XEXP (op0
, 1)))
2680 rtx a
= XEXP (op0
, 0);
2681 rtx b
= XEXP (op0
, 1);
2683 HOST_WIDE_INT bval
= INTVAL (b
);
2684 HOST_WIDE_INT cval
= INTVAL (c
);
2687 = simplify_binary_operation (AND
, mode
,
2688 simplify_gen_unary (NOT
, mode
, a
, mode
),
2690 if ((~cval
& bval
) == 0)
2692 /* Try to simplify ~A&C | ~B&C. */
2693 if (na_c
!= NULL_RTX
)
2694 return simplify_gen_binary (IOR
, mode
, na_c
,
2695 gen_int_mode (~bval
& cval
, mode
));
2699 /* If ~A&C is zero, simplify A&(~C&B) | ~B&C. */
2700 if (na_c
== const0_rtx
)
2702 rtx a_nc_b
= simplify_gen_binary (AND
, mode
, a
,
2703 gen_int_mode (~cval
& bval
,
2705 return simplify_gen_binary (IOR
, mode
, a_nc_b
,
2706 gen_int_mode (~bval
& cval
,
2712 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
2713 comparison if STORE_FLAG_VALUE is 1. */
2714 if (STORE_FLAG_VALUE
== 1
2715 && trueop1
== const1_rtx
2716 && COMPARISON_P (op0
)
2717 && (reversed
= reversed_comparison (op0
, mode
)))
2720 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
2721 is (lt foo (const_int 0)), so we can perform the above
2722 simplification if STORE_FLAG_VALUE is 1. */
2724 if (STORE_FLAG_VALUE
== 1
2725 && trueop1
== const1_rtx
2726 && GET_CODE (op0
) == LSHIFTRT
2727 && CONST_INT_P (XEXP (op0
, 1))
2728 && INTVAL (XEXP (op0
, 1)) == GET_MODE_PRECISION (mode
) - 1)
2729 return gen_rtx_GE (mode
, XEXP (op0
, 0), const0_rtx
);
2731 /* (xor (comparison foo bar) (const_int sign-bit))
2732 when STORE_FLAG_VALUE is the sign bit. */
2733 if (val_signbit_p (mode
, STORE_FLAG_VALUE
)
2734 && trueop1
== const_true_rtx
2735 && COMPARISON_P (op0
)
2736 && (reversed
= reversed_comparison (op0
, mode
)))
2739 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
2743 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2749 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
2751 if (INTEGRAL_MODE_P (mode
) && trueop1
== CONSTM1_RTX (mode
))
2753 if (HWI_COMPUTABLE_MODE_P (mode
))
2755 HOST_WIDE_INT nzop0
= nonzero_bits (trueop0
, mode
);
2756 HOST_WIDE_INT nzop1
;
2757 if (CONST_INT_P (trueop1
))
2759 HOST_WIDE_INT val1
= INTVAL (trueop1
);
2760 /* If we are turning off bits already known off in OP0, we need
2762 if ((nzop0
& ~val1
) == 0)
2765 nzop1
= nonzero_bits (trueop1
, mode
);
2766 /* If we are clearing all the nonzero bits, the result is zero. */
2767 if ((nzop1
& nzop0
) == 0
2768 && !side_effects_p (op0
) && !side_effects_p (op1
))
2769 return CONST0_RTX (mode
);
2771 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
)
2772 && GET_MODE_CLASS (mode
) != MODE_CC
)
2775 if (((GET_CODE (op0
) == NOT
&& rtx_equal_p (XEXP (op0
, 0), op1
))
2776 || (GET_CODE (op1
) == NOT
&& rtx_equal_p (XEXP (op1
, 0), op0
)))
2777 && ! side_effects_p (op0
)
2778 && GET_MODE_CLASS (mode
) != MODE_CC
)
2779 return CONST0_RTX (mode
);
2781 /* Transform (and (extend X) C) into (zero_extend (and X C)) if
2782 there are no nonzero bits of C outside of X's mode. */
2783 if ((GET_CODE (op0
) == SIGN_EXTEND
2784 || GET_CODE (op0
) == ZERO_EXTEND
)
2785 && CONST_INT_P (trueop1
)
2786 && HWI_COMPUTABLE_MODE_P (mode
)
2787 && (~GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))
2788 & UINTVAL (trueop1
)) == 0)
2790 enum machine_mode imode
= GET_MODE (XEXP (op0
, 0));
2791 tem
= simplify_gen_binary (AND
, imode
, XEXP (op0
, 0),
2792 gen_int_mode (INTVAL (trueop1
),
2794 return simplify_gen_unary (ZERO_EXTEND
, mode
, tem
, imode
);
2797 /* Transform (and (truncate X) C) into (truncate (and X C)). This way
2798 we might be able to further simplify the AND with X and potentially
2799 remove the truncation altogether. */
2800 if (GET_CODE (op0
) == TRUNCATE
&& CONST_INT_P (trueop1
))
2802 rtx x
= XEXP (op0
, 0);
2803 enum machine_mode xmode
= GET_MODE (x
);
2804 tem
= simplify_gen_binary (AND
, xmode
, x
,
2805 gen_int_mode (INTVAL (trueop1
), xmode
));
2806 return simplify_gen_unary (TRUNCATE
, mode
, tem
, xmode
);
2809 /* Canonicalize (A | C1) & C2 as (A & C2) | (C1 & C2). */
2810 if (GET_CODE (op0
) == IOR
2811 && CONST_INT_P (trueop1
)
2812 && CONST_INT_P (XEXP (op0
, 1)))
2814 HOST_WIDE_INT tmp
= INTVAL (trueop1
) & INTVAL (XEXP (op0
, 1));
2815 return simplify_gen_binary (IOR
, mode
,
2816 simplify_gen_binary (AND
, mode
,
2817 XEXP (op0
, 0), op1
),
2818 gen_int_mode (tmp
, mode
));
2821 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
2822 insn (and may simplify more). */
2823 if (GET_CODE (op0
) == XOR
2824 && rtx_equal_p (XEXP (op0
, 0), op1
)
2825 && ! side_effects_p (op1
))
2826 return simplify_gen_binary (AND
, mode
,
2827 simplify_gen_unary (NOT
, mode
,
2828 XEXP (op0
, 1), mode
),
2831 if (GET_CODE (op0
) == XOR
2832 && rtx_equal_p (XEXP (op0
, 1), op1
)
2833 && ! side_effects_p (op1
))
2834 return simplify_gen_binary (AND
, mode
,
2835 simplify_gen_unary (NOT
, mode
,
2836 XEXP (op0
, 0), mode
),
2839 /* Similarly for (~(A ^ B)) & A. */
2840 if (GET_CODE (op0
) == NOT
2841 && GET_CODE (XEXP (op0
, 0)) == XOR
2842 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
2843 && ! side_effects_p (op1
))
2844 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
2846 if (GET_CODE (op0
) == NOT
2847 && GET_CODE (XEXP (op0
, 0)) == XOR
2848 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
2849 && ! side_effects_p (op1
))
2850 return simplify_gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
2852 /* Convert (A | B) & A to A. */
2853 if (GET_CODE (op0
) == IOR
2854 && (rtx_equal_p (XEXP (op0
, 0), op1
)
2855 || rtx_equal_p (XEXP (op0
, 1), op1
))
2856 && ! side_effects_p (XEXP (op0
, 0))
2857 && ! side_effects_p (XEXP (op0
, 1)))
2860 /* For constants M and N, if M == (1LL << cst) - 1 && (N & M) == M,
2861 ((A & N) + B) & M -> (A + B) & M
2862 Similarly if (N & M) == 0,
2863 ((A | N) + B) & M -> (A + B) & M
2864 and for - instead of + and/or ^ instead of |.
2865 Also, if (N & M) == 0, then
2866 (A +- N) & M -> A & M. */
2867 if (CONST_INT_P (trueop1
)
2868 && HWI_COMPUTABLE_MODE_P (mode
)
2869 && ~UINTVAL (trueop1
)
2870 && (UINTVAL (trueop1
) & (UINTVAL (trueop1
) + 1)) == 0
2871 && (GET_CODE (op0
) == PLUS
|| GET_CODE (op0
) == MINUS
))
2876 pmop
[0] = XEXP (op0
, 0);
2877 pmop
[1] = XEXP (op0
, 1);
2879 if (CONST_INT_P (pmop
[1])
2880 && (UINTVAL (pmop
[1]) & UINTVAL (trueop1
)) == 0)
2881 return simplify_gen_binary (AND
, mode
, pmop
[0], op1
);
2883 for (which
= 0; which
< 2; which
++)
2886 switch (GET_CODE (tem
))
2889 if (CONST_INT_P (XEXP (tem
, 1))
2890 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
))
2891 == UINTVAL (trueop1
))
2892 pmop
[which
] = XEXP (tem
, 0);
2896 if (CONST_INT_P (XEXP (tem
, 1))
2897 && (UINTVAL (XEXP (tem
, 1)) & UINTVAL (trueop1
)) == 0)
2898 pmop
[which
] = XEXP (tem
, 0);
2905 if (pmop
[0] != XEXP (op0
, 0) || pmop
[1] != XEXP (op0
, 1))
2907 tem
= simplify_gen_binary (GET_CODE (op0
), mode
,
2909 return simplify_gen_binary (code
, mode
, tem
, op1
);
2913 /* (and X (ior (not X) Y) -> (and X Y) */
2914 if (GET_CODE (op1
) == IOR
2915 && GET_CODE (XEXP (op1
, 0)) == NOT
2916 && op0
== XEXP (XEXP (op1
, 0), 0))
2917 return simplify_gen_binary (AND
, mode
, op0
, XEXP (op1
, 1));
2919 /* (and (ior (not X) Y) X) -> (and X Y) */
2920 if (GET_CODE (op0
) == IOR
2921 && GET_CODE (XEXP (op0
, 0)) == NOT
2922 && op1
== XEXP (XEXP (op0
, 0), 0))
2923 return simplify_gen_binary (AND
, mode
, op1
, XEXP (op0
, 1));
2925 tem
= simplify_byte_swapping_operation (code
, mode
, op0
, op1
);
2929 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
2935 /* 0/x is 0 (or x&0 if x has side-effects). */
2936 if (trueop0
== CONST0_RTX (mode
))
2938 if (side_effects_p (op1
))
2939 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
2943 if (trueop1
== CONST1_RTX (mode
))
2945 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
2949 /* Convert divide by power of two into shift. */
2950 if (CONST_INT_P (trueop1
)
2951 && (val
= exact_log2 (UINTVAL (trueop1
))) > 0)
2952 return simplify_gen_binary (LSHIFTRT
, mode
, op0
, GEN_INT (val
));
2956 /* Handle floating point and integers separately. */
2957 if (SCALAR_FLOAT_MODE_P (mode
))
2959 /* Maybe change 0.0 / x to 0.0. This transformation isn't
2960 safe for modes with NaNs, since 0.0 / 0.0 will then be
2961 NaN rather than 0.0. Nor is it safe for modes with signed
2962 zeros, since dividing 0 by a negative number gives -0.0 */
2963 if (trueop0
== CONST0_RTX (mode
)
2964 && !HONOR_NANS (mode
)
2965 && !HONOR_SIGNED_ZEROS (mode
)
2966 && ! side_effects_p (op1
))
2969 if (trueop1
== CONST1_RTX (mode
)
2970 && !HONOR_SNANS (mode
))
2973 if (CONST_DOUBLE_AS_FLOAT_P (trueop1
)
2974 && trueop1
!= CONST0_RTX (mode
))
2977 REAL_VALUE_FROM_CONST_DOUBLE (d
, trueop1
);
2980 if (REAL_VALUES_EQUAL (d
, dconstm1
)
2981 && !HONOR_SNANS (mode
))
2982 return simplify_gen_unary (NEG
, mode
, op0
, mode
);
2984 /* Change FP division by a constant into multiplication.
2985 Only do this with -freciprocal-math. */
2986 if (flag_reciprocal_math
2987 && !REAL_VALUES_EQUAL (d
, dconst0
))
2989 REAL_ARITHMETIC (d
, RDIV_EXPR
, dconst1
, d
);
2990 tem
= CONST_DOUBLE_FROM_REAL_VALUE (d
, mode
);
2991 return simplify_gen_binary (MULT
, mode
, op0
, tem
);
2995 else if (SCALAR_INT_MODE_P (mode
))
2997 /* 0/x is 0 (or x&0 if x has side-effects). */
2998 if (trueop0
== CONST0_RTX (mode
)
2999 && !cfun
->can_throw_non_call_exceptions
)
3001 if (side_effects_p (op1
))
3002 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3006 if (trueop1
== CONST1_RTX (mode
))
3008 tem
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3013 if (trueop1
== constm1_rtx
)
3015 rtx x
= rtl_hooks
.gen_lowpart_no_emit (mode
, op0
);
3017 return simplify_gen_unary (NEG
, mode
, x
, mode
);
3023 /* 0%x is 0 (or x&0 if x has side-effects). */
3024 if (trueop0
== CONST0_RTX (mode
))
3026 if (side_effects_p (op1
))
3027 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3030 /* x%1 is 0 (of x&0 if x has side-effects). */
3031 if (trueop1
== CONST1_RTX (mode
))
3033 if (side_effects_p (op0
))
3034 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
3035 return CONST0_RTX (mode
);
3037 /* Implement modulus by power of two as AND. */
3038 if (CONST_INT_P (trueop1
)
3039 && exact_log2 (UINTVAL (trueop1
)) > 0)
3040 return simplify_gen_binary (AND
, mode
, op0
,
3041 gen_int_mode (INTVAL (op1
) - 1, mode
));
3045 /* 0%x is 0 (or x&0 if x has side-effects). */
3046 if (trueop0
== CONST0_RTX (mode
))
3048 if (side_effects_p (op1
))
3049 return simplify_gen_binary (AND
, mode
, op1
, trueop0
);
3052 /* x%1 and x%-1 is 0 (or x&0 if x has side-effects). */
3053 if (trueop1
== CONST1_RTX (mode
) || trueop1
== constm1_rtx
)
3055 if (side_effects_p (op0
))
3056 return simplify_gen_binary (AND
, mode
, op0
, CONST0_RTX (mode
));
3057 return CONST0_RTX (mode
);
3063 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
3064 prefer left rotation, if op1 is from bitsize / 2 + 1 to
3065 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
3067 if (CONST_INT_P (trueop1
)
3068 && IN_RANGE (INTVAL (trueop1
),
3069 GET_MODE_BITSIZE (mode
) / 2 + (code
== ROTATE
),
3070 GET_MODE_BITSIZE (mode
) - 1))
3071 return simplify_gen_binary (code
== ROTATE
? ROTATERT
: ROTATE
,
3072 mode
, op0
, GEN_INT (GET_MODE_BITSIZE (mode
)
3073 - INTVAL (trueop1
)));
3076 if (trueop1
== CONST0_RTX (mode
))
3078 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3080 /* Rotating ~0 always results in ~0. */
3081 if (CONST_INT_P (trueop0
) && width
<= HOST_BITS_PER_WIDE_INT
3082 && UINTVAL (trueop0
) == GET_MODE_MASK (mode
)
3083 && ! side_effects_p (op1
))
3086 if (SHIFT_COUNT_TRUNCATED
&& CONST_INT_P (op1
))
3088 val
= INTVAL (op1
) & (GET_MODE_BITSIZE (mode
) - 1);
3089 if (val
!= INTVAL (op1
))
3090 return simplify_gen_binary (code
, mode
, op0
, GEN_INT (val
));
3097 if (trueop1
== CONST0_RTX (mode
))
3099 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3101 goto canonicalize_shift
;
3104 if (trueop1
== CONST0_RTX (mode
))
3106 if (trueop0
== CONST0_RTX (mode
) && ! side_effects_p (op1
))
3108 /* Optimize (lshiftrt (clz X) C) as (eq X 0). */
3109 if (GET_CODE (op0
) == CLZ
3110 && CONST_INT_P (trueop1
)
3111 && STORE_FLAG_VALUE
== 1
3112 && INTVAL (trueop1
) < (HOST_WIDE_INT
)width
)
3114 enum machine_mode imode
= GET_MODE (XEXP (op0
, 0));
3115 unsigned HOST_WIDE_INT zero_val
= 0;
3117 if (CLZ_DEFINED_VALUE_AT_ZERO (imode
, zero_val
)
3118 && zero_val
== GET_MODE_PRECISION (imode
)
3119 && INTVAL (trueop1
) == exact_log2 (zero_val
))
3120 return simplify_gen_relational (EQ
, mode
, imode
,
3121 XEXP (op0
, 0), const0_rtx
);
3123 goto canonicalize_shift
;
3126 if (width
<= HOST_BITS_PER_WIDE_INT
3127 && mode_signbit_p (mode
, trueop1
)
3128 && ! side_effects_p (op0
))
3130 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3132 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3138 if (width
<= HOST_BITS_PER_WIDE_INT
3139 && CONST_INT_P (trueop1
)
3140 && (UINTVAL (trueop1
) == GET_MODE_MASK (mode
) >> 1)
3141 && ! side_effects_p (op0
))
3143 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3145 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3151 if (trueop1
== CONST0_RTX (mode
) && ! side_effects_p (op0
))
3153 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3155 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3161 if (trueop1
== constm1_rtx
&& ! side_effects_p (op0
))
3163 if (rtx_equal_p (trueop0
, trueop1
) && ! side_effects_p (op0
))
3165 tem
= simplify_associative_operation (code
, mode
, op0
, op1
);
3178 /* ??? There are simplifications that can be done. */
3182 if (!VECTOR_MODE_P (mode
))
3184 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
3185 gcc_assert (mode
== GET_MODE_INNER (GET_MODE (trueop0
)));
3186 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
3187 gcc_assert (XVECLEN (trueop1
, 0) == 1);
3188 gcc_assert (CONST_INT_P (XVECEXP (trueop1
, 0, 0)));
3190 if (GET_CODE (trueop0
) == CONST_VECTOR
)
3191 return CONST_VECTOR_ELT (trueop0
, INTVAL (XVECEXP
3194 /* Extract a scalar element from a nested VEC_SELECT expression
3195 (with optional nested VEC_CONCAT expression). Some targets
3196 (i386) extract scalar element from a vector using chain of
3197 nested VEC_SELECT expressions. When input operand is a memory
3198 operand, this operation can be simplified to a simple scalar
3199 load from an offseted memory address. */
3200 if (GET_CODE (trueop0
) == VEC_SELECT
)
3202 rtx op0
= XEXP (trueop0
, 0);
3203 rtx op1
= XEXP (trueop0
, 1);
3205 enum machine_mode opmode
= GET_MODE (op0
);
3206 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (opmode
));
3207 int n_elts
= GET_MODE_SIZE (opmode
) / elt_size
;
3209 int i
= INTVAL (XVECEXP (trueop1
, 0, 0));
3215 gcc_assert (GET_CODE (op1
) == PARALLEL
);
3216 gcc_assert (i
< n_elts
);
3218 /* Select element, pointed by nested selector. */
3219 elem
= INTVAL (XVECEXP (op1
, 0, i
));
3221 /* Handle the case when nested VEC_SELECT wraps VEC_CONCAT. */
3222 if (GET_CODE (op0
) == VEC_CONCAT
)
3224 rtx op00
= XEXP (op0
, 0);
3225 rtx op01
= XEXP (op0
, 1);
3227 enum machine_mode mode00
, mode01
;
3228 int n_elts00
, n_elts01
;
3230 mode00
= GET_MODE (op00
);
3231 mode01
= GET_MODE (op01
);
3233 /* Find out number of elements of each operand. */
3234 if (VECTOR_MODE_P (mode00
))
3236 elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode00
));
3237 n_elts00
= GET_MODE_SIZE (mode00
) / elt_size
;
3242 if (VECTOR_MODE_P (mode01
))
3244 elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode01
));
3245 n_elts01
= GET_MODE_SIZE (mode01
) / elt_size
;
3250 gcc_assert (n_elts
== n_elts00
+ n_elts01
);
3252 /* Select correct operand of VEC_CONCAT
3253 and adjust selector. */
3254 if (elem
< n_elts01
)
3265 vec
= rtvec_alloc (1);
3266 RTVEC_ELT (vec
, 0) = GEN_INT (elem
);
3268 tmp
= gen_rtx_fmt_ee (code
, mode
,
3269 tmp_op
, gen_rtx_PARALLEL (VOIDmode
, vec
));
3272 if (GET_CODE (trueop0
) == VEC_DUPLICATE
3273 && GET_MODE (XEXP (trueop0
, 0)) == mode
)
3274 return XEXP (trueop0
, 0);
3278 gcc_assert (VECTOR_MODE_P (GET_MODE (trueop0
)));
3279 gcc_assert (GET_MODE_INNER (mode
)
3280 == GET_MODE_INNER (GET_MODE (trueop0
)));
3281 gcc_assert (GET_CODE (trueop1
) == PARALLEL
);
3283 if (GET_CODE (trueop0
) == CONST_VECTOR
)
3285 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
3286 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
3287 rtvec v
= rtvec_alloc (n_elts
);
3290 gcc_assert (XVECLEN (trueop1
, 0) == (int) n_elts
);
3291 for (i
= 0; i
< n_elts
; i
++)
3293 rtx x
= XVECEXP (trueop1
, 0, i
);
3295 gcc_assert (CONST_INT_P (x
));
3296 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
,
3300 return gen_rtx_CONST_VECTOR (mode
, v
);
3303 /* Recognize the identity. */
3304 if (GET_MODE (trueop0
) == mode
)
3306 bool maybe_ident
= true;
3307 for (int i
= 0; i
< XVECLEN (trueop1
, 0); i
++)
3309 rtx j
= XVECEXP (trueop1
, 0, i
);
3310 if (!CONST_INT_P (j
) || INTVAL (j
) != i
)
3312 maybe_ident
= false;
3320 /* If we build {a,b} then permute it, build the result directly. */
3321 if (XVECLEN (trueop1
, 0) == 2
3322 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
3323 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
3324 && GET_CODE (trueop0
) == VEC_CONCAT
3325 && GET_CODE (XEXP (trueop0
, 0)) == VEC_CONCAT
3326 && GET_MODE (XEXP (trueop0
, 0)) == mode
3327 && GET_CODE (XEXP (trueop0
, 1)) == VEC_CONCAT
3328 && GET_MODE (XEXP (trueop0
, 1)) == mode
)
3330 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
3331 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
3334 gcc_assert (i0
< 4 && i1
< 4);
3335 subop0
= XEXP (XEXP (trueop0
, i0
/ 2), i0
% 2);
3336 subop1
= XEXP (XEXP (trueop0
, i1
/ 2), i1
% 2);
3338 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
3341 if (XVECLEN (trueop1
, 0) == 2
3342 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
3343 && CONST_INT_P (XVECEXP (trueop1
, 0, 1))
3344 && GET_CODE (trueop0
) == VEC_CONCAT
3345 && GET_MODE (trueop0
) == mode
)
3347 unsigned int i0
= INTVAL (XVECEXP (trueop1
, 0, 0));
3348 unsigned int i1
= INTVAL (XVECEXP (trueop1
, 0, 1));
3351 gcc_assert (i0
< 2 && i1
< 2);
3352 subop0
= XEXP (trueop0
, i0
);
3353 subop1
= XEXP (trueop0
, i1
);
3355 return simplify_gen_binary (VEC_CONCAT
, mode
, subop0
, subop1
);
3359 if (XVECLEN (trueop1
, 0) == 1
3360 && CONST_INT_P (XVECEXP (trueop1
, 0, 0))
3361 && GET_CODE (trueop0
) == VEC_CONCAT
)
3364 int offset
= INTVAL (XVECEXP (trueop1
, 0, 0)) * GET_MODE_SIZE (mode
);
3366 /* Try to find the element in the VEC_CONCAT. */
3367 while (GET_MODE (vec
) != mode
3368 && GET_CODE (vec
) == VEC_CONCAT
)
3370 HOST_WIDE_INT vec_size
= GET_MODE_SIZE (GET_MODE (XEXP (vec
, 0)));
3371 if (offset
< vec_size
)
3372 vec
= XEXP (vec
, 0);
3376 vec
= XEXP (vec
, 1);
3378 vec
= avoid_constant_pool_reference (vec
);
3381 if (GET_MODE (vec
) == mode
)
3385 /* If we select elements in a vec_merge that all come from the same
3386 operand, select from that operand directly. */
3387 if (GET_CODE (op0
) == VEC_MERGE
)
3389 rtx trueop02
= avoid_constant_pool_reference (XEXP (op0
, 2));
3390 if (CONST_INT_P (trueop02
))
3392 unsigned HOST_WIDE_INT sel
= UINTVAL (trueop02
);
3393 bool all_operand0
= true;
3394 bool all_operand1
= true;
3395 for (int i
= 0; i
< XVECLEN (trueop1
, 0); i
++)
3397 rtx j
= XVECEXP (trueop1
, 0, i
);
3398 if (sel
& (1 << UINTVAL (j
)))
3399 all_operand1
= false;
3401 all_operand0
= false;
3403 if (all_operand0
&& !side_effects_p (XEXP (op0
, 1)))
3404 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (op0
, 0), op1
);
3405 if (all_operand1
&& !side_effects_p (XEXP (op0
, 0)))
3406 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (op0
, 1), op1
);
3413 enum machine_mode op0_mode
= (GET_MODE (trueop0
) != VOIDmode
3414 ? GET_MODE (trueop0
)
3415 : GET_MODE_INNER (mode
));
3416 enum machine_mode op1_mode
= (GET_MODE (trueop1
) != VOIDmode
3417 ? GET_MODE (trueop1
)
3418 : GET_MODE_INNER (mode
));
3420 gcc_assert (VECTOR_MODE_P (mode
));
3421 gcc_assert (GET_MODE_SIZE (op0_mode
) + GET_MODE_SIZE (op1_mode
)
3422 == GET_MODE_SIZE (mode
));
3424 if (VECTOR_MODE_P (op0_mode
))
3425 gcc_assert (GET_MODE_INNER (mode
)
3426 == GET_MODE_INNER (op0_mode
));
3428 gcc_assert (GET_MODE_INNER (mode
) == op0_mode
);
3430 if (VECTOR_MODE_P (op1_mode
))
3431 gcc_assert (GET_MODE_INNER (mode
)
3432 == GET_MODE_INNER (op1_mode
));
3434 gcc_assert (GET_MODE_INNER (mode
) == op1_mode
);
3436 if ((GET_CODE (trueop0
) == CONST_VECTOR
3437 || CONST_SCALAR_INT_P (trueop0
)
3438 || CONST_DOUBLE_AS_FLOAT_P (trueop0
))
3439 && (GET_CODE (trueop1
) == CONST_VECTOR
3440 || CONST_SCALAR_INT_P (trueop1
)
3441 || CONST_DOUBLE_AS_FLOAT_P (trueop1
)))
3443 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
3444 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
3445 rtvec v
= rtvec_alloc (n_elts
);
3447 unsigned in_n_elts
= 1;
3449 if (VECTOR_MODE_P (op0_mode
))
3450 in_n_elts
= (GET_MODE_SIZE (op0_mode
) / elt_size
);
3451 for (i
= 0; i
< n_elts
; i
++)
3455 if (!VECTOR_MODE_P (op0_mode
))
3456 RTVEC_ELT (v
, i
) = trueop0
;
3458 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop0
, i
);
3462 if (!VECTOR_MODE_P (op1_mode
))
3463 RTVEC_ELT (v
, i
) = trueop1
;
3465 RTVEC_ELT (v
, i
) = CONST_VECTOR_ELT (trueop1
,
3470 return gen_rtx_CONST_VECTOR (mode
, v
);
3473 /* Try to merge two VEC_SELECTs from the same vector into a single one.
3474 Restrict the transformation to avoid generating a VEC_SELECT with a
3475 mode unrelated to its operand. */
3476 if (GET_CODE (trueop0
) == VEC_SELECT
3477 && GET_CODE (trueop1
) == VEC_SELECT
3478 && rtx_equal_p (XEXP (trueop0
, 0), XEXP (trueop1
, 0))
3479 && GET_MODE (XEXP (trueop0
, 0)) == mode
)
3481 rtx par0
= XEXP (trueop0
, 1);
3482 rtx par1
= XEXP (trueop1
, 1);
3483 int len0
= XVECLEN (par0
, 0);
3484 int len1
= XVECLEN (par1
, 0);
3485 rtvec vec
= rtvec_alloc (len0
+ len1
);
3486 for (int i
= 0; i
< len0
; i
++)
3487 RTVEC_ELT (vec
, i
) = XVECEXP (par0
, 0, i
);
3488 for (int i
= 0; i
< len1
; i
++)
3489 RTVEC_ELT (vec
, len0
+ i
) = XVECEXP (par1
, 0, i
);
3490 return simplify_gen_binary (VEC_SELECT
, mode
, XEXP (trueop0
, 0),
3491 gen_rtx_PARALLEL (VOIDmode
, vec
));
3504 simplify_const_binary_operation (enum rtx_code code
, enum machine_mode mode
,
3507 unsigned int width
= GET_MODE_PRECISION (mode
);
3509 if (VECTOR_MODE_P (mode
)
3510 && code
!= VEC_CONCAT
3511 && GET_CODE (op0
) == CONST_VECTOR
3512 && GET_CODE (op1
) == CONST_VECTOR
)
3514 unsigned n_elts
= GET_MODE_NUNITS (mode
);
3515 enum machine_mode op0mode
= GET_MODE (op0
);
3516 unsigned op0_n_elts
= GET_MODE_NUNITS (op0mode
);
3517 enum machine_mode op1mode
= GET_MODE (op1
);
3518 unsigned op1_n_elts
= GET_MODE_NUNITS (op1mode
);
3519 rtvec v
= rtvec_alloc (n_elts
);
3522 gcc_assert (op0_n_elts
== n_elts
);
3523 gcc_assert (op1_n_elts
== n_elts
);
3524 for (i
= 0; i
< n_elts
; i
++)
3526 rtx x
= simplify_binary_operation (code
, GET_MODE_INNER (mode
),
3527 CONST_VECTOR_ELT (op0
, i
),
3528 CONST_VECTOR_ELT (op1
, i
));
3531 RTVEC_ELT (v
, i
) = x
;
3534 return gen_rtx_CONST_VECTOR (mode
, v
);
3537 if (VECTOR_MODE_P (mode
)
3538 && code
== VEC_CONCAT
3539 && (CONST_SCALAR_INT_P (op0
)
3540 || GET_CODE (op0
) == CONST_FIXED
3541 || CONST_DOUBLE_AS_FLOAT_P (op0
))
3542 && (CONST_SCALAR_INT_P (op1
)
3543 || CONST_DOUBLE_AS_FLOAT_P (op1
)
3544 || GET_CODE (op1
) == CONST_FIXED
))
3546 unsigned n_elts
= GET_MODE_NUNITS (mode
);
3547 rtvec v
= rtvec_alloc (n_elts
);
3549 gcc_assert (n_elts
>= 2);
3552 gcc_assert (GET_CODE (op0
) != CONST_VECTOR
);
3553 gcc_assert (GET_CODE (op1
) != CONST_VECTOR
);
3555 RTVEC_ELT (v
, 0) = op0
;
3556 RTVEC_ELT (v
, 1) = op1
;
3560 unsigned op0_n_elts
= GET_MODE_NUNITS (GET_MODE (op0
));
3561 unsigned op1_n_elts
= GET_MODE_NUNITS (GET_MODE (op1
));
3564 gcc_assert (GET_CODE (op0
) == CONST_VECTOR
);
3565 gcc_assert (GET_CODE (op1
) == CONST_VECTOR
);
3566 gcc_assert (op0_n_elts
+ op1_n_elts
== n_elts
);
3568 for (i
= 0; i
< op0_n_elts
; ++i
)
3569 RTVEC_ELT (v
, i
) = XVECEXP (op0
, 0, i
);
3570 for (i
= 0; i
< op1_n_elts
; ++i
)
3571 RTVEC_ELT (v
, op0_n_elts
+i
) = XVECEXP (op1
, 0, i
);
3574 return gen_rtx_CONST_VECTOR (mode
, v
);
3577 if (SCALAR_FLOAT_MODE_P (mode
)
3578 && CONST_DOUBLE_AS_FLOAT_P (op0
)
3579 && CONST_DOUBLE_AS_FLOAT_P (op1
)
3580 && mode
== GET_MODE (op0
) && mode
== GET_MODE (op1
))
3591 real_to_target (tmp0
, CONST_DOUBLE_REAL_VALUE (op0
),
3593 real_to_target (tmp1
, CONST_DOUBLE_REAL_VALUE (op1
),
3595 for (i
= 0; i
< 4; i
++)
3612 real_from_target (&r
, tmp0
, mode
);
3613 return CONST_DOUBLE_FROM_REAL_VALUE (r
, mode
);
3617 REAL_VALUE_TYPE f0
, f1
, value
, result
;
3620 REAL_VALUE_FROM_CONST_DOUBLE (f0
, op0
);
3621 REAL_VALUE_FROM_CONST_DOUBLE (f1
, op1
);
3622 real_convert (&f0
, mode
, &f0
);
3623 real_convert (&f1
, mode
, &f1
);
3625 if (HONOR_SNANS (mode
)
3626 && (REAL_VALUE_ISNAN (f0
) || REAL_VALUE_ISNAN (f1
)))
3630 && REAL_VALUES_EQUAL (f1
, dconst0
)
3631 && (flag_trapping_math
|| ! MODE_HAS_INFINITIES (mode
)))
3634 if (MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
3635 && flag_trapping_math
3636 && REAL_VALUE_ISINF (f0
) && REAL_VALUE_ISINF (f1
))
3638 int s0
= REAL_VALUE_NEGATIVE (f0
);
3639 int s1
= REAL_VALUE_NEGATIVE (f1
);
3644 /* Inf + -Inf = NaN plus exception. */
3649 /* Inf - Inf = NaN plus exception. */
3654 /* Inf / Inf = NaN plus exception. */
3661 if (code
== MULT
&& MODE_HAS_INFINITIES (mode
) && HONOR_NANS (mode
)
3662 && flag_trapping_math
3663 && ((REAL_VALUE_ISINF (f0
) && REAL_VALUES_EQUAL (f1
, dconst0
))
3664 || (REAL_VALUE_ISINF (f1
)
3665 && REAL_VALUES_EQUAL (f0
, dconst0
))))
3666 /* Inf * 0 = NaN plus exception. */
3669 inexact
= real_arithmetic (&value
, rtx_to_tree_code (code
),
3671 real_convert (&result
, mode
, &value
);
3673 /* Don't constant fold this floating point operation if
3674 the result has overflowed and flag_trapping_math. */
3676 if (flag_trapping_math
3677 && MODE_HAS_INFINITIES (mode
)
3678 && REAL_VALUE_ISINF (result
)
3679 && !REAL_VALUE_ISINF (f0
)
3680 && !REAL_VALUE_ISINF (f1
))
3681 /* Overflow plus exception. */
3684 /* Don't constant fold this floating point operation if the
3685 result may dependent upon the run-time rounding mode and
3686 flag_rounding_math is set, or if GCC's software emulation
3687 is unable to accurately represent the result. */
3689 if ((flag_rounding_math
3690 || (MODE_COMPOSITE_P (mode
) && !flag_unsafe_math_optimizations
))
3691 && (inexact
|| !real_identical (&result
, &value
)))
3694 return CONST_DOUBLE_FROM_REAL_VALUE (result
, mode
);
3698 /* We can fold some multi-word operations. */
3699 if (GET_MODE_CLASS (mode
) == MODE_INT
3700 && CONST_SCALAR_INT_P (op0
)
3701 && CONST_SCALAR_INT_P (op1
))
3705 unsigned int bitsize
= GET_MODE_BITSIZE (mode
);
3706 rtx_mode_t pop0
= std::make_pair (op0
, mode
);
3707 rtx_mode_t pop1
= std::make_pair (op1
, mode
);
3709 #if TARGET_SUPPORTS_WIDE_INT == 0
3710 /* This assert keeps the simplification from producing a result
3711 that cannot be represented in a CONST_DOUBLE but a lot of
3712 upstream callers expect that this function never fails to
3713 simplify something and so you if you added this to the test
3714 above the code would die later anyway. If this assert
3715 happens, you just need to make the port support wide int. */
3716 gcc_assert (width
<= HOST_BITS_PER_DOUBLE_INT
);
3721 result
= wi::sub (pop0
, pop1
);
3725 result
= wi::add (pop0
, pop1
);
3729 result
= wi::mul (pop0
, pop1
);
3733 result
= wi::div_trunc (pop0
, pop1
, SIGNED
, &overflow
);
3739 result
= wi::mod_trunc (pop0
, pop1
, SIGNED
, &overflow
);
3745 result
= wi::div_trunc (pop0
, pop1
, UNSIGNED
, &overflow
);
3751 result
= wi::mod_trunc (pop0
, pop1
, UNSIGNED
, &overflow
);
3757 result
= wi::bit_and (pop0
, pop1
);
3761 result
= wi::bit_or (pop0
, pop1
);
3765 result
= wi::bit_xor (pop0
, pop1
);
3769 result
= wi::smin (pop0
, pop1
);
3773 result
= wi::smax (pop0
, pop1
);
3777 result
= wi::umin (pop0
, pop1
);
3781 result
= wi::umax (pop0
, pop1
);
3790 wide_int wop1
= pop1
;
3791 if (wi::neg_p (wop1
))
3794 if (SHIFT_COUNT_TRUNCATED
)
3795 wop1
= wi::umod_trunc (wop1
, width
);
3800 result
= wi::lrshift (pop0
, wop1
, bitsize
);
3804 result
= wi::arshift (pop0
, wop1
, bitsize
);
3808 result
= wi::lshift (pop0
, wop1
, bitsize
);
3812 result
= wi::lrotate (pop0
, wop1
);
3816 result
= wi::rrotate (pop0
, wop1
);
3827 return immed_wide_int_const (result
, mode
);
3835 /* Simplify a PLUS or MINUS, at least one of whose operands may be another
3838 Rather than test for specific case, we do this by a brute-force method
3839 and do all possible simplifications until no more changes occur. Then
3840 we rebuild the operation. */
3842 struct simplify_plus_minus_op_data
3849 simplify_plus_minus_op_data_cmp (rtx x
, rtx y
)
3853 result
= (commutative_operand_precedence (y
)
3854 - commutative_operand_precedence (x
));
3858 /* Group together equal REGs to do more simplification. */
3859 if (REG_P (x
) && REG_P (y
))
3860 return REGNO (x
) > REGNO (y
);
3866 simplify_plus_minus (enum rtx_code code
, enum machine_mode mode
, rtx op0
,
3869 struct simplify_plus_minus_op_data ops
[8];
3871 int n_ops
= 2, input_ops
= 2;
3872 int changed
, n_constants
= 0, canonicalized
= 0;
3875 memset (ops
, 0, sizeof ops
);
3877 /* Set up the two operands and then expand them until nothing has been
3878 changed. If we run out of room in our array, give up; this should
3879 almost never happen. */
3884 ops
[1].neg
= (code
== MINUS
);
3890 for (i
= 0; i
< n_ops
; i
++)
3892 rtx this_op
= ops
[i
].op
;
3893 int this_neg
= ops
[i
].neg
;
3894 enum rtx_code this_code
= GET_CODE (this_op
);
3903 ops
[n_ops
].op
= XEXP (this_op
, 1);
3904 ops
[n_ops
].neg
= (this_code
== MINUS
) ^ this_neg
;
3907 ops
[i
].op
= XEXP (this_op
, 0);
3910 canonicalized
|= this_neg
;
3914 ops
[i
].op
= XEXP (this_op
, 0);
3915 ops
[i
].neg
= ! this_neg
;
3922 && GET_CODE (XEXP (this_op
, 0)) == PLUS
3923 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 0))
3924 && CONSTANT_P (XEXP (XEXP (this_op
, 0), 1)))
3926 ops
[i
].op
= XEXP (XEXP (this_op
, 0), 0);
3927 ops
[n_ops
].op
= XEXP (XEXP (this_op
, 0), 1);
3928 ops
[n_ops
].neg
= this_neg
;
3936 /* ~a -> (-a - 1) */
3939 ops
[n_ops
].op
= CONSTM1_RTX (mode
);
3940 ops
[n_ops
++].neg
= this_neg
;
3941 ops
[i
].op
= XEXP (this_op
, 0);
3942 ops
[i
].neg
= !this_neg
;
3952 ops
[i
].op
= neg_const_int (mode
, this_op
);
3966 if (n_constants
> 1)
3969 gcc_assert (n_ops
>= 2);
3971 /* If we only have two operands, we can avoid the loops. */
3974 enum rtx_code code
= ops
[0].neg
|| ops
[1].neg
? MINUS
: PLUS
;
3977 /* Get the two operands. Be careful with the order, especially for
3978 the cases where code == MINUS. */
3979 if (ops
[0].neg
&& ops
[1].neg
)
3981 lhs
= gen_rtx_NEG (mode
, ops
[0].op
);
3984 else if (ops
[0].neg
)
3995 return simplify_const_binary_operation (code
, mode
, lhs
, rhs
);
3998 /* Now simplify each pair of operands until nothing changes. */
4001 /* Insertion sort is good enough for an eight-element array. */
4002 for (i
= 1; i
< n_ops
; i
++)
4004 struct simplify_plus_minus_op_data save
;
4006 if (!simplify_plus_minus_op_data_cmp (ops
[j
].op
, ops
[i
].op
))
4012 ops
[j
+ 1] = ops
[j
];
4013 while (j
-- && simplify_plus_minus_op_data_cmp (ops
[j
].op
, save
.op
));
4018 for (i
= n_ops
- 1; i
> 0; i
--)
4019 for (j
= i
- 1; j
>= 0; j
--)
4021 rtx lhs
= ops
[j
].op
, rhs
= ops
[i
].op
;
4022 int lneg
= ops
[j
].neg
, rneg
= ops
[i
].neg
;
4024 if (lhs
!= 0 && rhs
!= 0)
4026 enum rtx_code ncode
= PLUS
;
4032 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
4034 else if (swap_commutative_operands_p (lhs
, rhs
))
4035 tem
= lhs
, lhs
= rhs
, rhs
= tem
;
4037 if ((GET_CODE (lhs
) == CONST
|| CONST_INT_P (lhs
))
4038 && (GET_CODE (rhs
) == CONST
|| CONST_INT_P (rhs
)))
4040 rtx tem_lhs
, tem_rhs
;
4042 tem_lhs
= GET_CODE (lhs
) == CONST
? XEXP (lhs
, 0) : lhs
;
4043 tem_rhs
= GET_CODE (rhs
) == CONST
? XEXP (rhs
, 0) : rhs
;
4044 tem
= simplify_binary_operation (ncode
, mode
, tem_lhs
, tem_rhs
);
4046 if (tem
&& !CONSTANT_P (tem
))
4047 tem
= gen_rtx_CONST (GET_MODE (tem
), tem
);
4050 tem
= simplify_binary_operation (ncode
, mode
, lhs
, rhs
);
4052 /* Reject "simplifications" that just wrap the two
4053 arguments in a CONST. Failure to do so can result
4054 in infinite recursion with simplify_binary_operation
4055 when it calls us to simplify CONST operations. */
4057 && ! (GET_CODE (tem
) == CONST
4058 && GET_CODE (XEXP (tem
, 0)) == ncode
4059 && XEXP (XEXP (tem
, 0), 0) == lhs
4060 && XEXP (XEXP (tem
, 0), 1) == rhs
))
4063 if (GET_CODE (tem
) == NEG
)
4064 tem
= XEXP (tem
, 0), lneg
= !lneg
;
4065 if (CONST_INT_P (tem
) && lneg
)
4066 tem
= neg_const_int (mode
, tem
), lneg
= 0;
4070 ops
[j
].op
= NULL_RTX
;
4077 /* If nothing changed, fail. */
4081 /* Pack all the operands to the lower-numbered entries. */
4082 for (i
= 0, j
= 0; j
< n_ops
; j
++)
4092 /* Create (minus -C X) instead of (neg (const (plus X C))). */
4094 && CONST_INT_P (ops
[1].op
)
4095 && CONSTANT_P (ops
[0].op
)
4097 return gen_rtx_fmt_ee (MINUS
, mode
, ops
[1].op
, ops
[0].op
);
4099 /* We suppressed creation of trivial CONST expressions in the
4100 combination loop to avoid recursion. Create one manually now.
4101 The combination loop should have ensured that there is exactly
4102 one CONST_INT, and the sort will have ensured that it is last
4103 in the array and that any other constant will be next-to-last. */
4106 && CONST_INT_P (ops
[n_ops
- 1].op
)
4107 && CONSTANT_P (ops
[n_ops
- 2].op
))
4109 rtx value
= ops
[n_ops
- 1].op
;
4110 if (ops
[n_ops
- 1].neg
^ ops
[n_ops
- 2].neg
)
4111 value
= neg_const_int (mode
, value
);
4112 ops
[n_ops
- 2].op
= plus_constant (mode
, ops
[n_ops
- 2].op
,
4117 /* Put a non-negated operand first, if possible. */
4119 for (i
= 0; i
< n_ops
&& ops
[i
].neg
; i
++)
4122 ops
[0].op
= gen_rtx_NEG (mode
, ops
[0].op
);
4131 /* Now make the result by performing the requested operations. */
4133 for (i
= 1; i
< n_ops
; i
++)
4134 result
= gen_rtx_fmt_ee (ops
[i
].neg
? MINUS
: PLUS
,
4135 mode
, result
, ops
[i
].op
);
4140 /* Check whether an operand is suitable for calling simplify_plus_minus. */
4142 plus_minus_operand_p (const_rtx x
)
4144 return GET_CODE (x
) == PLUS
4145 || GET_CODE (x
) == MINUS
4146 || (GET_CODE (x
) == CONST
4147 && GET_CODE (XEXP (x
, 0)) == PLUS
4148 && CONSTANT_P (XEXP (XEXP (x
, 0), 0))
4149 && CONSTANT_P (XEXP (XEXP (x
, 0), 1)));
4152 /* Like simplify_binary_operation except used for relational operators.
4153 MODE is the mode of the result. If MODE is VOIDmode, both operands must
4154 not also be VOIDmode.
4156 CMP_MODE specifies in which mode the comparison is done in, so it is
4157 the mode of the operands. If CMP_MODE is VOIDmode, it is taken from
4158 the operands or, if both are VOIDmode, the operands are compared in
4159 "infinite precision". */
4161 simplify_relational_operation (enum rtx_code code
, enum machine_mode mode
,
4162 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
4164 rtx tem
, trueop0
, trueop1
;
4166 if (cmp_mode
== VOIDmode
)
4167 cmp_mode
= GET_MODE (op0
);
4168 if (cmp_mode
== VOIDmode
)
4169 cmp_mode
= GET_MODE (op1
);
4171 tem
= simplify_const_relational_operation (code
, cmp_mode
, op0
, op1
);
4174 if (SCALAR_FLOAT_MODE_P (mode
))
4176 if (tem
== const0_rtx
)
4177 return CONST0_RTX (mode
);
4178 #ifdef FLOAT_STORE_FLAG_VALUE
4180 REAL_VALUE_TYPE val
;
4181 val
= FLOAT_STORE_FLAG_VALUE (mode
);
4182 return CONST_DOUBLE_FROM_REAL_VALUE (val
, mode
);
4188 if (VECTOR_MODE_P (mode
))
4190 if (tem
== const0_rtx
)
4191 return CONST0_RTX (mode
);
4192 #ifdef VECTOR_STORE_FLAG_VALUE
4197 rtx val
= VECTOR_STORE_FLAG_VALUE (mode
);
4198 if (val
== NULL_RTX
)
4200 if (val
== const1_rtx
)
4201 return CONST1_RTX (mode
);
4203 units
= GET_MODE_NUNITS (mode
);
4204 v
= rtvec_alloc (units
);
4205 for (i
= 0; i
< units
; i
++)
4206 RTVEC_ELT (v
, i
) = val
;
4207 return gen_rtx_raw_CONST_VECTOR (mode
, v
);
4217 /* For the following tests, ensure const0_rtx is op1. */
4218 if (swap_commutative_operands_p (op0
, op1
)
4219 || (op0
== const0_rtx
&& op1
!= const0_rtx
))
4220 tem
= op0
, op0
= op1
, op1
= tem
, code
= swap_condition (code
);
4222 /* If op0 is a compare, extract the comparison arguments from it. */
4223 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
4224 return simplify_gen_relational (code
, mode
, VOIDmode
,
4225 XEXP (op0
, 0), XEXP (op0
, 1));
4227 if (GET_MODE_CLASS (cmp_mode
) == MODE_CC
4231 trueop0
= avoid_constant_pool_reference (op0
);
4232 trueop1
= avoid_constant_pool_reference (op1
);
4233 return simplify_relational_operation_1 (code
, mode
, cmp_mode
,
4237 /* This part of simplify_relational_operation is only used when CMP_MODE
4238 is not in class MODE_CC (i.e. it is a real comparison).
4240 MODE is the mode of the result, while CMP_MODE specifies in which
4241 mode the comparison is done in, so it is the mode of the operands. */
4244 simplify_relational_operation_1 (enum rtx_code code
, enum machine_mode mode
,
4245 enum machine_mode cmp_mode
, rtx op0
, rtx op1
)
4247 enum rtx_code op0code
= GET_CODE (op0
);
4249 if (op1
== const0_rtx
&& COMPARISON_P (op0
))
4251 /* If op0 is a comparison, extract the comparison arguments
4255 if (GET_MODE (op0
) == mode
)
4256 return simplify_rtx (op0
);
4258 return simplify_gen_relational (GET_CODE (op0
), mode
, VOIDmode
,
4259 XEXP (op0
, 0), XEXP (op0
, 1));
4261 else if (code
== EQ
)
4263 enum rtx_code new_code
= reversed_comparison_code (op0
, NULL_RTX
);
4264 if (new_code
!= UNKNOWN
)
4265 return simplify_gen_relational (new_code
, mode
, VOIDmode
,
4266 XEXP (op0
, 0), XEXP (op0
, 1));
4270 /* (LTU/GEU (PLUS a C) C), where C is constant, can be simplified to
4271 (GEU/LTU a -C). Likewise for (LTU/GEU (PLUS a C) a). */
4272 if ((code
== LTU
|| code
== GEU
)
4273 && GET_CODE (op0
) == PLUS
4274 && CONST_INT_P (XEXP (op0
, 1))
4275 && (rtx_equal_p (op1
, XEXP (op0
, 0))
4276 || rtx_equal_p (op1
, XEXP (op0
, 1)))
4277 /* (LTU/GEU (PLUS a 0) 0) is not the same as (GEU/LTU a 0). */
4278 && XEXP (op0
, 1) != const0_rtx
)
4281 = simplify_gen_unary (NEG
, cmp_mode
, XEXP (op0
, 1), cmp_mode
);
4282 return simplify_gen_relational ((code
== LTU
? GEU
: LTU
), mode
,
4283 cmp_mode
, XEXP (op0
, 0), new_cmp
);
4286 /* Canonicalize (LTU/GEU (PLUS a b) b) as (LTU/GEU (PLUS a b) a). */
4287 if ((code
== LTU
|| code
== GEU
)
4288 && GET_CODE (op0
) == PLUS
4289 && rtx_equal_p (op1
, XEXP (op0
, 1))
4290 /* Don't recurse "infinitely" for (LTU/GEU (PLUS b b) b). */
4291 && !rtx_equal_p (op1
, XEXP (op0
, 0)))
4292 return simplify_gen_relational (code
, mode
, cmp_mode
, op0
,
4293 copy_rtx (XEXP (op0
, 0)));
4295 if (op1
== const0_rtx
)
4297 /* Canonicalize (GTU x 0) as (NE x 0). */
4299 return simplify_gen_relational (NE
, mode
, cmp_mode
, op0
, op1
);
4300 /* Canonicalize (LEU x 0) as (EQ x 0). */
4302 return simplify_gen_relational (EQ
, mode
, cmp_mode
, op0
, op1
);
4304 else if (op1
== const1_rtx
)
4309 /* Canonicalize (GE x 1) as (GT x 0). */
4310 return simplify_gen_relational (GT
, mode
, cmp_mode
,
4313 /* Canonicalize (GEU x 1) as (NE x 0). */
4314 return simplify_gen_relational (NE
, mode
, cmp_mode
,
4317 /* Canonicalize (LT x 1) as (LE x 0). */
4318 return simplify_gen_relational (LE
, mode
, cmp_mode
,
4321 /* Canonicalize (LTU x 1) as (EQ x 0). */
4322 return simplify_gen_relational (EQ
, mode
, cmp_mode
,
4328 else if (op1
== constm1_rtx
)
4330 /* Canonicalize (LE x -1) as (LT x 0). */
4332 return simplify_gen_relational (LT
, mode
, cmp_mode
, op0
, const0_rtx
);
4333 /* Canonicalize (GT x -1) as (GE x 0). */
4335 return simplify_gen_relational (GE
, mode
, cmp_mode
, op0
, const0_rtx
);
4338 /* (eq/ne (plus x cst1) cst2) simplifies to (eq/ne x (cst2 - cst1)) */
4339 if ((code
== EQ
|| code
== NE
)
4340 && (op0code
== PLUS
|| op0code
== MINUS
)
4342 && CONSTANT_P (XEXP (op0
, 1))
4343 && (INTEGRAL_MODE_P (cmp_mode
) || flag_unsafe_math_optimizations
))
4345 rtx x
= XEXP (op0
, 0);
4346 rtx c
= XEXP (op0
, 1);
4347 enum rtx_code invcode
= op0code
== PLUS
? MINUS
: PLUS
;
4348 rtx tem
= simplify_gen_binary (invcode
, cmp_mode
, op1
, c
);
4350 /* Detect an infinite recursive condition, where we oscillate at this
4351 simplification case between:
4352 A + B == C <---> C - B == A,
4353 where A, B, and C are all constants with non-simplifiable expressions,
4354 usually SYMBOL_REFs. */
4355 if (GET_CODE (tem
) == invcode
4357 && rtx_equal_p (c
, XEXP (tem
, 1)))
4360 return simplify_gen_relational (code
, mode
, cmp_mode
, x
, tem
);
4363 /* (ne:SI (zero_extract:SI FOO (const_int 1) BAR) (const_int 0))) is
4364 the same as (zero_extract:SI FOO (const_int 1) BAR). */
4366 && op1
== const0_rtx
4367 && GET_MODE_CLASS (mode
) == MODE_INT
4368 && cmp_mode
!= VOIDmode
4369 /* ??? Work-around BImode bugs in the ia64 backend. */
4371 && cmp_mode
!= BImode
4372 && nonzero_bits (op0
, cmp_mode
) == 1
4373 && STORE_FLAG_VALUE
== 1)
4374 return GET_MODE_SIZE (mode
) > GET_MODE_SIZE (cmp_mode
)
4375 ? simplify_gen_unary (ZERO_EXTEND
, mode
, op0
, cmp_mode
)
4376 : lowpart_subreg (mode
, op0
, cmp_mode
);
4378 /* (eq/ne (xor x y) 0) simplifies to (eq/ne x y). */
4379 if ((code
== EQ
|| code
== NE
)
4380 && op1
== const0_rtx
4382 return simplify_gen_relational (code
, mode
, cmp_mode
,
4383 XEXP (op0
, 0), XEXP (op0
, 1));
4385 /* (eq/ne (xor x y) x) simplifies to (eq/ne y 0). */
4386 if ((code
== EQ
|| code
== NE
)
4388 && rtx_equal_p (XEXP (op0
, 0), op1
)
4389 && !side_effects_p (XEXP (op0
, 0)))
4390 return simplify_gen_relational (code
, mode
, cmp_mode
,
4391 XEXP (op0
, 1), const0_rtx
);
4393 /* Likewise (eq/ne (xor x y) y) simplifies to (eq/ne x 0). */
4394 if ((code
== EQ
|| code
== NE
)
4396 && rtx_equal_p (XEXP (op0
, 1), op1
)
4397 && !side_effects_p (XEXP (op0
, 1)))
4398 return simplify_gen_relational (code
, mode
, cmp_mode
,
4399 XEXP (op0
, 0), const0_rtx
);
4401 /* (eq/ne (xor x C1) C2) simplifies to (eq/ne x (C1^C2)). */
4402 if ((code
== EQ
|| code
== NE
)
4404 && CONST_SCALAR_INT_P (op1
)
4405 && CONST_SCALAR_INT_P (XEXP (op0
, 1)))
4406 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
4407 simplify_gen_binary (XOR
, cmp_mode
,
4408 XEXP (op0
, 1), op1
));
4410 /* (eq/ne (bswap x) C1) simplifies to (eq/ne x C2) with C2 swapped. */
4411 if ((code
== EQ
|| code
== NE
)
4412 && GET_CODE (op0
) == BSWAP
4413 && CONST_SCALAR_INT_P (op1
))
4414 return simplify_gen_relational (code
, mode
, cmp_mode
, XEXP (op0
, 0),
4415 simplify_gen_unary (BSWAP
, cmp_mode
,
4418 /* (eq/ne (bswap x) (bswap y)) simplifies to (eq/ne x y). */
4419 if ((code
== EQ
|| code
== NE
)
4420 && GET_CODE (op0
) == BSWAP
4421 && GET_CODE (op1
) == BSWAP
)
4422 return simplify_gen_relational (code
, mode
, cmp_mode
,
4423 XEXP (op0
, 0), XEXP (op1
, 0));
4425 if (op0code
== POPCOUNT
&& op1
== const0_rtx
)
4431 /* (eq (popcount x) (const_int 0)) -> (eq x (const_int 0)). */
4432 return simplify_gen_relational (EQ
, mode
, GET_MODE (XEXP (op0
, 0)),
4433 XEXP (op0
, 0), const0_rtx
);
4438 /* (ne (popcount x) (const_int 0)) -> (ne x (const_int 0)). */
4439 return simplify_gen_relational (NE
, mode
, GET_MODE (XEXP (op0
, 0)),
4440 XEXP (op0
, 0), const0_rtx
);
4459 /* Convert the known results for EQ, LT, GT, LTU, GTU contained in
4460 KNOWN_RESULT to a CONST_INT, based on the requested comparison CODE
4461 For KNOWN_RESULT to make sense it should be either CMP_EQ, or the
4462 logical OR of one of (CMP_LT, CMP_GT) and one of (CMP_LTU, CMP_GTU).
4463 For floating-point comparisons, assume that the operands were ordered. */
4466 comparison_result (enum rtx_code code
, int known_results
)
4472 return (known_results
& CMP_EQ
) ? const_true_rtx
: const0_rtx
;
4475 return (known_results
& CMP_EQ
) ? const0_rtx
: const_true_rtx
;
4479 return (known_results
& CMP_LT
) ? const_true_rtx
: const0_rtx
;
4482 return (known_results
& CMP_LT
) ? const0_rtx
: const_true_rtx
;
4486 return (known_results
& CMP_GT
) ? const_true_rtx
: const0_rtx
;
4489 return (known_results
& CMP_GT
) ? const0_rtx
: const_true_rtx
;
4492 return (known_results
& CMP_LTU
) ? const_true_rtx
: const0_rtx
;
4494 return (known_results
& CMP_LTU
) ? const0_rtx
: const_true_rtx
;
4497 return (known_results
& CMP_GTU
) ? const_true_rtx
: const0_rtx
;
4499 return (known_results
& CMP_GTU
) ? const0_rtx
: const_true_rtx
;
4502 return const_true_rtx
;
4510 /* Check if the given comparison (done in the given MODE) is actually
4511 a tautology or a contradiction. If the mode is VOID_mode, the
4512 comparison is done in "infinite precision". If no simplification
4513 is possible, this function returns zero. Otherwise, it returns
4514 either const_true_rtx or const0_rtx. */
4517 simplify_const_relational_operation (enum rtx_code code
,
4518 enum machine_mode mode
,
4525 gcc_assert (mode
!= VOIDmode
4526 || (GET_MODE (op0
) == VOIDmode
4527 && GET_MODE (op1
) == VOIDmode
));
4529 /* If op0 is a compare, extract the comparison arguments from it. */
4530 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
4532 op1
= XEXP (op0
, 1);
4533 op0
= XEXP (op0
, 0);
4535 if (GET_MODE (op0
) != VOIDmode
)
4536 mode
= GET_MODE (op0
);
4537 else if (GET_MODE (op1
) != VOIDmode
)
4538 mode
= GET_MODE (op1
);
4543 /* We can't simplify MODE_CC values since we don't know what the
4544 actual comparison is. */
4545 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
|| CC0_P (op0
))
4548 /* Make sure the constant is second. */
4549 if (swap_commutative_operands_p (op0
, op1
))
4551 tem
= op0
, op0
= op1
, op1
= tem
;
4552 code
= swap_condition (code
);
4555 trueop0
= avoid_constant_pool_reference (op0
);
4556 trueop1
= avoid_constant_pool_reference (op1
);
4558 /* For integer comparisons of A and B maybe we can simplify A - B and can
4559 then simplify a comparison of that with zero. If A and B are both either
4560 a register or a CONST_INT, this can't help; testing for these cases will
4561 prevent infinite recursion here and speed things up.
4563 We can only do this for EQ and NE comparisons as otherwise we may
4564 lose or introduce overflow which we cannot disregard as undefined as
4565 we do not know the signedness of the operation on either the left or
4566 the right hand side of the comparison. */
4568 if (INTEGRAL_MODE_P (mode
) && trueop1
!= const0_rtx
4569 && (code
== EQ
|| code
== NE
)
4570 && ! ((REG_P (op0
) || CONST_INT_P (trueop0
))
4571 && (REG_P (op1
) || CONST_INT_P (trueop1
)))
4572 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
, op0
, op1
))
4573 /* We cannot do this if tem is a nonzero address. */
4574 && ! nonzero_address_p (tem
))
4575 return simplify_const_relational_operation (signed_condition (code
),
4576 mode
, tem
, const0_rtx
);
4578 if (! HONOR_NANS (mode
) && code
== ORDERED
)
4579 return const_true_rtx
;
4581 if (! HONOR_NANS (mode
) && code
== UNORDERED
)
4584 /* For modes without NaNs, if the two operands are equal, we know the
4585 result except if they have side-effects. Even with NaNs we know
4586 the result of unordered comparisons and, if signaling NaNs are
4587 irrelevant, also the result of LT/GT/LTGT. */
4588 if ((! HONOR_NANS (GET_MODE (trueop0
))
4589 || code
== UNEQ
|| code
== UNLE
|| code
== UNGE
4590 || ((code
== LT
|| code
== GT
|| code
== LTGT
)
4591 && ! HONOR_SNANS (GET_MODE (trueop0
))))
4592 && rtx_equal_p (trueop0
, trueop1
)
4593 && ! side_effects_p (trueop0
))
4594 return comparison_result (code
, CMP_EQ
);
4596 /* If the operands are floating-point constants, see if we can fold
4598 if (CONST_DOUBLE_AS_FLOAT_P (trueop0
)
4599 && CONST_DOUBLE_AS_FLOAT_P (trueop1
)
4600 && SCALAR_FLOAT_MODE_P (GET_MODE (trueop0
)))
4602 REAL_VALUE_TYPE d0
, d1
;
4604 REAL_VALUE_FROM_CONST_DOUBLE (d0
, trueop0
);
4605 REAL_VALUE_FROM_CONST_DOUBLE (d1
, trueop1
);
4607 /* Comparisons are unordered iff at least one of the values is NaN. */
4608 if (REAL_VALUE_ISNAN (d0
) || REAL_VALUE_ISNAN (d1
))
4618 return const_true_rtx
;
4631 return comparison_result (code
,
4632 (REAL_VALUES_EQUAL (d0
, d1
) ? CMP_EQ
:
4633 REAL_VALUES_LESS (d0
, d1
) ? CMP_LT
: CMP_GT
));
4636 /* Otherwise, see if the operands are both integers. */
4637 if ((GET_MODE_CLASS (mode
) == MODE_INT
|| mode
== VOIDmode
)
4638 && CONST_SCALAR_INT_P (trueop0
) && CONST_SCALAR_INT_P (trueop1
))
4640 /* It would be nice if we really had a mode here. However, the
4641 largest int representable on the target is as good as
4643 enum machine_mode cmode
= (mode
== VOIDmode
) ? MAX_MODE_INT
: mode
;
4644 rtx_mode_t ptrueop0
= std::make_pair (trueop0
, cmode
);
4645 rtx_mode_t ptrueop1
= std::make_pair (trueop1
, cmode
);
4647 if (wi::eq_p (ptrueop0
, ptrueop1
))
4648 return comparison_result (code
, CMP_EQ
);
4651 int cr
= wi::lts_p (ptrueop0
, ptrueop1
) ? CMP_LT
: CMP_GT
;
4652 cr
|= wi::ltu_p (ptrueop0
, ptrueop1
) ? CMP_LTU
: CMP_GTU
;
4653 return comparison_result (code
, cr
);
4657 /* Optimize comparisons with upper and lower bounds. */
4658 if (HWI_COMPUTABLE_MODE_P (mode
)
4659 && CONST_INT_P (trueop1
))
4662 unsigned HOST_WIDE_INT nonzero
= nonzero_bits (trueop0
, mode
);
4663 HOST_WIDE_INT val
= INTVAL (trueop1
);
4664 HOST_WIDE_INT mmin
, mmax
;
4674 /* Get a reduced range if the sign bit is zero. */
4675 if (nonzero
<= (GET_MODE_MASK (mode
) >> 1))
4682 rtx mmin_rtx
, mmax_rtx
;
4683 get_mode_bounds (mode
, sign
, mode
, &mmin_rtx
, &mmax_rtx
);
4685 mmin
= INTVAL (mmin_rtx
);
4686 mmax
= INTVAL (mmax_rtx
);
4689 unsigned int sign_copies
= num_sign_bit_copies (trueop0
, mode
);
4691 mmin
>>= (sign_copies
- 1);
4692 mmax
>>= (sign_copies
- 1);
4698 /* x >= y is always true for y <= mmin, always false for y > mmax. */
4700 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
4701 return const_true_rtx
;
4702 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
4707 return const_true_rtx
;
4712 /* x <= y is always true for y >= mmax, always false for y < mmin. */
4714 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
4715 return const_true_rtx
;
4716 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
4721 return const_true_rtx
;
4727 /* x == y is always false for y out of range. */
4728 if (val
< mmin
|| val
> mmax
)
4732 /* x > y is always false for y >= mmax, always true for y < mmin. */
4734 if ((unsigned HOST_WIDE_INT
) val
>= (unsigned HOST_WIDE_INT
) mmax
)
4736 if ((unsigned HOST_WIDE_INT
) val
< (unsigned HOST_WIDE_INT
) mmin
)
4737 return const_true_rtx
;
4743 return const_true_rtx
;
4746 /* x < y is always false for y <= mmin, always true for y > mmax. */
4748 if ((unsigned HOST_WIDE_INT
) val
<= (unsigned HOST_WIDE_INT
) mmin
)
4750 if ((unsigned HOST_WIDE_INT
) val
> (unsigned HOST_WIDE_INT
) mmax
)
4751 return const_true_rtx
;
4757 return const_true_rtx
;
4761 /* x != y is always true for y out of range. */
4762 if (val
< mmin
|| val
> mmax
)
4763 return const_true_rtx
;
4771 /* Optimize integer comparisons with zero. */
4772 if (trueop1
== const0_rtx
)
4774 /* Some addresses are known to be nonzero. We don't know
4775 their sign, but equality comparisons are known. */
4776 if (nonzero_address_p (trueop0
))
4778 if (code
== EQ
|| code
== LEU
)
4780 if (code
== NE
|| code
== GTU
)
4781 return const_true_rtx
;
4784 /* See if the first operand is an IOR with a constant. If so, we
4785 may be able to determine the result of this comparison. */
4786 if (GET_CODE (op0
) == IOR
)
4788 rtx inner_const
= avoid_constant_pool_reference (XEXP (op0
, 1));
4789 if (CONST_INT_P (inner_const
) && inner_const
!= const0_rtx
)
4791 int sign_bitnum
= GET_MODE_PRECISION (mode
) - 1;
4792 int has_sign
= (HOST_BITS_PER_WIDE_INT
>= sign_bitnum
4793 && (UINTVAL (inner_const
)
4794 & ((unsigned HOST_WIDE_INT
) 1
4804 return const_true_rtx
;
4808 return const_true_rtx
;
4822 /* Optimize comparison of ABS with zero. */
4823 if (trueop1
== CONST0_RTX (mode
)
4824 && (GET_CODE (trueop0
) == ABS
4825 || (GET_CODE (trueop0
) == FLOAT_EXTEND
4826 && GET_CODE (XEXP (trueop0
, 0)) == ABS
)))
4831 /* Optimize abs(x) < 0.0. */
4832 if (!HONOR_SNANS (mode
)
4833 && (!INTEGRAL_MODE_P (mode
)
4834 || (!flag_wrapv
&& !flag_trapv
&& flag_strict_overflow
)))
4836 if (INTEGRAL_MODE_P (mode
)
4837 && (issue_strict_overflow_warning
4838 (WARN_STRICT_OVERFLOW_CONDITIONAL
)))
4839 warning (OPT_Wstrict_overflow
,
4840 ("assuming signed overflow does not occur when "
4841 "assuming abs (x) < 0 is false"));
4847 /* Optimize abs(x) >= 0.0. */
4848 if (!HONOR_NANS (mode
)
4849 && (!INTEGRAL_MODE_P (mode
)
4850 || (!flag_wrapv
&& !flag_trapv
&& flag_strict_overflow
)))
4852 if (INTEGRAL_MODE_P (mode
)
4853 && (issue_strict_overflow_warning
4854 (WARN_STRICT_OVERFLOW_CONDITIONAL
)))
4855 warning (OPT_Wstrict_overflow
,
4856 ("assuming signed overflow does not occur when "
4857 "assuming abs (x) >= 0 is true"));
4858 return const_true_rtx
;
4863 /* Optimize ! (abs(x) < 0.0). */
4864 return const_true_rtx
;
4874 /* Simplify CODE, an operation with result mode MODE and three operands,
4875 OP0, OP1, and OP2. OP0_MODE was the mode of OP0 before it became
4876 a constant. Return 0 if no simplifications is possible. */
4879 simplify_ternary_operation (enum rtx_code code
, enum machine_mode mode
,
4880 enum machine_mode op0_mode
, rtx op0
, rtx op1
,
4883 unsigned int width
= GET_MODE_PRECISION (mode
);
4884 bool any_change
= false;
4887 /* VOIDmode means "infinite" precision. */
4889 width
= HOST_BITS_PER_WIDE_INT
;
4894 /* Simplify negations around the multiplication. */
4895 /* -a * -b + c => a * b + c. */
4896 if (GET_CODE (op0
) == NEG
)
4898 tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
);
4900 op1
= tem
, op0
= XEXP (op0
, 0), any_change
= true;
4902 else if (GET_CODE (op1
) == NEG
)
4904 tem
= simplify_unary_operation (NEG
, mode
, op0
, mode
);
4906 op0
= tem
, op1
= XEXP (op1
, 0), any_change
= true;
4909 /* Canonicalize the two multiplication operands. */
4910 /* a * -b + c => -b * a + c. */
4911 if (swap_commutative_operands_p (op0
, op1
))
4912 tem
= op0
, op0
= op1
, op1
= tem
, any_change
= true;
4915 return gen_rtx_FMA (mode
, op0
, op1
, op2
);
4920 if (CONST_INT_P (op0
)
4921 && CONST_INT_P (op1
)
4922 && CONST_INT_P (op2
)
4923 && ((unsigned) INTVAL (op1
) + (unsigned) INTVAL (op2
) <= width
)
4924 && width
<= (unsigned) HOST_BITS_PER_WIDE_INT
)
4926 /* Extracting a bit-field from a constant */
4927 unsigned HOST_WIDE_INT val
= UINTVAL (op0
);
4928 HOST_WIDE_INT op1val
= INTVAL (op1
);
4929 HOST_WIDE_INT op2val
= INTVAL (op2
);
4930 if (BITS_BIG_ENDIAN
)
4931 val
>>= GET_MODE_PRECISION (op0_mode
) - op2val
- op1val
;
4935 if (HOST_BITS_PER_WIDE_INT
!= op1val
)
4937 /* First zero-extend. */
4938 val
&= ((unsigned HOST_WIDE_INT
) 1 << op1val
) - 1;
4939 /* If desired, propagate sign bit. */
4940 if (code
== SIGN_EXTRACT
4941 && (val
& ((unsigned HOST_WIDE_INT
) 1 << (op1val
- 1)))
4943 val
|= ~ (((unsigned HOST_WIDE_INT
) 1 << op1val
) - 1);
4946 return gen_int_mode (val
, mode
);
4951 if (CONST_INT_P (op0
))
4952 return op0
!= const0_rtx
? op1
: op2
;
4954 /* Convert c ? a : a into "a". */
4955 if (rtx_equal_p (op1
, op2
) && ! side_effects_p (op0
))
4958 /* Convert a != b ? a : b into "a". */
4959 if (GET_CODE (op0
) == NE
4960 && ! side_effects_p (op0
)
4961 && ! HONOR_NANS (mode
)
4962 && ! HONOR_SIGNED_ZEROS (mode
)
4963 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
4964 && rtx_equal_p (XEXP (op0
, 1), op2
))
4965 || (rtx_equal_p (XEXP (op0
, 0), op2
)
4966 && rtx_equal_p (XEXP (op0
, 1), op1
))))
4969 /* Convert a == b ? a : b into "b". */
4970 if (GET_CODE (op0
) == EQ
4971 && ! side_effects_p (op0
)
4972 && ! HONOR_NANS (mode
)
4973 && ! HONOR_SIGNED_ZEROS (mode
)
4974 && ((rtx_equal_p (XEXP (op0
, 0), op1
)
4975 && rtx_equal_p (XEXP (op0
, 1), op2
))
4976 || (rtx_equal_p (XEXP (op0
, 0), op2
)
4977 && rtx_equal_p (XEXP (op0
, 1), op1
))))
4980 if (COMPARISON_P (op0
) && ! side_effects_p (op0
))
4982 enum machine_mode cmp_mode
= (GET_MODE (XEXP (op0
, 0)) == VOIDmode
4983 ? GET_MODE (XEXP (op0
, 1))
4984 : GET_MODE (XEXP (op0
, 0)));
4987 /* Look for happy constants in op1 and op2. */
4988 if (CONST_INT_P (op1
) && CONST_INT_P (op2
))
4990 HOST_WIDE_INT t
= INTVAL (op1
);
4991 HOST_WIDE_INT f
= INTVAL (op2
);
4993 if (t
== STORE_FLAG_VALUE
&& f
== 0)
4994 code
= GET_CODE (op0
);
4995 else if (t
== 0 && f
== STORE_FLAG_VALUE
)
4998 tmp
= reversed_comparison_code (op0
, NULL_RTX
);
5006 return simplify_gen_relational (code
, mode
, cmp_mode
,
5007 XEXP (op0
, 0), XEXP (op0
, 1));
5010 if (cmp_mode
== VOIDmode
)
5011 cmp_mode
= op0_mode
;
5012 temp
= simplify_relational_operation (GET_CODE (op0
), op0_mode
,
5013 cmp_mode
, XEXP (op0
, 0),
5016 /* See if any simplifications were possible. */
5019 if (CONST_INT_P (temp
))
5020 return temp
== const0_rtx
? op2
: op1
;
5022 return gen_rtx_IF_THEN_ELSE (mode
, temp
, op1
, op2
);
5028 gcc_assert (GET_MODE (op0
) == mode
);
5029 gcc_assert (GET_MODE (op1
) == mode
);
5030 gcc_assert (VECTOR_MODE_P (mode
));
5031 trueop2
= avoid_constant_pool_reference (op2
);
5032 if (CONST_INT_P (trueop2
))
5034 int elt_size
= GET_MODE_SIZE (GET_MODE_INNER (mode
));
5035 unsigned n_elts
= (GET_MODE_SIZE (mode
) / elt_size
);
5036 unsigned HOST_WIDE_INT sel
= UINTVAL (trueop2
);
5037 unsigned HOST_WIDE_INT mask
;
5038 if (n_elts
== HOST_BITS_PER_WIDE_INT
)
5041 mask
= ((unsigned HOST_WIDE_INT
) 1 << n_elts
) - 1;
5043 if (!(sel
& mask
) && !side_effects_p (op0
))
5045 if ((sel
& mask
) == mask
&& !side_effects_p (op1
))
5048 rtx trueop0
= avoid_constant_pool_reference (op0
);
5049 rtx trueop1
= avoid_constant_pool_reference (op1
);
5050 if (GET_CODE (trueop0
) == CONST_VECTOR
5051 && GET_CODE (trueop1
) == CONST_VECTOR
)
5053 rtvec v
= rtvec_alloc (n_elts
);
5056 for (i
= 0; i
< n_elts
; i
++)
5057 RTVEC_ELT (v
, i
) = ((sel
& ((unsigned HOST_WIDE_INT
) 1 << i
))
5058 ? CONST_VECTOR_ELT (trueop0
, i
)
5059 : CONST_VECTOR_ELT (trueop1
, i
));
5060 return gen_rtx_CONST_VECTOR (mode
, v
);
5063 /* Replace (vec_merge (vec_merge a b m) c n) with (vec_merge b c n)
5064 if no element from a appears in the result. */
5065 if (GET_CODE (op0
) == VEC_MERGE
)
5067 tem
= avoid_constant_pool_reference (XEXP (op0
, 2));
5068 if (CONST_INT_P (tem
))
5070 unsigned HOST_WIDE_INT sel0
= UINTVAL (tem
);
5071 if (!(sel
& sel0
& mask
) && !side_effects_p (XEXP (op0
, 0)))
5072 return simplify_gen_ternary (code
, mode
, mode
,
5073 XEXP (op0
, 1), op1
, op2
);
5074 if (!(sel
& ~sel0
& mask
) && !side_effects_p (XEXP (op0
, 1)))
5075 return simplify_gen_ternary (code
, mode
, mode
,
5076 XEXP (op0
, 0), op1
, op2
);
5079 if (GET_CODE (op1
) == VEC_MERGE
)
5081 tem
= avoid_constant_pool_reference (XEXP (op1
, 2));
5082 if (CONST_INT_P (tem
))
5084 unsigned HOST_WIDE_INT sel1
= UINTVAL (tem
);
5085 if (!(~sel
& sel1
& mask
) && !side_effects_p (XEXP (op1
, 0)))
5086 return simplify_gen_ternary (code
, mode
, mode
,
5087 op0
, XEXP (op1
, 1), op2
);
5088 if (!(~sel
& ~sel1
& mask
) && !side_effects_p (XEXP (op1
, 1)))
5089 return simplify_gen_ternary (code
, mode
, mode
,
5090 op0
, XEXP (op1
, 0), op2
);
5095 if (rtx_equal_p (op0
, op1
)
5096 && !side_effects_p (op2
) && !side_effects_p (op1
))
5108 /* Evaluate a SUBREG of a CONST_INT or CONST_WIDE_INT or CONST_DOUBLE
5109 or CONST_FIXED or CONST_VECTOR, returning another CONST_INT or
5110 CONST_WIDE_INT or CONST_DOUBLE or CONST_FIXED or CONST_VECTOR.
5112 Works by unpacking OP into a collection of 8-bit values
5113 represented as a little-endian array of 'unsigned char', selecting by BYTE,
5114 and then repacking them again for OUTERMODE. */
5117 simplify_immed_subreg (enum machine_mode outermode
, rtx op
,
5118 enum machine_mode innermode
, unsigned int byte
)
5122 value_mask
= (1 << value_bit
) - 1
5124 unsigned char value
[MAX_BITSIZE_MODE_ANY_MODE
/value_bit
];
5133 rtvec result_v
= NULL
;
5134 enum mode_class outer_class
;
5135 enum machine_mode outer_submode
;
5138 /* Some ports misuse CCmode. */
5139 if (GET_MODE_CLASS (outermode
) == MODE_CC
&& CONST_INT_P (op
))
5142 /* We have no way to represent a complex constant at the rtl level. */
5143 if (COMPLEX_MODE_P (outermode
))
5146 /* We support any size mode. */
5147 max_bitsize
= MAX (GET_MODE_BITSIZE (outermode
),
5148 GET_MODE_BITSIZE (innermode
));
5150 /* Unpack the value. */
5152 if (GET_CODE (op
) == CONST_VECTOR
)
5154 num_elem
= CONST_VECTOR_NUNITS (op
);
5155 elems
= &CONST_VECTOR_ELT (op
, 0);
5156 elem_bitsize
= GET_MODE_BITSIZE (GET_MODE_INNER (innermode
));
5162 elem_bitsize
= max_bitsize
;
5164 /* If this asserts, it is too complicated; reducing value_bit may help. */
5165 gcc_assert (BITS_PER_UNIT
% value_bit
== 0);
5166 /* I don't know how to handle endianness of sub-units. */
5167 gcc_assert (elem_bitsize
% BITS_PER_UNIT
== 0);
5169 for (elem
= 0; elem
< num_elem
; elem
++)
5172 rtx el
= elems
[elem
];
5174 /* Vectors are kept in target memory order. (This is probably
5177 unsigned byte
= (elem
* elem_bitsize
) / BITS_PER_UNIT
;
5178 unsigned ibyte
= (((num_elem
- 1 - elem
) * elem_bitsize
)
5180 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
5181 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
5182 unsigned bytele
= (subword_byte
% UNITS_PER_WORD
5183 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
5184 vp
= value
+ (bytele
* BITS_PER_UNIT
) / value_bit
;
5187 switch (GET_CODE (el
))
5191 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
5193 *vp
++ = INTVAL (el
) >> i
;
5194 /* CONST_INTs are always logically sign-extended. */
5195 for (; i
< elem_bitsize
; i
+= value_bit
)
5196 *vp
++ = INTVAL (el
) < 0 ? -1 : 0;
5199 case CONST_WIDE_INT
:
5201 rtx_mode_t val
= std::make_pair (el
, innermode
);
5202 unsigned char extend
= wi::sign_mask (val
);
5204 for (i
= 0; i
< elem_bitsize
; i
+= value_bit
)
5205 *vp
++ = wi::extract_uhwi (val
, i
, value_bit
);
5206 for (; i
< elem_bitsize
; i
+= value_bit
)
5212 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (el
) == VOIDmode
)
5214 unsigned char extend
= 0;
5215 /* If this triggers, someone should have generated a
5216 CONST_INT instead. */
5217 gcc_assert (elem_bitsize
> HOST_BITS_PER_WIDE_INT
);
5219 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
+= value_bit
)
5220 *vp
++ = CONST_DOUBLE_LOW (el
) >> i
;
5221 while (i
< HOST_BITS_PER_DOUBLE_INT
&& i
< elem_bitsize
)
5224 = CONST_DOUBLE_HIGH (el
) >> (i
- HOST_BITS_PER_WIDE_INT
);
5228 if (CONST_DOUBLE_HIGH (el
) >> (HOST_BITS_PER_WIDE_INT
- 1))
5230 for (; i
< elem_bitsize
; i
+= value_bit
)
5235 /* This is big enough for anything on the platform. */
5236 long tmp
[MAX_BITSIZE_MODE_ANY_MODE
/ 32];
5237 int bitsize
= GET_MODE_BITSIZE (GET_MODE (el
));
5239 gcc_assert (SCALAR_FLOAT_MODE_P (GET_MODE (el
)));
5240 gcc_assert (bitsize
<= elem_bitsize
);
5241 gcc_assert (bitsize
% value_bit
== 0);
5243 real_to_target (tmp
, CONST_DOUBLE_REAL_VALUE (el
),
5246 /* real_to_target produces its result in words affected by
5247 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
5248 and use WORDS_BIG_ENDIAN instead; see the documentation
5249 of SUBREG in rtl.texi. */
5250 for (i
= 0; i
< bitsize
; i
+= value_bit
)
5253 if (WORDS_BIG_ENDIAN
)
5254 ibase
= bitsize
- 1 - i
;
5257 *vp
++ = tmp
[ibase
/ 32] >> i
% 32;
5260 /* It shouldn't matter what's done here, so fill it with
5262 for (; i
< elem_bitsize
; i
+= value_bit
)
5268 if (elem_bitsize
<= HOST_BITS_PER_WIDE_INT
)
5270 for (i
= 0; i
< elem_bitsize
; i
+= value_bit
)
5271 *vp
++ = CONST_FIXED_VALUE_LOW (el
) >> i
;
5275 for (i
= 0; i
< HOST_BITS_PER_WIDE_INT
; i
+= value_bit
)
5276 *vp
++ = CONST_FIXED_VALUE_LOW (el
) >> i
;
5277 for (; i
< HOST_BITS_PER_DOUBLE_INT
&& i
< elem_bitsize
;
5279 *vp
++ = CONST_FIXED_VALUE_HIGH (el
)
5280 >> (i
- HOST_BITS_PER_WIDE_INT
);
5281 for (; i
< elem_bitsize
; i
+= value_bit
)
5291 /* Now, pick the right byte to start with. */
5292 /* Renumber BYTE so that the least-significant byte is byte 0. A special
5293 case is paradoxical SUBREGs, which shouldn't be adjusted since they
5294 will already have offset 0. */
5295 if (GET_MODE_SIZE (innermode
) >= GET_MODE_SIZE (outermode
))
5297 unsigned ibyte
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
)
5299 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
5300 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
5301 byte
= (subword_byte
% UNITS_PER_WORD
5302 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
5305 /* BYTE should still be inside OP. (Note that BYTE is unsigned,
5306 so if it's become negative it will instead be very large.) */
5307 gcc_assert (byte
< GET_MODE_SIZE (innermode
));
5309 /* Convert from bytes to chunks of size value_bit. */
5310 value_start
= byte
* (BITS_PER_UNIT
/ value_bit
);
5312 /* Re-pack the value. */
5314 if (VECTOR_MODE_P (outermode
))
5316 num_elem
= GET_MODE_NUNITS (outermode
);
5317 result_v
= rtvec_alloc (num_elem
);
5318 elems
= &RTVEC_ELT (result_v
, 0);
5319 outer_submode
= GET_MODE_INNER (outermode
);
5325 outer_submode
= outermode
;
5328 outer_class
= GET_MODE_CLASS (outer_submode
);
5329 elem_bitsize
= GET_MODE_BITSIZE (outer_submode
);
5331 gcc_assert (elem_bitsize
% value_bit
== 0);
5332 gcc_assert (elem_bitsize
+ value_start
* value_bit
<= max_bitsize
);
5334 for (elem
= 0; elem
< num_elem
; elem
++)
5338 /* Vectors are stored in target memory order. (This is probably
5341 unsigned byte
= (elem
* elem_bitsize
) / BITS_PER_UNIT
;
5342 unsigned ibyte
= (((num_elem
- 1 - elem
) * elem_bitsize
)
5344 unsigned word_byte
= WORDS_BIG_ENDIAN
? ibyte
: byte
;
5345 unsigned subword_byte
= BYTES_BIG_ENDIAN
? ibyte
: byte
;
5346 unsigned bytele
= (subword_byte
% UNITS_PER_WORD
5347 + (word_byte
/ UNITS_PER_WORD
) * UNITS_PER_WORD
);
5348 vp
= value
+ value_start
+ (bytele
* BITS_PER_UNIT
) / value_bit
;
5351 switch (outer_class
)
5354 case MODE_PARTIAL_INT
:
5359 = (GET_MODE_BITSIZE (outer_submode
) + HOST_BITS_PER_WIDE_INT
- 1)
5360 / HOST_BITS_PER_WIDE_INT
;
5361 HOST_WIDE_INT tmp
[MAX_BITSIZE_MODE_ANY_INT
/ HOST_BITS_PER_WIDE_INT
];
5364 for (u
= 0; u
< units
; u
++)
5366 unsigned HOST_WIDE_INT buf
= 0;
5368 i
< HOST_BITS_PER_WIDE_INT
&& base
+ i
< elem_bitsize
;
5370 buf
|= (unsigned HOST_WIDE_INT
)(*vp
++ & value_mask
) << i
;
5373 base
+= HOST_BITS_PER_WIDE_INT
;
5375 r
= wide_int::from_array (tmp
, units
,
5376 GET_MODE_PRECISION (outer_submode
));
5377 elems
[elem
] = immed_wide_int_const (r
, outer_submode
);
5382 case MODE_DECIMAL_FLOAT
:
5385 long tmp
[MAX_BITSIZE_MODE_ANY_INT
/ 32];
5387 /* real_from_target wants its input in words affected by
5388 FLOAT_WORDS_BIG_ENDIAN. However, we ignore this,
5389 and use WORDS_BIG_ENDIAN instead; see the documentation
5390 of SUBREG in rtl.texi. */
5391 for (i
= 0; i
< max_bitsize
/ 32; i
++)
5393 for (i
= 0; i
< elem_bitsize
; i
+= value_bit
)
5396 if (WORDS_BIG_ENDIAN
)
5397 ibase
= elem_bitsize
- 1 - i
;
5400 tmp
[ibase
/ 32] |= (*vp
++ & value_mask
) << i
% 32;
5403 real_from_target (&r
, tmp
, outer_submode
);
5404 elems
[elem
] = CONST_DOUBLE_FROM_REAL_VALUE (r
, outer_submode
);
5416 f
.mode
= outer_submode
;
5419 i
< HOST_BITS_PER_WIDE_INT
&& i
< elem_bitsize
;
5421 f
.data
.low
|= (unsigned HOST_WIDE_INT
)(*vp
++ & value_mask
) << i
;
5422 for (; i
< elem_bitsize
; i
+= value_bit
)
5423 f
.data
.high
|= ((unsigned HOST_WIDE_INT
)(*vp
++ & value_mask
)
5424 << (i
- HOST_BITS_PER_WIDE_INT
));
5426 elems
[elem
] = CONST_FIXED_FROM_FIXED_VALUE (f
, outer_submode
);
5434 if (VECTOR_MODE_P (outermode
))
5435 return gen_rtx_CONST_VECTOR (outermode
, result_v
);
5440 /* Simplify SUBREG:OUTERMODE(OP:INNERMODE, BYTE)
5441 Return 0 if no simplifications are possible. */
5443 simplify_subreg (enum machine_mode outermode
, rtx op
,
5444 enum machine_mode innermode
, unsigned int byte
)
5446 /* Little bit of sanity checking. */
5447 gcc_assert (innermode
!= VOIDmode
);
5448 gcc_assert (outermode
!= VOIDmode
);
5449 gcc_assert (innermode
!= BLKmode
);
5450 gcc_assert (outermode
!= BLKmode
);
5452 gcc_assert (GET_MODE (op
) == innermode
5453 || GET_MODE (op
) == VOIDmode
);
5455 if ((byte
% GET_MODE_SIZE (outermode
)) != 0)
5458 if (byte
>= GET_MODE_SIZE (innermode
))
5461 if (outermode
== innermode
&& !byte
)
5464 if (CONST_SCALAR_INT_P (op
)
5465 || CONST_DOUBLE_AS_FLOAT_P (op
)
5466 || GET_CODE (op
) == CONST_FIXED
5467 || GET_CODE (op
) == CONST_VECTOR
)
5468 return simplify_immed_subreg (outermode
, op
, innermode
, byte
);
5470 /* Changing mode twice with SUBREG => just change it once,
5471 or not at all if changing back op starting mode. */
5472 if (GET_CODE (op
) == SUBREG
)
5474 enum machine_mode innermostmode
= GET_MODE (SUBREG_REG (op
));
5475 int final_offset
= byte
+ SUBREG_BYTE (op
);
5478 if (outermode
== innermostmode
5479 && byte
== 0 && SUBREG_BYTE (op
) == 0)
5480 return SUBREG_REG (op
);
5482 /* The SUBREG_BYTE represents offset, as if the value were stored
5483 in memory. Irritating exception is paradoxical subreg, where
5484 we define SUBREG_BYTE to be 0. On big endian machines, this
5485 value should be negative. For a moment, undo this exception. */
5486 if (byte
== 0 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
5488 int difference
= (GET_MODE_SIZE (innermode
) - GET_MODE_SIZE (outermode
));
5489 if (WORDS_BIG_ENDIAN
)
5490 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5491 if (BYTES_BIG_ENDIAN
)
5492 final_offset
+= difference
% UNITS_PER_WORD
;
5494 if (SUBREG_BYTE (op
) == 0
5495 && GET_MODE_SIZE (innermostmode
) < GET_MODE_SIZE (innermode
))
5497 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (innermode
));
5498 if (WORDS_BIG_ENDIAN
)
5499 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5500 if (BYTES_BIG_ENDIAN
)
5501 final_offset
+= difference
% UNITS_PER_WORD
;
5504 /* See whether resulting subreg will be paradoxical. */
5505 if (GET_MODE_SIZE (innermostmode
) > GET_MODE_SIZE (outermode
))
5507 /* In nonparadoxical subregs we can't handle negative offsets. */
5508 if (final_offset
< 0)
5510 /* Bail out in case resulting subreg would be incorrect. */
5511 if (final_offset
% GET_MODE_SIZE (outermode
)
5512 || (unsigned) final_offset
>= GET_MODE_SIZE (innermostmode
))
5518 int difference
= (GET_MODE_SIZE (innermostmode
) - GET_MODE_SIZE (outermode
));
5520 /* In paradoxical subreg, see if we are still looking on lower part.
5521 If so, our SUBREG_BYTE will be 0. */
5522 if (WORDS_BIG_ENDIAN
)
5523 offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5524 if (BYTES_BIG_ENDIAN
)
5525 offset
+= difference
% UNITS_PER_WORD
;
5526 if (offset
== final_offset
)
5532 /* Recurse for further possible simplifications. */
5533 newx
= simplify_subreg (outermode
, SUBREG_REG (op
), innermostmode
,
5537 if (validate_subreg (outermode
, innermostmode
,
5538 SUBREG_REG (op
), final_offset
))
5540 newx
= gen_rtx_SUBREG (outermode
, SUBREG_REG (op
), final_offset
);
5541 if (SUBREG_PROMOTED_VAR_P (op
)
5542 && SUBREG_PROMOTED_UNSIGNED_P (op
) >= 0
5543 && GET_MODE_CLASS (outermode
) == MODE_INT
5544 && IN_RANGE (GET_MODE_SIZE (outermode
),
5545 GET_MODE_SIZE (innermode
),
5546 GET_MODE_SIZE (innermostmode
))
5547 && subreg_lowpart_p (newx
))
5549 SUBREG_PROMOTED_VAR_P (newx
) = 1;
5550 SUBREG_PROMOTED_UNSIGNED_SET
5551 (newx
, SUBREG_PROMOTED_UNSIGNED_P (op
));
5558 /* SUBREG of a hard register => just change the register number
5559 and/or mode. If the hard register is not valid in that mode,
5560 suppress this simplification. If the hard register is the stack,
5561 frame, or argument pointer, leave this as a SUBREG. */
5563 if (REG_P (op
) && HARD_REGISTER_P (op
))
5565 unsigned int regno
, final_regno
;
5568 final_regno
= simplify_subreg_regno (regno
, innermode
, byte
, outermode
);
5569 if (HARD_REGISTER_NUM_P (final_regno
))
5572 int final_offset
= byte
;
5574 /* Adjust offset for paradoxical subregs. */
5576 && GET_MODE_SIZE (innermode
) < GET_MODE_SIZE (outermode
))
5578 int difference
= (GET_MODE_SIZE (innermode
)
5579 - GET_MODE_SIZE (outermode
));
5580 if (WORDS_BIG_ENDIAN
)
5581 final_offset
+= (difference
/ UNITS_PER_WORD
) * UNITS_PER_WORD
;
5582 if (BYTES_BIG_ENDIAN
)
5583 final_offset
+= difference
% UNITS_PER_WORD
;
5586 x
= gen_rtx_REG_offset (op
, outermode
, final_regno
, final_offset
);
5588 /* Propagate original regno. We don't have any way to specify
5589 the offset inside original regno, so do so only for lowpart.
5590 The information is used only by alias analysis that can not
5591 grog partial register anyway. */
5593 if (subreg_lowpart_offset (outermode
, innermode
) == byte
)
5594 ORIGINAL_REGNO (x
) = ORIGINAL_REGNO (op
);
5599 /* If we have a SUBREG of a register that we are replacing and we are
5600 replacing it with a MEM, make a new MEM and try replacing the
5601 SUBREG with it. Don't do this if the MEM has a mode-dependent address
5602 or if we would be widening it. */
5605 && ! mode_dependent_address_p (XEXP (op
, 0), MEM_ADDR_SPACE (op
))
5606 /* Allow splitting of volatile memory references in case we don't
5607 have instruction to move the whole thing. */
5608 && (! MEM_VOLATILE_P (op
)
5609 || ! have_insn_for (SET
, innermode
))
5610 && GET_MODE_SIZE (outermode
) <= GET_MODE_SIZE (GET_MODE (op
)))
5611 return adjust_address_nv (op
, outermode
, byte
);
5613 /* Handle complex values represented as CONCAT
5614 of real and imaginary part. */
5615 if (GET_CODE (op
) == CONCAT
)
5617 unsigned int part_size
, final_offset
;
5620 part_size
= GET_MODE_UNIT_SIZE (GET_MODE (XEXP (op
, 0)));
5621 if (byte
< part_size
)
5623 part
= XEXP (op
, 0);
5624 final_offset
= byte
;
5628 part
= XEXP (op
, 1);
5629 final_offset
= byte
- part_size
;
5632 if (final_offset
+ GET_MODE_SIZE (outermode
) > part_size
)
5635 res
= simplify_subreg (outermode
, part
, GET_MODE (part
), final_offset
);
5638 if (validate_subreg (outermode
, GET_MODE (part
), part
, final_offset
))
5639 return gen_rtx_SUBREG (outermode
, part
, final_offset
);
5643 /* A SUBREG resulting from a zero extension may fold to zero if
5644 it extracts higher bits that the ZERO_EXTEND's source bits. */
5645 if (GET_CODE (op
) == ZERO_EXTEND
&& SCALAR_INT_MODE_P (innermode
))
5647 unsigned int bitpos
= subreg_lsb_1 (outermode
, innermode
, byte
);
5648 if (bitpos
>= GET_MODE_PRECISION (GET_MODE (XEXP (op
, 0))))
5649 return CONST0_RTX (outermode
);
5652 if (SCALAR_INT_MODE_P (outermode
)
5653 && SCALAR_INT_MODE_P (innermode
)
5654 && GET_MODE_PRECISION (outermode
) < GET_MODE_PRECISION (innermode
)
5655 && byte
== subreg_lowpart_offset (outermode
, innermode
))
5657 rtx tem
= simplify_truncation (outermode
, op
, innermode
);
5665 /* Make a SUBREG operation or equivalent if it folds. */
5668 simplify_gen_subreg (enum machine_mode outermode
, rtx op
,
5669 enum machine_mode innermode
, unsigned int byte
)
5673 newx
= simplify_subreg (outermode
, op
, innermode
, byte
);
5677 if (GET_CODE (op
) == SUBREG
5678 || GET_CODE (op
) == CONCAT
5679 || GET_MODE (op
) == VOIDmode
)
5682 if (validate_subreg (outermode
, innermode
, op
, byte
))
5683 return gen_rtx_SUBREG (outermode
, op
, byte
);
5688 /* Simplify X, an rtx expression.
5690 Return the simplified expression or NULL if no simplifications
5693 This is the preferred entry point into the simplification routines;
5694 however, we still allow passes to call the more specific routines.
5696 Right now GCC has three (yes, three) major bodies of RTL simplification
5697 code that need to be unified.
5699 1. fold_rtx in cse.c. This code uses various CSE specific
5700 information to aid in RTL simplification.
5702 2. simplify_rtx in combine.c. Similar to fold_rtx, except that
5703 it uses combine specific information to aid in RTL
5706 3. The routines in this file.
5709 Long term we want to only have one body of simplification code; to
5710 get to that state I recommend the following steps:
5712 1. Pour over fold_rtx & simplify_rtx and move any simplifications
5713 which are not pass dependent state into these routines.
5715 2. As code is moved by #1, change fold_rtx & simplify_rtx to
5716 use this routine whenever possible.
5718 3. Allow for pass dependent state to be provided to these
5719 routines and add simplifications based on the pass dependent
5720 state. Remove code from cse.c & combine.c that becomes
5723 It will take time, but ultimately the compiler will be easier to
5724 maintain and improve. It's totally silly that when we add a
5725 simplification that it needs to be added to 4 places (3 for RTL
5726 simplification and 1 for tree simplification. */
5729 simplify_rtx (const_rtx x
)
5731 const enum rtx_code code
= GET_CODE (x
);
5732 const enum machine_mode mode
= GET_MODE (x
);
5734 switch (GET_RTX_CLASS (code
))
5737 return simplify_unary_operation (code
, mode
,
5738 XEXP (x
, 0), GET_MODE (XEXP (x
, 0)));
5739 case RTX_COMM_ARITH
:
5740 if (swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5741 return simplify_gen_binary (code
, mode
, XEXP (x
, 1), XEXP (x
, 0));
5743 /* Fall through.... */
5746 return simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5749 case RTX_BITFIELD_OPS
:
5750 return simplify_ternary_operation (code
, mode
, GET_MODE (XEXP (x
, 0)),
5751 XEXP (x
, 0), XEXP (x
, 1),
5755 case RTX_COMM_COMPARE
:
5756 return simplify_relational_operation (code
, mode
,
5757 ((GET_MODE (XEXP (x
, 0))
5759 ? GET_MODE (XEXP (x
, 0))
5760 : GET_MODE (XEXP (x
, 1))),
5766 return simplify_subreg (mode
, SUBREG_REG (x
),
5767 GET_MODE (SUBREG_REG (x
)),
5774 /* Convert (lo_sum (high FOO) FOO) to FOO. */
5775 if (GET_CODE (XEXP (x
, 0)) == HIGH
5776 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))