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aarch64: Add support for arm_sve_vector_bits
[thirdparty/gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve / acle / general / attributes_6.c
1 /* { dg-options "-O2 -msve-vector-bits=256" } */
2 /* { dg-final { check-function-bodies "**" "" } } */
3
4 #include <arm_sve.h>
5
6 #define N __ARM_FEATURE_SVE_BITS
7 #define FIXED_ATTR __attribute__ ((arm_sve_vector_bits (N)))
8 #define GNU_ATTR __attribute__ ((vector_size (N / 8)))
9
10 typedef svint8_t fixed_int8_t FIXED_ATTR;
11
12 typedef svbool_t fixed_bool_t FIXED_ATTR;
13
14 typedef int8_t gnu_int8_t GNU_ATTR;
15
16 #ifdef __cplusplus
17 extern "C" {
18 #endif
19
20 /*
21 ** test_add:
22 ** add z0\.b, (?:z0\.b, z1\.b|z1\.b, z0\.b)
23 ** ret
24 */
25 fixed_int8_t
26 test_add (fixed_int8_t x, fixed_int8_t y)
27 {
28 return x + y;
29 }
30
31 /*
32 ** test_add_gnu:
33 ** (
34 ** add (z[0-9]+\.b), (?:z0\.b, z1\.b|z1\.b, z0\.b)
35 ** ptrue (p[0-7])\.b, vl32
36 ** st1b \1, \2, \[x8\]
37 ** |
38 ** ptrue (p[0-7]\.b), vl32
39 ** add (z[0-9]+)\.b, (?:z0\.b, z1\.b|z1\.b, z0\.b)
40 ** st1b \4, \3, \[x8\]
41 ** )
42 ** ret
43 */
44 gnu_int8_t
45 test_add_gnu (fixed_int8_t x, fixed_int8_t y)
46 {
47 return x + y;
48 }
49
50 /*
51 ** test_load: { target lp64 }
52 ** ld1b z0\.b, p0/z, \[x0\]
53 ** ret
54 */
55 /*
56 ** test_load: { target ilp32 }
57 ** uxtw x0, w0
58 ** ld1b z0\.b, p0/z, \[x0\]
59 ** ret
60 */
61 fixed_int8_t
62 test_load (fixed_bool_t pg, int8_t *ptr)
63 {
64 return svld1 (pg, ptr);
65 }
66
67 /*
68 ** test_store: { target lp64 }
69 ** st1b z0\.b, p0, \[x0\]
70 ** ret
71 */
72 /*
73 ** test_store: { target ilp32 }
74 ** uxtw x0, w0
75 ** st1b z0\.b, p0, \[x0\]
76 ** ret
77 */
78 void
79 test_store (fixed_bool_t pg, int8_t *ptr, fixed_int8_t data)
80 {
81 svst1 (pg, ptr, data);
82 }
83
84 /*
85 ** test_and_z:
86 ** and p0\.b, p0/z, p1\.b, p2\.b
87 ** ret
88 */
89 fixed_bool_t
90 test_and_z (fixed_bool_t pg, svbool_t p1, fixed_bool_t p2)
91 {
92 return svand_z (pg, p1, p2);
93 }
94
95 #ifdef __cplusplus
96 }
97 #endif