gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qdmlalt_lane_s32.c

   1 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
   2
   3 #include "test_sve_acle.h"
   4
   5 /*
   6 ** qdmlalt_lane_0_s32_tied1:
   7 **      sqdmlalt        z0\.s, z4\.h, z5\.h\[0\]
   8 **      ret
   9 */
  10 TEST_DUAL_Z (qdmlalt_lane_0_s32_tied1, svint32_t, svint16_t,
  11              z0 = svqdmlalt_lane_s32 (z0, z4, z5, 0),
  12              z0 = svqdmlalt_lane (z0, z4, z5, 0))
  13
  14 /*
  15 ** qdmlalt_lane_0_s32_tied2:
  16 **      mov     (z[0-9]+)\.d, z0\.d
  17 **      movprfx z0, z4
  18 **      sqdmlalt        z0\.s, \1\.h, z1\.h\[0\]
  19 **      ret
  20 */
  21 TEST_DUAL_Z_REV (qdmlalt_lane_0_s32_tied2, svint32_t, svint16_t,
  22                  z0_res = svqdmlalt_lane_s32 (z4, z0, z1, 0),
  23                  z0_res = svqdmlalt_lane (z4, z0, z1, 0))
  24
  25 /*
  26 ** qdmlalt_lane_0_s32_tied3:
  27 **      mov     (z[0-9]+)\.d, z0\.d
  28 **      movprfx z0, z4
  29 **      sqdmlalt        z0\.s, z1\.h, \1\.h\[0\]
  30 **      ret
  31 */
  32 TEST_DUAL_Z_REV (qdmlalt_lane_0_s32_tied3, svint32_t, svint16_t,
  33                  z0_res = svqdmlalt_lane_s32 (z4, z1, z0, 0),
  34                  z0_res = svqdmlalt_lane (z4, z1, z0, 0))
  35
  36 /*
  37 ** qdmlalt_lane_0_s32_untied:
  38 **      movprfx z0, z1
  39 **      sqdmlalt        z0\.s, z4\.h, z5\.h\[0\]
  40 **      ret
  41 */
  42 TEST_DUAL_Z (qdmlalt_lane_0_s32_untied, svint32_t, svint16_t,
  43              z0 = svqdmlalt_lane_s32 (z1, z4, z5, 0),
  44              z0 = svqdmlalt_lane (z1, z4, z5, 0))
  45
  46 /*
  47 ** qdmlalt_lane_1_s32:
  48 **      sqdmlalt        z0\.s, z4\.h, z5\.h\[1\]
  49 **      ret
  50 */
  51 TEST_DUAL_Z (qdmlalt_lane_1_s32, svint32_t, svint16_t,
  52              z0 = svqdmlalt_lane_s32 (z0, z4, z5, 1),
  53              z0 = svqdmlalt_lane (z0, z4, z5, 1))
  54
  55 /*
  56 ** qdmlalt_lane_z8_s32:
  57 **      str     d8, \[sp, -16\]!
  58 **      mov     (z[0-7])\.d, z8\.d
  59 **      sqdmlalt        z0\.s, z1\.h, \1\.h\[1\]
  60 **      ldr     d8, \[sp\], 16
  61 **      ret
  62 */
  63 TEST_DUAL_LANE_REG (qdmlalt_lane_z8_s32, svint32_t, svint16_t, z8,
  64                     z0 = svqdmlalt_lane_s32 (z0, z1, z8, 1),
  65                     z0 = svqdmlalt_lane (z0, z1, z8, 1))
  66
  67 /*
  68 ** qdmlalt_lane_z16_s32:
  69 **      mov     (z[0-7])\.d, z16\.d
  70 **      sqdmlalt        z0\.s, z1\.h, \1\.h\[1\]
  71 **      ret
  72 */
  73 TEST_DUAL_LANE_REG (qdmlalt_lane_z16_s32, svint32_t, svint16_t, z16,
  74                     z0 = svqdmlalt_lane_s32 (z0, z1, z16, 1),
  75                     z0 = svqdmlalt_lane (z0, z1, z16, 1))