gcc/testsuite/gcc.target/aarch64/sve2/acle/asm/qrdmlsh_lane_s32.c

   1 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
   2
   3 #include "test_sve_acle.h"
   4
   5 /*
   6 ** qrdmlsh_lane_0_s32_tied1:
   7 **      sqrdmlsh        z0\.s, z1\.s, z2\.s\[0\]
   8 **      ret
   9 */
  10 TEST_UNIFORM_Z (qrdmlsh_lane_0_s32_tied1, svint32_t,
  11                 z0 = svqrdmlsh_lane_s32 (z0, z1, z2, 0),
  12                 z0 = svqrdmlsh_lane (z0, z1, z2, 0))
  13
  14 /*
  15 ** qrdmlsh_lane_0_s32_tied2:
  16 **      mov     (z[0-9]+)\.d, z0\.d
  17 **      movprfx z0, z1
  18 **      sqrdmlsh        z0\.s, \1\.s, z2\.s\[0\]
  19 **      ret
  20 */
  21 TEST_UNIFORM_Z (qrdmlsh_lane_0_s32_tied2, svint32_t,
  22                 z0 = svqrdmlsh_lane_s32 (z1, z0, z2, 0),
  23                 z0 = svqrdmlsh_lane (z1, z0, z2, 0))
  24
  25 /*
  26 ** qrdmlsh_lane_0_s32_tied3:
  27 **      mov     (z[0-9]+)\.d, z0\.d
  28 **      movprfx z0, z1
  29 **      sqrdmlsh        z0\.s, z2\.s, \1\.s\[0\]
  30 **      ret
  31 */
  32 TEST_UNIFORM_Z (qrdmlsh_lane_0_s32_tied3, svint32_t,
  33                 z0 = svqrdmlsh_lane_s32 (z1, z2, z0, 0),
  34                 z0 = svqrdmlsh_lane (z1, z2, z0, 0))
  35
  36 /*
  37 ** qrdmlsh_lane_0_s32_untied:
  38 **      movprfx z0, z1
  39 **      sqrdmlsh        z0\.s, z2\.s, z3\.s\[0\]
  40 **      ret
  41 */
  42 TEST_UNIFORM_Z (qrdmlsh_lane_0_s32_untied, svint32_t,
  43                 z0 = svqrdmlsh_lane_s32 (z1, z2, z3, 0),
  44                 z0 = svqrdmlsh_lane (z1, z2, z3, 0))
  45
  46 /*
  47 ** qrdmlsh_lane_1_s32:
  48 **      sqrdmlsh        z0\.s, z1\.s, z2\.s\[1\]
  49 **      ret
  50 */
  51 TEST_UNIFORM_Z (qrdmlsh_lane_1_s32, svint32_t,
  52                 z0 = svqrdmlsh_lane_s32 (z0, z1, z2, 1),
  53                 z0 = svqrdmlsh_lane (z0, z1, z2, 1))
  54
  55 /*
  56 ** qrdmlsh_lane_2_s32:
  57 **      sqrdmlsh        z0\.s, z1\.s, z2\.s\[2\]
  58 **      ret
  59 */
  60 TEST_UNIFORM_Z (qrdmlsh_lane_2_s32, svint32_t,
  61                 z0 = svqrdmlsh_lane_s32 (z0, z1, z2, 2),
  62                 z0 = svqrdmlsh_lane (z0, z1, z2, 2))
  63
  64 /*
  65 ** qrdmlsh_lane_3_s32:
  66 **      sqrdmlsh        z0\.s, z1\.s, z2\.s\[3\]
  67 **      ret
  68 */
  69 TEST_UNIFORM_Z (qrdmlsh_lane_3_s32, svint32_t,
  70                 z0 = svqrdmlsh_lane_s32 (z0, z1, z2, 3),
  71                 z0 = svqrdmlsh_lane (z0, z1, z2, 3))
  72
  73 /*
  74 ** qrdmlsh_lane_z8_s32:
  75 **      str     d8, \[sp, -16\]!
  76 **      mov     (z[0-7])\.d, z8\.d
  77 **      sqrdmlsh        z0\.s, z1\.s, \1\.s\[1\]
  78 **      ldr     d8, \[sp\], 16
  79 **      ret
  80 */
  81 TEST_DUAL_LANE_REG (qrdmlsh_lane_z8_s32, svint32_t, svint32_t, z8,
  82                     z0 = svqrdmlsh_lane_s32 (z0, z1, z8, 1),
  83                     z0 = svqrdmlsh_lane (z0, z1, z8, 1))
  84
  85 /*
  86 ** qrdmlsh_lane_z16_s32:
  87 **      mov     (z[0-7])\.d, z16\.d
  88 **      sqrdmlsh        z0\.s, z1\.s, \1\.s\[1\]
  89 **      ret
  90 */
  91 TEST_DUAL_LANE_REG (qrdmlsh_lane_z16_s32, svint32_t, svint32_t, z16,
  92                     z0 = svqrdmlsh_lane_s32 (z0, z1, z16, 1),
  93                     z0 = svqrdmlsh_lane (z0, z1, z16, 1))