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[AArch64] Add support for the SVE2 ACLE
[thirdparty/gcc.git] / gcc / testsuite / gcc.target / aarch64 / sve2 / acle / asm / raddhnb_s64.c
1 /* { dg-final { check-function-bodies "**" "" "-DCHECK_ASM" } } */
2
3 #include "test_sve_acle.h"
4
5 /*
6 ** raddhnb_s64_tied1:
7 ** raddhnb z0\.s, (z0\.d, z1\.d|z1\.d, z0\.d)
8 ** ret
9 */
10 TEST_TYPE_CHANGE_Z (raddhnb_s64_tied1, svint32_t, svint64_t,
11 z0_res = svraddhnb_s64 (z0, z1),
12 z0_res = svraddhnb (z0, z1))
13
14 /*
15 ** raddhnb_s64_tied2:
16 ** raddhnb z0\.s, (z0\.d, z1\.d|z1\.d, z0\.d)
17 ** ret
18 */
19 TEST_TYPE_CHANGE_Z (raddhnb_s64_tied2, svint32_t, svint64_t,
20 z0_res = svraddhnb_s64 (z1, z0),
21 z0_res = svraddhnb (z1, z0))
22
23 /*
24 ** raddhnb_s64_untied:
25 ** raddhnb z0\.s, (z1\.d, z2\.d|z2\.d, z1\.d)
26 ** ret
27 */
28 TEST_TYPE_CHANGE_Z (raddhnb_s64_untied, svint32_t, svint64_t,
29 z0_res = svraddhnb_s64 (z1, z2),
30 z0_res = svraddhnb (z1, z2))
31
32 /*
33 ** raddhnb_x0_s64_tied1:
34 ** mov (z[0-9]+\.d), x0
35 ** raddhnb z0\.s, (z0\.d, \1|\1, z0\.d)
36 ** ret
37 */
38 TEST_TYPE_CHANGE_ZX (raddhnb_x0_s64_tied1, svint32_t, svint64_t, int64_t,
39 z0_res = svraddhnb_n_s64 (z0, x0),
40 z0_res = svraddhnb (z0, x0))
41
42 /*
43 ** raddhnb_x0_s64_untied:
44 ** mov (z[0-9]+\.d), x0
45 ** raddhnb z0\.s, (z1\.d, \1|\1, z1\.d)
46 ** ret
47 */
48 TEST_TYPE_CHANGE_ZX (raddhnb_x0_s64_untied, svint32_t, svint64_t, int64_t,
49 z0_res = svraddhnb_n_s64 (z1, x0),
50 z0_res = svraddhnb (z1, x0))
51
52 /*
53 ** raddhnb_11_s64_tied1:
54 ** mov (z[0-9]+\.d), #11
55 ** raddhnb z0\.s, (z0\.d, \1|\1, z0\.d)
56 ** ret
57 */
58 TEST_TYPE_CHANGE_Z (raddhnb_11_s64_tied1, svint32_t, svint64_t,
59 z0_res = svraddhnb_n_s64 (z0, 11),
60 z0_res = svraddhnb (z0, 11))
61
62 /*
63 ** raddhnb_11_s64_untied:
64 ** mov (z[0-9]+\.d), #11
65 ** raddhnb z0\.s, (z1\.d, \1|\1, z1\.d)
66 ** ret
67 */
68 TEST_TYPE_CHANGE_Z (raddhnb_11_s64_untied, svint32_t, svint64_t,
69 z0_res = svraddhnb_n_s64 (z1, 11),
70 z0_res = svraddhnb (z1, 11))